arch/all-pc/hidds/pcipc/pci.h

   1 #ifndef _PCI_H
   2 #define _PCI_H
   3
   4 #include <exec/types.h>
   5 #include <exec/libraries.h>
   6 #include <exec/execbase.h>
   7 #include <exec/nodes.h>
   8 #include <exec/lists.h>
   9
  10 #include <dos/bptr.h>
  11
  12 #include <oop/oop.h>
  13
  14 #include <aros/arossupportbase.h>
  15 #include <exec/execbase.h>
  16
  17 #include <libraries/acpica.h>
  18
  19 #include LC_LIBDEFS_FILE
  20
  21 #ifdef __i386__
  22 /*
  23  * On i386 we can support very old Pentium-1 motherboards with PCI
  24  * configuration mechanism 2.
  25  * x86-64 is much more legacy-free...
  26  */
  27 #define LEGACY_SUPPORT
  28 #endif
  29
  30 struct pcipc_staticdata
  31 {
  32     OOP_AttrBase        hiddPCIDriverAB;
  33     OOP_AttrBase        hiddAB;
  34
  35     OOP_AttrBase        hidd_PCIDeviceAB;
  36
  37     OOP_Class           *driverClass;
  38
  39     /* Low-level sub-methods */
  40     ULONG               (*ReadConfigLong)(UBYTE bus, UBYTE dev, UBYTE sub, UWORD reg);
  41     void                (*WriteConfigLong)(UBYTE bus, UBYTE dev, UBYTE sub, UWORD reg, ULONG val);
  42
  43     /* ACPI related */
  44     struct Library      *pcipc_acpiBase;
  45     ACPI_TABLE_MCFG     *pcipc_acpiMcfgTbl;
  46
  47 };
  48
  49 struct pcibase
  50 {
  51     struct Library          LibNode;
  52     struct pcipc_staticdata   psd;
  53 };
  54
  55 #define BASE(lib) ((struct pcibase*)(lib))
  56 #define PSD(cl) (&((struct pcibase*)cl->UserData)->psd)
  57 #define _psd PSD(cl)
  58
  59 #undef ACPICABase
  60 #define ACPICABase (_psd->pcipc_acpiBase)
  61
  62 /* PCI configuration mechanism 1 registers */
  63 #define PCI_AddressPort 0x0cf8
  64 #define PCI_DataPort    0x0cfc
  65
  66 /*
  67  * PCI configuration mechanism 2 registers
  68  * This mechanism is obsolete long ago. But AROS runs on old hardware,
  69  * and we support this.
  70  */
  71 #define PCI_CSEPort     0x0cf8
  72 #define PCI_ForwardPort 0x0cfa
  73
  74 /*
  75  * PCI configuration mechanism selector register.
  76  * Supported by some transition-time chipsets, like Intel Neptune.
  77  */
  78 #define PCI_MechSelect  0x0cfb
  79
  80 #define PCICS_VENDOR    0x00
  81 #define PCICS_PRODUCT   0x02
  82 #define PCICS_SUBCLASS  0x0a
  83
  84 #define PCI_CLASS_BRIDGE_HOST   0x0600
  85 #define PCI_CLASS_DISPLAY_VGA   0x0300
  86
  87 #define PCI_VENDOR_INTEL        0x8086
  88 #define PCI_VENDOR_COMPAQ       0x0e11
  89
  90
  91 typedef union _pcicfg
  92 {
  93     ULONG   ul;
  94     UWORD   uw[2];
  95     UBYTE   ub[4];
  96 } pcicfg;
  97
  98 static inline UWORD ReadConfigWord(struct pcipc_staticdata *psd, UBYTE bus, UBYTE dev, UBYTE sub, UWORD reg)
  99 {
 100     pcicfg temp;
 101
 102     temp.ul = psd->ReadConfigLong(bus, dev, sub, reg);
 103     return temp.uw[(reg&2)>>1];
 104 }
 105
 106 ULONG ReadConfig1Long(UBYTE bus, UBYTE dev, UBYTE sub, UWORD reg);
 107 void WriteConfig1Long(UBYTE bus, UBYTE dev, UBYTE sub, UWORD reg, ULONG val);
 108
 109 #ifdef LEGACY_SUPPORT
 110
 111 void PCIPC_ProbeConfMech(struct pcipc_staticdata *psd);
 112
 113 #else
 114
 115 #define PCIPC_ProbeConfMech(x)
 116
 117 #endif
 118
 119 #endif /* _PCI_H */