arch/arm-raspi/include/asm/registers.h

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     These need refining if IO-base is moved to virtual memory, now they reflect the state of Arm physical address space
   6
   7 */
   8
   9 #ifndef REGISTERS_RASPI_H
  10 #define REGISTERS_RASPI_H
  11
  12 /* This stuff should really be in arm/bcm2835.h */
  13 #define VIRTIO_BASE         0x20000000                  // Peripheral base address
  14 #define GPIO_PADS           (VIRTIO_BASE + 0x100000)
  15 #define CLOCK_BASE          (VIRTIO_BASE + 0x101000)
  16 #define GPIO_BASE           (VIRTIO_BASE + 0x200000)
  17 #define UART0_BASE          (VIRTIO_BASE + 0x201000)
  18 #define SPI0_BASE           (VIRTIO_BASE + 0x204000)
  19 #define BSC0_BASE           (VIRTIO_BASE + 0x205000)
  20 #define GPIO_PWM            (VIRTIO_BASE + 0x20C000)
  21
  22 #define GPIO_PADS_0_27      0x002c
  23 #define GPIO_PADS_28_45     0x0030
  24 #define GPIO_PADS_46_53     0x0034
  25
  26 #define GPFSEL0             (GPIO_BASE + 0x0)           // GPIO Function Select 0
  27 #define GPFSEL1             (GPIO_BASE + 0x4)           // GPIO Function Select 1
  28 #define GPFSEL2             (GPIO_BASE + 0x8)           // GPIO Function Select 2
  29 #define GPFSEL3             (GPIO_BASE + 0xC)           // GPIO Function Select 3
  30 #define GPFSEL4             (GPIO_BASE + 0x10)          // GPIO Function Select 4
  31 #define GPFSEL5             (GPIO_BASE + 0x14)          // GPIO Function Select 5
  32 #define GPSET0              (GPIO_BASE + 0x1C)          // GPIO Pin Output Set 0
  33 #define GPSET1              (GPIO_BASE + 0x20)          // GPIO Pin Output Set 1
  34 #define GPCLR0              (GPIO_BASE + 0x28)          // GPIO Pin Output Clear 0
  35 #define GPCLR1              (GPIO_BASE + 0x2C)          // GPIO Pin Output Clear 1
  36 #define GPLEV0              (GPIO_BASE + 0x34)          // GPIO Pin Level 0
  37 #define GPLEV1              (GPIO_BASE + 0x38)          // GPIO Pin Level 1
  38 #define GPEDS0              (GPIO_BASE + 0x40)          // GPIO Pin Event Detect Status 0
  39 #define GPEDS1              (GPIO_BASE + 0x44)          // GPIO Pin Event Detect Status 1
  40 #define GPREN0              (GPIO_BASE + 0x4C)          // GPIO Pin Rising Edge Detect Enable 0
  41 #define GPREN1              (GPIO_BASE + 0x50)          // GPIO Pin Rising Edge Detect Enable 1
  42 #define GPFEN0              (GPIO_BASE + 0x58)          // GPIO Pin Falling Edge Detect Enable 0
  43 #define GPFEN1              (GPIO_BASE + 0x5C)          // GPIO Pin Falling Edge Detect Enable 1
  44 #define GPHEN0              (GPIO_BASE + 0x64)
  45 #define GPHEN1              (GPIO_BASE + 0x68)
  46 #define GPLEN0              (GPIO_BASE + 0x70)
  47 #define GPLEN1              (GPIO_BASE + 0x74)
  48 #define GPAREN0             (GPIO_BASE + 0x7c)
  49 #define GPAREN1             (GPIO_BASE + 0x80)
  50 #define GPAFEN0             (GPIO_BASE + 0x88)
  51 #define GPAFEN1             (GPIO_BASE + 0x8c)
  52 #define GPPUD               (GPIO_BASE + 0x94)
  53 #define GPPUDCLK0           (GPIO_BASE + 0x98)
  54 #define GPPUDCLK1           (GPIO_BASE + 0x9c)
  55
  56 #define UART_DR                 (0x00)
  57 #define UART_RSRECR             (0x04)
  58 #define UART_FR                 (0x18)
  59 #define UART_ILPR               (0x20)
  60 #define UART_IBRD               (0x24)
  61 #define UART_FBRD               (0x28)
  62 #define UART_LCRH               (0x2C)
  63 #define UART_CR                 (0x30)
  64 #define UART_IFLS               (0x34)
  65 #define UART_IMSC               (0x38)
  66 #define UART_RIS                (0x3C)
  67 #define UART_MIS                (0x40)
  68 #define UART_ICR                (0x44)
  69 #define UART_DMACR              (0x48)
  70 #define UART_ITCR               (0x80)
  71 #define UART_ITIP               (0x84)
  72 #define UART_ITOP               (0x88)
  73 #define UART_TDR                (0x8C)
  74
  75 #if (0)
  76 #define ONEMS                 (0xb0/4)
  77 #define UBIR                  (0xa4/4)
  78 #define UBMR                  (0xa8/4)
  79 #define UCR2                  (0x84/4)
  80 #endif
  81
  82 #define SPI0_CS             (0x00)
  83 #define SPI0_FIFO           (0x04)
  84 #define SPI0_CLK            (0x08)
  85 #define SPI0_DLEN           (0x0c)
  86 #define SPI0_LTOH           (0x10)
  87 #define SPI0_DC             (0x14)
  88
  89 #define AUX_IRQ             0x20215000  // Auxiliary Interrupt status
  90 #define AUX_ENABLES         0x20215004  // Auxiliary enables
  91 #define AUX_MU_IO_REG       0x20215040  // AUX_MU_IO_REG Mini Uart I/O Data
  92 #define AUX_MU_IER_REG      0x20215044  // Mini Uart Interrupt Enable
  93 #define AUX_MU_IIR_REG      0x20215048  // Mini Uart Interrupt Identify
  94 #define AUX_MU_LCR_REG      0x2021504C  // Mini Uart Line Control
  95 #define AUX_MU_MCR_REG      0x20215050  // Mini Uart Modem Control
  96 #define AUX_MU_LSR_REG      0x20215054  // Mini Uart Line Status
  97 #define AUX_MU_MSR_REG      0x20215058  // Mini Uart Modem Status
  98 #define AUX_MU_SCRATCH      0x2021505C  // Mini Uart Scratch
  99 #define AUX_MU_CNTL_REG     0x20215060  // Mini Uart Extra Control
 100 #define AUX_MU_STAT_REG     0x20215064  // Mini Uart Extra Status
 101 #define AUX_MU_BAUD_REG     0x20215068  // Mini Uart Baudrate
 102 #define AUX_SPI0_CNTL0_REG  0x20215080  // SPI 1 Control register 0
 103 #define AUX_SPI0_CNTL1_REG  0x20215084  // SPI 1 Control register 1
 104 #define AUX_SPI0_STAT_REG   0x20215088  // SPI 1 Status
 105 #define AUX_SPI0_IO_REG     0x20215090  // SPI 1 Data
 106 #define AUX_SPI0_PEEK_REG   0x20215094  // SPI 1 Peek
 107 #define AUX_SPI1_CNTL0_REG  0x202150C0  // SPI 2 Control register 0
 108 #define AUX_SPI1_CNTL1_REG  0x202150C4  // SPI 2 Control register 1
 109 #define AUX_SPI1_STAT_REG   0x202150C8  // SPI 2 Status
 110 #define AUX_SPI1_IO_REG     0x202150D0  // SPI 2 Data
 111 #define AUX_SPI1_PEEK_REG   0x202150D4  // SPI 2 Peek
 112
 113 #endif