arch/arm-raspi/include/hardware/pl011uart.h

   1 /*
   2     Copyright © 2013, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #ifndef PL011UART_H
   7 #define PL011UART_H
   8
   9 // TODO: implement/use primecell bus subsystem to attach to ip's
  10 #define PL011_0_BASE              (ARM_PERIIOBASE + 0x201000)
  11 #if (0)
  12 // Disabled on RasPi..
  13 #define PL011_1_BASE              (ARM_PERIIOBASE + 0x215000)
  14 #endif
  15 #define PRIMECELLID_PL011       0x011
  16
  17 #define PL011_DR                 (0x00)
  18 #define PL011_RSRECR             (0x04)
  19 #define PL011_FR                 (0x18)
  20 #define PL011_ILPR               (0x20)
  21 #define PL011_IBRD               (0x24)
  22 #define PL011_FBRD               (0x28)
  23 #define PL011_LCRH               (0x2C)
  24 #define PL011_CR                 (0x30)
  25 #define PL011_IFLS               (0x34)
  26 #define PL011_IMSC               (0x38)
  27 #define PL011_RIS                (0x3C)
  28 #define PL011_MIS                (0x40)
  29 #define PL011_ICR                (0x44)
  30 #define PL011_DMACR              (0x48)
  31 #define PL011_ITCR               (0x80)
  32 #define PL011_ITIP               (0x84)
  33 #define PL011_ITOP               (0x88)
  34 #define PL011_TDR                (0x8C)
  35
  36 #define PL011_FR_CTS             (1 << 0)
  37 #define PL011_FR_DSR             (1 << 1)
  38 #define PL011_FR_DCD             (1 << 2)
  39 #define PL011_FR_BUSY            (1 << 3)
  40 #define PL011_FR_RXFE            (1 << 4)
  41 #define PL011_FR_TXFF            (1 << 5)
  42 #define PL011_FR_RXFF            (1 << 6)
  43 #define PL011_FR_TXFE            (1 << 7)
  44
  45 #define PL011_LCRH_BRK           (1 << 0)
  46 #define PL011_LCRH_PEN           (1 << 1)
  47 #define PL011_LCRH_EPS           (1 << 2)
  48 #define PL011_LCRH_STP2          (1 << 3)
  49 #define PL011_LCRH_FEN           (1 << 4)
  50 #define PL011_LCRH_WLEN5         (0 << 5)
  51 #define PL011_LCRH_WLEN6         (1 << 5)
  52 #define PL011_LCRH_WLEN7         (2 << 5)
  53 #define PL011_LCRH_WLEN8         (3 << 5)
  54 #define PL011_LCRH_SPS           (1 << 7)
  55
  56 #define PL011_CR_UARTEN          (1 << 0)
  57 #define PL011_CR_SIREN           (1 << 1)
  58 #define PL011_CR_SIRLP           (1 << 2)
  59 #define PL011_CR_LBE             (1 << 7)
  60 #define PL011_CR_TXE             (1 << 8)
  61 #define PL011_CR_RXE             (1 << 9)
  62 #define PL011_CR_RTSEN           (1 << 14)
  63 #define PL011_CR_CTSEN           (1 << 15)
  64
  65 #define PL011_ICR_RIMIC          (1 << 0)
  66 #define PL011_ICR_CTSMIC         (1 << 1)
  67 #define PL011_ICR_DSRMIC         (1 << 2)
  68 #define PL011_ICR_DCDMIC         (1 << 3)
  69 #define PL011_ICR_RXIC           (1 << 4)
  70 #define PL011_ICR_TXIC           (1 << 5)
  71 #define PL011_ICR_RTIC           (1 << 6)
  72 #define PL011_ICR_FEIC           (1 << 7)
  73 #define PL011_ICR_PEIC           (1 << 8)
  74 #define PL011_ICR_BEIC           (1 << 9)
  75 #define PL011_ICR_OEIC           (1 << 10)
  76
  77 #endif /* PL011UART_H */