Synchronized with documentations/db/credits.
[AROS.git] / workbench / tools / SysExplorer / cpu_i386.c
blobdd099047f091632dff82de10ccb855442db44dce
1 #include <resources/processor.h>
2 #include <proto/processor.h>
4 #include <stdio.h>
5 #include <string.h>
7 #include "cpuspecific.h"
9 #ifdef __x86__
11 #define FLAGS_NUM 14
13 static const char *features[] =
15 "FPU",
16 "MMX",
17 "MMXExt",
18 "3DNow!",
19 "3DNowExt!",
20 "SSE",
21 "SSE2",
22 "SSE3",
23 "SSSE3",
24 "SSE4.1",
25 "SSE4.2",
26 "SSE4A",
27 "NoExecute",
28 "64Bit"
31 void PrintCPUSpecificInfo(char *buffer, LONG bufsize, ULONG i, APTR ProcessorBase)
33 LONG slen;
34 char *bufptr = buffer;
36 BOOL nothing = TRUE;
37 BOOL flags[FLAGS_NUM];
38 struct TagItem tags [FLAGS_NUM + 2] =
40 {GCIT_SelectedProcessor, i},
41 {GCIT_SupportsFPU , (IPTR)&flags[0 ]},
42 {GCIT_SupportsMMX , (IPTR)&flags[1 ]},
43 {GCIT_SupportsMMXEXT , (IPTR)&flags[2 ]},
44 {GCIT_Supports3DNOW , (IPTR)&flags[3 ]},
45 {GCIT_Supports3DNOWEXT , (IPTR)&flags[4 ]},
46 {GCIT_SupportsSSE , (IPTR)&flags[5 ]},
47 {GCIT_SupportsSSE2 , (IPTR)&flags[6 ]},
48 {GCIT_SupportsSSE3 , (IPTR)&flags[7 ]},
49 {GCIT_SupportsSSSE3 , (IPTR)&flags[8 ]},
50 {GCIT_SupportsSSE41 , (IPTR)&flags[9 ]},
51 {GCIT_SupportsSSE42 , (IPTR)&flags[10]},
52 {GCIT_SupportsSSE4A , (IPTR)&flags[11]},
53 {GCIT_SupportsNoExecutionBit, (IPTR)&flags[12]},
54 {GCIT_Supports64BitMode , (IPTR)&flags[13]},
55 {TAG_DONE , 0 }
58 GetCPUInfo(tags);
60 snprintf(bufptr, bufsize, "Features: ");
61 slen = strlen(bufptr);
62 bufptr += slen;
63 bufsize -= slen;
65 for (i = 0; bufsize > 1 && i < FLAGS_NUM; i++)
67 if (flags[i])
69 nothing = FALSE;
70 snprintf(bufptr, bufsize, "%s ", features[i]);
71 slen = strlen(bufptr);
72 bufptr += slen;
73 bufsize -= slen;
77 if (bufsize > 5)
79 if (nothing)
81 sprintf(bufptr, "None");
82 slen = strlen(bufptr);
83 bufptr += slen;
84 bufsize -= slen;
86 sprintf(bufptr, "\n");
90 #endif