compiler/include/hardware/uart.h

   1 /*
   2     Copyright © 1995-2011, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: IBM PC-compatible UART (16x50) specific definitions
   6     Lang: english
   7 */
   8
   9 #ifndef HARDWARE_UART_H
  10 #define HARDWARE_UART_H
  11
  12 #define UART_RX         0       /* In:  Receive buffer (DLAB=0) */
  13 #define UART_TX         0       /* Out: Transmit buffer (DLAB=0) */
  14 #define UART_DLL        0       /* Out: Divisor Latch Low (DLAB=1) */
  15 #define UART_DLM        1       /* Out: Divisor Latch High (DLAB=1) */
  16 #define UART_IER        1       /* Out: Interrupt Enable Register */
  17 #define UART_IIR        2       /* In:  Interrupt ID Register */
  18 #define UART_FCR        2       /* Out: FIFO Control Register */
  19 #define UART_EFR        2       /* I/O: Extended Features Register (DLAB=1, 16C660 only) */
  20 #define UART_LCR        3       /* Out: Line Control Register */
  21 #define UART_MCR        4       /* Out: Modem Control Register */
  22 #define UART_LSR        5       /* In:  Line Status Register */
  23 #define UART_MSR        6       /* In:  Modem Status Register */
  24 #define UART_SCR        7       /* I/O: Scratch Register */
  25
  26 /*
  27  * These are the definitions for the FIFO Control Register
  28  * (16650 only)
  29  */
  30 #define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
  31 #define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
  32 #define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
  33 #define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
  34 #define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
  35 #define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
  36 #define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
  37 #define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
  38 #define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
  39 /* 16650 redefinitions */
  40 #define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */
  41 #define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */
  42 #define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
  43 #define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */
  44 #define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */
  45 #define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */
  46 #define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
  47 #define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */
  48 /* TI 16750 definitions */
  49 #define UART_FCR7_64BYTE        0x20 /* Go into 64 byte mode */
  50
  51 /*
  52  * These are the definitions for the Line Control Register
  53  *
  54  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  55  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  56  */
  57 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  58 #define UART_LCR_SBC    0x40    /* Set break control */
  59 #define UART_LCR_SPAR   0x20    /* Stick parity (?) */
  60 #define UART_LCR_EPAR   0x10    /* Even parity select */
  61 #define UART_LCR_PARITY 0x08    /* Parity Enable */
  62 #define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
  63 #define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
  64 #define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
  65 #define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
  66 #define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
  67
  68 /*
  69  * These are the definitions for the Line Status Register
  70  */
  71 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  72 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  73 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  74 #define UART_LSR_FE     0x08    /* Frame error indicator */
  75 #define UART_LSR_PE     0x04    /* Parity error indicator */
  76 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  77 #define UART_LSR_DR     0x01    /* Receiver data ready */
  78
  79 /*
  80  * These are the definitions for the Interrupt Identification Register
  81  */
  82 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  83 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  84
  85 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  86 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  87 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  88 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  89
  90 /*
  91  * These are the definitions for the Interrupt Enable Register
  92  */
  93 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  94 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  95 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  96 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  97 /*
  98  * Sleep mode for ST16650 and TI16750.
  99  * Note that for 16650, EFR-bit 4 must be selected as well.
 100  */
 101 #define UART_IERX_SLEEP  0x10   /* Enable sleep mode */
 102
 103 /*
 104  * These are the definitions for the Modem Control Register
 105  */
 106 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
 107 #define UART_MCR_OUT2   0x08    /* Out2 complement */
 108 #define UART_MCR_OUT1   0x04    /* Out1 complement */
 109 #define UART_MCR_RTS    0x02    /* RTS complement */
 110 #define UART_MCR_DTR    0x01    /* DTR complement */
 111
 112 /*
 113  * These are the definitions for the Modem Status Register
 114  */
 115 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
 116 #define UART_MSR_RI     0x40    /* Ring Indicator */
 117 #define UART_MSR_DSR    0x20    /* Data Set Ready */
 118 #define UART_MSR_CTS    0x10    /* Clear to Send */
 119 #define UART_MSR_DDCD   0x08    /* Delta DCD */
 120 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
 121 #define UART_MSR_DDSR   0x02    /* Delta DSR */
 122 #define UART_MSR_DCTS   0x01    /* Delta CTS */
 123 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 124
 125 /*
 126  * These are the definitions for the Extended Features Register
 127  * (StarTech 16C660 only, when DLAB=1)
 128  */
 129 #define UART_EFR_CTS    0x80    /* CTS flow control */
 130 #define UART_EFR_RTS    0x40    /* RTS flow control */
 131 #define UART_EFR_SCD    0x20    /* Special character detect */
 132 #define UART_EFR_ECB    0x10    /* Enhanced control bit */
 133
 134 #endif