arch/all-pc/kernel/apic_ia32.h

   1 #ifndef APIC_IA32_H
   2 #define APIC_IA32_H
   3 /*
   4     Copyright © 1995-2017, The AROS Development Team. All rights reserved.
   5     $Id$
   6
   7     Desc: IA-32 APIC hardware definitions.
   8     Lang: english
   9 */
  10
  11 #include "i8259a.h"
  12
  13 // put the APIC IRQs after the cpu exceptions & pic IRQ's
  14 #define APIC_IRQ_MAX            256
  15 #define X86_CPU_EXCEPT_COUNT   32
  16 #define APIC_IRQ_BASE           (X86_CPU_EXCEPT_COUNT + I8259A_IRQCOUNT)
  17 #define APIC_LOCALIRQ_COUNT     10
  18 #define APIC_IRQ_COUNT          (APIC_IRQ_MAX - (INTB_KERNEL + APIC_IRQ_BASE + APIC_LOCALIRQ_COUNT))
  19 #define APIC_CPU_EXCEPT_COUNT   (APIC_IRQ_MAX - APIC_IRQ_COUNT)
  20
  21 // really vectors...
  22 #define APIC_IRQ_SYSCALL        0x80
  23 #define APIC_IRQ_IPI_START      0xF0
  24 #define APIC_IRQ_IPI_END        0xF8
  25 #define APIC_IRQ_ERROR          0xFE
  26 #define APIC_IRQ_HEARTBEAT      (APIC_IRQ_BASE + APIC_IRQ_COUNT - 1)
  27
  28 /* Local APIC base address register (MSR #27) */
  29 #define MSR_LAPIC_BASE 0x1B
  30
  31 #define APIC_BOOTSTRAP (1 << 8)
  32 #define APIC_ENABLE    (1 << 11)
  33
  34 /* APIC hardware registers */
  35
  36 #define APIC_ID          0x20
  37 #define APIC_VERSION     0x30
  38 #define APIC_TPR         0x80   /* Task Priority Register                       */
  39 #define APIC_APR         0x90   /* Arbitration Priority Register                */
  40 #define APIC_PPR         0xA0   /* Processor Priority Register                  */
  41 #define APIC_EOI         0xB0   /* End Of Interrupt Register                    */
  42 #define APIC_REMOTE_READ 0xC0
  43 #define APIC_LDR         0xD0   /* Logical Destination Register                 */
  44 #define APIC_DFR         0xE0   /* Destination Format Register                  */
  45 #define APIC_SVR         0xF0   /* Spurious Interrupt Vector Register           */
  46 #define APIC_ISR         0x100  /* In Service Register                          */
  47 #define APIC_TMR         0x180  /* Trigger Mode Register                        */
  48 #define APIC_IRR         0x200  /* Interrupt Request Register                   */
  49 #define APIC_ESR         0x280  /* Error Status Register                        */
  50 #define APIC_ICRL        0x300  /* Interrupt Command Register low part          */
  51 #define APIC_ICRH        0x310  /* Interrupt Command Register high part         */
  52 #define APIC_TIMER_VEC   0x320  /* Timer local vector table entry               */
  53 #define APIC_THERMAL_VEC 0x330  /* Thermal local vector table entry             */
  54 #define APIC_PCOUNT_VEC  0x340  /* Performance counter local vector table entry */
  55 #define APIC_LINT0_VEC   0x350  /* Local interrupt 0 vector table entry         */
  56 #define APIC_LINT1_VEC   0x360  /* Local interrupt 1 vector table entry         */
  57 #define APIC_ERROR_VEC   0x370  /* Error vector table entry                     */
  58 #define APIC_TIMER_ICR   0x380  /* Timer initial count                          */
  59 #define APIC_TIMER_CCR   0x390  /* Timer current count                          */
  60 #define APIC_TIMER_DIV   0x3E0  /* Timer divide configuration register          */
  61
  62 /* ID shift value */
  63 #define APIC_ID_SHIFT 24
  64
  65 /* Version register */
  66 #define APIC_VERSION_MASK 0x000000FF    /* The actual version number                         */
  67 #define APIC_LVT_MASK     0x00FF0000    /* Number of entries in local vector table minus one */
  68 #define APIC_LVT_SHIFT    16
  69 #define APIC_EAS          (1 << 31)     /* Whether this APIC has extended address space      */
  70
  71 /* Macros to help parsing version */
  72 #define APIC_INTEGRATED(ver) (ver & 0x000000F0)
  73 #define APIC_LVT(ver)        ((ver & APIC_LVT_MASK) >> APIC_LVT_SHIFT)
  74
  75 /* LDR shift value */
  76 #define LDR_ID_SHIFT 24
  77
  78 /* Destination format (interrupt model) */
  79 #define DFR_CLUSTER (0x0 << 28)
  80 #define DFR_FLAT    (0xF << 28)
  81
  82 #define SVR_VEC_MASK 0xFF
  83 #define SVR_ASE      (1 << 8)
  84 #define SVR_FCC      (1 << 9)
  85
  86 /* Error register */
  87 #define ERR_SAE (1 << 2) /* Sent accept error        */
  88 #define ERR_RAE (1 << 3) /* Receive accept error     */
  89 #define ERR_SIV (1 << 5) /* Sent illegal vector      */
  90 #define ERR_RIV (1 << 6) /* Received illegal vector  */
  91 #define ERR_IRA (1 << 7) /* Illegal register address */
  92
  93 /* ICRL register */
  94 #define ICR_VEC_MASK      0x000000FF    /* Vector number (request argument) mask        */
  95 #define ICR_DM_INIT       0x0500        /* INIT request (reset the CPU)                 */
  96 #define ICR_DM_STARTUP    0x0600        /* STARTUP request (run from specified address) */
  97 #define ICR_DS            0x1000        /* Delivery status flag                         */
  98 #define ICR_INT_LEVELTRIG 0x8000        /* Send level-triggered interrupt               */
  99 #define ICR_INT_ASSERT    0x4000        /* Assert (set) or deassert (reset)             */
 100
 101 /* Local vector table entry fields */
 102 #define LVT_VEC_MASK   0x0000FF         /* Vector no                            */
 103 #define LVT_MT_MASK    0x000700         /* Message type                         */
 104 #define LVT_MT_FIXED   0x000000
 105 #define LVT_MT_SMI     0x000200
 106 #define LVT_MT_NMI     0x000400
 107 #define LVT_MT_EXT     0x000700
 108 #define LVT_DS         0x001000         /* Delivery status bit                  */
 109 #define LVT_ACTIVE_LOW 0x002000         /* Polarity flag (1 = low active)       */
 110 #define LVT_RIR        0x004000         /* Remote IRR                           */
 111 #define LVT_TGM_LEVEL  0x008000         /* Level-trigger mode                   */
 112 #define LVT_MASK       0x010000         /* Mask bit                             */
 113 #define LVT_TMM_PERIOD 0x020000         /* Periodic timer mode                  */
 114
 115 /* Timer divisors */
 116 #define TIMER_DIV_1   0x0B
 117 #define TIMER_DIV_2   0x00
 118 #define TIMER_DIV_4   0x01
 119 #define TIMER_DIV_8   0x02
 120 #define TIMER_DIV_16  0x03
 121 #define TIMER_DIV_32  0x08
 122 #define TIMER_DIV_64  0x09
 123 #define TIMER_DIV_128 0x0A
 124
 125 /* Register access macro to make the code more readable */
 126 #define APIC_REG(base, reg) *((volatile ULONG *)(base + reg))
 127
 128 #endif /* !APIC_IA32_H */