Added empty bootstrap.c and its build target
[AROS.git] / workbench / tools / ShowConfig / cpu_i386.c
blob7a03e88d9df30f517423ad2cefe47fbaebc82b38
1 #include <resources/processor.h>
2 #include <proto/processor.h>
4 #include <stdio.h>
6 #include "cpuspecific.h"
8 #ifdef __x86__
10 #define FLAGS_NUM 14
12 static const char *features[] =
14 "FPU",
15 "MMX",
16 "MMXExt",
17 "3DNow!",
18 "3DNowExt!",
19 "SSE",
20 "SSE2",
21 "SSE3",
22 "SSSE3",
23 "SSE4.1",
24 "SSE4.2",
25 "SSE4A",
26 "NoExecute",
27 "64Bit"
30 void PrintCPUSpecificInfo(ULONG i, APTR ProcessorBase)
32 BOOL nothing = TRUE;
33 BOOL flags[FLAGS_NUM];
34 struct TagItem tags [FLAGS_NUM + 2] =
36 {GCIT_SelectedProcessor, i},
37 {GCIT_SupportsFPU , (IPTR)&flags[0 ]},
38 {GCIT_SupportsMMX , (IPTR)&flags[1 ]},
39 {GCIT_SupportsMMXEXT , (IPTR)&flags[2 ]},
40 {GCIT_Supports3DNOW , (IPTR)&flags[3 ]},
41 {GCIT_Supports3DNOWEXT , (IPTR)&flags[4 ]},
42 {GCIT_SupportsSSE , (IPTR)&flags[5 ]},
43 {GCIT_SupportsSSE2 , (IPTR)&flags[6 ]},
44 {GCIT_SupportsSSE3 , (IPTR)&flags[7 ]},
45 {GCIT_SupportsSSSE3 , (IPTR)&flags[8 ]},
46 {GCIT_SupportsSSE41 , (IPTR)&flags[9 ]},
47 {GCIT_SupportsSSE42 , (IPTR)&flags[10]},
48 {GCIT_SupportsSSE4A , (IPTR)&flags[11]},
49 {GCIT_SupportsNoExecutionBit, (IPTR)&flags[12]},
50 {GCIT_Supports64BitMode , (IPTR)&flags[13]},
51 {TAG_DONE , 0 }
54 GetCPUInfo(tags);
56 printf("\t\tFeatures: ");
58 for (i = 0; i < FLAGS_NUM; i++)
61 if (flags[i])
63 nothing = FALSE;
64 printf("%s ", features[i]);
68 if (nothing)
69 printf("None");
70 printf("\n");
73 #endif