set the lock the task is waiting on, and re-add spinning tasks when a lock is released
[AROS.git] / workbench / hidds / vmwaresvga / svga_reg.h
blob871352bf39f3d8922dc834f6875dbf9b4cc253c6
1 /* **********************************************************
2 * Copyright (C) 1998-2001 VMware, Inc.
3 * All Rights Reserved
4 * Id: svga_reg.h,v 1.9 2001/03/02 02:06:47 bhlim Exp $
5 * **********************************************************/
7 /*
8 * svga_reg.h --
10 * SVGA hardware definitions
13 #ifndef _SVGA_REG_H_
14 #define _SVGA_REG_H_
16 #include "svga_limits.h"
19 * Memory and port addresses and fundamental constants
22 #define SVGA_MAX_WIDTH 2360
23 #define SVGA_MAX_HEIGHT 1770
25 #define SVGA_MAX_BITS_PER_PIXEL 32
26 #if SVGA_MAX_WIDTH * SVGA_MAX_HEIGHT * SVGA_MAX_BITS_PER_PIXEL / 8 > \
27 SVGA_FB_MAX_SIZE
28 #error "Bad SVGA maximum sizes"
29 #endif
30 #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
31 #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
32 #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
34 #define SVGA_MAGIC 0x900000
35 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
37 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
38 #define SVGA_VERSION_2 2
39 #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
41 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
42 PALETTE_BASE has moved */
43 #define SVGA_VERSION_1 1
44 #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
46 /* Version 0 is the initial version */
47 #define SVGA_VERSION_0 0
48 #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
50 /* Invalid SVGA_ID_ */
51 #define SVGA_ID_INVALID 0xFFFFFFFF
53 /* More backwards compatibility, old location of color map: */
54 #define SVGA_OLD_PALETTE_BASE 17
56 /* Base and Offset gets us headed the right way for PCI Base Addr Registers */
57 #define SVGA_LEGACY_BASE_PORT 0x4560
58 #define SVGA_INDEX_PORT 0x0
59 #define SVGA_VALUE_PORT 0x1
60 #define SVGA_BIOS_PORT 0x2
61 #define SVGA_NUM_PORTS 0x3
63 /* This port is deprecated, but retained because of old drivers. */
64 #define SVGA_LEGACY_ACCEL_PORT 0x3
66 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
67 #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
68 #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
69 #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
70 #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
73 * Registers
76 enum {
77 SVGA_REG_ID = 0,
78 SVGA_REG_ENABLE = 1,
79 SVGA_REG_WIDTH = 2,
80 SVGA_REG_HEIGHT = 3,
81 SVGA_REG_MAX_WIDTH = 4,
82 SVGA_REG_MAX_HEIGHT = 5,
83 SVGA_REG_DEPTH = 6,
84 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
85 SVGA_REG_PSEUDOCOLOR = 8,
86 SVGA_REG_RED_MASK = 9,
87 SVGA_REG_GREEN_MASK = 10,
88 SVGA_REG_BLUE_MASK = 11,
89 SVGA_REG_BYTES_PER_LINE = 12,
90 SVGA_REG_FB_START = 13,
91 SVGA_REG_FB_OFFSET = 14,
92 SVGA_REG_VRAM_SIZE = 15,
93 SVGA_REG_FB_SIZE = 16,
95 /* ID 0 implementation only had the above registers, then the palette */
97 SVGA_REG_CAPABILITIES = 17,
98 SVGA_REG_MEM_START = 18, /* Memory for command FIFO and bitmaps */
99 SVGA_REG_MEM_SIZE = 19,
100 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
101 SVGA_REG_SYNC = 21, /* Write to force synchronization */
102 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
103 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
104 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
105 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
106 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
107 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
108 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
109 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
110 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
111 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
112 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
113 SVGA_REG_TOP = 33, /* Must be 1 more than the last register */
115 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
116 /* Next 768 (== 256*3) registers exist for colormap */
117 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
118 /* Base of scratch registers */
119 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
120 First 4 are reserved for VESA BIOS Extension; any remaining are for
121 the use of the current SVGA driver. */
126 * Capabilities
129 #define SVGA_CAP_NONE 0x00000
130 #define SVGA_CAP_RECT_FILL 0x00001
131 #define SVGA_CAP_RECT_COPY 0x00002
132 #define SVGA_CAP_RECT_PAT_FILL 0x00004
133 #define SVGA_CAP_LEGACY_OFFSCREEN 0x00008
134 #define SVGA_CAP_RASTER_OP 0x00010
135 #define SVGA_CAP_CURSOR 0x00020
136 #define SVGA_CAP_CURSOR_BYPASS 0x00040
137 #define SVGA_CAP_CURSOR_BYPASS_2 0x00080
138 #define SVGA_CAP_8BIT_EMULATION 0x00100
139 #define SVGA_CAP_ALPHA_CURSOR 0x00200
140 #define SVGA_CAP_GLYPH 0x00400
141 #define SVGA_CAP_GLYPH_CLIPPING 0x00800
142 #define SVGA_CAP_OFFSCREEN_1 0x01000
143 #define SVGA_CAP_ALPHA_BLEND 0x02000
144 #define SVGA_CAP_3D 0x04000
145 #define SVGA_CAP_EXTENDED_FIFO 0x08000
146 #define SVGA_CAP_MULTIMON 0x10000
147 #define SVGA_CAP_PITCHLOCK 0x20000
151 * Raster op codes (same encoding as X)
154 #define SVGA_ROP_CLEAR 0x00 /* 0 */
155 #define SVGA_ROP_AND 0x01 /* src AND dst */
156 #define SVGA_ROP_AND_REVERSE 0x02 /* src AND NOT dst */
157 #define SVGA_ROP_COPY 0x03 /* src */
158 #define SVGA_ROP_AND_INVERTED 0x04 /* NOT src AND dst */
159 #define SVGA_ROP_NOOP 0x05 /* dst */
160 #define SVGA_ROP_XOR 0x06 /* src XOR dst */
161 #define SVGA_ROP_OR 0x07 /* src OR dst */
162 #define SVGA_ROP_NOR 0x08 /* NOT src AND NOT dst */
163 #define SVGA_ROP_EQUIV 0x09 /* NOT src XOR dst */
164 #define SVGA_ROP_INVERT 0x0a /* NOT dst */
165 #define SVGA_ROP_OR_REVERSE 0x0b /* src OR NOT dst */
166 #define SVGA_ROP_COPY_INVERTED 0x0c /* NOT src */
167 #define SVGA_ROP_OR_INVERTED 0x0d /* NOT src OR dst */
168 #define SVGA_ROP_NAND 0x0e /* NOT src OR NOT dst */
169 #define SVGA_ROP_SET 0x0f /* 1 */
170 #define SVGA_ROP_UNSUPPORTED 0x10
172 #define SVGA_NUM_SUPPORTED_ROPS 16
175 * Memory area offsets (viewed as an array of 32-bit words)
179 * The distance from MIN to MAX must be at least 10K
182 #define SVGA_FIFO_MIN 0
183 #define SVGA_FIFO_MAX 1
184 #define SVGA_FIFO_NEXT_CMD 2
185 #define SVGA_FIFO_STOP 3
187 #define SVGA_FIFO_USER_DEFINED 4
190 * Drawing object ID's, in the range 0 to SVGA_MAX_ID
193 #define SVGA_MAX_ID 499
196 * Macros to compute variable length items (sizes in 32-bit words)
199 #define SVGA_BITMAP_SIZE(w,h) ((((w)+31) >> 5) * (h))
200 #define SVGA_BITMAP_SCANLINE_SIZE(w) (( (w)+31 ) >> 5)
201 #define SVGA_PIXMAP_SIZE(w,h,d) ((( ((w)*(d))+31 ) >> 5) * (h))
202 #define SVGA_PIXMAP_SCANLINE_SIZE(w,d) (( ((w)*(d))+31 ) >> 5)
203 #define SVGA_GLYPH_SIZE(w,h) ((((((w) + 7) >> 3) * (h)) + 3) >> 2)
204 #define SVGA_GLYPH_SCANLINE_SIZE(w) (((w) + 7) >> 3)
207 * Increment from one scanline to the next of a bitmap or pixmap
209 #define SVGA_BITMAP_INCREMENT(w) ((( (w)+31 ) >> 5) * sizeof (uint32))
210 #define SVGA_PIXMAP_INCREMENT(w,d) ((( ((w)*(d))+31 ) >> 5) * sizeof (uint32))
212 #define SVGA_COLOR_TRANSPARENT (~0)
215 * Commands in the command FIFO
218 #define SVGA_CMD_INVALID_CMD 0
219 /* FIFO layout:
220 <nothing> (well, undefined) */
222 #define SVGA_CMD_UPDATE 1
223 /* FIFO layout:
224 X, Y, Width, Height */
226 #define SVGA_CMD_RECT_FILL 2
227 /* FIFO layout:
228 Color, X, Y, Width, Height */
230 #define SVGA_CMD_RECT_COPY 3
231 /* FIFO layout:
232 Source X, Source Y, Dest X, Dest Y, Width, Height */
234 #define SVGA_CMD_DEFINE_BITMAP 4
235 /* FIFO layout:
236 Pixmap ID, Width, Height, <scanlines> */
238 #define SVGA_CMD_DEFINE_BITMAP_SCANLINE 5
239 /* FIFO layout:
240 Pixmap ID, Width, Height, Line #, scanline */
242 #define SVGA_CMD_DEFINE_PIXMAP 6
243 /* FIFO layout:
244 Pixmap ID, Width, Height, Depth, <scanlines> */
246 #define SVGA_CMD_DEFINE_PIXMAP_SCANLINE 7
247 /* FIFO layout:
248 Pixmap ID, Width, Height, Depth, Line #, scanline */
250 #define SVGA_CMD_RECT_BITMAP_FILL 8
251 /* FIFO layout:
252 Bitmap ID, X, Y, Width, Height, Foreground, Background */
254 #define SVGA_CMD_RECT_PIXMAP_FILL 9
255 /* FIFO layout:
256 Pixmap ID, X, Y, Width, Height */
258 #define SVGA_CMD_RECT_BITMAP_COPY 10
259 /* FIFO layout:
260 Bitmap ID, Source X, Source Y, Dest X, Dest Y,
261 Width, Height, Foreground, Background */
263 #define SVGA_CMD_RECT_PIXMAP_COPY 11
264 /* FIFO layout:
265 Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width, Height */
267 #define SVGA_CMD_FREE_OBJECT 12
268 /* FIFO layout:
269 Object (pixmap, bitmap, ...) ID */
271 #define SVGA_CMD_RECT_ROP_FILL 13
272 /* FIFO layout:
273 Color, X, Y, Width, Height, ROP */
275 #define SVGA_CMD_RECT_ROP_COPY 14
276 /* FIFO layout:
277 Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
279 #define SVGA_CMD_RECT_ROP_BITMAP_FILL 15
280 /* FIFO layout:
281 ID, X, Y, Width, Height, Foreground, Background, ROP */
283 #define SVGA_CMD_RECT_ROP_PIXMAP_FILL 16
284 /* FIFO layout:
285 ID, X, Y, Width, Height, ROP */
287 #define SVGA_CMD_RECT_ROP_BITMAP_COPY 17
288 /* FIFO layout:
289 ID, Source X, Source Y,
290 Dest X, Dest Y, Width, Height, Foreground, Background, ROP */
292 #define SVGA_CMD_RECT_ROP_PIXMAP_COPY 18
293 /* FIFO layout:
294 ID, Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
296 #define SVGA_CMD_DEFINE_CURSOR 19
297 /* FIFO layout:
298 ID, Hotspot X, Hotspot Y, Width, Height,
299 Depth for AND mask, Depth for XOR mask,
300 <scanlines for AND mask>, <scanlines for XOR mask> */
302 #define SVGA_CMD_DISPLAY_CURSOR 20
303 /* FIFO layout:
304 ID, On/Off (1 or 0) */
306 #define SVGA_CMD_MOVE_CURSOR 21
307 /* FIFO layout:
308 X, Y */
310 #define SVGA_CMD_DEFINE_ALPHA_CURSOR 22
311 /* FIFO layout:
312 ID, Hotspot X, Hotspot Y, Width, Height,
313 <scanlines> */
315 #define SVGA_CMD_DRAW_GLYPH 23
316 /* FIFO layout:
317 X, Y, W, H, FGCOLOR, <stencil buffer> */
319 #define SVGA_CMD_DRAW_GLYPH_CLIPPED 24
320 /* FIFO layout:
321 X, Y, W, H, FGCOLOR, BGCOLOR, <cliprect>, <stencil buffer>
322 Transparent color expands are done by setting BGCOLOR to ~0 */
324 #define SVGA_CMD_UPDATE_VERBOSE 25
325 /* FIFO layout:
326 X, Y, Width, Height, Reason */
328 #define SVGA_CMD_SURFACE_FILL 26
329 /* FIFO layout:
330 color, dstSurfaceOffset, x, y, w, h, rop */
332 #define SVGA_CMD_SURFACE_COPY 27
333 /* FIFO layout:
334 srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
335 destX, destY, w, h, rop */
337 #define SVGA_CMD_SURFACE_ALPHA_BLEND 28
338 /* FIFO layout:
339 srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
340 destX, destY, w, h, op (SVGA_BLENDOP*), flags (SVGA_BLENDFLAGS*),
341 param1, param2 */
343 #define SVGA_CMD_FRONT_ROP_FILL 29
344 /* FIFO layout:
345 Color, X, Y, Width, Height, ROP */
347 #define SVGA_CMD_FENCE 30
348 /* FIFO layout:
349 Fence value */
351 #define SVGA_CMD_MAX 31
353 #define SVGA_CMD_MAX_ARGS 64
355 #endif