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Added non-breaking space support
[AROS.git] / rom / devs / ahci / ahci.h
blob27b83c7aa8c7bc9437392507da51b6062e6cbb93
1 /*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
17 */
18
19 #if defined(__DragonFly__)
20 #include "ahci_dragonfly.h"
21 #elif defined(__AROS__)
22 #include "ahci_aros.h"
23 #else
24 #error "build for OS unknown"
25 #endif
26 #include "pmreg.h"
27 #include "atascsi.h"
28
29 /* change to AHCI_DEBUG for dmesg spam */
30 #define NO_AHCI_DEBUG
31
32 #ifdef AHCI_DEBUG
33 #define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \
34 while (0)
35 #define AHCI_D_TIMEOUT 0x00
36 #define AHCI_D_VERBOSE 0x01
37 #define AHCI_D_INTR 0x02
38 #define AHCI_D_XFER 0x08
39 static const int ahcidebug = 0xff;
40 #else
41 #define DPRINTF(m, f...)
42 #endif
43
44 #define AHCI_PCI_ATI_SB600_MAGIC 0x40
45 #define AHCI_PCI_ATI_SB600_LOCKED 0x01
46
47 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */
48 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
49 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
50 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
51 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
52 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
53 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
54 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
55 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
56 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching Supp */
57 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
58 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
59 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
60 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
61 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
62 #define AHCI_REG_CAP_ISS_G2 (0x2<<20) /* Gen 2 (3 Gbps) */
63 #define AHCI_REG_CAP_ISS_G3 (0x3<<20) /* Gen 3 (6 Gbps) */
64 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
65 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
66 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
67 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
68 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
69 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
70 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
71 #define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */
72 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
73 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
74 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
75 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
76 "\010CCCS" "\007EMS" "\006SXS"
77
78 #define AHCI_REG_GHC 0x004 /* Global HBA Control */
79 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
80 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
81 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
82 #define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */
83 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
84
85 #define AHCI_REG_IS 0x008 /* Interrupt Status */
86 #define AHCI_REG_PI 0x00c /* Ports Implemented */
87
88 #define AHCI_REG_VS 0x010 /* AHCI Version */
89 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
90 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
91 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
92 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
93 #define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */
94 #define AHCI_REG_VS_1_4 0x00010400 /* 1.4 */
95 #define AHCI_REG_VS_1_5 0x00010500 /* 1.5 (future...) */
96
97 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
98 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
99
100 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
101 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
102 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
103
104 #define AHCI_REG_CAP2 0x024 /* Host Capabilities Extended */
105 #define AHCI_REG_CAP2_BOH (1<<0) /* BIOS/OS Handoff */
106 #define AHCI_REG_CAP2_NVMP (1<<1) /* NVMHCI Present */
107 #define AHCI_REG_CAP2_APST (1<<2) /* A-Partial to Slumber Trans */
108 #define AHCI_FMT_CAP2 "\020" "\003BOH" "\002NVMP" "\001BOH"
109
110 #define AHCI_REG_BOHC 0x028 /* BIOS/OS Handoff Control and Status */
111 #define AHCI_REG_BOHC_BOS (1<<0) /* BIOS Owned Semaphore */
112 #define AHCI_REG_BOHC_OOS (1<<1) /* OS Owned Semaphore */
113 #define AHCI_REG_BOHC_SOOE (1<<2) /* SMI on OS Own chg enable */
114 #define AHCI_REG_BOHC_OOC (1<<3) /* OS Ownership Change */
115 #define AHCI_REG_BOHC_BB (1<<4) /* BIOS Busy */
116 #define AHCI_FMT_BOHC "\020" "\005BB" "\004OOC" "\003SOOE" \
117 "\002OOS" "\001BOS"
118
119 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
120 #define AHCI_PORT_SIZE 0x80
121
122 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
123 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
124 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */
125 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
126
127 #define AHCI_PREG_IS 0x10 /* Interrupt Status */
128 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
129 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
130 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
131 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
132 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
133 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
134 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
135 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
136 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
137 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
138 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
139 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
140 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
141 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
142 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
143 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
144 #define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */
145 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
146 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
147 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
148 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
149 "\002PSS" "\001DHRS"
150
151 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */
152 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
153 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
154 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
155 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
156 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
157 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
158 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
159 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
160 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
161 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
162 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
163 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
164 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
165 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
166 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
167 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
168 #define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */
169 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
170 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
171 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
172 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
173 "\002PSE" "\001DHRE"
174
175 /*
176 * NOTE: bits 22, 21, 20, 19, 18, 16, 15, 14, 13, 12:08, 07:05 are always
177 * read-only. Other bits may be read-only when the related feature
178 * is not supported by the HBA.
179 */
180 #define AHCI_PREG_CMD 0x18 /* Command and Status */
181 #define AHCI_PREG_CMD_ST (1<<0) /* Start */
182 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
183 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
184 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
185 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
186 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
187 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
188 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
189 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
190 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
191 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
192 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
193 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
194 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
195 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
196 #define AHCI_PREG_CMD_FBSCP (1<<22) /* FIS-based sw capable port */
197 #define AHCI_PREG_CMD_APSTE (1<<23) /* Auto Partial to Slumber */
198 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
199 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
200 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
201 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
202 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
203 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
204 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
205 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
206 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000
207 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
208 "\031ATAPI" "\030APSTE" "\027FBSCP" \
209 "\026ESP" "\025CPD" "\024MPSP" \
210 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \
211 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \
212 "\003POD" "\002SUD" "\001ST"
213
214 #define AHCI_PREG_TFD 0x20 /* Task File Data*/
215 #define AHCI_PREG_TFD_STS 0xff
216 #define AHCI_PREG_TFD_STS_ERR (1<<0)
217 #define AHCI_PREG_TFD_STS_DRQ (1<<3)
218 #define AHCI_PREG_TFD_STS_BSY (1<<7)
219 #define AHCI_PREG_TFD_ERR 0xff00
220
221 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
222 #define AHCI_PREG_SIG 0x24 /* Signature */
223
224 #define AHCI_PREG_SSTS 0x28 /* SATA Status */
225 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
226 #define AHCI_PREG_SSTS_DET_NONE 0x0
227 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1
228 #define AHCI_PREG_SSTS_DET_DEV 0x3
229 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
230 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
231 #define AHCI_PREG_SSTS_SPD_NONE 0x00
232 #define AHCI_PREG_SSTS_SPD_GEN1 0x10
233 #define AHCI_PREG_SSTS_SPD_GEN2 0x20
234 #define AHCI_PREG_SSTS_SPD_GEN3 0x30
235 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
236 #define AHCI_PREG_SSTS_IPM_NONE 0x000
237 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
238 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
239 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
240
241 #define AHCI_PREG_SCTL 0x2c /* SATA Control */
242 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
243 #define AHCI_PREG_SCTL_DET_NONE 0x0
244 #define AHCI_PREG_SCTL_DET_INIT 0x1
245 #define AHCI_PREG_SCTL_DET_DISABLE 0x4
246 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
247 #define AHCI_PREG_SCTL_SPD_ANY 0x00
248 #define AHCI_PREG_SCTL_SPD_GEN1 0x10
249 #define AHCI_PREG_SCTL_SPD_GEN2 0x20
250 #define AHCI_PREG_SCTL_SPD_GEN3 0x30
251 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
252 #define AHCI_PREG_SCTL_IPM_NONE 0x000
253 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
254 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
255 #define AHCI_PREG_SCTL_IPM_DISABLED 0x300
256 #define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */
257 #define AHCI_PREG_SCTL_SPM_NONE 0x0000
258 #define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000
259 #define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000
260 #define AHCI_PREG_SCTL_SPM_DISABLED 0x3000
261 #define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */
262 #define AHCI_PREG_SCTL_PMP_SHIFT 16
263
264 #define AHCI_PREG_SERR 0x30 /* SATA Error */
265 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
266 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
267 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
268 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
269 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
270 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
271 #define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */
272 #define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */
273 #define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */
274 #define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */
275 #define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */
276 #define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */
277 #define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */
278 #define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */
279 #define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */
280 #define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */
281 #define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */
282
283 #define AHCI_PFMT_SERR "\020" \
284 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \
285 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \
286 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \
287 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \
288 "\002ERR.M" "\001ERR.I"
289
290 #define AHCI_PREG_SACT 0x34 /* SATA Active */
291 #define AHCI_PREG_CI 0x38 /* Command Issue */
292 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
293 #define AHCI_PREG_SNTF 0x3c /* SNotification */
294
295 /*
296 * EN - Enable FIS based switch, can only be changed when ST is clear
297 *
298 * DEC - Device Error Clear, state machine. Set to 1 by software only
299 * for the EN+SDE case, then poll until hardware sets it back to 0.
300 * Writing 0 has no effect.
301 *
302 * SDE - Set by hardware indicating a single device error occurred. If
303 * not set and an error occurred then the error was whole-port.
304 *
305 * DEV - Set by software to the PM target of the next command to issue
306 * via the PREG_CI registers. Software should not issue multiple
307 * commands covering different targets in a single write. This
308 * basically causes writes to PREG_CI to index within the hardware.
309 *
310 * ADO - (read only) Indicate how many concurrent devices commands may
311 * be issued to at once. Degredation may occur if commands are
312 * issued to more devices but the case is allowed.
313 *
314 * DWE - (read only) Only valid on SDE errors. Hardware indicates which
315 * PM target generated the error in this field.
316 *
317 */
318 #define AHCI_PREG_FBS 0x40 /* FIS-Based Switching Control */
319 #define AHCI_PREG_FBS_EN (1<<0) /* FIS-Based switching enable */
320 #define AHCI_PREG_FBS_DEC (1<<1) /* Device Error Clear */
321 #define AHCI_PREG_FBS_SDE (1<<2) /* Single-device Error */
322 #define AHCI_PREG_FBS_DEV 0x00000F00 /* Device to Issue mask */
323 #define AHCI_PREG_FBS_ADO 0x0000F000 /* Active Dev Optimize */
324 #define AHCI_PREG_FBS_DWE 0x000F0000 /* Device With Error */
325 #define AHCI_PREG_FBS_DEV_SHIFT 8
326 #define AHCI_PREG_FBS_ADO_SHIFT 12
327 #define AHCI_PREG_FBS_DWE_SHIFT 16
328
329 /*
330 * AHCI mapped structures
331 */
332 struct ahci_cmd_hdr {
333 u_int16_t flags;
334 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
335 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
336 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
337 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
338 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
339 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
340 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
341 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
342 #define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12
343 u_int16_t prdtl; /* sgl len */
344
345 u_int32_t prdbc; /* transferred byte count */
346
347 u_int32_t ctba_lo;
348 u_int32_t ctba_hi;
349
350 u_int32_t reserved[4];
351 } __packed;
352
353 struct ahci_rfis {
354 u_int8_t dsfis[28];
355 u_int8_t reserved1[4];
356 u_int8_t psfis[24];
357 u_int8_t reserved2[8];
358 u_int8_t rfis[24];
359 u_int8_t reserved3[4];
360 u_int8_t sdbfis[4];
361 u_int8_t ufis[64];
362 u_int8_t reserved4[96];
363 } __packed;
364
365 struct ahci_prdt {
366 u_int32_t dba_lo;
367 u_int32_t dba_hi;
368 u_int32_t reserved;
369 u_int32_t flags;
370 #define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */
371 } __packed;
372
373 /*
374 * The base command table structure is 128 bytes. Each prdt is 16 bytes.
375 * We need to accomodate a 2MB maximum I/O transfer size, which is at least
376 * 512 entries, plus one for page slop.
377 *
378 * Making the ahci_cmd_table 16384 bytes (a reasonable power of 2)
379 * thus requires MAX_PRDT to be set to 1016.
380 */
381 #define AHCI_MAX_PRDT 1016
382 #define AHCI_MAX_PMPORTS 16
383
384 #define AHCI_MAXPHYS (2 * 1024 * 1024) /* 2MB */
385 #if AHCI_MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT
386 #error "AHCI_MAX_PRDT is not big enough"
387 #endif
388
389 struct ahci_cmd_table {
390 u_int8_t cfis[64]; /* Command FIS */
391 u_int8_t acmd[16]; /* ATAPI Command */
392 u_int8_t reserved[48];
393
394 struct ahci_prdt prdt[AHCI_MAX_PRDT];
395 } __packed;
396
397 #define AHCI_MAX_PORTS 32
398
399 struct ahci_dmamem {
400 bus_dma_tag_t adm_tag;
401 bus_dmamap_t adm_map;
402 bus_dma_segment_t adm_seg;
403 bus_addr_t adm_busaddr;
404 caddr_t adm_kva;
405 };
406 #define AHCI_DMA_MAP(_adm) ((_adm)->adm_map)
407 #define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr)
408 #define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva)
409
410 struct ahci_softc;
411 struct ahci_port;
412 struct ahci_device;
413
414 struct ahci_ccb {
415 /* ATA xfer associated with this CCB. Must be 1st struct member. */
416 struct ata_xfer ccb_xa;
417 struct callout ccb_timeout;
418
419 int ccb_slot;
420 struct ahci_port *ccb_port;
421
422 bus_dmamap_t ccb_dmamap;
423 struct ahci_cmd_hdr *ccb_cmd_hdr;
424 struct ahci_cmd_table *ccb_cmd_table;
425
426 void (*ccb_done)(struct ahci_ccb *);
427
428 TAILQ_ENTRY(ahci_ccb) ccb_entry;
429 };
430
431 struct ahci_port {
432 struct ahci_softc *ap_sc;
433 bus_space_handle_t ap_ioh;
434
435 int ap_num;
436 int ap_pmcount;
437 int ap_flags;
438 #define AP_F_BUS_REGISTERED 0x0001
439 #define AP_F_CAM_ATTACHED 0x0002
440 #define AP_F_IN_RESET 0x0004
441 #define AP_F_SCAN_RUNNING 0x0008
442 #define AP_F_SCAN_REQUESTED 0x0010
443 #define AP_F_SCAN_COMPLETED 0x0020
444 #define AP_F_IGNORE_IFS 0x0040
445 #define AP_F_IFS_IGNORED 0x0080
446 #define AP_F_UNUSED_0100 0x0100
447 #define AP_F_EXCLUSIVE_ACCESS 0x0200
448 #define AP_F_ERR_CCB_RESERVED 0x0400
449 #define AP_F_HARSH_REINIT 0x0800
450 int ap_signal; /* os per-port thread sig */
451 thread_t ap_thread; /* os per-port thread */
452 struct lock ap_lock; /* os per-port lock */
453 struct lock ap_sim_lock; /* cam sim lock */
454 struct lock ap_sig_lock; /* signal thread */
455 #define AP_SIGF_INIT 0x0001
456 #define AP_SIGF_TIMEOUT 0x0002
457 #define AP_SIGF_PORTINT 0x0004
458 #define AP_SIGF_THREAD_SYNC 0x0008
459 #define AP_SIGF_STOP 0x8000
460 struct cam_sim *ap_sim;
461
462 struct ahci_rfis *ap_rfis;
463 struct ahci_dmamem *ap_dmamem_rfis;
464
465 struct ahci_dmamem *ap_dmamem_cmd_list;
466 struct ahci_dmamem *ap_dmamem_cmd_table;
467
468 u_int32_t ap_active; /* active CI command bmask */
469 u_int32_t ap_active_cnt; /* active CI command count */
470 u_int32_t ap_sactive; /* active SACT command bmask */
471 u_int32_t ap_expired; /* deferred expired bmask */
472 u_int32_t ap_intmask; /* interrupts we care about */
473 struct ahci_ccb *ap_ccbs;
474 struct ahci_ccb *ap_err_ccb; /* always CCB SLOT 1 */
475 int ap_run_flags; /* used to check excl mode */
476
477 TAILQ_HEAD(, ahci_ccb) ap_ccb_free;
478 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending;
479 struct lock ap_ccb_lock;
480
481 int ap_type; /* ATA_PORT_T_xxx */
482 int ap_probe; /* ATA_PROBE_xxx */
483 struct ata_port *ap_ata[AHCI_MAX_PMPORTS];
484
485 u_int32_t ap_state;
486 #define AP_S_NORMAL 0
487 #define AP_S_FATAL_ERROR 1
488
489 /* For error recovery. */
490 u_int32_t ap_err_saved_sactive;
491 u_int32_t ap_err_saved_active;
492 u_int32_t ap_err_saved_active_cnt;
493
494 u_int8_t *ap_err_scratch;
495
496 int link_pwr_mgmt;
497
498 struct sysctl_ctx_list sysctl_ctx;
499 struct sysctl_oid *sysctl_tree;
500
501 char ap_name[16];
502 };
503
504 #define PORTNAME(_ap) ((_ap)->ap_name)
505 #define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name)
506
507 struct ahci_softc {
508 device_t sc_dev;
509 const struct ahci_device *sc_ad; /* special casing */
510
511 struct resource *sc_irq; /* bus resources */
512 struct resource *sc_regs; /* bus resources */
513 bus_space_tag_t sc_iot; /* split from sc_regs */
514 bus_space_handle_t sc_ioh; /* split from sc_regs */
515
516 int sc_rid_irq; /* saved bus RIDs */
517 int sc_rid_regs;
518 u_int32_t sc_cap; /* capabilities */
519 u_int32_t sc_cap2; /* capabilities */
520 u_int32_t sc_vers; /* AHCI version */
521 int sc_numports;
522 u_int32_t sc_portmask;
523
524 void *sc_irq_handle; /* installed irq vector */
525
526 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */
527 bus_dma_tag_t sc_tag_cmdh;
528 bus_dma_tag_t sc_tag_cmdt;
529 bus_dma_tag_t sc_tag_data;
530
531 int sc_flags;
532 #define AHCI_F_NO_NCQ 0x00000001
533 #define AHCI_F_IGN_FR 0x00000002
534 #define AHCI_F_INT_GOOD 0x00000004
535 #define AHCI_F_FORCE_FBSS 0x00000008
536 #define AHCI_F_NO_PM 0x00000010
537
538 u_int sc_ncmds;
539
540 struct ahci_port *sc_ports[AHCI_MAX_PORTS];
541
542 #ifdef AHCI_COALESCE
543 u_int32_t sc_ccc_mask;
544 u_int32_t sc_ccc_ports;
545 u_int32_t sc_ccc_ports_cur;
546 #endif
547
548 struct sysctl_ctx_list sysctl_ctx;
549 struct sysctl_oid *sysctl_tree;
550 };
551 #define DEVNAME(_s) "ahci.device"
552
553 struct ahci_device {
554 pci_vendor_id_t ad_vendor;
555 pci_product_id_t ad_product;
556 int (*ad_attach)(device_t dev);
557 int (*ad_detach)(device_t dev);
558 char *name;
559 };
560
561 /* Wait for all bits in _b to be cleared */
562 #define ahci_pwait_clr(_ap, _r, _b) \
563 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0)
564 #define ahci_pwait_clr_to(_ap, _to, _r, _b) \
565 ahci_pwait_eq((_ap), _to, (_r), (_b), 0)
566
567 /* Wait for all bits in _b to be set */
568 #define ahci_pwait_set(_ap, _r, _b) \
569 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b))
570 #define ahci_pwait_set_to(_ap, _to, _r, _b) \
571 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b))
572
573 #define AHCI_PWAIT_TIMEOUT 1000
574
575 const struct ahci_device *ahci_lookup_device(device_t dev);
576 int ahci_init(struct ahci_softc *);
577 int ahci_port_init(struct ahci_port *ap);
578 int ahci_port_alloc(struct ahci_softc *, u_int);
579 void ahci_port_state_machine(struct ahci_port *ap, int initial);
580 void ahci_port_free(struct ahci_softc *, u_int);
581 int ahci_port_reset(struct ahci_port *, struct ata_port *at, int);
582 void ahci_port_link_pwr_mgmt(struct ahci_port *, int link_pwr_mgmt);
583 int ahci_port_link_pwr_state(struct ahci_port *);
584
585 u_int32_t ahci_read(struct ahci_softc *, bus_size_t);
586 void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t);
587 int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t);
588 u_int32_t ahci_pread(struct ahci_port *, bus_size_t);
589 void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t);
590 int ahci_pwait_eq(struct ahci_port *, int, bus_size_t,
591 u_int32_t, u_int32_t);
592 void ahci_intr(void *);
593 void ahci_port_intr(struct ahci_port *ap, int blockable);
594
595 int ahci_port_start(struct ahci_port *ap);
596 int ahci_port_stop(struct ahci_port *ap, int stop_fis_rx);
597 int ahci_port_clo(struct ahci_port *ap);
598 void ahci_flush_tfd(struct ahci_port *ap);
599 int ahci_set_feature(struct ahci_port *ap, struct ata_port *atx,
600 int feature, int enable);
601
602 int ahci_cam_attach(struct ahci_port *ap);
603 void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found);
604 void ahci_cam_detach(struct ahci_port *ap);
605 int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at);
606
607 struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at);
608 void ahci_ata_put_xfer(struct ata_xfer *xa);
609 int ahci_ata_cmd(struct ata_xfer *xa);
610
611 int ahci_pm_port_probe(struct ahci_port *ap, int);
612 int ahci_pm_port_init(struct ahci_port *ap, struct ata_port *at);
613 int ahci_pm_identify(struct ahci_port *ap);
614 int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard);
615 int ahci_pm_softreset(struct ahci_port *ap, int target);
616 int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap);
617 int ahci_pm_read(struct ahci_port *ap, int target,
618 int which, u_int32_t *res);
619 int ahci_pm_write(struct ahci_port *ap, int target,
620 int which, u_int32_t data);
621 void ahci_pm_check_good(struct ahci_port *ap, int target);
622 void ahci_ata_cmd_timeout(struct ahci_ccb *ccb);
623 void ahci_quick_timeout(struct ahci_ccb *ccb);
624 struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap);
625 void ahci_put_ccb(struct ahci_ccb *ccb);
626 struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *);
627 void ahci_put_err_ccb(struct ahci_ccb *);
628 int ahci_poll(struct ahci_ccb *ccb, int timeout,
629 void (*timeout_fn)(struct ahci_ccb *));
630
631 int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at);
632 void ahci_port_thread_core(struct ahci_port *ap, int mask);
633
634 void ahci_os_sleep(int ms);
635 void ahci_os_hardsleep(int us);
636 int ahci_os_softsleep(void);
637 void ahci_os_start_port(struct ahci_port *ap);
638 void ahci_os_stop_port(struct ahci_port *ap);
639 void ahci_os_signal_port_thread(struct ahci_port *ap, int mask);
640 void ahci_os_lock_port(struct ahci_port *ap);
641 int ahci_os_lock_port_nb(struct ahci_port *ap);
642 void ahci_os_unlock_port(struct ahci_port *ap);
643
644 extern u_int32_t AhciForceGen;
645 extern u_int32_t AhciNoFeatures;
646
647 enum {AHCI_LINK_PWR_MGMT_NONE, AHCI_LINK_PWR_MGMT_MEDIUM,
648 AHCI_LINK_PWR_MGMT_AGGR};
Mirror of AROS' svn.