rom/hidds/hidd.pci/pci.h

   1 #ifndef _PCI_H
   2 #define _PCI_H
   3
   4 /*
   5     Copyright © 2004-2011, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8
   9 #include <exec/types.h>
  10 #include <exec/libraries.h>
  11 #include <exec/execbase.h>
  12 #include <exec/nodes.h>
  13 #include <exec/lists.h>
  14 #include <exec/semaphores.h>
  15 #include <dos/bptr.h>
  16
  17 #include <aros/libcall.h>
  18 #include <aros/asmcall.h>
  19
  20 #include <oop/oop.h>
  21
  22 #include <exec/execbase.h>
  23
  24 #include LC_LIBDEFS_FILE
  25
  26 /* Private data and structures unavailable outside the pci base classes */
  27
  28 struct DriverNode {
  29     struct Node         node;
  30     OOP_Class           *driverClass;   /* Driver class */
  31     OOP_Object          *driverObject;  /* Driver object */
  32     ULONG               highBus;
  33     struct List         devices;        /* List of defices behind this node */
  34 };
  35
  36 struct DrvInstData {
  37     BOOL DirectBus;
  38 };
  39
  40 struct PciDevice {
  41     struct MinNode      node;
  42     OOP_Object          *device;
  43 };
  44
  45 typedef struct DeviceData {
  46     OOP_Object          *driver;
  47     UBYTE               bus,dev,sub;
  48     UBYTE               isBridge;
  49     UBYTE               subbus;
  50     UWORD               VendorID;
  51     UWORD               ProductID;
  52     UBYTE               RevisionID;
  53     UBYTE               Interface;
  54     UBYTE               SubClass;
  55     UBYTE               Class;
  56     UWORD               SubsysVID;
  57     UWORD               SubsystemID;
  58     UBYTE               INTLine;
  59     UBYTE               IRQLine;
  60     UBYTE               HeaderType;
  61     struct {
  62         IPTR            addr;
  63         IPTR            size;
  64     } BaseReg[6];
  65     ULONG               RomBase;
  66     ULONG               RomSize;
  67
  68     STRPTR              strClass;
  69     STRPTR              strSubClass;
  70     STRPTR              strInterface;
  71 } tDeviceData;
  72
  73 struct pci_staticdata {
  74     struct SignalSemaphore driver_lock;
  75     struct List         drivers;
  76
  77     APTR                MemPool;
  78
  79     OOP_AttrBase        hiddAB;
  80     OOP_AttrBase        hiddPCIAB;
  81     OOP_AttrBase        hiddPCIDriverAB;
  82     OOP_AttrBase        hiddPCIBusAB;
  83     OOP_AttrBase        hiddPCIDeviceAB;
  84
  85     OOP_Class           *pciClass;
  86     OOP_Class           *pciDeviceClass;
  87     OOP_Class           *pciDriverClass;
  88
  89     ULONG               users;
  90
  91     /* Most commonly used methods have already the mID's stored here */
  92     OOP_MethodID        mid_RB;
  93     OOP_MethodID        mid_RW;
  94     OOP_MethodID        mid_RL;
  95     OOP_MethodID        mid_WB;
  96     OOP_MethodID        mid_WW;
  97     OOP_MethodID        mid_WL;
  98 };
  99
 100 struct pcibase {
 101     struct Library              LibNode;
 102     APTR                        MemPool;
 103     struct pci_staticdata       psd;
 104 };
 105
 106 OOP_Class *init_pcideviceclass(struct pci_staticdata *);
 107 void free_pcideviceclass(struct pci_staticdata *, OOP_Class *cl);
 108
 109 #define BASE(lib) ((struct pcibase*)(lib))
 110
 111 #define PSD(cl) (&BASE(cl->UserData)->psd)
 112
 113 /* PCI Configspace offsets */
 114 #define PCICS_VENDOR        0x00
 115 #define PCICS_PRODUCT       0x02
 116 #define PCICS_COMMAND       0x04
 117 #define PCICS_STATUS        0x06
 118 #define PCICS_REVISION      0x08
 119 #define PCICS_PROGIF        0x09
 120 #define PCICS_SUBCLASS      0x0a
 121 #define PCICS_CLASS         0x0b
 122 #define PCICS_CACHELS       0x0c
 123 #define PCICS_LATENCY       0x0d
 124 #define PCICS_HEADERTYPE    0x0e
 125 #define PCICS_BIST          0x0f
 126 #define PCICS_BAR0          0x10
 127 #define PCICS_BAR1          0x14
 128 #define PCICS_BAR2          0x18
 129 #define PCICS_BAR3          0x1c
 130 #define PCICS_BAR4          0x20
 131 #define PCICS_BAR5          0x24
 132 #define PCICS_CARDBUS_CIS   0x28
 133 #define PCICS_SUBVENDOR     0x2c
 134 #define PCICS_SUBSYSTEM     0x2e
 135 #define PCICS_EXPROM_BASE   0x30
 136 #define PCICS_CAP_PTR       0x34
 137 #define PCICS_INT_LINE      0x3c
 138 #define PCICS_INT_PIN       0x3d
 139 #define PCICS_MIN_GNT       0x3e
 140 #define PCICS_MAX_LAT       0x3f
 141
 142 /* PCI Headertypes */
 143 #define PCIHT_MASK          0x7f
 144 #define PCIHT_MULTIFUNC     0x80
 145
 146 #define PCIHT_NORMAL        0x00
 147 #define PCIHT_BRIDGE        0x01
 148 #define PCIHT_CARDBUS       0x02
 149
 150 /* PCI Command register bits */
 151 #define PCICMB_IODECODE     0
 152 #define PCICMB_MEMDECODE    1
 153 #define PCICMB_BUSMASTER    2
 154 #define PCICMB_SPECIAL      3
 155 #define PCICMB_INVALIDATE   4
 156 #define PCICMB_VGASNOOP     5
 157 #define PCICMB_PARITY       6
 158 #define PCICMB_STEPPING     7
 159 #define PCICMB_SERR         8
 160 #define PCICMB_FASTB2B      9
 161
 162 #define PCICMF_IODECODE     (1 << PCICMB_IODECODE)
 163 #define PCICMF_MEMDECODE    (1 << PCICMB_MEMDECODE)
 164 #define PCICMF_BUSMASTER    (1 << PCICMB_BUSMASTER)
 165 #define PCICMF_SPECIAL      (1 << PCICMB_SPECIAL)
 166 #define PCICMF_INVALIDATE   (1 << PCICMB_INVALIDATE)
 167 #define PCICMF_VGASNOOP     (1 << PCICMB_VGASNOOP)
 168 #define PCICMF_PARITY       (1 << PCICMB_PARITY)
 169 #define PCICMF_STEPPING     (1 << PCICMB_STEPPING)
 170 #define PCICMF_SERR         (1 << PCICMB_SERR)
 171 #define PCICMF_FASTB2B      (1 << PCICMB_FASTB2B)
 172
 173 /* PCI Status register bits */
 174 #define PCISTB_INTERRUPT_STATUS 3       /* might be AHCI specific */
 175 #define PCISTB_CAPABILITES      4
 176 #define PCISTB_66MHZ            5
 177 #define PCISTB_FASTB2B          7
 178 #define PCISTB_PARITY           8
 179 #define PCISTB_SIG_TGT_ABORT    11
 180 #define PCISTB_REC_TGT_ABORT    12
 181 #define PCISTB_REC_MAS_ABORT    13
 182 #define PCISTB_SIG_SYSERR       14
 183 #define PCISTB_PARITYERR        15
 184
 185 #define PCISTF_INTERRUPT_STATUS (1 << PCISTB_INTERRUPT_STATUS)
 186 #define PCISTF_CAPABILITIES     (1 << PCISTB_CAPABILITES)
 187 #define PCISTF_66MHZ            (1 << PCISTB_66MHZ)
 188 #define PCISTF_FASTB2B          (1 << PCISTB_FASTB2B)
 189 #define PCISTF_PARITY           (1 << PCISTB_PARITY)
 190 #define PCISTF_SIG_TGT_ABORT    (1 << PCISTB_SIG_TGT_ABORT)
 191 #define PCISTF_REC_TGT_ABORT    (1 << PCISTB_REC_TGT_ABORT)
 192 #define PCISTF_REC_MAS_ABORT    (1 << PCISTB_REC_MAS_ABORT)
 193 #define PCISTF_SIG_SYSERR       (1 << PCISTB_SIG_SYSERR)
 194 #define PCISTF_PARITYERR        (1 << PCISTB_PARITYERR)
 195
 196 #define PCIST_DEVSEL_MASK   0x600
 197 #define PCIST_DEVSEL_FAST   0x000
 198 #define PCIST_DEVSEL_MEDIUM 0x200
 199 #define PCIST_DEVSEL_SLOW   0x400
 200
 201 /* PCI BIST register */
 202 #define PCIBSB_START            6
 203 #define PCIBSB_CAPABLE          7
 204
 205 #define PCIBSF_START            (1 << PCIBSB_START)
 206 #define PCIBSF_CAPABLE          (1 << PCIBSB_CAPABLE)
 207
 208 #define PCIBS_CODEMASK          0x0f
 209
 210 /* PCI BaseAddressRegister defines */
 211 #define PCIBAR_MASK_TYPE        0x01
 212 #define PCIBAR_TYPE_MMAP        0x00
 213 #define PCIBAR_TYPE_IO          0x01
 214 #define PCIBAR_MASK_MEM         0xfffffff0
 215 #define PCIBAR_MASK_IO          0xfffffffc
 216
 217 #define PCIBAR_MEMTYPE_MASK     0x06
 218 #define PCIBAR_MEMTYPE_32BIT    0x00
 219 #define PCIBAR_MEMTYPE_64BIT    0x04
 220
 221 #define PCIBARB_PREFETCHABLE    3
 222 #define PCIBARF_PREFETCHABLE    (1 << PCIBARB_PREFETCHABLE)
 223
 224 /*
 225  * PCI-to-PCI bridge header defines
 226  * First 16 bytes are the same as normal PCI dev
 227  * Use either PCICS_ or PCIBR_ prefix
 228  */
 229 #define PCIBR_VENDOR        PCICS_VENDOR
 230 #define PCIBR_PRODUCT       PCICS_PRODUCT
 231 #define PCIBR_COMMAND       PCICS_COMMAND
 232 #define PCIBR_STATUS        PCICS_STATUS
 233 #define PCIBR_REVISION      PCICS_REVISION
 234 #define PCIBR_PROGIF        PCICS_PROGIF
 235 #define PCIBR_SUBCLASS      PCICS_SUBCLASS
 236 #define PCIBR_CLASS         PCICS_CLASS
 237 #define PCIBR_CACHELS       PCICS_CACHELS
 238 #define PCIBR_LATENCY       PCICS_LATENCY
 239 #define PCIBR_HEADERTYPE    PCICS_HEADERTYPE
 240 #define PCIBR_BIST          PCICS_BIST
 241 #define PCIBR_BAR0          0x10
 242 #define PCIBR_BAR1          0x14
 243 #define PCIBR_PRIBUS        0x18
 244 #define PCIBR_SECBUS        0x19
 245 #define PCIBR_SUBBUS        0x1a
 246 #define PCIBR_SECLATENCY    0x1b
 247 #define PCIBR_IOBASE        0x1c
 248 #define PCIBR_IOLIMIT       0x1d
 249 #define PCIBR_SECSTATUS     0x1e
 250 #define PCIBR_MEMBASE       0x20
 251 #define PCIBR_MEMLIMIT      0x22
 252 #define PCIBR_PREFETCHBASE  0x24
 253 #define PCIBR_PREFETCHLIMIT 0x26
 254 #define PCIBR_PREBASEUPPER  0x28
 255 #define PCIBR_PRELIMITUPPER 0x2c
 256 #define PCIBR_IOBASEUPPER   0x30
 257 #define PCIBR_IOLIMITUPPER  0x32
 258 #define PCIBR_CAPPTR        0x34
 259 #define PCIBR_EXPROMBASE    0x38
 260 #define PCIBR_INT_LINE      0x3c
 261 #define PCIBR_INT_PIN       0x3d
 262 #define PCIBR_CONTROL       0x3e
 263
 264 #define PCICTRLB_ISAENABLE      2
 265 #define PCICTRLB_VGAENABLE      3
 266
 267 #define PCICTRLF_ISAENABLE          (1 << PCICTRLB_ISAENABLE)
 268 #define PCICTRLF_VGAENABLE          (1 << PCICTRLB_VGAENABLE)
 269
 270 /* PCI capabilities */
 271 #define PCICAP_POWER_MANAGEMENT     0x01
 272 #define PCICAP_AGP                  0x02
 273 #define PCICAP_VITAL_PRODUCT_DATA   0x03
 274 #define PCICAP_SLOT_ID              0x04
 275 #define PCICAP_MSI                  0x05
 276 #define PCICAP_CPCI_HOT_SWAP        0x06
 277 #define PCICAP_PCIX                 0x07
 278 #define PCICAP_HYPER_TRANSPORT      0x08
 279 #define PCICAP_VENDOR_SPECIFIC      0x09
 280 #define PCICAP_DEBUG_PORT           0x0a
 281 #define PCICAP_CPCI_CR              0x0b
 282 #define PCICAP_HOT_PLUG_CONTROLLER  0x0c
 283 #define PCICAP_SSVPID               0x0d
 284 #define PCICAP_AGP3                 0x0e
 285 #define PCICAP_PCIE                 0x10
 286 #define PCICAP_MSIX                 0x11
 287 #define PCICAP_ADVANCED_FEATURES    0x13
 288
 289 /* PCI Express Configspace offsets */
 290 #define PCIECS_VENDOR       PCICS_VENDOR
 291 #define PCIECS_PRODUCT      PCICS_PRODUCT
 292 #define PCIECS_COMMAND      PCICS_COMMAND
 293 #define PCIECS_STATUS       PCICS_STATUS
 294 #define PCIECS_REVISION     PCICS_REVISION
 295 #define PCIECS_PROGIF       PCICS_PROGIF
 296 #define PCIECS_SUBCLASS     PCICS_SUBCLASS
 297 #define PCIECS_CLASS        PCICS_CLASS
 298 #define PCIECS_CACHELS      PCICS_CACHELS
 299 #define PCIECS_LATENCY      PCICS_LATENCY
 300 #define PCIECS_HEADERTYPE   PCICS_HEADERTYPE
 301 #define PCIECS_BIST         PCICS_BIST
 302 #define PCIECS_CAP_PTR      PCICS_CAP_PTR
 303 #define PCIECS_INT_LINE     PCICS_INT_LINE
 304 #define PCIECS_INT_PIN      PCICS_INT_PIN
 305
 306 /* PCI Express capability structure */
 307 #define PCIECS_CAPID        0x00
 308 #define PCIECS_NEXTCAP      0x01
 309 #define PCIECS_PCIECAP      0x02
 310 #define PCIECS_DEVCAP       0x04
 311 #define PCIECS_DEVCTL       0x08
 312 #define PCIECS_DEVSTS       0x0A
 313 #define PCIECS_LINKCAP      0x0C
 314 #define PCIECS_LINKCTL      0x10
 315 #define PCIECS_LINKSTS      0x12
 316 #define PCIECS_SLOTCAP      0x14
 317 #define PCIECS_SLOTCTL      0x18
 318 #define PCIECS_SLOTSTS      0x1A
 319 #define PCIECS_ROOTCTL      0x1C
 320 #define PCIECS_ROOTSTS      0x20
 321 #define PCIECS_DEVCAP2      0x24
 322 #define PCIECS_DEVCTL2      0x28
 323 #define PCIECS_DEVSTS2      0x2A
 324 #define PCIECS_LINKCAP2     0x2C
 325 #define PCIECS_LINKCTL2     0x30
 326 #define PCIECS_LINKSTS2     0x32
 327 #define PCIECS_SLOTCAP2     0x34
 328 #define PCIECS_SLOTCTL2     0x38
 329 #define PCIECS_SLOTSTS2     0x3A
 330
 331 /* PCI Express capabilities */
 332 #define PCIECAP_VER_MASK    0xF
 333 #define PCIECAP_VER_10      0x1 /* PCIe spec 1.0 */
 334 #define PCIECAP_VER_20      0x2 /* PCIe spec 2.0 */
 335
 336 #endif /* _PCI_H */
 337