arch/x86-all/processor/processor_arch_intern.h

   1 /*
   2     Copyright © 2010-2011, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #ifndef PROCESSOR_ARCH_INTERN_H
   7 #define PROCESSOR_ARCH_INTERN_H
   8
   9 #include <exec/types.h>
  10
  11 struct X86ProcessorInformation
  12 {
  13     TEXT    VendorID[13]; /* 12 + \0 */
  14     ULONG   Vendor;
  15     TEXT    BrandStringBuffer[48];
  16     STRPTR  BrandString;
  17     ULONG   Family;
  18     ULONG   Model;
  19     ULONG   VectorUnit;
  20     ULONG   Features1;  /* From EDX, function 00000001 */
  21     ULONG   Features2;  /* From ECX, function 00000001 */
  22     ULONG   Features3;  /* From EDX, function 80000001 */
  23     ULONG   Features4;  /* From ECX, function 80000001 */
  24
  25     /* CPUID Information */
  26     ULONG   CPUIDHighestStandardFunction;
  27     ULONG   CPUIDHighestExtendedFunction;
  28
  29     /* Processor cache */
  30     ULONG   L1DataCacheSize;
  31     ULONG   L1InstructionCacheSize;
  32     ULONG   L2CacheSize;
  33     ULONG   L3CacheSize;
  34     ULONG   CacheLineSize;  /* Min. of L1, L2, L3 */
  35
  36     /* MSR Support */
  37     BOOL    APERFMPERF;
  38
  39     /* Frequency information */
  40     UQUAD   MaxCPUFrequency;
  41     UQUAD   MaxFSBFrequency;
  42 };
  43
  44 #define cpuid(num) \
  45     do { asm volatile("cpuid":"=a"(eax),"=b"(ebx),"=c"(ecx),"=d"(edx):"a"(num)); } while(0)
  46
  47 static inline void __attribute__((always_inline)) rdmsr(LONG msr_no, LONG *ret_lo, LONG *ret_hi)
  48 {
  49     LONG ret1,ret2;
  50     asm volatile("rdmsr":"=a"(ret1),"=d"(ret2):"c"(msr_no));
  51     *ret_lo=ret1;
  52     *ret_hi=ret2;
  53 }
  54
  55
  56 VOID ReadProcessorInformation(struct X86ProcessorInformation * info);
  57 VOID ReadMaxFrequencyInformation(struct X86ProcessorInformation * info);
  58 UQUAD GetCurrentProcessorFrequency(struct X86ProcessorInformation * info);
  59
  60 /* EDX 00000001 Flags */
  61 #define FEATB_FPU   0
  62 #define FEATB_VME   1
  63 #define FEATB_PSE   3
  64 #define FEATB_MSR   5
  65 #define FEATB_PAE   6
  66 #define FEATB_CX8   8
  67 #define FEATB_APIC  9
  68 #define FEATB_CMOV  15
  69 #define FEATB_PSE36 17
  70 #define FEATB_CLFSH 19
  71 #define FEATB_ACPI  22
  72 #define FEATB_MMX   23
  73 #define FEATB_FXSR  24
  74 #define FEATB_SSE   25
  75 #define FEATB_SSE2  26
  76 #define FEATB_HTT   28
  77
  78 #define FEATF_FPU   (1 << FEATB_FPU)
  79 #define FEATF_VME   (1 << FEATB_VME)
  80 #define FEATF_PSE   (1 << FEATB_PSE)
  81 #define FEATF_MSR   (1 << FEATB_MSR)
  82 #define FEATF_PAE   (1 << FEATB_PAE)
  83 #define FEATF_CX8   (1 << FEATB_CX8)
  84 #define FEATF_APIC  (1 << FEATB_APIC)
  85 #define FEATF_CMOV  (1 << FEATB_CMOV)
  86 #define FEATF_PSE36 (1 << FEATB_PSE36)
  87 #define FEATF_CLFSH (1 << FEATB_CLFSH)
  88 #define FEATF_ACPI  (1 << FEATB_ACPI)
  89 #define FEATF_MMX   (1 << FEATB_MMX)
  90 #define FEATF_FXSR  (1 << FEATB_FXSR)
  91 #define FEATF_SSE   (1 << FEATB_SSE)
  92 #define FEATF_SSE2  (1 << FEATB_SSE2)
  93 #define FEATF_HTT   (1 << FEATB_HTT)
  94
  95 /* ECX 00000001 Flags */
  96 #define FEATB_SSE3  0
  97 #define FEATB_VMX   5
  98 #define FEATB_SSSE3 9
  99 #define FEATB_CX16  13
 100 #define FEATB_SSE41 19
 101 #define FEATB_SSE42 20
 102
 103 #define FEATF_SSE3  (1 << FEATB_SSE3)
 104 #define FEATF_VMX   (1 << FEATB_VMX)
 105 #define FEATF_SSSE3 (1 << FEATB_SSSE3)
 106 #define FEATF_CX16  (1 << FEATB_CX16)
 107 #define FEATF_SSE41 (1 << FEATB_SSE41)
 108 #define FEATF_SSE42 (1 << FEATB_SSE42)
 109
 110 /* EDX 80000001 AMD Flags */
 111 #define FEATB_XDNX      20
 112 #define FEATB_MMXEXT    22
 113 #define FEATB_AMD64     29
 114 #define FEATB_3DNOWEXT  30
 115 #define FEATB_3DNOW     31
 116
 117 #define FEATF_XDNX      (1 << FEATB_XDNX)
 118 #define FEATF_MMXEXT    (1 << FEATB_MMXEXT)
 119 #define FEATF_AMD64     (1 << FEATB_AMD64)
 120 #define FEATF_3DNOWEXT  (1 << FEATB_3DNOWEXT)
 121 #define FEATF_3DNOW     (1 << FEATB_3DNOW)
 122
 123 /* ECX 80000001 AMD Flags */
 124 #define FEATB_SVM       2
 125 #define FEATB_SSE4A     6
 126
 127 #define FEATF_SVM       (1 << FEATB_SVM)
 128 #define FEATF_SSE4A     (1 << FEATB_SSE4A)
 129
 130 /* Per manufacturer feature masks */
 131 #define FEATURE_MASK_EDX_UNKNOWN    0
 132 #define FEATURE_MASK_ECX_UNKNOWN    0
 133
 134 #define FEATURE_MASK_EDX_INTEL \
 135     (FEATF_FPU | FEATF_VME | FEATF_PSE | FEATF_MSR | FEATF_PAE | FEATF_CX8 | FEATF_APIC | \
 136     FEATF_CMOV | FEATF_PSE36 | FEATF_CLFSH | FEATF_ACPI | FEATF_MMX | \
 137     FEATF_FXSR | FEATF_SSE | FEATF_SSE2 | FEATF_HTT)
 138 #define FEATURE_MASK_ECX_INTEL \
 139     (FEATF_SSE3 | FEATF_VMX | FEATF_SSSE3 | FEATF_CX16 | FEATF_SSE41 | \
 140     FEATF_SSE42)
 141 #define FEATURE_MASK_EDX_EXT_INTEL \
 142     (FEATF_XDNX | FEATF_AMD64)
 143 #define FEATURE_MASK_ECX_EXT_INTEL  0
 144
 145 #define FEATURE_MASK_EDX_AMD \
 146     (FEATF_FPU | FEATF_VME | FEATF_PSE | FEATF_MSR | FEATF_PAE | FEATF_CX8 | FEATF_APIC | \
 147     FEATF_CMOV | FEATF_PSE36 | FEATF_CLFSH | FEATF_MMX | FEATF_FXSR | \
 148     FEATF_SSE | FEATF_SSE2 | FEATF_HTT)
 149 #define FEATURE_MASK_ECX_AMD \
 150     (FEATF_SSE3 | FEATF_SSSE3 | FEATF_CX16 | FEATF_SSE41)
 151 #define FEATURE_MASK_EDX_EXT_AMD \
 152     (FEATF_XDNX | FEATF_MMXEXT | FEATF_AMD64 | FEATF_3DNOWEXT | FEATF_3DNOW)
 153 #define FEATURE_MASK_ECX_EXT_AMD \
 154     (FEATF_SVM | FEATF_SSE4A)
 155
 156 #endif /* PROCESSOR_ARCH_INTERN_H */