1 Test Access Port implementation for the ZPU (alpha)
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3 08/2011 Martin Strubel <hackfin@section5.ch>
6 - Implements JTAG interface (on FPGA custom pins) for the zealot small core.
7 Zealot medium (and others) under scrutiny.
8 - Important: Clock synchronization between TCK and core clock domain has
9 to be taken care of by the parenting module, in particular for the
10 emuexec_i pin. That means: From the emuexec rising edge signal from the TAP
11 you have to create a one core clock cycle wide emuexec_i pulse.
12 - If you want to swap the debug interface, just write a new tapxxx.vhd
13 - The software debug interface may change, and it may be different for various
14 implementations of the ZPU.
16 * Create and register various ZPU core IDs (IDCODE instruction)
17 * Take care of the ZPU variant in the zpu emulation library:
18 $ZPU/zpu/sw/emulation/
19 * Likewise, handle various debug interfaces (direct/indirect JTAG, etc.)
20 * Implement different debug targets in gdbproxy, callable like
21 'gdbproxy zpu_<special_interface_name>', and just use different
22 libzpuemu configurations.