gdi32/tests: GetGlyphOutline should fail for a bitmap font.
[wine/multimedia.git] / programs / winedbg / be_arm.c
blobc66c2b0fcbf6fcfbacc053081ba9d6cabd56a63f
1 /*
2 * Debugger ARM specific functions
4 * Copyright 2000-2003 Marcus Meissner
5 * 2004 Eric Pouech
6 * 2010-2012 André Hentschel
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
23 #include "debugger.h"
25 #if defined(__arm__) && !defined(__ARMEB__)
28 * Switch to disassemble Thumb code.
30 static BOOL db_disasm_thumb = FALSE;
33 * Flag to indicate whether we need to display instruction,
34 * or whether we just need to know the address of the next
35 * instruction.
37 static BOOL db_display = FALSE;
39 #define ARM_INSN_SIZE 4
40 #define THUMB_INSN_SIZE 2
41 #define THUMB2_INSN_SIZE 4
43 #define ROR32(n, r) (((n) >> (r)) | ((n) << (32 - (r))))
45 #define get_cond(ins) tbl_cond[(ins >> 28) & 0x0f]
46 #define get_nibble(ins, num) ((ins >> (num * 4)) & 0x0f)
48 static char const tbl_regs[][4] = {
49 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
50 "fp", "ip", "sp", "lr", "pc", "cpsr"
53 static char const tbl_addrmode[][3] = {
54 "da", "ia", "db", "ib"
57 static char const tbl_cond[][3] = {
58 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", ""
61 static char const tbl_dataops[][4] = {
62 "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", "tst", "teq", "cmp", "cmn", "orr",
63 "mov", "bic", "mvn"
66 static char const tbl_shifts[][4] = {
67 "lsl", "lsr", "asr", "ror"
70 static char const tbl_hiops_t[][4] = {
71 "add", "cmp", "mov", "bx"
74 static char const tbl_aluops_t[][4] = {
75 "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", "tst", "neg", "cmp", "cmn", "orr",
76 "mul", "bic", "mvn"
79 static char const tbl_immops_t[][4] = {
80 "mov", "cmp", "add", "sub"
83 static char const tbl_sregops_t[][5] = {
84 "strh", "ldsb", "ldrh", "ldsh"
87 static UINT db_get_inst(void* addr, int size)
89 UINT result = 0;
90 char buffer[4];
92 if (dbg_read_memory(addr, buffer, size))
94 switch (size)
96 case 4:
97 result = *(UINT*)buffer;
98 break;
99 case 2:
100 result = *(WORD*)buffer;
101 break;
104 return result;
107 static void db_printsym(unsigned int addr)
109 ADDRESS64 a;
111 a.Mode = AddrModeFlat;
112 a.Offset = addr;
114 print_address(&a, TRUE);
117 static UINT arm_disasm_branch(UINT inst, ADDRESS64 *addr)
119 short link = (inst >> 24) & 0x01;
120 int offset = (inst << 2) & 0x03ffffff;
122 if (offset & 0x02000000) offset |= 0xfc000000;
123 offset += 8;
125 dbg_printf("\n\tb%s%s\t", link ? "l" : "", get_cond(inst));
126 db_printsym(addr->Offset + offset);
127 return 0;
130 static UINT arm_disasm_branchreg(UINT inst, ADDRESS64 *addr)
132 dbg_printf("\n\tb%s\t%s", get_cond(inst), tbl_regs[get_nibble(inst, 0)]);
133 return 0;
136 static UINT arm_disasm_dataprocessing(UINT inst, ADDRESS64 *addr)
138 short condcodes = (inst >> 20) & 0x01;
139 short opcode = (inst >> 21) & 0x0f;
140 short immediate = (inst >> 25) & 0x01;
141 short no_op1 = (opcode & 0x0d) == 0x0d;
142 short no_dst = (opcode & 0x0c) == 0x08;
144 /* check for nop */
145 if (get_nibble(inst, 3) == 15 /* r15 */ && condcodes == 0 &&
146 opcode >= 8 /* tst */ && opcode <= 11 /* cmn */)
148 dbg_printf("\n\tnop");
149 return 0;
152 dbg_printf("\n\t%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond(inst));
153 if (!no_dst) dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
154 else dbg_printf("\t");
156 if (no_op1)
158 if (immediate)
159 dbg_printf("#%u", ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
160 else
161 dbg_printf("%s", tbl_regs[get_nibble(inst, 0)]);
163 else
165 if (immediate)
166 dbg_printf("%s, #%u", tbl_regs[get_nibble(inst, 4)],
167 ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
168 else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
169 dbg_printf("%s, %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
170 else if (((inst >> 4) & 0x09) == 0x01) /* register shift */
171 dbg_printf("%s, %s, %s %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
172 tbl_shifts[(inst >> 5) & 0x03], tbl_regs[(inst >> 8) & 0x0f]);
173 else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift */
174 dbg_printf("%s, %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
175 tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
176 else
177 return inst;
179 return 0;
182 static UINT arm_disasm_singletrans(UINT inst, ADDRESS64 *addr)
184 short load = (inst >> 20) & 0x01;
185 short writeback = (inst >> 21) & 0x01;
186 short byte = (inst >> 22) & 0x01;
187 short direction = (inst >> 23) & 0x01;
188 short indexing = (inst >> 24) & 0x01;
189 short immediate = !((inst >> 25) & 0x01);
190 short offset = inst & 0x0fff;
192 if (!direction) offset *= -1;
194 dbg_printf("\n\t%s%s%s%s", load ? "ldr" : "str", byte ? "b" : "", writeback ? "t" : "",
195 get_cond(inst));
196 dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
197 if (indexing)
199 if (immediate)
200 dbg_printf("[%s, #%d]", tbl_regs[get_nibble(inst, 4)], offset);
201 else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
202 dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
203 else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
204 dbg_printf("[%s, %s, %s #%d]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
205 tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
206 else
207 return inst;
209 else
211 if (immediate)
212 dbg_printf("[%s], #%d", tbl_regs[get_nibble(inst, 4)], offset);
213 else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
214 dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
215 else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
216 dbg_printf("[%s], %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
217 tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
218 else
219 return inst;
221 return 0;
224 static UINT arm_disasm_halfwordtrans(UINT inst, ADDRESS64 *addr)
226 short halfword = (inst >> 5) & 0x01;
227 short sign = (inst >> 6) & 0x01;
228 short load = (inst >> 20) & 0x01;
229 short writeback = (inst >> 21) & 0x01;
230 short immediate = (inst >> 22) & 0x01;
231 short direction = (inst >> 23) & 0x01;
232 short indexing = (inst >> 24) & 0x01;
233 short offset = ((inst >> 4) & 0xf0) + (inst & 0x0f);
235 if (!direction) offset *= -1;
237 dbg_printf("\n\t%s%s%s%s%s", load ? "ldr" : "str", sign ? "s" : "",
238 halfword ? "h" : (sign ? "b" : ""), writeback ? "t" : "", get_cond(inst));
239 dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
240 if (indexing)
242 if (immediate)
243 dbg_printf("[%s, #%d]", tbl_regs[get_nibble(inst, 4)], offset);
244 else
245 dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
247 else
249 if (immediate)
250 dbg_printf("[%s], #%d", tbl_regs[get_nibble(inst, 4)], offset);
251 else
252 dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
254 return 0;
257 static UINT arm_disasm_blocktrans(UINT inst, ADDRESS64 *addr)
259 short load = (inst >> 20) & 0x01;
260 short writeback = (inst >> 21) & 0x01;
261 short psr = (inst >> 22) & 0x01;
262 short addrmode = (inst >> 23) & 0x03;
263 short i;
264 short last=15;
265 for (i=15;i>=0;i--)
266 if ((inst>>i) & 1)
268 last = i;
269 break;
272 dbg_printf("\n\t%s%s%s\t%s%s, {", load ? "ldm" : "stm", tbl_addrmode[addrmode], get_cond(inst),
273 tbl_regs[get_nibble(inst, 4)], writeback ? "!" : "");
274 for (i=0;i<=15;i++)
275 if ((inst>>i) & 1)
277 if (i == last) dbg_printf("%s", tbl_regs[i]);
278 else dbg_printf("%s, ", tbl_regs[i]);
280 dbg_printf("}%s", psr ? "^" : "");
281 return 0;
284 static UINT arm_disasm_swi(UINT inst, ADDRESS64 *addr)
286 UINT comment = inst & 0x00ffffff;
287 dbg_printf("\n\tswi%s\t#%d", get_cond(inst), comment);
288 return 0;
291 static UINT arm_disasm_coproctrans(UINT inst, ADDRESS64 *addr)
293 WORD CRm = inst & 0x0f;
294 WORD CP = (inst >> 5) & 0x07;
295 WORD CPnum = (inst >> 8) & 0x0f;
296 WORD CRn = (inst >> 16) & 0x0f;
297 WORD load = (inst >> 20) & 0x01;
298 WORD CP_Opc = (inst >> 21) & 0x07;
300 dbg_printf("\n\t%s%s\t%u, %u, %s, cr%u, cr%u, {%u}", load ? "mrc" : "mcr", get_cond(inst), CPnum,
301 CP, tbl_regs[get_nibble(inst, 3)], CRn, CRm, CP_Opc);
302 return 0;
305 static UINT arm_disasm_coprocdataop(UINT inst, ADDRESS64 *addr)
307 WORD CRm = inst & 0x0f;
308 WORD CP = (inst >> 5) & 0x07;
309 WORD CPnum = (inst >> 8) & 0x0f;
310 WORD CRd = (inst >> 12) & 0x0f;
311 WORD CRn = (inst >> 16) & 0x0f;
312 WORD CP_Opc = (inst >> 20) & 0x0f;
314 dbg_printf("\n\tcdp%s\t%u, %u, cr%u, cr%u, cr%u, {%u}", get_cond(inst),
315 CPnum, CP, CRd, CRn, CRm, CP_Opc);
316 return 0;
319 static UINT arm_disasm_coprocdatatrans(UINT inst, ADDRESS64 *addr)
321 WORD CPnum = (inst >> 8) & 0x0f;
322 WORD CRd = (inst >> 12) & 0x0f;
323 WORD load = (inst >> 20) & 0x01;
324 WORD writeback = (inst >> 21) & 0x01;
325 WORD translen = (inst >> 22) & 0x01;
326 WORD direction = (inst >> 23) & 0x01;
327 WORD indexing = (inst >> 24) & 0x01;
328 short offset = (inst & 0xff) << 2;
330 if (!direction) offset *= -1;
332 dbg_printf("\n\t%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond(inst));
333 if (indexing)
334 dbg_printf("\t%u, cr%u, [%s, #%d]%s", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], offset, writeback?"!":"");
335 else
336 dbg_printf("\t%u, cr%u, [%s], #%d", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], offset);
337 return 0;
340 static WORD thumb_disasm_hireg(WORD inst, ADDRESS64 *addr)
342 short dst = inst & 0x07;
343 short src = (inst >> 3) & 0x07;
344 short h2 = (inst >> 6) & 0x01;
345 short h1 = (inst >> 7) & 0x01;
346 short op = (inst >> 8) & 0x03;
348 if (h1) dst += 8;
349 if (h2) src += 8;
351 if (op == 2 && dst == src) /* mov rx, rx */
353 dbg_printf("\n\tnop");
354 return 0;
357 if (op == 3)
358 dbg_printf("\n\tb%sx\t%s", h1?"l":"", tbl_regs[src]);
359 else
360 dbg_printf("\n\t%s\t%s, %s", tbl_hiops_t[op], tbl_regs[dst], tbl_regs[src]);
362 return 0;
365 static WORD thumb_disasm_aluop(WORD inst, ADDRESS64 *addr)
367 short dst = inst & 0x07;
368 short src = (inst >> 3) & 0x07;
369 short op = (inst >> 6) & 0x0f;
371 dbg_printf("\n\t%s\t%s, %s", tbl_aluops_t[op], tbl_regs[dst], tbl_regs[src]);
373 return 0;
376 static WORD thumb_disasm_pushpop(WORD inst, ADDRESS64 *addr)
378 short lrpc = (inst >> 8) & 0x01;
379 short load = (inst >> 11) & 0x01;
380 short i;
381 short last;
383 for (i=7;i>=0;i--)
384 if ((inst>>i) & 1) break;
385 last = i;
387 dbg_printf("\n\t%s\t{", load ? "pop" : "push");
389 for (i=0;i<=7;i++)
390 if ((inst>>i) & 1)
392 if (i == last) dbg_printf("%s", tbl_regs[i]);
393 else dbg_printf("%s, ", tbl_regs[i]);
395 if (lrpc)
396 dbg_printf("%s%s", last ? ", " : "", load ? "pc" : "lr");
398 dbg_printf("}");
399 return 0;
402 static WORD thumb_disasm_blocktrans(WORD inst, ADDRESS64 *addr)
404 short load = (inst >> 11) & 0x01;
405 short i;
406 short last;
408 for (i=7;i>=0;i--)
409 if ((inst>>i) & 1) break;
410 last = i;
412 dbg_printf("\n\t%s\t%s!, {", load ? "ldmia" : "stmia", tbl_regs[(inst >> 8) & 0x07]);
414 for (i=0;i<=7;i++)
415 if ((inst>>i) & 1)
417 if (i == last) dbg_printf("%s", tbl_regs[i]);
418 else dbg_printf("%s, ", tbl_regs[i]);
421 dbg_printf("}");
422 return 0;
425 static WORD thumb_disasm_condbranch(WORD inst, ADDRESS64 *addr)
427 WORD offset = inst & 0x00ff;
428 dbg_printf("\n\tb%s\t", tbl_cond[(inst >> 8) & 0x0f]);
429 db_printsym(addr->Offset + offset);
430 return 0;
433 static WORD thumb_disasm_uncondbranch(WORD inst, ADDRESS64 *addr)
435 short offset = (inst & 0x07ff) << 1;
437 if (offset & 0x0800) offset |= 0xf000;
438 offset += 4;
440 dbg_printf("\n\tb\t");
441 db_printsym(addr->Offset + offset);
442 return 0;
445 static WORD thumb_disasm_loadadr(WORD inst, ADDRESS64 *addr)
447 WORD src = (inst >> 11) & 0x01;
448 WORD offset = (inst & 0xff) << 2;
450 dbg_printf("\n\tadd\t%s, %s, #%d", tbl_regs[(inst >> 8) & 0x07], src ? "sp" : "pc", offset);
451 return 0;
454 static WORD thumb_disasm_swi(WORD inst, ADDRESS64 *addr)
456 WORD comment = inst & 0x00ff;
457 dbg_printf("\n\tswi\t#%d", comment);
458 return 0;
461 static WORD thumb_disasm_nop(WORD inst, ADDRESS64 *addr)
463 dbg_printf("\n\tnop");
464 return 0;
467 static WORD thumb_disasm_ldrpcrel(WORD inst, ADDRESS64 *addr)
469 WORD offset = (inst & 0xff) << 2;
470 dbg_printf("\n\tldr\t%s, [pc, #%u]", tbl_regs[(inst >> 8) & 0x07], offset);
471 return 0;
474 static WORD thumb_disasm_ldrsprel(WORD inst, ADDRESS64 *addr)
476 WORD offset = (inst & 0xff) << 2;
477 dbg_printf("\n\t%s\t%s, [sp, #%u]", (inst & 0x0800)?"ldr":"str", tbl_regs[(inst >> 8) & 0x07], offset);
478 return 0;
481 static WORD thumb_disasm_addsprel(WORD inst, ADDRESS64 *addr)
483 WORD offset = (inst & 0x7f) << 2;
484 if ((inst >> 7) & 0x01)
485 dbg_printf("\n\tsub\tsp, sp, #%u", offset);
486 else
487 dbg_printf("\n\tadd\tsp, sp, #%u", offset);
488 return 0;
491 static WORD thumb_disasm_ldrimm(WORD inst, ADDRESS64 *addr)
493 WORD offset = (inst & 0x07c0) >> 6;
494 dbg_printf("\n\t%s%s\t%s, [%s, #%u]", (inst & 0x0800)?"ldr":"str", (inst & 0x1000)?"b":"",
495 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst & 0x1000)?offset:(offset << 2));
496 return 0;
499 static WORD thumb_disasm_ldrhimm(WORD inst, ADDRESS64 *addr)
501 WORD offset = (inst & 0x07c0) >> 5;
502 dbg_printf("\n\t%s\t%s, [%s, #%u]", (inst & 0x0800)?"ldrh":"strh",
503 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], offset);
504 return 0;
507 static WORD thumb_disasm_ldrreg(WORD inst, ADDRESS64 *addr)
509 dbg_printf("\n\t%s%s\t%s, [%s, %s]", (inst & 0x0800)?"ldr":"str", (inst & 0x0400)?"b":"",
510 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], tbl_regs[(inst >> 6) & 0x07]);
511 return 0;
514 static WORD thumb_disasm_ldrsreg(WORD inst, ADDRESS64 *addr)
516 dbg_printf("\n\t%s\t%s, [%s, %s]", tbl_sregops_t[(inst >> 10) & 0x03],
517 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], tbl_regs[(inst >> 6) & 0x07]);
518 return 0;
521 static WORD thumb_disasm_immop(WORD inst, ADDRESS64 *addr)
523 WORD op = (inst >> 11) & 0x03;
524 dbg_printf("\n\t%s\t%s, #%u", tbl_immops_t[op], tbl_regs[(inst >> 8) & 0x07], inst & 0xff);
525 return 0;
528 static WORD thumb_disasm_addsub(WORD inst, ADDRESS64 *addr)
530 WORD op = (inst >> 9) & 0x01;
531 WORD immediate = (inst >> 10) & 0x01;
533 dbg_printf("\n\t%s\t%s, %s, ", op ? "sub" : "add",
534 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07]);
535 if (immediate)
536 dbg_printf("#%d", (inst >> 6) & 0x07);
537 else
538 dbg_printf("%s", tbl_regs[(inst >> 6) & 0x07]);
539 return 0;
542 static WORD thumb_disasm_movshift(WORD inst, ADDRESS64 *addr)
544 WORD op = (inst >> 11) & 0x03;
545 dbg_printf("\n\t%s\t%s, %s, #%u", tbl_shifts[op],
546 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst >> 6) & 0x1f);
547 return 0;
550 static UINT thumb2_disasm_branchlinked(UINT inst, ADDRESS64 *addr)
552 UINT offset = (((inst & 0x07ff0000) >> 4) | ((inst & 0x000007ff) << 1)) + 4;
554 dbg_printf("\n\tbl\t");
555 db_printsym(addr->Offset + offset);
556 return 0;
559 static UINT thumb2_disasm_misc(UINT inst, ADDRESS64 *addr)
561 WORD op1 = (inst >> 20) & 0x03;
562 WORD op2 = (inst >> 4) & 0x03;
564 if (get_nibble(inst, 4) != get_nibble(inst, 0))
565 return inst;
567 if (op1 == 3 && op2 == 0)
569 dbg_printf("\n\tclz\t%s, %s\t", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
570 return 0;
573 if (op1 == 1)
575 switch (op2)
577 case 0:
578 dbg_printf("\n\trev\t");
579 break;
580 case 1:
581 dbg_printf("\n\trev16\t");
582 break;
583 case 2:
584 dbg_printf("\n\trbit\t");
585 break;
586 case 3:
587 dbg_printf("\n\trevsh\t");
588 break;
590 dbg_printf("%s, %s\t", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
591 return 0;
594 return inst;
597 struct inst_arm
599 UINT mask;
600 UINT pattern;
601 UINT (*func)(UINT, ADDRESS64*);
604 static const struct inst_arm tbl_arm[] = {
605 { 0x0e000000, 0x0a000000, arm_disasm_branch },
606 { 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
607 { 0x0fffff00, 0x012fff00, arm_disasm_branchreg },
608 { 0x0c000000, 0x00000000, arm_disasm_dataprocessing },
609 { 0x0c000000, 0x04000000, arm_disasm_singletrans },
610 { 0x0e000000, 0x08000000, arm_disasm_blocktrans },
611 { 0x0f000000, 0x0f000000, arm_disasm_swi },
612 { 0x0f000010, 0x0e000010, arm_disasm_coproctrans },
613 { 0x0f000010, 0x0e000000, arm_disasm_coprocdataop },
614 { 0x0e000000, 0x0c000000, arm_disasm_coprocdatatrans },
615 { 0x00000000, 0x00000000, NULL }
618 struct inst_thumb16
620 WORD mask;
621 WORD pattern;
622 WORD (*func)(WORD, ADDRESS64*);
625 static const struct inst_thumb16 tbl_thumb16[] = {
626 { 0xfc00, 0x4400, thumb_disasm_hireg },
627 { 0xfc00, 0x4000, thumb_disasm_aluop },
628 { 0xf600, 0xb400, thumb_disasm_pushpop },
629 { 0xf000, 0xc000, thumb_disasm_blocktrans },
630 { 0xf000, 0xd000, thumb_disasm_condbranch },
631 { 0xf800, 0xe000, thumb_disasm_uncondbranch },
632 { 0xf000, 0xa000, thumb_disasm_loadadr },
633 { 0xf800, 0x4800, thumb_disasm_ldrpcrel },
634 { 0xf000, 0x9000, thumb_disasm_ldrsprel },
635 { 0xff00, 0xb000, thumb_disasm_addsprel },
636 { 0xe000, 0x6000, thumb_disasm_ldrimm },
637 { 0xf000, 0x8000, thumb_disasm_ldrhimm },
638 { 0xf200, 0x5000, thumb_disasm_ldrreg },
639 { 0xf200, 0x5200, thumb_disasm_ldrsreg },
640 { 0xe000, 0x2000, thumb_disasm_immop },
641 { 0xff00, 0xdf00, thumb_disasm_swi },
642 { 0xff00, 0xbf00, thumb_disasm_nop },
643 { 0xf800, 0x1800, thumb_disasm_addsub },
644 { 0xe000, 0x0000, thumb_disasm_movshift },
645 { 0x0000, 0x0000, NULL }
648 static const struct inst_arm tbl_thumb32[] = {
649 { 0xf800f800, 0xf000f800, thumb2_disasm_branchlinked },
650 { 0xffc0f0c0, 0xfa80f080, thumb2_disasm_misc },
651 { 0x00000000, 0x00000000, NULL }
654 /***********************************************************************
655 * disasm_one_insn
657 * Disassemble instruction at 'addr'. addr is changed to point to the
658 * start of the next instruction.
660 void be_arm_disasm_one_insn(ADDRESS64 *addr, int display)
662 struct inst_arm *a_ptr = (struct inst_arm *)&tbl_arm;
663 struct inst_thumb16 *t_ptr = (struct inst_thumb16 *)&tbl_thumb16;
664 struct inst_arm *t2_ptr = (struct inst_arm *)&tbl_thumb32;
665 UINT inst;
666 WORD tinst;
667 int size;
668 int matched = 0;
670 char tmp[64];
671 DWORD_PTR* pval;
673 if (!memory_get_register(CV_ARM_CPSR, &pval, tmp, sizeof(tmp)))
674 dbg_printf("\n\tmemory_get_register failed: %s", tmp);
675 else
676 db_disasm_thumb=(*pval & 0x20)?TRUE:FALSE;
678 db_display = display;
680 if (!db_disasm_thumb)
682 size = ARM_INSN_SIZE;
683 inst = db_get_inst( memory_to_linear_addr(addr), size );
684 while (a_ptr->func) {
685 if ((inst & a_ptr->mask) == a_ptr->pattern) {
686 matched = 1;
687 break;
689 a_ptr++;
692 if (!matched) {
693 dbg_printf("\n\tUnknown ARM Instruction: %08x", inst);
694 addr->Offset += size;
696 else
698 if (!a_ptr->func(inst, addr))
699 addr->Offset += size;
701 return;
703 else
705 WORD *taddr = memory_to_linear_addr(addr);
706 tinst = db_get_inst( taddr, THUMB_INSN_SIZE );
707 switch (tinst & 0xf800)
709 case 0xe800:
710 case 0xf000:
711 case 0xf800:
712 size = THUMB2_INSN_SIZE;
713 taddr++;
714 inst = db_get_inst( taddr, THUMB_INSN_SIZE );
715 inst |= (tinst << 16);
717 while (t2_ptr->func) {
718 if ((inst & t2_ptr->mask) == t2_ptr->pattern) {
719 matched = 1;
720 break;
722 t2_ptr++;
725 if (!matched) {
726 dbg_printf("\n\tUnknown Thumb2 Instruction: %08x", inst);
727 addr->Offset += size;
729 else
731 if (!t2_ptr->func(inst, addr))
732 addr->Offset += size;
734 return;
735 default:
736 break;
739 size = THUMB_INSN_SIZE;
740 while (t_ptr->func) {
741 if ((tinst & t_ptr->mask) == t_ptr->pattern) {
742 matched = 1;
743 break;
745 t_ptr++;
748 if (!matched) {
749 dbg_printf("\n\tUnknown Thumb Instruction: %04x", tinst);
750 addr->Offset += size;
752 else
754 if (!t_ptr->func(tinst, addr))
755 addr->Offset += size;
757 return;
761 static unsigned be_arm_get_addr(HANDLE hThread, const CONTEXT* ctx,
762 enum be_cpu_addr bca, ADDRESS64* addr)
764 switch (bca)
766 case be_cpu_addr_pc:
767 return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Pc);
768 case be_cpu_addr_stack:
769 return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Sp);
770 case be_cpu_addr_frame:
771 return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Fp);
773 return FALSE;
776 static unsigned be_arm_get_register_info(int regno, enum be_cpu_addr* kind)
778 switch (regno)
780 case CV_ARM_PC: *kind = be_cpu_addr_pc; return TRUE;
781 case CV_ARM_R0 + 11: *kind = be_cpu_addr_frame; return TRUE;
782 case CV_ARM_SP: *kind = be_cpu_addr_stack; return TRUE;
784 return FALSE;
787 static void be_arm_single_step(CONTEXT* ctx, unsigned enable)
789 dbg_printf("be_arm_single_step: not done\n");
792 static void be_arm_print_context(HANDLE hThread, const CONTEXT* ctx, int all_regs)
794 static const char condflags[] = "NZCV";
795 int i;
796 char buf[8];
798 switch (ctx->Cpsr & 0x1F)
800 case 0: strcpy(buf, "User26"); break;
801 case 1: strcpy(buf, "FIQ26"); break;
802 case 2: strcpy(buf, "IRQ26"); break;
803 case 3: strcpy(buf, "SVC26"); break;
804 case 16: strcpy(buf, "User"); break;
805 case 17: strcpy(buf, "FIQ"); break;
806 case 18: strcpy(buf, "IRQ"); break;
807 case 19: strcpy(buf, "SVC"); break;
808 case 23: strcpy(buf, "ABT"); break;
809 case 27: strcpy(buf, "UND"); break;
810 default: strcpy(buf, "UNKNWN"); break;
813 dbg_printf("Register dump:\n");
814 dbg_printf("%s %s Mode\n", (ctx->Cpsr & 0x20) ? "Thumb" : "ARM", buf);
816 strcpy(buf, condflags);
817 for (i = 0; buf[i]; i++)
818 if (!((ctx->Cpsr >> 26) & (1 << (sizeof(condflags) - i))))
819 buf[i] = '-';
821 dbg_printf(" Pc:%04x Sp:%04x Lr:%04x Cpsr:%04x(%s)\n",
822 ctx->Pc, ctx->Sp, ctx->Lr, ctx->Cpsr, buf);
823 dbg_printf(" r0:%04x r1:%04x r2:%04x r3:%04x\n",
824 ctx->R0, ctx->R1, ctx->R2, ctx->R3);
825 dbg_printf(" r4:%04x r5:%04x r6:%04x r7:%04x r8:%04x\n",
826 ctx->R4, ctx->R5, ctx->R6, ctx->R7, ctx->R8 );
827 dbg_printf(" r9:%04x r10:%04x Fp:%04x Ip:%04x\n",
828 ctx->R9, ctx->R10, ctx->Fp, ctx->Ip );
830 if (all_regs) dbg_printf( "Floating point ARM dump not implemented\n" );
833 static void be_arm_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
837 static struct dbg_internal_var be_arm_ctx[] =
839 {CV_ARM_R0 + 0, "r0", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R0), dbg_itype_unsigned_int},
840 {CV_ARM_R0 + 1, "r1", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R1), dbg_itype_unsigned_int},
841 {CV_ARM_R0 + 2, "r2", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R2), dbg_itype_unsigned_int},
842 {CV_ARM_R0 + 3, "r3", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R3), dbg_itype_unsigned_int},
843 {CV_ARM_R0 + 4, "r4", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R4), dbg_itype_unsigned_int},
844 {CV_ARM_R0 + 5, "r5", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R5), dbg_itype_unsigned_int},
845 {CV_ARM_R0 + 6, "r6", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R6), dbg_itype_unsigned_int},
846 {CV_ARM_R0 + 7, "r7", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R7), dbg_itype_unsigned_int},
847 {CV_ARM_R0 + 8, "r8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_int},
848 {CV_ARM_R0 + 9, "r9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_int},
849 {CV_ARM_R0 + 10, "r10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_int},
850 {CV_ARM_R0 + 11, "r11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Fp), dbg_itype_unsigned_int},
851 {CV_ARM_R0 + 12, "r12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Ip), dbg_itype_unsigned_int},
852 {CV_ARM_SP, "sp", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Sp), dbg_itype_unsigned_int},
853 {CV_ARM_LR, "lr", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Lr), dbg_itype_unsigned_int},
854 {CV_ARM_PC, "pc", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Pc), dbg_itype_unsigned_int},
855 {CV_ARM_CPSR, "cpsr", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Cpsr), dbg_itype_unsigned_int},
856 {0, NULL, 0, dbg_itype_none}
859 static unsigned be_arm_is_step_over_insn(const void* insn)
861 dbg_printf("be_arm_is_step_over_insn: not done\n");
862 return FALSE;
865 static unsigned be_arm_is_function_return(const void* insn)
867 dbg_printf("be_arm_is_function_return: not done\n");
868 return FALSE;
871 static unsigned be_arm_is_break_insn(const void* insn)
873 dbg_printf("be_arm_is_break_insn: not done\n");
874 return FALSE;
877 static unsigned be_arm_is_func_call(const void* insn, ADDRESS64* callee)
879 return FALSE;
882 static unsigned be_arm_is_jump(const void* insn, ADDRESS64* jumpee)
884 return FALSE;
887 static unsigned be_arm_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
888 CONTEXT* ctx, enum be_xpoint_type type,
889 void* addr, unsigned long* val, unsigned size)
891 SIZE_T sz;
893 switch (type)
895 case be_xpoint_break:
896 if (!size) return 0;
897 if (!pio->read(hProcess, addr, val, 4, &sz) || sz != 4) return 0;
898 default:
899 dbg_printf("Unknown/unsupported bp type %c\n", type);
900 return 0;
902 return 1;
905 static unsigned be_arm_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
906 CONTEXT* ctx, enum be_xpoint_type type,
907 void* addr, unsigned long val, unsigned size)
909 SIZE_T sz;
911 switch (type)
913 case be_xpoint_break:
914 if (!size) return 0;
915 if (!pio->write(hProcess, addr, &val, 4, &sz) || sz == 4) return 0;
916 break;
917 default:
918 dbg_printf("Unknown/unsupported bp type %c\n", type);
919 return 0;
921 return 1;
924 static unsigned be_arm_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
926 dbg_printf("be_arm_is_watchpoint_set: not done\n");
927 return FALSE;
930 static void be_arm_clear_watchpoint(CONTEXT* ctx, unsigned idx)
932 dbg_printf("be_arm_clear_watchpoint: not done\n");
935 static int be_arm_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
937 INT step = (ctx->Cpsr & 0x20) ? 2 : 4;
939 if (way)
941 ctx->Pc -= step;
942 return -step;
944 ctx->Pc += step;
945 return step;
948 static int be_arm_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
949 unsigned ext_sign, LONGLONG* ret)
951 if (size != 1 && size != 2 && size != 4 && size != 8) return FALSE;
953 memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
954 /* FIXME: this assumes that debuggee and debugger use the same
955 * integral representation
957 if (!memory_read_value(lvalue, size, ret)) return FALSE;
959 /* propagate sign information */
960 if (ext_sign && size < 8 && (*ret >> (size * 8 - 1)) != 0)
962 ULONGLONG neg = -1;
963 *ret |= neg << (size * 8);
965 return TRUE;
968 static int be_arm_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
969 long double* ret)
971 char tmp[sizeof(long double)];
973 /* FIXME: this assumes that debuggee and debugger use the same
974 * representation for reals
976 if (!memory_read_value(lvalue, size, tmp)) return FALSE;
978 switch (size)
980 case sizeof(float): *ret = *(float*)tmp; break;
981 case sizeof(double): *ret = *(double*)tmp; break;
982 default: return FALSE;
984 return TRUE;
987 static int be_arm_store_integer(const struct dbg_lvalue* lvalue, unsigned size,
988 unsigned is_signed, LONGLONG val)
990 /* this is simple if we're on a little endian CPU */
991 return memory_write_value(lvalue, size, &val);
994 struct backend_cpu be_arm =
996 IMAGE_FILE_MACHINE_ARMV7,
998 be_cpu_linearize,
999 be_cpu_build_addr,
1000 be_arm_get_addr,
1001 be_arm_get_register_info,
1002 be_arm_single_step,
1003 be_arm_print_context,
1004 be_arm_print_segment_info,
1005 be_arm_ctx,
1006 be_arm_is_step_over_insn,
1007 be_arm_is_function_return,
1008 be_arm_is_break_insn,
1009 be_arm_is_func_call,
1010 be_arm_is_jump,
1011 be_arm_disasm_one_insn,
1012 be_arm_insert_Xpoint,
1013 be_arm_remove_Xpoint,
1014 be_arm_is_watchpoint_set,
1015 be_arm_clear_watchpoint,
1016 be_arm_adjust_pc_for_break,
1017 be_arm_fetch_integer,
1018 be_arm_fetch_float,
1019 be_arm_store_integer,
1021 #endif