programs/winedbg/be_arm.c

   1 /*
   2  * Debugger ARM specific functions
   3  *
   4  * Copyright 2000-2003 Marcus Meissner
   5  *                2004 Eric Pouech
   6  *           2010-2012 André Hentschel
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2.1 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
  21  */
  22
  23 #include "debugger.h"
  24
  25 #if defined(__arm__) && !defined(__ARMEB__)
  26
  27 /*
  28  * Switch to disassemble Thumb code.
  29  */
  30 static BOOL db_disasm_thumb = FALSE;
  31
  32 /*
  33  * Flag to indicate whether we need to display instruction,
  34  * or whether we just need to know the address of the next
  35  * instruction.
  36  */
  37 static BOOL db_display = FALSE;
  38
  39 #define ARM_INSN_SIZE    4
  40 #define THUMB_INSN_SIZE  2
  41
  42 #define ROR32(n, r) (((n) >> (r)) | ((n) << (32 - (r))))
  43
  44 #define get_cond(ins)           tbl_cond[(ins >> 28) & 0x0f]
  45 #define get_nibble(ins, num)    ((ins >> (num * 4)) & 0x0f)
  46
  47 static char const tbl_regs[][4] = {
  48     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
  49     "fp", "ip", "sp", "lr", "pc", "cpsr"
  50 };
  51
  52 static char const tbl_addrmode[][3] = {
  53     "da", "ia", "db", "ib"
  54 };
  55
  56 static char const tbl_cond[][3] = {
  57     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", ""
  58 };
  59
  60 static char const tbl_dataops[][4] = {
  61     "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", "tst", "teq", "cmp", "cmn", "orr",
  62     "mov", "bic", "mvn"
  63 };
  64
  65 static char const tbl_shifts[][4] = {
  66     "lsl", "lsr", "asr", "ror"
  67 };
  68
  69 static char const tbl_hiops_t[][4] = {
  70 "add", "cmp", "mov", "bx"
  71 };
  72
  73 static char const tbl_aluops_t[][4] = {
  74     "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", "tst", "neg", "cmp", "cmn", "orr",
  75     "mul", "bic", "mvn"
  76 };
  77
  78 static char const tbl_immops_t[][4] = {
  79 "mov", "cmp", "add", "sub"
  80 };
  81
  82 static UINT db_get_inst(void* addr, int size)
  83 {
  84     UINT result = 0;
  85     char buffer[4];
  86
  87     if (dbg_read_memory(addr, buffer, size))
  88     {
  89         switch (size)
  90         {
  91         case 4:
  92             result = *(UINT*)buffer;
  93             break;
  94         case 2:
  95             result = *(WORD*)buffer;
  96             break;
  97         }
  98     }
  99     return result;
 100 }
 101
 102 static UINT arm_disasm_branch(UINT inst)
 103 {
 104     short link = (inst >> 24) & 0x01;
 105     int offset = (inst << 2) & 0x03ffffff;
 106
 107     if (offset & 0x02000000) offset |= 0xfc000000;
 108     offset += 8;
 109
 110     dbg_printf("\n\tb%s%s\t#%d", link ? "l" : "", get_cond(inst), offset);
 111     return 0;
 112 }
 113
 114 static UINT arm_disasm_branchreg(UINT inst)
 115 {
 116     dbg_printf("\n\tb%s\t%s", get_cond(inst), tbl_regs[get_nibble(inst, 0)]);
 117     return 0;
 118 }
 119
 120 static UINT arm_disasm_dataprocessing(UINT inst)
 121 {
 122     short condcodes = (inst >> 20) & 0x01;
 123     short opcode    = (inst >> 21) & 0x0f;
 124     short immediate = (inst >> 25) & 0x01;
 125     short no_op1    = (opcode & 0x0d) == 0x0d;
 126     short no_dst    = (opcode & 0x0c) == 0x08;
 127
 128     /* check for nop */
 129     if (get_nibble(inst, 3) == 15 /* r15 */ && condcodes == 0 &&
 130         opcode >= 8 /* tst */ && opcode <= 11 /* cmn */)
 131     {
 132         dbg_printf("\n\tnop");
 133         return 0;
 134     }
 135
 136     dbg_printf("\n\t%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond(inst));
 137     if (!no_dst) dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
 138     else dbg_printf("\t");
 139
 140     if (no_op1)
 141     {
 142         if (immediate)
 143             dbg_printf("#%u", ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
 144         else
 145             dbg_printf("%s", tbl_regs[get_nibble(inst, 0)]);
 146     }
 147     else
 148     {
 149         if (immediate)
 150             dbg_printf("%s, #%u", tbl_regs[get_nibble(inst, 4)],
 151                        ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
 152         else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
 153             dbg_printf("%s, %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
 154         else if (((inst >> 4) & 0x09) == 0x01) /* register shift */
 155             dbg_printf("%s, %s, %s %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
 156                        tbl_shifts[(inst >> 5) & 0x03], tbl_regs[(inst >> 8) & 0x0f]);
 157         else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift */
 158             dbg_printf("%s, %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
 159                        tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
 160         else
 161             return inst;
 162     }
 163     return 0;
 164 }
 165
 166 static UINT arm_disasm_singletrans(UINT inst)
 167 {
 168     short load      = (inst >> 20) & 0x01;
 169     short writeback = (inst >> 21) & 0x01;
 170     short byte      = (inst >> 22) & 0x01;
 171     short direction = (inst >> 23) & 0x01;
 172     short indexing  = (inst >> 24) & 0x01;
 173     short immediate = !((inst >> 25) & 0x01);
 174     short offset    = inst & 0x0fff;
 175
 176     if (!direction) offset *= -1;
 177
 178     dbg_printf("\n\t%s%s%s%s", load ? "ldr" : "str", byte ? "b" : "", writeback ? "t" : "",
 179                get_cond(inst));
 180     dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
 181     if (indexing)
 182     {
 183         if (immediate)
 184             dbg_printf("[%s, #%d]", tbl_regs[get_nibble(inst, 4)], offset);
 185         else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
 186             dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
 187         else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
 188             dbg_printf("[%s, %s, %s #%d]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
 189                        tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
 190         else
 191             return inst;
 192     }
 193     else
 194     {
 195         if (immediate)
 196             dbg_printf("[%s], #%d", tbl_regs[get_nibble(inst, 4)], offset);
 197         else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
 198             dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
 199         else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
 200             dbg_printf("[%s], %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
 201                        tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
 202         else
 203             return inst;
 204     }
 205     return 0;
 206 }
 207
 208 static UINT arm_disasm_halfwordtrans(UINT inst)
 209 {
 210     short halfword  = (inst >> 5)  & 0x01;
 211     short sign      = (inst >> 6)  & 0x01;
 212     short load      = (inst >> 20) & 0x01;
 213     short writeback = (inst >> 21) & 0x01;
 214     short immediate = (inst >> 22) & 0x01;
 215     short direction = (inst >> 23) & 0x01;
 216     short indexing  = (inst >> 24) & 0x01;
 217     short offset    = ((inst >> 4) & 0xf0) + (inst & 0x0f);
 218
 219     if (!direction) offset *= -1;
 220
 221     dbg_printf("\n\t%s%s%s%s%s", load ? "ldr" : "str", sign ? "s" : "",
 222                halfword ? "h" : (sign ? "b" : ""), writeback ? "t" : "", get_cond(inst));
 223     dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
 224     if (indexing)
 225     {
 226         if (immediate)
 227             dbg_printf("[%s, #%d]", tbl_regs[get_nibble(inst, 4)], offset);
 228         else
 229             dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
 230     }
 231     else
 232     {
 233         if (immediate)
 234             dbg_printf("[%s], #%d", tbl_regs[get_nibble(inst, 4)], offset);
 235         else
 236             dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
 237     }
 238     return 0;
 239 }
 240
 241 static UINT arm_disasm_blocktrans(UINT inst)
 242 {
 243     short load      = (inst >> 20) & 0x01;
 244     short writeback = (inst >> 21) & 0x01;
 245     short psr       = (inst >> 22) & 0x01;
 246     short addrmode  = (inst >> 23) & 0x03;
 247     short i;
 248     short last=15;
 249     for (i=15;i>=0;i--)
 250         if ((inst>>i) & 1)
 251         {
 252             last = i;
 253             break;
 254         }
 255
 256     dbg_printf("\n\t%s%s%s\t%s%s, {", load ? "ldm" : "stm", tbl_addrmode[addrmode], get_cond(inst),
 257                tbl_regs[get_nibble(inst, 4)], writeback ? "!" : "");
 258     for (i=0;i<=15;i++)
 259         if ((inst>>i) & 1)
 260         {
 261             if (i == last) dbg_printf("%s", tbl_regs[i]);
 262             else dbg_printf("%s, ", tbl_regs[i]);
 263         }
 264     dbg_printf("}%s", psr ? "^" : "");
 265     return 0;
 266 }
 267
 268 static UINT arm_disasm_swi(UINT inst)
 269 {
 270     UINT comment = inst & 0x00ffffff;
 271     dbg_printf("\n\tswi%s\t#%d", get_cond(inst), comment);
 272     return 0;
 273 }
 274
 275 static UINT arm_disasm_coproctrans(UINT inst)
 276 {
 277     WORD CRm    = inst & 0x0f;
 278     WORD CP     = (inst >> 5)  & 0x07;
 279     WORD CPnum  = (inst >> 8)  & 0x0f;
 280     WORD CRn    = (inst >> 16) & 0x0f;
 281     WORD load   = (inst >> 20) & 0x01;
 282     WORD CP_Opc = (inst >> 21) & 0x07;
 283
 284     dbg_printf("\n\t%s%s\t%u, %u, %s, cr%u, cr%u, {%u}", load ? "mrc" : "mcr", get_cond(inst), CPnum,
 285                CP, tbl_regs[get_nibble(inst, 3)], CRn, CRm, CP_Opc);
 286     return 0;
 287 }
 288
 289 static UINT arm_disasm_coprocdataop(UINT inst)
 290 {
 291     WORD CRm    = inst & 0x0f;
 292     WORD CP     = (inst >> 5)  & 0x07;
 293     WORD CPnum  = (inst >> 8)  & 0x0f;
 294     WORD CRd    = (inst >> 12) & 0x0f;
 295     WORD CRn    = (inst >> 16) & 0x0f;
 296     WORD CP_Opc = (inst >> 20) & 0x0f;
 297
 298     dbg_printf("\n\tcdp%s\t%u, %u, cr%u, cr%u, cr%u, {%u}", get_cond(inst),
 299                CPnum, CP, CRd, CRn, CRm, CP_Opc);
 300     return 0;
 301 }
 302
 303 static UINT arm_disasm_coprocdatatrans(UINT inst)
 304 {
 305     WORD CPnum  = (inst >> 8)  & 0x0f;
 306     WORD CRd    = (inst >> 12) & 0x0f;
 307     WORD load      = (inst >> 20) & 0x01;
 308     WORD writeback = (inst >> 21) & 0x01;
 309     WORD translen  = (inst >> 22) & 0x01;
 310     WORD direction = (inst >> 23) & 0x01;
 311     WORD indexing  = (inst >> 24) & 0x01;
 312     short offset    = (inst & 0xff) << 2;
 313
 314     if (!direction) offset *= -1;
 315
 316     dbg_printf("\n\t%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond(inst));
 317     if (indexing)
 318         dbg_printf("\t%u, cr%u, [%s, #%d]%s", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], offset, writeback?"!":"");
 319     else
 320         dbg_printf("\t%u, cr%u, [%s], #%d", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], offset);
 321     return 0;
 322 }
 323
 324 static WORD thumb_disasm_hireg(WORD inst, ADDRESS64 *addr)
 325 {
 326     short dst = inst & 0x07;
 327     short src = (inst >> 3) & 0x07;
 328     short h2  = (inst >> 6) & 0x01;
 329     short h1  = (inst >> 7) & 0x01;
 330     short op  = (inst >> 8) & 0x03;
 331
 332     if (h1) dst += 8;
 333     if (h2) src += 8;
 334
 335     if (op == 2 && dst == src) /* mov rx, rx */
 336     {
 337         dbg_printf("\n\tnop");
 338         return 0;
 339     }
 340
 341     if (op == 3)
 342         dbg_printf("\n\tb%sx\t%s", h1?"l":"", tbl_regs[src]);
 343     else
 344         dbg_printf("\n\t%s\t%s, %s", tbl_hiops_t[op], tbl_regs[dst], tbl_regs[src]);
 345
 346     return 0;
 347 }
 348
 349 static WORD thumb_disasm_aluop(WORD inst, ADDRESS64 *addr)
 350 {
 351     short dst = inst & 0x07;
 352     short src = (inst >> 3) & 0x07;
 353     short op  = (inst >> 6) & 0x0f;
 354
 355     dbg_printf("\n\t%s\t%s, %s", tbl_aluops_t[op], tbl_regs[dst], tbl_regs[src]);
 356
 357     return 0;
 358 }
 359
 360 static WORD thumb_disasm_blocktrans(WORD inst, ADDRESS64 *addr)
 361 {
 362     short lrpc = (inst >> 8)  & 0x01;
 363     short load = (inst >> 11) & 0x01;
 364     short i;
 365     short last;
 366
 367     for (i=7;i>=0;i--)
 368         if ((inst>>i) & 1) break;
 369     last = i;
 370
 371     dbg_printf("\n\t%s\t{", load ? "pop" : "push");
 372
 373     for (i=0;i<=7;i++)
 374         if ((inst>>i) & 1)
 375         {
 376             if (i == last) dbg_printf("%s", tbl_regs[i]);
 377             else dbg_printf("%s, ", tbl_regs[i]);
 378         }
 379     if (lrpc)
 380         dbg_printf(", %s", load ? "pc" : "lr");
 381
 382     dbg_printf("}");
 383     return 0;
 384 }
 385
 386 static WORD thumb_disasm_longbl(WORD inst, ADDRESS64 *addr)
 387 {
 388     WORD inst2;
 389     UINT offset = (inst & 0x07ff) << 12;
 390
 391     addr->Offset += 2;
 392     inst2 = db_get_inst( memory_to_linear_addr(addr), 2 );
 393     if (!((inst2 & 0xf800) == 0xf800)) return inst;
 394
 395     offset += (inst2 & 0x07ff) << 1;
 396     dbg_printf("\n\tbl\t%08x", offset);
 397     return 0;
 398 }
 399
 400 static WORD thumb_disasm_condbranch(WORD inst, ADDRESS64 *addr)
 401 {
 402     WORD offset = inst & 0x00ff;
 403     dbg_printf("\n\tb%s\t%04x", tbl_cond[(inst >> 8) & 0x0f], offset);
 404     return 0;
 405 }
 406
 407 static WORD thumb_disasm_loadadr(WORD inst, ADDRESS64 *addr)
 408 {
 409     WORD src = (inst >> 11) & 0x01;
 410     WORD offset = (inst & 0xff) << 2;
 411
 412     dbg_printf("\n\tadd\t%s, %s, #%d", tbl_regs[(inst >> 8) & 0x07], src ? "sp" : "pc", offset);
 413     return 0;
 414 }
 415
 416 static WORD thumb_disasm_swi(WORD inst, ADDRESS64 *addr)
 417 {
 418     WORD comment = inst & 0x00ff;
 419     dbg_printf("\n\tswi\t#%d", comment);
 420     return 0;
 421 }
 422
 423 static WORD thumb_disasm_nop(WORD inst, ADDRESS64 *addr)
 424 {
 425     dbg_printf("\n\tnop");
 426     return 0;
 427 }
 428
 429 static WORD thumb_disasm_ldrpcrel(WORD inst, ADDRESS64 *addr)
 430 {
 431     WORD offset = (inst & 0xff) << 2;
 432     dbg_printf("\n\tldr\t%s, [pc, #%u]", tbl_regs[(inst >> 8) & 0x07], offset);
 433     return 0;
 434 }
 435
 436 static WORD thumb_disasm_ldrsprel(WORD inst, ADDRESS64 *addr)
 437 {
 438     WORD offset = (inst & 0xff) << 2;
 439     dbg_printf("\n\t%s\t%s, [sp, #%u]", (inst & 0x0800)?"ldr":"str", tbl_regs[(inst >> 8) & 0x07], offset);
 440     return 0;
 441 }
 442
 443 static WORD thumb_disasm_addsprel(WORD inst, ADDRESS64 *addr)
 444 {
 445     WORD offset = (inst & 0x7f) << 2;
 446     if ((inst >> 7) & 0x01)
 447         dbg_printf("\n\tsub\tsp, sp, #%u", offset);
 448     else
 449         dbg_printf("\n\tadd\tsp, sp, #%u", offset);
 450     return 0;
 451 }
 452
 453 static WORD thumb_disasm_ldrimm(WORD inst, ADDRESS64 *addr)
 454 {
 455     WORD offset = (inst & 0x07c0) >> 6;
 456     dbg_printf("\n\t%s%s\t%s, [%s, #%u]", (inst & 0x0800)?"ldr":"str", (inst & 0x1000)?"b":"",
 457                tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst & 0x1000)?offset:(offset << 2));
 458     return 0;
 459 }
 460
 461 static WORD thumb_disasm_immop(WORD inst, ADDRESS64 *addr)
 462 {
 463     WORD op = (inst >> 11) & 0x03;
 464     dbg_printf("\n\t%s\t%s, #%u", tbl_immops_t[op], tbl_regs[(inst >> 8) & 0x07], inst & 0xff);
 465     return 0;
 466 }
 467
 468 static WORD thumb_disasm_addsub(WORD inst, ADDRESS64 *addr)
 469 {
 470     WORD op = (inst >> 9) & 0x01;
 471     WORD immediate = (inst >> 10) & 0x01;
 472
 473     dbg_printf("\n\t%s\t%s, %s, ", op ? "sub" : "add",
 474                tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07]);
 475     if (immediate)
 476         dbg_printf("#%d", (inst >> 6) & 0x07);
 477     else
 478         dbg_printf("%s", tbl_regs[(inst >> 6) & 0x07]);
 479     return 0;
 480 }
 481
 482 static WORD thumb_disasm_movshift(WORD inst, ADDRESS64 *addr)
 483 {
 484     WORD op = (inst >> 11) & 0x03;
 485     dbg_printf("\n\t%s\t%s, %s, #%u", tbl_shifts[op],
 486                tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst >> 6) & 0x1f);
 487     return 0;
 488 }
 489
 490 struct inst_arm
 491 {
 492         UINT mask;
 493         UINT pattern;
 494         UINT (*func)(UINT);
 495 };
 496
 497 static const struct inst_arm tbl_arm[] = {
 498     { 0x0e000000, 0x0a000000, arm_disasm_branch },
 499     { 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
 500     { 0x0fffff00, 0x012fff00, arm_disasm_branchreg },
 501     { 0x0c000000, 0x00000000, arm_disasm_dataprocessing },
 502     { 0x0c000000, 0x04000000, arm_disasm_singletrans },
 503     { 0x0e000000, 0x08000000, arm_disasm_blocktrans },
 504     { 0x0f000000, 0x0f000000, arm_disasm_swi },
 505     { 0x0f000010, 0x0e000010, arm_disasm_coproctrans },
 506     { 0x0f000010, 0x0e000000, arm_disasm_coprocdataop },
 507     { 0x0e000000, 0x0c000000, arm_disasm_coprocdatatrans },
 508     { 0x00000000, 0x00000000, NULL }
 509 };
 510
 511 struct inst_thumb16
 512 {
 513         WORD mask;
 514         WORD pattern;
 515         WORD (*func)(WORD, ADDRESS64*);
 516 };
 517
 518 static const struct inst_thumb16 tbl_thumb16[] = {
 519     { 0xfc00, 0x4400, thumb_disasm_hireg },
 520     { 0xfc00, 0x4000, thumb_disasm_aluop },
 521     { 0xf600, 0xb400, thumb_disasm_blocktrans },
 522     { 0xf800, 0xf000, thumb_disasm_longbl },
 523     { 0xf000, 0xd000, thumb_disasm_condbranch },
 524     { 0xf000, 0xa000, thumb_disasm_loadadr },
 525     { 0xf800, 0x4800, thumb_disasm_ldrpcrel },
 526     { 0xf000, 0x9000, thumb_disasm_ldrsprel },
 527     { 0xff00, 0xb000, thumb_disasm_addsprel },
 528     { 0xe000, 0x6000, thumb_disasm_ldrimm },
 529     { 0xe000, 0x2000, thumb_disasm_immop },
 530     { 0xf000, 0xd000, thumb_disasm_condbranch },
 531     { 0xff00, 0xdf00, thumb_disasm_swi },
 532     { 0xff00, 0xbf00, thumb_disasm_nop },
 533     { 0xf800, 0x1800, thumb_disasm_addsub },
 534     { 0xe000, 0x0000, thumb_disasm_movshift },
 535     { 0x0000, 0x0000, NULL }
 536 };
 537
 538 /***********************************************************************
 539  *              disasm_one_insn
 540  *
 541  * Disassemble instruction at 'addr'. addr is changed to point to the
 542  * start of the next instruction.
 543  */
 544 void be_arm_disasm_one_insn(ADDRESS64 *addr, int display)
 545 {
 546     struct inst_arm *a_ptr = (struct inst_arm *)&tbl_arm;
 547     struct inst_thumb16 *t_ptr = (struct inst_thumb16 *)&tbl_thumb16;
 548     UINT inst;
 549     WORD tinst;
 550     int size;
 551     int matched = 0;
 552
 553     char tmp[64];
 554     DWORD_PTR* pval;
 555
 556     if (!memory_get_register(CV_ARM_CPSR, &pval, tmp, sizeof(tmp)))
 557         dbg_printf("\n\tmemory_get_register failed: %s", tmp);
 558     else
 559         db_disasm_thumb=(*pval & 0x20)?TRUE:FALSE;
 560
 561     if (db_disasm_thumb) size = THUMB_INSN_SIZE;
 562     else size = ARM_INSN_SIZE;
 563
 564     db_display = display;
 565     inst = db_get_inst( memory_to_linear_addr(addr), size );
 566
 567     if (!db_disasm_thumb)
 568     {
 569         while (a_ptr->func) {
 570                 if ((inst & a_ptr->mask) ==  a_ptr->pattern) {
 571                         matched = 1;
 572                         break;
 573                 }
 574                 a_ptr++;
 575         }
 576
 577         if (!matched) {
 578                 dbg_printf("\n\tUnknown Instruction: %08x", inst);
 579                 addr->Offset += size;
 580                 return;
 581         }
 582         else
 583         {
 584             if (!a_ptr->func(inst))
 585                 addr->Offset += size;
 586             return;
 587         }
 588     }
 589     else
 590     {
 591         tinst = inst;
 592         while (t_ptr->func) {
 593                 if ((tinst & t_ptr->mask) ==  t_ptr->pattern) {
 594                         matched = 1;
 595                         break;
 596                 }
 597                 t_ptr++;
 598         }
 599
 600         if (!matched) {
 601                 dbg_printf("\n\tUnknown Instruction: %04x", tinst);
 602                 addr->Offset += size;
 603                 return;
 604         }
 605         else
 606         {
 607             if (!t_ptr->func(tinst, addr))
 608                 addr->Offset += size;
 609         }
 610         return;
 611     }
 612 }
 613
 614 static unsigned be_arm_get_addr(HANDLE hThread, const CONTEXT* ctx,
 615                                 enum be_cpu_addr bca, ADDRESS64* addr)
 616 {
 617     switch (bca)
 618     {
 619     case be_cpu_addr_pc:
 620         return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Pc);
 621     case be_cpu_addr_stack:
 622         return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Sp);
 623     case be_cpu_addr_frame:
 624         return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Fp);
 625     }
 626     return FALSE;
 627 }
 628
 629 static unsigned be_arm_get_register_info(int regno, enum be_cpu_addr* kind)
 630 {
 631     switch (regno)
 632     {
 633     case CV_ARM_PC:  *kind = be_cpu_addr_pc; return TRUE;
 634     case CV_ARM_R0 + 11: *kind = be_cpu_addr_frame; return TRUE;
 635     case CV_ARM_SP:  *kind = be_cpu_addr_stack; return TRUE;
 636     }
 637     return FALSE;
 638 }
 639
 640 static void be_arm_single_step(CONTEXT* ctx, unsigned enable)
 641 {
 642     dbg_printf("be_arm_single_step: not done\n");
 643 }
 644
 645 static void be_arm_print_context(HANDLE hThread, const CONTEXT* ctx, int all_regs)
 646 {
 647     static const char condflags[] = "NZCV";
 648     int i;
 649     char        buf[8];
 650
 651     switch (ctx->Cpsr & 0x1F)
 652     {
 653     case 0:  strcpy(buf, "User26"); break;
 654     case 1:  strcpy(buf, "FIQ26"); break;
 655     case 2:  strcpy(buf, "IRQ26"); break;
 656     case 3:  strcpy(buf, "SVC26"); break;
 657     case 16: strcpy(buf, "User"); break;
 658     case 17: strcpy(buf, "FIQ"); break;
 659     case 18: strcpy(buf, "IRQ"); break;
 660     case 19: strcpy(buf, "SVC"); break;
 661     case 23: strcpy(buf, "ABT"); break;
 662     case 27: strcpy(buf, "UND"); break;
 663     default: strcpy(buf, "UNKNWN"); break;
 664     }
 665
 666     dbg_printf("Register dump:\n");
 667     dbg_printf("%s %s Mode\n", (ctx->Cpsr & 0x20) ? "Thumb" : "ARM", buf);
 668
 669     strcpy(buf, condflags);
 670     for (i = 0; buf[i]; i++)
 671         if (!((ctx->Cpsr >> 26) & (1 << (sizeof(condflags) - i))))
 672             buf[i] = '-';
 673
 674     dbg_printf(" Pc:%04x Sp:%04x Lr:%04x Cpsr:%04x(%s)\n",
 675                ctx->Pc, ctx->Sp, ctx->Lr, ctx->Cpsr, buf);
 676     dbg_printf(" r0:%04x r1:%04x r2:%04x r3:%04x\n",
 677                ctx->R0, ctx->R1, ctx->R2, ctx->R3);
 678     dbg_printf(" r4:%04x r5:%04x  r6:%04x  r7:%04x r8:%04x\n",
 679                ctx->R4, ctx->R5, ctx->R6, ctx->R7, ctx->R8 );
 680     dbg_printf(" r9:%04x r10:%04x Fp:%04x Ip:%04x\n",
 681                ctx->R9, ctx->R10, ctx->Fp, ctx->Ip );
 682
 683     if (all_regs) dbg_printf( "Floating point ARM dump not implemented\n" );
 684 }
 685
 686 static void be_arm_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
 687 {
 688 }
 689
 690 static struct dbg_internal_var be_arm_ctx[] =
 691 {
 692     {CV_ARM_R0 +  0,    "r0",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R0),     dbg_itype_unsigned_int},
 693     {CV_ARM_R0 +  1,    "r1",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R1),     dbg_itype_unsigned_int},
 694     {CV_ARM_R0 +  2,    "r2",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R2),     dbg_itype_unsigned_int},
 695     {CV_ARM_R0 +  3,    "r3",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R3),     dbg_itype_unsigned_int},
 696     {CV_ARM_R0 +  4,    "r4",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R4),     dbg_itype_unsigned_int},
 697     {CV_ARM_R0 +  5,    "r5",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R5),     dbg_itype_unsigned_int},
 698     {CV_ARM_R0 +  6,    "r6",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R6),     dbg_itype_unsigned_int},
 699     {CV_ARM_R0 +  7,    "r7",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R7),     dbg_itype_unsigned_int},
 700     {CV_ARM_R0 +  8,    "r8",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8),     dbg_itype_unsigned_int},
 701     {CV_ARM_R0 +  9,    "r9",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9),     dbg_itype_unsigned_int},
 702     {CV_ARM_R0 +  10,   "r10",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10),    dbg_itype_unsigned_int},
 703     {CV_ARM_R0 +  11,   "r11",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Fp),     dbg_itype_unsigned_int},
 704     {CV_ARM_R0 +  12,   "r12",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Ip),     dbg_itype_unsigned_int},
 705     {CV_ARM_SP,         "sp",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Sp),     dbg_itype_unsigned_int},
 706     {CV_ARM_LR,         "lr",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Lr),     dbg_itype_unsigned_int},
 707     {CV_ARM_PC,         "pc",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Pc),     dbg_itype_unsigned_int},
 708     {CV_ARM_CPSR,       "cpsr",         (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Cpsr),   dbg_itype_unsigned_int},
 709     {0,                 NULL,           0,                                         dbg_itype_none}
 710 };
 711
 712 static unsigned be_arm_is_step_over_insn(const void* insn)
 713 {
 714     dbg_printf("be_arm_is_step_over_insn: not done\n");
 715     return FALSE;
 716 }
 717
 718 static unsigned be_arm_is_function_return(const void* insn)
 719 {
 720     dbg_printf("be_arm_is_function_return: not done\n");
 721     return FALSE;
 722 }
 723
 724 static unsigned be_arm_is_break_insn(const void* insn)
 725 {
 726     dbg_printf("be_arm_is_break_insn: not done\n");
 727     return FALSE;
 728 }
 729
 730 static unsigned be_arm_is_func_call(const void* insn, ADDRESS64* callee)
 731 {
 732     return FALSE;
 733 }
 734
 735 static unsigned be_arm_is_jump(const void* insn, ADDRESS64* jumpee)
 736 {
 737     return FALSE;
 738 }
 739
 740 static unsigned be_arm_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
 741                                      CONTEXT* ctx, enum be_xpoint_type type,
 742                                      void* addr, unsigned long* val, unsigned size)
 743 {
 744     SIZE_T              sz;
 745
 746     switch (type)
 747     {
 748     case be_xpoint_break:
 749         if (!size) return 0;
 750         if (!pio->read(hProcess, addr, val, 4, &sz) || sz != 4) return 0;
 751     default:
 752         dbg_printf("Unknown/unsupported bp type %c\n", type);
 753         return 0;
 754     }
 755     return 1;
 756 }
 757
 758 static unsigned be_arm_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
 759                                      CONTEXT* ctx, enum be_xpoint_type type,
 760                                      void* addr, unsigned long val, unsigned size)
 761 {
 762     SIZE_T              sz;
 763
 764     switch (type)
 765     {
 766     case be_xpoint_break:
 767         if (!size) return 0;
 768         if (!pio->write(hProcess, addr, &val, 4, &sz) || sz == 4) return 0;
 769         break;
 770     default:
 771         dbg_printf("Unknown/unsupported bp type %c\n", type);
 772         return 0;
 773     }
 774     return 1;
 775 }
 776
 777 static unsigned be_arm_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
 778 {
 779     dbg_printf("be_arm_is_watchpoint_set: not done\n");
 780     return FALSE;
 781 }
 782
 783 static void be_arm_clear_watchpoint(CONTEXT* ctx, unsigned idx)
 784 {
 785     dbg_printf("be_arm_clear_watchpoint: not done\n");
 786 }
 787
 788 static int be_arm_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
 789 {
 790     INT step = (ctx->Cpsr & 0x20) ? 2 : 4;
 791
 792     if (way)
 793     {
 794         ctx->Pc -= step;
 795         return -step;
 796     }
 797     ctx->Pc += step;
 798     return step;
 799 }
 800
 801 static int be_arm_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
 802                                 unsigned ext_sign, LONGLONG* ret)
 803 {
 804     if (size != 1 && size != 2 && size != 4 && size != 8) return FALSE;
 805
 806     memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
 807     /* FIXME: this assumes that debuggee and debugger use the same
 808      * integral representation
 809      */
 810     if (!memory_read_value(lvalue, size, ret)) return FALSE;
 811
 812     /* propagate sign information */
 813     if (ext_sign && size < 8 && (*ret >> (size * 8 - 1)) != 0)
 814     {
 815         ULONGLONG neg = -1;
 816         *ret |= neg << (size * 8);
 817     }
 818     return TRUE;
 819 }
 820
 821 static int be_arm_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
 822                               long double* ret)
 823 {
 824     char        tmp[sizeof(long double)];
 825
 826     /* FIXME: this assumes that debuggee and debugger use the same
 827      * representation for reals
 828      */
 829     if (!memory_read_value(lvalue, size, tmp)) return FALSE;
 830
 831     switch (size)
 832     {
 833     case sizeof(float):         *ret = *(float*)tmp;            break;
 834     case sizeof(double):        *ret = *(double*)tmp;           break;
 835     default:                    return FALSE;
 836     }
 837     return TRUE;
 838 }
 839
 840 static int be_arm_store_integer(const struct dbg_lvalue* lvalue, unsigned size,
 841                                 unsigned is_signed, LONGLONG val)
 842 {
 843     /* this is simple if we're on a little endian CPU */
 844     return memory_write_value(lvalue, size, &val);
 845 }
 846
 847 struct backend_cpu be_arm =
 848 {
 849     IMAGE_FILE_MACHINE_ARMV7,
 850     4,
 851     be_cpu_linearize,
 852     be_cpu_build_addr,
 853     be_arm_get_addr,
 854     be_arm_get_register_info,
 855     be_arm_single_step,
 856     be_arm_print_context,
 857     be_arm_print_segment_info,
 858     be_arm_ctx,
 859     be_arm_is_step_over_insn,
 860     be_arm_is_function_return,
 861     be_arm_is_break_insn,
 862     be_arm_is_func_call,
 863     be_arm_is_jump,
 864     be_arm_disasm_one_insn,
 865     be_arm_insert_Xpoint,
 866     be_arm_remove_Xpoint,
 867     be_arm_is_watchpoint_set,
 868     be_arm_clear_watchpoint,
 869     be_arm_adjust_pc_for_break,
 870     be_arm_fetch_integer,
 871     be_arm_fetch_float,
 872     be_arm_store_integer,
 873 };
 874 #endif