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push 87b6981010d7405c33b14cddcceec21b47729eba
[wine/hacks.git] / programs / winedbg / be_x86_64.c
blob682bd05ae0549f1aa9a5de71225a76d5feb16441
1 /*
2 * Debugger x86_64 specific functions
3 *
4 * Copyright 2004 Vincent Béron
5 * Copyright 2009 Eric Pouech
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20 */
21
22 #include "debugger.h"
23 #include "wine/debug.h"
24
25 WINE_DEFAULT_DEBUG_CHANNEL(winedbg);
26
27 #if defined(__x86_64__)
28
29 #define STEP_FLAG 0x00000100 /* single step flag */
30
31 static unsigned be_x86_64_get_addr(HANDLE hThread, const CONTEXT* ctx,
32 enum be_cpu_addr bca, ADDRESS64* addr)
33 {
34 addr->Mode = AddrModeFlat;
35 switch (bca)
36 {
37 case be_cpu_addr_pc:
38 addr->Segment = ctx->SegCs;
39 addr->Offset = ctx->Rip;
40 return TRUE;
41 case be_cpu_addr_stack:
42 addr->Segment = ctx->SegSs;
43 addr->Offset = ctx->Rsp;
44 return TRUE;
45 case be_cpu_addr_frame:
46 addr->Segment = ctx->SegSs;
47 addr->Offset = ctx->Rbp;
48 return TRUE;
49 default:
50 addr->Mode = -1;
51 return FALSE;
52 }
53 }
54
55 static unsigned be_x86_64_get_register_info(int regno, enum be_cpu_addr* kind)
56 {
57 /* this is true when running in 32bit mode... and wrong in 64 :-/ */
58 switch (regno)
59 {
60 case CV_AMD64_RIP: *kind = be_cpu_addr_pc; return TRUE;
61 case CV_AMD64_EBP: *kind = be_cpu_addr_frame; return TRUE;
62 case CV_AMD64_ESP: *kind = be_cpu_addr_stack; return TRUE;
63 }
64 return FALSE;
65 }
66
67 static void be_x86_64_single_step(CONTEXT* ctx, unsigned enable)
68 {
69 if (enable) ctx->EFlags |= STEP_FLAG;
70 else ctx->EFlags &= ~STEP_FLAG;
71 }
72
73 static void be_x86_64_print_context(HANDLE hThread, const CONTEXT* ctx,
74 int all_regs)
75 {
76 static const char flags[] = "aVR-N--ODITSZ-A-P-C";
77 char buf[33];
78 int i;
79
80 strcpy(buf, flags);
81 for (i = 0; buf[i]; i++)
82 if (buf[i] != '-' && !(ctx->EFlags & (1 << (sizeof(flags) - 2 - i))))
83 buf[i] = ' ';
84
85 dbg_printf("Register dump:\n");
86 dbg_printf(" rip:%016lx rsp:%016lx rbp:%016lx eflags:%08x (%s)\n",
87 ctx->Rip, ctx->Rsp, ctx->Rbp, ctx->EFlags, buf);
88 dbg_printf(" rax:%016lx rbx:%016lx rcx:%016lx rdx:%016lx\n",
89 ctx->Rax, ctx->Rbx, ctx->Rcx, ctx->Rdx);
90 dbg_printf(" rsi:%016lx rdi:%016lx r8:%016lx r9:%016lx r10:%016lx\n",
91 ctx->Rsi, ctx->Rdi, ctx->R8, ctx->R9, ctx->R10 );
92 dbg_printf(" r11:%016lx r12:%016lx r13:%016lx r14:%016lx r15:%016lx\n",
93 ctx->R11, ctx->R12, ctx->R13, ctx->R14, ctx->R15 );
94
95 if (all_regs) dbg_printf( "Floating point x86_64 dump not implemented\n" );
96 }
97
98 static void be_x86_64_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
99 {
100 }
101
102 static struct dbg_internal_var be_x86_64_ctx[] =
103 {
104 {CV_AMD64_AL, "AL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_char_int},
105 {CV_AMD64_BL, "BL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_char_int},
106 {CV_AMD64_CL, "CL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_char_int},
107 {CV_AMD64_DL, "DL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_char_int},
108 {CV_AMD64_AH, "AH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rax)+1), dbg_itype_unsigned_char_int},
109 {CV_AMD64_BH, "BH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rbx)+1), dbg_itype_unsigned_char_int},
110 {CV_AMD64_CH, "CH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rcx)+1), dbg_itype_unsigned_char_int},
111 {CV_AMD64_DH, "DH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rdx)+1), dbg_itype_unsigned_char_int},
112 {CV_AMD64_AX, "AX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_short_int},
113 {CV_AMD64_BX, "BX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_short_int},
114 {CV_AMD64_CX, "CX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_short_int},
115 {CV_AMD64_DX, "DX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_short_int},
116 {CV_AMD64_SP, "SP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_short_int},
117 {CV_AMD64_BP, "BP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_short_int},
118 {CV_AMD64_SI, "SI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_short_int},
119 {CV_AMD64_DI, "DI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_short_int},
120 {CV_AMD64_EAX, "EAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_int},
121 {CV_AMD64_EBX, "EBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_int},
122 {CV_AMD64_ECX, "ECX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_int},
123 {CV_AMD64_EDX, "EDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_int},
124 {CV_AMD64_ESP, "ESP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_int},
125 {CV_AMD64_EBP, "EBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_int},
126 {CV_AMD64_ESI, "ESI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_int},
127 {CV_AMD64_EDI, "EDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_int},
128 {CV_AMD64_ES, "ES", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegEs), dbg_itype_unsigned_short_int},
129 {CV_AMD64_CS, "CS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegCs), dbg_itype_unsigned_short_int},
130 {CV_AMD64_SS, "SS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegSs), dbg_itype_unsigned_short_int},
131 {CV_AMD64_DS, "DS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegDs), dbg_itype_unsigned_short_int},
132 {CV_AMD64_FS, "FS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegFs), dbg_itype_unsigned_short_int},
133 {CV_AMD64_GS, "GS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegGs), dbg_itype_unsigned_short_int},
134 {CV_AMD64_FLAGS, "FLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_short_int},
135 {CV_AMD64_EFLAGS, "EFLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_int},
136 {CV_AMD64_RIP, "RIP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rip), dbg_itype_unsigned_long_int},
137 {CV_AMD64_RAX, "RAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_long_int},
138 {CV_AMD64_RBX, "RBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_long_int},
139 {CV_AMD64_RCX, "RCX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_long_int},
140 {CV_AMD64_RDX, "RDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_long_int},
141 {CV_AMD64_RSP, "RSP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_long_int},
142 {CV_AMD64_RBP, "RBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_long_int},
143 {CV_AMD64_RSI, "RSI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_long_int},
144 {CV_AMD64_RDI, "RDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_long_int},
145 {CV_AMD64_R8, "R8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_long_int},
146 {CV_AMD64_R9, "R9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_long_int},
147 {CV_AMD64_R10, "R10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_long_int},
148 {CV_AMD64_R11, "R11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R11), dbg_itype_unsigned_long_int},
149 {CV_AMD64_R12, "R12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R12), dbg_itype_unsigned_long_int},
150 {CV_AMD64_R13, "R13", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R13), dbg_itype_unsigned_long_int},
151 {CV_AMD64_R14, "R14", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R14), dbg_itype_unsigned_long_int},
152 {CV_AMD64_R15, "R15", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R15), dbg_itype_unsigned_long_int},
153 {0, NULL, 0, dbg_itype_none}
154 };
155
156 static const struct dbg_internal_var* be_x86_64_init_registers(CONTEXT* ctx)
157 {
158 struct dbg_internal_var* div;
159
160 for (div = be_x86_64_ctx; div->name; div++)
161 div->pval = (DWORD_PTR*)((char*)ctx + (DWORD_PTR)div->pval);
162 return be_x86_64_ctx;
163 }
164
165 #define f_mod(b) ((b)>>6)
166 #define f_reg(b) (((b)>>3)&0x7)
167 #define f_rm(b) ((b)&0x7)
168
169 static unsigned be_x86_64_is_step_over_insn(const void* insn)
170 {
171 BYTE ch;
172
173 for (;;)
174 {
175 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
176
177 switch (ch)
178 {
179 /* Skip all prefixes */
180 case 0x2e: /* cs: */
181 case 0x36: /* ss: */
182 case 0x3e: /* ds: */
183 case 0x26: /* es: */
184 case 0x64: /* fs: */
185 case 0x65: /* gs: */
186 case 0x66: /* opcode size prefix */
187 case 0x67: /* addr size prefix */
188 case 0xf0: /* lock */
189 case 0xf2: /* repne */
190 case 0xf3: /* repe */
191 insn = (const char*)insn + 1;
192 continue;
193
194 /* Handle call instructions */
195 case 0xcd: /* int <intno> */
196 case 0xe8: /* call <offset> */
197 case 0x9a: /* lcall <seg>:<off> */
198 return TRUE;
199
200 case 0xff: /* call <regmodrm> */
201 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
202 return FALSE;
203 return (((ch & 0x38) == 0x10) || ((ch & 0x38) == 0x18));
204
205 /* Handle string instructions */
206 case 0x6c: /* insb */
207 case 0x6d: /* insw */
208 case 0x6e: /* outsb */
209 case 0x6f: /* outsw */
210 case 0xa4: /* movsb */
211 case 0xa5: /* movsw */
212 case 0xa6: /* cmpsb */
213 case 0xa7: /* cmpsw */
214 case 0xaa: /* stosb */
215 case 0xab: /* stosw */
216 case 0xac: /* lodsb */
217 case 0xad: /* lodsw */
218 case 0xae: /* scasb */
219 case 0xaf: /* scasw */
220 return TRUE;
221
222 default:
223 return FALSE;
224 }
225 }
226 }
227
228 static unsigned be_x86_64_is_function_return(const void* insn)
229 {
230 BYTE c;
231 return dbg_read_memory(insn, &c, sizeof(c)) && ((c == 0xC2) || (c == 0xC3));
232 }
233
234 static unsigned be_x86_64_is_break_insn(const void* insn)
235 {
236 BYTE c;
237 return dbg_read_memory(insn, &c, sizeof(c)) && c == 0xCC;
238 }
239
240 static BOOL fetch_value(const char* addr, unsigned sz, int* value)
241 {
242 char value8;
243 short value16;
244
245 switch (sz)
246 {
247 case 8:
248 if (!dbg_read_memory(addr, &value8, sizeof(value8))) return FALSE;
249 *value = value8;
250 break;
251 case 16:
252 if (!dbg_read_memory(addr, &value16, sizeof(value16))) return FALSE;
253 *value = value16;
254 case 32:
255 if (!dbg_read_memory(addr, value, sizeof(*value))) return FALSE;
256 break;
257 default: return FALSE;
258 }
259 return TRUE;
260 }
261
262 static unsigned be_x86_64_is_func_call(const void* insn, ADDRESS64* callee)
263 {
264 BYTE ch;
265 LONG delta;
266 short segment;
267 unsigned op_size = 32, rex = 0;
268 DWORD64 dst;
269
270 /* we assume 64bit mode all over the place */
271 for (;;)
272 {
273 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
274 if (ch == 0x66) op_size = 16;
275 else if (ch == 0x67) WINE_FIXME("prefix not supported %x\n", ch);
276 else if (ch >= 0x40 && ch <= 0x4f) rex = ch & 0xf;
277 else break;
278 insn = (const char*)insn + 1;
279 } while (0);
280
281 /* that's the only mode we support anyway */
282 callee->Mode = AddrModeFlat;
283 callee->Segment = dbg_context.SegCs;
284
285 switch (ch)
286 {
287 case 0xe8: /* relative near call */
288 assert(op_size == 32);
289 if (!fetch_value((const char*)insn + 1, sizeof(delta), &delta))
290 return FALSE;
291 callee->Offset = (DWORD_PTR)insn + 1 + 4 + delta;
292 return TRUE;
293
294 case 0xff:
295 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
296 return FALSE;
297 WINE_TRACE("Got 0xFF %x (&C7=%x) with rex=%x\n", ch, ch & 0xC7, rex);
298 /* keep only the CALL and LCALL insn:s */
299 switch (f_reg(ch))
300 {
301 case 0x02:
302 segment = dbg_context.SegCs;
303 break;
304 default: return FALSE;
305 }
306 if (rex == 0) switch (ch & 0xC7) /* keep Mod R/M only (skip reg) */
307 {
308 case 0x04:
309 case 0x44:
310 case 0x84:
311 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) (SIB bytes) at %p\n", ch, insn);
312 return FALSE;
313 case 0x05: /* addr32 */
314 if (f_reg(ch) == 0x2)
315 {
316 /* rip-relative to next insn */
317 if (!dbg_read_memory((const char*)insn + 2, &delta, sizeof(delta)) ||
318 !dbg_read_memory((const char*)insn + 6 + delta, &dst, sizeof(dst)))
319 return FALSE;
320
321 callee->Offset = dst;
322 return TRUE;
323 }
324 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
325 return FALSE;
326 default:
327 switch (f_rm(ch))
328 {
329 case 0x00: dst = dbg_context.Rax; break;
330 case 0x01: dst = dbg_context.Rcx; break;
331 case 0x02: dst = dbg_context.Rdx; break;
332 case 0x03: dst = dbg_context.Rbx; break;
333 case 0x04: dst = dbg_context.Rsp; break;
334 case 0x05: dst = dbg_context.Rbp; break;
335 case 0x06: dst = dbg_context.Rsi; break;
336 case 0x07: dst = dbg_context.Rdi; break;
337 }
338 if (f_mod(ch) != 0x03)
339 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
340 else
341 {
342 callee->Offset = dst;
343 }
344 break;
345 }
346 else
347 WINE_FIXME("Unsupported yet call insn (rex=0x%02x 0xFF 0x%02x) at %p\n", rex, ch, insn);
348 return FALSE;
349
350 default:
351 return FALSE;
352 }
353 }
354
355 extern void be_x86_64_disasm_one_insn(ADDRESS64* addr, int display);
356
357 #define DR7_CONTROL_SHIFT 16
358 #define DR7_CONTROL_SIZE 4
359
360 #define DR7_RW_EXECUTE (0x0)
361 #define DR7_RW_WRITE (0x1)
362 #define DR7_RW_READ (0x3)
363
364 #define DR7_LEN_1 (0x0)
365 #define DR7_LEN_2 (0x4)
366 #define DR7_LEN_4 (0xC)
367
368 #define DR7_LOCAL_ENABLE_SHIFT 0
369 #define DR7_GLOBAL_ENABLE_SHIFT 1
370 #define DR7_ENABLE_SIZE 2
371
372 #define DR7_LOCAL_ENABLE_MASK (0x55)
373 #define DR7_GLOBAL_ENABLE_MASK (0xAA)
374
375 #define DR7_CONTROL_RESERVED (0xFC00)
376 #define DR7_LOCAL_SLOWDOWN (0x100)
377 #define DR7_GLOBAL_SLOWDOWN (0x200)
378
379 #define DR7_ENABLE_MASK(dr) (1<<(DR7_LOCAL_ENABLE_SHIFT+DR7_ENABLE_SIZE*(dr)))
380 #define IS_DR7_SET(ctrl,dr) ((ctrl)&DR7_ENABLE_MASK(dr))
381
382 static inline int be_x86_64_get_unused_DR(CONTEXT* ctx, DWORD64** r)
383 {
384 if (!IS_DR7_SET(ctx->Dr7, 0))
385 {
386 *r = &ctx->Dr0;
387 return 0;
388 }
389 if (!IS_DR7_SET(ctx->Dr7, 1))
390 {
391 *r = &ctx->Dr1;
392 return 1;
393 }
394 if (!IS_DR7_SET(ctx->Dr7, 2))
395 {
396 *r = &ctx->Dr2;
397 return 2;
398 }
399 if (!IS_DR7_SET(ctx->Dr7, 3))
400 {
401 *r = &ctx->Dr3;
402 return 3;
403 }
404 dbg_printf("All hardware registers have been used\n");
405
406 return -1;
407 }
408
409 static unsigned be_x86_64_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
410 CONTEXT* ctx, enum be_xpoint_type type,
411 void* addr, unsigned long* val, unsigned size)
412 {
413 unsigned char ch;
414 SIZE_T sz;
415 DWORD64 *pr;
416 int reg;
417 unsigned long bits;
418
419 switch (type)
420 {
421 case be_xpoint_break:
422 if (size != 0) return 0;
423 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
424 *val = ch;
425 ch = 0xcc;
426 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
427 break;
428 case be_xpoint_watch_exec:
429 bits = DR7_RW_EXECUTE;
430 goto hw_bp;
431 case be_xpoint_watch_read:
432 bits = DR7_RW_READ;
433 goto hw_bp;
434 case be_xpoint_watch_write:
435 bits = DR7_RW_WRITE;
436 hw_bp:
437 if ((reg = be_x86_64_get_unused_DR(ctx, &pr)) == -1) return 0;
438 *pr = (DWORD64)addr;
439 if (type != be_xpoint_watch_exec) switch (size)
440 {
441 case 4: bits |= DR7_LEN_4; break;
442 case 2: bits |= DR7_LEN_2; break;
443 case 1: bits |= DR7_LEN_1; break;
444 default: return 0;
445 }
446 *val = reg;
447 /* clear old values */
448 ctx->Dr7 &= ~(0x0F << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg));
449 /* set the correct ones */
450 ctx->Dr7 |= bits << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg);
451 ctx->Dr7 |= DR7_ENABLE_MASK(reg) | DR7_LOCAL_SLOWDOWN;
452 break;
453 default:
454 dbg_printf("Unknown bp type %c\n", type);
455 return 0;
456 }
457 return 1;
458 }
459
460 static unsigned be_x86_64_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
461 CONTEXT* ctx, enum be_xpoint_type type,
462 void* addr, unsigned long val, unsigned size)
463 {
464 SIZE_T sz;
465 unsigned char ch;
466
467 switch (type)
468 {
469 case be_xpoint_break:
470 if (size != 0) return 0;
471 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
472 if (ch != (unsigned char)0xCC)
473 WINE_FIXME("Cannot get back %02x instead of 0xCC at %08lx\n",
474 ch, (unsigned long)addr);
475 ch = (unsigned char)val;
476 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
477 break;
478 case be_xpoint_watch_exec:
479 case be_xpoint_watch_read:
480 case be_xpoint_watch_write:
481 /* simply disable the entry */
482 ctx->Dr7 &= ~DR7_ENABLE_MASK(val);
483 break;
484 default:
485 dbg_printf("Unknown bp type %c\n", type);
486 return 0;
487 }
488 return 1;
489 }
490
491 static unsigned be_x86_64_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
492 {
493 return ctx->Dr6 & (1 << idx);
494 }
495
496 static void be_x86_64_clear_watchpoint(CONTEXT* ctx, unsigned idx)
497 {
498 ctx->Dr6 &= ~(1 << idx);
499 }
500
501 static int be_x86_64_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
502 {
503 if (way)
504 {
505 ctx->Rip--;
506 return -1;
507 }
508 ctx->Rip++;
509 return 1;
510 }
511
512 static int be_x86_64_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
513 unsigned ext_sign, LONGLONG* ret)
514 {
515 if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
516 return FALSE;
517
518 memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
519 /* FIXME: this assumes that debuggee and debugger use the same
520 * integral representation
521 */
522 if (!memory_read_value(lvalue, size, ret)) return FALSE;
523
524 /* propagate sign information */
525 if (ext_sign && size < 16 && (*ret >> (size * 8 - 1)) != 0)
526 {
527 ULONGLONG neg = -1;
528 *ret |= neg << (size * 8);
529 }
530 return TRUE;
531 }
532
533 static int be_x86_64_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
534 long double* ret)
535 {
536 char tmp[sizeof(long double)];
537
538 /* FIXME: this assumes that debuggee and debugger use the same
539 * representation for reals
540 */
541 if (!memory_read_value(lvalue, size, tmp)) return FALSE;
542
543 /* float & double types have to be promoted to a long double */
544 switch (size)
545 {
546 case sizeof(float): *ret = *(float*)tmp; break;
547 case sizeof(double): *ret = *(double*)tmp; break;
548 case sizeof(long double): *ret = *(long double*)tmp; break;
549 default: return FALSE;
550 }
551 return TRUE;
552 }
553
554 struct backend_cpu be_x86_64 =
555 {
556 IMAGE_FILE_MACHINE_AMD64,
557 be_cpu_linearize,
558 be_cpu_build_addr,
559 be_x86_64_get_addr,
560 be_x86_64_get_register_info,
561 be_x86_64_single_step,
562 be_x86_64_print_context,
563 be_x86_64_print_segment_info,
564 be_x86_64_init_registers,
565 be_x86_64_is_step_over_insn,
566 be_x86_64_is_function_return,
567 be_x86_64_is_break_insn,
568 be_x86_64_is_func_call,
569 be_x86_64_disasm_one_insn,
570 be_x86_64_insert_Xpoint,
571 be_x86_64_remove_Xpoint,
572 be_x86_64_is_watchpoint_set,
573 be_x86_64_clear_watchpoint,
574 be_x86_64_adjust_pc_for_break,
575 be_x86_64_fetch_integer,
576 be_x86_64_fetch_float,
577 };
578 #endif
useful hacks and other patches not (yet) suitable for mainline