Improve efficiency of macro concatenation
[tinycc.git] / x86_64-gen.c
1 /*
2 * x86-64 code generator for TCC
3 *
4 * Copyright (c) 2008 Shinichiro Hamaji
5 *
6 * Based on i386-gen.c by Fabrice Bellard
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #ifdef TARGET_DEFS_ONLY
24
25 /* number of available registers */
26 #define NB_REGS 25
27 #define NB_ASM_REGS 8
28
29 /* a register can belong to several classes. The classes must be
30 sorted from more general to more precise (see gv2() code which does
31 assumptions on it). */
32 #define RC_INT 0x0001 /* generic integer register */
33 #define RC_FLOAT 0x0002 /* generic float register */
34 #define RC_RAX 0x0004
35 #define RC_RCX 0x0008
36 #define RC_RDX 0x0010
37 #define RC_ST0 0x0080 /* only for long double */
38 #define RC_R8 0x0100
39 #define RC_R9 0x0200
40 #define RC_R10 0x0400
41 #define RC_R11 0x0800
42 #define RC_XMM0 0x1000
43 #define RC_XMM1 0x2000
44 #define RC_XMM2 0x4000
45 #define RC_XMM3 0x8000
46 #define RC_XMM4 0x10000
47 #define RC_XMM5 0x20000
48 #define RC_XMM6 0x40000
49 #define RC_XMM7 0x80000
50 #define RC_IRET RC_RAX /* function return: integer register */
51 #define RC_LRET RC_RDX /* function return: second integer register */
52 #define RC_FRET RC_XMM0 /* function return: float register */
53 #define RC_QRET RC_XMM1 /* function return: second float register */
54
55 /* pretty names for the registers */
56 enum {
57 TREG_RAX = 0,
58 TREG_RCX = 1,
59 TREG_RDX = 2,
60 TREG_RSP = 4,
61 TREG_RSI = 6,
62 TREG_RDI = 7,
63
64 TREG_R8 = 8,
65 TREG_R9 = 9,
66 TREG_R10 = 10,
67 TREG_R11 = 11,
68
69 TREG_XMM0 = 16,
70 TREG_XMM1 = 17,
71 TREG_XMM2 = 18,
72 TREG_XMM3 = 19,
73 TREG_XMM4 = 20,
74 TREG_XMM5 = 21,
75 TREG_XMM6 = 22,
76 TREG_XMM7 = 23,
77
78 TREG_ST0 = 24,
79
80 TREG_MEM = 0x20,
81 };
82
83 #define REX_BASE(reg) (((reg) >> 3) & 1)
84 #define REG_VALUE(reg) ((reg) & 7)
85
86 /* return registers for function */
87 #define REG_IRET TREG_RAX /* single word int return register */
88 #define REG_LRET TREG_RDX /* second word return register (for long long) */
89 #define REG_FRET TREG_XMM0 /* float return register */
90 #define REG_QRET TREG_XMM1 /* second float return register */
91
92 /* defined if function parameters must be evaluated in reverse order */
93 #define INVERT_FUNC_PARAMS
94
95 /* pointer size, in bytes */
96 #define PTR_SIZE 8
97
98 /* long double size and alignment, in bytes */
99 #define LDOUBLE_SIZE 16
100 #define LDOUBLE_ALIGN 16
101 /* maximum alignment (for aligned attribute support) */
102 #define MAX_ALIGN 16
103
104 /******************************************************/
105 /* ELF defines */
106
107 #define EM_TCC_TARGET EM_X86_64
108
109 /* relocation type for 32 bit data relocation */
110 #define R_DATA_32 R_X86_64_32
111 #define R_DATA_PTR R_X86_64_64
112 #define R_JMP_SLOT R_X86_64_JUMP_SLOT
113 #define R_COPY R_X86_64_COPY
114
115 #define ELF_START_ADDR 0x400000
116 #define ELF_PAGE_SIZE 0x200000
117
118 /******************************************************/
119 #else /* ! TARGET_DEFS_ONLY */
120 /******************************************************/
121 #include "tcc.h"
122 #include <assert.h>
123
124 ST_DATA const int reg_classes[NB_REGS] = {
125 /* eax */ RC_INT | RC_RAX,
126 /* ecx */ RC_INT | RC_RCX,
127 /* edx */ RC_INT | RC_RDX,
128 0,
129 0,
130 0,
131 0,
132 0,
133 RC_R8,
134 RC_R9,
135 RC_R10,
136 RC_R11,
137 0,
138 0,
139 0,
140 0,
141 /* xmm0 */ RC_FLOAT | RC_XMM0,
142 /* xmm1 */ RC_FLOAT | RC_XMM1,
143 /* xmm2 */ RC_FLOAT | RC_XMM2,
144 /* xmm3 */ RC_FLOAT | RC_XMM3,
145 /* xmm4 */ RC_FLOAT | RC_XMM4,
146 /* xmm5 */ RC_FLOAT | RC_XMM5,
147 /* xmm6 an xmm7 are included so gv() can be used on them,
148 but they are not tagged with RC_FLOAT because they are
149 callee saved on Windows */
150 RC_XMM6,
151 RC_XMM7,
152 /* st0 */ RC_ST0
153 };
154
155 static unsigned long func_sub_sp_offset;
156 static int func_ret_sub;
157
158 /* XXX: make it faster ? */
159 void g(int c)
160 {
161 int ind1;
162 ind1 = ind + 1;
163 if (ind1 > cur_text_section->data_allocated)
164 section_realloc(cur_text_section, ind1);
165 cur_text_section->data[ind] = c;
166 ind = ind1;
167 }
168
169 void o(unsigned int c)
170 {
171 while (c) {
172 g(c);
173 c = c >> 8;
174 }
175 }
176
177 void gen_le16(int v)
178 {
179 g(v);
180 g(v >> 8);
181 }
182
183 void gen_le32(int c)
184 {
185 g(c);
186 g(c >> 8);
187 g(c >> 16);
188 g(c >> 24);
189 }
190
191 void gen_le64(int64_t c)
192 {
193 g(c);
194 g(c >> 8);
195 g(c >> 16);
196 g(c >> 24);
197 g(c >> 32);
198 g(c >> 40);
199 g(c >> 48);
200 g(c >> 56);
201 }
202
203 void orex(int ll, int r, int r2, int b)
204 {
205 if ((r & VT_VALMASK) >= VT_CONST)
206 r = 0;
207 if ((r2 & VT_VALMASK) >= VT_CONST)
208 r2 = 0;
209 if (ll || REX_BASE(r) || REX_BASE(r2))
210 o(0x40 | REX_BASE(r) | (REX_BASE(r2) << 2) | (ll << 3));
211 o(b);
212 }
213
214 /* output a symbol and patch all calls to it */
215 void gsym_addr(int t, int a)
216 {
217 int n, *ptr;
218 while (t) {
219 ptr = (int *)(cur_text_section->data + t);
220 n = *ptr; /* next value */
221 *ptr = a - t - 4;
222 t = n;
223 }
224 }
225
226 void gsym(int t)
227 {
228 gsym_addr(t, ind);
229 }
230
231 /* psym is used to put an instruction with a data field which is a
232 reference to a symbol. It is in fact the same as oad ! */
233 #define psym oad
234
235 static int is64_type(int t)
236 {
237 return ((t & VT_BTYPE) == VT_PTR ||
238 (t & VT_BTYPE) == VT_FUNC ||
239 (t & VT_BTYPE) == VT_LLONG);
240 }
241
242 /* instruction + 4 bytes data. Return the address of the data */
243 ST_FUNC int oad(int c, int s)
244 {
245 int ind1;
246
247 o(c);
248 ind1 = ind + 4;
249 if (ind1 > cur_text_section->data_allocated)
250 section_realloc(cur_text_section, ind1);
251 *(int *)(cur_text_section->data + ind) = s;
252 s = ind;
253 ind = ind1;
254 return s;
255 }
256
257 ST_FUNC void gen_addr32(int r, Sym *sym, int c)
258 {
259 if (r & VT_SYM)
260 greloc(cur_text_section, sym, ind, R_X86_64_32);
261 gen_le32(c);
262 }
263
264 /* output constant with relocation if 'r & VT_SYM' is true */
265 ST_FUNC void gen_addr64(int r, Sym *sym, int64_t c)
266 {
267 if (r & VT_SYM)
268 greloc(cur_text_section, sym, ind, R_X86_64_64);
269 gen_le64(c);
270 }
271
272 /* output constant with relocation if 'r & VT_SYM' is true */
273 ST_FUNC void gen_addrpc32(int r, Sym *sym, int c)
274 {
275 if (r & VT_SYM)
276 greloc(cur_text_section, sym, ind, R_X86_64_PC32);
277 gen_le32(c-4);
278 }
279
280 /* output got address with relocation */
281 static void gen_gotpcrel(int r, Sym *sym, int c)
282 {
283 #ifndef TCC_TARGET_PE
284 Section *sr;
285 ElfW(Rela) *rel;
286 greloc(cur_text_section, sym, ind, R_X86_64_GOTPCREL);
287 sr = cur_text_section->reloc;
288 rel = (ElfW(Rela) *)(sr->data + sr->data_offset - sizeof(ElfW(Rela)));
289 rel->r_addend = -4;
290 #else
291 printf("picpic: %s %x %x | %02x %02x %02x\n", get_tok_str(sym->v, NULL), c, r,
292 cur_text_section->data[ind-3],
293 cur_text_section->data[ind-2],
294 cur_text_section->data[ind-1]
295 );
296 greloc(cur_text_section, sym, ind, R_X86_64_PC32);
297 #endif
298 gen_le32(0);
299 if (c) {
300 /* we use add c, %xxx for displacement */
301 orex(1, r, 0, 0x81);
302 o(0xc0 + REG_VALUE(r));
303 gen_le32(c);
304 }
305 }
306
307 static void gen_modrm_impl(int op_reg, int r, Sym *sym, int c, int is_got)
308 {
309 op_reg = REG_VALUE(op_reg) << 3;
310 if ((r & VT_VALMASK) == VT_CONST) {
311 /* constant memory reference */
312 o(0x05 | op_reg);
313 if (is_got) {
314 gen_gotpcrel(r, sym, c);
315 } else {
316 gen_addrpc32(r, sym, c);
317 }
318 } else if ((r & VT_VALMASK) == VT_LOCAL) {
319 /* currently, we use only ebp as base */
320 if (c == (char)c) {
321 /* short reference */
322 o(0x45 | op_reg);
323 g(c);
324 } else {
325 oad(0x85 | op_reg, c);
326 }
327 } else if ((r & VT_VALMASK) >= TREG_MEM) {
328 if (c) {
329 g(0x80 | op_reg | REG_VALUE(r));
330 gen_le32(c);
331 } else {
332 g(0x00 | op_reg | REG_VALUE(r));
333 }
334 } else {
335 g(0x00 | op_reg | REG_VALUE(r));
336 }
337 }
338
339 /* generate a modrm reference. 'op_reg' contains the addtionnal 3
340 opcode bits */
341 static void gen_modrm(int op_reg, int r, Sym *sym, int c)
342 {
343 gen_modrm_impl(op_reg, r, sym, c, 0);
344 }
345
346 /* generate a modrm reference. 'op_reg' contains the addtionnal 3
347 opcode bits */
348 static void gen_modrm64(int opcode, int op_reg, int r, Sym *sym, int c)
349 {
350 int is_got;
351 is_got = (op_reg & TREG_MEM) && !(sym->type.t & VT_STATIC);
352 orex(1, r, op_reg, opcode);
353 gen_modrm_impl(op_reg, r, sym, c, is_got);
354 }
355
356
357 /* load 'r' from value 'sv' */
358 void load(int r, SValue *sv)
359 {
360 int v, t, ft, fc, fr;
361 SValue v1;
362
363 #ifdef TCC_TARGET_PE
364 SValue v2;
365 sv = pe_getimport(sv, &v2);
366 #endif
367
368 fr = sv->r;
369 ft = sv->type.t & ~VT_DEFSIGN;
370 fc = sv->c.ul;
371
372 #ifndef TCC_TARGET_PE
373 /* we use indirect access via got */
374 if ((fr & VT_VALMASK) == VT_CONST && (fr & VT_SYM) &&
375 (fr & VT_LVAL) && !(sv->sym->type.t & VT_STATIC)) {
376 /* use the result register as a temporal register */
377 int tr = r | TREG_MEM;
378 if (is_float(ft)) {
379 /* we cannot use float registers as a temporal register */
380 tr = get_reg(RC_INT) | TREG_MEM;
381 }
382 gen_modrm64(0x8b, tr, fr, sv->sym, 0);
383
384 /* load from the temporal register */
385 fr = tr | VT_LVAL;
386 }
387 #endif
388
389 v = fr & VT_VALMASK;
390 if (fr & VT_LVAL) {
391 int b, ll;
392 if (v == VT_LLOCAL) {
393 v1.type.t = VT_PTR;
394 v1.r = VT_LOCAL | VT_LVAL;
395 v1.c.ul = fc;
396 fr = r;
397 if (!(reg_classes[fr] & RC_INT))
398 fr = get_reg(RC_INT);
399 load(fr, &v1);
400 }
401 ll = 0;
402 if ((ft & VT_BTYPE) == VT_FLOAT) {
403 b = 0x6e0f66;
404 r = REG_VALUE(r); /* movd */
405 } else if ((ft & VT_BTYPE) == VT_DOUBLE) {
406 b = 0x7e0ff3; /* movq */
407 r = REG_VALUE(r);
408 } else if ((ft & VT_BTYPE) == VT_LDOUBLE) {
409 b = 0xdb, r = 5; /* fldt */
410 } else if ((ft & VT_TYPE) == VT_BYTE || (ft & VT_TYPE) == VT_BOOL) {
411 b = 0xbe0f; /* movsbl */
412 } else if ((ft & VT_TYPE) == (VT_BYTE | VT_UNSIGNED)) {
413 b = 0xb60f; /* movzbl */
414 } else if ((ft & VT_TYPE) == VT_SHORT) {
415 b = 0xbf0f; /* movswl */
416 } else if ((ft & VT_TYPE) == (VT_SHORT | VT_UNSIGNED)) {
417 b = 0xb70f; /* movzwl */
418 } else {
419 assert(((ft & VT_BTYPE) == VT_INT) || ((ft & VT_BTYPE) == VT_LLONG)
420 || ((ft & VT_BTYPE) == VT_PTR) || ((ft & VT_BTYPE) == VT_ENUM)
421 || ((ft & VT_BTYPE) == VT_FUNC));
422 ll = is64_type(ft);
423 b = 0x8b;
424 }
425 if (ll) {
426 gen_modrm64(b, r, fr, sv->sym, fc);
427 } else {
428 orex(ll, fr, r, b);
429 gen_modrm(r, fr, sv->sym, fc);
430 }
431 } else {
432 if (v == VT_CONST) {
433 if (fr & VT_SYM) {
434 #ifdef TCC_TARGET_PE
435 orex(1,0,r,0x8d);
436 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
437 gen_addrpc32(fr, sv->sym, fc);
438 #else
439 if (sv->sym->type.t & VT_STATIC) {
440 orex(1,0,r,0x8d);
441 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
442 gen_addrpc32(fr, sv->sym, fc);
443 } else {
444 orex(1,0,r,0x8b);
445 o(0x05 + REG_VALUE(r) * 8); /* mov xx(%rip), r */
446 gen_gotpcrel(r, sv->sym, fc);
447 }
448 #endif
449 } else if (is64_type(ft)) {
450 orex(1,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
451 gen_le64(sv->c.ull);
452 } else {
453 orex(0,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
454 gen_le32(fc);
455 }
456 } else if (v == VT_LOCAL) {
457 orex(1,0,r,0x8d); /* lea xxx(%ebp), r */
458 gen_modrm(r, VT_LOCAL, sv->sym, fc);
459 } else if (v == VT_CMP) {
460 orex(0,r,0,0);
461 if ((fc & ~0x100) != TOK_NE)
462 oad(0xb8 + REG_VALUE(r), 0); /* mov $0, r */
463 else
464 oad(0xb8 + REG_VALUE(r), 1); /* mov $1, r */
465 if (fc & 0x100)
466 {
467 /* This was a float compare. If the parity bit is
468 set the result was unordered, meaning false for everything
469 except TOK_NE, and true for TOK_NE. */
470 fc &= ~0x100;
471 o(0x037a + (REX_BASE(r) << 8));
472 }
473 orex(0,r,0, 0x0f); /* setxx %br */
474 o(fc);
475 o(0xc0 + REG_VALUE(r));
476 } else if (v == VT_JMP || v == VT_JMPI) {
477 t = v & 1;
478 orex(0,r,0,0);
479 oad(0xb8 + REG_VALUE(r), t); /* mov $1, r */
480 o(0x05eb + (REX_BASE(r) << 8)); /* jmp after */
481 gsym(fc);
482 orex(0,r,0,0);
483 oad(0xb8 + REG_VALUE(r), t ^ 1); /* mov $0, r */
484 } else if (v != r) {
485 if ((r >= TREG_XMM0) && (r <= TREG_XMM7)) {
486 if (v == TREG_ST0) {
487 /* gen_cvt_ftof(VT_DOUBLE); */
488 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
489 /* movsd -0x10(%rsp),%xmmN */
490 o(0x100ff2);
491 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
492 o(0xf024);
493 } else {
494 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
495 if ((ft & VT_BTYPE) == VT_FLOAT) {
496 o(0x100ff3);
497 } else {
498 assert((ft & VT_BTYPE) == VT_DOUBLE);
499 o(0x100ff2);
500 }
501 o(0xc0 + REG_VALUE(v) + REG_VALUE(r)*8);
502 }
503 } else if (r == TREG_ST0) {
504 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
505 /* gen_cvt_ftof(VT_LDOUBLE); */
506 /* movsd %xmmN,-0x10(%rsp) */
507 o(0x110ff2);
508 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
509 o(0xf024);
510 o(0xf02444dd); /* fldl -0x10(%rsp) */
511 } else {
512 orex(1,r,v, 0x89);
513 o(0xc0 + REG_VALUE(r) + REG_VALUE(v) * 8); /* mov v, r */
514 }
515 }
516 }
517 }
518
519 /* store register 'r' in lvalue 'v' */
520 void store(int r, SValue *v)
521 {
522 int fr, bt, ft, fc;
523 int op64 = 0;
524 /* store the REX prefix in this variable when PIC is enabled */
525 int pic = 0;
526
527 #ifdef TCC_TARGET_PE
528 SValue v2;
529 v = pe_getimport(v, &v2);
530 #endif
531
532 ft = v->type.t;
533 fc = v->c.ul;
534 fr = v->r & VT_VALMASK;
535 bt = ft & VT_BTYPE;
536
537 #ifndef TCC_TARGET_PE
538 /* we need to access the variable via got */
539 if (fr == VT_CONST && (v->r & VT_SYM)) {
540 /* mov xx(%rip), %r11 */
541 o(0x1d8b4c);
542 gen_gotpcrel(TREG_R11, v->sym, v->c.ul);
543 pic = is64_type(bt) ? 0x49 : 0x41;
544 }
545 #endif
546
547 /* XXX: incorrect if float reg to reg */
548 if (bt == VT_FLOAT) {
549 o(0x66);
550 o(pic);
551 o(0x7e0f); /* movd */
552 r = REG_VALUE(r);
553 } else if (bt == VT_DOUBLE) {
554 o(0x66);
555 o(pic);
556 o(0xd60f); /* movq */
557 r = REG_VALUE(r);
558 } else if (bt == VT_LDOUBLE) {
559 o(0xc0d9); /* fld %st(0) */
560 o(pic);
561 o(0xdb); /* fstpt */
562 r = 7;
563 } else {
564 if (bt == VT_SHORT)
565 o(0x66);
566 o(pic);
567 if (bt == VT_BYTE || bt == VT_BOOL)
568 orex(0, 0, r, 0x88);
569 else if (is64_type(bt))
570 op64 = 0x89;
571 else
572 orex(0, 0, r, 0x89);
573 }
574 if (pic) {
575 /* xxx r, (%r11) where xxx is mov, movq, fld, or etc */
576 if (op64)
577 o(op64);
578 o(3 + (r << 3));
579 } else if (op64) {
580 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
581 gen_modrm64(op64, r, v->r, v->sym, fc);
582 } else if (fr != r) {
583 /* XXX: don't we really come here? */
584 abort();
585 o(0xc0 + fr + r * 8); /* mov r, fr */
586 }
587 } else {
588 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
589 gen_modrm(r, v->r, v->sym, fc);
590 } else if (fr != r) {
591 /* XXX: don't we really come here? */
592 abort();
593 o(0xc0 + fr + r * 8); /* mov r, fr */
594 }
595 }
596 }
597
598 /* 'is_jmp' is '1' if it is a jump */
599 static void gcall_or_jmp(int is_jmp)
600 {
601 int r;
602 if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
603 /* constant case */
604 if (vtop->r & VT_SYM) {
605 /* relocation case */
606 greloc(cur_text_section, vtop->sym,
607 ind + 1, R_X86_64_PLT32);
608 } else {
609 /* put an empty PC32 relocation */
610 put_elf_reloc(symtab_section, cur_text_section,
611 ind + 1, R_X86_64_PC32, 0);
612 }
613 oad(0xe8 + is_jmp, vtop->c.ul - 4); /* call/jmp im */
614 } else {
615 /* otherwise, indirect call */
616 r = TREG_R11;
617 load(r, vtop);
618 o(0x41); /* REX */
619 o(0xff); /* call/jmp *r */
620 o(0xd0 + REG_VALUE(r) + (is_jmp << 4));
621 }
622 }
623
624 #ifdef TCC_TARGET_PE
625
626 #define REGN 4
627 static const uint8_t arg_regs[REGN] = {
628 TREG_RCX, TREG_RDX, TREG_R8, TREG_R9
629 };
630
631 /* Prepare arguments in R10 and R11 rather than RCX and RDX
632 because gv() will not ever use these */
633 static int arg_prepare_reg(int idx) {
634 if (idx == 0 || idx == 1)
635 /* idx=0: r10, idx=1: r11 */
636 return idx + 10;
637 else
638 return arg_regs[idx];
639 }
640
641 static int func_scratch;
642
643 /* Generate function call. The function address is pushed first, then
644 all the parameters in call order. This functions pops all the
645 parameters and the function address. */
646
647 void gen_offs_sp(int b, int r, int d)
648 {
649 orex(1,0,r & 0x100 ? 0 : r, b);
650 if (d == (char)d) {
651 o(0x2444 | (REG_VALUE(r) << 3));
652 g(d);
653 } else {
654 o(0x2484 | (REG_VALUE(r) << 3));
655 gen_le32(d);
656 }
657 }
658
659 /* Return the number of registers needed to return the struct, or 0 if
660 returning via struct pointer. */
661 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align)
662 {
663 int size, align;
664 *ret_align = 1; // Never have to re-align return values for x86-64
665 size = type_size(vt, &align);
666 ret->ref = NULL;
667 if (size > 8) {
668 return 0;
669 } else if (size > 4) {
670 ret->t = VT_LLONG;
671 return 1;
672 } else if (size > 2) {
673 ret->t = VT_INT;
674 return 1;
675 } else if (size > 1) {
676 ret->t = VT_SHORT;
677 return 1;
678 } else {
679 ret->t = VT_BYTE;
680 return 1;
681 }
682 }
683
684 static int is_sse_float(int t) {
685 int bt;
686 bt = t & VT_BTYPE;
687 return bt == VT_DOUBLE || bt == VT_FLOAT;
688 }
689
690 int gfunc_arg_size(CType *type) {
691 int align;
692 if (type->t & (VT_ARRAY|VT_BITFIELD))
693 return 8;
694 return type_size(type, &align);
695 }
696
697 void gfunc_call(int nb_args)
698 {
699 int size, r, args_size, i, d, bt, struct_size;
700 int arg;
701
702 args_size = (nb_args < REGN ? REGN : nb_args) * PTR_SIZE;
703 arg = nb_args;
704
705 /* for struct arguments, we need to call memcpy and the function
706 call breaks register passing arguments we are preparing.
707 So, we process arguments which will be passed by stack first. */
708 struct_size = args_size;
709 for(i = 0; i < nb_args; i++) {
710 SValue *sv;
711
712 --arg;
713 sv = &vtop[-i];
714 bt = (sv->type.t & VT_BTYPE);
715 size = gfunc_arg_size(&sv->type);
716
717 if (size <= 8)
718 continue; /* arguments smaller than 8 bytes passed in registers or on stack */
719
720 if (bt == VT_STRUCT) {
721 /* align to stack align size */
722 size = (size + 15) & ~15;
723 /* generate structure store */
724 r = get_reg(RC_INT);
725 gen_offs_sp(0x8d, r, struct_size);
726 struct_size += size;
727
728 /* generate memcpy call */
729 vset(&sv->type, r | VT_LVAL, 0);
730 vpushv(sv);
731 vstore();
732 --vtop;
733 } else if (bt == VT_LDOUBLE) {
734 gv(RC_ST0);
735 gen_offs_sp(0xdb, 0x107, struct_size);
736 struct_size += 16;
737 }
738 }
739
740 if (func_scratch < struct_size)
741 func_scratch = struct_size;
742
743 arg = nb_args;
744 struct_size = args_size;
745
746 for(i = 0; i < nb_args; i++) {
747 --arg;
748 bt = (vtop->type.t & VT_BTYPE);
749
750 size = gfunc_arg_size(&vtop->type);
751 if (size > 8) {
752 /* align to stack align size */
753 size = (size + 15) & ~15;
754 if (arg >= REGN) {
755 d = get_reg(RC_INT);
756 gen_offs_sp(0x8d, d, struct_size);
757 gen_offs_sp(0x89, d, arg*8);
758 } else {
759 d = arg_prepare_reg(arg);
760 gen_offs_sp(0x8d, d, struct_size);
761 }
762 struct_size += size;
763 } else {
764 if (is_sse_float(vtop->type.t)) {
765 gv(RC_XMM0); /* only use one float register */
766 if (arg >= REGN) {
767 /* movq %xmm0, j*8(%rsp) */
768 gen_offs_sp(0xd60f66, 0x100, arg*8);
769 } else {
770 /* movaps %xmm0, %xmmN */
771 o(0x280f);
772 o(0xc0 + (arg << 3));
773 d = arg_prepare_reg(arg);
774 /* mov %xmm0, %rxx */
775 o(0x66);
776 orex(1,d,0, 0x7e0f);
777 o(0xc0 + REG_VALUE(d));
778 }
779 } else {
780 if (bt == VT_STRUCT) {
781 vtop->type.ref = NULL;
782 vtop->type.t = size > 4 ? VT_LLONG : size > 2 ? VT_INT
783 : size > 1 ? VT_SHORT : VT_BYTE;
784 }
785
786 r = gv(RC_INT);
787 if (arg >= REGN) {
788 gen_offs_sp(0x89, r, arg*8);
789 } else {
790 d = arg_prepare_reg(arg);
791 orex(1,d,r,0x89); /* mov */
792 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
793 }
794 }
795 }
796 vtop--;
797 }
798 save_regs(0);
799
800 /* Copy R10 and R11 into RCX and RDX, respectively */
801 if (nb_args > 0) {
802 o(0xd1894c); /* mov %r10, %rcx */
803 if (nb_args > 1) {
804 o(0xda894c); /* mov %r11, %rdx */
805 }
806 }
807
808 gcall_or_jmp(0);
809 vtop--;
810 }
811
812
813 #define FUNC_PROLOG_SIZE 11
814
815 /* generate function prolog of type 't' */
816 void gfunc_prolog(CType *func_type)
817 {
818 int addr, reg_param_index, bt, size;
819 Sym *sym;
820 CType *type;
821
822 func_ret_sub = 0;
823 func_scratch = 0;
824 loc = 0;
825
826 addr = PTR_SIZE * 2;
827 ind += FUNC_PROLOG_SIZE;
828 func_sub_sp_offset = ind;
829 reg_param_index = 0;
830
831 sym = func_type->ref;
832
833 /* if the function returns a structure, then add an
834 implicit pointer parameter */
835 func_vt = sym->type;
836 func_var = (sym->c == FUNC_ELLIPSIS);
837 size = gfunc_arg_size(&func_vt);
838 if (size > 8) {
839 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
840 func_vc = addr;
841 reg_param_index++;
842 addr += 8;
843 }
844
845 /* define parameters */
846 while ((sym = sym->next) != NULL) {
847 type = &sym->type;
848 bt = type->t & VT_BTYPE;
849 size = gfunc_arg_size(type);
850 if (size > 8) {
851 if (reg_param_index < REGN) {
852 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
853 }
854 sym_push(sym->v & ~SYM_FIELD, type, VT_LOCAL | VT_LVAL | VT_REF, addr);
855 } else {
856 if (reg_param_index < REGN) {
857 /* save arguments passed by register */
858 if ((bt == VT_FLOAT) || (bt == VT_DOUBLE)) {
859 o(0xd60f66); /* movq */
860 gen_modrm(reg_param_index, VT_LOCAL, NULL, addr);
861 } else {
862 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
863 }
864 }
865 sym_push(sym->v & ~SYM_FIELD, type, VT_LOCAL | VT_LVAL, addr);
866 }
867 addr += 8;
868 reg_param_index++;
869 }
870
871 while (reg_param_index < REGN) {
872 if (func_type->ref->c == FUNC_ELLIPSIS) {
873 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
874 addr += 8;
875 }
876 reg_param_index++;
877 }
878 }
879
880 /* generate function epilog */
881 void gfunc_epilog(void)
882 {
883 int v, saved_ind;
884
885 o(0xc9); /* leave */
886 if (func_ret_sub == 0) {
887 o(0xc3); /* ret */
888 } else {
889 o(0xc2); /* ret n */
890 g(func_ret_sub);
891 g(func_ret_sub >> 8);
892 }
893
894 saved_ind = ind;
895 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
896 /* align local size to word & save local variables */
897 v = (func_scratch + -loc + 15) & -16;
898
899 if (v >= 4096) {
900 Sym *sym = external_global_sym(TOK___chkstk, &func_old_type, 0);
901 oad(0xb8, v); /* mov stacksize, %eax */
902 oad(0xe8, -4); /* call __chkstk, (does the stackframe too) */
903 greloc(cur_text_section, sym, ind-4, R_X86_64_PC32);
904 o(0x90); /* fill for FUNC_PROLOG_SIZE = 11 bytes */
905 } else {
906 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
907 o(0xec8148); /* sub rsp, stacksize */
908 gen_le32(v);
909 }
910
911 cur_text_section->data_offset = saved_ind;
912 pe_add_unwind_data(ind, saved_ind, v);
913 ind = cur_text_section->data_offset;
914 }
915
916 #else
917
918 static void gadd_sp(int val)
919 {
920 if (val == (char)val) {
921 o(0xc48348);
922 g(val);
923 } else {
924 oad(0xc48148, val); /* add $xxx, %rsp */
925 }
926 }
927
928 typedef enum X86_64_Mode {
929 x86_64_mode_none,
930 x86_64_mode_memory,
931 x86_64_mode_integer,
932 x86_64_mode_sse,
933 x86_64_mode_x87
934 } X86_64_Mode;
935
936 static X86_64_Mode classify_x86_64_merge(X86_64_Mode a, X86_64_Mode b)
937 {
938 if (a == b)
939 return a;
940 else if (a == x86_64_mode_none)
941 return b;
942 else if (b == x86_64_mode_none)
943 return a;
944 else if ((a == x86_64_mode_memory) || (b == x86_64_mode_memory))
945 return x86_64_mode_memory;
946 else if ((a == x86_64_mode_integer) || (b == x86_64_mode_integer))
947 return x86_64_mode_integer;
948 else if ((a == x86_64_mode_x87) || (b == x86_64_mode_x87))
949 return x86_64_mode_memory;
950 else
951 return x86_64_mode_sse;
952 }
953
954 static X86_64_Mode classify_x86_64_inner(CType *ty)
955 {
956 X86_64_Mode mode;
957 Sym *f;
958
959 switch (ty->t & VT_BTYPE) {
960 case VT_VOID: return x86_64_mode_none;
961
962 case VT_INT:
963 case VT_BYTE:
964 case VT_SHORT:
965 case VT_LLONG:
966 case VT_BOOL:
967 case VT_PTR:
968 case VT_FUNC:
969 case VT_ENUM: return x86_64_mode_integer;
970
971 case VT_FLOAT:
972 case VT_DOUBLE: return x86_64_mode_sse;
973
974 case VT_LDOUBLE: return x86_64_mode_x87;
975
976 case VT_STRUCT:
977 f = ty->ref;
978
979 // Detect union
980 if (f->next && (f->c == f->next->c))
981 return x86_64_mode_memory;
982
983 mode = x86_64_mode_none;
984 for (; f; f = f->next)
985 mode = classify_x86_64_merge(mode, classify_x86_64_inner(&f->type));
986
987 return mode;
988 }
989
990 assert(0);
991 }
992
993 static X86_64_Mode classify_x86_64_arg(CType *ty, CType *ret, int *psize, int *palign, int *reg_count)
994 {
995 X86_64_Mode mode;
996 int size, align, ret_t = 0;
997
998 if (ty->t & (VT_BITFIELD|VT_ARRAY)) {
999 *psize = 8;
1000 *palign = 8;
1001 *reg_count = 1;
1002 ret_t = ty->t;
1003 mode = x86_64_mode_integer;
1004 } else {
1005 size = type_size(ty, &align);
1006 *psize = (size + 7) & ~7;
1007 *palign = (align + 7) & ~7;
1008
1009 if (size > 16) {
1010 mode = x86_64_mode_memory;
1011 } else {
1012 mode = classify_x86_64_inner(ty);
1013 switch (mode) {
1014 case x86_64_mode_integer:
1015 if (size > 8) {
1016 *reg_count = 2;
1017 ret_t = VT_QLONG;
1018 } else {
1019 *reg_count = 1;
1020 ret_t = (size > 4) ? VT_LLONG : VT_INT;
1021 }
1022 break;
1023
1024 case x86_64_mode_x87:
1025 *reg_count = 1;
1026 ret_t = VT_LDOUBLE;
1027 break;
1028
1029 case x86_64_mode_sse:
1030 if (size > 8) {
1031 *reg_count = 2;
1032 ret_t = VT_QFLOAT;
1033 } else {
1034 *reg_count = 1;
1035 ret_t = (size > 4) ? VT_DOUBLE : VT_FLOAT;
1036 }
1037 break;
1038 default: break; /* nothing to be done for x86_64_mode_memory and x86_64_mode_none*/
1039 }
1040 }
1041 }
1042
1043 if (ret) {
1044 ret->ref = NULL;
1045 ret->t = ret_t;
1046 }
1047
1048 return mode;
1049 }
1050
1051 ST_FUNC int classify_x86_64_va_arg(CType *ty)
1052 {
1053 /* This definition must be synced with stdarg.h */
1054 enum __va_arg_type {
1055 __va_gen_reg, __va_float_reg, __va_stack
1056 };
1057 int size, align, reg_count;
1058 X86_64_Mode mode = classify_x86_64_arg(ty, NULL, &size, &align, &reg_count);
1059 switch (mode) {
1060 default: return __va_stack;
1061 case x86_64_mode_integer: return __va_gen_reg;
1062 case x86_64_mode_sse: return __va_float_reg;
1063 }
1064 }
1065
1066 /* Return the number of registers needed to return the struct, or 0 if
1067 returning via struct pointer. */
1068 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align)
1069 {
1070 int size, align, reg_count;
1071 *ret_align = 1; // Never have to re-align return values for x86-64
1072 return (classify_x86_64_arg(vt, ret, &size, &align, &reg_count) != x86_64_mode_memory);
1073 }
1074
1075 #define REGN 6
1076 static const uint8_t arg_regs[REGN] = {
1077 TREG_RDI, TREG_RSI, TREG_RDX, TREG_RCX, TREG_R8, TREG_R9
1078 };
1079
1080 static int arg_prepare_reg(int idx) {
1081 if (idx == 2 || idx == 3)
1082 /* idx=2: r10, idx=3: r11 */
1083 return idx + 8;
1084 else
1085 return arg_regs[idx];
1086 }
1087
1088 /* Generate function call. The function address is pushed first, then
1089 all the parameters in call order. This functions pops all the
1090 parameters and the function address. */
1091 void gfunc_call(int nb_args)
1092 {
1093 X86_64_Mode mode;
1094 CType type;
1095 int size, align, r, args_size, stack_adjust, run_start, run_end, i, reg_count;
1096 int nb_reg_args = 0;
1097 int nb_sse_args = 0;
1098 int sse_reg, gen_reg;
1099
1100 /* calculate the number of integer/float register arguments */
1101 for(i = 0; i < nb_args; i++) {
1102 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1103 if (mode == x86_64_mode_sse)
1104 nb_sse_args += reg_count;
1105 else if (mode == x86_64_mode_integer)
1106 nb_reg_args += reg_count;
1107 }
1108
1109 /* arguments are collected in runs. Each run is a collection of 8-byte aligned arguments
1110 and ended by a 16-byte aligned argument. This is because, from the point of view of
1111 the callee, argument alignment is computed from the bottom up. */
1112 /* for struct arguments, we need to call memcpy and the function
1113 call breaks register passing arguments we are preparing.
1114 So, we process arguments which will be passed by stack first. */
1115 gen_reg = nb_reg_args;
1116 sse_reg = nb_sse_args;
1117 run_start = 0;
1118 args_size = 0;
1119 while (run_start != nb_args) {
1120 int run_gen_reg = gen_reg, run_sse_reg = sse_reg;
1121
1122 run_end = nb_args;
1123 stack_adjust = 0;
1124 for(i = run_start; (i < nb_args) && (run_end == nb_args); i++) {
1125 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1126 switch (mode) {
1127 case x86_64_mode_memory:
1128 case x86_64_mode_x87:
1129 stack_arg:
1130 if (align == 16)
1131 run_end = i;
1132 else
1133 stack_adjust += size;
1134 break;
1135
1136 case x86_64_mode_sse:
1137 sse_reg -= reg_count;
1138 if (sse_reg + reg_count > 8) goto stack_arg;
1139 break;
1140
1141 case x86_64_mode_integer:
1142 gen_reg -= reg_count;
1143 if (gen_reg + reg_count > REGN) goto stack_arg;
1144 break;
1145 default: break; /* nothing to be done for x86_64_mode_none */
1146 }
1147 }
1148
1149 gen_reg = run_gen_reg;
1150 sse_reg = run_sse_reg;
1151
1152 /* adjust stack to align SSE boundary */
1153 if (stack_adjust &= 15) {
1154 /* fetch cpu flag before the following sub will change the value */
1155 if (vtop >= vstack && (vtop->r & VT_VALMASK) == VT_CMP)
1156 gv(RC_INT);
1157
1158 stack_adjust = 16 - stack_adjust;
1159 o(0x48);
1160 oad(0xec81, stack_adjust); /* sub $xxx, %rsp */
1161 args_size += stack_adjust;
1162 }
1163
1164 for(i = run_start; i < run_end;) {
1165 /* Swap argument to top, it will possibly be changed here,
1166 and might use more temps. At the end of the loop we keep
1167 in on the stack and swap it back to its original position
1168 if it is a register. */
1169 SValue tmp = vtop[0];
1170 vtop[0] = vtop[-i];
1171 vtop[-i] = tmp;
1172
1173 mode = classify_x86_64_arg(&vtop->type, NULL, &size, &align, &reg_count);
1174
1175 int arg_stored = 1;
1176 switch (vtop->type.t & VT_BTYPE) {
1177 case VT_STRUCT:
1178 if (mode == x86_64_mode_sse) {
1179 if (sse_reg > 8)
1180 sse_reg -= reg_count;
1181 else
1182 arg_stored = 0;
1183 } else if (mode == x86_64_mode_integer) {
1184 if (gen_reg > REGN)
1185 gen_reg -= reg_count;
1186 else
1187 arg_stored = 0;
1188 }
1189
1190 if (arg_stored) {
1191 /* allocate the necessary size on stack */
1192 o(0x48);
1193 oad(0xec81, size); /* sub $xxx, %rsp */
1194 /* generate structure store */
1195 r = get_reg(RC_INT);
1196 orex(1, r, 0, 0x89); /* mov %rsp, r */
1197 o(0xe0 + REG_VALUE(r));
1198 vset(&vtop->type, r | VT_LVAL, 0);
1199 vswap();
1200 vstore();
1201 args_size += size;
1202 }
1203 break;
1204
1205 case VT_LDOUBLE:
1206 assert(0);
1207 break;
1208
1209 case VT_FLOAT:
1210 case VT_DOUBLE:
1211 assert(mode == x86_64_mode_sse);
1212 if (sse_reg > 8) {
1213 --sse_reg;
1214 r = gv(RC_FLOAT);
1215 o(0x50); /* push $rax */
1216 /* movq %xmmN, (%rsp) */
1217 o(0xd60f66);
1218 o(0x04 + REG_VALUE(r)*8);
1219 o(0x24);
1220 args_size += size;
1221 } else {
1222 arg_stored = 0;
1223 }
1224 break;
1225
1226 default:
1227 assert(mode == x86_64_mode_integer);
1228 /* simple type */
1229 /* XXX: implicit cast ? */
1230 if (gen_reg > REGN) {
1231 --gen_reg;
1232 r = gv(RC_INT);
1233 orex(0,r,0,0x50 + REG_VALUE(r)); /* push r */
1234 args_size += size;
1235 } else {
1236 arg_stored = 0;
1237 }
1238 break;
1239 }
1240
1241 /* And swap the argument back to it's original position. */
1242 tmp = vtop[0];
1243 vtop[0] = vtop[-i];
1244 vtop[-i] = tmp;
1245
1246 if (arg_stored) {
1247 vrotb(i+1);
1248 assert((vtop->type.t == tmp.type.t) && (vtop->r == tmp.r));
1249 vpop();
1250 --nb_args;
1251 --run_end;
1252 } else {
1253 ++i;
1254 }
1255 }
1256
1257 /* handle 16 byte aligned arguments at end of run */
1258 run_start = i = run_end;
1259 while (i < nb_args) {
1260 /* Rotate argument to top since it will always be popped */
1261 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1262 if (align != 16)
1263 break;
1264
1265 vrotb(i+1);
1266
1267 if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
1268 gv(RC_ST0);
1269 oad(0xec8148, size); /* sub $xxx, %rsp */
1270 o(0x7cdb); /* fstpt 0(%rsp) */
1271 g(0x24);
1272 g(0x00);
1273 args_size += size;
1274 } else {
1275 assert(mode == x86_64_mode_memory);
1276
1277 /* allocate the necessary size on stack */
1278 o(0x48);
1279 oad(0xec81, size); /* sub $xxx, %rsp */
1280 /* generate structure store */
1281 r = get_reg(RC_INT);
1282 orex(1, r, 0, 0x89); /* mov %rsp, r */
1283 o(0xe0 + REG_VALUE(r));
1284 vset(&vtop->type, r | VT_LVAL, 0);
1285 vswap();
1286 vstore();
1287 args_size += size;
1288 }
1289
1290 vpop();
1291 --nb_args;
1292 }
1293 }
1294
1295 /* XXX This should be superfluous. */
1296 save_regs(0); /* save used temporary registers */
1297
1298 /* then, we prepare register passing arguments.
1299 Note that we cannot set RDX and RCX in this loop because gv()
1300 may break these temporary registers. Let's use R10 and R11
1301 instead of them */
1302 assert(gen_reg <= REGN);
1303 assert(sse_reg <= 8);
1304 for(i = 0; i < nb_args; i++) {
1305 mode = classify_x86_64_arg(&vtop->type, &type, &size, &align, &reg_count);
1306 /* Alter stack entry type so that gv() knows how to treat it */
1307 vtop->type = type;
1308 if (mode == x86_64_mode_sse) {
1309 if (reg_count == 2) {
1310 sse_reg -= 2;
1311 gv(RC_FRET); /* Use pair load into xmm0 & xmm1 */
1312 if (sse_reg) { /* avoid redundant movaps %xmm0, %xmm0 */
1313 /* movaps %xmm0, %xmmN */
1314 o(0x280f);
1315 o(0xc0 + (sse_reg << 3));
1316 /* movaps %xmm1, %xmmN */
1317 o(0x280f);
1318 o(0xc1 + ((sse_reg+1) << 3));
1319 }
1320 } else {
1321 assert(reg_count == 1);
1322 --sse_reg;
1323 /* Load directly to register */
1324 gv(RC_XMM0 << sse_reg);
1325 }
1326 } else if (mode == x86_64_mode_integer) {
1327 /* simple type */
1328 /* XXX: implicit cast ? */
1329 gen_reg -= reg_count;
1330 r = gv(RC_INT);
1331 int d = arg_prepare_reg(gen_reg);
1332 orex(1,d,r,0x89); /* mov */
1333 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
1334 if (reg_count == 2) {
1335 d = arg_prepare_reg(gen_reg+1);
1336 orex(1,d,vtop->r2,0x89); /* mov */
1337 o(0xc0 + REG_VALUE(vtop->r2) * 8 + REG_VALUE(d));
1338 }
1339 }
1340 vtop--;
1341 }
1342 assert(gen_reg == 0);
1343 assert(sse_reg == 0);
1344
1345 /* We shouldn't have many operands on the stack anymore, but the
1346 call address itself is still there, and it might be in %eax
1347 (or edx/ecx) currently, which the below writes would clobber.
1348 So evict all remaining operands here. */
1349 save_regs(0);
1350
1351 /* Copy R10 and R11 into RDX and RCX, respectively */
1352 if (nb_reg_args > 2) {
1353 o(0xd2894c); /* mov %r10, %rdx */
1354 if (nb_reg_args > 3) {
1355 o(0xd9894c); /* mov %r11, %rcx */
1356 }
1357 }
1358
1359 oad(0xb8, nb_sse_args < 8 ? nb_sse_args : 8); /* mov nb_sse_args, %eax */
1360 gcall_or_jmp(0);
1361 if (args_size)
1362 gadd_sp(args_size);
1363 vtop--;
1364 }
1365
1366
1367 #define FUNC_PROLOG_SIZE 11
1368
1369 static void push_arg_reg(int i) {
1370 loc -= 8;
1371 gen_modrm64(0x89, arg_regs[i], VT_LOCAL, NULL, loc);
1372 }
1373
1374 /* generate function prolog of type 't' */
1375 void gfunc_prolog(CType *func_type)
1376 {
1377 X86_64_Mode mode;
1378 int i, addr, align, size, reg_count;
1379 int param_addr = 0, reg_param_index, sse_param_index;
1380 Sym *sym;
1381 CType *type;
1382
1383 sym = func_type->ref;
1384 addr = PTR_SIZE * 2;
1385 loc = 0;
1386 ind += FUNC_PROLOG_SIZE;
1387 func_sub_sp_offset = ind;
1388 func_ret_sub = 0;
1389
1390 if (func_type->ref->c == FUNC_ELLIPSIS) {
1391 int seen_reg_num, seen_sse_num, seen_stack_size;
1392 seen_reg_num = seen_sse_num = 0;
1393 /* frame pointer and return address */
1394 seen_stack_size = PTR_SIZE * 2;
1395 /* count the number of seen parameters */
1396 sym = func_type->ref;
1397 while ((sym = sym->next) != NULL) {
1398 type = &sym->type;
1399 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1400 switch (mode) {
1401 default:
1402 stack_arg:
1403 seen_stack_size = ((seen_stack_size + align - 1) & -align) + size;
1404 break;
1405
1406 case x86_64_mode_integer:
1407 if (seen_reg_num + reg_count <= 8) {
1408 seen_reg_num += reg_count;
1409 } else {
1410 seen_reg_num = 8;
1411 goto stack_arg;
1412 }
1413 break;
1414
1415 case x86_64_mode_sse:
1416 if (seen_sse_num + reg_count <= 8) {
1417 seen_sse_num += reg_count;
1418 } else {
1419 seen_sse_num = 8;
1420 goto stack_arg;
1421 }
1422 break;
1423 }
1424 }
1425
1426 loc -= 16;
1427 /* movl $0x????????, -0x10(%rbp) */
1428 o(0xf045c7);
1429 gen_le32(seen_reg_num * 8);
1430 /* movl $0x????????, -0xc(%rbp) */
1431 o(0xf445c7);
1432 gen_le32(seen_sse_num * 16 + 48);
1433 /* movl $0x????????, -0x8(%rbp) */
1434 o(0xf845c7);
1435 gen_le32(seen_stack_size);
1436
1437 /* save all register passing arguments */
1438 for (i = 0; i < 8; i++) {
1439 loc -= 16;
1440 o(0xd60f66); /* movq */
1441 gen_modrm(7 - i, VT_LOCAL, NULL, loc);
1442 /* movq $0, loc+8(%rbp) */
1443 o(0x85c748);
1444 gen_le32(loc + 8);
1445 gen_le32(0);
1446 }
1447 for (i = 0; i < REGN; i++) {
1448 push_arg_reg(REGN-1-i);
1449 }
1450 }
1451
1452 sym = func_type->ref;
1453 reg_param_index = 0;
1454 sse_param_index = 0;
1455
1456 /* if the function returns a structure, then add an
1457 implicit pointer parameter */
1458 func_vt = sym->type;
1459 mode = classify_x86_64_arg(&func_vt, NULL, &size, &align, &reg_count);
1460 if (mode == x86_64_mode_memory) {
1461 push_arg_reg(reg_param_index);
1462 func_vc = loc;
1463 reg_param_index++;
1464 }
1465 /* define parameters */
1466 while ((sym = sym->next) != NULL) {
1467 type = &sym->type;
1468 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1469 switch (mode) {
1470 case x86_64_mode_sse:
1471 if (sse_param_index + reg_count <= 8) {
1472 /* save arguments passed by register */
1473 loc -= reg_count * 8;
1474 param_addr = loc;
1475 for (i = 0; i < reg_count; ++i) {
1476 o(0xd60f66); /* movq */
1477 gen_modrm(sse_param_index, VT_LOCAL, NULL, param_addr + i*8);
1478 ++sse_param_index;
1479 }
1480 } else {
1481 addr = (addr + align - 1) & -align;
1482 param_addr = addr;
1483 addr += size;
1484 sse_param_index += reg_count;
1485 }
1486 break;
1487
1488 case x86_64_mode_memory:
1489 case x86_64_mode_x87:
1490 addr = (addr + align - 1) & -align;
1491 param_addr = addr;
1492 addr += size;
1493 break;
1494
1495 case x86_64_mode_integer: {
1496 if (reg_param_index + reg_count <= REGN) {
1497 /* save arguments passed by register */
1498 loc -= reg_count * 8;
1499 param_addr = loc;
1500 for (i = 0; i < reg_count; ++i) {
1501 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, param_addr + i*8);
1502 ++reg_param_index;
1503 }
1504 } else {
1505 addr = (addr + align - 1) & -align;
1506 param_addr = addr;
1507 addr += size;
1508 reg_param_index += reg_count;
1509 }
1510 break;
1511 }
1512 default: break; /* nothing to be done for x86_64_mode_none */
1513 }
1514 sym_push(sym->v & ~SYM_FIELD, type,
1515 VT_LOCAL | VT_LVAL, param_addr);
1516 }
1517 }
1518
1519 /* generate function epilog */
1520 void gfunc_epilog(void)
1521 {
1522 int v, saved_ind;
1523
1524 o(0xc9); /* leave */
1525 if (func_ret_sub == 0) {
1526 o(0xc3); /* ret */
1527 } else {
1528 o(0xc2); /* ret n */
1529 g(func_ret_sub);
1530 g(func_ret_sub >> 8);
1531 }
1532 /* align local size to word & save local variables */
1533 v = (-loc + 15) & -16;
1534 saved_ind = ind;
1535 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
1536 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1537 o(0xec8148); /* sub rsp, stacksize */
1538 gen_le32(v);
1539 ind = saved_ind;
1540 }
1541
1542 #endif /* not PE */
1543
1544 /* generate a jump to a label */
1545 int gjmp(int t)
1546 {
1547 return psym(0xe9, t);
1548 }
1549
1550 /* generate a jump to a fixed address */
1551 void gjmp_addr(int a)
1552 {
1553 int r;
1554 r = a - ind - 2;
1555 if (r == (char)r) {
1556 g(0xeb);
1557 g(r);
1558 } else {
1559 oad(0xe9, a - ind - 5);
1560 }
1561 }
1562
1563 /* generate a test. set 'inv' to invert test. Stack entry is popped */
1564 int gtst(int inv, int t)
1565 {
1566 int v, *p;
1567
1568 v = vtop->r & VT_VALMASK;
1569 if (v == VT_CMP) {
1570 /* fast case : can jump directly since flags are set */
1571 if (vtop->c.i & 0x100)
1572 {
1573 /* This was a float compare. If the parity flag is set
1574 the result was unordered. For anything except != this
1575 means false and we don't jump (anding both conditions).
1576 For != this means true (oring both).
1577 Take care about inverting the test. We need to jump
1578 to our target if the result was unordered and test wasn't NE,
1579 otherwise if unordered we don't want to jump. */
1580 vtop->c.i &= ~0x100;
1581 if (!inv == (vtop->c.i != TOK_NE))
1582 o(0x067a); /* jp +6 */
1583 else
1584 {
1585 g(0x0f);
1586 t = psym(0x8a, t); /* jp t */
1587 }
1588 }
1589 g(0x0f);
1590 t = psym((vtop->c.i - 16) ^ inv, t);
1591 } else { /* VT_JMP || VT_JMPI */
1592 /* && or || optimization */
1593 if ((v & 1) == inv) {
1594 /* insert vtop->c jump list in t */
1595 p = &vtop->c.i;
1596 while (*p != 0)
1597 p = (int *)(cur_text_section->data + *p);
1598 *p = t;
1599 t = vtop->c.i;
1600 } else {
1601 t = gjmp(t);
1602 gsym(vtop->c.i);
1603 }
1604 }
1605 vtop--;
1606 return t;
1607 }
1608
1609 /* generate an integer binary operation */
1610 void gen_opi(int op)
1611 {
1612 int r, fr, opc, c;
1613 int ll, uu, cc;
1614
1615 ll = is64_type(vtop[-1].type.t);
1616 uu = (vtop[-1].type.t & VT_UNSIGNED) != 0;
1617 cc = (vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST;
1618
1619 switch(op) {
1620 case '+':
1621 case TOK_ADDC1: /* add with carry generation */
1622 opc = 0;
1623 gen_op8:
1624 if (cc && (!ll || (int)vtop->c.ll == vtop->c.ll)) {
1625 /* constant case */
1626 vswap();
1627 r = gv(RC_INT);
1628 vswap();
1629 c = vtop->c.i;
1630 if (c == (char)c) {
1631 /* XXX: generate inc and dec for smaller code ? */
1632 orex(ll, r, 0, 0x83);
1633 o(0xc0 | (opc << 3) | REG_VALUE(r));
1634 g(c);
1635 } else {
1636 orex(ll, r, 0, 0x81);
1637 oad(0xc0 | (opc << 3) | REG_VALUE(r), c);
1638 }
1639 } else {
1640 gv2(RC_INT, RC_INT);
1641 r = vtop[-1].r;
1642 fr = vtop[0].r;
1643 orex(ll, r, fr, (opc << 3) | 0x01);
1644 o(0xc0 + REG_VALUE(r) + REG_VALUE(fr) * 8);
1645 }
1646 vtop--;
1647 if (op >= TOK_ULT && op <= TOK_GT) {
1648 vtop->r = VT_CMP;
1649 vtop->c.i = op;
1650 }
1651 break;
1652 case '-':
1653 case TOK_SUBC1: /* sub with carry generation */
1654 opc = 5;
1655 goto gen_op8;
1656 case TOK_ADDC2: /* add with carry use */
1657 opc = 2;
1658 goto gen_op8;
1659 case TOK_SUBC2: /* sub with carry use */
1660 opc = 3;
1661 goto gen_op8;
1662 case '&':
1663 opc = 4;
1664 goto gen_op8;
1665 case '^':
1666 opc = 6;
1667 goto gen_op8;
1668 case '|':
1669 opc = 1;
1670 goto gen_op8;
1671 case '*':
1672 gv2(RC_INT, RC_INT);
1673 r = vtop[-1].r;
1674 fr = vtop[0].r;
1675 orex(ll, fr, r, 0xaf0f); /* imul fr, r */
1676 o(0xc0 + REG_VALUE(fr) + REG_VALUE(r) * 8);
1677 vtop--;
1678 break;
1679 case TOK_SHL:
1680 opc = 4;
1681 goto gen_shift;
1682 case TOK_SHR:
1683 opc = 5;
1684 goto gen_shift;
1685 case TOK_SAR:
1686 opc = 7;
1687 gen_shift:
1688 opc = 0xc0 | (opc << 3);
1689 if (cc) {
1690 /* constant case */
1691 vswap();
1692 r = gv(RC_INT);
1693 vswap();
1694 orex(ll, r, 0, 0xc1); /* shl/shr/sar $xxx, r */
1695 o(opc | REG_VALUE(r));
1696 g(vtop->c.i & (ll ? 63 : 31));
1697 } else {
1698 /* we generate the shift in ecx */
1699 gv2(RC_INT, RC_RCX);
1700 r = vtop[-1].r;
1701 orex(ll, r, 0, 0xd3); /* shl/shr/sar %cl, r */
1702 o(opc | REG_VALUE(r));
1703 }
1704 vtop--;
1705 break;
1706 case TOK_UDIV:
1707 case TOK_UMOD:
1708 uu = 1;
1709 goto divmod;
1710 case '/':
1711 case '%':
1712 case TOK_PDIV:
1713 uu = 0;
1714 divmod:
1715 /* first operand must be in eax */
1716 /* XXX: need better constraint for second operand */
1717 gv2(RC_RAX, RC_RCX);
1718 r = vtop[-1].r;
1719 fr = vtop[0].r;
1720 vtop--;
1721 save_reg(TREG_RDX);
1722 orex(ll, 0, 0, uu ? 0xd231 : 0x99); /* xor %edx,%edx : cqto */
1723 orex(ll, fr, 0, 0xf7); /* div fr, %eax */
1724 o((uu ? 0xf0 : 0xf8) + REG_VALUE(fr));
1725 if (op == '%' || op == TOK_UMOD)
1726 r = TREG_RDX;
1727 else
1728 r = TREG_RAX;
1729 vtop->r = r;
1730 break;
1731 default:
1732 opc = 7;
1733 goto gen_op8;
1734 }
1735 }
1736
1737 void gen_opl(int op)
1738 {
1739 gen_opi(op);
1740 }
1741
1742 /* generate a floating point operation 'v = t1 op t2' instruction. The
1743 two operands are guaranted to have the same floating point type */
1744 /* XXX: need to use ST1 too */
1745 void gen_opf(int op)
1746 {
1747 int a, ft, fc, swapped, r;
1748 int float_type =
1749 (vtop->type.t & VT_BTYPE) == VT_LDOUBLE ? RC_ST0 : RC_FLOAT;
1750
1751 /* convert constants to memory references */
1752 if ((vtop[-1].r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
1753 vswap();
1754 gv(float_type);
1755 vswap();
1756 }
1757 if ((vtop[0].r & (VT_VALMASK | VT_LVAL)) == VT_CONST)
1758 gv(float_type);
1759
1760 /* must put at least one value in the floating point register */
1761 if ((vtop[-1].r & VT_LVAL) &&
1762 (vtop[0].r & VT_LVAL)) {
1763 vswap();
1764 gv(float_type);
1765 vswap();
1766 }
1767 swapped = 0;
1768 /* swap the stack if needed so that t1 is the register and t2 is
1769 the memory reference */
1770 if (vtop[-1].r & VT_LVAL) {
1771 vswap();
1772 swapped = 1;
1773 }
1774 if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
1775 if (op >= TOK_ULT && op <= TOK_GT) {
1776 /* load on stack second operand */
1777 load(TREG_ST0, vtop);
1778 save_reg(TREG_RAX); /* eax is used by FP comparison code */
1779 if (op == TOK_GE || op == TOK_GT)
1780 swapped = !swapped;
1781 else if (op == TOK_EQ || op == TOK_NE)
1782 swapped = 0;
1783 if (swapped)
1784 o(0xc9d9); /* fxch %st(1) */
1785 if (op == TOK_EQ || op == TOK_NE)
1786 o(0xe9da); /* fucompp */
1787 else
1788 o(0xd9de); /* fcompp */
1789 o(0xe0df); /* fnstsw %ax */
1790 if (op == TOK_EQ) {
1791 o(0x45e480); /* and $0x45, %ah */
1792 o(0x40fC80); /* cmp $0x40, %ah */
1793 } else if (op == TOK_NE) {
1794 o(0x45e480); /* and $0x45, %ah */
1795 o(0x40f480); /* xor $0x40, %ah */
1796 op = TOK_NE;
1797 } else if (op == TOK_GE || op == TOK_LE) {
1798 o(0x05c4f6); /* test $0x05, %ah */
1799 op = TOK_EQ;
1800 } else {
1801 o(0x45c4f6); /* test $0x45, %ah */
1802 op = TOK_EQ;
1803 }
1804 vtop--;
1805 vtop->r = VT_CMP;
1806 vtop->c.i = op;
1807 } else {
1808 /* no memory reference possible for long double operations */
1809 load(TREG_ST0, vtop);
1810 swapped = !swapped;
1811
1812 switch(op) {
1813 default:
1814 case '+':
1815 a = 0;
1816 break;
1817 case '-':
1818 a = 4;
1819 if (swapped)
1820 a++;
1821 break;
1822 case '*':
1823 a = 1;
1824 break;
1825 case '/':
1826 a = 6;
1827 if (swapped)
1828 a++;
1829 break;
1830 }
1831 ft = vtop->type.t;
1832 fc = vtop->c.ul;
1833 o(0xde); /* fxxxp %st, %st(1) */
1834 o(0xc1 + (a << 3));
1835 vtop--;
1836 }
1837 } else {
1838 if (op >= TOK_ULT && op <= TOK_GT) {
1839 /* if saved lvalue, then we must reload it */
1840 r = vtop->r;
1841 fc = vtop->c.ul;
1842 if ((r & VT_VALMASK) == VT_LLOCAL) {
1843 SValue v1;
1844 r = get_reg(RC_INT);
1845 v1.type.t = VT_PTR;
1846 v1.r = VT_LOCAL | VT_LVAL;
1847 v1.c.ul = fc;
1848 load(r, &v1);
1849 fc = 0;
1850 }
1851
1852 if (op == TOK_EQ || op == TOK_NE) {
1853 swapped = 0;
1854 } else {
1855 if (op == TOK_LE || op == TOK_LT)
1856 swapped = !swapped;
1857 if (op == TOK_LE || op == TOK_GE) {
1858 op = 0x93; /* setae */
1859 } else {
1860 op = 0x97; /* seta */
1861 }
1862 }
1863
1864 if (swapped) {
1865 gv(RC_FLOAT);
1866 vswap();
1867 }
1868 assert(!(vtop[-1].r & VT_LVAL));
1869
1870 if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
1871 o(0x66);
1872 if (op == TOK_EQ || op == TOK_NE)
1873 o(0x2e0f); /* ucomisd */
1874 else
1875 o(0x2f0f); /* comisd */
1876
1877 if (vtop->r & VT_LVAL) {
1878 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
1879 } else {
1880 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
1881 }
1882
1883 vtop--;
1884 vtop->r = VT_CMP;
1885 vtop->c.i = op | 0x100;
1886 } else {
1887 assert((vtop->type.t & VT_BTYPE) != VT_LDOUBLE);
1888 switch(op) {
1889 default:
1890 case '+':
1891 a = 0;
1892 break;
1893 case '-':
1894 a = 4;
1895 break;
1896 case '*':
1897 a = 1;
1898 break;
1899 case '/':
1900 a = 6;
1901 break;
1902 }
1903 ft = vtop->type.t;
1904 fc = vtop->c.ul;
1905 assert((ft & VT_BTYPE) != VT_LDOUBLE);
1906
1907 r = vtop->r;
1908 /* if saved lvalue, then we must reload it */
1909 if ((vtop->r & VT_VALMASK) == VT_LLOCAL) {
1910 SValue v1;
1911 r = get_reg(RC_INT);
1912 v1.type.t = VT_PTR;
1913 v1.r = VT_LOCAL | VT_LVAL;
1914 v1.c.ul = fc;
1915 load(r, &v1);
1916 fc = 0;
1917 }
1918
1919 assert(!(vtop[-1].r & VT_LVAL));
1920 if (swapped) {
1921 assert(vtop->r & VT_LVAL);
1922 gv(RC_FLOAT);
1923 vswap();
1924 }
1925
1926 if ((ft & VT_BTYPE) == VT_DOUBLE) {
1927 o(0xf2);
1928 } else {
1929 o(0xf3);
1930 }
1931 o(0x0f);
1932 o(0x58 + a);
1933
1934 if (vtop->r & VT_LVAL) {
1935 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
1936 } else {
1937 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
1938 }
1939
1940 vtop--;
1941 }
1942 }
1943 }
1944
1945 /* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
1946 and 'long long' cases. */
1947 void gen_cvt_itof(int t)
1948 {
1949 if ((t & VT_BTYPE) == VT_LDOUBLE) {
1950 save_reg(TREG_ST0);
1951 gv(RC_INT);
1952 if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
1953 /* signed long long to float/double/long double (unsigned case
1954 is handled generically) */
1955 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
1956 o(0x242cdf); /* fildll (%rsp) */
1957 o(0x08c48348); /* add $8, %rsp */
1958 } else if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
1959 (VT_INT | VT_UNSIGNED)) {
1960 /* unsigned int to float/double/long double */
1961 o(0x6a); /* push $0 */
1962 g(0x00);
1963 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
1964 o(0x242cdf); /* fildll (%rsp) */
1965 o(0x10c48348); /* add $16, %rsp */
1966 } else {
1967 /* int to float/double/long double */
1968 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
1969 o(0x2404db); /* fildl (%rsp) */
1970 o(0x08c48348); /* add $8, %rsp */
1971 }
1972 vtop->r = TREG_ST0;
1973 } else {
1974 int r = get_reg(RC_FLOAT);
1975 gv(RC_INT);
1976 o(0xf2 + ((t & VT_BTYPE) == VT_FLOAT?1:0));
1977 if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
1978 (VT_INT | VT_UNSIGNED) ||
1979 (vtop->type.t & VT_BTYPE) == VT_LLONG) {
1980 o(0x48); /* REX */
1981 }
1982 o(0x2a0f);
1983 o(0xc0 + (vtop->r & VT_VALMASK) + REG_VALUE(r)*8); /* cvtsi2sd */
1984 vtop->r = r;
1985 }
1986 }
1987
1988 /* convert from one floating point type to another */
1989 void gen_cvt_ftof(int t)
1990 {
1991 int ft, bt, tbt;
1992
1993 ft = vtop->type.t;
1994 bt = ft & VT_BTYPE;
1995 tbt = t & VT_BTYPE;
1996
1997 if (bt == VT_FLOAT) {
1998 gv(RC_FLOAT);
1999 if (tbt == VT_DOUBLE) {
2000 o(0x140f); /* unpcklps */
2001 o(0xc0 + REG_VALUE(vtop->r)*9);
2002 o(0x5a0f); /* cvtps2pd */
2003 o(0xc0 + REG_VALUE(vtop->r)*9);
2004 } else if (tbt == VT_LDOUBLE) {
2005 save_reg(RC_ST0);
2006 /* movss %xmm0,-0x10(%rsp) */
2007 o(0x110ff3);
2008 o(0x44 + REG_VALUE(vtop->r)*8);
2009 o(0xf024);
2010 o(0xf02444d9); /* flds -0x10(%rsp) */
2011 vtop->r = TREG_ST0;
2012 }
2013 } else if (bt == VT_DOUBLE) {
2014 gv(RC_FLOAT);
2015 if (tbt == VT_FLOAT) {
2016 o(0x140f66); /* unpcklpd */
2017 o(0xc0 + REG_VALUE(vtop->r)*9);
2018 o(0x5a0f66); /* cvtpd2ps */
2019 o(0xc0 + REG_VALUE(vtop->r)*9);
2020 } else if (tbt == VT_LDOUBLE) {
2021 save_reg(RC_ST0);
2022 /* movsd %xmm0,-0x10(%rsp) */
2023 o(0x110ff2);
2024 o(0x44 + REG_VALUE(vtop->r)*8);
2025 o(0xf024);
2026 o(0xf02444dd); /* fldl -0x10(%rsp) */
2027 vtop->r = TREG_ST0;
2028 }
2029 } else {
2030 int r;
2031 gv(RC_ST0);
2032 r = get_reg(RC_FLOAT);
2033 if (tbt == VT_DOUBLE) {
2034 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
2035 /* movsd -0x10(%rsp),%xmm0 */
2036 o(0x100ff2);
2037 o(0x44 + REG_VALUE(r)*8);
2038 o(0xf024);
2039 vtop->r = r;
2040 } else if (tbt == VT_FLOAT) {
2041 o(0xf0245cd9); /* fstps -0x10(%rsp) */
2042 /* movss -0x10(%rsp),%xmm0 */
2043 o(0x100ff3);
2044 o(0x44 + REG_VALUE(r)*8);
2045 o(0xf024);
2046 vtop->r = r;
2047 }
2048 }
2049 }
2050
2051 /* convert fp to int 't' type */
2052 void gen_cvt_ftoi(int t)
2053 {
2054 int ft, bt, size, r;
2055 ft = vtop->type.t;
2056 bt = ft & VT_BTYPE;
2057 if (bt == VT_LDOUBLE) {
2058 gen_cvt_ftof(VT_DOUBLE);
2059 bt = VT_DOUBLE;
2060 }
2061
2062 gv(RC_FLOAT);
2063 if (t != VT_INT)
2064 size = 8;
2065 else
2066 size = 4;
2067
2068 r = get_reg(RC_INT);
2069 if (bt == VT_FLOAT) {
2070 o(0xf3);
2071 } else if (bt == VT_DOUBLE) {
2072 o(0xf2);
2073 } else {
2074 assert(0);
2075 }
2076 orex(size == 8, r, 0, 0x2c0f); /* cvttss2si or cvttsd2si */
2077 o(0xc0 + REG_VALUE(vtop->r) + REG_VALUE(r)*8);
2078 vtop->r = r;
2079 }
2080
2081 /* computed goto support */
2082 void ggoto(void)
2083 {
2084 gcall_or_jmp(1);
2085 vtop--;
2086 }
2087
2088 /* Save the stack pointer onto the stack and return the location of its address */
2089 ST_FUNC void gen_vla_sp_save(int addr) {
2090 /* mov %rsp,addr(%rbp)*/
2091 gen_modrm64(0x89, TREG_RSP, VT_LOCAL, NULL, addr);
2092 }
2093
2094 /* Restore the SP from a location on the stack */
2095 ST_FUNC void gen_vla_sp_restore(int addr) {
2096 gen_modrm64(0x8b, TREG_RSP, VT_LOCAL, NULL, addr);
2097 }
2098
2099 /* Subtract from the stack pointer, and push the resulting value onto the stack */
2100 ST_FUNC void gen_vla_alloc(CType *type, int align) {
2101 #ifdef TCC_TARGET_PE
2102 /* alloca does more than just adjust %rsp on Windows */
2103 vpush_global_sym(&func_old_type, TOK_alloca);
2104 vswap(); /* Move alloca ref past allocation size */
2105 gfunc_call(1);
2106 vset(type, REG_IRET, 0);
2107 #else
2108 int r;
2109 r = gv(RC_INT); /* allocation size */
2110 /* sub r,%rsp */
2111 o(0x2b48);
2112 o(0xe0 | REG_VALUE(r));
2113 /* We align to 16 bytes rather than align */
2114 /* and ~15, %rsp */
2115 o(0xf0e48348);
2116 /* mov %rsp, r */
2117 o(0x8948);
2118 o(0xe0 | REG_VALUE(r));
2119 vpop();
2120 vset(type, r, 0);
2121 #endif
2122 }
2123
2124
2125 /* end of x86-64 code generator */
2126 /*************************************************************/
2127 #endif /* ! TARGET_DEFS_ONLY */
2128 /******************************************************/