| commit | 0aca861194089e9122faa7d04717f45a9b412287 | |
| author | Ekaitz Zarraga <ekaitz@elenq.tech> | |
| Sat, 27 Apr 2024 22:13:01 +0000 (28 00:13 +0200) | ||
| committer | Ekaitz Zarraga <ekaitz@elenq.tech> | |
| Sat, 27 Apr 2024 22:15:23 +0000 (28 00:15 +0200) | ||
| tree | a4a98dbfea6de4955d1d35fa6606f3ea7728db47 | treesnapshot (tar.gz zip) |
| parent | 8baadb3b5529cca321d5e4cca748a1e533bf413a | commitdiff |
fixup! riscv: Implement large addend for global address
Use `t1` instead of `t0` for the cases when `rr` is not set so `t0` is
used by default and this happens:
lui t0, XXX
add t0, t0, t0
Instead, now we do:
lui t1, XXX
add t0, t0, t1
Use `t1` instead of `t0` for the cases when `rr` is not set so `t0` is
used by default and this happens:
lui t0, XXX
add t0, t0, t0
Instead, now we do:
lui t1, XXX
add t0, t0, t1
| riscv64-gen.c | diffblobblamehistory |