From 0aca861194089e9122faa7d04717f45a9b412287 Mon Sep 17 00:00:00 2001
From: Ekaitz Zarraga <ekaitz@elenq.tech>
Date: Sun, 28 Apr 2024 00:13:01 +0200
Subject: [PATCH] fixup! riscv: Implement large addend for global address

Use `t1` instead of `t0` for the cases when `rr` is not set so `t0` is
used by default and this happens:

    lui t0, XXX
    add t0, t0, t0

Instead, now we do:

    lui t1, XXX
    add t0, t0, t1
---
 riscv64-gen.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv64-gen.c b/riscv64-gen.c
index de48b5bc..76a9e49c 100644
--- a/riscv64-gen.c
+++ b/riscv64-gen.c
@@ -193,8 +193,8 @@ static int load_symofs(int r, SValue *sv, int forstore)
         if (doload) {
             EI(0x03, 3, rr, rr, 0); // ld RR, 0(RR)
             if (large_addend) {
-                o(0x37 | (5 << 7) | ((0x800 + fc) & 0xfffff000)); //lui t0, high(fc)
-                ER(0x33, 0, rr, rr, 5, 0); // add RR, RR, t0
+                o(0x37 | (6 << 7) | ((0x800 + fc) & 0xfffff000)); //lui t1, high(fc)
+                ER(0x33, 0, rr, rr, 6, 0); // add RR, RR, t1
                 sv->c.i = fc << 20 >> 20;
             }
         }
-- 
2.11.4.GIT