2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
21 #define CPU_NO_GLOBAL_REGS
27 #if !defined(CONFIG_SOFTMMU)
39 #include <sys/ucontext.h>
43 #if defined(__sparc__) && !defined(HOST_SOLARIS)
44 // Work around ugly bugs in glibc that mangle global register contents
46 #define env cpu_single_env
49 int tb_invalidated_flag
;
52 //#define DEBUG_SIGNAL
54 void cpu_loop_exit(void)
56 /* NOTE: the register at this point must be saved by hand because
57 longjmp restore them */
59 longjmp(env
->jmp_env
, 1);
62 /* exit the current TB from a signal handler. The host registers are
63 restored in a state compatible with the CPU emulator
65 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
67 #if !defined(CONFIG_SOFTMMU)
69 struct ucontext
*uc
= puc
;
70 #elif defined(__OpenBSD__)
71 struct sigcontext
*uc
= puc
;
77 /* XXX: restore cpu registers saved in host registers */
79 #if !defined(CONFIG_SOFTMMU)
81 /* XXX: use siglongjmp ? */
83 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
84 #elif defined(__OpenBSD__)
85 sigprocmask(SIG_SETMASK
, &uc
->sc_mask
, NULL
);
89 env
->exception_index
= -1;
90 longjmp(env
->jmp_env
, 1);
93 /* Execute the code without caching the generated code. An interpreter
94 could be used if available. */
95 static void cpu_exec_nocache(int max_cycles
, TranslationBlock
*orig_tb
)
97 unsigned long next_tb
;
100 /* Should never happen.
101 We only end up here when an existing TB is too long. */
102 if (max_cycles
> CF_COUNT_MASK
)
103 max_cycles
= CF_COUNT_MASK
;
105 tb
= tb_gen_code(env
, orig_tb
->pc
, orig_tb
->cs_base
, orig_tb
->flags
,
107 env
->current_tb
= tb
;
108 /* execute the generated code */
109 next_tb
= tcg_qemu_tb_exec(tb
->tc_ptr
);
111 if ((next_tb
& 3) == 2) {
112 /* Restore PC. This may happen if async event occurs before
113 the TB starts executing. */
114 cpu_pc_from_tb(env
, tb
);
116 tb_phys_invalidate(tb
, -1);
120 static TranslationBlock
*tb_find_slow(target_ulong pc
,
121 target_ulong cs_base
,
124 TranslationBlock
*tb
, **ptb1
;
126 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
128 tb_invalidated_flag
= 0;
130 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
132 /* find translated block using physical mappings */
133 phys_pc
= get_phys_addr_code(env
, pc
);
134 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
136 h
= tb_phys_hash_func(phys_pc
);
137 ptb1
= &tb_phys_hash
[h
];
143 tb
->page_addr
[0] == phys_page1
&&
144 tb
->cs_base
== cs_base
&&
145 tb
->flags
== flags
) {
146 /* check next page if needed */
147 if (tb
->page_addr
[1] != -1) {
148 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
150 phys_page2
= get_phys_addr_code(env
, virt_page2
);
151 if (tb
->page_addr
[1] == phys_page2
)
157 ptb1
= &tb
->phys_hash_next
;
160 /* if no translated code available, then translate it now */
161 tb
= tb_gen_code(env
, pc
, cs_base
, flags
, 0);
164 /* we add the TB in the virtual pc hash table */
165 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
169 static inline TranslationBlock
*tb_find_fast(void)
171 TranslationBlock
*tb
;
172 target_ulong cs_base
, pc
;
175 /* we record a subset of the CPU state. It will
176 always be the same before a given translated block
178 cpu_get_tb_cpu_state(env
, &pc
, &cs_base
, &flags
);
179 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
180 if (unlikely(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
181 tb
->flags
!= flags
)) {
182 tb
= tb_find_slow(pc
, cs_base
, flags
);
187 static CPUDebugExcpHandler
*debug_excp_handler
;
189 CPUDebugExcpHandler
*cpu_set_debug_excp_handler(CPUDebugExcpHandler
*handler
)
191 CPUDebugExcpHandler
*old_handler
= debug_excp_handler
;
193 debug_excp_handler
= handler
;
197 static void cpu_handle_debug_exception(CPUState
*env
)
201 if (!env
->watchpoint_hit
)
202 TAILQ_FOREACH(wp
, &env
->watchpoints
, entry
)
203 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
205 if (debug_excp_handler
)
206 debug_excp_handler(env
);
209 /* main execution loop */
211 int cpu_exec(CPUState
*env1
)
213 #define DECLARE_HOST_REGS 1
214 #include "hostregs_helper.h"
215 int ret
, interrupt_request
;
216 TranslationBlock
*tb
;
218 unsigned long next_tb
;
220 if (cpu_halted(env1
) == EXCP_HALTED
)
223 cpu_single_env
= env1
;
225 /* first we save global registers */
226 #define SAVE_HOST_REGS 1
227 #include "hostregs_helper.h"
231 #if defined(TARGET_I386)
232 /* put eflags in CPU temporary format */
233 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
234 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
235 CC_OP
= CC_OP_EFLAGS
;
236 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
237 #elif defined(TARGET_SPARC)
238 #elif defined(TARGET_M68K)
239 env
->cc_op
= CC_OP_FLAGS
;
240 env
->cc_dest
= env
->sr
& 0xf;
241 env
->cc_x
= (env
->sr
>> 4) & 1;
242 #elif defined(TARGET_ALPHA)
243 #elif defined(TARGET_ARM)
244 #elif defined(TARGET_PPC)
245 #elif defined(TARGET_MIPS)
246 #elif defined(TARGET_SH4)
247 #elif defined(TARGET_CRIS)
250 #error unsupported target CPU
252 env
->exception_index
= -1;
254 /* prepare setjmp context for exception handling */
256 if (setjmp(env
->jmp_env
) == 0) {
257 env
->current_tb
= NULL
;
258 /* if an exception is pending, we execute it here */
259 if (env
->exception_index
>= 0) {
260 if (env
->exception_index
>= EXCP_INTERRUPT
) {
261 /* exit request from the cpu execution loop */
262 ret
= env
->exception_index
;
263 if (ret
== EXCP_DEBUG
)
264 cpu_handle_debug_exception(env
);
266 } else if (env
->user_mode_only
) {
267 /* if user mode only, we simulate a fake exception
268 which will be handled outside the cpu execution
270 #if defined(TARGET_I386)
271 do_interrupt_user(env
->exception_index
,
272 env
->exception_is_int
,
274 env
->exception_next_eip
);
275 /* successfully delivered */
276 env
->old_exception
= -1;
278 ret
= env
->exception_index
;
281 #if defined(TARGET_I386)
282 /* simulate a real cpu exception. On i386, it can
283 trigger new exceptions, but we do not handle
284 double or triple faults yet. */
285 do_interrupt(env
->exception_index
,
286 env
->exception_is_int
,
288 env
->exception_next_eip
, 0);
289 /* successfully delivered */
290 env
->old_exception
= -1;
291 #elif defined(TARGET_PPC)
293 #elif defined(TARGET_MIPS)
295 #elif defined(TARGET_SPARC)
297 #elif defined(TARGET_ARM)
299 #elif defined(TARGET_SH4)
301 #elif defined(TARGET_ALPHA)
303 #elif defined(TARGET_CRIS)
305 #elif defined(TARGET_M68K)
309 env
->exception_index
= -1;
312 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
314 env
->eflags
= env
->eflags
| helper_cc_compute_all(CC_OP
) | (DF
& DF_MASK
);
315 ret
= kqemu_cpu_exec(env
);
316 /* put eflags in CPU temporary format */
317 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
318 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
319 CC_OP
= CC_OP_EFLAGS
;
320 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
323 longjmp(env
->jmp_env
, 1);
324 } else if (ret
== 2) {
325 /* softmmu execution needed */
327 if (env
->interrupt_request
!= 0) {
328 /* hardware interrupt will be executed just after */
330 /* otherwise, we restart */
331 longjmp(env
->jmp_env
, 1);
339 longjmp(env
->jmp_env
, 1);
342 next_tb
= 0; /* force lookup of first TB */
344 interrupt_request
= env
->interrupt_request
;
345 if (unlikely(interrupt_request
)) {
346 if (unlikely(env
->singlestep_enabled
& SSTEP_NOIRQ
)) {
347 /* Mask out external interrupts for this step. */
348 interrupt_request
&= ~(CPU_INTERRUPT_HARD
|
353 if (interrupt_request
& CPU_INTERRUPT_DEBUG
) {
354 env
->interrupt_request
&= ~CPU_INTERRUPT_DEBUG
;
355 env
->exception_index
= EXCP_DEBUG
;
358 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
359 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
360 if (interrupt_request
& CPU_INTERRUPT_HALT
) {
361 env
->interrupt_request
&= ~CPU_INTERRUPT_HALT
;
363 env
->exception_index
= EXCP_HLT
;
367 #if defined(TARGET_I386)
368 if (env
->hflags2
& HF2_GIF_MASK
) {
369 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
370 !(env
->hflags
& HF_SMM_MASK
)) {
371 svm_check_intercept(SVM_EXIT_SMI
);
372 env
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
375 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
376 !(env
->hflags2
& HF2_NMI_MASK
)) {
377 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
378 env
->hflags2
|= HF2_NMI_MASK
;
379 do_interrupt(EXCP02_NMI
, 0, 0, 0, 1);
381 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
382 (((env
->hflags2
& HF2_VINTR_MASK
) &&
383 (env
->hflags2
& HF2_HIF_MASK
)) ||
384 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
385 (env
->eflags
& IF_MASK
&&
386 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
388 svm_check_intercept(SVM_EXIT_INTR
);
389 env
->interrupt_request
&= ~(CPU_INTERRUPT_HARD
| CPU_INTERRUPT_VIRQ
);
390 intno
= cpu_get_pic_interrupt(env
);
391 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
392 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
394 do_interrupt(intno
, 0, 0, 0, 1);
395 /* ensure that no TB jump will be modified as
396 the program flow was changed */
398 #if !defined(CONFIG_USER_ONLY)
399 } else if ((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
400 (env
->eflags
& IF_MASK
) &&
401 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
403 /* FIXME: this should respect TPR */
404 svm_check_intercept(SVM_EXIT_VINTR
);
405 intno
= ldl_phys(env
->vm_vmcb
+ offsetof(struct vmcb
, control
.int_vector
));
406 if (loglevel
& CPU_LOG_TB_IN_ASM
)
407 fprintf(logfile
, "Servicing virtual hardware INT=0x%02x\n", intno
);
408 do_interrupt(intno
, 0, 0, 0, 1);
409 env
->interrupt_request
&= ~CPU_INTERRUPT_VIRQ
;
414 #elif defined(TARGET_PPC)
416 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
420 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
421 ppc_hw_interrupt(env
);
422 if (env
->pending_interrupts
== 0)
423 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
426 #elif defined(TARGET_MIPS)
427 if (interrupt_request
& CPU_INTERRUPT_HARD
)
429 if (env
->CP0_Cause
&0x400)
431 printf("HARD INT \n");
432 printf("env->CP0_Status %x env->CP0_Cause %x CP0Ca_IP_mask %x \n",env
->CP0_Status
,env
->CP0_Cause
,CP0Ca_IP_mask
);
433 printf("CP0St_IE %x CP0St_EXL %x CP0St_ERL %x \n",CP0St_IE
,CP0St_EXL
,CP0St_ERL
);
434 printf("env->hflags %x MIPS_HFLAG_DM %x \n",env
->hflags
,MIPS_HFLAG_DM
);
437 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
438 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
) &&
439 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
440 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
441 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
442 !(env
->hflags
& MIPS_HFLAG_DM
)) {
444 env
->exception_index
= EXCP_EXT_INTERRUPT
;
449 #elif defined(TARGET_SPARC)
450 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
452 int pil
= env
->interrupt_index
& 15;
453 int type
= env
->interrupt_index
& 0xf0;
455 if (((type
== TT_EXTINT
) &&
456 (pil
== 15 || pil
> env
->psrpil
)) ||
458 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
459 env
->exception_index
= env
->interrupt_index
;
461 env
->interrupt_index
= 0;
462 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
467 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
468 //do_interrupt(0, 0, 0, 0, 0);
469 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
471 #elif defined(TARGET_ARM)
472 if (interrupt_request
& CPU_INTERRUPT_FIQ
473 && !(env
->uncached_cpsr
& CPSR_F
)) {
474 env
->exception_index
= EXCP_FIQ
;
478 /* ARMv7-M interrupt return works by loading a magic value
479 into the PC. On real hardware the load causes the
480 return to occur. The qemu implementation performs the
481 jump normally, then does the exception return when the
482 CPU tries to execute code at the magic address.
483 This will cause the magic PC value to be pushed to
484 the stack if an interrupt occured at the wrong time.
485 We avoid this by disabling interrupts when
486 pc contains a magic address. */
487 if (interrupt_request
& CPU_INTERRUPT_HARD
488 && ((IS_M(env
) && env
->regs
[15] < 0xfffffff0)
489 || !(env
->uncached_cpsr
& CPSR_I
))) {
490 env
->exception_index
= EXCP_IRQ
;
494 #elif defined(TARGET_SH4)
495 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
499 #elif defined(TARGET_ALPHA)
500 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
504 #elif defined(TARGET_CRIS)
505 if (interrupt_request
& CPU_INTERRUPT_HARD
506 && (env
->pregs
[PR_CCS
] & I_FLAG
)) {
507 env
->exception_index
= EXCP_IRQ
;
511 if (interrupt_request
& CPU_INTERRUPT_NMI
512 && (env
->pregs
[PR_CCS
] & M_FLAG
)) {
513 env
->exception_index
= EXCP_NMI
;
517 #elif defined(TARGET_M68K)
518 if (interrupt_request
& CPU_INTERRUPT_HARD
519 && ((env
->sr
& SR_I
) >> SR_I_SHIFT
)
520 < env
->pending_level
) {
521 /* Real hardware gets the interrupt vector via an
522 IACK cycle at this point. Current emulated
523 hardware doesn't rely on this, so we
524 provide/save the vector when the interrupt is
526 env
->exception_index
= env
->pending_vector
;
531 /* Don't use the cached interupt_request value,
532 do_interrupt may have updated the EXITTB flag. */
533 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
534 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
535 /* ensure that no TB jump will be modified as
536 the program flow was changed */
539 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
540 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
541 env
->exception_index
= EXCP_INTERRUPT
;
546 if ((loglevel
& CPU_LOG_TB_CPU
)) {
547 /* restore flags in standard format */
549 #if defined(TARGET_I386)
550 env
->eflags
= env
->eflags
| helper_cc_compute_all(CC_OP
) | (DF
& DF_MASK
);
551 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
552 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
553 #elif defined(TARGET_ARM)
554 cpu_dump_state(env
, logfile
, fprintf
, 0);
555 #elif defined(TARGET_SPARC)
556 cpu_dump_state(env
, logfile
, fprintf
, 0);
557 #elif defined(TARGET_PPC)
558 cpu_dump_state(env
, logfile
, fprintf
, 0);
559 #elif defined(TARGET_M68K)
560 cpu_m68k_flush_flags(env
, env
->cc_op
);
561 env
->cc_op
= CC_OP_FLAGS
;
562 env
->sr
= (env
->sr
& 0xffe0)
563 | env
->cc_dest
| (env
->cc_x
<< 4);
564 cpu_dump_state(env
, logfile
, fprintf
, 0);
565 #elif defined(TARGET_MIPS)
566 cpu_dump_state(env
, logfile
, fprintf
, 0);
567 #elif defined(TARGET_SH4)
568 cpu_dump_state(env
, logfile
, fprintf
, 0);
569 #elif defined(TARGET_ALPHA)
570 cpu_dump_state(env
, logfile
, fprintf
, 0);
571 #elif defined(TARGET_CRIS)
572 cpu_dump_state(env
, logfile
, fprintf
, 0);
574 #error unsupported target CPU
580 /* Note: we do it here to avoid a gcc bug on Mac OS X when
581 doing it in tb_find_slow */
582 if (tb_invalidated_flag
) {
583 /* as some TB could have been invalidated because
584 of memory exceptions while generating the code, we
585 must recompute the hash index here */
587 tb_invalidated_flag
= 0;
590 if ((loglevel
& CPU_LOG_EXEC
)) {
591 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
592 (long)tb
->tc_ptr
, tb
->pc
,
593 lookup_symbol(tb
->pc
));
596 /* see if we can patch the calling TB. When the TB
597 spans two pages, we cannot safely do a direct
602 (env
->kqemu_enabled
!= 2) &&
604 tb
->page_addr
[1] == -1) {
605 tb_add_jump((TranslationBlock
*)(next_tb
& ~3), next_tb
& 3, tb
);
608 spin_unlock(&tb_lock
);
609 env
->current_tb
= tb
;
611 /* cpu_interrupt might be called while translating the
612 TB, but before it is linked into a potentially
613 infinite loop and becomes env->current_tb. Avoid
614 starting execution if there is a pending interrupt. */
615 if (unlikely (env
->interrupt_request
& CPU_INTERRUPT_EXIT
))
616 env
->current_tb
= NULL
;
618 while (env
->current_tb
) {
620 /* execute the generated code */
621 #if defined(__sparc__) && !defined(HOST_SOLARIS)
623 env
= cpu_single_env
;
624 #define env cpu_single_env
626 next_tb
= tcg_qemu_tb_exec(tc_ptr
);
627 env
->current_tb
= NULL
;
628 if ((next_tb
& 3) == 2) {
629 /* Instruction counter expired. */
631 tb
= (TranslationBlock
*)(long)(next_tb
& ~3);
633 cpu_pc_from_tb(env
, tb
);
634 insns_left
= env
->icount_decr
.u32
;
635 if (env
->icount_extra
&& insns_left
>= 0) {
636 /* Refill decrementer and continue execution. */
637 env
->icount_extra
+= insns_left
;
638 if (env
->icount_extra
> 0xffff) {
641 insns_left
= env
->icount_extra
;
643 env
->icount_extra
-= insns_left
;
644 env
->icount_decr
.u16
.low
= insns_left
;
646 if (insns_left
> 0) {
647 /* Execute remaining instructions. */
648 cpu_exec_nocache(insns_left
, tb
);
650 env
->exception_index
= EXCP_INTERRUPT
;
656 /* reset soft MMU for next block (it can currently
657 only be set by a memory fault) */
658 #if defined(USE_KQEMU)
659 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
660 if (kqemu_is_ok(env
) &&
661 (cpu_get_time_fast() - env
->last_io_time
) >= MIN_CYCLE_BEFORE_SWITCH
) {
672 #if defined(TARGET_I386)
673 /* restore flags in standard format */
674 env
->eflags
= env
->eflags
| helper_cc_compute_all(CC_OP
) | (DF
& DF_MASK
);
675 #elif defined(TARGET_ARM)
676 /* XXX: Save/restore host fpu exception state?. */
677 #elif defined(TARGET_SPARC)
678 #elif defined(TARGET_PPC)
679 #elif defined(TARGET_M68K)
680 cpu_m68k_flush_flags(env
, env
->cc_op
);
681 env
->cc_op
= CC_OP_FLAGS
;
682 env
->sr
= (env
->sr
& 0xffe0)
683 | env
->cc_dest
| (env
->cc_x
<< 4);
684 #elif defined(TARGET_MIPS)
685 #elif defined(TARGET_SH4)
686 #elif defined(TARGET_ALPHA)
687 #elif defined(TARGET_CRIS)
690 #error unsupported target CPU
693 /* restore global registers */
694 #include "hostregs_helper.h"
696 /* fail safe : never use cpu_single_env outside cpu_exec() */
697 cpu_single_env
= NULL
;
701 /* must only be called from the generated code as an exception can be
703 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
705 /* XXX: cannot enable it yet because it yields to MMU exception
706 where NIP != read address on PowerPC */
708 target_ulong phys_addr
;
709 phys_addr
= get_phys_addr_code(env
, start
);
710 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
714 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
716 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
718 CPUX86State
*saved_env
;
722 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
724 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
725 (selector
<< 4), 0xffff, 0);
727 helper_load_seg(seg_reg
, selector
);
732 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
)
734 CPUX86State
*saved_env
;
739 helper_fsave(ptr
, data32
);
744 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
)
746 CPUX86State
*saved_env
;
751 helper_frstor(ptr
, data32
);
756 #endif /* TARGET_I386 */
758 #if !defined(CONFIG_SOFTMMU)
760 #if defined(TARGET_I386)
762 /* 'pc' is the host PC at which the exception was raised. 'address' is
763 the effective address of the memory exception. 'is_write' is 1 if a
764 write caused the exception and otherwise 0'. 'old_set' is the
765 signal set which should be restored */
766 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
767 int is_write
, sigset_t
*old_set
,
770 TranslationBlock
*tb
;
774 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
775 #if defined(DEBUG_SIGNAL)
776 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
777 pc
, address
, is_write
, *(unsigned long *)old_set
);
779 /* XXX: locking issue */
780 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
784 /* see if it is an MMU fault */
785 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
787 return 0; /* not an MMU fault */
789 return 1; /* the MMU fault was handled without causing real CPU fault */
790 /* now we have a real cpu fault */
793 /* the PC is inside the translated code. It means that we have
794 a virtual CPU fault */
795 cpu_restore_state(tb
, env
, pc
, puc
);
799 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
800 env
->eip
, env
->cr
[2], env
->error_code
);
802 /* we restore the process signal mask as the sigreturn should
803 do it (XXX: use sigsetjmp) */
804 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
805 raise_exception_err(env
->exception_index
, env
->error_code
);
807 /* activate soft MMU for this block */
808 env
->hflags
|= HF_SOFTMMU_MASK
;
809 cpu_resume_from_signal(env
, puc
);
811 /* never comes here */
815 #elif defined(TARGET_ARM)
816 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
817 int is_write
, sigset_t
*old_set
,
820 TranslationBlock
*tb
;
824 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
825 #if defined(DEBUG_SIGNAL)
826 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
827 pc
, address
, is_write
, *(unsigned long *)old_set
);
829 /* XXX: locking issue */
830 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
833 /* see if it is an MMU fault */
834 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
836 return 0; /* not an MMU fault */
838 return 1; /* the MMU fault was handled without causing real CPU fault */
839 /* now we have a real cpu fault */
842 /* the PC is inside the translated code. It means that we have
843 a virtual CPU fault */
844 cpu_restore_state(tb
, env
, pc
, puc
);
846 /* we restore the process signal mask as the sigreturn should
847 do it (XXX: use sigsetjmp) */
848 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
850 /* never comes here */
853 #elif defined(TARGET_SPARC)
854 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
855 int is_write
, sigset_t
*old_set
,
858 TranslationBlock
*tb
;
862 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
863 #if defined(DEBUG_SIGNAL)
864 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
865 pc
, address
, is_write
, *(unsigned long *)old_set
);
867 /* XXX: locking issue */
868 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
871 /* see if it is an MMU fault */
872 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
874 return 0; /* not an MMU fault */
876 return 1; /* the MMU fault was handled without causing real CPU fault */
877 /* now we have a real cpu fault */
880 /* the PC is inside the translated code. It means that we have
881 a virtual CPU fault */
882 cpu_restore_state(tb
, env
, pc
, puc
);
884 /* we restore the process signal mask as the sigreturn should
885 do it (XXX: use sigsetjmp) */
886 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
888 /* never comes here */
891 #elif defined (TARGET_PPC)
892 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
893 int is_write
, sigset_t
*old_set
,
896 TranslationBlock
*tb
;
900 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
901 #if defined(DEBUG_SIGNAL)
902 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
903 pc
, address
, is_write
, *(unsigned long *)old_set
);
905 /* XXX: locking issue */
906 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
910 /* see if it is an MMU fault */
911 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
913 return 0; /* not an MMU fault */
915 return 1; /* the MMU fault was handled without causing real CPU fault */
917 /* now we have a real cpu fault */
920 /* the PC is inside the translated code. It means that we have
921 a virtual CPU fault */
922 cpu_restore_state(tb
, env
, pc
, puc
);
926 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
927 env
->nip
, env
->error_code
, tb
);
929 /* we restore the process signal mask as the sigreturn should
930 do it (XXX: use sigsetjmp) */
931 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
934 /* activate soft MMU for this block */
935 cpu_resume_from_signal(env
, puc
);
937 /* never comes here */
941 #elif defined(TARGET_M68K)
942 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
943 int is_write
, sigset_t
*old_set
,
946 TranslationBlock
*tb
;
950 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
951 #if defined(DEBUG_SIGNAL)
952 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
953 pc
, address
, is_write
, *(unsigned long *)old_set
);
955 /* XXX: locking issue */
956 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
959 /* see if it is an MMU fault */
960 ret
= cpu_m68k_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
962 return 0; /* not an MMU fault */
964 return 1; /* the MMU fault was handled without causing real CPU fault */
965 /* now we have a real cpu fault */
968 /* the PC is inside the translated code. It means that we have
969 a virtual CPU fault */
970 cpu_restore_state(tb
, env
, pc
, puc
);
972 /* we restore the process signal mask as the sigreturn should
973 do it (XXX: use sigsetjmp) */
974 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
976 /* never comes here */
980 #elif defined (TARGET_MIPS)
981 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
982 int is_write
, sigset_t
*old_set
,
985 TranslationBlock
*tb
;
989 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
990 #if defined(DEBUG_SIGNAL)
991 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
992 pc
, address
, is_write
, *(unsigned long *)old_set
);
994 /* XXX: locking issue */
995 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
999 /* see if it is an MMU fault */
1000 ret
= cpu_mips_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
1002 return 0; /* not an MMU fault */
1004 return 1; /* the MMU fault was handled without causing real CPU fault */
1006 /* now we have a real cpu fault */
1007 tb
= tb_find_pc(pc
);
1009 /* the PC is inside the translated code. It means that we have
1010 a virtual CPU fault */
1011 cpu_restore_state(tb
, env
, pc
, puc
);
1015 printf("PF exception: PC=0x" TARGET_FMT_lx
" error=0x%x %p\n",
1016 env
->PC
, env
->error_code
, tb
);
1018 /* we restore the process signal mask as the sigreturn should
1019 do it (XXX: use sigsetjmp) */
1020 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1023 /* activate soft MMU for this block */
1024 cpu_resume_from_signal(env
, puc
);
1026 /* never comes here */
1030 #elif defined (TARGET_SH4)
1031 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1032 int is_write
, sigset_t
*old_set
,
1035 TranslationBlock
*tb
;
1039 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1040 #if defined(DEBUG_SIGNAL)
1041 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1042 pc
, address
, is_write
, *(unsigned long *)old_set
);
1044 /* XXX: locking issue */
1045 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1049 /* see if it is an MMU fault */
1050 ret
= cpu_sh4_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
1052 return 0; /* not an MMU fault */
1054 return 1; /* the MMU fault was handled without causing real CPU fault */
1056 /* now we have a real cpu fault */
1057 tb
= tb_find_pc(pc
);
1059 /* the PC is inside the translated code. It means that we have
1060 a virtual CPU fault */
1061 cpu_restore_state(tb
, env
, pc
, puc
);
1064 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1065 env
->nip
, env
->error_code
, tb
);
1067 /* we restore the process signal mask as the sigreturn should
1068 do it (XXX: use sigsetjmp) */
1069 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1071 /* never comes here */
1075 #elif defined (TARGET_ALPHA)
1076 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1077 int is_write
, sigset_t
*old_set
,
1080 TranslationBlock
*tb
;
1084 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1085 #if defined(DEBUG_SIGNAL)
1086 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1087 pc
, address
, is_write
, *(unsigned long *)old_set
);
1089 /* XXX: locking issue */
1090 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1094 /* see if it is an MMU fault */
1095 ret
= cpu_alpha_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
1097 return 0; /* not an MMU fault */
1099 return 1; /* the MMU fault was handled without causing real CPU fault */
1101 /* now we have a real cpu fault */
1102 tb
= tb_find_pc(pc
);
1104 /* the PC is inside the translated code. It means that we have
1105 a virtual CPU fault */
1106 cpu_restore_state(tb
, env
, pc
, puc
);
1109 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1110 env
->nip
, env
->error_code
, tb
);
1112 /* we restore the process signal mask as the sigreturn should
1113 do it (XXX: use sigsetjmp) */
1114 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1116 /* never comes here */
1119 #elif defined (TARGET_CRIS)
1120 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1121 int is_write
, sigset_t
*old_set
,
1124 TranslationBlock
*tb
;
1128 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1129 #if defined(DEBUG_SIGNAL)
1130 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1131 pc
, address
, is_write
, *(unsigned long *)old_set
);
1133 /* XXX: locking issue */
1134 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1138 /* see if it is an MMU fault */
1139 ret
= cpu_cris_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
1141 return 0; /* not an MMU fault */
1143 return 1; /* the MMU fault was handled without causing real CPU fault */
1145 /* now we have a real cpu fault */
1146 tb
= tb_find_pc(pc
);
1148 /* the PC is inside the translated code. It means that we have
1149 a virtual CPU fault */
1150 cpu_restore_state(tb
, env
, pc
, puc
);
1152 /* we restore the process signal mask as the sigreturn should
1153 do it (XXX: use sigsetjmp) */
1154 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1156 /* never comes here */
1161 #error unsupported target CPU
1164 #if defined(__i386__)
1166 #if defined(__APPLE__)
1167 # include <sys/ucontext.h>
1169 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1170 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1171 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1173 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1174 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1175 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1178 int cpu_signal_handler(int host_signum
, void *pinfo
,
1181 siginfo_t
*info
= pinfo
;
1182 struct ucontext
*uc
= puc
;
1190 #define REG_TRAPNO TRAPNO
1193 trapno
= TRAP_sig(uc
);
1194 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1196 (ERROR_sig(uc
) >> 1) & 1 : 0,
1197 &uc
->uc_sigmask
, puc
);
1200 #elif defined(__x86_64__)
1203 #define REG_ERR _REG_ERR
1204 #define REG_TRAPNO _REG_TRAPNO
1206 #define QEMU_UC_MCONTEXT_GREGS(uc, reg) (uc)->uc_mcontext.__gregs[(reg)]
1207 #define QEMU_UC_MACHINE_PC(uc) _UC_MACHINE_PC(uc)
1209 #define QEMU_UC_MCONTEXT_GREGS(uc, reg) (uc)->uc_mcontext.gregs[(reg)]
1210 #define QEMU_UC_MACHINE_PC(uc) QEMU_UC_MCONTEXT_GREGS(uc, REG_RIP)
1213 int cpu_signal_handler(int host_signum
, void *pinfo
,
1216 siginfo_t
*info
= pinfo
;
1219 ucontext_t
*uc
= puc
;
1221 struct ucontext
*uc
= puc
;
1224 pc
= QEMU_UC_MACHINE_PC(uc
);
1225 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1226 QEMU_UC_MCONTEXT_GREGS(uc
, REG_TRAPNO
) == 0xe ?
1227 (QEMU_UC_MCONTEXT_GREGS(uc
, REG_ERR
) >> 1) & 1 : 0,
1228 &uc
->uc_sigmask
, puc
);
1231 #elif defined(__powerpc__)
1233 /***********************************************************************
1234 * signal context platform-specific definitions
1238 /* All Registers access - only for local access */
1239 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1240 /* Gpr Registers access */
1241 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1242 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1243 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1244 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1245 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1246 # define LR_sig(context) REG_sig(link, context) /* Link register */
1247 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1248 /* Float Registers access */
1249 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1250 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1251 /* Exception Registers access */
1252 # define DAR_sig(context) REG_sig(dar, context)
1253 # define DSISR_sig(context) REG_sig(dsisr, context)
1254 # define TRAP_sig(context) REG_sig(trap, context)
1258 # include <sys/ucontext.h>
1259 typedef struct ucontext SIGCONTEXT
;
1260 /* All Registers access - only for local access */
1261 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1262 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1263 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1264 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1265 /* Gpr Registers access */
1266 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1267 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1268 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1269 # define CTR_sig(context) REG_sig(ctr, context)
1270 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1271 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1272 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1273 /* Float Registers access */
1274 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1275 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1276 /* Exception Registers access */
1277 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1278 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1279 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1280 #endif /* __APPLE__ */
1282 int cpu_signal_handler(int host_signum
, void *pinfo
,
1285 siginfo_t
*info
= pinfo
;
1286 struct ucontext
*uc
= puc
;
1294 if (DSISR_sig(uc
) & 0x00800000)
1297 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1300 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1301 is_write
, &uc
->uc_sigmask
, puc
);
1304 #elif defined(__alpha__)
1306 int cpu_signal_handler(int host_signum
, void *pinfo
,
1309 siginfo_t
*info
= pinfo
;
1310 struct ucontext
*uc
= puc
;
1311 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1312 uint32_t insn
= *pc
;
1315 /* XXX: need kernel patch to get write flag faster */
1316 switch (insn
>> 26) {
1331 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1332 is_write
, &uc
->uc_sigmask
, puc
);
1334 #elif defined(__sparc__)
1336 int cpu_signal_handler(int host_signum
, void *pinfo
,
1339 siginfo_t
*info
= pinfo
;
1342 #if !defined(__arch64__) || defined(HOST_SOLARIS)
1343 uint32_t *regs
= (uint32_t *)(info
+ 1);
1344 void *sigmask
= (regs
+ 20);
1345 /* XXX: is there a standard glibc define ? */
1346 unsigned long pc
= regs
[1];
1349 struct sigcontext
*sc
= puc
;
1350 unsigned long pc
= sc
->sigc_regs
.tpc
;
1351 void *sigmask
= (void *)sc
->sigc_mask
;
1352 #elif defined(__OpenBSD__)
1353 struct sigcontext
*uc
= puc
;
1354 unsigned long pc
= uc
->sc_pc
;
1355 void *sigmask
= (void *)(long)uc
->sc_mask
;
1359 /* XXX: need kernel patch to get write flag faster */
1361 insn
= *(uint32_t *)pc
;
1362 if ((insn
>> 30) == 3) {
1363 switch((insn
>> 19) & 0x3f) {
1375 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1376 is_write
, sigmask
, NULL
);
1379 #elif defined(__arm__)
1381 int cpu_signal_handler(int host_signum
, void *pinfo
,
1384 siginfo_t
*info
= pinfo
;
1385 struct ucontext
*uc
= puc
;
1389 #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
1390 pc
= uc
->uc_mcontext
.gregs
[R15
];
1392 pc
= uc
->uc_mcontext
.arm_pc
;
1394 /* XXX: compute is_write */
1396 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1398 &uc
->uc_sigmask
, puc
);
1401 #elif defined(__mc68000)
1403 int cpu_signal_handler(int host_signum
, void *pinfo
,
1406 siginfo_t
*info
= pinfo
;
1407 struct ucontext
*uc
= puc
;
1411 pc
= uc
->uc_mcontext
.gregs
[16];
1412 /* XXX: compute is_write */
1414 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1416 &uc
->uc_sigmask
, puc
);
1419 #elif defined(__ia64)
1422 /* This ought to be in <bits/siginfo.h>... */
1423 # define __ISR_VALID 1
1426 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
1428 siginfo_t
*info
= pinfo
;
1429 struct ucontext
*uc
= puc
;
1433 ip
= uc
->uc_mcontext
.sc_ip
;
1434 switch (host_signum
) {
1440 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1441 /* ISR.W (write-access) is bit 33: */
1442 is_write
= (info
->si_isr
>> 33) & 1;
1448 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1450 &uc
->uc_sigmask
, puc
);
1453 #elif defined(__s390__)
1455 int cpu_signal_handler(int host_signum
, void *pinfo
,
1458 siginfo_t
*info
= pinfo
;
1459 struct ucontext
*uc
= puc
;
1463 pc
= uc
->uc_mcontext
.psw
.addr
;
1464 /* XXX: compute is_write */
1466 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1467 is_write
, &uc
->uc_sigmask
, puc
);
1470 #elif defined(__mips__)
1472 int cpu_signal_handler(int host_signum
, void *pinfo
,
1475 siginfo_t
*info
= pinfo
;
1476 struct ucontext
*uc
= puc
;
1477 greg_t pc
= uc
->uc_mcontext
.pc
;
1480 /* XXX: compute is_write */
1482 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1483 is_write
, &uc
->uc_sigmask
, puc
);
1486 #elif defined(__hppa__)
1488 int cpu_signal_handler(int host_signum
, void *pinfo
,
1491 struct siginfo
*info
= pinfo
;
1492 struct ucontext
*uc
= puc
;
1496 pc
= uc
->uc_mcontext
.sc_iaoq
[0];
1497 /* FIXME: compute is_write */
1499 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1501 &uc
->uc_sigmask
, puc
);
1506 #error host CPU specific signal handler needed
1510 #endif /* !defined(CONFIG_SOFTMMU) */