?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[RFC] mips: Enable bulk write optimization for all writes
[openocd.git] / src / target / mips_m4k.c
blobfc2a3f808a27e6175cbb2c0e1288c09f3c91c108
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 * *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the *
24 * Free Software Foundation, Inc., *
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
26 ***************************************************************************/
27
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "breakpoints.h"
33 #include "mips32.h"
34 #include "mips_m4k.h"
35 #include "mips32_dmaacc.h"
36 #include "target_type.h"
37 #include "register.h"
38
39 static void mips_m4k_enable_breakpoints(struct target *target);
40 static void mips_m4k_enable_watchpoints(struct target *target);
41 static int mips_m4k_set_breakpoint(struct target *target,
42 struct breakpoint *breakpoint);
43 static int mips_m4k_unset_breakpoint(struct target *target,
44 struct breakpoint *breakpoint);
45 static int mips_m4k_internal_restore(struct target *target, int current,
46 uint32_t address, int handle_breakpoints,
47 int debug_execution);
48 static int mips_m4k_halt(struct target *target);
49 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
50 uint32_t count, const uint8_t *buffer);
51
52 static int mips_m4k_examine_debug_reason(struct target *target)
53 {
54 uint32_t break_status;
55 int retval;
56
57 if ((target->debug_reason != DBG_REASON_DBGRQ)
58 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
59 /* get info about inst breakpoint support */
60 retval = target_read_u32(target, EJTAG_IBS, &break_status);
61 if (retval != ERROR_OK)
62 return retval;
63 if (break_status & 0x1f) {
64 /* we have halted on a breakpoint */
65 retval = target_write_u32(target, EJTAG_IBS, 0);
66 if (retval != ERROR_OK)
67 return retval;
68 target->debug_reason = DBG_REASON_BREAKPOINT;
69 }
70
71 /* get info about data breakpoint support */
72 retval = target_read_u32(target, EJTAG_DBS, &break_status);
73 if (retval != ERROR_OK)
74 return retval;
75 if (break_status & 0x1f) {
76 /* we have halted on a breakpoint */
77 retval = target_write_u32(target, EJTAG_DBS, 0);
78 if (retval != ERROR_OK)
79 return retval;
80 target->debug_reason = DBG_REASON_WATCHPOINT;
81 }
82 }
83
84 return ERROR_OK;
85 }
86
87 static int mips_m4k_debug_entry(struct target *target)
88 {
89 struct mips32_common *mips32 = target_to_mips32(target);
90 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
91
92 mips32_save_context(target);
93
94 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
95 mips_ejtag_config_step(ejtag_info, 0);
96
97 /* make sure break unit configured */
98 mips32_configure_break_unit(target);
99
100 /* attempt to find halt reason */
101 mips_m4k_examine_debug_reason(target);
102
103 /* default to mips32 isa, it will be changed below if required */
104 mips32->isa_mode = MIPS32_ISA_MIPS32;
105
106 if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
107 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
108
109 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
110 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
111 target_state_name(target));
112
113 return ERROR_OK;
114 }
115
116 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
117 {
118 struct target_list *head;
119 struct target *curr;
120
121 head = target->head;
122 while (head != (struct target_list *)NULL) {
123 curr = head->target;
124 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
125 return curr;
126 head = head->next;
127 }
128 return target;
129 }
130
131 static int mips_m4k_halt_smp(struct target *target)
132 {
133 int retval = ERROR_OK;
134 struct target_list *head;
135 struct target *curr;
136 head = target->head;
137 while (head != (struct target_list *)NULL) {
138 int ret = ERROR_OK;
139 curr = head->target;
140 if ((curr != target) && (curr->state != TARGET_HALTED))
141 ret = mips_m4k_halt(curr);
142
143 if (ret != ERROR_OK) {
144 LOG_ERROR("halt failed target->coreid: %d", curr->coreid);
145 retval = ret;
146 }
147 head = head->next;
148 }
149 return retval;
150 }
151
152 static int update_halt_gdb(struct target *target)
153 {
154 int retval = ERROR_OK;
155 if (target->gdb_service->core[0] == -1) {
156 target->gdb_service->target = target;
157 target->gdb_service->core[0] = target->coreid;
158 retval = mips_m4k_halt_smp(target);
159 }
160 return retval;
161 }
162
163 static int mips_m4k_poll(struct target *target)
164 {
165 int retval = ERROR_OK;
166 struct mips32_common *mips32 = target_to_mips32(target);
167 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
168 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
169 enum target_state prev_target_state = target->state;
170
171 /* toggle to another core is done by gdb as follow */
172 /* maint packet J core_id */
173 /* continue */
174 /* the next polling trigger an halt event sent to gdb */
175 if ((target->state == TARGET_HALTED) && (target->smp) &&
176 (target->gdb_service) &&
177 (target->gdb_service->target == NULL)) {
178 target->gdb_service->target =
179 get_mips_m4k(target, target->gdb_service->core[1]);
180 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
181 return retval;
182 }
183
184 /* read ejtag control reg */
185 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
186 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
187 if (retval != ERROR_OK)
188 return retval;
189
190 /* clear this bit before handling polling
191 * as after reset registers will read zero */
192 if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
193 /* we have detected a reset, clear flag
194 * otherwise ejtag will not work */
195 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
196
197 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
198 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
199 if (retval != ERROR_OK)
200 return retval;
201 LOG_DEBUG("Reset Detected");
202 }
203
204 /* check for processor halted */
205 if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
206 if ((target->state != TARGET_HALTED)
207 && (target->state != TARGET_DEBUG_RUNNING)) {
208 if (target->state == TARGET_UNKNOWN)
209 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
210
211 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
212 * (maybe put on by HALT-ing the board in the previous session).
213 *
214 * Force enable debug entry for this session.
215 */
216 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
217 target->state = TARGET_HALTED;
218 retval = mips_m4k_debug_entry(target);
219 if (retval != ERROR_OK)
220 return retval;
221
222 if (target->smp &&
223 ((prev_target_state == TARGET_RUNNING)
224 || (prev_target_state == TARGET_RESET))) {
225 retval = update_halt_gdb(target);
226 if (retval != ERROR_OK)
227 return retval;
228 }
229 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
230 } else if (target->state == TARGET_DEBUG_RUNNING) {
231 target->state = TARGET_HALTED;
232
233 retval = mips_m4k_debug_entry(target);
234 if (retval != ERROR_OK)
235 return retval;
236
237 if (target->smp) {
238 retval = update_halt_gdb(target);
239 if (retval != ERROR_OK)
240 return retval;
241 }
242
243 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
244 }
245 } else
246 target->state = TARGET_RUNNING;
247
248 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
249
250 return ERROR_OK;
251 }
252
253 static int mips_m4k_halt(struct target *target)
254 {
255 struct mips32_common *mips32 = target_to_mips32(target);
256 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
257
258 LOG_DEBUG("target->state: %s", target_state_name(target));
259
260 if (target->state == TARGET_HALTED) {
261 LOG_DEBUG("target was already halted");
262 return ERROR_OK;
263 }
264
265 if (target->state == TARGET_UNKNOWN)
266 LOG_WARNING("target was in unknown state when halt was requested");
267
268 if (target->state == TARGET_RESET) {
269 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
270 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
271 return ERROR_TARGET_FAILURE;
272 } else {
273 /* we came here in a reset_halt or reset_init sequence
274 * debug entry was already prepared in mips_m4k_assert_reset()
275 */
276 target->debug_reason = DBG_REASON_DBGRQ;
277
278 return ERROR_OK;
279 }
280 }
281
282 /* break processor */
283 mips_ejtag_enter_debug(ejtag_info);
284
285 target->debug_reason = DBG_REASON_DBGRQ;
286
287 return ERROR_OK;
288 }
289
290 static int mips_m4k_assert_reset(struct target *target)
291 {
292 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
293 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
294
295 LOG_DEBUG("target->state: %s",
296 target_state_name(target));
297
298 enum reset_types jtag_reset_config = jtag_get_reset_config();
299
300 /* some cores support connecting while srst is asserted
301 * use that mode is it has been configured */
302
303 bool srst_asserted = false;
304
305 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
306 (jtag_reset_config & RESET_SRST_NO_GATING)) {
307 jtag_add_reset(0, 1);
308 srst_asserted = true;
309 }
310
311 if (target->reset_halt) {
312 /* use hardware to catch reset */
313 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
314 } else
315 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
316
317 if (jtag_reset_config & RESET_HAS_SRST) {
318 /* here we should issue a srst only, but we may have to assert trst as well */
319 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
320 jtag_add_reset(1, 1);
321 else if (!srst_asserted)
322 jtag_add_reset(0, 1);
323 } else {
324 if (mips_m4k->is_pic32mx) {
325 LOG_DEBUG("Using MTAP reset to reset processor...");
326
327 /* use microchip specific MTAP reset */
328 mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
329 mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
330
331 mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
332 mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
333 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
334 } else {
335 /* use ejtag reset - not supported by all cores */
336 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
337 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
338 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
339 mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
340 }
341 }
342
343 target->state = TARGET_RESET;
344 jtag_add_sleep(50000);
345
346 register_cache_invalidate(mips_m4k->mips32.core_cache);
347
348 if (target->reset_halt) {
349 int retval = target_halt(target);
350 if (retval != ERROR_OK)
351 return retval;
352 }
353
354 return ERROR_OK;
355 }
356
357 static int mips_m4k_deassert_reset(struct target *target)
358 {
359 LOG_DEBUG("target->state: %s", target_state_name(target));
360
361 /* deassert reset lines */
362 jtag_add_reset(0, 0);
363
364 return ERROR_OK;
365 }
366
367 static int mips_m4k_soft_reset_halt(struct target *target)
368 {
369 /* TODO */
370 return ERROR_OK;
371 }
372
373 static int mips_m4k_single_step_core(struct target *target)
374 {
375 struct mips32_common *mips32 = target_to_mips32(target);
376 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
377
378 /* configure single step mode */
379 mips_ejtag_config_step(ejtag_info, 1);
380
381 /* disable interrupts while stepping */
382 mips32_enable_interrupts(target, 0);
383
384 /* exit debug mode */
385 mips_ejtag_exit_debug(ejtag_info);
386
387 mips_m4k_debug_entry(target);
388
389 return ERROR_OK;
390 }
391
392 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
393 {
394 int retval = ERROR_OK;
395 struct target_list *head;
396 struct target *curr;
397
398 head = target->head;
399 while (head != (struct target_list *)NULL) {
400 int ret = ERROR_OK;
401 curr = head->target;
402 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
403 /* resume current address , not in step mode */
404 ret = mips_m4k_internal_restore(curr, 1, address,
405 handle_breakpoints, 0);
406
407 if (ret != ERROR_OK) {
408 LOG_ERROR("target->coreid :%d failed to resume at address :0x%x",
409 curr->coreid, address);
410 retval = ret;
411 }
412 }
413 head = head->next;
414 }
415 return retval;
416 }
417
418 static int mips_m4k_internal_restore(struct target *target, int current,
419 uint32_t address, int handle_breakpoints, int debug_execution)
420 {
421 struct mips32_common *mips32 = target_to_mips32(target);
422 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
423 struct breakpoint *breakpoint = NULL;
424 uint32_t resume_pc;
425
426 if (target->state != TARGET_HALTED) {
427 LOG_WARNING("target not halted");
428 return ERROR_TARGET_NOT_HALTED;
429 }
430
431 if (!debug_execution) {
432 target_free_all_working_areas(target);
433 mips_m4k_enable_breakpoints(target);
434 mips_m4k_enable_watchpoints(target);
435 }
436
437 /* current = 1: continue on current pc, otherwise continue at <address> */
438 if (!current) {
439 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
440 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
441 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
442 }
443
444 if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
445 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
446
447 if (!current)
448 resume_pc = address;
449 else
450 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
451
452 mips32_restore_context(target);
453
454 /* the front-end may request us not to handle breakpoints */
455 if (handle_breakpoints) {
456 /* Single step past breakpoint at current address */
457 breakpoint = breakpoint_find(target, resume_pc);
458 if (breakpoint) {
459 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
460 mips_m4k_unset_breakpoint(target, breakpoint);
461 mips_m4k_single_step_core(target);
462 mips_m4k_set_breakpoint(target, breakpoint);
463 }
464 }
465
466 /* enable interrupts if we are running */
467 mips32_enable_interrupts(target, !debug_execution);
468
469 /* exit debug mode */
470 mips_ejtag_exit_debug(ejtag_info);
471 target->debug_reason = DBG_REASON_NOTHALTED;
472
473 /* registers are now invalid */
474 register_cache_invalidate(mips32->core_cache);
475
476 if (!debug_execution) {
477 target->state = TARGET_RUNNING;
478 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
479 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
480 } else {
481 target->state = TARGET_DEBUG_RUNNING;
482 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
483 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
484 }
485
486 return ERROR_OK;
487 }
488
489 static int mips_m4k_resume(struct target *target, int current,
490 uint32_t address, int handle_breakpoints, int debug_execution)
491 {
492 int retval = ERROR_OK;
493
494 /* dummy resume for smp toggle in order to reduce gdb impact */
495 if ((target->smp) && (target->gdb_service->core[1] != -1)) {
496 /* simulate a start and halt of target */
497 target->gdb_service->target = NULL;
498 target->gdb_service->core[0] = target->gdb_service->core[1];
499 /* fake resume at next poll we play the target core[1], see poll*/
500 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
501 return retval;
502 }
503
504 retval = mips_m4k_internal_restore(target, current, address,
505 handle_breakpoints,
506 debug_execution);
507
508 if (retval == ERROR_OK && target->smp) {
509 target->gdb_service->core[0] = -1;
510 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
511 }
512
513 return retval;
514 }
515
516 static int mips_m4k_step(struct target *target, int current,
517 uint32_t address, int handle_breakpoints)
518 {
519 /* get pointers to arch-specific information */
520 struct mips32_common *mips32 = target_to_mips32(target);
521 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
522 struct breakpoint *breakpoint = NULL;
523
524 if (target->state != TARGET_HALTED) {
525 LOG_WARNING("target not halted");
526 return ERROR_TARGET_NOT_HALTED;
527 }
528
529 /* current = 1: continue on current pc, otherwise continue at <address> */
530 if (!current) {
531 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
532 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
533 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
534 }
535
536 /* the front-end may request us not to handle breakpoints */
537 if (handle_breakpoints) {
538 breakpoint = breakpoint_find(target,
539 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
540 if (breakpoint)
541 mips_m4k_unset_breakpoint(target, breakpoint);
542 }
543
544 /* restore context */
545 mips32_restore_context(target);
546
547 /* configure single step mode */
548 mips_ejtag_config_step(ejtag_info, 1);
549
550 target->debug_reason = DBG_REASON_SINGLESTEP;
551
552 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
553
554 /* disable interrupts while stepping */
555 mips32_enable_interrupts(target, 0);
556
557 /* exit debug mode */
558 mips_ejtag_exit_debug(ejtag_info);
559
560 /* registers are now invalid */
561 register_cache_invalidate(mips32->core_cache);
562
563 LOG_DEBUG("target stepped ");
564 mips_m4k_debug_entry(target);
565
566 if (breakpoint)
567 mips_m4k_set_breakpoint(target, breakpoint);
568
569 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
570
571 return ERROR_OK;
572 }
573
574 static void mips_m4k_enable_breakpoints(struct target *target)
575 {
576 struct breakpoint *breakpoint = target->breakpoints;
577
578 /* set any pending breakpoints */
579 while (breakpoint) {
580 if (breakpoint->set == 0)
581 mips_m4k_set_breakpoint(target, breakpoint);
582 breakpoint = breakpoint->next;
583 }
584 }
585
586 static int mips_m4k_set_breakpoint(struct target *target,
587 struct breakpoint *breakpoint)
588 {
589 struct mips32_common *mips32 = target_to_mips32(target);
590 struct mips32_comparator *comparator_list = mips32->inst_break_list;
591 int retval;
592
593 if (breakpoint->set) {
594 LOG_WARNING("breakpoint already set");
595 return ERROR_OK;
596 }
597
598 if (breakpoint->type == BKPT_HARD) {
599 int bp_num = 0;
600
601 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
602 bp_num++;
603 if (bp_num >= mips32->num_inst_bpoints) {
604 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
605 breakpoint->unique_id);
606 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
607 }
608 breakpoint->set = bp_num + 1;
609 comparator_list[bp_num].used = 1;
610 comparator_list[bp_num].bp_value = breakpoint->address;
611 target_write_u32(target, comparator_list[bp_num].reg_address,
612 comparator_list[bp_num].bp_value);
613 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
614 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
615 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
616 breakpoint->unique_id,
617 bp_num, comparator_list[bp_num].bp_value);
618 } else if (breakpoint->type == BKPT_SOFT) {
619 LOG_DEBUG("bpid: %d", breakpoint->unique_id);
620 if (breakpoint->length == 4) {
621 uint32_t verify = 0xffffffff;
622
623 retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
624 breakpoint->orig_instr);
625 if (retval != ERROR_OK)
626 return retval;
627 retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP);
628 if (retval != ERROR_OK)
629 return retval;
630
631 retval = target_read_u32(target, breakpoint->address, &verify);
632 if (retval != ERROR_OK)
633 return retval;
634 if (verify != MIPS32_SDBBP) {
635 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
636 " - check that memory is read/writable", breakpoint->address);
637 return ERROR_OK;
638 }
639 } else {
640 uint16_t verify = 0xffff;
641
642 retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
643 breakpoint->orig_instr);
644 if (retval != ERROR_OK)
645 return retval;
646 retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP);
647 if (retval != ERROR_OK)
648 return retval;
649
650 retval = target_read_u16(target, breakpoint->address, &verify);
651 if (retval != ERROR_OK)
652 return retval;
653 if (verify != MIPS16_SDBBP) {
654 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
655 " - check that memory is read/writable", breakpoint->address);
656 return ERROR_OK;
657 }
658 }
659
660 breakpoint->set = 20; /* Any nice value but 0 */
661 }
662
663 return ERROR_OK;
664 }
665
666 static int mips_m4k_unset_breakpoint(struct target *target,
667 struct breakpoint *breakpoint)
668 {
669 /* get pointers to arch-specific information */
670 struct mips32_common *mips32 = target_to_mips32(target);
671 struct mips32_comparator *comparator_list = mips32->inst_break_list;
672 int retval;
673
674 if (!breakpoint->set) {
675 LOG_WARNING("breakpoint not set");
676 return ERROR_OK;
677 }
678
679 if (breakpoint->type == BKPT_HARD) {
680 int bp_num = breakpoint->set - 1;
681 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
682 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
683 breakpoint->unique_id);
684 return ERROR_OK;
685 }
686 LOG_DEBUG("bpid: %d - releasing hw: %d",
687 breakpoint->unique_id,
688 bp_num);
689 comparator_list[bp_num].used = 0;
690 comparator_list[bp_num].bp_value = 0;
691 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
692
693 } else {
694 /* restore original instruction (kept in target endianness) */
695 LOG_DEBUG("bpid: %d", breakpoint->unique_id);
696 if (breakpoint->length == 4) {
697 uint32_t current_instr;
698
699 /* check that user program has not modified breakpoint instruction */
700 retval = target_read_memory(target, breakpoint->address, 4, 1,
701 (uint8_t *)&current_instr);
702 if (retval != ERROR_OK)
703 return retval;
704
705 /**
706 * target_read_memory() gets us data in _target_ endianess.
707 * If we want to use this data on the host for comparisons with some macros
708 * we must first transform it to _host_ endianess using target_buffer_get_u32().
709 */
710 current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
711
712 if (current_instr == MIPS32_SDBBP) {
713 retval = target_write_memory(target, breakpoint->address, 4, 1,
714 breakpoint->orig_instr);
715 if (retval != ERROR_OK)
716 return retval;
717 }
718 } else {
719 uint16_t current_instr;
720
721 /* check that user program has not modified breakpoint instruction */
722 retval = target_read_memory(target, breakpoint->address, 2, 1,
723 (uint8_t *)&current_instr);
724 if (retval != ERROR_OK)
725 return retval;
726 current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
727 if (current_instr == MIPS16_SDBBP) {
728 retval = target_write_memory(target, breakpoint->address, 2, 1,
729 breakpoint->orig_instr);
730 if (retval != ERROR_OK)
731 return retval;
732 }
733 }
734 }
735 breakpoint->set = 0;
736
737 return ERROR_OK;
738 }
739
740 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
741 {
742 struct mips32_common *mips32 = target_to_mips32(target);
743
744 if (breakpoint->type == BKPT_HARD) {
745 if (mips32->num_inst_bpoints_avail < 1) {
746 LOG_INFO("no hardware breakpoint available");
747 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
748 }
749
750 mips32->num_inst_bpoints_avail--;
751 }
752
753 return mips_m4k_set_breakpoint(target, breakpoint);
754 }
755
756 static int mips_m4k_remove_breakpoint(struct target *target,
757 struct breakpoint *breakpoint)
758 {
759 /* get pointers to arch-specific information */
760 struct mips32_common *mips32 = target_to_mips32(target);
761
762 if (target->state != TARGET_HALTED) {
763 LOG_WARNING("target not halted");
764 return ERROR_TARGET_NOT_HALTED;
765 }
766
767 if (breakpoint->set)
768 mips_m4k_unset_breakpoint(target, breakpoint);
769
770 if (breakpoint->type == BKPT_HARD)
771 mips32->num_inst_bpoints_avail++;
772
773 return ERROR_OK;
774 }
775
776 static int mips_m4k_set_watchpoint(struct target *target,
777 struct watchpoint *watchpoint)
778 {
779 struct mips32_common *mips32 = target_to_mips32(target);
780 struct mips32_comparator *comparator_list = mips32->data_break_list;
781 int wp_num = 0;
782 /*
783 * watchpoint enabled, ignore all byte lanes in value register
784 * and exclude both load and store accesses from watchpoint
785 * condition evaluation
786 */
787 int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
788 (0xff << EJTAG_DBCn_BLM_SHIFT);
789
790 if (watchpoint->set) {
791 LOG_WARNING("watchpoint already set");
792 return ERROR_OK;
793 }
794
795 while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
796 wp_num++;
797 if (wp_num >= mips32->num_data_bpoints) {
798 LOG_ERROR("Can not find free FP Comparator");
799 return ERROR_FAIL;
800 }
801
802 if (watchpoint->length != 4) {
803 LOG_ERROR("Only watchpoints of length 4 are supported");
804 return ERROR_TARGET_UNALIGNED_ACCESS;
805 }
806
807 if (watchpoint->address % 4) {
808 LOG_ERROR("Watchpoints address should be word aligned");
809 return ERROR_TARGET_UNALIGNED_ACCESS;
810 }
811
812 switch (watchpoint->rw) {
813 case WPT_READ:
814 enable &= ~EJTAG_DBCn_NOLB;
815 break;
816 case WPT_WRITE:
817 enable &= ~EJTAG_DBCn_NOSB;
818 break;
819 case WPT_ACCESS:
820 enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
821 break;
822 default:
823 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
824 }
825
826 watchpoint->set = wp_num + 1;
827 comparator_list[wp_num].used = 1;
828 comparator_list[wp_num].bp_value = watchpoint->address;
829 target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
830 target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
831 target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
832 target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
833 target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
834 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
835
836 return ERROR_OK;
837 }
838
839 static int mips_m4k_unset_watchpoint(struct target *target,
840 struct watchpoint *watchpoint)
841 {
842 /* get pointers to arch-specific information */
843 struct mips32_common *mips32 = target_to_mips32(target);
844 struct mips32_comparator *comparator_list = mips32->data_break_list;
845
846 if (!watchpoint->set) {
847 LOG_WARNING("watchpoint not set");
848 return ERROR_OK;
849 }
850
851 int wp_num = watchpoint->set - 1;
852 if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
853 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
854 return ERROR_OK;
855 }
856 comparator_list[wp_num].used = 0;
857 comparator_list[wp_num].bp_value = 0;
858 target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
859 watchpoint->set = 0;
860
861 return ERROR_OK;
862 }
863
864 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
865 {
866 struct mips32_common *mips32 = target_to_mips32(target);
867
868 if (mips32->num_data_bpoints_avail < 1) {
869 LOG_INFO("no hardware watchpoints available");
870 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
871 }
872
873 mips32->num_data_bpoints_avail--;
874
875 mips_m4k_set_watchpoint(target, watchpoint);
876 return ERROR_OK;
877 }
878
879 static int mips_m4k_remove_watchpoint(struct target *target,
880 struct watchpoint *watchpoint)
881 {
882 /* get pointers to arch-specific information */
883 struct mips32_common *mips32 = target_to_mips32(target);
884
885 if (target->state != TARGET_HALTED) {
886 LOG_WARNING("target not halted");
887 return ERROR_TARGET_NOT_HALTED;
888 }
889
890 if (watchpoint->set)
891 mips_m4k_unset_watchpoint(target, watchpoint);
892
893 mips32->num_data_bpoints_avail++;
894
895 return ERROR_OK;
896 }
897
898 static void mips_m4k_enable_watchpoints(struct target *target)
899 {
900 struct watchpoint *watchpoint = target->watchpoints;
901
902 /* set any pending watchpoints */
903 while (watchpoint) {
904 if (watchpoint->set == 0)
905 mips_m4k_set_watchpoint(target, watchpoint);
906 watchpoint = watchpoint->next;
907 }
908 }
909
910 static int mips_m4k_read_memory(struct target *target, uint32_t address,
911 uint32_t size, uint32_t count, uint8_t *buffer)
912 {
913 struct mips32_common *mips32 = target_to_mips32(target);
914 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
915
916 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
917 address, size, count);
918
919 if (target->state != TARGET_HALTED) {
920 LOG_WARNING("target not halted");
921 return ERROR_TARGET_NOT_HALTED;
922 }
923
924 /* sanitize arguments */
925 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
926 return ERROR_COMMAND_SYNTAX_ERROR;
927
928 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
929 return ERROR_TARGET_UNALIGNED_ACCESS;
930
931 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
932 void *t = NULL;
933
934 if (size > 1) {
935 t = malloc(count * size * sizeof(uint8_t));
936 if (t == NULL) {
937 LOG_ERROR("Out of memory");
938 return ERROR_FAIL;
939 }
940 } else
941 t = buffer;
942
943 /* if noDMA off, use DMAACC mode for memory read */
944 int retval;
945 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
946 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
947 else
948 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
949
950 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
951 /* endianness, but byte array should represent target endianness */
952 if (ERROR_OK == retval) {
953 switch (size) {
954 case 4:
955 target_buffer_set_u32_array(target, buffer, count, t);
956 break;
957 case 2:
958 target_buffer_set_u16_array(target, buffer, count, t);
959 break;
960 }
961 }
962
963 if ((size > 1) && (t != NULL))
964 free(t);
965
966 return retval;
967 }
968
969 static int mips_m4k_write_memory(struct target *target, uint32_t address,
970 uint32_t size, uint32_t count, const uint8_t *buffer)
971 {
972 struct mips32_common *mips32 = target_to_mips32(target);
973 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
974
975 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
976 address, size, count);
977
978 if (target->state != TARGET_HALTED) {
979 LOG_WARNING("target not halted");
980 return ERROR_TARGET_NOT_HALTED;
981 }
982
983 if (size == 4 && count > 32) {
984 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
985 if (retval == ERROR_OK)
986 return ERROR_OK;
987 LOG_WARNING("Falling back to non-bulk write");
988 }
989
990 /* sanitize arguments */
991 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
992 return ERROR_COMMAND_SYNTAX_ERROR;
993
994 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
995 return ERROR_TARGET_UNALIGNED_ACCESS;
996
997 /** correct endianess if we have word or hword access */
998 void *t = NULL;
999 if (size > 1) {
1000 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1001 /* endianness, but byte array represents target endianness */
1002 t = malloc(count * size * sizeof(uint8_t));
1003 if (t == NULL) {
1004 LOG_ERROR("Out of memory");
1005 return ERROR_FAIL;
1006 }
1007
1008 switch (size) {
1009 case 4:
1010 target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1011 break;
1012 case 2:
1013 target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1014 break;
1015 }
1016 buffer = t;
1017 }
1018
1019 /* if noDMA off, use DMAACC mode for memory write */
1020 int retval;
1021 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1022 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
1023 else
1024 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
1025
1026 if (t != NULL)
1027 free(t);
1028
1029 if (ERROR_OK != retval)
1030 return retval;
1031
1032 return ERROR_OK;
1033 }
1034
1035 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1036 struct target *target)
1037 {
1038 mips32_build_reg_cache(target);
1039
1040 return ERROR_OK;
1041 }
1042
1043 static int mips_m4k_init_arch_info(struct target *target,
1044 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1045 {
1046 struct mips32_common *mips32 = &mips_m4k->mips32;
1047
1048 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1049
1050 /* initialize mips4k specific info */
1051 mips32_init_arch_info(target, mips32, tap);
1052 mips32->arch_info = mips_m4k;
1053
1054 return ERROR_OK;
1055 }
1056
1057 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1058 {
1059 struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1060
1061 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1062
1063 return ERROR_OK;
1064 }
1065
1066 static int mips_m4k_examine(struct target *target)
1067 {
1068 int retval;
1069 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1070 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1071 uint32_t idcode = 0;
1072
1073 if (!target_was_examined(target)) {
1074 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1075 if (retval != ERROR_OK)
1076 return retval;
1077 ejtag_info->idcode = idcode;
1078
1079 if (((idcode >> 1) & 0x7FF) == 0x29) {
1080 /* we are using a pic32mx so select ejtag port
1081 * as it is not selected by default */
1082 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1083 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1084 mips_m4k->is_pic32mx = true;
1085 }
1086 }
1087
1088 /* init rest of ejtag interface */
1089 retval = mips_ejtag_init(ejtag_info);
1090 if (retval != ERROR_OK)
1091 return retval;
1092
1093 retval = mips32_examine(target);
1094 if (retval != ERROR_OK)
1095 return retval;
1096
1097 return ERROR_OK;
1098 }
1099
1100 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
1101 uint32_t count, const uint8_t *buffer)
1102 {
1103 struct mips32_common *mips32 = target_to_mips32(target);
1104 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1105 int retval;
1106 int write_t = 1;
1107
1108 LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
1109
1110 /* check alignment */
1111 if (address & 0x3u)
1112 return ERROR_TARGET_UNALIGNED_ACCESS;
1113
1114 if (mips32->fast_data_area == NULL) {
1115 /* Get memory for block write handler
1116 * we preserve this area between calls and gain a speed increase
1117 * of about 3kb/sec when writing flash
1118 * this will be released/nulled by the system when the target is resumed or reset */
1119 retval = target_alloc_working_area(target,
1120 MIPS32_FASTDATA_HANDLER_SIZE,
1121 &mips32->fast_data_area);
1122 if (retval != ERROR_OK) {
1123 LOG_ERROR("No working area available");
1124 return retval;
1125 }
1126
1127 /* reset fastadata state so the algo get reloaded */
1128 ejtag_info->fast_access_save = -1;
1129 }
1130
1131 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1132 /* but byte array represents target endianness */
1133 uint32_t *t = NULL;
1134 t = malloc(count * sizeof(uint32_t));
1135 if (t == NULL) {
1136 LOG_ERROR("Out of memory");
1137 return ERROR_FAIL;
1138 }
1139
1140 target_buffer_get_u32_array(target, buffer, count, t);
1141
1142 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1143 count, t);
1144
1145 if (t != NULL)
1146 free(t);
1147
1148 if (retval != ERROR_OK)
1149 LOG_ERROR("Fastdata access Failed");
1150
1151 return retval;
1152 }
1153
1154 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1155 struct mips_m4k_common *mips_m4k)
1156 {
1157 if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1158 command_print(cmd_ctx, "target is not an MIPS_M4K");
1159 return ERROR_TARGET_INVALID;
1160 }
1161 return ERROR_OK;
1162 }
1163
1164 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1165 {
1166 int retval;
1167 struct target *target = get_current_target(CMD_CTX);
1168 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1169 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1170
1171 retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1172 if (retval != ERROR_OK)
1173 return retval;
1174
1175 if (target->state != TARGET_HALTED) {
1176 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1177 return ERROR_OK;
1178 }
1179
1180 /* two or more argument, access a single register/select (write if third argument is given) */
1181 if (CMD_ARGC < 2)
1182 return ERROR_COMMAND_SYNTAX_ERROR;
1183 else {
1184 uint32_t cp0_reg, cp0_sel;
1185 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1186 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1187
1188 if (CMD_ARGC == 2) {
1189 uint32_t value;
1190 retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1191 if (retval != ERROR_OK) {
1192 command_print(CMD_CTX,
1193 "couldn't access reg %" PRIi32,
1194 cp0_reg);
1195 return ERROR_OK;
1196 }
1197 command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1198 cp0_reg, cp0_sel, value);
1199
1200 } else if (CMD_ARGC == 3) {
1201 uint32_t value;
1202 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1203 retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1204 if (retval != ERROR_OK) {
1205 command_print(CMD_CTX,
1206 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1207 cp0_reg, cp0_sel);
1208 return ERROR_OK;
1209 }
1210 command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1211 cp0_reg, cp0_sel, value);
1212 }
1213 }
1214
1215 return ERROR_OK;
1216 }
1217
1218 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1219 {
1220 struct target *target = get_current_target(CMD_CTX);
1221 /* check target is an smp target */
1222 struct target_list *head;
1223 struct target *curr;
1224 head = target->head;
1225 target->smp = 0;
1226 if (head != (struct target_list *)NULL) {
1227 while (head != (struct target_list *)NULL) {
1228 curr = head->target;
1229 curr->smp = 0;
1230 head = head->next;
1231 }
1232 /* fixes the target display to the debugger */
1233 target->gdb_service->target = target;
1234 }
1235 return ERROR_OK;
1236 }
1237
1238 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1239 {
1240 struct target *target = get_current_target(CMD_CTX);
1241 struct target_list *head;
1242 struct target *curr;
1243 head = target->head;
1244 if (head != (struct target_list *)NULL) {
1245 target->smp = 1;
1246 while (head != (struct target_list *)NULL) {
1247 curr = head->target;
1248 curr->smp = 1;
1249 head = head->next;
1250 }
1251 }
1252 return ERROR_OK;
1253 }
1254
1255 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1256 {
1257 struct target *target = get_current_target(CMD_CTX);
1258 int retval = ERROR_OK;
1259 struct target_list *head;
1260 head = target->head;
1261 if (head != (struct target_list *)NULL) {
1262 if (CMD_ARGC == 1) {
1263 int coreid = 0;
1264 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1265 if (ERROR_OK != retval)
1266 return retval;
1267 target->gdb_service->core[1] = coreid;
1268
1269 }
1270 command_print(CMD_CTX, "gdb coreid %d -> %d", target->gdb_service->core[0]
1271 , target->gdb_service->core[1]);
1272 }
1273 return ERROR_OK;
1274 }
1275
1276 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1277 {
1278 struct target *target = get_current_target(CMD_CTX);
1279 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1280 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1281
1282 if (CMD_ARGC == 1)
1283 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], ejtag_info->scan_delay);
1284 else if (CMD_ARGC > 1)
1285 return ERROR_COMMAND_SYNTAX_ERROR;
1286
1287 command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1288 if (ejtag_info->scan_delay >= 20000000) {
1289 ejtag_info->mode = 0;
1290 command_print(CMD_CTX, "running in legacy mode");
1291 } else {
1292 ejtag_info->mode = 1;
1293 command_print(CMD_CTX, "running in fast queued mode");
1294 }
1295
1296 return ERROR_OK;
1297 }
1298
1299 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1300 {
1301 .name = "cp0",
1302 .handler = mips_m4k_handle_cp0_command,
1303 .mode = COMMAND_EXEC,
1304 .usage = "regnum [value]",
1305 .help = "display/modify cp0 register",
1306 },
1307 {
1308 .name = "smp_off",
1309 .handler = mips_m4k_handle_smp_off_command,
1310 .mode = COMMAND_EXEC,
1311 .help = "Stop smp handling",
1312 .usage = "",},
1313
1314 {
1315 .name = "smp_on",
1316 .handler = mips_m4k_handle_smp_on_command,
1317 .mode = COMMAND_EXEC,
1318 .help = "Restart smp handling",
1319 .usage = "",
1320 },
1321 {
1322 .name = "smp_gdb",
1323 .handler = mips_m4k_handle_smp_gdb_command,
1324 .mode = COMMAND_EXEC,
1325 .help = "display/fix current core played to gdb",
1326 .usage = "",
1327 },
1328 {
1329 .name = "scan_delay",
1330 .handler = mips_m4k_handle_scan_delay_command,
1331 .mode = COMMAND_ANY,
1332 .help = "display/set scan delay in nano seconds",
1333 .usage = "[value]",
1334 },
1335 COMMAND_REGISTRATION_DONE
1336 };
1337
1338 const struct command_registration mips_m4k_command_handlers[] = {
1339 {
1340 .chain = mips32_command_handlers,
1341 },
1342 {
1343 .name = "mips_m4k",
1344 .mode = COMMAND_ANY,
1345 .help = "mips_m4k command group",
1346 .usage = "",
1347 .chain = mips_m4k_exec_command_handlers,
1348 },
1349 COMMAND_REGISTRATION_DONE
1350 };
1351
1352 struct target_type mips_m4k_target = {
1353 .name = "mips_m4k",
1354
1355 .poll = mips_m4k_poll,
1356 .arch_state = mips32_arch_state,
1357
1358 .target_request_data = NULL,
1359
1360 .halt = mips_m4k_halt,
1361 .resume = mips_m4k_resume,
1362 .step = mips_m4k_step,
1363
1364 .assert_reset = mips_m4k_assert_reset,
1365 .deassert_reset = mips_m4k_deassert_reset,
1366 .soft_reset_halt = mips_m4k_soft_reset_halt,
1367
1368 .get_gdb_reg_list = mips32_get_gdb_reg_list,
1369
1370 .read_memory = mips_m4k_read_memory,
1371 .write_memory = mips_m4k_write_memory,
1372 .checksum_memory = mips32_checksum_memory,
1373 .blank_check_memory = mips32_blank_check_memory,
1374
1375 .run_algorithm = mips32_run_algorithm,
1376
1377 .add_breakpoint = mips_m4k_add_breakpoint,
1378 .remove_breakpoint = mips_m4k_remove_breakpoint,
1379 .add_watchpoint = mips_m4k_add_watchpoint,
1380 .remove_watchpoint = mips_m4k_remove_watchpoint,
1381
1382 .commands = mips_m4k_command_handlers,
1383 .target_create = mips_m4k_target_create,
1384 .init_target = mips_m4k_init_target,
1385 .examine = mips_m4k_examine,
1386 };
Official OpenOCD Mirror