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* configure.ac: Add test for ARM TLS support.
[official-gcc.git] / gcc / config / arm / arm.h
blob2bca1538dc1a5dd48e2ef9f1ed310d52a999edc2
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The architecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 extern GTY(()) rtx arm_compare_op0;
123 extern GTY(()) rtx arm_compare_op1;
124 /* The label of the current constant pool. */
125 extern rtx pool_vector_label;
126 /* Set to 1 when a return insn is output, this means that the epilogue
127 is not needed. */
128 extern int return_used_this_function;
129 /* Used to produce AOF syntax assembler. */
130 extern GTY(()) rtx aof_pic_label;
131 \f
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
135 #endif
136
137
138 #undef CPP_SPEC
139 #define CPP_SPEC "%(subtarget_cpp_spec) \
140 %{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142 %{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
144
145 #ifndef CC1_SPEC
146 #define CC1_SPEC ""
147 #endif
148
149 /* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
152
153 Each subgrouping contains a string constant, that defines the
154 specification name, and a string constant that used by the GCC driver
155 program.
156
157 Do not define this macro if it does not need to do anything. */
158 #define EXTRA_SPECS \
159 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
160 SUBTARGET_EXTRA_SPECS
161
162 #ifndef SUBTARGET_EXTRA_SPECS
163 #define SUBTARGET_EXTRA_SPECS
164 #endif
165
166 #ifndef SUBTARGET_CPP_SPEC
167 #define SUBTARGET_CPP_SPEC ""
168 #endif
169 \f
170 /* Run-time Target Specification. */
171 #ifndef TARGET_VERSION
172 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
173 #endif
174
175 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
176 /* Use hardware floating point instructions. */
177 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point calling convention. */
179 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
180 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
183 #define TARGET_IWMMXT (arm_arch_iwmmxt)
184 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
185 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
186 #define TARGET_ARM (! TARGET_THUMB)
187 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
188 #define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
190 : TARGET_TPCS_FRAME)
191 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
192 #define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
194
195 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
196 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
197
198 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
199 then TARGET_AAPCS_BASED must be true -- but the converse does not
200 hold. TARGET_BPABI implies the use of the BPABI runtime library,
201 etc., in addition to just the AAPCS calling conventions. */
202 #ifndef TARGET_BPABI
203 #define TARGET_BPABI false
204 #endif
205
206 /* Support for a compile-time default CPU, et cetera. The rules are:
207 --with-arch is ignored if -march or -mcpu are specified.
208 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
209 by --with-arch.
210 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
211 by -march).
212 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
213 specified.
214 --with-fpu is ignored if -mfpu is specified.
215 --with-abi is ignored is -mabi is specified. */
216 #define OPTION_DEFAULT_SPECS \
217 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
218 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
219 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
220 {"float", \
221 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
222 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
223 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
224
225 /* Which floating point model to use. */
226 enum arm_fp_model
227 {
228 ARM_FP_MODEL_UNKNOWN,
229 /* FPA model (Hardware or software). */
230 ARM_FP_MODEL_FPA,
231 /* Cirrus Maverick floating point model. */
232 ARM_FP_MODEL_MAVERICK,
233 /* VFP floating point model. */
234 ARM_FP_MODEL_VFP
235 };
236
237 extern enum arm_fp_model arm_fp_model;
238
239 /* Which floating point hardware is available. Also update
240 fp_model_for_fpu in arm.c when adding entries to this list. */
241 enum fputype
242 {
243 /* No FP hardware. */
244 FPUTYPE_NONE,
245 /* Full FPA support. */
246 FPUTYPE_FPA,
247 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
248 FPUTYPE_FPA_EMU2,
249 /* Emulated FPA hardware, Issue 3 emulator. */
250 FPUTYPE_FPA_EMU3,
251 /* Cirrus Maverick floating point co-processor. */
252 FPUTYPE_MAVERICK,
253 /* VFP. */
254 FPUTYPE_VFP
255 };
256
257 /* Recast the floating point class to be the floating point attribute. */
258 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
259
260 /* What type of floating point to tune for */
261 extern enum fputype arm_fpu_tune;
262
263 /* What type of floating point instructions are available */
264 extern enum fputype arm_fpu_arch;
265
266 enum float_abi_type
267 {
268 ARM_FLOAT_ABI_SOFT,
269 ARM_FLOAT_ABI_SOFTFP,
270 ARM_FLOAT_ABI_HARD
271 };
272
273 extern enum float_abi_type arm_float_abi;
274
275 #ifndef TARGET_DEFAULT_FLOAT_ABI
276 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
277 #endif
278
279 /* Which ABI to use. */
280 enum arm_abi_type
281 {
282 ARM_ABI_APCS,
283 ARM_ABI_ATPCS,
284 ARM_ABI_AAPCS,
285 ARM_ABI_IWMMXT,
286 ARM_ABI_AAPCS_LINUX
287 };
288
289 extern enum arm_abi_type arm_abi;
290
291 #ifndef ARM_DEFAULT_ABI
292 #define ARM_DEFAULT_ABI ARM_ABI_APCS
293 #endif
294
295 /* Which thread pointer access sequence to use. */
296 enum arm_tp_type {
297 TP_AUTO,
298 TP_SOFT,
299 TP_CP15
300 };
301
302 extern enum arm_tp_type target_thread_pointer;
303
304 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
305 extern int arm_arch3m;
306
307 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
308 extern int arm_arch4;
309
310 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
311 extern int arm_arch4t;
312
313 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
314 extern int arm_arch5;
315
316 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
317 extern int arm_arch5e;
318
319 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
320 extern int arm_arch6;
321
322 /* Nonzero if this chip can benefit from load scheduling. */
323 extern int arm_ld_sched;
324
325 /* Nonzero if generating thumb code. */
326 extern int thumb_code;
327
328 /* Nonzero if this chip is a StrongARM. */
329 extern int arm_tune_strongarm;
330
331 /* Nonzero if this chip is a Cirrus variant. */
332 extern int arm_arch_cirrus;
333
334 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
335 extern int arm_arch_iwmmxt;
336
337 /* Nonzero if this chip is an XScale. */
338 extern int arm_arch_xscale;
339
340 /* Nonzero if tuning for XScale. */
341 extern int arm_tune_xscale;
342
343 /* Nonzero if tuning for stores via the write buffer. */
344 extern int arm_tune_wbuf;
345
346 /* Nonzero if we should define __THUMB_INTERWORK__ in the
347 preprocessor.
348 XXX This is a bit of a hack, it's intended to help work around
349 problems in GLD which doesn't understand that armv5t code is
350 interworking clean. */
351 extern int arm_cpp_interwork;
352
353 #ifndef TARGET_DEFAULT
354 #define TARGET_DEFAULT (MASK_APCS_FRAME)
355 #endif
356
357 /* The frame pointer register used in gcc has nothing to do with debugging;
358 that is controlled by the APCS-FRAME option. */
359 #define CAN_DEBUG_WITHOUT_FP
360
361 #define OVERRIDE_OPTIONS arm_override_options ()
362
363 /* Nonzero if PIC code requires explicit qualifiers to generate
364 PLT and GOT relocs rather than the assembler doing so implicitly.
365 Subtargets can override these if required. */
366 #ifndef NEED_GOT_RELOC
367 #define NEED_GOT_RELOC 0
368 #endif
369 #ifndef NEED_PLT_RELOC
370 #define NEED_PLT_RELOC 0
371 #endif
372
373 /* Nonzero if we need to refer to the GOT with a PC-relative
374 offset. In other words, generate
375
376 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
377
378 rather than
379
380 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
381
382 The default is true, which matches NetBSD. Subtargets can
383 override this if required. */
384 #ifndef GOT_PCREL
385 #define GOT_PCREL 1
386 #endif
387 \f
388 /* Target machine storage Layout. */
389
390
391 /* Define this macro if it is advisable to hold scalars in registers
392 in a wider mode than that declared by the program. In such cases,
393 the value is constrained to be within the bounds of the declared
394 type, but kept valid in the wider mode. The signedness of the
395 extension may differ from that of the type. */
396
397 /* It is far faster to zero extend chars than to sign extend them */
398
399 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
400 if (GET_MODE_CLASS (MODE) == MODE_INT \
401 && GET_MODE_SIZE (MODE) < 4) \
402 { \
403 if (MODE == QImode) \
404 UNSIGNEDP = 1; \
405 else if (MODE == HImode) \
406 UNSIGNEDP = 1; \
407 (MODE) = SImode; \
408 }
409
410 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
411 if ((GET_MODE_CLASS (MODE) == MODE_INT \
412 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
413 && GET_MODE_SIZE (MODE) < 4) \
414 (MODE) = SImode; \
415
416 /* Define this if most significant bit is lowest numbered
417 in instructions that operate on numbered bit-fields. */
418 #define BITS_BIG_ENDIAN 0
419
420 /* Define this if most significant byte of a word is the lowest numbered.
421 Most ARM processors are run in little endian mode, so that is the default.
422 If you want to have it run-time selectable, change the definition in a
423 cover file to be TARGET_BIG_ENDIAN. */
424 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
425
426 /* Define this if most significant word of a multiword number is the lowest
427 numbered.
428 This is always false, even when in big-endian mode. */
429 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
430
431 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
432 on processor pre-defineds when compiling libgcc2.c. */
433 #if defined(__ARMEB__) && !defined(__ARMWEL__)
434 #define LIBGCC2_WORDS_BIG_ENDIAN 1
435 #else
436 #define LIBGCC2_WORDS_BIG_ENDIAN 0
437 #endif
438
439 /* Define this if most significant word of doubles is the lowest numbered.
440 The rules are different based on whether or not we use FPA-format,
441 VFP-format or some other floating point co-processor's format doubles. */
442 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
443
444 #define UNITS_PER_WORD 4
445
446 /* True if natural alignment is used for doubleword types. */
447 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
448
449 #define DOUBLEWORD_ALIGNMENT 64
450
451 #define PARM_BOUNDARY 32
452
453 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
454
455 #define PREFERRED_STACK_BOUNDARY \
456 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
457
458 #define FUNCTION_BOUNDARY 32
459
460 /* The lowest bit is used to indicate Thumb-mode functions, so the
461 vbit must go into the delta field of pointers to member
462 functions. */
463 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
464
465 #define EMPTY_FIELD_BOUNDARY 32
466
467 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
468
469 /* XXX Blah -- this macro is used directly by libobjc. Since it
470 supports no vector modes, cut out the complexity and fall back
471 on BIGGEST_FIELD_ALIGNMENT. */
472 #ifdef IN_TARGET_LIBS
473 #define BIGGEST_FIELD_ALIGNMENT 64
474 #endif
475
476 /* Make strings word-aligned so strcpy from constants will be faster. */
477 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
478
479 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
480 ((TREE_CODE (EXP) == STRING_CST \
481 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
482 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
483
484 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
485 value set in previous versions of this toolchain was 8, which produces more
486 compact structures. The command line option -mstructure_size_boundary=<n>
487 can be used to change this value. For compatibility with the ARM SDK
488 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
489 0020D) page 2-20 says "Structures are aligned on word boundaries".
490 The AAPCS specifies a value of 8. */
491 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
492 extern int arm_structure_size_boundary;
493
494 /* This is the value used to initialize arm_structure_size_boundary. If a
495 particular arm target wants to change the default value it should change
496 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
497 for an example of this. */
498 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
499 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
500 #endif
501
502 /* Nonzero if move instructions will actually fail to work
503 when given unaligned data. */
504 #define STRICT_ALIGNMENT 1
505
506 /* wchar_t is unsigned under the AAPCS. */
507 #ifndef WCHAR_TYPE
508 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
509
510 #define WCHAR_TYPE_SIZE BITS_PER_WORD
511 #endif
512
513 #ifndef SIZE_TYPE
514 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
515 #endif
516
517 #ifndef PTRDIFF_TYPE
518 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
519 #endif
520
521 /* AAPCS requires that structure alignment is affected by bitfields. */
522 #ifndef PCC_BITFIELD_TYPE_MATTERS
523 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
524 #endif
525
526 \f
527 /* Standard register usage. */
528
529 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
530 (S - saved over call).
531
532 r0 * argument word/integer result
533 r1-r3 argument word
534
535 r4-r8 S register variable
536 r9 S (rfp) register variable (real frame pointer)
537
538 r10 F S (sl) stack limit (used by -mapcs-stack-check)
539 r11 F S (fp) argument pointer
540 r12 (ip) temp workspace
541 r13 F S (sp) lower end of current stack frame
542 r14 (lr) link address/workspace
543 r15 F (pc) program counter
544
545 f0 floating point result
546 f1-f3 floating point scratch
547
548 f4-f7 S floating point variable
549
550 cc This is NOT a real register, but is used internally
551 to represent things that use or set the condition
552 codes.
553 sfp This isn't either. It is used during rtl generation
554 since the offset between the frame pointer and the
555 auto's isn't known until after register allocation.
556 afp Nor this, we only need this because of non-local
557 goto. Without it fp appears to be used and the
558 elimination code won't get rid of sfp. It tracks
559 fp exactly at all times.
560
561 *: See CONDITIONAL_REGISTER_USAGE */
562
563 /*
564 mvf0 Cirrus floating point result
565 mvf1-mvf3 Cirrus floating point scratch
566 mvf4-mvf15 S Cirrus floating point variable. */
567
568 /* s0-s15 VFP scratch (aka d0-d7).
569 s16-s31 S VFP variable (aka d8-d15).
570 vfpcc Not a real register. Represents the VFP condition
571 code flags. */
572
573 /* The stack backtrace structure is as follows:
574 fp points to here: | save code pointer | [fp]
575 | return link value | [fp, #-4]
576 | return sp value | [fp, #-8]
577 | return fp value | [fp, #-12]
578 [| saved r10 value |]
579 [| saved r9 value |]
580 [| saved r8 value |]
581 [| saved r7 value |]
582 [| saved r6 value |]
583 [| saved r5 value |]
584 [| saved r4 value |]
585 [| saved r3 value |]
586 [| saved r2 value |]
587 [| saved r1 value |]
588 [| saved r0 value |]
589 [| saved f7 value |] three words
590 [| saved f6 value |] three words
591 [| saved f5 value |] three words
592 [| saved f4 value |] three words
593 r0-r3 are not normally saved in a C function. */
594
595 /* 1 for registers that have pervasive standard uses
596 and are not available for the register allocator. */
597 #define FIXED_REGISTERS \
598 { \
599 0,0,0,0,0,0,0,0, \
600 0,0,0,0,0,1,0,1, \
601 0,0,0,0,0,0,0,0, \
602 1,1,1, \
603 1,1,1,1,1,1,1,1, \
604 1,1,1,1,1,1,1,1, \
605 1,1,1,1,1,1,1,1, \
606 1,1,1,1,1,1,1,1, \
607 1,1,1,1, \
608 1,1,1,1,1,1,1,1, \
609 1,1,1,1,1,1,1,1, \
610 1,1,1,1,1,1,1,1, \
611 1,1,1,1,1,1,1,1, \
612 1 \
613 }
614
615 /* 1 for registers not available across function calls.
616 These must include the FIXED_REGISTERS and also any
617 registers that can be used without being saved.
618 The latter must include the registers where values are returned
619 and the register where structure-value addresses are passed.
620 Aside from that, you can include as many other registers as you like.
621 The CC is not preserved over function calls on the ARM 6, so it is
622 easier to assume this for all. SFP is preserved, since FP is. */
623 #define CALL_USED_REGISTERS \
624 { \
625 1,1,1,1,0,0,0,0, \
626 0,0,0,0,1,1,1,1, \
627 1,1,1,1,0,0,0,0, \
628 1,1,1, \
629 1,1,1,1,1,1,1,1, \
630 1,1,1,1,1,1,1,1, \
631 1,1,1,1,1,1,1,1, \
632 1,1,1,1,1,1,1,1, \
633 1,1,1,1, \
634 1,1,1,1,1,1,1,1, \
635 1,1,1,1,1,1,1,1, \
636 1,1,1,1,1,1,1,1, \
637 1,1,1,1,1,1,1,1, \
638 1 \
639 }
640
641 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
642 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
643 #endif
644
645 #define CONDITIONAL_REGISTER_USAGE \
646 { \
647 int regno; \
648 \
649 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
650 { \
651 for (regno = FIRST_FPA_REGNUM; \
652 regno <= LAST_FPA_REGNUM; ++regno) \
653 fixed_regs[regno] = call_used_regs[regno] = 1; \
654 } \
655 \
656 if (TARGET_THUMB && optimize_size) \
657 { \
658 /* When optimizing for size, it's better not to use \
659 the HI regs, because of the overhead of stacking \
660 them. */ \
661 for (regno = FIRST_HI_REGNUM; \
662 regno <= LAST_HI_REGNUM; ++regno) \
663 fixed_regs[regno] = call_used_regs[regno] = 1; \
664 } \
665 \
666 /* The link register can be clobbered by any branch insn, \
667 but we have no way to track that at present, so mark \
668 it as unavailable. */ \
669 if (TARGET_THUMB) \
670 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
671 \
672 if (TARGET_ARM && TARGET_HARD_FLOAT) \
673 { \
674 if (TARGET_MAVERICK) \
675 { \
676 for (regno = FIRST_FPA_REGNUM; \
677 regno <= LAST_FPA_REGNUM; ++ regno) \
678 fixed_regs[regno] = call_used_regs[regno] = 1; \
679 for (regno = FIRST_CIRRUS_FP_REGNUM; \
680 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
681 { \
682 fixed_regs[regno] = 0; \
683 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
684 } \
685 } \
686 if (TARGET_VFP) \
687 { \
688 for (regno = FIRST_VFP_REGNUM; \
689 regno <= LAST_VFP_REGNUM; ++ regno) \
690 { \
691 fixed_regs[regno] = 0; \
692 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
693 } \
694 } \
695 } \
696 \
697 if (TARGET_REALLY_IWMMXT) \
698 { \
699 regno = FIRST_IWMMXT_GR_REGNUM; \
700 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
701 and wCG1 as call-preserved registers. The 2002/11/21 \
702 revision changed this so that all wCG registers are \
703 scratch registers. */ \
704 for (regno = FIRST_IWMMXT_GR_REGNUM; \
705 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
706 fixed_regs[regno] = 0; \
707 /* The XScale ABI has wR0 - wR9 as scratch registers, \
708 the rest as call-preserved registers. */ \
709 for (regno = FIRST_IWMMXT_REGNUM; \
710 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
711 { \
712 fixed_regs[regno] = 0; \
713 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
714 } \
715 } \
716 \
717 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
718 { \
719 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
720 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
721 } \
722 else if (TARGET_APCS_STACK) \
723 { \
724 fixed_regs[10] = 1; \
725 call_used_regs[10] = 1; \
726 } \
727 /* -mcaller-super-interworking reserves r11 for calls to \
728 _interwork_r11_call_via_rN(). Making the register global \
729 is an easy way of ensuring that it remains valid for all \
730 calls. */ \
731 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
732 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
733 { \
734 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
735 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
736 if (TARGET_CALLER_INTERWORKING) \
737 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
738 } \
739 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
740 }
741
742 /* These are a couple of extensions to the formats accepted
743 by asm_fprintf:
744 %@ prints out ASM_COMMENT_START
745 %r prints out REGISTER_PREFIX reg_names[arg] */
746 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
747 case '@': \
748 fputs (ASM_COMMENT_START, FILE); \
749 break; \
750 \
751 case 'r': \
752 fputs (REGISTER_PREFIX, FILE); \
753 fputs (reg_names [va_arg (ARGS, int)], FILE); \
754 break;
755
756 /* Round X up to the nearest word. */
757 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
758
759 /* Convert fron bytes to ints. */
760 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
761
762 /* The number of (integer) registers required to hold a quantity of type MODE.
763 Also used for VFP registers. */
764 #define ARM_NUM_REGS(MODE) \
765 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
766
767 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
768 #define ARM_NUM_REGS2(MODE, TYPE) \
769 ARM_NUM_INTS ((MODE) == BLKmode ? \
770 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
771
772 /* The number of (integer) argument register available. */
773 #define NUM_ARG_REGS 4
774
775 /* Return the register number of the N'th (integer) argument. */
776 #define ARG_REGISTER(N) (N - 1)
777
778 /* Specify the registers used for certain standard purposes.
779 The values of these macros are register numbers. */
780
781 /* The number of the last argument register. */
782 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
783
784 /* The numbers of the Thumb register ranges. */
785 #define FIRST_LO_REGNUM 0
786 #define LAST_LO_REGNUM 7
787 #define FIRST_HI_REGNUM 8
788 #define LAST_HI_REGNUM 11
789
790 #ifndef TARGET_UNWIND_INFO
791 /* We use sjlj exceptions for backwards compatibility. */
792 #define MUST_USE_SJLJ_EXCEPTIONS 1
793 #endif
794
795 /* We can generate DWARF2 Unwind info, even though we don't use it. */
796 #define DWARF2_UNWIND_INFO 1
797
798 /* Use r0 and r1 to pass exception handling information. */
799 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
800
801 /* The register that holds the return address in exception handlers. */
802 #define ARM_EH_STACKADJ_REGNUM 2
803 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
804
805 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
806 as an invisible last argument (possible since varargs don't exist in
807 Pascal), so the following is not true. */
808 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
809
810 /* Define this to be where the real frame pointer is if it is not possible to
811 work out the offset between the frame pointer and the automatic variables
812 until after register allocation has taken place. FRAME_POINTER_REGNUM
813 should point to a special register that we will make sure is eliminated.
814
815 For the Thumb we have another problem. The TPCS defines the frame pointer
816 as r11, and GCC believes that it is always possible to use the frame pointer
817 as base register for addressing purposes. (See comments in
818 find_reloads_address()). But - the Thumb does not allow high registers,
819 including r11, to be used as base address registers. Hence our problem.
820
821 The solution used here, and in the old thumb port is to use r7 instead of
822 r11 as the hard frame pointer and to have special code to generate
823 backtrace structures on the stack (if required to do so via a command line
824 option) using r11. This is the only 'user visible' use of r11 as a frame
825 pointer. */
826 #define ARM_HARD_FRAME_POINTER_REGNUM 11
827 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
828
829 #define HARD_FRAME_POINTER_REGNUM \
830 (TARGET_ARM \
831 ? ARM_HARD_FRAME_POINTER_REGNUM \
832 : THUMB_HARD_FRAME_POINTER_REGNUM)
833
834 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
835
836 /* Register to use for pushing function arguments. */
837 #define STACK_POINTER_REGNUM SP_REGNUM
838
839 /* ARM floating pointer registers. */
840 #define FIRST_FPA_REGNUM 16
841 #define LAST_FPA_REGNUM 23
842 #define IS_FPA_REGNUM(REGNUM) \
843 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
844
845 #define FIRST_IWMMXT_GR_REGNUM 43
846 #define LAST_IWMMXT_GR_REGNUM 46
847 #define FIRST_IWMMXT_REGNUM 47
848 #define LAST_IWMMXT_REGNUM 62
849 #define IS_IWMMXT_REGNUM(REGNUM) \
850 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
851 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
852 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
853
854 /* Base register for access to local variables of the function. */
855 #define FRAME_POINTER_REGNUM 25
856
857 /* Base register for access to arguments of the function. */
858 #define ARG_POINTER_REGNUM 26
859
860 #define FIRST_CIRRUS_FP_REGNUM 27
861 #define LAST_CIRRUS_FP_REGNUM 42
862 #define IS_CIRRUS_REGNUM(REGNUM) \
863 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
864
865 #define FIRST_VFP_REGNUM 63
866 #define LAST_VFP_REGNUM 94
867 #define IS_VFP_REGNUM(REGNUM) \
868 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
869
870 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
871 /* + 16 Cirrus registers take us up to 43. */
872 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
873 /* VFP adds 32 + 1 more. */
874 #define FIRST_PSEUDO_REGISTER 96
875
876 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
877
878 /* Value should be nonzero if functions must have frame pointers.
879 Zero means the frame pointer need not be set up (and parms may be accessed
880 via the stack pointer) in functions that seem suitable.
881 If we have to have a frame pointer we might as well make use of it.
882 APCS says that the frame pointer does not need to be pushed in leaf
883 functions, or simple tail call functions. */
884
885 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
886 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
887 #endif
888
889 #define FRAME_POINTER_REQUIRED \
890 (current_function_has_nonlocal_label \
891 || SUBTARGET_FRAME_POINTER_REQUIRED \
892 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
893
894 /* Return number of consecutive hard regs needed starting at reg REGNO
895 to hold something of mode MODE.
896 This is ordinarily the length in words of a value of mode MODE
897 but can be less for certain modes in special long registers.
898
899 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
900 mode. */
901 #define HARD_REGNO_NREGS(REGNO, MODE) \
902 ((TARGET_ARM \
903 && REGNO >= FIRST_FPA_REGNUM \
904 && REGNO != FRAME_POINTER_REGNUM \
905 && REGNO != ARG_POINTER_REGNUM) \
906 && !IS_VFP_REGNUM (REGNO) \
907 ? 1 : ARM_NUM_REGS (MODE))
908
909 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
910 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
911 arm_hard_regno_mode_ok ((REGNO), (MODE))
912
913 /* Value is 1 if it is a good idea to tie two pseudo registers
914 when one has mode MODE1 and one has mode MODE2.
915 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
916 for any hard reg, then this must be 0 for correct output. */
917 #define MODES_TIEABLE_P(MODE1, MODE2) \
918 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
919
920 #define VALID_IWMMXT_REG_MODE(MODE) \
921 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
922
923 /* The order in which register should be allocated. It is good to use ip
924 since no saving is required (though calls clobber it) and it never contains
925 function parameters. It is quite good to use lr since other calls may
926 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
927 least likely to contain a function parameter; in addition results are
928 returned in r0. */
929
930 #define REG_ALLOC_ORDER \
931 { \
932 3, 2, 1, 0, 12, 14, 4, 5, \
933 6, 7, 8, 10, 9, 11, 13, 15, \
934 16, 17, 18, 19, 20, 21, 22, 23, \
935 27, 28, 29, 30, 31, 32, 33, 34, \
936 35, 36, 37, 38, 39, 40, 41, 42, \
937 43, 44, 45, 46, 47, 48, 49, 50, \
938 51, 52, 53, 54, 55, 56, 57, 58, \
939 59, 60, 61, 62, \
940 24, 25, 26, \
941 78, 77, 76, 75, 74, 73, 72, 71, \
942 70, 69, 68, 67, 66, 65, 64, 63, \
943 79, 80, 81, 82, 83, 84, 85, 86, \
944 87, 88, 89, 90, 91, 92, 93, 94, \
945 95 \
946 }
947
948 /* Interrupt functions can only use registers that have already been
949 saved by the prologue, even if they would normally be
950 call-clobbered. */
951 #define HARD_REGNO_RENAME_OK(SRC, DST) \
952 (! IS_INTERRUPT (cfun->machine->func_type) || \
953 regs_ever_live[DST])
954 \f
955 /* Register and constant classes. */
956
957 /* Register classes: used to be simple, just all ARM regs or all FPA regs
958 Now that the Thumb is involved it has become more complicated. */
959 enum reg_class
960 {
961 NO_REGS,
962 FPA_REGS,
963 CIRRUS_REGS,
964 VFP_REGS,
965 IWMMXT_GR_REGS,
966 IWMMXT_REGS,
967 LO_REGS,
968 STACK_REG,
969 BASE_REGS,
970 HI_REGS,
971 CC_REG,
972 VFPCC_REG,
973 GENERAL_REGS,
974 ALL_REGS,
975 LIM_REG_CLASSES
976 };
977
978 #define N_REG_CLASSES (int) LIM_REG_CLASSES
979
980 /* Give names of register classes as strings for dump file. */
981 #define REG_CLASS_NAMES \
982 { \
983 "NO_REGS", \
984 "FPA_REGS", \
985 "CIRRUS_REGS", \
986 "VFP_REGS", \
987 "IWMMXT_GR_REGS", \
988 "IWMMXT_REGS", \
989 "LO_REGS", \
990 "STACK_REG", \
991 "BASE_REGS", \
992 "HI_REGS", \
993 "CC_REG", \
994 "VFPCC_REG", \
995 "GENERAL_REGS", \
996 "ALL_REGS", \
997 }
998
999 /* Define which registers fit in which classes.
1000 This is an initializer for a vector of HARD_REG_SET
1001 of length N_REG_CLASSES. */
1002 #define REG_CLASS_CONTENTS \
1003 { \
1004 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1005 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1006 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1007 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1008 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1009 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1010 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1011 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1012 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1013 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1014 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1015 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1016 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1017 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1018 }
1019
1020 /* The same information, inverted:
1021 Return the class number of the smallest class containing
1022 reg number REGNO. This could be a conditional expression
1023 or could index an array. */
1024 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1025
1026 /* FPA registers can't do subreg as all values are reformatted to internal
1027 precision. VFP registers may only be accessed in the mode they
1028 were set. */
1029 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1030 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1031 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1032 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1033 : 0)
1034
1035 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1036 using r0-r4 for function arguments, r7 for the stack frame and don't
1037 have enough left over to do doubleword arithmetic. */
1038 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1039 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1040 || (CLASS) == CC_REG)
1041
1042 /* The class value for index registers, and the one for base regs. */
1043 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1044 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1045
1046 /* For the Thumb the high registers cannot be used as base registers
1047 when addressing quantities in QI or HI mode; if we don't know the
1048 mode, then we must be conservative. */
1049 #define MODE_BASE_REG_CLASS(MODE) \
1050 (TARGET_ARM ? GENERAL_REGS : \
1051 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1052
1053 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1054 instead of BASE_REGS. */
1055 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1056
1057 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1058 registers explicitly used in the rtl to be used as spill registers
1059 but prevents the compiler from extending the lifetime of these
1060 registers. */
1061 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1062
1063 /* Get reg_class from a letter such as appears in the machine description.
1064 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1065 ARM, but several more letters for the Thumb. */
1066 #define REG_CLASS_FROM_LETTER(C) \
1067 ( (C) == 'f' ? FPA_REGS \
1068 : (C) == 'v' ? CIRRUS_REGS \
1069 : (C) == 'w' ? VFP_REGS \
1070 : (C) == 'y' ? IWMMXT_REGS \
1071 : (C) == 'z' ? IWMMXT_GR_REGS \
1072 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1073 : TARGET_ARM ? NO_REGS \
1074 : (C) == 'h' ? HI_REGS \
1075 : (C) == 'b' ? BASE_REGS \
1076 : (C) == 'k' ? STACK_REG \
1077 : (C) == 'c' ? CC_REG \
1078 : NO_REGS)
1079
1080 /* The letters I, J, K, L and M in a register constraint string
1081 can be used to stand for particular ranges of immediate operands.
1082 This macro defines what the ranges are.
1083 C is the letter, and VALUE is a constant value.
1084 Return 1 if VALUE is in the range specified by C.
1085 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1086 J: valid indexing constants.
1087 K: ~value ok in rhs argument of data operand.
1088 L: -value ok in rhs argument of data operand.
1089 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1090 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1091 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1092 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1093 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1094 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1095 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1096 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1097 : 0)
1098
1099 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1100 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1101 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1102 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1103 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1104 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1105 && ((VAL) & 3) == 0) : \
1106 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1107 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1108 : 0)
1109
1110 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1111 (TARGET_ARM ? \
1112 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1113
1114 /* Constant letter 'G' for the FP immediate constants.
1115 'H' means the same constant negated. */
1116 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1117 ((C) == 'G' ? arm_const_double_rtx (X) : \
1118 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1119
1120 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1121 (TARGET_ARM ? \
1122 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1123
1124 /* For the ARM, `Q' means that this is a memory operand that is just
1125 an offset from a register.
1126 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1127 address. This means that the symbol is in the text segment and can be
1128 accessed without using a load.
1129 'D' Prefixes a number of const_double operands where:
1130 'Da' is a constant that takes two ARM insns to load.
1131 'Db' takes three ARM insns.
1132 'Dc' takes four ARM insns, if we allow that in this compilation.
1133 'U' Prefixes an extended memory constraint where:
1134 'Uv' is an address valid for VFP load/store insns.
1135 'Uy' is an address valid for iwmmxt load/store insns.
1136 'Uq' is an address valid for ldrsb. */
1137
1138 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1139 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1140 || GET_CODE (OP) == CONST_INT \
1141 || GET_CODE (OP) == CONST_VECTOR) \
1142 && (((STR)[1] == 'a' \
1143 && arm_const_double_inline_cost (OP) == 2) \
1144 || ((STR)[1] == 'b' \
1145 && arm_const_double_inline_cost (OP) == 3) \
1146 || ((STR)[1] == 'c' \
1147 && arm_const_double_inline_cost (OP) == 4 \
1148 && !(optimize_size || arm_ld_sched)))) : \
1149 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1150 && GET_CODE (XEXP (OP, 0)) == REG) : \
1151 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1152 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1153 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1154 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1155 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1156 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1157 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1158 ((C) == 'U' && (STR)[1] == 'q') \
1159 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1160 : 0)
1161
1162 #define CONSTRAINT_LEN(C,STR) \
1163 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1164
1165 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1166 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1167 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1168
1169 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1170 (TARGET_ARM \
1171 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1172 : EXTRA_CONSTRAINT_THUMB (X, C))
1173
1174 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1175
1176 /* Given an rtx X being reloaded into a reg required to be
1177 in class CLASS, return the class of reg to actually use.
1178 In general this is just CLASS, but for the Thumb we prefer
1179 a LO_REGS class or a subset. */
1180 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1181 (TARGET_ARM ? (CLASS) : \
1182 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1183
1184 /* Must leave BASE_REGS reloads alone */
1185 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1186 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1187 ? ((true_regnum (X) == -1 ? LO_REGS \
1188 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1189 : NO_REGS)) \
1190 : NO_REGS)
1191
1192 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1193 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1194 ? ((true_regnum (X) == -1 ? LO_REGS \
1195 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1196 : NO_REGS)) \
1197 : NO_REGS)
1198
1199 /* Return the register class of a scratch register needed to copy IN into
1200 or out of a register in CLASS in MODE. If it can be done directly,
1201 NO_REGS is returned. */
1202 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1203 /* Restrict which direct reloads are allowed for VFP regs. */ \
1204 ((TARGET_VFP && TARGET_HARD_FLOAT \
1205 && (CLASS) == VFP_REGS) \
1206 ? vfp_secondary_reload_class (MODE, X) \
1207 : TARGET_ARM \
1208 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1209 ? GENERAL_REGS : NO_REGS) \
1210 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1211
1212 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1213 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1214 /* Restrict which direct reloads are allowed for VFP regs. */ \
1215 ((TARGET_VFP && TARGET_HARD_FLOAT \
1216 && (CLASS) == VFP_REGS) \
1217 ? vfp_secondary_reload_class (MODE, X) : \
1218 /* Cannot load constants into Cirrus registers. */ \
1219 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1220 && (CLASS) == CIRRUS_REGS \
1221 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1222 ? GENERAL_REGS : \
1223 (TARGET_ARM ? \
1224 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1225 && CONSTANT_P (X)) \
1226 ? GENERAL_REGS : \
1227 (((MODE) == HImode && ! arm_arch4 \
1228 && (GET_CODE (X) == MEM \
1229 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1230 && true_regnum (X) == -1))) \
1231 ? GENERAL_REGS : NO_REGS) \
1232 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1233
1234 /* Try a machine-dependent way of reloading an illegitimate address
1235 operand. If we find one, push the reload and jump to WIN. This
1236 macro is used in only one place: `find_reloads_address' in reload.c.
1237
1238 For the ARM, we wish to handle large displacements off a base
1239 register by splitting the addend across a MOV and the mem insn.
1240 This can cut the number of reloads needed. */
1241 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1242 do \
1243 { \
1244 if (GET_CODE (X) == PLUS \
1245 && GET_CODE (XEXP (X, 0)) == REG \
1246 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1247 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1248 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1249 { \
1250 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1251 HOST_WIDE_INT low, high; \
1252 \
1253 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1254 low = ((val & 0xf) ^ 0x8) - 0x8; \
1255 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1256 /* Need to be careful, -256 is not a valid offset. */ \
1257 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1258 else if (MODE == SImode \
1259 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1260 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1261 /* Need to be careful, -4096 is not a valid offset. */ \
1262 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1263 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1264 /* Need to be careful, -256 is not a valid offset. */ \
1265 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1266 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1267 && TARGET_HARD_FLOAT && TARGET_FPA) \
1268 /* Need to be careful, -1024 is not a valid offset. */ \
1269 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1270 else \
1271 break; \
1272 \
1273 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1274 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1275 - (unsigned HOST_WIDE_INT) 0x80000000); \
1276 /* Check for overflow or zero */ \
1277 if (low == 0 || high == 0 || (high + low != val)) \
1278 break; \
1279 \
1280 /* Reload the high part into a base reg; leave the low part \
1281 in the mem. */ \
1282 X = gen_rtx_PLUS (GET_MODE (X), \
1283 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1284 GEN_INT (high)), \
1285 GEN_INT (low)); \
1286 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1287 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1288 VOIDmode, 0, 0, OPNUM, TYPE); \
1289 goto WIN; \
1290 } \
1291 } \
1292 while (0)
1293
1294 /* XXX If an HImode FP+large_offset address is converted to an HImode
1295 SP+large_offset address, then reload won't know how to fix it. It sees
1296 only that SP isn't valid for HImode, and so reloads the SP into an index
1297 register, but the resulting address is still invalid because the offset
1298 is too big. We fix it here instead by reloading the entire address. */
1299 /* We could probably achieve better results by defining PROMOTE_MODE to help
1300 cope with the variances between the Thumb's signed and unsigned byte and
1301 halfword load instructions. */
1302 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1303 do { \
1304 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1305 if (new_x) \
1306 { \
1307 X = new_x; \
1308 goto WIN; \
1309 } \
1310 } while (0)
1311
1312 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1313 if (TARGET_ARM) \
1314 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1315 else \
1316 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1317
1318 /* Return the maximum number of consecutive registers
1319 needed to represent mode MODE in a register of class CLASS.
1320 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1321 #define CLASS_MAX_NREGS(CLASS, MODE) \
1322 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1323
1324 /* If defined, gives a class of registers that cannot be used as the
1325 operand of a SUBREG that changes the mode of the object illegally. */
1326
1327 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1328 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1329 (TARGET_ARM ? \
1330 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1331 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1332 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1333 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1334 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1335 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1336 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1337 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1338 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1339 2) \
1340 : \
1341 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1342 \f
1343 /* Stack layout; function entry, exit and calling. */
1344
1345 /* Define this if pushing a word on the stack
1346 makes the stack pointer a smaller address. */
1347 #define STACK_GROWS_DOWNWARD 1
1348
1349 /* Define this to nonzero if the nominal address of the stack frame
1350 is at the high-address end of the local variables;
1351 that is, each additional local variable allocated
1352 goes at a more negative offset in the frame. */
1353 #define FRAME_GROWS_DOWNWARD 1
1354
1355 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1356 When present, it is one word in size, and sits at the top of the frame,
1357 between the soft frame pointer and either r7 or r11.
1358
1359 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1360 and only then if some outgoing arguments are passed on the stack. It would
1361 be tempting to also check whether the stack arguments are passed by indirect
1362 calls, but there seems to be no reason in principle why a post-reload pass
1363 couldn't convert a direct call into an indirect one. */
1364 #define CALLER_INTERWORKING_SLOT_SIZE \
1365 (TARGET_CALLER_INTERWORKING \
1366 && current_function_outgoing_args_size != 0 \
1367 ? UNITS_PER_WORD : 0)
1368
1369 /* Offset within stack frame to start allocating local variables at.
1370 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1371 first local allocated. Otherwise, it is the offset to the BEGINNING
1372 of the first local allocated. */
1373 #define STARTING_FRAME_OFFSET 0
1374
1375 /* If we generate an insn to push BYTES bytes,
1376 this says how many the stack pointer really advances by. */
1377 /* The push insns do not do this rounding implicitly.
1378 So don't define this. */
1379 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1380
1381 /* Define this if the maximum size of all the outgoing args is to be
1382 accumulated and pushed during the prologue. The amount can be
1383 found in the variable current_function_outgoing_args_size. */
1384 #define ACCUMULATE_OUTGOING_ARGS 1
1385
1386 /* Offset of first parameter from the argument pointer register value. */
1387 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1388
1389 /* Value is the number of byte of arguments automatically
1390 popped when returning from a subroutine call.
1391 FUNDECL is the declaration node of the function (as a tree),
1392 FUNTYPE is the data type of the function (as a tree),
1393 or for a library call it is an identifier node for the subroutine name.
1394 SIZE is the number of bytes of arguments passed on the stack.
1395
1396 On the ARM, the caller does not pop any of its arguments that were passed
1397 on the stack. */
1398 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1399
1400 /* Define how to find the value returned by a library function
1401 assuming the value has mode MODE. */
1402 #define LIBCALL_VALUE(MODE) \
1403 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1404 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1405 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1406 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1407 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1408 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1409 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1410 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1411 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1412
1413 /* Define how to find the value returned by a function.
1414 VALTYPE is the data type of the value (as a tree).
1415 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1416 otherwise, FUNC is 0. */
1417 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1418 arm_function_value (VALTYPE, FUNC);
1419
1420 /* 1 if N is a possible register number for a function value.
1421 On the ARM, only r0 and f0 can return results. */
1422 /* On a Cirrus chip, mvf0 can return results. */
1423 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1424 ((REGNO) == ARG_REGISTER (1) \
1425 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1426 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1427 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1428 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1429 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1430
1431 /* Amount of memory needed for an untyped call to save all possible return
1432 registers. */
1433 #define APPLY_RESULT_SIZE arm_apply_result_size()
1434
1435 /* How large values are returned */
1436 /* A C expression which can inhibit the returning of certain function values
1437 in registers, based on the type of value. */
1438 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1439
1440 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1441 values must be in memory. On the ARM, they need only do so if larger
1442 than a word, or if they contain elements offset from zero in the struct. */
1443 #define DEFAULT_PCC_STRUCT_RETURN 0
1444
1445 /* Flags for the call/call_value rtl operations set up by function_arg. */
1446 #define CALL_NORMAL 0x00000000 /* No special processing. */
1447 #define CALL_LONG 0x00000001 /* Always call indirect. */
1448 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1449
1450 /* These bits describe the different types of function supported
1451 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1452 normal function and an interworked function, for example. Knowing the
1453 type of a function is important for determining its prologue and
1454 epilogue sequences.
1455 Note value 7 is currently unassigned. Also note that the interrupt
1456 function types all have bit 2 set, so that they can be tested for easily.
1457 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1458 machine_function structure is initialized (to zero) func_type will
1459 default to unknown. This will force the first use of arm_current_func_type
1460 to call arm_compute_func_type. */
1461 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1462 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1463 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1464 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1465 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1466 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1467
1468 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1469
1470 /* In addition functions can have several type modifiers,
1471 outlined by these bit masks: */
1472 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1473 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1474 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1475 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1476
1477 /* Some macros to test these flags. */
1478 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1479 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1480 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1481 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1482 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1483
1484
1485 /* Structure used to hold the function stack frame layout. Offsets are
1486 relative to the stack pointer on function entry. Positive offsets are
1487 in the direction of stack growth.
1488 Only soft_frame is used in thumb mode. */
1489
1490 typedef struct arm_stack_offsets GTY(())
1491 {
1492 int saved_args; /* ARG_POINTER_REGNUM. */
1493 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1494 int saved_regs;
1495 int soft_frame; /* FRAME_POINTER_REGNUM. */
1496 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1497 int outgoing_args; /* STACK_POINTER_REGNUM. */
1498 }
1499 arm_stack_offsets;
1500
1501 /* A C structure for machine-specific, per-function data.
1502 This is added to the cfun structure. */
1503 typedef struct machine_function GTY(())
1504 {
1505 /* Additional stack adjustment in __builtin_eh_throw. */
1506 rtx eh_epilogue_sp_ofs;
1507 /* Records if LR has to be saved for far jumps. */
1508 int far_jump_used;
1509 /* Records if ARG_POINTER was ever live. */
1510 int arg_pointer_live;
1511 /* Records if the save of LR has been eliminated. */
1512 int lr_save_eliminated;
1513 /* The size of the stack frame. Only valid after reload. */
1514 arm_stack_offsets stack_offsets;
1515 /* Records the type of the current function. */
1516 unsigned long func_type;
1517 /* Record if the function has a variable argument list. */
1518 int uses_anonymous_args;
1519 /* Records if sibcalls are blocked because an argument
1520 register is needed to preserve stack alignment. */
1521 int sibcall_blocked;
1522 /* Labels for per-function Thumb call-via stubs. One per potential calling
1523 register. We can never call via LR or PC. We can call via SP if a
1524 trampoline happens to be on the top of the stack. */
1525 rtx call_via[14];
1526 }
1527 machine_function;
1528
1529 /* As in the machine_function, a global set of call-via labels, for code
1530 that is in text_section(). */
1531 extern GTY(()) rtx thumb_call_via_label[14];
1532
1533 /* A C type for declaring a variable that is used as the first argument of
1534 `FUNCTION_ARG' and other related values. For some target machines, the
1535 type `int' suffices and can hold the number of bytes of argument so far. */
1536 typedef struct
1537 {
1538 /* This is the number of registers of arguments scanned so far. */
1539 int nregs;
1540 /* This is the number of iWMMXt register arguments scanned so far. */
1541 int iwmmxt_nregs;
1542 int named_count;
1543 int nargs;
1544 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1545 int call_cookie;
1546 int can_split;
1547 } CUMULATIVE_ARGS;
1548
1549 /* Define where to put the arguments to a function.
1550 Value is zero to push the argument on the stack,
1551 or a hard register in which to store the argument.
1552
1553 MODE is the argument's machine mode.
1554 TYPE is the data type of the argument (as a tree).
1555 This is null for libcalls where that information may
1556 not be available.
1557 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1558 the preceding args and about the function being called.
1559 NAMED is nonzero if this argument is a named parameter
1560 (otherwise it is an extra parameter matching an ellipsis).
1561
1562 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1563 other arguments are passed on the stack. If (NAMED == 0) (which happens
1564 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1565 defined), say it is passed in the stack (function_prologue will
1566 indeed make it pass in the stack if necessary). */
1567 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1568 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1569
1570 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1571 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1572
1573 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1574 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1575
1576 /* For AAPCS, padding should never be below the argument. For other ABIs,
1577 * mimic the default. */
1578 #define PAD_VARARGS_DOWN \
1579 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1580
1581 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1582 for a call to a function whose data type is FNTYPE.
1583 For a library call, FNTYPE is 0.
1584 On the ARM, the offset starts at 0. */
1585 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1586 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1587
1588 /* Update the data in CUM to advance over an argument
1589 of mode MODE and data type TYPE.
1590 (TYPE is null for libcalls where that information may not be available.) */
1591 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1592 (CUM).nargs += 1; \
1593 if (arm_vector_mode_supported_p (MODE) \
1594 && (CUM).named_count > (CUM).nargs) \
1595 (CUM).iwmmxt_nregs += 1; \
1596 else \
1597 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1598
1599 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1600 argument with the specified mode and type. If it is not defined,
1601 `PARM_BOUNDARY' is used for all arguments. */
1602 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1603 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1604 ? DOUBLEWORD_ALIGNMENT \
1605 : PARM_BOUNDARY )
1606
1607 /* 1 if N is a possible register number for function argument passing.
1608 On the ARM, r0-r3 are used to pass args. */
1609 #define FUNCTION_ARG_REGNO_P(REGNO) \
1610 (IN_RANGE ((REGNO), 0, 3) \
1611 || (TARGET_IWMMXT_ABI \
1612 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1613
1614 \f
1615 /* If your target environment doesn't prefix user functions with an
1616 underscore, you may wish to re-define this to prevent any conflicts.
1617 e.g. AOF may prefix mcount with an underscore. */
1618 #ifndef ARM_MCOUNT_NAME
1619 #define ARM_MCOUNT_NAME "*mcount"
1620 #endif
1621
1622 /* Call the function profiler with a given profile label. The Acorn
1623 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1624 On the ARM the full profile code will look like:
1625 .data
1626 LP1
1627 .word 0
1628 .text
1629 mov ip, lr
1630 bl mcount
1631 .word LP1
1632
1633 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1634 will output the .text section.
1635
1636 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1637 ``prof'' doesn't seem to mind about this!
1638
1639 Note - this version of the code is designed to work in both ARM and
1640 Thumb modes. */
1641 #ifndef ARM_FUNCTION_PROFILER
1642 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1643 { \
1644 char temp[20]; \
1645 rtx sym; \
1646 \
1647 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1648 IP_REGNUM, LR_REGNUM); \
1649 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1650 fputc ('\n', STREAM); \
1651 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1652 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1653 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1654 }
1655 #endif
1656
1657 #ifdef THUMB_FUNCTION_PROFILER
1658 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1659 if (TARGET_ARM) \
1660 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1661 else \
1662 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1663 #else
1664 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1665 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1666 #endif
1667
1668 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1669 the stack pointer does not matter. The value is tested only in
1670 functions that have frame pointers.
1671 No definition is equivalent to always zero.
1672
1673 On the ARM, the function epilogue recovers the stack pointer from the
1674 frame. */
1675 #define EXIT_IGNORE_STACK 1
1676
1677 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1678
1679 /* Determine if the epilogue should be output as RTL.
1680 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1681 #define USE_RETURN_INSN(ISCOND) \
1682 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1683
1684 /* Definitions for register eliminations.
1685
1686 This is an array of structures. Each structure initializes one pair
1687 of eliminable registers. The "from" register number is given first,
1688 followed by "to". Eliminations of the same "from" register are listed
1689 in order of preference.
1690
1691 We have two registers that can be eliminated on the ARM. First, the
1692 arg pointer register can often be eliminated in favor of the stack
1693 pointer register. Secondly, the pseudo frame pointer register can always
1694 be eliminated; it is replaced with either the stack or the real frame
1695 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1696 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1697
1698 #define ELIMINABLE_REGS \
1699 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1700 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1701 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1702 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1703 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1704 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1705 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1706
1707 /* Given FROM and TO register numbers, say whether this elimination is
1708 allowed. Frame pointer elimination is automatically handled.
1709
1710 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1711 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1712 pointer, we must eliminate FRAME_POINTER_REGNUM into
1713 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1714 ARG_POINTER_REGNUM. */
1715 #define CAN_ELIMINATE(FROM, TO) \
1716 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1717 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1718 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1719 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1720 1)
1721
1722 /* Define the offset between two registers, one to be eliminated, and the
1723 other its replacement, at the start of a routine. */
1724 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1725 if (TARGET_ARM) \
1726 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1727 else \
1728 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1729
1730 /* Special case handling of the location of arguments passed on the stack. */
1731 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1732
1733 /* Initialize data used by insn expanders. This is called from insn_emit,
1734 once for every function before code is generated. */
1735 #define INIT_EXPANDERS arm_init_expanders ()
1736
1737 /* Output assembler code for a block containing the constant parts
1738 of a trampoline, leaving space for the variable parts.
1739
1740 On the ARM, (if r8 is the static chain regnum, and remembering that
1741 referencing pc adds an offset of 8) the trampoline looks like:
1742 ldr r8, [pc, #0]
1743 ldr pc, [pc]
1744 .word static chain value
1745 .word function's address
1746 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1747 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1748 { \
1749 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1750 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1751 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1752 PC_REGNUM, PC_REGNUM); \
1753 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1754 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1755 }
1756
1757 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1758 Why - because it is easier. This code will always be branched to via
1759 a BX instruction and since the compiler magically generates the address
1760 of the function the linker has no opportunity to ensure that the
1761 bottom bit is set. Thus the processor will be in ARM mode when it
1762 reaches this code. So we duplicate the ARM trampoline code and add
1763 a switch into Thumb mode as well. */
1764 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1765 { \
1766 fprintf (FILE, "\t.code 32\n"); \
1767 fprintf (FILE, ".Ltrampoline_start:\n"); \
1768 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1769 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1770 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1771 IP_REGNUM, PC_REGNUM); \
1772 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1773 IP_REGNUM, IP_REGNUM); \
1774 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1775 fprintf (FILE, "\t.word\t0\n"); \
1776 fprintf (FILE, "\t.word\t0\n"); \
1777 fprintf (FILE, "\t.code 16\n"); \
1778 }
1779
1780 #define TRAMPOLINE_TEMPLATE(FILE) \
1781 if (TARGET_ARM) \
1782 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1783 else \
1784 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1785
1786 /* Length in units of the trampoline for entering a nested function. */
1787 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1788
1789 /* Alignment required for a trampoline in bits. */
1790 #define TRAMPOLINE_ALIGNMENT 32
1791
1792
1793 /* Emit RTL insns to initialize the variable parts of a trampoline.
1794 FNADDR is an RTX for the address of the function's pure code.
1795 CXT is an RTX for the static chain value for the function. */
1796 #ifndef INITIALIZE_TRAMPOLINE
1797 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1798 { \
1799 emit_move_insn (gen_rtx_MEM (SImode, \
1800 plus_constant (TRAMP, \
1801 TARGET_ARM ? 8 : 16)), \
1802 CXT); \
1803 emit_move_insn (gen_rtx_MEM (SImode, \
1804 plus_constant (TRAMP, \
1805 TARGET_ARM ? 12 : 20)), \
1806 FNADDR); \
1807 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1808 0, VOIDmode, 2, TRAMP, Pmode, \
1809 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1810 }
1811 #endif
1812
1813 \f
1814 /* Addressing modes, and classification of registers for them. */
1815 #define HAVE_POST_INCREMENT 1
1816 #define HAVE_PRE_INCREMENT TARGET_ARM
1817 #define HAVE_POST_DECREMENT TARGET_ARM
1818 #define HAVE_PRE_DECREMENT TARGET_ARM
1819 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1820 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1821 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1822 #define HAVE_POST_MODIFY_REG TARGET_ARM
1823
1824 /* Macros to check register numbers against specific register classes. */
1825
1826 /* These assume that REGNO is a hard or pseudo reg number.
1827 They give nonzero only if REGNO is a hard reg of the suitable class
1828 or a pseudo reg currently allocated to a suitable hard reg.
1829 Since they use reg_renumber, they are safe only once reg_renumber
1830 has been allocated, which happens in local-alloc.c. */
1831 #define TEST_REGNO(R, TEST, VALUE) \
1832 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1833
1834 /* On the ARM, don't allow the pc to be used. */
1835 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1836 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1837 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1838 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1839
1840 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1841 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1842 || (GET_MODE_SIZE (MODE) >= 4 \
1843 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1844
1845 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1846 (TARGET_THUMB \
1847 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1848 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1849
1850 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1851 For Thumb, we can not use SP + reg, so reject SP. */
1852 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1853 REGNO_OK_FOR_INDEX_P (X)
1854
1855 /* For ARM code, we don't care about the mode, but for Thumb, the index
1856 must be suitable for use in a QImode load. */
1857 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1858 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1859
1860 /* Maximum number of registers that can appear in a valid memory address.
1861 Shifts in addresses can't be by a register. */
1862 #define MAX_REGS_PER_ADDRESS 2
1863
1864 /* Recognize any constant value that is a valid address. */
1865 /* XXX We can address any constant, eventually... */
1866
1867 #ifdef AOF_ASSEMBLER
1868
1869 #define CONSTANT_ADDRESS_P(X) \
1870 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1871
1872 #else
1873
1874 #define CONSTANT_ADDRESS_P(X) \
1875 (GET_CODE (X) == SYMBOL_REF \
1876 && (CONSTANT_POOL_ADDRESS_P (X) \
1877 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1878
1879 #endif /* AOF_ASSEMBLER */
1880
1881 /* Nonzero if the constant value X is a legitimate general operand.
1882 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1883
1884 On the ARM, allow any integer (invalid ones are removed later by insn
1885 patterns), nice doubles and symbol_refs which refer to the function's
1886 constant pool XXX.
1887
1888 When generating pic allow anything. */
1889 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1890
1891 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1892 ( GET_CODE (X) == CONST_INT \
1893 || GET_CODE (X) == CONST_DOUBLE \
1894 || CONSTANT_ADDRESS_P (X) \
1895 || flag_pic)
1896
1897 #define LEGITIMATE_CONSTANT_P(X) \
1898 (!arm_tls_referenced_p (X) \
1899 && (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) \
1900 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1901
1902 /* Special characters prefixed to function names
1903 in order to encode attribute like information.
1904 Note, '@' and '*' have already been taken. */
1905 #define SHORT_CALL_FLAG_CHAR '^'
1906 #define LONG_CALL_FLAG_CHAR '#'
1907
1908 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1909 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1910
1911 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1912 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1913
1914 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1915 #define SUBTARGET_NAME_ENCODING_LENGTHS
1916 #endif
1917
1918 /* This is a C fragment for the inside of a switch statement.
1919 Each case label should return the number of characters to
1920 be stripped from the start of a function's name, if that
1921 name starts with the indicated character. */
1922 #define ARM_NAME_ENCODING_LENGTHS \
1923 case SHORT_CALL_FLAG_CHAR: return 1; \
1924 case LONG_CALL_FLAG_CHAR: return 1; \
1925 case '*': return 1; \
1926 SUBTARGET_NAME_ENCODING_LENGTHS
1927
1928 /* This is how to output a reference to a user-level label named NAME.
1929 `assemble_name' uses this. */
1930 #undef ASM_OUTPUT_LABELREF
1931 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1932 arm_asm_output_labelref (FILE, NAME)
1933
1934 /* The EABI specifies that constructors should go in .init_array.
1935 Other targets use .ctors for compatibility. */
1936 #ifndef ARM_EABI_CTORS_SECTION_OP
1937 #define ARM_EABI_CTORS_SECTION_OP \
1938 "\t.section\t.init_array,\"aw\",%init_array"
1939 #endif
1940 #ifndef ARM_EABI_DTORS_SECTION_OP
1941 #define ARM_EABI_DTORS_SECTION_OP \
1942 "\t.section\t.fini_array,\"aw\",%fini_array"
1943 #endif
1944 #define ARM_CTORS_SECTION_OP \
1945 "\t.section\t.ctors,\"aw\",%progbits"
1946 #define ARM_DTORS_SECTION_OP \
1947 "\t.section\t.dtors,\"aw\",%progbits"
1948
1949 /* Define CTORS_SECTION_ASM_OP. */
1950 #undef CTORS_SECTION_ASM_OP
1951 #undef DTORS_SECTION_ASM_OP
1952 #ifndef IN_LIBGCC2
1953 # define CTORS_SECTION_ASM_OP \
1954 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1955 # define DTORS_SECTION_ASM_OP \
1956 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1957 #else /* !defined (IN_LIBGCC2) */
1958 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1959 so we cannot use the definition above. */
1960 # ifdef __ARM_EABI__
1961 /* The .ctors section is not part of the EABI, so we do not define
1962 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1963 from trying to use it. We do define it when doing normal
1964 compilation, as .init_array can be used instead of .ctors. */
1965 /* There is no need to emit begin or end markers when using
1966 init_array; the dynamic linker will compute the size of the
1967 array itself based on special symbols created by the static
1968 linker. However, we do need to arrange to set up
1969 exception-handling here. */
1970 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1971 # define CTOR_LIST_END /* empty */
1972 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1973 # define DTOR_LIST_END /* empty */
1974 # else /* !defined (__ARM_EABI__) */
1975 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1976 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1977 # endif /* !defined (__ARM_EABI__) */
1978 #endif /* !defined (IN_LIBCC2) */
1979
1980 /* True if the operating system can merge entities with vague linkage
1981 (e.g., symbols in COMDAT group) during dynamic linking. */
1982 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1983 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1984 #endif
1985
1986 /* Set the short-call flag for any function compiled in the current
1987 compilation unit. We skip this for functions with the section
1988 attribute when long-calls are in effect as this tells the compiler
1989 that the section might be placed a long way from the caller.
1990 See arm_is_longcall_p() for more information. */
1991 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1992 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1993 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1994
1995 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1996
1997 #ifdef TARGET_UNWIND_INFO
1998 #define ARM_EABI_UNWIND_TABLES \
1999 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2000 #else
2001 #define ARM_EABI_UNWIND_TABLES 0
2002 #endif
2003
2004 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2005 and check its validity for a certain class.
2006 We have two alternate definitions for each of them.
2007 The usual definition accepts all pseudo regs; the other rejects
2008 them unless they have been allocated suitable hard regs.
2009 The symbol REG_OK_STRICT causes the latter definition to be used. */
2010 #ifndef REG_OK_STRICT
2011
2012 #define ARM_REG_OK_FOR_BASE_P(X) \
2013 (REGNO (X) <= LAST_ARM_REGNUM \
2014 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2015 || REGNO (X) == FRAME_POINTER_REGNUM \
2016 || REGNO (X) == ARG_POINTER_REGNUM)
2017
2018 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2019 (REGNO (X) <= LAST_LO_REGNUM \
2020 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2021 || (GET_MODE_SIZE (MODE) >= 4 \
2022 && (REGNO (X) == STACK_POINTER_REGNUM \
2023 || (X) == hard_frame_pointer_rtx \
2024 || (X) == arg_pointer_rtx)))
2025
2026 #define REG_STRICT_P 0
2027
2028 #else /* REG_OK_STRICT */
2029
2030 #define ARM_REG_OK_FOR_BASE_P(X) \
2031 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2032
2033 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2034 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2035
2036 #define REG_STRICT_P 1
2037
2038 #endif /* REG_OK_STRICT */
2039
2040 /* Now define some helpers in terms of the above. */
2041
2042 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2043 (TARGET_THUMB \
2044 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2045 : ARM_REG_OK_FOR_BASE_P (X))
2046
2047 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2048
2049 /* For Thumb, a valid index register is anything that can be used in
2050 a byte load instruction. */
2051 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2052
2053 /* Nonzero if X is a hard reg that can be used as an index
2054 or if it is a pseudo reg. On the Thumb, the stack pointer
2055 is not suitable. */
2056 #define REG_OK_FOR_INDEX_P(X) \
2057 (TARGET_THUMB \
2058 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2059 : ARM_REG_OK_FOR_INDEX_P (X))
2060
2061 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2062 For Thumb, we can not use SP + reg, so reject SP. */
2063 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2064 REG_OK_FOR_INDEX_P (X)
2065 \f
2066 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2067 that is a valid memory address for an instruction.
2068 The MODE argument is the machine mode for the MEM expression
2069 that wants to use this address. */
2070
2071 #define ARM_BASE_REGISTER_RTX_P(X) \
2072 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2073
2074 #define ARM_INDEX_REGISTER_RTX_P(X) \
2075 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2076
2077 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2078 { \
2079 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2080 goto WIN; \
2081 }
2082
2083 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2084 { \
2085 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2086 goto WIN; \
2087 }
2088
2089 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2090 if (TARGET_ARM) \
2091 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2092 else /* if (TARGET_THUMB) */ \
2093 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2094
2095 \f
2096 /* Try machine-dependent ways of modifying an illegitimate address
2097 to be legitimate. If we find one, return the new, valid address. */
2098 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2099 do { \
2100 X = arm_legitimize_address (X, OLDX, MODE); \
2101 } while (0)
2102
2103 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2104 do { \
2105 X = thumb_legitimize_address (X, OLDX, MODE); \
2106 } while (0)
2107
2108 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2109 do { \
2110 if (TARGET_ARM) \
2111 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2112 else \
2113 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2114 \
2115 if (memory_address_p (MODE, X)) \
2116 goto WIN; \
2117 } while (0)
2118
2119 /* Go to LABEL if ADDR (a legitimate address expression)
2120 has an effect that depends on the machine mode it is used for. */
2121 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2122 { \
2123 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2124 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2125 goto LABEL; \
2126 }
2127
2128 /* Nothing helpful to do for the Thumb */
2129 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2130 if (TARGET_ARM) \
2131 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2132 \f
2133
2134 /* Specify the machine mode that this machine uses
2135 for the index in the tablejump instruction. */
2136 #define CASE_VECTOR_MODE Pmode
2137
2138 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2139 unsigned is probably best, but may break some code. */
2140 #ifndef DEFAULT_SIGNED_CHAR
2141 #define DEFAULT_SIGNED_CHAR 0
2142 #endif
2143
2144 /* Max number of bytes we can move from memory to memory
2145 in one reasonably fast instruction. */
2146 #define MOVE_MAX 4
2147
2148 #undef MOVE_RATIO
2149 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2150
2151 /* Define if operations between registers always perform the operation
2152 on the full register even if a narrower mode is specified. */
2153 #define WORD_REGISTER_OPERATIONS
2154
2155 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2156 will either zero-extend or sign-extend. The value of this macro should
2157 be the code that says which one of the two operations is implicitly
2158 done, UNKNOWN if none. */
2159 #define LOAD_EXTEND_OP(MODE) \
2160 (TARGET_THUMB ? ZERO_EXTEND : \
2161 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2162 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2163
2164 /* Nonzero if access to memory by bytes is slow and undesirable. */
2165 #define SLOW_BYTE_ACCESS 0
2166
2167 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2168
2169 /* Immediate shift counts are truncated by the output routines (or was it
2170 the assembler?). Shift counts in a register are truncated by ARM. Note
2171 that the native compiler puts too large (> 32) immediate shift counts
2172 into a register and shifts by the register, letting the ARM decide what
2173 to do instead of doing that itself. */
2174 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2175 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2176 On the arm, Y in a register is used modulo 256 for the shift. Only for
2177 rotates is modulo 32 used. */
2178 /* #define SHIFT_COUNT_TRUNCATED 1 */
2179
2180 /* All integers have the same format so truncation is easy. */
2181 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2182
2183 /* Calling from registers is a massive pain. */
2184 #define NO_FUNCTION_CSE 1
2185
2186 /* The machine modes of pointers and functions */
2187 #define Pmode SImode
2188 #define FUNCTION_MODE Pmode
2189
2190 #define ARM_FRAME_RTX(X) \
2191 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2192 || (X) == arg_pointer_rtx)
2193
2194 /* Moves to and from memory are quite expensive */
2195 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2196 (TARGET_ARM ? 10 : \
2197 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2198 * (CLASS == LO_REGS ? 1 : 2)))
2199
2200 /* Try to generate sequences that don't involve branches, we can then use
2201 conditional instructions */
2202 #define BRANCH_COST \
2203 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2204 \f
2205 /* Position Independent Code. */
2206 /* We decide which register to use based on the compilation options and
2207 the assembler in use; this is more general than the APCS restriction of
2208 using sb (r9) all the time. */
2209 extern int arm_pic_register;
2210
2211 /* The register number of the register used to address a table of static
2212 data addresses in memory. */
2213 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2214
2215 /* We can't directly access anything that contains a symbol,
2216 nor can we indirect via the constant pool. One exception is
2217 UNSPEC_TLS, which is always PIC. */
2218 #define LEGITIMATE_PIC_OPERAND_P(X) \
2219 (!(symbol_mentioned_p (X) \
2220 || label_mentioned_p (X) \
2221 || (GET_CODE (X) == SYMBOL_REF \
2222 && CONSTANT_POOL_ADDRESS_P (X) \
2223 && (symbol_mentioned_p (get_pool_constant (X)) \
2224 || label_mentioned_p (get_pool_constant (X))))) \
2225 || tls_mentioned_p (X))
2226
2227 /* We need to know when we are making a constant pool; this determines
2228 whether data needs to be in the GOT or can be referenced via a GOT
2229 offset. */
2230 extern int making_const_table;
2231 \f
2232 /* Handle pragmas for compatibility with Intel's compilers. */
2233 #define REGISTER_TARGET_PRAGMAS() do { \
2234 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2235 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2236 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2237 } while (0)
2238
2239 /* Condition code information. */
2240 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2241 return the mode to be used for the comparison. */
2242
2243 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2244
2245 #define REVERSIBLE_CC_MODE(MODE) 1
2246
2247 #define REVERSE_CONDITION(CODE,MODE) \
2248 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2249 ? reverse_condition_maybe_unordered (code) \
2250 : reverse_condition (code))
2251
2252 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2253 do \
2254 { \
2255 if (GET_CODE (OP1) == CONST_INT \
2256 && ! (const_ok_for_arm (INTVAL (OP1)) \
2257 || (const_ok_for_arm (- INTVAL (OP1))))) \
2258 { \
2259 rtx const_op = OP1; \
2260 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2261 &const_op); \
2262 OP1 = const_op; \
2263 } \
2264 } \
2265 while (0)
2266
2267 /* The arm5 clz instruction returns 32. */
2268 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2269 \f
2270 #undef ASM_APP_OFF
2271 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2272
2273 /* Output a push or a pop instruction (only used when profiling). */
2274 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2275 do \
2276 { \
2277 if (TARGET_ARM) \
2278 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2279 STACK_POINTER_REGNUM, REGNO); \
2280 else \
2281 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2282 } while (0)
2283
2284
2285 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2286 do \
2287 { \
2288 if (TARGET_ARM) \
2289 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2290 STACK_POINTER_REGNUM, REGNO); \
2291 else \
2292 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2293 } while (0)
2294
2295 /* This is how to output a label which precedes a jumptable. Since
2296 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2297 #undef ASM_OUTPUT_CASE_LABEL
2298 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2299 do \
2300 { \
2301 if (TARGET_THUMB) \
2302 ASM_OUTPUT_ALIGN (FILE, 2); \
2303 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2304 } \
2305 while (0)
2306
2307 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2308 do \
2309 { \
2310 if (TARGET_THUMB) \
2311 { \
2312 if (is_called_in_ARM_mode (DECL) \
2313 || current_function_is_thunk) \
2314 fprintf (STREAM, "\t.code 32\n") ; \
2315 else \
2316 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2317 } \
2318 if (TARGET_POKE_FUNCTION_NAME) \
2319 arm_poke_function_name (STREAM, (char *) NAME); \
2320 } \
2321 while (0)
2322
2323 /* For aliases of functions we use .thumb_set instead. */
2324 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2325 do \
2326 { \
2327 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2328 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2329 \
2330 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2331 { \
2332 fprintf (FILE, "\t.thumb_set "); \
2333 assemble_name (FILE, LABEL1); \
2334 fprintf (FILE, ","); \
2335 assemble_name (FILE, LABEL2); \
2336 fprintf (FILE, "\n"); \
2337 } \
2338 else \
2339 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2340 } \
2341 while (0)
2342
2343 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2344 /* To support -falign-* switches we need to use .p2align so
2345 that alignment directives in code sections will be padded
2346 with no-op instructions, rather than zeroes. */
2347 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2348 if ((LOG) != 0) \
2349 { \
2350 if ((MAX_SKIP) == 0) \
2351 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2352 else \
2353 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2354 (int) (LOG), (int) (MAX_SKIP)); \
2355 }
2356 #endif
2357 \f
2358 /* Only perform branch elimination (by making instructions conditional) if
2359 we're optimizing. Otherwise it's of no use anyway. */
2360 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2361 if (TARGET_ARM && optimize) \
2362 arm_final_prescan_insn (INSN); \
2363 else if (TARGET_THUMB) \
2364 thumb_final_prescan_insn (INSN)
2365
2366 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2367 (CODE == '@' || CODE == '|' \
2368 || (TARGET_ARM && (CODE == '?')) \
2369 || (TARGET_THUMB && (CODE == '_')))
2370
2371 /* Output an operand of an instruction. */
2372 #define PRINT_OPERAND(STREAM, X, CODE) \
2373 arm_print_operand (STREAM, X, CODE)
2374
2375 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2376 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2377 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2378 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2379 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2380 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2381 : 0))))
2382
2383 /* Output the address of an operand. */
2384 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2385 { \
2386 int is_minus = GET_CODE (X) == MINUS; \
2387 \
2388 if (GET_CODE (X) == REG) \
2389 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2390 else if (GET_CODE (X) == PLUS || is_minus) \
2391 { \
2392 rtx base = XEXP (X, 0); \
2393 rtx index = XEXP (X, 1); \
2394 HOST_WIDE_INT offset = 0; \
2395 if (GET_CODE (base) != REG) \
2396 { \
2397 /* Ensure that BASE is a register. */ \
2398 /* (one of them must be). */ \
2399 rtx temp = base; \
2400 base = index; \
2401 index = temp; \
2402 } \
2403 switch (GET_CODE (index)) \
2404 { \
2405 case CONST_INT: \
2406 offset = INTVAL (index); \
2407 if (is_minus) \
2408 offset = -offset; \
2409 asm_fprintf (STREAM, "[%r, #%wd]", \
2410 REGNO (base), offset); \
2411 break; \
2412 \
2413 case REG: \
2414 asm_fprintf (STREAM, "[%r, %s%r]", \
2415 REGNO (base), is_minus ? "-" : "", \
2416 REGNO (index)); \
2417 break; \
2418 \
2419 case MULT: \
2420 case ASHIFTRT: \
2421 case LSHIFTRT: \
2422 case ASHIFT: \
2423 case ROTATERT: \
2424 { \
2425 asm_fprintf (STREAM, "[%r, %s%r", \
2426 REGNO (base), is_minus ? "-" : "", \
2427 REGNO (XEXP (index, 0))); \
2428 arm_print_operand (STREAM, index, 'S'); \
2429 fputs ("]", STREAM); \
2430 break; \
2431 } \
2432 \
2433 default: \
2434 gcc_unreachable (); \
2435 } \
2436 } \
2437 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2438 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2439 { \
2440 extern enum machine_mode output_memory_reference_mode; \
2441 \
2442 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2443 \
2444 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2445 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2446 REGNO (XEXP (X, 0)), \
2447 GET_CODE (X) == PRE_DEC ? "-" : "", \
2448 GET_MODE_SIZE (output_memory_reference_mode)); \
2449 else \
2450 asm_fprintf (STREAM, "[%r], #%s%d", \
2451 REGNO (XEXP (X, 0)), \
2452 GET_CODE (X) == POST_DEC ? "-" : "", \
2453 GET_MODE_SIZE (output_memory_reference_mode)); \
2454 } \
2455 else if (GET_CODE (X) == PRE_MODIFY) \
2456 { \
2457 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2458 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2459 asm_fprintf (STREAM, "#%wd]!", \
2460 INTVAL (XEXP (XEXP (X, 1), 1))); \
2461 else \
2462 asm_fprintf (STREAM, "%r]!", \
2463 REGNO (XEXP (XEXP (X, 1), 1))); \
2464 } \
2465 else if (GET_CODE (X) == POST_MODIFY) \
2466 { \
2467 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2468 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2469 asm_fprintf (STREAM, "#%wd", \
2470 INTVAL (XEXP (XEXP (X, 1), 1))); \
2471 else \
2472 asm_fprintf (STREAM, "%r", \
2473 REGNO (XEXP (XEXP (X, 1), 1))); \
2474 } \
2475 else output_addr_const (STREAM, X); \
2476 }
2477
2478 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2479 { \
2480 if (GET_CODE (X) == REG) \
2481 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2482 else if (GET_CODE (X) == POST_INC) \
2483 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2484 else if (GET_CODE (X) == PLUS) \
2485 { \
2486 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2487 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2488 asm_fprintf (STREAM, "[%r, #%wd]", \
2489 REGNO (XEXP (X, 0)), \
2490 INTVAL (XEXP (X, 1))); \
2491 else \
2492 asm_fprintf (STREAM, "[%r, %r]", \
2493 REGNO (XEXP (X, 0)), \
2494 REGNO (XEXP (X, 1))); \
2495 } \
2496 else \
2497 output_addr_const (STREAM, X); \
2498 }
2499
2500 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2501 if (TARGET_ARM) \
2502 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2503 else \
2504 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2505
2506 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2507 if (arm_output_addr_const_extra (file, x) == FALSE) \
2508 goto fail
2509
2510 /* A C expression whose value is RTL representing the value of the return
2511 address for the frame COUNT steps up from the current frame. */
2512
2513 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2514 arm_return_addr (COUNT, FRAME)
2515
2516 /* Mask of the bits in the PC that contain the real return address
2517 when running in 26-bit mode. */
2518 #define RETURN_ADDR_MASK26 (0x03fffffc)
2519
2520 /* Pick up the return address upon entry to a procedure. Used for
2521 dwarf2 unwind information. This also enables the table driven
2522 mechanism. */
2523 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2524 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2525
2526 /* Used to mask out junk bits from the return address, such as
2527 processor state, interrupt status, condition codes and the like. */
2528 #define MASK_RETURN_ADDR \
2529 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2530 in 26 bit mode, the condition codes must be masked out of the \
2531 return address. This does not apply to ARM6 and later processors \
2532 when running in 32 bit mode. */ \
2533 ((arm_arch4 || TARGET_THUMB) \
2534 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2535 : arm_gen_return_addr_mask ())
2536
2537 \f
2538 enum arm_builtins
2539 {
2540 ARM_BUILTIN_GETWCX,
2541 ARM_BUILTIN_SETWCX,
2542
2543 ARM_BUILTIN_WZERO,
2544
2545 ARM_BUILTIN_WAVG2BR,
2546 ARM_BUILTIN_WAVG2HR,
2547 ARM_BUILTIN_WAVG2B,
2548 ARM_BUILTIN_WAVG2H,
2549
2550 ARM_BUILTIN_WACCB,
2551 ARM_BUILTIN_WACCH,
2552 ARM_BUILTIN_WACCW,
2553
2554 ARM_BUILTIN_WMACS,
2555 ARM_BUILTIN_WMACSZ,
2556 ARM_BUILTIN_WMACU,
2557 ARM_BUILTIN_WMACUZ,
2558
2559 ARM_BUILTIN_WSADB,
2560 ARM_BUILTIN_WSADBZ,
2561 ARM_BUILTIN_WSADH,
2562 ARM_BUILTIN_WSADHZ,
2563
2564 ARM_BUILTIN_WALIGN,
2565
2566 ARM_BUILTIN_TMIA,
2567 ARM_BUILTIN_TMIAPH,
2568 ARM_BUILTIN_TMIABB,
2569 ARM_BUILTIN_TMIABT,
2570 ARM_BUILTIN_TMIATB,
2571 ARM_BUILTIN_TMIATT,
2572
2573 ARM_BUILTIN_TMOVMSKB,
2574 ARM_BUILTIN_TMOVMSKH,
2575 ARM_BUILTIN_TMOVMSKW,
2576
2577 ARM_BUILTIN_TBCSTB,
2578 ARM_BUILTIN_TBCSTH,
2579 ARM_BUILTIN_TBCSTW,
2580
2581 ARM_BUILTIN_WMADDS,
2582 ARM_BUILTIN_WMADDU,
2583
2584 ARM_BUILTIN_WPACKHSS,
2585 ARM_BUILTIN_WPACKWSS,
2586 ARM_BUILTIN_WPACKDSS,
2587 ARM_BUILTIN_WPACKHUS,
2588 ARM_BUILTIN_WPACKWUS,
2589 ARM_BUILTIN_WPACKDUS,
2590
2591 ARM_BUILTIN_WADDB,
2592 ARM_BUILTIN_WADDH,
2593 ARM_BUILTIN_WADDW,
2594 ARM_BUILTIN_WADDSSB,
2595 ARM_BUILTIN_WADDSSH,
2596 ARM_BUILTIN_WADDSSW,
2597 ARM_BUILTIN_WADDUSB,
2598 ARM_BUILTIN_WADDUSH,
2599 ARM_BUILTIN_WADDUSW,
2600 ARM_BUILTIN_WSUBB,
2601 ARM_BUILTIN_WSUBH,
2602 ARM_BUILTIN_WSUBW,
2603 ARM_BUILTIN_WSUBSSB,
2604 ARM_BUILTIN_WSUBSSH,
2605 ARM_BUILTIN_WSUBSSW,
2606 ARM_BUILTIN_WSUBUSB,
2607 ARM_BUILTIN_WSUBUSH,
2608 ARM_BUILTIN_WSUBUSW,
2609
2610 ARM_BUILTIN_WAND,
2611 ARM_BUILTIN_WANDN,
2612 ARM_BUILTIN_WOR,
2613 ARM_BUILTIN_WXOR,
2614
2615 ARM_BUILTIN_WCMPEQB,
2616 ARM_BUILTIN_WCMPEQH,
2617 ARM_BUILTIN_WCMPEQW,
2618 ARM_BUILTIN_WCMPGTUB,
2619 ARM_BUILTIN_WCMPGTUH,
2620 ARM_BUILTIN_WCMPGTUW,
2621 ARM_BUILTIN_WCMPGTSB,
2622 ARM_BUILTIN_WCMPGTSH,
2623 ARM_BUILTIN_WCMPGTSW,
2624
2625 ARM_BUILTIN_TEXTRMSB,
2626 ARM_BUILTIN_TEXTRMSH,
2627 ARM_BUILTIN_TEXTRMSW,
2628 ARM_BUILTIN_TEXTRMUB,
2629 ARM_BUILTIN_TEXTRMUH,
2630 ARM_BUILTIN_TEXTRMUW,
2631 ARM_BUILTIN_TINSRB,
2632 ARM_BUILTIN_TINSRH,
2633 ARM_BUILTIN_TINSRW,
2634
2635 ARM_BUILTIN_WMAXSW,
2636 ARM_BUILTIN_WMAXSH,
2637 ARM_BUILTIN_WMAXSB,
2638 ARM_BUILTIN_WMAXUW,
2639 ARM_BUILTIN_WMAXUH,
2640 ARM_BUILTIN_WMAXUB,
2641 ARM_BUILTIN_WMINSW,
2642 ARM_BUILTIN_WMINSH,
2643 ARM_BUILTIN_WMINSB,
2644 ARM_BUILTIN_WMINUW,
2645 ARM_BUILTIN_WMINUH,
2646 ARM_BUILTIN_WMINUB,
2647
2648 ARM_BUILTIN_WMULUM,
2649 ARM_BUILTIN_WMULSM,
2650 ARM_BUILTIN_WMULUL,
2651
2652 ARM_BUILTIN_PSADBH,
2653 ARM_BUILTIN_WSHUFH,
2654
2655 ARM_BUILTIN_WSLLH,
2656 ARM_BUILTIN_WSLLW,
2657 ARM_BUILTIN_WSLLD,
2658 ARM_BUILTIN_WSRAH,
2659 ARM_BUILTIN_WSRAW,
2660 ARM_BUILTIN_WSRAD,
2661 ARM_BUILTIN_WSRLH,
2662 ARM_BUILTIN_WSRLW,
2663 ARM_BUILTIN_WSRLD,
2664 ARM_BUILTIN_WRORH,
2665 ARM_BUILTIN_WRORW,
2666 ARM_BUILTIN_WRORD,
2667 ARM_BUILTIN_WSLLHI,
2668 ARM_BUILTIN_WSLLWI,
2669 ARM_BUILTIN_WSLLDI,
2670 ARM_BUILTIN_WSRAHI,
2671 ARM_BUILTIN_WSRAWI,
2672 ARM_BUILTIN_WSRADI,
2673 ARM_BUILTIN_WSRLHI,
2674 ARM_BUILTIN_WSRLWI,
2675 ARM_BUILTIN_WSRLDI,
2676 ARM_BUILTIN_WRORHI,
2677 ARM_BUILTIN_WRORWI,
2678 ARM_BUILTIN_WRORDI,
2679
2680 ARM_BUILTIN_WUNPCKIHB,
2681 ARM_BUILTIN_WUNPCKIHH,
2682 ARM_BUILTIN_WUNPCKIHW,
2683 ARM_BUILTIN_WUNPCKILB,
2684 ARM_BUILTIN_WUNPCKILH,
2685 ARM_BUILTIN_WUNPCKILW,
2686
2687 ARM_BUILTIN_WUNPCKEHSB,
2688 ARM_BUILTIN_WUNPCKEHSH,
2689 ARM_BUILTIN_WUNPCKEHSW,
2690 ARM_BUILTIN_WUNPCKEHUB,
2691 ARM_BUILTIN_WUNPCKEHUH,
2692 ARM_BUILTIN_WUNPCKEHUW,
2693 ARM_BUILTIN_WUNPCKELSB,
2694 ARM_BUILTIN_WUNPCKELSH,
2695 ARM_BUILTIN_WUNPCKELSW,
2696 ARM_BUILTIN_WUNPCKELUB,
2697 ARM_BUILTIN_WUNPCKELUH,
2698 ARM_BUILTIN_WUNPCKELUW,
2699
2700 ARM_BUILTIN_THREAD_POINTER,
2701
2702 ARM_BUILTIN_MAX
2703 };
2704 #endif /* ! GCC_ARM_H */
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