2007-03-01 Paul Brook <paul@codesourcery.com>
[official-gcc.git] / gcc / config / arm / arm.h
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The architecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 if (TARGET_THUMB2) \
43 builtin_define ("__thumb2__"); \
44 \
45 if (TARGET_BIG_END) \
46 { \
47 builtin_define ("__ARMEB__"); \
48 if (TARGET_THUMB) \
49 builtin_define ("__THUMBEB__"); \
50 if (TARGET_LITTLE_WORDS) \
51 builtin_define ("__ARMWEL__"); \
52 } \
53 else \
54 { \
55 builtin_define ("__ARMEL__"); \
56 if (TARGET_THUMB) \
57 builtin_define ("__THUMBEL__"); \
58 } \
59 \
60 if (TARGET_SOFT_FLOAT) \
61 builtin_define ("__SOFTFP__"); \
62 \
63 if (TARGET_VFP) \
64 builtin_define ("__VFP_FP__"); \
65 \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (arm_cpp_interwork) \
69 builtin_define ("__THUMB_INTERWORK__"); \
70 \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
73 \
74 builtin_define (arm_arch_name); \
75 if (arm_arch_cirrus) \
76 builtin_define ("__MAVERICK__"); \
77 if (arm_arch_xscale) \
78 builtin_define ("__XSCALE__"); \
79 if (arm_arch_iwmmxt) \
80 builtin_define ("__IWMMXT__"); \
81 if (TARGET_AAPCS_BASED) \
82 builtin_define ("__ARM_EABI__"); \
83 } while (0)
84
85 /* The various ARM cores. */
86 enum processor_type
87 {
88 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
89 IDENT,
90 #include "arm-cores.def"
91 #undef ARM_CORE
92 /* Used to indicate that no processor has been specified. */
93 arm_none
94 };
95
96 enum target_cpus
97 {
98 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
99 TARGET_CPU_##IDENT,
100 #include "arm-cores.def"
101 #undef ARM_CORE
102 TARGET_CPU_generic
103 };
104
105 /* The processor for which instructions should be scheduled. */
106 extern enum processor_type arm_tune;
107
108 typedef enum arm_cond_code
109 {
110 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
111 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
112 }
113 arm_cc;
114
115 extern arm_cc arm_current_cc;
116
117 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
118
119 extern int arm_target_label;
120 extern int arm_ccfsm_state;
121 extern GTY(()) rtx arm_target_insn;
122 /* Define the information needed to generate branch insns. This is
123 stored from the compare operation. */
124 extern GTY(()) rtx arm_compare_op0;
125 extern GTY(()) rtx arm_compare_op1;
126 /* The label of the current constant pool. */
127 extern rtx pool_vector_label;
128 /* Set to 1 when a return insn is output, this means that the epilogue
129 is not needed. */
130 extern int return_used_this_function;
131 /* Used to produce AOF syntax assembler. */
132 extern GTY(()) rtx aof_pic_label;
133 \f
134 /* Just in case configure has failed to define anything. */
135 #ifndef TARGET_CPU_DEFAULT
136 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
137 #endif
138
139
140 #undef CPP_SPEC
141 #define CPP_SPEC "%(subtarget_cpp_spec) \
142 %{msoft-float:%{mhard-float: \
143 %e-msoft-float and -mhard_float may not be used together}} \
144 %{mbig-endian:%{mlittle-endian: \
145 %e-mbig-endian and -mlittle-endian may not be used together}}"
146
147 #ifndef CC1_SPEC
148 #define CC1_SPEC ""
149 #endif
150
151 /* This macro defines names of additional specifications to put in the specs
152 that can be used in various specifications like CC1_SPEC. Its definition
153 is an initializer with a subgrouping for each command option.
154
155 Each subgrouping contains a string constant, that defines the
156 specification name, and a string constant that used by the GCC driver
157 program.
158
159 Do not define this macro if it does not need to do anything. */
160 #define EXTRA_SPECS \
161 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
162 SUBTARGET_EXTRA_SPECS
163
164 #ifndef SUBTARGET_EXTRA_SPECS
165 #define SUBTARGET_EXTRA_SPECS
166 #endif
167
168 #ifndef SUBTARGET_CPP_SPEC
169 #define SUBTARGET_CPP_SPEC ""
170 #endif
171 \f
172 /* Run-time Target Specification. */
173 #ifndef TARGET_VERSION
174 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
175 #endif
176
177 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point instructions. */
179 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
180 /* Use hardware floating point calling convention. */
181 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
182 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
183 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
184 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
185 #define TARGET_IWMMXT (arm_arch_iwmmxt)
186 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
187 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
188 #define TARGET_ARM (! TARGET_THUMB)
189 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
190 #define TARGET_BACKTRACE (leaf_function_p () \
191 ? TARGET_TPCS_LEAF_FRAME \
192 : TARGET_TPCS_FRAME)
193 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
194 #define TARGET_AAPCS_BASED \
195 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
196
197 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
198 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
199
200 /* Only 16-bit thumb code. */
201 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
202 /* Arm or Thumb-2 32-bit code. */
203 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
204 /* 32-bit Thumb-2 code. */
205 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
206
207 /* "DSP" multiply instructions, eg. SMULxy. */
208 #define TARGET_DSP_MULTIPLY \
209 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
210 /* Integer SIMD instructions, and extend-accumulate instructions. */
211 #define TARGET_INT_SIMD \
212 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
213
214 /* We could use unified syntax for arm mode, but for now we just use it
215 for Thumb-2. */
216 #define TARGET_UNIFIED_ASM TARGET_THUMB2
217
218
219 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
220 then TARGET_AAPCS_BASED must be true -- but the converse does not
221 hold. TARGET_BPABI implies the use of the BPABI runtime library,
222 etc., in addition to just the AAPCS calling conventions. */
223 #ifndef TARGET_BPABI
224 #define TARGET_BPABI false
225 #endif
226
227 /* Support for a compile-time default CPU, et cetera. The rules are:
228 --with-arch is ignored if -march or -mcpu are specified.
229 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
230 by --with-arch.
231 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
232 by -march).
233 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
234 specified.
235 --with-fpu is ignored if -mfpu is specified.
236 --with-abi is ignored is -mabi is specified. */
237 #define OPTION_DEFAULT_SPECS \
238 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
239 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
240 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
241 {"float", \
242 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
243 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
244 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
245 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
246
247 /* Which floating point model to use. */
248 enum arm_fp_model
249 {
250 ARM_FP_MODEL_UNKNOWN,
251 /* FPA model (Hardware or software). */
252 ARM_FP_MODEL_FPA,
253 /* Cirrus Maverick floating point model. */
254 ARM_FP_MODEL_MAVERICK,
255 /* VFP floating point model. */
256 ARM_FP_MODEL_VFP
257 };
258
259 extern enum arm_fp_model arm_fp_model;
260
261 /* Which floating point hardware is available. Also update
262 fp_model_for_fpu in arm.c when adding entries to this list. */
263 enum fputype
264 {
265 /* No FP hardware. */
266 FPUTYPE_NONE,
267 /* Full FPA support. */
268 FPUTYPE_FPA,
269 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
270 FPUTYPE_FPA_EMU2,
271 /* Emulated FPA hardware, Issue 3 emulator. */
272 FPUTYPE_FPA_EMU3,
273 /* Cirrus Maverick floating point co-processor. */
274 FPUTYPE_MAVERICK,
275 /* VFP. */
276 FPUTYPE_VFP
277 };
278
279 /* Recast the floating point class to be the floating point attribute. */
280 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
281
282 /* What type of floating point to tune for */
283 extern enum fputype arm_fpu_tune;
284
285 /* What type of floating point instructions are available */
286 extern enum fputype arm_fpu_arch;
287
288 enum float_abi_type
289 {
290 ARM_FLOAT_ABI_SOFT,
291 ARM_FLOAT_ABI_SOFTFP,
292 ARM_FLOAT_ABI_HARD
293 };
294
295 extern enum float_abi_type arm_float_abi;
296
297 #ifndef TARGET_DEFAULT_FLOAT_ABI
298 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
299 #endif
300
301 /* Which ABI to use. */
302 enum arm_abi_type
303 {
304 ARM_ABI_APCS,
305 ARM_ABI_ATPCS,
306 ARM_ABI_AAPCS,
307 ARM_ABI_IWMMXT,
308 ARM_ABI_AAPCS_LINUX
309 };
310
311 extern enum arm_abi_type arm_abi;
312
313 #ifndef ARM_DEFAULT_ABI
314 #define ARM_DEFAULT_ABI ARM_ABI_APCS
315 #endif
316
317 /* Which thread pointer access sequence to use. */
318 enum arm_tp_type {
319 TP_AUTO,
320 TP_SOFT,
321 TP_CP15
322 };
323
324 extern enum arm_tp_type target_thread_pointer;
325
326 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
327 extern int arm_arch3m;
328
329 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
330 extern int arm_arch4;
331
332 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
333 extern int arm_arch4t;
334
335 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
336 extern int arm_arch5;
337
338 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
339 extern int arm_arch5e;
340
341 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
342 extern int arm_arch6;
343
344 /* Nonzero if instructions not present in the 'M' profile can be used. */
345 extern int arm_arch_notm;
346
347 /* Nonzero if this chip can benefit from load scheduling. */
348 extern int arm_ld_sched;
349
350 /* Nonzero if generating thumb code. */
351 extern int thumb_code;
352
353 /* Nonzero if this chip is a StrongARM. */
354 extern int arm_tune_strongarm;
355
356 /* Nonzero if this chip is a Cirrus variant. */
357 extern int arm_arch_cirrus;
358
359 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
360 extern int arm_arch_iwmmxt;
361
362 /* Nonzero if this chip is an XScale. */
363 extern int arm_arch_xscale;
364
365 /* Nonzero if tuning for XScale. */
366 extern int arm_tune_xscale;
367
368 /* Nonzero if tuning for stores via the write buffer. */
369 extern int arm_tune_wbuf;
370
371 /* Nonzero if we should define __THUMB_INTERWORK__ in the
372 preprocessor.
373 XXX This is a bit of a hack, it's intended to help work around
374 problems in GLD which doesn't understand that armv5t code is
375 interworking clean. */
376 extern int arm_cpp_interwork;
377
378 /* Nonzero if chip supports Thumb 2. */
379 extern int arm_arch_thumb2;
380
381 /* Nonzero if chip supports integer division instruction. */
382 extern int arm_arch_hwdiv;
383
384 #ifndef TARGET_DEFAULT
385 #define TARGET_DEFAULT (MASK_APCS_FRAME)
386 #endif
387
388 /* The frame pointer register used in gcc has nothing to do with debugging;
389 that is controlled by the APCS-FRAME option. */
390 #define CAN_DEBUG_WITHOUT_FP
391
392 #define OVERRIDE_OPTIONS arm_override_options ()
393
394 /* Nonzero if PIC code requires explicit qualifiers to generate
395 PLT and GOT relocs rather than the assembler doing so implicitly.
396 Subtargets can override these if required. */
397 #ifndef NEED_GOT_RELOC
398 #define NEED_GOT_RELOC 0
399 #endif
400 #ifndef NEED_PLT_RELOC
401 #define NEED_PLT_RELOC 0
402 #endif
403
404 /* Nonzero if we need to refer to the GOT with a PC-relative
405 offset. In other words, generate
406
407 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
408
409 rather than
410
411 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
412
413 The default is true, which matches NetBSD. Subtargets can
414 override this if required. */
415 #ifndef GOT_PCREL
416 #define GOT_PCREL 1
417 #endif
418 \f
419 /* Target machine storage Layout. */
420
421
422 /* Define this macro if it is advisable to hold scalars in registers
423 in a wider mode than that declared by the program. In such cases,
424 the value is constrained to be within the bounds of the declared
425 type, but kept valid in the wider mode. The signedness of the
426 extension may differ from that of the type. */
427
428 /* It is far faster to zero extend chars than to sign extend them */
429
430 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
431 if (GET_MODE_CLASS (MODE) == MODE_INT \
432 && GET_MODE_SIZE (MODE) < 4) \
433 { \
434 if (MODE == QImode) \
435 UNSIGNEDP = 1; \
436 else if (MODE == HImode) \
437 UNSIGNEDP = 1; \
438 (MODE) = SImode; \
439 }
440
441 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
442 if ((GET_MODE_CLASS (MODE) == MODE_INT \
443 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
444 && GET_MODE_SIZE (MODE) < 4) \
445 (MODE) = SImode; \
446
447 /* Define this if most significant bit is lowest numbered
448 in instructions that operate on numbered bit-fields. */
449 #define BITS_BIG_ENDIAN 0
450
451 /* Define this if most significant byte of a word is the lowest numbered.
452 Most ARM processors are run in little endian mode, so that is the default.
453 If you want to have it run-time selectable, change the definition in a
454 cover file to be TARGET_BIG_ENDIAN. */
455 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
456
457 /* Define this if most significant word of a multiword number is the lowest
458 numbered.
459 This is always false, even when in big-endian mode. */
460 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
461
462 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
463 on processor pre-defineds when compiling libgcc2.c. */
464 #if defined(__ARMEB__) && !defined(__ARMWEL__)
465 #define LIBGCC2_WORDS_BIG_ENDIAN 1
466 #else
467 #define LIBGCC2_WORDS_BIG_ENDIAN 0
468 #endif
469
470 /* Define this if most significant word of doubles is the lowest numbered.
471 The rules are different based on whether or not we use FPA-format,
472 VFP-format or some other floating point co-processor's format doubles. */
473 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
474
475 #define UNITS_PER_WORD 4
476
477 /* True if natural alignment is used for doubleword types. */
478 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
479
480 #define DOUBLEWORD_ALIGNMENT 64
481
482 #define PARM_BOUNDARY 32
483
484 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
485
486 #define PREFERRED_STACK_BOUNDARY \
487 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
488
489 #define FUNCTION_BOUNDARY 32
490
491 /* The lowest bit is used to indicate Thumb-mode functions, so the
492 vbit must go into the delta field of pointers to member
493 functions. */
494 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
495
496 #define EMPTY_FIELD_BOUNDARY 32
497
498 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
499
500 /* XXX Blah -- this macro is used directly by libobjc. Since it
501 supports no vector modes, cut out the complexity and fall back
502 on BIGGEST_FIELD_ALIGNMENT. */
503 #ifdef IN_TARGET_LIBS
504 #define BIGGEST_FIELD_ALIGNMENT 64
505 #endif
506
507 /* Make strings word-aligned so strcpy from constants will be faster. */
508 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
509
510 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
511 ((TREE_CODE (EXP) == STRING_CST \
512 && !optimize_size \
513 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
514 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
515
516 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
517 value set in previous versions of this toolchain was 8, which produces more
518 compact structures. The command line option -mstructure_size_boundary=<n>
519 can be used to change this value. For compatibility with the ARM SDK
520 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
521 0020D) page 2-20 says "Structures are aligned on word boundaries".
522 The AAPCS specifies a value of 8. */
523 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
524 extern int arm_structure_size_boundary;
525
526 /* This is the value used to initialize arm_structure_size_boundary. If a
527 particular arm target wants to change the default value it should change
528 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
529 for an example of this. */
530 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
531 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
532 #endif
533
534 /* Nonzero if move instructions will actually fail to work
535 when given unaligned data. */
536 #define STRICT_ALIGNMENT 1
537
538 /* wchar_t is unsigned under the AAPCS. */
539 #ifndef WCHAR_TYPE
540 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
541
542 #define WCHAR_TYPE_SIZE BITS_PER_WORD
543 #endif
544
545 #ifndef SIZE_TYPE
546 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
547 #endif
548
549 #ifndef PTRDIFF_TYPE
550 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
551 #endif
552
553 /* AAPCS requires that structure alignment is affected by bitfields. */
554 #ifndef PCC_BITFIELD_TYPE_MATTERS
555 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
556 #endif
557
558 \f
559 /* Standard register usage. */
560
561 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
562 (S - saved over call).
563
564 r0 * argument word/integer result
565 r1-r3 argument word
566
567 r4-r8 S register variable
568 r9 S (rfp) register variable (real frame pointer)
569
570 r10 F S (sl) stack limit (used by -mapcs-stack-check)
571 r11 F S (fp) argument pointer
572 r12 (ip) temp workspace
573 r13 F S (sp) lower end of current stack frame
574 r14 (lr) link address/workspace
575 r15 F (pc) program counter
576
577 f0 floating point result
578 f1-f3 floating point scratch
579
580 f4-f7 S floating point variable
581
582 cc This is NOT a real register, but is used internally
583 to represent things that use or set the condition
584 codes.
585 sfp This isn't either. It is used during rtl generation
586 since the offset between the frame pointer and the
587 auto's isn't known until after register allocation.
588 afp Nor this, we only need this because of non-local
589 goto. Without it fp appears to be used and the
590 elimination code won't get rid of sfp. It tracks
591 fp exactly at all times.
592
593 *: See CONDITIONAL_REGISTER_USAGE */
594
595 /*
596 mvf0 Cirrus floating point result
597 mvf1-mvf3 Cirrus floating point scratch
598 mvf4-mvf15 S Cirrus floating point variable. */
599
600 /* s0-s15 VFP scratch (aka d0-d7).
601 s16-s31 S VFP variable (aka d8-d15).
602 vfpcc Not a real register. Represents the VFP condition
603 code flags. */
604
605 /* The stack backtrace structure is as follows:
606 fp points to here: | save code pointer | [fp]
607 | return link value | [fp, #-4]
608 | return sp value | [fp, #-8]
609 | return fp value | [fp, #-12]
610 [| saved r10 value |]
611 [| saved r9 value |]
612 [| saved r8 value |]
613 [| saved r7 value |]
614 [| saved r6 value |]
615 [| saved r5 value |]
616 [| saved r4 value |]
617 [| saved r3 value |]
618 [| saved r2 value |]
619 [| saved r1 value |]
620 [| saved r0 value |]
621 [| saved f7 value |] three words
622 [| saved f6 value |] three words
623 [| saved f5 value |] three words
624 [| saved f4 value |] three words
625 r0-r3 are not normally saved in a C function. */
626
627 /* 1 for registers that have pervasive standard uses
628 and are not available for the register allocator. */
629 #define FIXED_REGISTERS \
630 { \
631 0,0,0,0,0,0,0,0, \
632 0,0,0,0,0,1,0,1, \
633 0,0,0,0,0,0,0,0, \
634 1,1,1, \
635 1,1,1,1,1,1,1,1, \
636 1,1,1,1,1,1,1,1, \
637 1,1,1,1,1,1,1,1, \
638 1,1,1,1,1,1,1,1, \
639 1,1,1,1, \
640 1,1,1,1,1,1,1,1, \
641 1,1,1,1,1,1,1,1, \
642 1,1,1,1,1,1,1,1, \
643 1,1,1,1,1,1,1,1, \
644 1 \
645 }
646
647 /* 1 for registers not available across function calls.
648 These must include the FIXED_REGISTERS and also any
649 registers that can be used without being saved.
650 The latter must include the registers where values are returned
651 and the register where structure-value addresses are passed.
652 Aside from that, you can include as many other registers as you like.
653 The CC is not preserved over function calls on the ARM 6, so it is
654 easier to assume this for all. SFP is preserved, since FP is. */
655 #define CALL_USED_REGISTERS \
656 { \
657 1,1,1,1,0,0,0,0, \
658 0,0,0,0,1,1,1,1, \
659 1,1,1,1,0,0,0,0, \
660 1,1,1, \
661 1,1,1,1,1,1,1,1, \
662 1,1,1,1,1,1,1,1, \
663 1,1,1,1,1,1,1,1, \
664 1,1,1,1,1,1,1,1, \
665 1,1,1,1, \
666 1,1,1,1,1,1,1,1, \
667 1,1,1,1,1,1,1,1, \
668 1,1,1,1,1,1,1,1, \
669 1,1,1,1,1,1,1,1, \
670 1 \
671 }
672
673 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
674 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
675 #endif
676
677 #define CONDITIONAL_REGISTER_USAGE \
678 { \
679 int regno; \
680 \
681 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
682 { \
683 for (regno = FIRST_FPA_REGNUM; \
684 regno <= LAST_FPA_REGNUM; ++regno) \
685 fixed_regs[regno] = call_used_regs[regno] = 1; \
686 } \
687 \
688 if (TARGET_THUMB && optimize_size) \
689 { \
690 /* When optimizing for size, it's better not to use \
691 the HI regs, because of the overhead of stacking \
692 them. */ \
693 /* ??? Is this still true for thumb2? */ \
694 for (regno = FIRST_HI_REGNUM; \
695 regno <= LAST_HI_REGNUM; ++regno) \
696 fixed_regs[regno] = call_used_regs[regno] = 1; \
697 } \
698 \
699 /* The link register can be clobbered by any branch insn, \
700 but we have no way to track that at present, so mark \
701 it as unavailable. */ \
702 if (TARGET_THUMB1) \
703 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
704 \
705 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
706 { \
707 if (TARGET_MAVERICK) \
708 { \
709 for (regno = FIRST_FPA_REGNUM; \
710 regno <= LAST_FPA_REGNUM; ++ regno) \
711 fixed_regs[regno] = call_used_regs[regno] = 1; \
712 for (regno = FIRST_CIRRUS_FP_REGNUM; \
713 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
714 { \
715 fixed_regs[regno] = 0; \
716 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
717 } \
718 } \
719 if (TARGET_VFP) \
720 { \
721 for (regno = FIRST_VFP_REGNUM; \
722 regno <= LAST_VFP_REGNUM; ++ regno) \
723 { \
724 fixed_regs[regno] = 0; \
725 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
726 } \
727 } \
728 } \
729 \
730 if (TARGET_REALLY_IWMMXT) \
731 { \
732 regno = FIRST_IWMMXT_GR_REGNUM; \
733 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
734 and wCG1 as call-preserved registers. The 2002/11/21 \
735 revision changed this so that all wCG registers are \
736 scratch registers. */ \
737 for (regno = FIRST_IWMMXT_GR_REGNUM; \
738 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
739 fixed_regs[regno] = 0; \
740 /* The XScale ABI has wR0 - wR9 as scratch registers, \
741 the rest as call-preserved registers. */ \
742 for (regno = FIRST_IWMMXT_REGNUM; \
743 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
744 { \
745 fixed_regs[regno] = 0; \
746 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
747 } \
748 } \
749 \
750 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
751 { \
752 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
753 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
754 } \
755 else if (TARGET_APCS_STACK) \
756 { \
757 fixed_regs[10] = 1; \
758 call_used_regs[10] = 1; \
759 } \
760 /* -mcaller-super-interworking reserves r11 for calls to \
761 _interwork_r11_call_via_rN(). Making the register global \
762 is an easy way of ensuring that it remains valid for all \
763 calls. */ \
764 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
765 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
766 { \
767 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
768 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
769 if (TARGET_CALLER_INTERWORKING) \
770 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
771 } \
772 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
773 }
774
775 /* These are a couple of extensions to the formats accepted
776 by asm_fprintf:
777 %@ prints out ASM_COMMENT_START
778 %r prints out REGISTER_PREFIX reg_names[arg] */
779 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
780 case '@': \
781 fputs (ASM_COMMENT_START, FILE); \
782 break; \
783 \
784 case 'r': \
785 fputs (REGISTER_PREFIX, FILE); \
786 fputs (reg_names [va_arg (ARGS, int)], FILE); \
787 break;
788
789 /* Round X up to the nearest word. */
790 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
791
792 /* Convert fron bytes to ints. */
793 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
794
795 /* The number of (integer) registers required to hold a quantity of type MODE.
796 Also used for VFP registers. */
797 #define ARM_NUM_REGS(MODE) \
798 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
799
800 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
801 #define ARM_NUM_REGS2(MODE, TYPE) \
802 ARM_NUM_INTS ((MODE) == BLKmode ? \
803 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
804
805 /* The number of (integer) argument register available. */
806 #define NUM_ARG_REGS 4
807
808 /* Return the register number of the N'th (integer) argument. */
809 #define ARG_REGISTER(N) (N - 1)
810
811 /* Specify the registers used for certain standard purposes.
812 The values of these macros are register numbers. */
813
814 /* The number of the last argument register. */
815 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
816
817 /* The numbers of the Thumb register ranges. */
818 #define FIRST_LO_REGNUM 0
819 #define LAST_LO_REGNUM 7
820 #define FIRST_HI_REGNUM 8
821 #define LAST_HI_REGNUM 11
822
823 #ifndef TARGET_UNWIND_INFO
824 /* We use sjlj exceptions for backwards compatibility. */
825 #define MUST_USE_SJLJ_EXCEPTIONS 1
826 #endif
827
828 /* We can generate DWARF2 Unwind info, even though we don't use it. */
829 #define DWARF2_UNWIND_INFO 1
830
831 /* Use r0 and r1 to pass exception handling information. */
832 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
833
834 /* The register that holds the return address in exception handlers. */
835 #define ARM_EH_STACKADJ_REGNUM 2
836 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
837
838 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
839 as an invisible last argument (possible since varargs don't exist in
840 Pascal), so the following is not true. */
841 #define STATIC_CHAIN_REGNUM 12
842
843 /* Define this to be where the real frame pointer is if it is not possible to
844 work out the offset between the frame pointer and the automatic variables
845 until after register allocation has taken place. FRAME_POINTER_REGNUM
846 should point to a special register that we will make sure is eliminated.
847
848 For the Thumb we have another problem. The TPCS defines the frame pointer
849 as r11, and GCC believes that it is always possible to use the frame pointer
850 as base register for addressing purposes. (See comments in
851 find_reloads_address()). But - the Thumb does not allow high registers,
852 including r11, to be used as base address registers. Hence our problem.
853
854 The solution used here, and in the old thumb port is to use r7 instead of
855 r11 as the hard frame pointer and to have special code to generate
856 backtrace structures on the stack (if required to do so via a command line
857 option) using r11. This is the only 'user visible' use of r11 as a frame
858 pointer. */
859 #define ARM_HARD_FRAME_POINTER_REGNUM 11
860 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
861
862 #define HARD_FRAME_POINTER_REGNUM \
863 (TARGET_ARM \
864 ? ARM_HARD_FRAME_POINTER_REGNUM \
865 : THUMB_HARD_FRAME_POINTER_REGNUM)
866
867 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
868
869 /* Register to use for pushing function arguments. */
870 #define STACK_POINTER_REGNUM SP_REGNUM
871
872 /* ARM floating pointer registers. */
873 #define FIRST_FPA_REGNUM 16
874 #define LAST_FPA_REGNUM 23
875 #define IS_FPA_REGNUM(REGNUM) \
876 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
877
878 #define FIRST_IWMMXT_GR_REGNUM 43
879 #define LAST_IWMMXT_GR_REGNUM 46
880 #define FIRST_IWMMXT_REGNUM 47
881 #define LAST_IWMMXT_REGNUM 62
882 #define IS_IWMMXT_REGNUM(REGNUM) \
883 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
884 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
885 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
886
887 /* Base register for access to local variables of the function. */
888 #define FRAME_POINTER_REGNUM 25
889
890 /* Base register for access to arguments of the function. */
891 #define ARG_POINTER_REGNUM 26
892
893 #define FIRST_CIRRUS_FP_REGNUM 27
894 #define LAST_CIRRUS_FP_REGNUM 42
895 #define IS_CIRRUS_REGNUM(REGNUM) \
896 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
897
898 #define FIRST_VFP_REGNUM 63
899 #define LAST_VFP_REGNUM 94
900 #define IS_VFP_REGNUM(REGNUM) \
901 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
902
903 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
904 /* + 16 Cirrus registers take us up to 43. */
905 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
906 /* VFP adds 32 + 1 more. */
907 #define FIRST_PSEUDO_REGISTER 96
908
909 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
910
911 /* Value should be nonzero if functions must have frame pointers.
912 Zero means the frame pointer need not be set up (and parms may be accessed
913 via the stack pointer) in functions that seem suitable.
914 If we have to have a frame pointer we might as well make use of it.
915 APCS says that the frame pointer does not need to be pushed in leaf
916 functions, or simple tail call functions. */
917
918 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
919 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
920 #endif
921
922 #define FRAME_POINTER_REQUIRED \
923 (current_function_has_nonlocal_label \
924 || SUBTARGET_FRAME_POINTER_REQUIRED \
925 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
926
927 /* Return number of consecutive hard regs needed starting at reg REGNO
928 to hold something of mode MODE.
929 This is ordinarily the length in words of a value of mode MODE
930 but can be less for certain modes in special long registers.
931
932 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
933 mode. */
934 #define HARD_REGNO_NREGS(REGNO, MODE) \
935 ((TARGET_32BIT \
936 && REGNO >= FIRST_FPA_REGNUM \
937 && REGNO != FRAME_POINTER_REGNUM \
938 && REGNO != ARG_POINTER_REGNUM) \
939 && !IS_VFP_REGNUM (REGNO) \
940 ? 1 : ARM_NUM_REGS (MODE))
941
942 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
943 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
944 arm_hard_regno_mode_ok ((REGNO), (MODE))
945
946 /* Value is 1 if it is a good idea to tie two pseudo registers
947 when one has mode MODE1 and one has mode MODE2.
948 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
949 for any hard reg, then this must be 0 for correct output. */
950 #define MODES_TIEABLE_P(MODE1, MODE2) \
951 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
952
953 #define VALID_IWMMXT_REG_MODE(MODE) \
954 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
955
956 /* The order in which register should be allocated. It is good to use ip
957 since no saving is required (though calls clobber it) and it never contains
958 function parameters. It is quite good to use lr since other calls may
959 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
960 least likely to contain a function parameter; in addition results are
961 returned in r0. */
962
963 #define REG_ALLOC_ORDER \
964 { \
965 3, 2, 1, 0, 12, 14, 4, 5, \
966 6, 7, 8, 10, 9, 11, 13, 15, \
967 16, 17, 18, 19, 20, 21, 22, 23, \
968 27, 28, 29, 30, 31, 32, 33, 34, \
969 35, 36, 37, 38, 39, 40, 41, 42, \
970 43, 44, 45, 46, 47, 48, 49, 50, \
971 51, 52, 53, 54, 55, 56, 57, 58, \
972 59, 60, 61, 62, \
973 24, 25, 26, \
974 78, 77, 76, 75, 74, 73, 72, 71, \
975 70, 69, 68, 67, 66, 65, 64, 63, \
976 79, 80, 81, 82, 83, 84, 85, 86, \
977 87, 88, 89, 90, 91, 92, 93, 94, \
978 95 \
979 }
980
981 /* Interrupt functions can only use registers that have already been
982 saved by the prologue, even if they would normally be
983 call-clobbered. */
984 #define HARD_REGNO_RENAME_OK(SRC, DST) \
985 (! IS_INTERRUPT (cfun->machine->func_type) || \
986 regs_ever_live[DST])
987 \f
988 /* Register and constant classes. */
989
990 /* Register classes: used to be simple, just all ARM regs or all FPA regs
991 Now that the Thumb is involved it has become more complicated. */
992 enum reg_class
993 {
994 NO_REGS,
995 FPA_REGS,
996 CIRRUS_REGS,
997 VFP_REGS,
998 IWMMXT_GR_REGS,
999 IWMMXT_REGS,
1000 LO_REGS,
1001 STACK_REG,
1002 BASE_REGS,
1003 HI_REGS,
1004 CC_REG,
1005 VFPCC_REG,
1006 GENERAL_REGS,
1007 ALL_REGS,
1008 LIM_REG_CLASSES
1009 };
1010
1011 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1012
1013 /* Give names of register classes as strings for dump file. */
1014 #define REG_CLASS_NAMES \
1015 { \
1016 "NO_REGS", \
1017 "FPA_REGS", \
1018 "CIRRUS_REGS", \
1019 "VFP_REGS", \
1020 "IWMMXT_GR_REGS", \
1021 "IWMMXT_REGS", \
1022 "LO_REGS", \
1023 "STACK_REG", \
1024 "BASE_REGS", \
1025 "HI_REGS", \
1026 "CC_REG", \
1027 "VFPCC_REG", \
1028 "GENERAL_REGS", \
1029 "ALL_REGS", \
1030 }
1031
1032 /* Define which registers fit in which classes.
1033 This is an initializer for a vector of HARD_REG_SET
1034 of length N_REG_CLASSES. */
1035 #define REG_CLASS_CONTENTS \
1036 { \
1037 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1038 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1039 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1040 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1041 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1042 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1043 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1044 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1045 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1046 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1047 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1048 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1049 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1050 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1051 }
1052
1053 /* The same information, inverted:
1054 Return the class number of the smallest class containing
1055 reg number REGNO. This could be a conditional expression
1056 or could index an array. */
1057 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1058
1059 /* FPA registers can't do subreg as all values are reformatted to internal
1060 precision. VFP registers may only be accessed in the mode they
1061 were set. */
1062 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1063 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1064 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1065 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1066 : 0)
1067
1068 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1069 using r0-r4 for function arguments, r7 for the stack frame and don't
1070 have enough left over to do doubleword arithmetic. */
1071 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1072 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1073 || (CLASS) == CC_REG)
1074
1075 /* The class value for index registers, and the one for base regs. */
1076 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1077 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1078
1079 /* For the Thumb the high registers cannot be used as base registers
1080 when addressing quantities in QI or HI mode; if we don't know the
1081 mode, then we must be conservative. */
1082 #define MODE_BASE_REG_CLASS(MODE) \
1083 (TARGET_32BIT ? GENERAL_REGS : \
1084 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1085
1086 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1087 instead of BASE_REGS. */
1088 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1089
1090 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1091 registers explicitly used in the rtl to be used as spill registers
1092 but prevents the compiler from extending the lifetime of these
1093 registers. */
1094 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1095
1096 /* Given an rtx X being reloaded into a reg required to be
1097 in class CLASS, return the class of reg to actually use.
1098 In general this is just CLASS, but for the Thumb core registers and
1099 immediate constants we prefer a LO_REGS class or a subset. */
1100 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1101 (TARGET_ARM ? (CLASS) : \
1102 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1103 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
1104
1105 /* Must leave BASE_REGS reloads alone */
1106 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1107 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1108 ? ((true_regnum (X) == -1 ? LO_REGS \
1109 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1110 : NO_REGS)) \
1111 : NO_REGS)
1112
1113 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1114 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1115 ? ((true_regnum (X) == -1 ? LO_REGS \
1116 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1117 : NO_REGS)) \
1118 : NO_REGS)
1119
1120 /* Return the register class of a scratch register needed to copy IN into
1121 or out of a register in CLASS in MODE. If it can be done directly,
1122 NO_REGS is returned. */
1123 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1124 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1125 ((TARGET_VFP && TARGET_HARD_FLOAT \
1126 && (CLASS) == VFP_REGS) \
1127 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1128 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1129 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1130 : TARGET_32BIT \
1131 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1132 ? GENERAL_REGS : NO_REGS) \
1133 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1134
1135 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1136 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1137 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1138 ((TARGET_VFP && TARGET_HARD_FLOAT \
1139 && (CLASS) == VFP_REGS) \
1140 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1141 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1142 coproc_secondary_reload_class (MODE, X, TRUE) : \
1143 /* Cannot load constants into Cirrus registers. */ \
1144 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1145 && (CLASS) == CIRRUS_REGS \
1146 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1147 ? GENERAL_REGS : \
1148 (TARGET_32BIT ? \
1149 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1150 && CONSTANT_P (X)) \
1151 ? GENERAL_REGS : \
1152 (((MODE) == HImode && ! arm_arch4 \
1153 && (GET_CODE (X) == MEM \
1154 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1155 && true_regnum (X) == -1))) \
1156 ? GENERAL_REGS : NO_REGS) \
1157 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1158
1159 /* Try a machine-dependent way of reloading an illegitimate address
1160 operand. If we find one, push the reload and jump to WIN. This
1161 macro is used in only one place: `find_reloads_address' in reload.c.
1162
1163 For the ARM, we wish to handle large displacements off a base
1164 register by splitting the addend across a MOV and the mem insn.
1165 This can cut the number of reloads needed. */
1166 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1167 do \
1168 { \
1169 if (GET_CODE (X) == PLUS \
1170 && GET_CODE (XEXP (X, 0)) == REG \
1171 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1172 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1173 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1174 { \
1175 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1176 HOST_WIDE_INT low, high; \
1177 \
1178 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1179 low = ((val & 0xf) ^ 0x8) - 0x8; \
1180 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1181 /* Need to be careful, -256 is not a valid offset. */ \
1182 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1183 else if (MODE == SImode \
1184 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1185 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1186 /* Need to be careful, -4096 is not a valid offset. */ \
1187 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1188 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1189 /* Need to be careful, -256 is not a valid offset. */ \
1190 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1191 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1192 && TARGET_HARD_FLOAT && TARGET_FPA) \
1193 /* Need to be careful, -1024 is not a valid offset. */ \
1194 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1195 else \
1196 break; \
1197 \
1198 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1199 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1200 - (unsigned HOST_WIDE_INT) 0x80000000); \
1201 /* Check for overflow or zero */ \
1202 if (low == 0 || high == 0 || (high + low != val)) \
1203 break; \
1204 \
1205 /* Reload the high part into a base reg; leave the low part \
1206 in the mem. */ \
1207 X = gen_rtx_PLUS (GET_MODE (X), \
1208 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1209 GEN_INT (high)), \
1210 GEN_INT (low)); \
1211 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1212 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1213 VOIDmode, 0, 0, OPNUM, TYPE); \
1214 goto WIN; \
1215 } \
1216 } \
1217 while (0)
1218
1219 /* XXX If an HImode FP+large_offset address is converted to an HImode
1220 SP+large_offset address, then reload won't know how to fix it. It sees
1221 only that SP isn't valid for HImode, and so reloads the SP into an index
1222 register, but the resulting address is still invalid because the offset
1223 is too big. We fix it here instead by reloading the entire address. */
1224 /* We could probably achieve better results by defining PROMOTE_MODE to help
1225 cope with the variances between the Thumb's signed and unsigned byte and
1226 halfword load instructions. */
1227 /* ??? This should be safe for thumb2, but we may be able to do better. */
1228 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1229 do { \
1230 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1231 if (new_x) \
1232 { \
1233 X = new_x; \
1234 goto WIN; \
1235 } \
1236 } while (0)
1237
1238 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1239 if (TARGET_ARM) \
1240 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1241 else \
1242 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1243
1244 /* Return the maximum number of consecutive registers
1245 needed to represent mode MODE in a register of class CLASS.
1246 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1247 #define CLASS_MAX_NREGS(CLASS, MODE) \
1248 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1249
1250 /* If defined, gives a class of registers that cannot be used as the
1251 operand of a SUBREG that changes the mode of the object illegally. */
1252
1253 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1254 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1255 (TARGET_32BIT ? \
1256 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1257 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1258 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1259 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1260 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1261 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1262 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1263 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1264 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1265 2) \
1266 : \
1267 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1268 \f
1269 /* Stack layout; function entry, exit and calling. */
1270
1271 /* Define this if pushing a word on the stack
1272 makes the stack pointer a smaller address. */
1273 #define STACK_GROWS_DOWNWARD 1
1274
1275 /* Define this to nonzero if the nominal address of the stack frame
1276 is at the high-address end of the local variables;
1277 that is, each additional local variable allocated
1278 goes at a more negative offset in the frame. */
1279 #define FRAME_GROWS_DOWNWARD 1
1280
1281 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1282 When present, it is one word in size, and sits at the top of the frame,
1283 between the soft frame pointer and either r7 or r11.
1284
1285 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1286 and only then if some outgoing arguments are passed on the stack. It would
1287 be tempting to also check whether the stack arguments are passed by indirect
1288 calls, but there seems to be no reason in principle why a post-reload pass
1289 couldn't convert a direct call into an indirect one. */
1290 #define CALLER_INTERWORKING_SLOT_SIZE \
1291 (TARGET_CALLER_INTERWORKING \
1292 && current_function_outgoing_args_size != 0 \
1293 ? UNITS_PER_WORD : 0)
1294
1295 /* Offset within stack frame to start allocating local variables at.
1296 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1297 first local allocated. Otherwise, it is the offset to the BEGINNING
1298 of the first local allocated. */
1299 #define STARTING_FRAME_OFFSET 0
1300
1301 /* If we generate an insn to push BYTES bytes,
1302 this says how many the stack pointer really advances by. */
1303 /* The push insns do not do this rounding implicitly.
1304 So don't define this. */
1305 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1306
1307 /* Define this if the maximum size of all the outgoing args is to be
1308 accumulated and pushed during the prologue. The amount can be
1309 found in the variable current_function_outgoing_args_size. */
1310 #define ACCUMULATE_OUTGOING_ARGS 1
1311
1312 /* Offset of first parameter from the argument pointer register value. */
1313 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1314
1315 /* Value is the number of byte of arguments automatically
1316 popped when returning from a subroutine call.
1317 FUNDECL is the declaration node of the function (as a tree),
1318 FUNTYPE is the data type of the function (as a tree),
1319 or for a library call it is an identifier node for the subroutine name.
1320 SIZE is the number of bytes of arguments passed on the stack.
1321
1322 On the ARM, the caller does not pop any of its arguments that were passed
1323 on the stack. */
1324 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1325
1326 /* Define how to find the value returned by a library function
1327 assuming the value has mode MODE. */
1328 #define LIBCALL_VALUE(MODE) \
1329 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1330 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1331 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1332 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1333 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1334 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1335 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1336 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1337 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1338
1339 /* Define how to find the value returned by a function.
1340 VALTYPE is the data type of the value (as a tree).
1341 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1342 otherwise, FUNC is 0. */
1343 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1344 arm_function_value (VALTYPE, FUNC);
1345
1346 /* 1 if N is a possible register number for a function value.
1347 On the ARM, only r0 and f0 can return results. */
1348 /* On a Cirrus chip, mvf0 can return results. */
1349 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1350 ((REGNO) == ARG_REGISTER (1) \
1351 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1352 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1353 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1354 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1355 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1356
1357 /* Amount of memory needed for an untyped call to save all possible return
1358 registers. */
1359 #define APPLY_RESULT_SIZE arm_apply_result_size()
1360
1361 /* How large values are returned */
1362 /* A C expression which can inhibit the returning of certain function values
1363 in registers, based on the type of value. */
1364 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1365
1366 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1367 values must be in memory. On the ARM, they need only do so if larger
1368 than a word, or if they contain elements offset from zero in the struct. */
1369 #define DEFAULT_PCC_STRUCT_RETURN 0
1370
1371 /* Flags for the call/call_value rtl operations set up by function_arg. */
1372 #define CALL_NORMAL 0x00000000 /* No special processing. */
1373 #define CALL_LONG 0x00000001 /* Always call indirect. */
1374 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1375
1376 /* These bits describe the different types of function supported
1377 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1378 normal function and an interworked function, for example. Knowing the
1379 type of a function is important for determining its prologue and
1380 epilogue sequences.
1381 Note value 7 is currently unassigned. Also note that the interrupt
1382 function types all have bit 2 set, so that they can be tested for easily.
1383 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1384 machine_function structure is initialized (to zero) func_type will
1385 default to unknown. This will force the first use of arm_current_func_type
1386 to call arm_compute_func_type. */
1387 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1388 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1389 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1390 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1391 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1392 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1393
1394 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1395
1396 /* In addition functions can have several type modifiers,
1397 outlined by these bit masks: */
1398 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1399 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1400 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1401 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1402 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1403
1404 /* Some macros to test these flags. */
1405 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1406 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1407 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1408 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1409 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1410 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1411
1412
1413 /* Structure used to hold the function stack frame layout. Offsets are
1414 relative to the stack pointer on function entry. Positive offsets are
1415 in the direction of stack growth.
1416 Only soft_frame is used in thumb mode. */
1417
1418 typedef struct arm_stack_offsets GTY(())
1419 {
1420 int saved_args; /* ARG_POINTER_REGNUM. */
1421 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1422 int saved_regs;
1423 int soft_frame; /* FRAME_POINTER_REGNUM. */
1424 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1425 int outgoing_args; /* STACK_POINTER_REGNUM. */
1426 }
1427 arm_stack_offsets;
1428
1429 /* A C structure for machine-specific, per-function data.
1430 This is added to the cfun structure. */
1431 typedef struct machine_function GTY(())
1432 {
1433 /* Additional stack adjustment in __builtin_eh_throw. */
1434 rtx eh_epilogue_sp_ofs;
1435 /* Records if LR has to be saved for far jumps. */
1436 int far_jump_used;
1437 /* Records if ARG_POINTER was ever live. */
1438 int arg_pointer_live;
1439 /* Records if the save of LR has been eliminated. */
1440 int lr_save_eliminated;
1441 /* The size of the stack frame. Only valid after reload. */
1442 arm_stack_offsets stack_offsets;
1443 /* Records the type of the current function. */
1444 unsigned long func_type;
1445 /* Record if the function has a variable argument list. */
1446 int uses_anonymous_args;
1447 /* Records if sibcalls are blocked because an argument
1448 register is needed to preserve stack alignment. */
1449 int sibcall_blocked;
1450 /* The PIC register for this function. This might be a pseudo. */
1451 rtx pic_reg;
1452 /* Labels for per-function Thumb call-via stubs. One per potential calling
1453 register. We can never call via LR or PC. We can call via SP if a
1454 trampoline happens to be on the top of the stack. */
1455 rtx call_via[14];
1456 }
1457 machine_function;
1458
1459 /* As in the machine_function, a global set of call-via labels, for code
1460 that is in text_section. */
1461 extern GTY(()) rtx thumb_call_via_label[14];
1462
1463 /* A C type for declaring a variable that is used as the first argument of
1464 `FUNCTION_ARG' and other related values. For some target machines, the
1465 type `int' suffices and can hold the number of bytes of argument so far. */
1466 typedef struct
1467 {
1468 /* This is the number of registers of arguments scanned so far. */
1469 int nregs;
1470 /* This is the number of iWMMXt register arguments scanned so far. */
1471 int iwmmxt_nregs;
1472 int named_count;
1473 int nargs;
1474 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1475 int call_cookie;
1476 int can_split;
1477 } CUMULATIVE_ARGS;
1478
1479 /* Define where to put the arguments to a function.
1480 Value is zero to push the argument on the stack,
1481 or a hard register in which to store the argument.
1482
1483 MODE is the argument's machine mode.
1484 TYPE is the data type of the argument (as a tree).
1485 This is null for libcalls where that information may
1486 not be available.
1487 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1488 the preceding args and about the function being called.
1489 NAMED is nonzero if this argument is a named parameter
1490 (otherwise it is an extra parameter matching an ellipsis).
1491
1492 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1493 other arguments are passed on the stack. If (NAMED == 0) (which happens
1494 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1495 defined), say it is passed in the stack (function_prologue will
1496 indeed make it pass in the stack if necessary). */
1497 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1498 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1499
1500 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1501 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1502
1503 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1504 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1505
1506 /* For AAPCS, padding should never be below the argument. For other ABIs,
1507 * mimic the default. */
1508 #define PAD_VARARGS_DOWN \
1509 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1510
1511 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1512 for a call to a function whose data type is FNTYPE.
1513 For a library call, FNTYPE is 0.
1514 On the ARM, the offset starts at 0. */
1515 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1516 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1517
1518 /* Update the data in CUM to advance over an argument
1519 of mode MODE and data type TYPE.
1520 (TYPE is null for libcalls where that information may not be available.) */
1521 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1522 (CUM).nargs += 1; \
1523 if (arm_vector_mode_supported_p (MODE) \
1524 && (CUM).named_count > (CUM).nargs \
1525 && TARGET_IWMMXT_ABI) \
1526 (CUM).iwmmxt_nregs += 1; \
1527 else \
1528 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1529
1530 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1531 argument with the specified mode and type. If it is not defined,
1532 `PARM_BOUNDARY' is used for all arguments. */
1533 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1534 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1535 ? DOUBLEWORD_ALIGNMENT \
1536 : PARM_BOUNDARY )
1537
1538 /* 1 if N is a possible register number for function argument passing.
1539 On the ARM, r0-r3 are used to pass args. */
1540 #define FUNCTION_ARG_REGNO_P(REGNO) \
1541 (IN_RANGE ((REGNO), 0, 3) \
1542 || (TARGET_IWMMXT_ABI \
1543 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1544
1545 \f
1546 /* If your target environment doesn't prefix user functions with an
1547 underscore, you may wish to re-define this to prevent any conflicts.
1548 e.g. AOF may prefix mcount with an underscore. */
1549 #ifndef ARM_MCOUNT_NAME
1550 #define ARM_MCOUNT_NAME "*mcount"
1551 #endif
1552
1553 /* Call the function profiler with a given profile label. The Acorn
1554 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1555 On the ARM the full profile code will look like:
1556 .data
1557 LP1
1558 .word 0
1559 .text
1560 mov ip, lr
1561 bl mcount
1562 .word LP1
1563
1564 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1565 will output the .text section.
1566
1567 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1568 ``prof'' doesn't seem to mind about this!
1569
1570 Note - this version of the code is designed to work in both ARM and
1571 Thumb modes. */
1572 #ifndef ARM_FUNCTION_PROFILER
1573 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1574 { \
1575 char temp[20]; \
1576 rtx sym; \
1577 \
1578 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1579 IP_REGNUM, LR_REGNUM); \
1580 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1581 fputc ('\n', STREAM); \
1582 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1583 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1584 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1585 }
1586 #endif
1587
1588 #ifdef THUMB_FUNCTION_PROFILER
1589 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1590 if (TARGET_ARM) \
1591 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1592 else \
1593 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1594 #else
1595 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1596 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1597 #endif
1598
1599 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1600 the stack pointer does not matter. The value is tested only in
1601 functions that have frame pointers.
1602 No definition is equivalent to always zero.
1603
1604 On the ARM, the function epilogue recovers the stack pointer from the
1605 frame. */
1606 #define EXIT_IGNORE_STACK 1
1607
1608 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1609
1610 /* Determine if the epilogue should be output as RTL.
1611 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1612 /* This is disabled for Thumb-2 because it will confuse the
1613 conditional insn counter. */
1614 #define USE_RETURN_INSN(ISCOND) \
1615 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1616
1617 /* Definitions for register eliminations.
1618
1619 This is an array of structures. Each structure initializes one pair
1620 of eliminable registers. The "from" register number is given first,
1621 followed by "to". Eliminations of the same "from" register are listed
1622 in order of preference.
1623
1624 We have two registers that can be eliminated on the ARM. First, the
1625 arg pointer register can often be eliminated in favor of the stack
1626 pointer register. Secondly, the pseudo frame pointer register can always
1627 be eliminated; it is replaced with either the stack or the real frame
1628 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1629 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1630
1631 #define ELIMINABLE_REGS \
1632 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1633 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1634 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1635 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1636 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1637 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1638 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1639
1640 /* Given FROM and TO register numbers, say whether this elimination is
1641 allowed. Frame pointer elimination is automatically handled.
1642
1643 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1644 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1645 pointer, we must eliminate FRAME_POINTER_REGNUM into
1646 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1647 ARG_POINTER_REGNUM. */
1648 #define CAN_ELIMINATE(FROM, TO) \
1649 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1650 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1651 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1652 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1653 1)
1654
1655 /* Define the offset between two registers, one to be eliminated, and the
1656 other its replacement, at the start of a routine. */
1657 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1658 if (TARGET_ARM) \
1659 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1660 else \
1661 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1662
1663 /* Special case handling of the location of arguments passed on the stack. */
1664 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1665
1666 /* Initialize data used by insn expanders. This is called from insn_emit,
1667 once for every function before code is generated. */
1668 #define INIT_EXPANDERS arm_init_expanders ()
1669
1670 /* Output assembler code for a block containing the constant parts
1671 of a trampoline, leaving space for the variable parts.
1672
1673 On the ARM, (if r8 is the static chain regnum, and remembering that
1674 referencing pc adds an offset of 8) the trampoline looks like:
1675 ldr r8, [pc, #0]
1676 ldr pc, [pc]
1677 .word static chain value
1678 .word function's address
1679 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1680 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1681 { \
1682 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1683 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1684 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1685 PC_REGNUM, PC_REGNUM); \
1686 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1687 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1688 }
1689
1690 /* The Thumb-2 trampoline is similar to the arm implementation.
1691 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1692 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1693 { \
1694 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1695 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1696 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1697 PC_REGNUM, PC_REGNUM); \
1698 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1699 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1700 }
1701
1702 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1703 { \
1704 ASM_OUTPUT_ALIGN(FILE, 2); \
1705 fprintf (FILE, "\t.code\t16\n"); \
1706 fprintf (FILE, ".Ltrampoline_start:\n"); \
1707 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1708 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1709 PC_REGNUM); \
1710 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1711 STATIC_CHAIN_REGNUM); \
1712 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1713 PC_REGNUM); \
1714 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1715 SP_REGNUM); \
1716 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1717 PC_REGNUM); \
1718 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1719 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1720 }
1721
1722 #define TRAMPOLINE_TEMPLATE(FILE) \
1723 if (TARGET_ARM) \
1724 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1725 else if (TARGET_THUMB2) \
1726 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1727 else \
1728 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1729
1730 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1731 of the address. */
1732 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1733 { \
1734 if (TARGET_THUMB) \
1735 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1736 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1737 } while(0)
1738
1739 /* Length in units of the trampoline for entering a nested function. */
1740 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1741
1742 /* Alignment required for a trampoline in bits. */
1743 #define TRAMPOLINE_ALIGNMENT 32
1744
1745
1746 /* Emit RTL insns to initialize the variable parts of a trampoline.
1747 FNADDR is an RTX for the address of the function's pure code.
1748 CXT is an RTX for the static chain value for the function. */
1749 #ifndef INITIALIZE_TRAMPOLINE
1750 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1751 { \
1752 emit_move_insn (gen_rtx_MEM (SImode, \
1753 plus_constant (TRAMP, \
1754 TARGET_32BIT ? 8 : 12)), \
1755 CXT); \
1756 emit_move_insn (gen_rtx_MEM (SImode, \
1757 plus_constant (TRAMP, \
1758 TARGET_32BIT ? 12 : 16)), \
1759 FNADDR); \
1760 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1761 0, VOIDmode, 2, TRAMP, Pmode, \
1762 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1763 }
1764 #endif
1765
1766 \f
1767 /* Addressing modes, and classification of registers for them. */
1768 #define HAVE_POST_INCREMENT 1
1769 #define HAVE_PRE_INCREMENT TARGET_32BIT
1770 #define HAVE_POST_DECREMENT TARGET_32BIT
1771 #define HAVE_PRE_DECREMENT TARGET_32BIT
1772 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1773 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1774 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1775 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1776
1777 /* Macros to check register numbers against specific register classes. */
1778
1779 /* These assume that REGNO is a hard or pseudo reg number.
1780 They give nonzero only if REGNO is a hard reg of the suitable class
1781 or a pseudo reg currently allocated to a suitable hard reg.
1782 Since they use reg_renumber, they are safe only once reg_renumber
1783 has been allocated, which happens in local-alloc.c. */
1784 #define TEST_REGNO(R, TEST, VALUE) \
1785 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1786
1787 /* Don't allow the pc to be used. */
1788 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1789 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1790 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1791 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1792
1793 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1794 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1795 || (GET_MODE_SIZE (MODE) >= 4 \
1796 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1797
1798 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1799 (TARGET_THUMB1 \
1800 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1801 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1802
1803 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1804 For Thumb, we can not use SP + reg, so reject SP. */
1805 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1806 REGNO_OK_FOR_INDEX_P (X)
1807
1808 /* For ARM code, we don't care about the mode, but for Thumb, the index
1809 must be suitable for use in a QImode load. */
1810 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1811 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1812
1813 /* Maximum number of registers that can appear in a valid memory address.
1814 Shifts in addresses can't be by a register. */
1815 #define MAX_REGS_PER_ADDRESS 2
1816
1817 /* Recognize any constant value that is a valid address. */
1818 /* XXX We can address any constant, eventually... */
1819
1820 #ifdef AOF_ASSEMBLER
1821
1822 #define CONSTANT_ADDRESS_P(X) \
1823 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1824
1825 #else
1826
1827 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1828 #define CONSTANT_ADDRESS_P(X) \
1829 (GET_CODE (X) == SYMBOL_REF \
1830 && (CONSTANT_POOL_ADDRESS_P (X) \
1831 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1832
1833 #endif /* AOF_ASSEMBLER */
1834
1835 /* Nonzero if the constant value X is a legitimate general operand.
1836 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1837
1838 On the ARM, allow any integer (invalid ones are removed later by insn
1839 patterns), nice doubles and symbol_refs which refer to the function's
1840 constant pool XXX.
1841
1842 When generating pic allow anything. */
1843 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1844
1845 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1846 ( GET_CODE (X) == CONST_INT \
1847 || GET_CODE (X) == CONST_DOUBLE \
1848 || CONSTANT_ADDRESS_P (X) \
1849 || flag_pic)
1850
1851 #define LEGITIMATE_CONSTANT_P(X) \
1852 (!arm_tls_referenced_p (X) \
1853 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1854 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1855
1856 /* Special characters prefixed to function names
1857 in order to encode attribute like information.
1858 Note, '@' and '*' have already been taken. */
1859 #define SHORT_CALL_FLAG_CHAR '^'
1860 #define LONG_CALL_FLAG_CHAR '#'
1861
1862 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1863 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1864
1865 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1866 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1867
1868 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1869 #define SUBTARGET_NAME_ENCODING_LENGTHS
1870 #endif
1871
1872 /* This is a C fragment for the inside of a switch statement.
1873 Each case label should return the number of characters to
1874 be stripped from the start of a function's name, if that
1875 name starts with the indicated character. */
1876 #define ARM_NAME_ENCODING_LENGTHS \
1877 case SHORT_CALL_FLAG_CHAR: return 1; \
1878 case LONG_CALL_FLAG_CHAR: return 1; \
1879 case '*': return 1; \
1880 SUBTARGET_NAME_ENCODING_LENGTHS
1881
1882 /* This is how to output a reference to a user-level label named NAME.
1883 `assemble_name' uses this. */
1884 #undef ASM_OUTPUT_LABELREF
1885 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1886 arm_asm_output_labelref (FILE, NAME)
1887
1888 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1889 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1890 if (TARGET_THUMB2) \
1891 thumb2_asm_output_opcode (STREAM);
1892
1893 /* The EABI specifies that constructors should go in .init_array.
1894 Other targets use .ctors for compatibility. */
1895 #ifndef ARM_EABI_CTORS_SECTION_OP
1896 #define ARM_EABI_CTORS_SECTION_OP \
1897 "\t.section\t.init_array,\"aw\",%init_array"
1898 #endif
1899 #ifndef ARM_EABI_DTORS_SECTION_OP
1900 #define ARM_EABI_DTORS_SECTION_OP \
1901 "\t.section\t.fini_array,\"aw\",%fini_array"
1902 #endif
1903 #define ARM_CTORS_SECTION_OP \
1904 "\t.section\t.ctors,\"aw\",%progbits"
1905 #define ARM_DTORS_SECTION_OP \
1906 "\t.section\t.dtors,\"aw\",%progbits"
1907
1908 /* Define CTORS_SECTION_ASM_OP. */
1909 #undef CTORS_SECTION_ASM_OP
1910 #undef DTORS_SECTION_ASM_OP
1911 #ifndef IN_LIBGCC2
1912 # define CTORS_SECTION_ASM_OP \
1913 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1914 # define DTORS_SECTION_ASM_OP \
1915 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1916 #else /* !defined (IN_LIBGCC2) */
1917 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1918 so we cannot use the definition above. */
1919 # ifdef __ARM_EABI__
1920 /* The .ctors section is not part of the EABI, so we do not define
1921 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1922 from trying to use it. We do define it when doing normal
1923 compilation, as .init_array can be used instead of .ctors. */
1924 /* There is no need to emit begin or end markers when using
1925 init_array; the dynamic linker will compute the size of the
1926 array itself based on special symbols created by the static
1927 linker. However, we do need to arrange to set up
1928 exception-handling here. */
1929 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1930 # define CTOR_LIST_END /* empty */
1931 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1932 # define DTOR_LIST_END /* empty */
1933 # else /* !defined (__ARM_EABI__) */
1934 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1935 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1936 # endif /* !defined (__ARM_EABI__) */
1937 #endif /* !defined (IN_LIBCC2) */
1938
1939 /* True if the operating system can merge entities with vague linkage
1940 (e.g., symbols in COMDAT group) during dynamic linking. */
1941 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1942 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1943 #endif
1944
1945 /* Set the short-call flag for any function compiled in the current
1946 compilation unit. We skip this for functions with the section
1947 attribute when long-calls are in effect as this tells the compiler
1948 that the section might be placed a long way from the caller.
1949 See arm_is_longcall_p() for more information. */
1950 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1951 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1952 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1953
1954 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1955
1956 #ifdef TARGET_UNWIND_INFO
1957 #define ARM_EABI_UNWIND_TABLES \
1958 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1959 #else
1960 #define ARM_EABI_UNWIND_TABLES 0
1961 #endif
1962
1963 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1964 and check its validity for a certain class.
1965 We have two alternate definitions for each of them.
1966 The usual definition accepts all pseudo regs; the other rejects
1967 them unless they have been allocated suitable hard regs.
1968 The symbol REG_OK_STRICT causes the latter definition to be used.
1969 Thumb-2 has the same restrictions as arm. */
1970 #ifndef REG_OK_STRICT
1971
1972 #define ARM_REG_OK_FOR_BASE_P(X) \
1973 (REGNO (X) <= LAST_ARM_REGNUM \
1974 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1975 || REGNO (X) == FRAME_POINTER_REGNUM \
1976 || REGNO (X) == ARG_POINTER_REGNUM)
1977
1978 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1979 (REGNO (X) <= LAST_LO_REGNUM \
1980 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1981 || (GET_MODE_SIZE (MODE) >= 4 \
1982 && (REGNO (X) == STACK_POINTER_REGNUM \
1983 || (X) == hard_frame_pointer_rtx \
1984 || (X) == arg_pointer_rtx)))
1985
1986 #define REG_STRICT_P 0
1987
1988 #else /* REG_OK_STRICT */
1989
1990 #define ARM_REG_OK_FOR_BASE_P(X) \
1991 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1992
1993 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1994 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1995
1996 #define REG_STRICT_P 1
1997
1998 #endif /* REG_OK_STRICT */
1999
2000 /* Now define some helpers in terms of the above. */
2001
2002 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2003 (TARGET_THUMB1 \
2004 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2005 : ARM_REG_OK_FOR_BASE_P (X))
2006
2007 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2008
2009 /* For 16-bit Thumb, a valid index register is anything that can be used in
2010 a byte load instruction. */
2011 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2012 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2013
2014 /* Nonzero if X is a hard reg that can be used as an index
2015 or if it is a pseudo reg. On the Thumb, the stack pointer
2016 is not suitable. */
2017 #define REG_OK_FOR_INDEX_P(X) \
2018 (TARGET_THUMB1 \
2019 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2020 : ARM_REG_OK_FOR_INDEX_P (X))
2021
2022 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2023 For Thumb, we can not use SP + reg, so reject SP. */
2024 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2025 REG_OK_FOR_INDEX_P (X)
2026 \f
2027 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2028 that is a valid memory address for an instruction.
2029 The MODE argument is the machine mode for the MEM expression
2030 that wants to use this address. */
2031
2032 #define ARM_BASE_REGISTER_RTX_P(X) \
2033 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2034
2035 #define ARM_INDEX_REGISTER_RTX_P(X) \
2036 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2037
2038 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2039 { \
2040 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2041 goto WIN; \
2042 }
2043
2044 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2045 { \
2046 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2047 goto WIN; \
2048 }
2049
2050 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2051 { \
2052 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2053 goto WIN; \
2054 }
2055
2056 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2057 if (TARGET_ARM) \
2058 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2059 else if (TARGET_THUMB2) \
2060 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2061 else /* if (TARGET_THUMB1) */ \
2062 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2063
2064 \f
2065 /* Try machine-dependent ways of modifying an illegitimate address
2066 to be legitimate. If we find one, return the new, valid address. */
2067 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2068 do { \
2069 X = arm_legitimize_address (X, OLDX, MODE); \
2070 } while (0)
2071
2072 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2073 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2074 do { \
2075 } while (0)
2076
2077 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2078 do { \
2079 X = thumb_legitimize_address (X, OLDX, MODE); \
2080 } while (0)
2081
2082 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2083 do { \
2084 if (TARGET_ARM) \
2085 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2086 else if (TARGET_THUMB2) \
2087 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2088 else \
2089 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2090 \
2091 if (memory_address_p (MODE, X)) \
2092 goto WIN; \
2093 } while (0)
2094
2095 /* Go to LABEL if ADDR (a legitimate address expression)
2096 has an effect that depends on the machine mode it is used for. */
2097 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2098 { \
2099 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2100 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2101 goto LABEL; \
2102 }
2103
2104 /* Nothing helpful to do for the Thumb */
2105 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2106 if (TARGET_32BIT) \
2107 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2108 \f
2109
2110 /* Specify the machine mode that this machine uses
2111 for the index in the tablejump instruction. */
2112 #define CASE_VECTOR_MODE Pmode
2113
2114 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2115
2116 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2117 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2118 : (max >= 0x200) ? HImode \
2119 : QImode)
2120
2121 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2122 unsigned is probably best, but may break some code. */
2123 #ifndef DEFAULT_SIGNED_CHAR
2124 #define DEFAULT_SIGNED_CHAR 0
2125 #endif
2126
2127 /* Max number of bytes we can move from memory to memory
2128 in one reasonably fast instruction. */
2129 #define MOVE_MAX 4
2130
2131 #undef MOVE_RATIO
2132 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2133
2134 /* Define if operations between registers always perform the operation
2135 on the full register even if a narrower mode is specified. */
2136 #define WORD_REGISTER_OPERATIONS
2137
2138 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2139 will either zero-extend or sign-extend. The value of this macro should
2140 be the code that says which one of the two operations is implicitly
2141 done, UNKNOWN if none. */
2142 #define LOAD_EXTEND_OP(MODE) \
2143 (TARGET_THUMB ? ZERO_EXTEND : \
2144 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2145 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2146
2147 /* Nonzero if access to memory by bytes is slow and undesirable. */
2148 #define SLOW_BYTE_ACCESS 0
2149
2150 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2151
2152 /* Immediate shift counts are truncated by the output routines (or was it
2153 the assembler?). Shift counts in a register are truncated by ARM. Note
2154 that the native compiler puts too large (> 32) immediate shift counts
2155 into a register and shifts by the register, letting the ARM decide what
2156 to do instead of doing that itself. */
2157 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2158 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2159 On the arm, Y in a register is used modulo 256 for the shift. Only for
2160 rotates is modulo 32 used. */
2161 /* #define SHIFT_COUNT_TRUNCATED 1 */
2162
2163 /* All integers have the same format so truncation is easy. */
2164 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2165
2166 /* Calling from registers is a massive pain. */
2167 #define NO_FUNCTION_CSE 1
2168
2169 /* The machine modes of pointers and functions */
2170 #define Pmode SImode
2171 #define FUNCTION_MODE Pmode
2172
2173 #define ARM_FRAME_RTX(X) \
2174 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2175 || (X) == arg_pointer_rtx)
2176
2177 /* Moves to and from memory are quite expensive */
2178 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2179 (TARGET_32BIT ? 10 : \
2180 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2181 * (CLASS == LO_REGS ? 1 : 2)))
2182
2183 /* Try to generate sequences that don't involve branches, we can then use
2184 conditional instructions */
2185 #define BRANCH_COST \
2186 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2187 \f
2188 /* Position Independent Code. */
2189 /* We decide which register to use based on the compilation options and
2190 the assembler in use; this is more general than the APCS restriction of
2191 using sb (r9) all the time. */
2192 extern unsigned arm_pic_register;
2193
2194 /* The register number of the register used to address a table of static
2195 data addresses in memory. */
2196 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2197
2198 /* We can't directly access anything that contains a symbol,
2199 nor can we indirect via the constant pool. One exception is
2200 UNSPEC_TLS, which is always PIC. */
2201 #define LEGITIMATE_PIC_OPERAND_P(X) \
2202 (!(symbol_mentioned_p (X) \
2203 || label_mentioned_p (X) \
2204 || (GET_CODE (X) == SYMBOL_REF \
2205 && CONSTANT_POOL_ADDRESS_P (X) \
2206 && (symbol_mentioned_p (get_pool_constant (X)) \
2207 || label_mentioned_p (get_pool_constant (X))))) \
2208 || tls_mentioned_p (X))
2209
2210 /* We need to know when we are making a constant pool; this determines
2211 whether data needs to be in the GOT or can be referenced via a GOT
2212 offset. */
2213 extern int making_const_table;
2214 \f
2215 /* Handle pragmas for compatibility with Intel's compilers. */
2216 #define REGISTER_TARGET_PRAGMAS() do { \
2217 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2218 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2219 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2220 } while (0)
2221
2222 /* Condition code information. */
2223 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2224 return the mode to be used for the comparison. */
2225
2226 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2227
2228 #define REVERSIBLE_CC_MODE(MODE) 1
2229
2230 #define REVERSE_CONDITION(CODE,MODE) \
2231 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2232 ? reverse_condition_maybe_unordered (code) \
2233 : reverse_condition (code))
2234
2235 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2236 do \
2237 { \
2238 if (GET_CODE (OP1) == CONST_INT \
2239 && ! (const_ok_for_arm (INTVAL (OP1)) \
2240 || (const_ok_for_arm (- INTVAL (OP1))))) \
2241 { \
2242 rtx const_op = OP1; \
2243 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2244 &const_op); \
2245 OP1 = const_op; \
2246 } \
2247 } \
2248 while (0)
2249
2250 /* The arm5 clz instruction returns 32. */
2251 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2252 \f
2253 #undef ASM_APP_OFF
2254 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2255 TARGET_THUMB2 ? "\t.thumb\n" : "")
2256
2257 /* Output a push or a pop instruction (only used when profiling). */
2258 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2259 do \
2260 { \
2261 if (TARGET_ARM) \
2262 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2263 STACK_POINTER_REGNUM, REGNO); \
2264 else \
2265 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2266 } while (0)
2267
2268
2269 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2270 do \
2271 { \
2272 if (TARGET_ARM) \
2273 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2274 STACK_POINTER_REGNUM, REGNO); \
2275 else \
2276 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2277 } while (0)
2278
2279 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2280 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2281
2282 /* This is how to output a label which precedes a jumptable. Since
2283 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2284 #undef ASM_OUTPUT_CASE_LABEL
2285 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2286 do \
2287 { \
2288 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2289 ASM_OUTPUT_ALIGN (FILE, 2); \
2290 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2291 } \
2292 while (0)
2293
2294 /* Make sure subsequent insns are aligned after a TBB. */
2295 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2296 do \
2297 { \
2298 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2299 ASM_OUTPUT_ALIGN (FILE, 1); \
2300 } \
2301 while (0)
2302
2303 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2304 do \
2305 { \
2306 if (TARGET_THUMB) \
2307 { \
2308 if (is_called_in_ARM_mode (DECL) \
2309 || (TARGET_THUMB1 && current_function_is_thunk)) \
2310 fprintf (STREAM, "\t.code 32\n") ; \
2311 else if (TARGET_THUMB1) \
2312 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2313 else \
2314 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2315 } \
2316 if (TARGET_POKE_FUNCTION_NAME) \
2317 arm_poke_function_name (STREAM, (char *) NAME); \
2318 } \
2319 while (0)
2320
2321 /* For aliases of functions we use .thumb_set instead. */
2322 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2323 do \
2324 { \
2325 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2326 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2327 \
2328 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2329 { \
2330 fprintf (FILE, "\t.thumb_set "); \
2331 assemble_name (FILE, LABEL1); \
2332 fprintf (FILE, ","); \
2333 assemble_name (FILE, LABEL2); \
2334 fprintf (FILE, "\n"); \
2335 } \
2336 else \
2337 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2338 } \
2339 while (0)
2340
2341 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2342 /* To support -falign-* switches we need to use .p2align so
2343 that alignment directives in code sections will be padded
2344 with no-op instructions, rather than zeroes. */
2345 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2346 if ((LOG) != 0) \
2347 { \
2348 if ((MAX_SKIP) == 0) \
2349 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2350 else \
2351 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2352 (int) (LOG), (int) (MAX_SKIP)); \
2353 }
2354 #endif
2355 \f
2356 /* Add two bytes to the length of conditionally executed Thumb-2
2357 instructions for the IT instruction. */
2358 #define ADJUST_INSN_LENGTH(insn, length) \
2359 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2360 length += 2;
2361
2362 /* Only perform branch elimination (by making instructions conditional) if
2363 we're optimizing. For Thumb-2 check if any IT instructions need
2364 outputting. */
2365 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2366 if (TARGET_ARM && optimize) \
2367 arm_final_prescan_insn (INSN); \
2368 else if (TARGET_THUMB2) \
2369 thumb2_final_prescan_insn (INSN); \
2370 else if (TARGET_THUMB1) \
2371 thumb1_final_prescan_insn (INSN)
2372
2373 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2374 (CODE == '@' || CODE == '|' || CODE == '.' \
2375 || CODE == '(' || CODE == ')' \
2376 || (TARGET_32BIT && (CODE == '?')) \
2377 || (TARGET_THUMB2 && (CODE == '!')) \
2378 || (TARGET_THUMB && (CODE == '_')))
2379
2380 /* Output an operand of an instruction. */
2381 #define PRINT_OPERAND(STREAM, X, CODE) \
2382 arm_print_operand (STREAM, X, CODE)
2383
2384 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2385 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2386 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2387 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2388 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2389 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2390 : 0))))
2391
2392 /* Output the address of an operand. */
2393 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2394 { \
2395 int is_minus = GET_CODE (X) == MINUS; \
2396 \
2397 if (GET_CODE (X) == REG) \
2398 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2399 else if (GET_CODE (X) == PLUS || is_minus) \
2400 { \
2401 rtx base = XEXP (X, 0); \
2402 rtx index = XEXP (X, 1); \
2403 HOST_WIDE_INT offset = 0; \
2404 if (GET_CODE (base) != REG) \
2405 { \
2406 /* Ensure that BASE is a register. */ \
2407 /* (one of them must be). */ \
2408 rtx temp = base; \
2409 base = index; \
2410 index = temp; \
2411 } \
2412 switch (GET_CODE (index)) \
2413 { \
2414 case CONST_INT: \
2415 offset = INTVAL (index); \
2416 if (is_minus) \
2417 offset = -offset; \
2418 asm_fprintf (STREAM, "[%r, #%wd]", \
2419 REGNO (base), offset); \
2420 break; \
2421 \
2422 case REG: \
2423 asm_fprintf (STREAM, "[%r, %s%r]", \
2424 REGNO (base), is_minus ? "-" : "", \
2425 REGNO (index)); \
2426 break; \
2427 \
2428 case MULT: \
2429 case ASHIFTRT: \
2430 case LSHIFTRT: \
2431 case ASHIFT: \
2432 case ROTATERT: \
2433 { \
2434 asm_fprintf (STREAM, "[%r, %s%r", \
2435 REGNO (base), is_minus ? "-" : "", \
2436 REGNO (XEXP (index, 0))); \
2437 arm_print_operand (STREAM, index, 'S'); \
2438 fputs ("]", STREAM); \
2439 break; \
2440 } \
2441 \
2442 default: \
2443 gcc_unreachable (); \
2444 } \
2445 } \
2446 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2447 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2448 { \
2449 extern enum machine_mode output_memory_reference_mode; \
2450 \
2451 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2452 \
2453 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2454 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2455 REGNO (XEXP (X, 0)), \
2456 GET_CODE (X) == PRE_DEC ? "-" : "", \
2457 GET_MODE_SIZE (output_memory_reference_mode)); \
2458 else \
2459 asm_fprintf (STREAM, "[%r], #%s%d", \
2460 REGNO (XEXP (X, 0)), \
2461 GET_CODE (X) == POST_DEC ? "-" : "", \
2462 GET_MODE_SIZE (output_memory_reference_mode)); \
2463 } \
2464 else if (GET_CODE (X) == PRE_MODIFY) \
2465 { \
2466 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2467 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2468 asm_fprintf (STREAM, "#%wd]!", \
2469 INTVAL (XEXP (XEXP (X, 1), 1))); \
2470 else \
2471 asm_fprintf (STREAM, "%r]!", \
2472 REGNO (XEXP (XEXP (X, 1), 1))); \
2473 } \
2474 else if (GET_CODE (X) == POST_MODIFY) \
2475 { \
2476 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2477 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2478 asm_fprintf (STREAM, "#%wd", \
2479 INTVAL (XEXP (XEXP (X, 1), 1))); \
2480 else \
2481 asm_fprintf (STREAM, "%r", \
2482 REGNO (XEXP (XEXP (X, 1), 1))); \
2483 } \
2484 else output_addr_const (STREAM, X); \
2485 }
2486
2487 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2488 { \
2489 if (GET_CODE (X) == REG) \
2490 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2491 else if (GET_CODE (X) == POST_INC) \
2492 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2493 else if (GET_CODE (X) == PLUS) \
2494 { \
2495 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2496 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2497 asm_fprintf (STREAM, "[%r, #%wd]", \
2498 REGNO (XEXP (X, 0)), \
2499 INTVAL (XEXP (X, 1))); \
2500 else \
2501 asm_fprintf (STREAM, "[%r, %r]", \
2502 REGNO (XEXP (X, 0)), \
2503 REGNO (XEXP (X, 1))); \
2504 } \
2505 else \
2506 output_addr_const (STREAM, X); \
2507 }
2508
2509 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2510 if (TARGET_32BIT) \
2511 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2512 else \
2513 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2514
2515 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2516 if (arm_output_addr_const_extra (file, x) == FALSE) \
2517 goto fail
2518
2519 /* A C expression whose value is RTL representing the value of the return
2520 address for the frame COUNT steps up from the current frame. */
2521
2522 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2523 arm_return_addr (COUNT, FRAME)
2524
2525 /* Mask of the bits in the PC that contain the real return address
2526 when running in 26-bit mode. */
2527 #define RETURN_ADDR_MASK26 (0x03fffffc)
2528
2529 /* Pick up the return address upon entry to a procedure. Used for
2530 dwarf2 unwind information. This also enables the table driven
2531 mechanism. */
2532 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2533 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2534
2535 /* Used to mask out junk bits from the return address, such as
2536 processor state, interrupt status, condition codes and the like. */
2537 #define MASK_RETURN_ADDR \
2538 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2539 in 26 bit mode, the condition codes must be masked out of the \
2540 return address. This does not apply to ARM6 and later processors \
2541 when running in 32 bit mode. */ \
2542 ((arm_arch4 || TARGET_THUMB) \
2543 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2544 : arm_gen_return_addr_mask ())
2545
2546 \f
2547 enum arm_builtins
2548 {
2549 ARM_BUILTIN_GETWCX,
2550 ARM_BUILTIN_SETWCX,
2551
2552 ARM_BUILTIN_WZERO,
2553
2554 ARM_BUILTIN_WAVG2BR,
2555 ARM_BUILTIN_WAVG2HR,
2556 ARM_BUILTIN_WAVG2B,
2557 ARM_BUILTIN_WAVG2H,
2558
2559 ARM_BUILTIN_WACCB,
2560 ARM_BUILTIN_WACCH,
2561 ARM_BUILTIN_WACCW,
2562
2563 ARM_BUILTIN_WMACS,
2564 ARM_BUILTIN_WMACSZ,
2565 ARM_BUILTIN_WMACU,
2566 ARM_BUILTIN_WMACUZ,
2567
2568 ARM_BUILTIN_WSADB,
2569 ARM_BUILTIN_WSADBZ,
2570 ARM_BUILTIN_WSADH,
2571 ARM_BUILTIN_WSADHZ,
2572
2573 ARM_BUILTIN_WALIGN,
2574
2575 ARM_BUILTIN_TMIA,
2576 ARM_BUILTIN_TMIAPH,
2577 ARM_BUILTIN_TMIABB,
2578 ARM_BUILTIN_TMIABT,
2579 ARM_BUILTIN_TMIATB,
2580 ARM_BUILTIN_TMIATT,
2581
2582 ARM_BUILTIN_TMOVMSKB,
2583 ARM_BUILTIN_TMOVMSKH,
2584 ARM_BUILTIN_TMOVMSKW,
2585
2586 ARM_BUILTIN_TBCSTB,
2587 ARM_BUILTIN_TBCSTH,
2588 ARM_BUILTIN_TBCSTW,
2589
2590 ARM_BUILTIN_WMADDS,
2591 ARM_BUILTIN_WMADDU,
2592
2593 ARM_BUILTIN_WPACKHSS,
2594 ARM_BUILTIN_WPACKWSS,
2595 ARM_BUILTIN_WPACKDSS,
2596 ARM_BUILTIN_WPACKHUS,
2597 ARM_BUILTIN_WPACKWUS,
2598 ARM_BUILTIN_WPACKDUS,
2599
2600 ARM_BUILTIN_WADDB,
2601 ARM_BUILTIN_WADDH,
2602 ARM_BUILTIN_WADDW,
2603 ARM_BUILTIN_WADDSSB,
2604 ARM_BUILTIN_WADDSSH,
2605 ARM_BUILTIN_WADDSSW,
2606 ARM_BUILTIN_WADDUSB,
2607 ARM_BUILTIN_WADDUSH,
2608 ARM_BUILTIN_WADDUSW,
2609 ARM_BUILTIN_WSUBB,
2610 ARM_BUILTIN_WSUBH,
2611 ARM_BUILTIN_WSUBW,
2612 ARM_BUILTIN_WSUBSSB,
2613 ARM_BUILTIN_WSUBSSH,
2614 ARM_BUILTIN_WSUBSSW,
2615 ARM_BUILTIN_WSUBUSB,
2616 ARM_BUILTIN_WSUBUSH,
2617 ARM_BUILTIN_WSUBUSW,
2618
2619 ARM_BUILTIN_WAND,
2620 ARM_BUILTIN_WANDN,
2621 ARM_BUILTIN_WOR,
2622 ARM_BUILTIN_WXOR,
2623
2624 ARM_BUILTIN_WCMPEQB,
2625 ARM_BUILTIN_WCMPEQH,
2626 ARM_BUILTIN_WCMPEQW,
2627 ARM_BUILTIN_WCMPGTUB,
2628 ARM_BUILTIN_WCMPGTUH,
2629 ARM_BUILTIN_WCMPGTUW,
2630 ARM_BUILTIN_WCMPGTSB,
2631 ARM_BUILTIN_WCMPGTSH,
2632 ARM_BUILTIN_WCMPGTSW,
2633
2634 ARM_BUILTIN_TEXTRMSB,
2635 ARM_BUILTIN_TEXTRMSH,
2636 ARM_BUILTIN_TEXTRMSW,
2637 ARM_BUILTIN_TEXTRMUB,
2638 ARM_BUILTIN_TEXTRMUH,
2639 ARM_BUILTIN_TEXTRMUW,
2640 ARM_BUILTIN_TINSRB,
2641 ARM_BUILTIN_TINSRH,
2642 ARM_BUILTIN_TINSRW,
2643
2644 ARM_BUILTIN_WMAXSW,
2645 ARM_BUILTIN_WMAXSH,
2646 ARM_BUILTIN_WMAXSB,
2647 ARM_BUILTIN_WMAXUW,
2648 ARM_BUILTIN_WMAXUH,
2649 ARM_BUILTIN_WMAXUB,
2650 ARM_BUILTIN_WMINSW,
2651 ARM_BUILTIN_WMINSH,
2652 ARM_BUILTIN_WMINSB,
2653 ARM_BUILTIN_WMINUW,
2654 ARM_BUILTIN_WMINUH,
2655 ARM_BUILTIN_WMINUB,
2656
2657 ARM_BUILTIN_WMULUM,
2658 ARM_BUILTIN_WMULSM,
2659 ARM_BUILTIN_WMULUL,
2660
2661 ARM_BUILTIN_PSADBH,
2662 ARM_BUILTIN_WSHUFH,
2663
2664 ARM_BUILTIN_WSLLH,
2665 ARM_BUILTIN_WSLLW,
2666 ARM_BUILTIN_WSLLD,
2667 ARM_BUILTIN_WSRAH,
2668 ARM_BUILTIN_WSRAW,
2669 ARM_BUILTIN_WSRAD,
2670 ARM_BUILTIN_WSRLH,
2671 ARM_BUILTIN_WSRLW,
2672 ARM_BUILTIN_WSRLD,
2673 ARM_BUILTIN_WRORH,
2674 ARM_BUILTIN_WRORW,
2675 ARM_BUILTIN_WRORD,
2676 ARM_BUILTIN_WSLLHI,
2677 ARM_BUILTIN_WSLLWI,
2678 ARM_BUILTIN_WSLLDI,
2679 ARM_BUILTIN_WSRAHI,
2680 ARM_BUILTIN_WSRAWI,
2681 ARM_BUILTIN_WSRADI,
2682 ARM_BUILTIN_WSRLHI,
2683 ARM_BUILTIN_WSRLWI,
2684 ARM_BUILTIN_WSRLDI,
2685 ARM_BUILTIN_WRORHI,
2686 ARM_BUILTIN_WRORWI,
2687 ARM_BUILTIN_WRORDI,
2688
2689 ARM_BUILTIN_WUNPCKIHB,
2690 ARM_BUILTIN_WUNPCKIHH,
2691 ARM_BUILTIN_WUNPCKIHW,
2692 ARM_BUILTIN_WUNPCKILB,
2693 ARM_BUILTIN_WUNPCKILH,
2694 ARM_BUILTIN_WUNPCKILW,
2695
2696 ARM_BUILTIN_WUNPCKEHSB,
2697 ARM_BUILTIN_WUNPCKEHSH,
2698 ARM_BUILTIN_WUNPCKEHSW,
2699 ARM_BUILTIN_WUNPCKEHUB,
2700 ARM_BUILTIN_WUNPCKEHUH,
2701 ARM_BUILTIN_WUNPCKEHUW,
2702 ARM_BUILTIN_WUNPCKELSB,
2703 ARM_BUILTIN_WUNPCKELSH,
2704 ARM_BUILTIN_WUNPCKELSW,
2705 ARM_BUILTIN_WUNPCKELUB,
2706 ARM_BUILTIN_WUNPCKELUH,
2707 ARM_BUILTIN_WUNPCKELUW,
2708
2709 ARM_BUILTIN_THREAD_POINTER,
2710
2711 ARM_BUILTIN_MAX
2712 };
2713
2714 /* Do not emit .note.GNU-stack by default. */
2715 #ifndef NEED_INDICATE_EXEC_STACK
2716 #define NEED_INDICATE_EXEC_STACK 0
2717 #endif
2718
2719 #endif /* ! GCC_ARM_H */