1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
77 static bool arm_assemble_integer (rtx
, unsigned int, int);
79 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
80 static arm_cc
get_arm_condition_code (rtx
);
81 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
82 static rtx
is_jump_table (rtx
);
83 static const char *output_multi_immediate (rtx
*, const char *, const char *,
85 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
86 static struct machine_function
*arm_init_machine_status (void);
87 static void thumb_exit (FILE *, int);
88 static rtx
is_jump_table (rtx
);
89 static HOST_WIDE_INT
get_jump_table_size (rtx
);
90 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
91 static Mnode
*add_minipool_forward_ref (Mfix
*);
92 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
93 static Mnode
*add_minipool_backward_ref (Mfix
*);
94 static void assign_minipool_offsets (Mfix
*);
95 static void arm_print_value (FILE *, rtx
);
96 static void dump_minipool (rtx
);
97 static int arm_barrier_cost (rtx
);
98 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
99 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
100 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
102 static void arm_reorg (void);
103 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
104 static int current_file_function_operand (rtx
);
105 static unsigned long arm_compute_save_reg0_reg12_mask (void);
106 static unsigned long arm_compute_save_reg_mask (void);
107 static unsigned long arm_isr_value (tree
);
108 static unsigned long arm_compute_func_type (void);
109 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
110 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
111 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
112 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static int arm_comp_type_attributes (tree
, tree
);
118 static void arm_set_default_type_attributes (tree
);
119 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
120 static int count_insns_for_constant (HOST_WIDE_INT
, int);
121 static int arm_get_strip_length (int);
122 static bool arm_function_ok_for_sibcall (tree
, tree
);
123 static void arm_internal_label (FILE *, const char *, unsigned long);
124 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
126 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
127 static bool arm_size_rtx_costs (rtx
, int, int, int *);
128 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
132 static int arm_address_cost (rtx
);
133 static bool arm_memory_load_p (rtx
);
134 static bool arm_cirrus_insn_p (rtx
);
135 static void cirrus_reorg (rtx
);
136 static void arm_init_builtins (void);
137 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
140 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
141 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
142 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
143 static void emit_constant_insn (rtx cond
, rtx pattern
);
144 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
148 static void arm_encode_section_info (tree
, rtx
, int);
151 static void arm_file_end (void);
154 static void aof_globalize_label (FILE *, const char *);
155 static void aof_dump_imports (FILE *);
156 static void aof_dump_pic_table (FILE *);
157 static void aof_file_start (void);
158 static void aof_file_end (void);
160 static rtx
arm_struct_value_rtx (tree
, int);
161 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
163 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
164 enum machine_mode
, tree
, bool);
165 static bool arm_promote_prototypes (tree
);
166 static bool arm_default_short_enums (void);
167 static bool arm_align_anon_bitfield (void);
169 static tree
arm_cxx_guard_type (void);
170 static bool arm_cxx_guard_mask_bit (void);
171 static tree
arm_get_cookie_size (tree
);
172 static bool arm_cookie_has_size (void);
173 static bool arm_cxx_cdtor_returns_this (void);
174 static bool arm_cxx_key_method_may_be_inline (void);
175 static bool arm_cxx_export_class_data (void);
176 static void arm_init_libfuncs (void);
177 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
179 /* Initialize the GCC target structure. */
180 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
181 #undef TARGET_MERGE_DECL_ATTRIBUTES
182 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
185 #undef TARGET_ATTRIBUTE_TABLE
186 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
188 #undef TARGET_ASM_FILE_END
189 #define TARGET_ASM_FILE_END arm_file_end
192 #undef TARGET_ASM_BYTE_OP
193 #define TARGET_ASM_BYTE_OP "\tDCB\t"
194 #undef TARGET_ASM_ALIGNED_HI_OP
195 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
196 #undef TARGET_ASM_ALIGNED_SI_OP
197 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
198 #undef TARGET_ASM_GLOBALIZE_LABEL
199 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
200 #undef TARGET_ASM_FILE_START
201 #define TARGET_ASM_FILE_START aof_file_start
202 #undef TARGET_ASM_FILE_END
203 #define TARGET_ASM_FILE_END aof_file_end
205 #undef TARGET_ASM_ALIGNED_SI_OP
206 #define TARGET_ASM_ALIGNED_SI_OP NULL
207 #undef TARGET_ASM_INTEGER
208 #define TARGET_ASM_INTEGER arm_assemble_integer
211 #undef TARGET_ASM_FUNCTION_PROLOGUE
212 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
214 #undef TARGET_ASM_FUNCTION_EPILOGUE
215 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
217 #undef TARGET_COMP_TYPE_ATTRIBUTES
218 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
220 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
221 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
223 #undef TARGET_SCHED_ADJUST_COST
224 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
226 #undef TARGET_ENCODE_SECTION_INFO
228 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
230 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
233 #undef TARGET_STRIP_NAME_ENCODING
234 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
236 #undef TARGET_ASM_INTERNAL_LABEL
237 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
239 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
240 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
242 #undef TARGET_ASM_OUTPUT_MI_THUNK
243 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
244 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
245 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
247 /* This will be overridden in arm_override_options. */
248 #undef TARGET_RTX_COSTS
249 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
250 #undef TARGET_ADDRESS_COST
251 #define TARGET_ADDRESS_COST arm_address_cost
253 #undef TARGET_SHIFT_TRUNCATION_MASK
254 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
255 #undef TARGET_VECTOR_MODE_SUPPORTED_P
256 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
258 #undef TARGET_MACHINE_DEPENDENT_REORG
259 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
261 #undef TARGET_INIT_BUILTINS
262 #define TARGET_INIT_BUILTINS arm_init_builtins
263 #undef TARGET_EXPAND_BUILTIN
264 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
266 #undef TARGET_INIT_LIBFUNCS
267 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
269 #undef TARGET_PROMOTE_FUNCTION_ARGS
270 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
271 #undef TARGET_PROMOTE_FUNCTION_RETURN
272 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
273 #undef TARGET_PROMOTE_PROTOTYPES
274 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
275 #undef TARGET_PASS_BY_REFERENCE
276 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
277 #undef TARGET_ARG_PARTIAL_BYTES
278 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
280 #undef TARGET_STRUCT_VALUE_RTX
281 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
283 #undef TARGET_SETUP_INCOMING_VARARGS
284 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
286 #undef TARGET_DEFAULT_SHORT_ENUMS
287 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
289 #undef TARGET_ALIGN_ANON_BITFIELD
290 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
292 #undef TARGET_CXX_GUARD_TYPE
293 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
295 #undef TARGET_CXX_GUARD_MASK_BIT
296 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
298 #undef TARGET_CXX_GET_COOKIE_SIZE
299 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
301 #undef TARGET_CXX_COOKIE_HAS_SIZE
302 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
304 #undef TARGET_CXX_CDTOR_RETURNS_THIS
305 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
307 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
308 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
310 #undef TARGET_CXX_EXPORT_CLASS_DATA
311 #define TARGET_CXX_EXPORT_CLASS_DATA arm_cxx_export_class_data
313 struct gcc_target targetm
= TARGET_INITIALIZER
;
315 /* Obstack for minipool constant handling. */
316 static struct obstack minipool_obstack
;
317 static char * minipool_startobj
;
319 /* The maximum number of insns skipped which
320 will be conditionalised if possible. */
321 static int max_insns_skipped
= 5;
323 extern FILE * asm_out_file
;
325 /* True if we are currently building a constant table. */
326 int making_const_table
;
328 /* Define the information needed to generate branch insns. This is
329 stored from the compare operation. */
330 rtx arm_compare_op0
, arm_compare_op1
;
332 /* The processor for which instructions should be scheduled. */
333 enum processor_type arm_tune
= arm_none
;
335 /* Which floating point model to use. */
336 enum arm_fp_model arm_fp_model
;
338 /* Which floating point hardware is available. */
339 enum fputype arm_fpu_arch
;
341 /* Which floating point hardware to schedule for. */
342 enum fputype arm_fpu_tune
;
344 /* Whether to use floating point hardware. */
345 enum float_abi_type arm_float_abi
;
347 /* Which ABI to use. */
348 enum arm_abi_type arm_abi
;
350 /* Set by the -mfpu=... option. */
351 const char * target_fpu_name
= NULL
;
353 /* Set by the -mfpe=... option. */
354 const char * target_fpe_name
= NULL
;
356 /* Set by the -mfloat-abi=... option. */
357 const char * target_float_abi_name
= NULL
;
359 /* Set by the legacy -mhard-float and -msoft-float options. */
360 const char * target_float_switch
= NULL
;
362 /* Set by the -mabi=... option. */
363 const char * target_abi_name
= NULL
;
365 /* Used to parse -mstructure_size_boundary command line option. */
366 const char * structure_size_string
= NULL
;
367 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
369 /* Used for Thumb call_via trampolines. */
370 rtx thumb_call_via_label
[14];
371 static int thumb_call_reg_needed
;
373 /* Bit values used to identify processor capabilities. */
374 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
375 #define FL_ARCH3M (1 << 1) /* Extended multiply */
376 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
377 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
378 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
379 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
380 #define FL_THUMB (1 << 6) /* Thumb aware */
381 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
382 #define FL_STRONG (1 << 8) /* StrongARM */
383 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
384 #define FL_XSCALE (1 << 10) /* XScale */
385 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
386 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
387 media instructions. */
388 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
389 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
390 Note: ARM6 & 7 derivatives only. */
392 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
394 #define FL_FOR_ARCH2 0
395 #define FL_FOR_ARCH3 FL_MODE32
396 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
397 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
398 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
399 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
400 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
401 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
402 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
403 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
404 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
405 #define FL_FOR_ARCH6J FL_FOR_ARCH6
406 #define FL_FOR_ARCH6K FL_FOR_ARCH6
407 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
408 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6
410 /* The bits in this mask specify which
411 instructions we are allowed to generate. */
412 static unsigned long insn_flags
= 0;
414 /* The bits in this mask specify which instruction scheduling options should
416 static unsigned long tune_flags
= 0;
418 /* The following are used in the arm.md file as equivalents to bits
419 in the above two flag variables. */
421 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
424 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
427 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
430 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
433 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
436 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
439 /* Nonzero if this chip can benefit from load scheduling. */
440 int arm_ld_sched
= 0;
442 /* Nonzero if this chip is a StrongARM. */
443 int arm_tune_strongarm
= 0;
445 /* Nonzero if this chip is a Cirrus variant. */
446 int arm_arch_cirrus
= 0;
448 /* Nonzero if this chip supports Intel Wireless MMX technology. */
449 int arm_arch_iwmmxt
= 0;
451 /* Nonzero if this chip is an XScale. */
452 int arm_arch_xscale
= 0;
454 /* Nonzero if tuning for XScale */
455 int arm_tune_xscale
= 0;
457 /* Nonzero if we want to tune for stores that access the write-buffer.
458 This typically means an ARM6 or ARM7 with MMU or MPU. */
459 int arm_tune_wbuf
= 0;
461 /* Nonzero if generating Thumb instructions. */
464 /* Nonzero if we should define __THUMB_INTERWORK__ in the
466 XXX This is a bit of a hack, it's intended to help work around
467 problems in GLD which doesn't understand that armv5t code is
468 interworking clean. */
469 int arm_cpp_interwork
= 0;
471 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
472 must report the mode of the memory reference from PRINT_OPERAND to
473 PRINT_OPERAND_ADDRESS. */
474 enum machine_mode output_memory_reference_mode
;
476 /* The register number to be used for the PIC offset register. */
477 const char * arm_pic_register_string
= NULL
;
478 int arm_pic_register
= INVALID_REGNUM
;
480 /* Set to 1 when a return insn is output, this means that the epilogue
482 int return_used_this_function
;
484 /* Set to 1 after arm_reorg has started. Reset to start at the start of
485 the next function. */
486 static int after_arm_reorg
= 0;
488 /* The maximum number of insns to be used when loading a constant. */
489 static int arm_constant_limit
= 3;
491 /* For an explanation of these variables, see final_prescan_insn below. */
493 enum arm_cond_code arm_current_cc
;
495 int arm_target_label
;
497 /* The condition codes of the ARM, and the inverse function. */
498 static const char * const arm_condition_codes
[] =
500 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
501 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
504 #define streq(string1, string2) (strcmp (string1, string2) == 0)
506 /* Initialization code. */
510 const char *const name
;
511 enum processor_type core
;
513 const unsigned long flags
;
514 bool (* rtx_costs
) (rtx
, int, int, int *);
517 /* Not all of these give usefully different compilation alternatives,
518 but there is no simple way of generalizing them. */
519 static const struct processors all_cores
[] =
522 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
523 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
524 #include "arm-cores.def"
526 {NULL
, arm_none
, NULL
, 0, NULL
}
529 static const struct processors all_architectures
[] =
531 /* ARM Architectures */
532 /* We don't specify rtx_costs here as it will be figured out
535 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
536 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
537 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
538 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
539 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
540 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
541 implementations that support it, so we will leave it out for now. */
542 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
543 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
544 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
545 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
546 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
547 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
548 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
549 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
550 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
551 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
552 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
553 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
554 {NULL
, arm_none
, NULL
, 0 , NULL
}
557 /* This is a magic structure. The 'string' field is magically filled in
558 with a pointer to the value specified by the user on the command line
559 assuming that the user has specified such a value. */
561 struct arm_cpu_select arm_select
[] =
563 /* string name processors */
564 { NULL
, "-mcpu=", all_cores
},
565 { NULL
, "-march=", all_architectures
},
566 { NULL
, "-mtune=", all_cores
}
570 /* The name of the proprocessor macro to define for this architecture. */
572 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
581 /* Available values for for -mfpu=. */
583 static const struct fpu_desc all_fpus
[] =
585 {"fpa", FPUTYPE_FPA
},
586 {"fpe2", FPUTYPE_FPA_EMU2
},
587 {"fpe3", FPUTYPE_FPA_EMU2
},
588 {"maverick", FPUTYPE_MAVERICK
},
593 /* Floating point models used by the different hardware.
594 See fputype in arm.h. */
596 static const enum fputype fp_model_for_fpu
[] =
598 /* No FP hardware. */
599 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
600 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
601 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
602 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
603 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
604 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
611 enum float_abi_type abi_type
;
615 /* Available values for -mfloat-abi=. */
617 static const struct float_abi all_float_abis
[] =
619 {"soft", ARM_FLOAT_ABI_SOFT
},
620 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
621 {"hard", ARM_FLOAT_ABI_HARD
}
628 enum arm_abi_type abi_type
;
632 /* Available values for -mabi=. */
634 static const struct abi_name arm_all_abis
[] =
636 {"apcs-gnu", ARM_ABI_APCS
},
637 {"atpcs", ARM_ABI_ATPCS
},
638 {"aapcs", ARM_ABI_AAPCS
},
639 {"iwmmxt", ARM_ABI_IWMMXT
}
642 /* Return the number of bits set in VALUE. */
644 bit_count (unsigned long value
)
646 unsigned long count
= 0;
651 value
&= value
- 1; /* Clear the least-significant set bit. */
657 /* Set up library functions unique to ARM. */
660 arm_init_libfuncs (void)
662 /* There are no special library functions unless we are using the
667 /* The functions below are described in Section 4 of the "Run-Time
668 ABI for the ARM architecture", Version 1.0. */
670 /* Double-precision floating-point arithmetic. Table 2. */
671 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
672 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
673 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
674 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
675 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
677 /* Double-precision comparisons. Table 3. */
678 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
679 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
680 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
681 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
682 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
683 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
684 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
686 /* Single-precision floating-point arithmetic. Table 4. */
687 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
688 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
689 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
690 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
691 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
693 /* Single-precision comparisons. Table 5. */
694 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
695 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
696 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
697 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
698 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
699 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
700 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
702 /* Floating-point to integer conversions. Table 6. */
703 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
704 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
705 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
706 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
707 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
708 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
709 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
710 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
712 /* Conversions between floating types. Table 7. */
713 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
714 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
716 /* Integer to floating-point conversions. Table 8. */
717 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
718 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
719 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
720 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
721 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
722 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
723 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
724 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
726 /* Long long. Table 9. */
727 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
728 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
729 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
730 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
731 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
732 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
733 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
734 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
736 /* Integer (32/32->32) division. \S 4.3.1. */
737 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
738 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
740 /* The divmod functions are designed so that they can be used for
741 plain division, even though they return both the quotient and the
742 remainder. The quotient is returned in the usual location (i.e.,
743 r0 for SImode, {r0, r1} for DImode), just as would be expected
744 for an ordinary division routine. Because the AAPCS calling
745 conventions specify that all of { r0, r1, r2, r3 } are
746 callee-saved registers, there is no need to tell the compiler
747 explicitly that those registers are clobbered by these
749 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
750 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
751 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idivmod");
752 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidivmod");
755 /* Fix up any incompatible options that the user has specified.
756 This has now turned into a maze. */
758 arm_override_options (void)
762 /* Set up the flags based on the cpu/architecture selected by the user. */
763 for (i
= ARRAY_SIZE (arm_select
); i
--;)
765 struct arm_cpu_select
* ptr
= arm_select
+ i
;
767 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
769 const struct processors
* sel
;
771 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
772 if (streq (ptr
->string
, sel
->name
))
774 /* Set the architecture define. */
776 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
778 /* Determine the processor core for which we should
779 tune code-generation. */
780 if (/* -mcpu= is a sensible default. */
782 /* If -march= is used, and -mcpu= has not been used,
783 assume that we should tune for a representative
784 CPU from that architecture. */
786 /* -mtune= overrides -mcpu= and -march=. */
788 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
792 /* If we have been given an architecture and a processor
793 make sure that they are compatible. We only generate
794 a warning though, and we prefer the CPU over the
796 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
797 warning ("switch -mcpu=%s conflicts with -march= switch",
800 insn_flags
= sel
->flags
;
806 if (sel
->name
== NULL
)
807 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
811 /* If the user did not specify a processor, choose one for them. */
814 const struct processors
* sel
;
816 enum processor_type cpu
;
818 cpu
= TARGET_CPU_DEFAULT
;
821 #ifdef SUBTARGET_CPU_DEFAULT
822 /* Use the subtarget default CPU if none was specified by
824 cpu
= SUBTARGET_CPU_DEFAULT
;
826 /* Default to ARM6. */
830 sel
= &all_cores
[cpu
];
832 insn_flags
= sel
->flags
;
834 /* Now check to see if the user has specified some command line
835 switch that require certain abilities from the cpu. */
838 if (TARGET_INTERWORK
|| TARGET_THUMB
)
840 sought
|= (FL_THUMB
| FL_MODE32
);
842 /* There are no ARM processors that support both APCS-26 and
843 interworking. Therefore we force FL_MODE26 to be removed
844 from insn_flags here (if it was set), so that the search
845 below will always be able to find a compatible processor. */
846 insn_flags
&= ~FL_MODE26
;
849 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
851 /* Try to locate a CPU type that supports all of the abilities
852 of the default CPU, plus the extra abilities requested by
854 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
855 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
858 if (sel
->name
== NULL
)
860 unsigned current_bit_count
= 0;
861 const struct processors
* best_fit
= NULL
;
863 /* Ideally we would like to issue an error message here
864 saying that it was not possible to find a CPU compatible
865 with the default CPU, but which also supports the command
866 line options specified by the programmer, and so they
867 ought to use the -mcpu=<name> command line option to
868 override the default CPU type.
870 If we cannot find a cpu that has both the
871 characteristics of the default cpu and the given
872 command line options we scan the array again looking
874 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
875 if ((sel
->flags
& sought
) == sought
)
879 count
= bit_count (sel
->flags
& insn_flags
);
881 if (count
>= current_bit_count
)
884 current_bit_count
= count
;
888 if (best_fit
== NULL
)
894 insn_flags
= sel
->flags
;
896 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
897 if (arm_tune
== arm_none
)
898 arm_tune
= (enum processor_type
) (sel
- all_cores
);
901 /* The processor for which we should tune should now have been
903 if (arm_tune
== arm_none
)
906 tune_flags
= all_cores
[(int)arm_tune
].flags
;
908 targetm
.rtx_costs
= arm_size_rtx_costs
;
910 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
912 /* Make sure that the processor choice does not conflict with any of the
913 other command line choices. */
914 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
916 warning ("target CPU does not support interworking" );
917 target_flags
&= ~ARM_FLAG_INTERWORK
;
920 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
922 warning ("target CPU does not support THUMB instructions");
923 target_flags
&= ~ARM_FLAG_THUMB
;
926 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
928 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
929 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
932 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
933 from here where no function is being compiled currently. */
934 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
936 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
938 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
939 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
941 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
942 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
944 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
946 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
947 target_flags
|= ARM_FLAG_APCS_FRAME
;
950 if (TARGET_POKE_FUNCTION_NAME
)
951 target_flags
|= ARM_FLAG_APCS_FRAME
;
953 if (TARGET_APCS_REENT
&& flag_pic
)
954 error ("-fpic and -mapcs-reent are incompatible");
956 if (TARGET_APCS_REENT
)
957 warning ("APCS reentrant code not supported. Ignored");
959 /* If this target is normally configured to use APCS frames, warn if they
960 are turned off and debugging is turned on. */
962 && write_symbols
!= NO_DEBUG
963 && !TARGET_APCS_FRAME
964 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
965 warning ("-g with -mno-apcs-frame may not give sensible debugging");
967 /* If stack checking is disabled, we can use r10 as the PIC register,
968 which keeps r9 available. */
970 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
972 if (TARGET_APCS_FLOAT
)
973 warning ("passing floating point arguments in fp regs not yet supported");
975 /* Initialize boolean versions of the flags, for use in the arm.md file. */
976 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
977 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
978 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
979 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
980 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
981 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
982 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
983 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
985 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
986 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
987 thumb_code
= (TARGET_ARM
== 0);
988 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
989 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
990 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
992 /* V5 code we generate is completely interworking capable, so we turn off
993 TARGET_INTERWORK here to avoid many tests later on. */
995 /* XXX However, we must pass the right pre-processor defines to CPP
996 or GLD can get confused. This is a hack. */
997 if (TARGET_INTERWORK
)
998 arm_cpp_interwork
= 1;
1001 target_flags
&= ~ARM_FLAG_INTERWORK
;
1003 if (target_abi_name
)
1005 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1007 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1009 arm_abi
= arm_all_abis
[i
].abi_type
;
1013 if (i
== ARRAY_SIZE (arm_all_abis
))
1014 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1017 arm_abi
= ARM_DEFAULT_ABI
;
1019 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1020 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1022 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1023 error ("iwmmxt abi requires an iwmmxt capable cpu");
1025 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1026 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1028 if (streq (target_fpe_name
, "2"))
1029 target_fpu_name
= "fpe2";
1030 else if (streq (target_fpe_name
, "3"))
1031 target_fpu_name
= "fpe3";
1033 error ("invalid floating point emulation option: -mfpe=%s",
1036 if (target_fpu_name
!= NULL
)
1038 /* The user specified a FPU. */
1039 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1041 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1043 arm_fpu_arch
= all_fpus
[i
].fpu
;
1044 arm_fpu_tune
= arm_fpu_arch
;
1045 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1049 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1050 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1054 #ifdef FPUTYPE_DEFAULT
1055 /* Use the default if it is specified for this platform. */
1056 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1057 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1059 /* Pick one based on CPU type. */
1060 /* ??? Some targets assume FPA is the default.
1061 if ((insn_flags & FL_VFP) != 0)
1062 arm_fpu_arch = FPUTYPE_VFP;
1065 if (arm_arch_cirrus
)
1066 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1068 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1070 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1071 arm_fpu_tune
= FPUTYPE_FPA
;
1073 arm_fpu_tune
= arm_fpu_arch
;
1074 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1075 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1079 if (target_float_abi_name
!= NULL
)
1081 /* The user specified a FP ABI. */
1082 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1084 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1086 arm_float_abi
= all_float_abis
[i
].abi_type
;
1090 if (i
== ARRAY_SIZE (all_float_abis
))
1091 error ("invalid floating point abi: -mfloat-abi=%s",
1092 target_float_abi_name
);
1094 else if (target_float_switch
)
1096 /* This is a bit of a hack to avoid needing target flags for these. */
1097 if (target_float_switch
[0] == 'h')
1098 arm_float_abi
= ARM_FLOAT_ABI_HARD
;
1100 arm_float_abi
= ARM_FLOAT_ABI_SOFT
;
1103 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1105 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1106 sorry ("-mfloat-abi=hard and VFP");
1108 /* If soft-float is specified then don't use FPU. */
1109 if (TARGET_SOFT_FLOAT
)
1110 arm_fpu_arch
= FPUTYPE_NONE
;
1112 /* For arm2/3 there is no need to do any scheduling if there is only
1113 a floating point emulator, or we are doing software floating-point. */
1114 if ((TARGET_SOFT_FLOAT
1115 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1116 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1117 && (tune_flags
& FL_MODE32
) == 0)
1118 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1120 /* Override the default structure alignment for AAPCS ABI. */
1121 if (arm_abi
== ARM_ABI_AAPCS
)
1122 arm_structure_size_boundary
= 8;
1124 if (structure_size_string
!= NULL
)
1126 int size
= strtol (structure_size_string
, NULL
, 0);
1128 if (size
== 8 || size
== 32
1129 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1130 arm_structure_size_boundary
= size
;
1132 warning ("structure size boundary can only be set to %s",
1133 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1136 if (arm_pic_register_string
!= NULL
)
1138 int pic_register
= decode_reg_name (arm_pic_register_string
);
1141 warning ("-mpic-register= is useless without -fpic");
1143 /* Prevent the user from choosing an obviously stupid PIC register. */
1144 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1145 || pic_register
== HARD_FRAME_POINTER_REGNUM
1146 || pic_register
== STACK_POINTER_REGNUM
1147 || pic_register
>= PC_REGNUM
)
1148 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1150 arm_pic_register
= pic_register
;
1153 if (TARGET_THUMB
&& flag_schedule_insns
)
1155 /* Don't warn since it's on by default in -O2. */
1156 flag_schedule_insns
= 0;
1161 /* There's some dispute as to whether this should be 1 or 2. However,
1162 experiments seem to show that in pathological cases a setting of
1163 1 degrades less severely than a setting of 2. This could change if
1164 other parts of the compiler change their behavior. */
1165 arm_constant_limit
= 1;
1167 /* If optimizing for size, bump the number of instructions that we
1168 are prepared to conditionally execute (even on a StrongARM). */
1169 max_insns_skipped
= 6;
1173 /* For processors with load scheduling, it never costs more than
1174 2 cycles to load a constant, and the load scheduler may well
1175 reduce that to 1. */
1177 arm_constant_limit
= 1;
1179 /* On XScale the longer latency of a load makes it more difficult
1180 to achieve a good schedule, so it's faster to synthesize
1181 constants that can be done in two insns. */
1182 if (arm_tune_xscale
)
1183 arm_constant_limit
= 2;
1185 /* StrongARM has early execution of branches, so a sequence
1186 that is worth skipping is shorter. */
1187 if (arm_tune_strongarm
)
1188 max_insns_skipped
= 3;
1191 /* Register global variables with the garbage collector. */
1192 arm_add_gc_roots ();
1196 arm_add_gc_roots (void)
1198 gcc_obstack_init(&minipool_obstack
);
1199 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1202 /* A table of known ARM exception types.
1203 For use with the interrupt function attribute. */
1207 const char *const arg
;
1208 const unsigned long return_value
;
1212 static const isr_attribute_arg isr_attribute_args
[] =
1214 { "IRQ", ARM_FT_ISR
},
1215 { "irq", ARM_FT_ISR
},
1216 { "FIQ", ARM_FT_FIQ
},
1217 { "fiq", ARM_FT_FIQ
},
1218 { "ABORT", ARM_FT_ISR
},
1219 { "abort", ARM_FT_ISR
},
1220 { "ABORT", ARM_FT_ISR
},
1221 { "abort", ARM_FT_ISR
},
1222 { "UNDEF", ARM_FT_EXCEPTION
},
1223 { "undef", ARM_FT_EXCEPTION
},
1224 { "SWI", ARM_FT_EXCEPTION
},
1225 { "swi", ARM_FT_EXCEPTION
},
1226 { NULL
, ARM_FT_NORMAL
}
1229 /* Returns the (interrupt) function type of the current
1230 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1232 static unsigned long
1233 arm_isr_value (tree argument
)
1235 const isr_attribute_arg
* ptr
;
1238 /* No argument - default to IRQ. */
1239 if (argument
== NULL_TREE
)
1242 /* Get the value of the argument. */
1243 if (TREE_VALUE (argument
) == NULL_TREE
1244 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1245 return ARM_FT_UNKNOWN
;
1247 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1249 /* Check it against the list of known arguments. */
1250 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1251 if (streq (arg
, ptr
->arg
))
1252 return ptr
->return_value
;
1254 /* An unrecognized interrupt type. */
1255 return ARM_FT_UNKNOWN
;
1258 /* Computes the type of the current function. */
1260 static unsigned long
1261 arm_compute_func_type (void)
1263 unsigned long type
= ARM_FT_UNKNOWN
;
1267 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
1270 /* Decide if the current function is volatile. Such functions
1271 never return, and many memory cycles can be saved by not storing
1272 register values that will never be needed again. This optimization
1273 was added to speed up context switching in a kernel application. */
1275 && TREE_NOTHROW (current_function_decl
)
1276 && TREE_THIS_VOLATILE (current_function_decl
))
1277 type
|= ARM_FT_VOLATILE
;
1279 if (cfun
->static_chain_decl
!= NULL
)
1280 type
|= ARM_FT_NESTED
;
1282 attr
= DECL_ATTRIBUTES (current_function_decl
);
1284 a
= lookup_attribute ("naked", attr
);
1286 type
|= ARM_FT_NAKED
;
1288 a
= lookup_attribute ("isr", attr
);
1290 a
= lookup_attribute ("interrupt", attr
);
1293 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1295 type
|= arm_isr_value (TREE_VALUE (a
));
1300 /* Returns the type of the current function. */
1303 arm_current_func_type (void)
1305 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1306 cfun
->machine
->func_type
= arm_compute_func_type ();
1308 return cfun
->machine
->func_type
;
1311 /* Return 1 if it is possible to return using a single instruction.
1312 If SIBLING is non-null, this is a test for a return before a sibling
1313 call. SIBLING is the call insn, so we can examine its register usage. */
1316 use_return_insn (int iscond
, rtx sibling
)
1319 unsigned int func_type
;
1320 unsigned long saved_int_regs
;
1321 unsigned HOST_WIDE_INT stack_adjust
;
1322 arm_stack_offsets
*offsets
;
1324 /* Never use a return instruction before reload has run. */
1325 if (!reload_completed
)
1328 func_type
= arm_current_func_type ();
1330 /* Naked functions and volatile functions need special
1332 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1335 /* So do interrupt functions that use the frame pointer. */
1336 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1339 offsets
= arm_get_frame_offsets ();
1340 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1342 /* As do variadic functions. */
1343 if (current_function_pretend_args_size
1344 || cfun
->machine
->uses_anonymous_args
1345 /* Or if the function calls __builtin_eh_return () */
1346 || current_function_calls_eh_return
1347 /* Or if the function calls alloca */
1348 || current_function_calls_alloca
1349 /* Or if there is a stack adjustment. However, if the stack pointer
1350 is saved on the stack, we can use a pre-incrementing stack load. */
1351 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1354 saved_int_regs
= arm_compute_save_reg_mask ();
1356 /* Unfortunately, the insn
1358 ldmib sp, {..., sp, ...}
1360 triggers a bug on most SA-110 based devices, such that the stack
1361 pointer won't be correctly restored if the instruction takes a
1362 page fault. We work around this problem by popping r3 along with
1363 the other registers, since that is never slower than executing
1364 another instruction.
1366 We test for !arm_arch5 here, because code for any architecture
1367 less than this could potentially be run on one of the buggy
1369 if (stack_adjust
== 4 && !arm_arch5
)
1371 /* Validate that r3 is a call-clobbered register (always true in
1372 the default abi) ... */
1373 if (!call_used_regs
[3])
1376 /* ... that it isn't being used for a return value (always true
1377 until we implement return-in-regs), or for a tail-call
1381 if (GET_CODE (sibling
) != CALL_INSN
)
1384 if (find_regno_fusage (sibling
, USE
, 3))
1388 /* ... and that there are no call-saved registers in r0-r2
1389 (always true in the default ABI). */
1390 if (saved_int_regs
& 0x7)
1394 /* Can't be done if interworking with Thumb, and any registers have been
1396 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1399 /* On StrongARM, conditional returns are expensive if they aren't
1400 taken and multiple registers have been stacked. */
1401 if (iscond
&& arm_tune_strongarm
)
1403 /* Conditional return when just the LR is stored is a simple
1404 conditional-load instruction, that's not expensive. */
1405 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1408 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1412 /* If there are saved registers but the LR isn't saved, then we need
1413 two instructions for the return. */
1414 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1417 /* Can't be done if any of the FPA regs are pushed,
1418 since this also requires an insn. */
1419 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1420 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1421 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1424 /* Likewise VFP regs. */
1425 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1426 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1427 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1430 if (TARGET_REALLY_IWMMXT
)
1431 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1432 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1438 /* Return TRUE if int I is a valid immediate ARM constant. */
1441 const_ok_for_arm (HOST_WIDE_INT i
)
1443 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1445 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1446 be all zero, or all one. */
1447 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1448 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1449 != ((~(unsigned HOST_WIDE_INT
) 0)
1450 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1453 /* Fast return for 0 and powers of 2 */
1454 if ((i
& (i
- 1)) == 0)
1459 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1462 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1463 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1465 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1470 /* Return true if I is a valid constant for the operation CODE. */
1472 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1474 if (const_ok_for_arm (i
))
1480 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1482 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1488 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1495 /* Emit a sequence of insns to handle a large constant.
1496 CODE is the code of the operation required, it can be any of SET, PLUS,
1497 IOR, AND, XOR, MINUS;
1498 MODE is the mode in which the operation is being performed;
1499 VAL is the integer to operate on;
1500 SOURCE is the other operand (a register, or a null-pointer for SET);
1501 SUBTARGETS means it is safe to create scratch registers if that will
1502 either produce a simpler sequence, or we will want to cse the values.
1503 Return value is the number of insns emitted. */
1506 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1507 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1511 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1512 cond
= COND_EXEC_TEST (PATTERN (insn
));
1516 if (subtargets
|| code
== SET
1517 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1518 && REGNO (target
) != REGNO (source
)))
1520 /* After arm_reorg has been called, we can't fix up expensive
1521 constants by pushing them into memory so we must synthesize
1522 them in-line, regardless of the cost. This is only likely to
1523 be more costly on chips that have load delay slots and we are
1524 compiling without running the scheduler (so no splitting
1525 occurred before the final instruction emission).
1527 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1529 if (!after_arm_reorg
1531 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1533 > arm_constant_limit
+ (code
!= SET
)))
1537 /* Currently SET is the only monadic value for CODE, all
1538 the rest are diadic. */
1539 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1544 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1546 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1547 /* For MINUS, the value is subtracted from, since we never
1548 have subtraction of a constant. */
1550 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1551 gen_rtx_MINUS (mode
, temp
, source
)));
1553 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1554 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1560 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1565 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1567 HOST_WIDE_INT temp1
;
1575 if (remainder
& (3 << (i
- 2)))
1580 temp1
= remainder
& ((0x0ff << end
)
1581 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1582 remainder
&= ~temp1
;
1587 } while (remainder
);
1591 /* Emit an instruction with the indicated PATTERN. If COND is
1592 non-NULL, conditionalize the execution of the instruction on COND
1596 emit_constant_insn (rtx cond
, rtx pattern
)
1599 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1600 emit_insn (pattern
);
1603 /* As above, but extra parameter GENERATE which, if clear, suppresses
1607 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1608 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1613 int can_negate_initial
= 0;
1616 int num_bits_set
= 0;
1617 int set_sign_bit_copies
= 0;
1618 int clear_sign_bit_copies
= 0;
1619 int clear_zero_bit_copies
= 0;
1620 int set_zero_bit_copies
= 0;
1622 unsigned HOST_WIDE_INT temp1
, temp2
;
1623 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1625 /* Find out which operations are safe for a given CODE. Also do a quick
1626 check for degenerate cases; these can occur when DImode operations
1638 can_negate_initial
= 1;
1642 if (remainder
== 0xffffffff)
1645 emit_constant_insn (cond
,
1646 gen_rtx_SET (VOIDmode
, target
,
1647 GEN_INT (ARM_SIGN_EXTEND (val
))));
1652 if (reload_completed
&& rtx_equal_p (target
, source
))
1655 emit_constant_insn (cond
,
1656 gen_rtx_SET (VOIDmode
, target
, source
));
1665 emit_constant_insn (cond
,
1666 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1669 if (remainder
== 0xffffffff)
1671 if (reload_completed
&& rtx_equal_p (target
, source
))
1674 emit_constant_insn (cond
,
1675 gen_rtx_SET (VOIDmode
, target
, source
));
1684 if (reload_completed
&& rtx_equal_p (target
, source
))
1687 emit_constant_insn (cond
,
1688 gen_rtx_SET (VOIDmode
, target
, source
));
1691 if (remainder
== 0xffffffff)
1694 emit_constant_insn (cond
,
1695 gen_rtx_SET (VOIDmode
, target
,
1696 gen_rtx_NOT (mode
, source
)));
1700 /* We don't know how to handle this yet below. */
1704 /* We treat MINUS as (val - source), since (source - val) is always
1705 passed as (source + (-val)). */
1709 emit_constant_insn (cond
,
1710 gen_rtx_SET (VOIDmode
, target
,
1711 gen_rtx_NEG (mode
, source
)));
1714 if (const_ok_for_arm (val
))
1717 emit_constant_insn (cond
,
1718 gen_rtx_SET (VOIDmode
, target
,
1719 gen_rtx_MINUS (mode
, GEN_INT (val
),
1731 /* If we can do it in one insn get out quickly. */
1732 if (const_ok_for_arm (val
)
1733 || (can_negate_initial
&& const_ok_for_arm (-val
))
1734 || (can_invert
&& const_ok_for_arm (~val
)))
1737 emit_constant_insn (cond
,
1738 gen_rtx_SET (VOIDmode
, target
,
1740 ? gen_rtx_fmt_ee (code
, mode
, source
,
1746 /* Calculate a few attributes that may be useful for specific
1748 for (i
= 31; i
>= 0; i
--)
1750 if ((remainder
& (1 << i
)) == 0)
1751 clear_sign_bit_copies
++;
1756 for (i
= 31; i
>= 0; i
--)
1758 if ((remainder
& (1 << i
)) != 0)
1759 set_sign_bit_copies
++;
1764 for (i
= 0; i
<= 31; i
++)
1766 if ((remainder
& (1 << i
)) == 0)
1767 clear_zero_bit_copies
++;
1772 for (i
= 0; i
<= 31; i
++)
1774 if ((remainder
& (1 << i
)) != 0)
1775 set_zero_bit_copies
++;
1783 /* See if we can do this by sign_extending a constant that is known
1784 to be negative. This is a good, way of doing it, since the shift
1785 may well merge into a subsequent insn. */
1786 if (set_sign_bit_copies
> 1)
1788 if (const_ok_for_arm
1789 (temp1
= ARM_SIGN_EXTEND (remainder
1790 << (set_sign_bit_copies
- 1))))
1794 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1795 emit_constant_insn (cond
,
1796 gen_rtx_SET (VOIDmode
, new_src
,
1798 emit_constant_insn (cond
,
1799 gen_ashrsi3 (target
, new_src
,
1800 GEN_INT (set_sign_bit_copies
- 1)));
1804 /* For an inverted constant, we will need to set the low bits,
1805 these will be shifted out of harm's way. */
1806 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1807 if (const_ok_for_arm (~temp1
))
1811 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1812 emit_constant_insn (cond
,
1813 gen_rtx_SET (VOIDmode
, new_src
,
1815 emit_constant_insn (cond
,
1816 gen_ashrsi3 (target
, new_src
,
1817 GEN_INT (set_sign_bit_copies
- 1)));
1823 /* See if we can generate this by setting the bottom (or the top)
1824 16 bits, and then shifting these into the other half of the
1825 word. We only look for the simplest cases, to do more would cost
1826 too much. Be careful, however, not to generate this when the
1827 alternative would take fewer insns. */
1828 if (val
& 0xffff0000)
1830 temp1
= remainder
& 0xffff0000;
1831 temp2
= remainder
& 0x0000ffff;
1833 /* Overlaps outside this range are best done using other methods. */
1834 for (i
= 9; i
< 24; i
++)
1836 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1837 && !const_ok_for_arm (temp2
))
1839 rtx new_src
= (subtargets
1840 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1842 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
1843 source
, subtargets
, generate
);
1851 gen_rtx_ASHIFT (mode
, source
,
1858 /* Don't duplicate cases already considered. */
1859 for (i
= 17; i
< 24; i
++)
1861 if (((temp1
| (temp1
>> i
)) == remainder
)
1862 && !const_ok_for_arm (temp1
))
1864 rtx new_src
= (subtargets
1865 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1867 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
1868 source
, subtargets
, generate
);
1873 gen_rtx_SET (VOIDmode
, target
,
1876 gen_rtx_LSHIFTRT (mode
, source
,
1887 /* If we have IOR or XOR, and the constant can be loaded in a
1888 single instruction, and we can find a temporary to put it in,
1889 then this can be done in two instructions instead of 3-4. */
1891 /* TARGET can't be NULL if SUBTARGETS is 0 */
1892 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1894 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1898 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1900 emit_constant_insn (cond
,
1901 gen_rtx_SET (VOIDmode
, sub
,
1903 emit_constant_insn (cond
,
1904 gen_rtx_SET (VOIDmode
, target
,
1905 gen_rtx_fmt_ee (code
, mode
,
1915 if (set_sign_bit_copies
> 8
1916 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1920 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1921 rtx shift
= GEN_INT (set_sign_bit_copies
);
1925 gen_rtx_SET (VOIDmode
, sub
,
1927 gen_rtx_ASHIFT (mode
,
1932 gen_rtx_SET (VOIDmode
, target
,
1934 gen_rtx_LSHIFTRT (mode
, sub
,
1940 if (set_zero_bit_copies
> 8
1941 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1945 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1946 rtx shift
= GEN_INT (set_zero_bit_copies
);
1950 gen_rtx_SET (VOIDmode
, sub
,
1952 gen_rtx_LSHIFTRT (mode
,
1957 gen_rtx_SET (VOIDmode
, target
,
1959 gen_rtx_ASHIFT (mode
, sub
,
1965 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1969 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1970 emit_constant_insn (cond
,
1971 gen_rtx_SET (VOIDmode
, sub
,
1972 gen_rtx_NOT (mode
, source
)));
1975 sub
= gen_reg_rtx (mode
);
1976 emit_constant_insn (cond
,
1977 gen_rtx_SET (VOIDmode
, sub
,
1978 gen_rtx_AND (mode
, source
,
1980 emit_constant_insn (cond
,
1981 gen_rtx_SET (VOIDmode
, target
,
1982 gen_rtx_NOT (mode
, sub
)));
1989 /* See if two shifts will do 2 or more insn's worth of work. */
1990 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1992 HOST_WIDE_INT shift_mask
= ((0xffffffff
1993 << (32 - clear_sign_bit_copies
))
1996 if ((remainder
| shift_mask
) != 0xffffffff)
2000 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2001 insns
= arm_gen_constant (AND
, mode
, cond
,
2002 remainder
| shift_mask
,
2003 new_src
, source
, subtargets
, 1);
2008 rtx targ
= subtargets
? NULL_RTX
: target
;
2009 insns
= arm_gen_constant (AND
, mode
, cond
,
2010 remainder
| shift_mask
,
2011 targ
, source
, subtargets
, 0);
2017 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2018 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2020 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2021 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2027 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2029 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2031 if ((remainder
| shift_mask
) != 0xffffffff)
2035 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2037 insns
= arm_gen_constant (AND
, mode
, cond
,
2038 remainder
| shift_mask
,
2039 new_src
, source
, subtargets
, 1);
2044 rtx targ
= subtargets
? NULL_RTX
: target
;
2046 insns
= arm_gen_constant (AND
, mode
, cond
,
2047 remainder
| shift_mask
,
2048 targ
, source
, subtargets
, 0);
2054 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2055 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2057 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2058 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2070 for (i
= 0; i
< 32; i
++)
2071 if (remainder
& (1 << i
))
2074 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2075 remainder
= (~remainder
) & 0xffffffff;
2076 else if (code
== PLUS
&& num_bits_set
> 16)
2077 remainder
= (-remainder
) & 0xffffffff;
2084 /* Now try and find a way of doing the job in either two or three
2086 We start by looking for the largest block of zeros that are aligned on
2087 a 2-bit boundary, we then fill up the temps, wrapping around to the
2088 top of the word when we drop off the bottom.
2089 In the worst case this code should produce no more than four insns. */
2092 int best_consecutive_zeros
= 0;
2094 for (i
= 0; i
< 32; i
+= 2)
2096 int consecutive_zeros
= 0;
2098 if (!(remainder
& (3 << i
)))
2100 while ((i
< 32) && !(remainder
& (3 << i
)))
2102 consecutive_zeros
+= 2;
2105 if (consecutive_zeros
> best_consecutive_zeros
)
2107 best_consecutive_zeros
= consecutive_zeros
;
2108 best_start
= i
- consecutive_zeros
;
2114 /* So long as it won't require any more insns to do so, it's
2115 desirable to emit a small constant (in bits 0...9) in the last
2116 insn. This way there is more chance that it can be combined with
2117 a later addressing insn to form a pre-indexed load or store
2118 operation. Consider:
2120 *((volatile int *)0xe0000100) = 1;
2121 *((volatile int *)0xe0000110) = 2;
2123 We want this to wind up as:
2127 str rB, [rA, #0x100]
2129 str rB, [rA, #0x110]
2131 rather than having to synthesize both large constants from scratch.
2133 Therefore, we calculate how many insns would be required to emit
2134 the constant starting from `best_start', and also starting from
2135 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2136 yield a shorter sequence, we may as well use zero. */
2138 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2139 && (count_insns_for_constant (remainder
, 0) <=
2140 count_insns_for_constant (remainder
, best_start
)))
2143 /* Now start emitting the insns. */
2151 if (remainder
& (3 << (i
- 2)))
2156 temp1
= remainder
& ((0x0ff << end
)
2157 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2158 remainder
&= ~temp1
;
2162 rtx new_src
, temp1_rtx
;
2164 if (code
== SET
|| code
== MINUS
)
2166 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2167 if (can_invert
&& code
!= MINUS
)
2172 if (remainder
&& subtargets
)
2173 new_src
= gen_reg_rtx (mode
);
2178 else if (can_negate
)
2182 temp1
= trunc_int_for_mode (temp1
, mode
);
2183 temp1_rtx
= GEN_INT (temp1
);
2187 else if (code
== MINUS
)
2188 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2190 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2192 emit_constant_insn (cond
,
2193 gen_rtx_SET (VOIDmode
, new_src
,
2203 else if (code
== MINUS
)
2217 /* Canonicalize a comparison so that we are more likely to recognize it.
2218 This can be done for a few constant compares, where we can make the
2219 immediate value easier to load. */
2222 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
2224 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2234 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
2235 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2237 *op1
= GEN_INT (i
+ 1);
2238 return code
== GT
? GE
: LT
;
2244 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
2245 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2247 *op1
= GEN_INT (i
- 1);
2248 return code
== GE
? GT
: LE
;
2254 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2255 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2257 *op1
= GEN_INT (i
+ 1);
2258 return code
== GTU
? GEU
: LTU
;
2265 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2267 *op1
= GEN_INT (i
- 1);
2268 return code
== GEU
? GTU
: LEU
;
2280 /* Define how to find the value returned by a function. */
2283 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2285 enum machine_mode mode
;
2286 int unsignedp ATTRIBUTE_UNUSED
;
2287 rtx r ATTRIBUTE_UNUSED
;
2290 mode
= TYPE_MODE (type
);
2291 /* Promote integer types. */
2292 if (INTEGRAL_TYPE_P (type
))
2293 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2294 return LIBCALL_VALUE(mode
);
2297 /* Determine the amount of memory needed to store the possible return
2298 registers of an untyped call. */
2300 arm_apply_result_size (void)
2306 if (TARGET_HARD_FLOAT_ABI
)
2310 if (TARGET_MAVERICK
)
2313 if (TARGET_IWMMXT_ABI
)
2320 /* Decide whether a type should be returned in memory (true)
2321 or in a register (false). This is called by the macro
2322 RETURN_IN_MEMORY. */
2324 arm_return_in_memory (tree type
)
2328 if (!AGGREGATE_TYPE_P (type
) &&
2329 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2330 /* All simple types are returned in registers.
2331 For AAPCS, complex types are treated the same as aggregates. */
2334 size
= int_size_in_bytes (type
);
2336 if (arm_abi
!= ARM_ABI_APCS
)
2338 /* ATPCS and later return aggregate types in memory only if they are
2339 larger than a word (or are variable size). */
2340 return (size
< 0 || size
> UNITS_PER_WORD
);
2343 /* For the arm-wince targets we choose to be compatible with Microsoft's
2344 ARM and Thumb compilers, which always return aggregates in memory. */
2346 /* All structures/unions bigger than one word are returned in memory.
2347 Also catch the case where int_size_in_bytes returns -1. In this case
2348 the aggregate is either huge or of variable size, and in either case
2349 we will want to return it via memory and not in a register. */
2350 if (size
< 0 || size
> UNITS_PER_WORD
)
2353 if (TREE_CODE (type
) == RECORD_TYPE
)
2357 /* For a struct the APCS says that we only return in a register
2358 if the type is 'integer like' and every addressable element
2359 has an offset of zero. For practical purposes this means
2360 that the structure can have at most one non bit-field element
2361 and that this element must be the first one in the structure. */
2363 /* Find the first field, ignoring non FIELD_DECL things which will
2364 have been created by C++. */
2365 for (field
= TYPE_FIELDS (type
);
2366 field
&& TREE_CODE (field
) != FIELD_DECL
;
2367 field
= TREE_CHAIN (field
))
2371 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2373 /* Check that the first field is valid for returning in a register. */
2375 /* ... Floats are not allowed */
2376 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2379 /* ... Aggregates that are not themselves valid for returning in
2380 a register are not allowed. */
2381 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2384 /* Now check the remaining fields, if any. Only bitfields are allowed,
2385 since they are not addressable. */
2386 for (field
= TREE_CHAIN (field
);
2388 field
= TREE_CHAIN (field
))
2390 if (TREE_CODE (field
) != FIELD_DECL
)
2393 if (!DECL_BIT_FIELD_TYPE (field
))
2400 if (TREE_CODE (type
) == UNION_TYPE
)
2404 /* Unions can be returned in registers if every element is
2405 integral, or can be returned in an integer register. */
2406 for (field
= TYPE_FIELDS (type
);
2408 field
= TREE_CHAIN (field
))
2410 if (TREE_CODE (field
) != FIELD_DECL
)
2413 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2416 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2422 #endif /* not ARM_WINCE */
2424 /* Return all other types in memory. */
2428 /* Indicate whether or not words of a double are in big-endian order. */
2431 arm_float_words_big_endian (void)
2433 if (TARGET_MAVERICK
)
2436 /* For FPA, float words are always big-endian. For VFP, floats words
2437 follow the memory system mode. */
2445 return (TARGET_BIG_END
? 1 : 0);
2450 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2451 for a call to a function whose data type is FNTYPE.
2452 For a library call, FNTYPE is NULL. */
2454 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2455 rtx libname ATTRIBUTE_UNUSED
,
2456 tree fndecl ATTRIBUTE_UNUSED
)
2458 /* On the ARM, the offset starts at 0. */
2459 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2460 pcum
->iwmmxt_nregs
= 0;
2461 pcum
->can_split
= true;
2463 pcum
->call_cookie
= CALL_NORMAL
;
2465 if (TARGET_LONG_CALLS
)
2466 pcum
->call_cookie
= CALL_LONG
;
2468 /* Check for long call/short call attributes. The attributes
2469 override any command line option. */
2472 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2473 pcum
->call_cookie
= CALL_SHORT
;
2474 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2475 pcum
->call_cookie
= CALL_LONG
;
2478 /* Varargs vectors are treated the same as long long.
2479 named_count avoids having to change the way arm handles 'named' */
2480 pcum
->named_count
= 0;
2483 if (TARGET_REALLY_IWMMXT
&& fntype
)
2487 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2489 fn_arg
= TREE_CHAIN (fn_arg
))
2490 pcum
->named_count
+= 1;
2492 if (! pcum
->named_count
)
2493 pcum
->named_count
= INT_MAX
;
2498 /* Return true if mode/type need doubleword alignment. */
2500 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2502 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2503 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2507 /* Determine where to put an argument to a function.
2508 Value is zero to push the argument on the stack,
2509 or a hard register in which to store the argument.
2511 MODE is the argument's machine mode.
2512 TYPE is the data type of the argument (as a tree).
2513 This is null for libcalls where that information may
2515 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2516 the preceding args and about the function being called.
2517 NAMED is nonzero if this argument is a named parameter
2518 (otherwise it is an extra parameter matching an ellipsis). */
2521 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2522 tree type
, int named
)
2526 /* Varargs vectors are treated the same as long long.
2527 named_count avoids having to change the way arm handles 'named' */
2528 if (TARGET_IWMMXT_ABI
2529 && arm_vector_mode_supported_p (mode
)
2530 && pcum
->named_count
> pcum
->nargs
+ 1)
2532 if (pcum
->iwmmxt_nregs
<= 9)
2533 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2536 pcum
->can_split
= false;
2541 /* Put doubleword aligned quantities in even register pairs. */
2543 && ARM_DOUBLEWORD_ALIGN
2544 && arm_needs_doubleword_align (mode
, type
))
2547 if (mode
== VOIDmode
)
2548 /* Compute operand 2 of the call insn. */
2549 return GEN_INT (pcum
->call_cookie
);
2551 /* Only allow splitting an arg between regs and memory if all preceding
2552 args were allocated to regs. For args passed by reference we only count
2553 the reference pointer. */
2554 if (pcum
->can_split
)
2557 nregs
= ARM_NUM_REGS2 (mode
, type
);
2559 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2562 return gen_rtx_REG (mode
, pcum
->nregs
);
2566 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2567 tree type
, bool named ATTRIBUTE_UNUSED
)
2569 int nregs
= pcum
->nregs
;
2571 if (arm_vector_mode_supported_p (mode
))
2574 if (NUM_ARG_REGS
> nregs
2575 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2577 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2582 /* Variable sized types are passed by reference. This is a GCC
2583 extension to the ARM ABI. */
2586 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2587 enum machine_mode mode ATTRIBUTE_UNUSED
,
2588 tree type
, bool named ATTRIBUTE_UNUSED
)
2590 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2593 /* Encode the current state of the #pragma [no_]long_calls. */
2596 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2597 LONG
, /* #pragma long_calls is in effect. */
2598 SHORT
/* #pragma no_long_calls is in effect. */
2601 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2604 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2606 arm_pragma_long_calls
= LONG
;
2610 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2612 arm_pragma_long_calls
= SHORT
;
2616 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2618 arm_pragma_long_calls
= OFF
;
2621 /* Table of machine attributes. */
2622 const struct attribute_spec arm_attribute_table
[] =
2624 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2625 /* Function calls made to this symbol must be done indirectly, because
2626 it may lie outside of the 26 bit addressing range of a normal function
2628 { "long_call", 0, 0, false, true, true, NULL
},
2629 /* Whereas these functions are always known to reside within the 26 bit
2630 addressing range. */
2631 { "short_call", 0, 0, false, true, true, NULL
},
2632 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2633 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2634 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2635 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2637 /* ARM/PE has three new attributes:
2639 dllexport - for exporting a function/variable that will live in a dll
2640 dllimport - for importing a function/variable from a dll
2642 Microsoft allows multiple declspecs in one __declspec, separating
2643 them with spaces. We do NOT support this. Instead, use __declspec
2646 { "dllimport", 0, 0, true, false, false, NULL
},
2647 { "dllexport", 0, 0, true, false, false, NULL
},
2648 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2649 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2650 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2651 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2652 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2654 { NULL
, 0, 0, false, false, false, NULL
}
2657 /* Handle an attribute requiring a FUNCTION_DECL;
2658 arguments as in struct attribute_spec.handler. */
2660 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2661 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2663 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2665 warning ("%qs attribute only applies to functions",
2666 IDENTIFIER_POINTER (name
));
2667 *no_add_attrs
= true;
2673 /* Handle an "interrupt" or "isr" attribute;
2674 arguments as in struct attribute_spec.handler. */
2676 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2681 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2683 warning ("%qs attribute only applies to functions",
2684 IDENTIFIER_POINTER (name
));
2685 *no_add_attrs
= true;
2687 /* FIXME: the argument if any is checked for type attributes;
2688 should it be checked for decl ones? */
2692 if (TREE_CODE (*node
) == FUNCTION_TYPE
2693 || TREE_CODE (*node
) == METHOD_TYPE
)
2695 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2697 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
2698 *no_add_attrs
= true;
2701 else if (TREE_CODE (*node
) == POINTER_TYPE
2702 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2703 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2704 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2706 *node
= build_variant_type_copy (*node
);
2707 TREE_TYPE (*node
) = build_type_attribute_variant
2709 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2710 *no_add_attrs
= true;
2714 /* Possibly pass this attribute on from the type to a decl. */
2715 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2716 | (int) ATTR_FLAG_FUNCTION_NEXT
2717 | (int) ATTR_FLAG_ARRAY_NEXT
))
2719 *no_add_attrs
= true;
2720 return tree_cons (name
, args
, NULL_TREE
);
2724 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
2732 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2733 /* Handle the "notshared" attribute. This attribute is another way of
2734 requesting hidden visibility. ARM's compiler supports
2735 "__declspec(notshared)"; we support the same thing via an
2739 arm_handle_notshared_attribute (tree
*node
,
2740 tree name ATTRIBUTE_UNUSED
,
2741 tree args ATTRIBUTE_UNUSED
,
2742 int flags ATTRIBUTE_UNUSED
,
2745 tree decl
= TYPE_NAME (*node
);
2749 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2750 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2751 *no_add_attrs
= false;
2757 /* Return 0 if the attributes for two types are incompatible, 1 if they
2758 are compatible, and 2 if they are nearly compatible (which causes a
2759 warning to be generated). */
2761 arm_comp_type_attributes (tree type1
, tree type2
)
2765 /* Check for mismatch of non-default calling convention. */
2766 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2769 /* Check for mismatched call attributes. */
2770 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2771 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2772 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2773 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2775 /* Only bother to check if an attribute is defined. */
2776 if (l1
| l2
| s1
| s2
)
2778 /* If one type has an attribute, the other must have the same attribute. */
2779 if ((l1
!= l2
) || (s1
!= s2
))
2782 /* Disallow mixed attributes. */
2783 if ((l1
& s2
) || (l2
& s1
))
2787 /* Check for mismatched ISR attribute. */
2788 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2790 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2791 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2793 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2800 /* Encode long_call or short_call attribute by prefixing
2801 symbol name in DECL with a special character FLAG. */
2803 arm_encode_call_attribute (tree decl
, int flag
)
2805 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2806 int len
= strlen (str
);
2809 /* Do not allow weak functions to be treated as short call. */
2810 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2813 newstr
= alloca (len
+ 2);
2815 strcpy (newstr
+ 1, str
);
2817 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2818 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2821 /* Assigns default attributes to newly defined type. This is used to
2822 set short_call/long_call attributes for function types of
2823 functions defined inside corresponding #pragma scopes. */
2825 arm_set_default_type_attributes (tree type
)
2827 /* Add __attribute__ ((long_call)) to all functions, when
2828 inside #pragma long_calls or __attribute__ ((short_call)),
2829 when inside #pragma no_long_calls. */
2830 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2832 tree type_attr_list
, attr_name
;
2833 type_attr_list
= TYPE_ATTRIBUTES (type
);
2835 if (arm_pragma_long_calls
== LONG
)
2836 attr_name
= get_identifier ("long_call");
2837 else if (arm_pragma_long_calls
== SHORT
)
2838 attr_name
= get_identifier ("short_call");
2842 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2843 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2847 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2848 defined within the current compilation unit. If this cannot be
2849 determined, then 0 is returned. */
2851 current_file_function_operand (rtx sym_ref
)
2853 /* This is a bit of a fib. A function will have a short call flag
2854 applied to its name if it has the short call attribute, or it has
2855 already been defined within the current compilation unit. */
2856 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2859 /* The current function is always defined within the current compilation
2860 unit. If it s a weak definition however, then this may not be the real
2861 definition of the function, and so we have to say no. */
2862 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2863 && !DECL_WEAK (current_function_decl
))
2866 /* We cannot make the determination - default to returning 0. */
2870 /* Return nonzero if a 32 bit "long_call" should be generated for
2871 this call. We generate a long_call if the function:
2873 a. has an __attribute__((long call))
2874 or b. is within the scope of a #pragma long_calls
2875 or c. the -mlong-calls command line switch has been specified
2877 1. -ffunction-sections is in effect
2878 or 2. the current function has __attribute__ ((section))
2879 or 3. the target function has __attribute__ ((section))
2881 However we do not generate a long call if the function:
2883 d. has an __attribute__ ((short_call))
2884 or e. is inside the scope of a #pragma no_long_calls
2885 or f. is defined within the current compilation unit.
2887 This function will be called by C fragments contained in the machine
2888 description file. SYM_REF and CALL_COOKIE correspond to the matched
2889 rtl operands. CALL_SYMBOL is used to distinguish between
2890 two different callers of the function. It is set to 1 in the
2891 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2892 and "call_value" patterns. This is because of the difference in the
2893 SYM_REFs passed by these patterns. */
2895 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2899 if (GET_CODE (sym_ref
) != MEM
)
2902 sym_ref
= XEXP (sym_ref
, 0);
2905 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2908 if (call_cookie
& CALL_SHORT
)
2911 if (TARGET_LONG_CALLS
)
2913 if (flag_function_sections
2914 || DECL_SECTION_NAME (current_function_decl
))
2915 /* c.3 is handled by the definition of the
2916 ARM_DECLARE_FUNCTION_SIZE macro. */
2920 if (current_file_function_operand (sym_ref
))
2923 return (call_cookie
& CALL_LONG
)
2924 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2925 || TARGET_LONG_CALLS
;
2928 /* Return nonzero if it is ok to make a tail-call to DECL. */
2930 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2932 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2934 if (cfun
->machine
->sibcall_blocked
)
2937 /* Never tailcall something for which we have no decl, or if we
2938 are in Thumb mode. */
2939 if (decl
== NULL
|| TARGET_THUMB
)
2942 /* Get the calling method. */
2943 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2944 call_type
= CALL_SHORT
;
2945 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2946 call_type
= CALL_LONG
;
2948 /* Cannot tail-call to long calls, since these are out of range of
2949 a branch instruction. However, if not compiling PIC, we know
2950 we can reach the symbol if it is in this compilation unit. */
2951 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2954 /* If we are interworking and the function is not declared static
2955 then we can't tail-call it unless we know that it exists in this
2956 compilation unit (since it might be a Thumb routine). */
2957 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2960 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2961 if (IS_INTERRUPT (arm_current_func_type ()))
2964 /* Everything else is ok. */
2969 /* Addressing mode support functions. */
2971 /* Return nonzero if X is a legitimate immediate operand when compiling
2974 legitimate_pic_operand_p (rtx x
)
2978 && (GET_CODE (x
) == SYMBOL_REF
2979 || (GET_CODE (x
) == CONST
2980 && GET_CODE (XEXP (x
, 0)) == PLUS
2981 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2988 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2990 if (GET_CODE (orig
) == SYMBOL_REF
2991 || GET_CODE (orig
) == LABEL_REF
)
2993 #ifndef AOF_ASSEMBLER
2994 rtx pic_ref
, address
;
3004 reg
= gen_reg_rtx (Pmode
);
3009 #ifdef AOF_ASSEMBLER
3010 /* The AOF assembler can generate relocations for these directly, and
3011 understands that the PIC register has to be added into the offset. */
3012 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3015 address
= gen_reg_rtx (Pmode
);
3020 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3022 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3024 if ((GET_CODE (orig
) == LABEL_REF
3025 || (GET_CODE (orig
) == SYMBOL_REF
&&
3026 SYMBOL_REF_LOCAL_P (orig
)))
3028 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
3031 pic_ref
= gen_const_mem (Pmode
,
3032 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3036 insn
= emit_move_insn (reg
, pic_ref
);
3038 current_function_uses_pic_offset_table
= 1;
3039 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3041 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3045 else if (GET_CODE (orig
) == CONST
)
3049 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3050 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3058 reg
= gen_reg_rtx (Pmode
);
3061 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
3063 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3064 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3065 base
== reg
? 0 : reg
);
3070 if (GET_CODE (offset
) == CONST_INT
)
3072 /* The base register doesn't really matter, we only want to
3073 test the index for the appropriate mode. */
3074 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3076 if (!no_new_pseudos
)
3077 offset
= force_reg (Pmode
, offset
);
3082 if (GET_CODE (offset
) == CONST_INT
)
3083 return plus_constant (base
, INTVAL (offset
));
3086 if (GET_MODE_SIZE (mode
) > 4
3087 && (GET_MODE_CLASS (mode
) == MODE_INT
3088 || TARGET_SOFT_FLOAT
))
3090 emit_insn (gen_addsi3 (reg
, base
, offset
));
3094 return gen_rtx_PLUS (Pmode
, base
, offset
);
3101 /* Find a spare low register to use during the prolog of a function. */
3104 thumb_find_work_register (unsigned long pushed_regs_mask
)
3108 /* Check the argument registers first as these are call-used. The
3109 register allocation order means that sometimes r3 might be used
3110 but earlier argument registers might not, so check them all. */
3111 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3112 if (!regs_ever_live
[reg
])
3115 /* Before going on to check the call-saved registers we can try a couple
3116 more ways of deducing that r3 is available. The first is when we are
3117 pushing anonymous arguments onto the stack and we have less than 4
3118 registers worth of fixed arguments(*). In this case r3 will be part of
3119 the variable argument list and so we can be sure that it will be
3120 pushed right at the start of the function. Hence it will be available
3121 for the rest of the prologue.
3122 (*): ie current_function_pretend_args_size is greater than 0. */
3123 if (cfun
->machine
->uses_anonymous_args
3124 && current_function_pretend_args_size
> 0)
3125 return LAST_ARG_REGNUM
;
3127 /* The other case is when we have fixed arguments but less than 4 registers
3128 worth. In this case r3 might be used in the body of the function, but
3129 it is not being used to convey an argument into the function. In theory
3130 we could just check current_function_args_size to see how many bytes are
3131 being passed in argument registers, but it seems that it is unreliable.
3132 Sometimes it will have the value 0 when in fact arguments are being
3133 passed. (See testcase execute/20021111-1.c for an example). So we also
3134 check the args_info.nregs field as well. The problem with this field is
3135 that it makes no allowances for arguments that are passed to the
3136 function but which are not used. Hence we could miss an opportunity
3137 when a function has an unused argument in r3. But it is better to be
3138 safe than to be sorry. */
3139 if (! cfun
->machine
->uses_anonymous_args
3140 && current_function_args_size
>= 0
3141 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3142 && cfun
->args_info
.nregs
< 4)
3143 return LAST_ARG_REGNUM
;
3145 /* Otherwise look for a call-saved register that is going to be pushed. */
3146 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3147 if (pushed_regs_mask
& (1 << reg
))
3150 /* Something went wrong - thumb_compute_save_reg_mask()
3151 should have arranged for a suitable register to be pushed. */
3156 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3160 arm_load_pic_register (unsigned int scratch
)
3162 #ifndef AOF_ASSEMBLER
3163 rtx l1
, pic_tmp
, pic_tmp2
, pic_rtx
;
3164 rtx global_offset_table
;
3166 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3172 l1
= gen_label_rtx ();
3174 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3175 /* On the ARM the PC register contains 'dot + 8' at the time of the
3176 addition, on the Thumb it is 'dot + 4'. */
3177 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
3179 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3180 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3182 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3184 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3188 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3189 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
3193 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3195 /* We will have pushed the pic register, so should always be
3196 able to find a work register. */
3197 pic_tmp
= gen_rtx_REG (SImode
, scratch
);
3198 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3199 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3202 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3203 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
3206 /* Need to emit this whether or not we obey regdecls,
3207 since setjmp/longjmp can cause life info to screw up. */
3208 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3209 #endif /* AOF_ASSEMBLER */
3213 /* Return nonzero if X is valid as an ARM state addressing register. */
3215 arm_address_register_rtx_p (rtx x
, int strict_p
)
3219 if (GET_CODE (x
) != REG
)
3225 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3227 return (regno
<= LAST_ARM_REGNUM
3228 || regno
>= FIRST_PSEUDO_REGISTER
3229 || regno
== FRAME_POINTER_REGNUM
3230 || regno
== ARG_POINTER_REGNUM
);
3233 /* Return nonzero if X is a valid ARM state address operand. */
3235 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3239 enum rtx_code code
= GET_CODE (x
);
3241 if (arm_address_register_rtx_p (x
, strict_p
))
3244 use_ldrd
= (TARGET_LDRD
3246 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3248 if (code
== POST_INC
|| code
== PRE_DEC
3249 || ((code
== PRE_INC
|| code
== POST_DEC
)
3250 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3251 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3253 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3254 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3255 && GET_CODE (XEXP (x
, 1)) == PLUS
3256 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3258 rtx addend
= XEXP (XEXP (x
, 1), 1);
3260 /* Don't allow ldrd post increment by register because it's hard
3261 to fixup invalid register choices. */
3263 && GET_CODE (x
) == POST_MODIFY
3264 && GET_CODE (addend
) == REG
)
3267 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3268 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3271 /* After reload constants split into minipools will have addresses
3272 from a LABEL_REF. */
3273 else if (reload_completed
3274 && (code
== LABEL_REF
3276 && GET_CODE (XEXP (x
, 0)) == PLUS
3277 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3278 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3281 else if (mode
== TImode
)
3284 else if (code
== PLUS
)
3286 rtx xop0
= XEXP (x
, 0);
3287 rtx xop1
= XEXP (x
, 1);
3289 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3290 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3291 || (arm_address_register_rtx_p (xop1
, strict_p
)
3292 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3296 /* Reload currently can't handle MINUS, so disable this for now */
3297 else if (GET_CODE (x
) == MINUS
)
3299 rtx xop0
= XEXP (x
, 0);
3300 rtx xop1
= XEXP (x
, 1);
3302 return (arm_address_register_rtx_p (xop0
, strict_p
)
3303 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3307 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3308 && code
== SYMBOL_REF
3309 && CONSTANT_POOL_ADDRESS_P (x
)
3311 && symbol_mentioned_p (get_pool_constant (x
))))
3317 /* Return nonzero if INDEX is valid for an address index operand in
3320 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3323 HOST_WIDE_INT range
;
3324 enum rtx_code code
= GET_CODE (index
);
3326 /* Standard coprocessor addressing modes. */
3327 if (TARGET_HARD_FLOAT
3328 && (TARGET_FPA
|| TARGET_MAVERICK
)
3329 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3330 || (TARGET_MAVERICK
&& mode
== DImode
)))
3331 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3332 && INTVAL (index
) > -1024
3333 && (INTVAL (index
) & 3) == 0);
3335 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3336 return (code
== CONST_INT
3337 && INTVAL (index
) < 1024
3338 && INTVAL (index
) > -1024
3339 && (INTVAL (index
) & 3) == 0);
3341 if (arm_address_register_rtx_p (index
, strict_p
)
3342 && (GET_MODE_SIZE (mode
) <= 4))
3345 if (mode
== DImode
|| mode
== DFmode
)
3347 if (code
== CONST_INT
)
3349 HOST_WIDE_INT val
= INTVAL (index
);
3352 return val
> -256 && val
< 256;
3354 return val
> -4096 && val
< 4092;
3357 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3360 if (GET_MODE_SIZE (mode
) <= 4
3363 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3367 rtx xiop0
= XEXP (index
, 0);
3368 rtx xiop1
= XEXP (index
, 1);
3370 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3371 && power_of_two_operand (xiop1
, SImode
))
3372 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3373 && power_of_two_operand (xiop0
, SImode
)));
3375 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3376 || code
== ASHIFT
|| code
== ROTATERT
)
3378 rtx op
= XEXP (index
, 1);
3380 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3381 && GET_CODE (op
) == CONST_INT
3383 && INTVAL (op
) <= 31);
3387 /* For ARM v4 we may be doing a sign-extend operation during the
3391 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3397 range
= (mode
== HImode
) ? 4095 : 4096;
3399 return (code
== CONST_INT
3400 && INTVAL (index
) < range
3401 && INTVAL (index
) > -range
);
3404 /* Return nonzero if X is valid as a Thumb state base register. */
3406 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3410 if (GET_CODE (x
) != REG
)
3416 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3418 return (regno
<= LAST_LO_REGNUM
3419 || regno
> LAST_VIRTUAL_REGISTER
3420 || regno
== FRAME_POINTER_REGNUM
3421 || (GET_MODE_SIZE (mode
) >= 4
3422 && (regno
== STACK_POINTER_REGNUM
3423 || regno
>= FIRST_PSEUDO_REGISTER
3424 || x
== hard_frame_pointer_rtx
3425 || x
== arg_pointer_rtx
)));
3428 /* Return nonzero if x is a legitimate index register. This is the case
3429 for any base register that can access a QImode object. */
3431 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3433 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3436 /* Return nonzero if x is a legitimate Thumb-state address.
3438 The AP may be eliminated to either the SP or the FP, so we use the
3439 least common denominator, e.g. SImode, and offsets from 0 to 64.
3441 ??? Verify whether the above is the right approach.
3443 ??? Also, the FP may be eliminated to the SP, so perhaps that
3444 needs special handling also.
3446 ??? Look at how the mips16 port solves this problem. It probably uses
3447 better ways to solve some of these problems.
3449 Although it is not incorrect, we don't accept QImode and HImode
3450 addresses based on the frame pointer or arg pointer until the
3451 reload pass starts. This is so that eliminating such addresses
3452 into stack based ones won't produce impossible code. */
3454 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3456 /* ??? Not clear if this is right. Experiment. */
3457 if (GET_MODE_SIZE (mode
) < 4
3458 && !(reload_in_progress
|| reload_completed
)
3459 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3460 || reg_mentioned_p (arg_pointer_rtx
, x
)
3461 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3462 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3463 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3464 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3467 /* Accept any base register. SP only in SImode or larger. */
3468 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3471 /* This is PC relative data before arm_reorg runs. */
3472 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3473 && GET_CODE (x
) == SYMBOL_REF
3474 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3477 /* This is PC relative data after arm_reorg runs. */
3478 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3479 && (GET_CODE (x
) == LABEL_REF
3480 || (GET_CODE (x
) == CONST
3481 && GET_CODE (XEXP (x
, 0)) == PLUS
3482 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3483 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3486 /* Post-inc indexing only supported for SImode and larger. */
3487 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3488 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3491 else if (GET_CODE (x
) == PLUS
)
3493 /* REG+REG address can be any two index registers. */
3494 /* We disallow FRAME+REG addressing since we know that FRAME
3495 will be replaced with STACK, and SP relative addressing only
3496 permits SP+OFFSET. */
3497 if (GET_MODE_SIZE (mode
) <= 4
3498 && XEXP (x
, 0) != frame_pointer_rtx
3499 && XEXP (x
, 1) != frame_pointer_rtx
3500 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3501 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3504 /* REG+const has 5-7 bit offset for non-SP registers. */
3505 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3506 || XEXP (x
, 0) == arg_pointer_rtx
)
3507 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3508 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3511 /* REG+const has 10 bit offset for SP, but only SImode and
3512 larger is supported. */
3513 /* ??? Should probably check for DI/DFmode overflow here
3514 just like GO_IF_LEGITIMATE_OFFSET does. */
3515 else if (GET_CODE (XEXP (x
, 0)) == REG
3516 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3517 && GET_MODE_SIZE (mode
) >= 4
3518 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3519 && INTVAL (XEXP (x
, 1)) >= 0
3520 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3521 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3524 else if (GET_CODE (XEXP (x
, 0)) == REG
3525 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3526 && GET_MODE_SIZE (mode
) >= 4
3527 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3528 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3532 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3533 && GET_MODE_SIZE (mode
) == 4
3534 && GET_CODE (x
) == SYMBOL_REF
3535 && CONSTANT_POOL_ADDRESS_P (x
)
3537 && symbol_mentioned_p (get_pool_constant (x
))))
3543 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3544 instruction of mode MODE. */
3546 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3548 switch (GET_MODE_SIZE (mode
))
3551 return val
>= 0 && val
< 32;
3554 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3558 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3563 /* Try machine-dependent ways of modifying an illegitimate address
3564 to be legitimate. If we find one, return the new, valid address. */
3566 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3568 if (GET_CODE (x
) == PLUS
)
3570 rtx xop0
= XEXP (x
, 0);
3571 rtx xop1
= XEXP (x
, 1);
3573 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3574 xop0
= force_reg (SImode
, xop0
);
3576 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3577 xop1
= force_reg (SImode
, xop1
);
3579 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3580 && GET_CODE (xop1
) == CONST_INT
)
3582 HOST_WIDE_INT n
, low_n
;
3586 /* VFP addressing modes actually allow greater offsets, but for
3587 now we just stick with the lowest common denominator. */
3589 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3601 low_n
= ((mode
) == TImode
? 0
3602 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3606 base_reg
= gen_reg_rtx (SImode
);
3607 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3608 GEN_INT (n
)), NULL_RTX
);
3609 emit_move_insn (base_reg
, val
);
3610 x
= (low_n
== 0 ? base_reg
3611 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3613 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3614 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3617 /* XXX We don't allow MINUS any more -- see comment in
3618 arm_legitimate_address_p (). */
3619 else if (GET_CODE (x
) == MINUS
)
3621 rtx xop0
= XEXP (x
, 0);
3622 rtx xop1
= XEXP (x
, 1);
3624 if (CONSTANT_P (xop0
))
3625 xop0
= force_reg (SImode
, xop0
);
3627 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3628 xop1
= force_reg (SImode
, xop1
);
3630 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3631 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3636 /* We need to find and carefully transform any SYMBOL and LABEL
3637 references; so go back to the original address expression. */
3638 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3640 if (new_x
!= orig_x
)
3648 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3649 to be legitimate. If we find one, return the new, valid address. */
3651 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3653 if (GET_CODE (x
) == PLUS
3654 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3655 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
3656 || INTVAL (XEXP (x
, 1)) < 0))
3658 rtx xop0
= XEXP (x
, 0);
3659 rtx xop1
= XEXP (x
, 1);
3660 HOST_WIDE_INT offset
= INTVAL (xop1
);
3662 /* Try and fold the offset into a biasing of the base register and
3663 then offsetting that. Don't do this when optimizing for space
3664 since it can cause too many CSEs. */
3665 if (optimize_size
&& offset
>= 0
3666 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
3668 HOST_WIDE_INT delta
;
3671 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
3672 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
3673 delta
= 31 * GET_MODE_SIZE (mode
);
3675 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
3677 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
3679 x
= plus_constant (xop0
, delta
);
3681 else if (offset
< 0 && offset
> -256)
3682 /* Small negative offsets are best done with a subtract before the
3683 dereference, forcing these into a register normally takes two
3685 x
= force_operand (x
, NULL_RTX
);
3688 /* For the remaining cases, force the constant into a register. */
3689 xop1
= force_reg (SImode
, xop1
);
3690 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3693 else if (GET_CODE (x
) == PLUS
3694 && s_register_operand (XEXP (x
, 1), SImode
)
3695 && !s_register_operand (XEXP (x
, 0), SImode
))
3697 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
3699 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
3704 /* We need to find and carefully transform any SYMBOL and LABEL
3705 references; so go back to the original address expression. */
3706 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3708 if (new_x
!= orig_x
)
3717 #define REG_OR_SUBREG_REG(X) \
3718 (GET_CODE (X) == REG \
3719 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3721 #define REG_OR_SUBREG_RTX(X) \
3722 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3724 #ifndef COSTS_N_INSNS
3725 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3728 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3730 enum machine_mode mode
= GET_MODE (x
);
3743 return COSTS_N_INSNS (1);
3746 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3749 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3756 return COSTS_N_INSNS (2) + cycles
;
3758 return COSTS_N_INSNS (1) + 16;
3761 return (COSTS_N_INSNS (1)
3762 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3763 + GET_CODE (SET_DEST (x
)) == MEM
));
3768 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3770 if (thumb_shiftable_const (INTVAL (x
)))
3771 return COSTS_N_INSNS (2);
3772 return COSTS_N_INSNS (3);
3774 else if ((outer
== PLUS
|| outer
== COMPARE
)
3775 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3777 else if (outer
== AND
3778 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3779 return COSTS_N_INSNS (1);
3780 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3781 || outer
== LSHIFTRT
)
3783 return COSTS_N_INSNS (2);
3789 return COSTS_N_INSNS (3);
3807 /* XXX another guess. */
3808 /* Memory costs quite a lot for the first word, but subsequent words
3809 load at the equivalent of a single insn each. */
3810 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3811 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3816 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3821 /* XXX still guessing. */
3822 switch (GET_MODE (XEXP (x
, 0)))
3825 return (1 + (mode
== DImode
? 4 : 0)
3826 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3829 return (4 + (mode
== DImode
? 4 : 0)
3830 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3833 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3845 /* Worker routine for arm_rtx_costs. */
3847 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3849 enum machine_mode mode
= GET_MODE (x
);
3850 enum rtx_code subcode
;
3856 /* Memory costs quite a lot for the first word, but subsequent words
3857 load at the equivalent of a single insn each. */
3858 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3859 + (GET_CODE (x
) == SYMBOL_REF
3860 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3866 return optimize_size
? COSTS_N_INSNS (2) : 100;
3869 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3876 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3878 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3879 + ((GET_CODE (XEXP (x
, 0)) == REG
3880 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3881 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3883 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3884 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3885 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3887 + ((GET_CODE (XEXP (x
, 1)) == REG
3888 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3889 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3890 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3895 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3896 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3897 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3898 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3901 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3902 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3903 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3904 && arm_const_double_rtx (XEXP (x
, 1))))
3906 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3907 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3908 && arm_const_double_rtx (XEXP (x
, 0))))
3911 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3912 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3913 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3914 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3915 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3916 || subcode
== ROTATE
|| subcode
== ROTATERT
3918 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3919 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3920 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3921 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3922 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3923 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3924 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3929 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3930 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3931 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3932 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3933 && arm_const_double_rtx (XEXP (x
, 1))))
3937 case AND
: case XOR
: case IOR
:
3940 /* Normally the frame registers will be spilt into reg+const during
3941 reload, so it is a bad idea to combine them with other instructions,
3942 since then they might not be moved outside of loops. As a compromise
3943 we allow integration with ops that have a constant as their second
3945 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3946 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3947 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3948 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3949 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3953 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3954 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3955 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3956 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3959 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3960 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3961 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3962 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3963 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3966 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3967 return (1 + extra_cost
3968 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3969 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3970 || subcode
== ROTATE
|| subcode
== ROTATERT
3972 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3973 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3974 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3975 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3976 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3977 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3983 /* This should have been handled by the CPU specific routines. */
3987 if (arm_arch3m
&& mode
== SImode
3988 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3989 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3990 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3991 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3992 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3993 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3998 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3999 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4003 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4005 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4008 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4016 return 4 + (mode
== DImode
? 4 : 0);
4019 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4020 return (4 + (mode
== DImode
? 4 : 0)
4021 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4024 switch (GET_MODE (XEXP (x
, 0)))
4027 return (1 + (mode
== DImode
? 4 : 0)
4028 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4031 return (4 + (mode
== DImode
? 4 : 0)
4032 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4035 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4050 if (const_ok_for_arm (INTVAL (x
)))
4051 return outer
== SET
? 2 : -1;
4052 else if (outer
== AND
4053 && const_ok_for_arm (~INTVAL (x
)))
4055 else if ((outer
== COMPARE
4056 || outer
== PLUS
|| outer
== MINUS
)
4057 && const_ok_for_arm (-INTVAL (x
)))
4068 if (arm_const_double_rtx (x
))
4069 return outer
== SET
? 2 : -1;
4070 else if ((outer
== COMPARE
|| outer
== PLUS
)
4071 && neg_const_double_rtx_ok_for_fpa (x
))
4080 /* RTX costs when optimizing for size. */
4082 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4084 enum machine_mode mode
= GET_MODE (x
);
4088 /* XXX TBD. For now, use the standard costs. */
4089 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4096 /* A memory access costs 1 insn if the mode is small, or the address is
4097 a single register, otherwise it costs one insn per word. */
4098 if (REG_P (XEXP (x
, 0)))
4099 *total
= COSTS_N_INSNS (1);
4101 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4108 /* Needs a libcall, so it costs about this. */
4109 *total
= COSTS_N_INSNS (2);
4113 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4115 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4123 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4125 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4128 else if (mode
== SImode
)
4130 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4131 /* Slightly disparage register shifts, but not by much. */
4132 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4133 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4137 /* Needs a libcall. */
4138 *total
= COSTS_N_INSNS (2);
4142 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4144 *total
= COSTS_N_INSNS (1);
4150 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4151 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4153 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4154 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4155 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4156 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4157 || subcode1
== ASHIFTRT
)
4159 /* It's just the cost of the two operands. */
4164 *total
= COSTS_N_INSNS (1);
4168 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4172 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4174 *total
= COSTS_N_INSNS (1);
4179 case AND
: case XOR
: case IOR
:
4182 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4184 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4185 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4186 || (code
== AND
&& subcode
== NOT
))
4188 /* It's just the cost of the two operands. */
4194 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4198 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4202 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4203 *total
= COSTS_N_INSNS (1);
4206 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4215 if (cc_register (XEXP (x
, 0), VOIDmode
))
4218 *total
= COSTS_N_INSNS (1);
4222 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4223 *total
= COSTS_N_INSNS (1);
4225 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4230 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4232 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4233 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4236 *total
+= COSTS_N_INSNS (1);
4241 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4243 switch (GET_MODE (XEXP (x
, 0)))
4246 *total
+= COSTS_N_INSNS (1);
4250 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4256 *total
+= COSTS_N_INSNS (2);
4261 *total
+= COSTS_N_INSNS (1);
4266 if (const_ok_for_arm (INTVAL (x
)))
4267 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4268 else if (const_ok_for_arm (~INTVAL (x
)))
4269 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4270 else if (const_ok_for_arm (-INTVAL (x
)))
4272 if (outer_code
== COMPARE
|| outer_code
== PLUS
4273 || outer_code
== MINUS
)
4276 *total
= COSTS_N_INSNS (1);
4279 *total
= COSTS_N_INSNS (2);
4285 *total
= COSTS_N_INSNS (2);
4289 *total
= COSTS_N_INSNS (4);
4293 if (mode
!= VOIDmode
)
4294 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4296 *total
= COSTS_N_INSNS (4); /* How knows? */
4301 /* RTX costs for cores with a slow MUL implementation. */
4304 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4306 enum machine_mode mode
= GET_MODE (x
);
4310 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4317 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4324 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4326 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4327 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4328 int cost
, const_ok
= const_ok_for_arm (i
);
4329 int j
, booth_unit_size
;
4331 /* Tune as appropriate. */
4332 cost
= const_ok
? 4 : 8;
4333 booth_unit_size
= 2;
4334 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4336 i
>>= booth_unit_size
;
4344 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4345 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4349 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4355 /* RTX cost for cores with a fast multiply unit (M variants). */
4358 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4360 enum machine_mode mode
= GET_MODE (x
);
4364 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4371 /* There is no point basing this on the tuning, since it is always the
4372 fast variant if it exists at all. */
4374 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4375 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4376 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4383 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4390 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4392 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4393 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4394 int cost
, const_ok
= const_ok_for_arm (i
);
4395 int j
, booth_unit_size
;
4397 /* Tune as appropriate. */
4398 cost
= const_ok
? 4 : 8;
4399 booth_unit_size
= 8;
4400 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4402 i
>>= booth_unit_size
;
4410 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4411 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4415 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4421 /* RTX cost for XScale CPUs. */
4424 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4426 enum machine_mode mode
= GET_MODE (x
);
4430 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4437 /* There is no point basing this on the tuning, since it is always the
4438 fast variant if it exists at all. */
4440 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4441 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4442 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4449 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4456 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4458 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4459 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4460 int cost
, const_ok
= const_ok_for_arm (i
);
4461 unsigned HOST_WIDE_INT masked_const
;
4463 /* The cost will be related to two insns.
4464 First a load of the constant (MOV or LDR), then a multiply. */
4467 cost
+= 1; /* LDR is probably more expensive because
4468 of longer result latency. */
4469 masked_const
= i
& 0xffff8000;
4470 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4472 masked_const
= i
& 0xf8000000;
4473 if (masked_const
== 0 || masked_const
== 0xf8000000)
4482 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4483 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4487 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4488 will stall until the multiplication is complete. */
4489 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4490 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
4492 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4496 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4502 /* RTX costs for 9e (and later) cores. */
4505 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4507 enum machine_mode mode
= GET_MODE (x
);
4516 *total
= COSTS_N_INSNS (3);
4520 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4528 /* There is no point basing this on the tuning, since it is always the
4529 fast variant if it exists at all. */
4531 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4532 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4533 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4540 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4557 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
4558 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
4562 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4566 /* All address computations that can be done are free, but rtx cost returns
4567 the same for practically all of them. So we weight the different types
4568 of address here in the order (most pref first):
4569 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4571 arm_arm_address_cost (rtx x
)
4573 enum rtx_code c
= GET_CODE (x
);
4575 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
4577 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
4580 if (c
== PLUS
|| c
== MINUS
)
4582 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4585 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
4595 arm_thumb_address_cost (rtx x
)
4597 enum rtx_code c
= GET_CODE (x
);
4602 && GET_CODE (XEXP (x
, 0)) == REG
4603 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4610 arm_address_cost (rtx x
)
4612 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
4616 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
4620 /* Some true dependencies can have a higher cost depending
4621 on precisely how certain input operands are used. */
4623 && REG_NOTE_KIND (link
) == 0
4624 && recog_memoized (insn
) >= 0
4625 && recog_memoized (dep
) >= 0)
4627 int shift_opnum
= get_attr_shift (insn
);
4628 enum attr_type attr_type
= get_attr_type (dep
);
4630 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4631 operand for INSN. If we have a shifted input operand and the
4632 instruction we depend on is another ALU instruction, then we may
4633 have to account for an additional stall. */
4634 if (shift_opnum
!= 0
4635 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
4637 rtx shifted_operand
;
4640 /* Get the shifted operand. */
4641 extract_insn (insn
);
4642 shifted_operand
= recog_data
.operand
[shift_opnum
];
4644 /* Iterate over all the operands in DEP. If we write an operand
4645 that overlaps with SHIFTED_OPERAND, then we have increase the
4646 cost of this dependency. */
4648 preprocess_constraints ();
4649 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4651 /* We can ignore strict inputs. */
4652 if (recog_data
.operand_type
[opno
] == OP_IN
)
4655 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
4662 /* XXX This is not strictly true for the FPA. */
4663 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
4664 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4667 /* Call insns don't incur a stall, even if they follow a load. */
4668 if (REG_NOTE_KIND (link
) == 0
4669 && GET_CODE (insn
) == CALL_INSN
)
4672 if ((i_pat
= single_set (insn
)) != NULL
4673 && GET_CODE (SET_SRC (i_pat
)) == MEM
4674 && (d_pat
= single_set (dep
)) != NULL
4675 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
4677 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
4678 /* This is a load after a store, there is no conflict if the load reads
4679 from a cached area. Assume that loads from the stack, and from the
4680 constant pool are cached, and that others will miss. This is a
4683 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
4684 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
4685 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
4686 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
4693 static int fp_consts_inited
= 0;
4695 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4696 static const char * const strings_fp
[8] =
4699 "4", "5", "0.5", "10"
4702 static REAL_VALUE_TYPE values_fp
[8];
4705 init_fp_table (void)
4711 fp_consts_inited
= 1;
4713 fp_consts_inited
= 8;
4715 for (i
= 0; i
< fp_consts_inited
; i
++)
4717 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
4722 /* Return TRUE if rtx X is a valid immediate FP constant. */
4724 arm_const_double_rtx (rtx x
)
4729 if (!fp_consts_inited
)
4732 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4733 if (REAL_VALUE_MINUS_ZERO (r
))
4736 for (i
= 0; i
< fp_consts_inited
; i
++)
4737 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4743 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4745 neg_const_double_rtx_ok_for_fpa (rtx x
)
4750 if (!fp_consts_inited
)
4753 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4754 r
= REAL_VALUE_NEGATE (r
);
4755 if (REAL_VALUE_MINUS_ZERO (r
))
4758 for (i
= 0; i
< 8; i
++)
4759 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4765 /* Predicates for `match_operand' and `match_operator'. */
4767 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4769 cirrus_memory_offset (rtx op
)
4771 /* Reject eliminable registers. */
4772 if (! (reload_in_progress
|| reload_completed
)
4773 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4774 || reg_mentioned_p (arg_pointer_rtx
, op
)
4775 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4776 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4777 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4778 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4781 if (GET_CODE (op
) == MEM
)
4787 /* Match: (mem (reg)). */
4788 if (GET_CODE (ind
) == REG
)
4794 if (GET_CODE (ind
) == PLUS
4795 && GET_CODE (XEXP (ind
, 0)) == REG
4796 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4797 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4804 /* Return TRUE if OP is a valid VFP memory address pattern.
4805 WB if true if writeback address modes are allowed. */
4808 arm_coproc_mem_operand (rtx op
, bool wb
)
4812 /* Reject eliminable registers. */
4813 if (! (reload_in_progress
|| reload_completed
)
4814 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4815 || reg_mentioned_p (arg_pointer_rtx
, op
)
4816 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4817 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4818 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4819 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4822 /* Constants are converted into offsets from labels. */
4823 if (GET_CODE (op
) != MEM
)
4828 if (reload_completed
4829 && (GET_CODE (ind
) == LABEL_REF
4830 || (GET_CODE (ind
) == CONST
4831 && GET_CODE (XEXP (ind
, 0)) == PLUS
4832 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
4833 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
4836 /* Match: (mem (reg)). */
4837 if (GET_CODE (ind
) == REG
)
4838 return arm_address_register_rtx_p (ind
, 0);
4840 /* Autoincremment addressing modes. */
4842 && (GET_CODE (ind
) == PRE_INC
4843 || GET_CODE (ind
) == POST_INC
4844 || GET_CODE (ind
) == PRE_DEC
4845 || GET_CODE (ind
) == POST_DEC
))
4846 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
4849 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
4850 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
4851 && GET_CODE (XEXP (ind
, 1)) == PLUS
4852 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
4853 ind
= XEXP (ind
, 1);
4858 if (GET_CODE (ind
) == PLUS
4859 && GET_CODE (XEXP (ind
, 0)) == REG
4860 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4861 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
4862 && INTVAL (XEXP (ind
, 1)) > -1024
4863 && INTVAL (XEXP (ind
, 1)) < 1024
4864 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
4870 /* Return true if X is a register that will be eliminated later on. */
4872 arm_eliminable_register (rtx x
)
4874 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
4875 || REGNO (x
) == ARG_POINTER_REGNUM
4876 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
4877 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
4880 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4881 VFP registers. Otherwise return NO_REGS. */
4884 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
4886 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
4889 return GENERAL_REGS
;
4893 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4894 Use by the Cirrus Maverick code which has to workaround
4895 a hardware bug triggered by such instructions. */
4897 arm_memory_load_p (rtx insn
)
4899 rtx body
, lhs
, rhs
;;
4901 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
4904 body
= PATTERN (insn
);
4906 if (GET_CODE (body
) != SET
)
4909 lhs
= XEXP (body
, 0);
4910 rhs
= XEXP (body
, 1);
4912 lhs
= REG_OR_SUBREG_RTX (lhs
);
4914 /* If the destination is not a general purpose
4915 register we do not have to worry. */
4916 if (GET_CODE (lhs
) != REG
4917 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
4920 /* As well as loads from memory we also have to react
4921 to loads of invalid constants which will be turned
4922 into loads from the minipool. */
4923 return (GET_CODE (rhs
) == MEM
4924 || GET_CODE (rhs
) == SYMBOL_REF
4925 || note_invalid_constants (insn
, -1, false));
4928 /* Return TRUE if INSN is a Cirrus instruction. */
4930 arm_cirrus_insn_p (rtx insn
)
4932 enum attr_cirrus attr
;
4934 /* get_attr aborts on USE and CLOBBER. */
4936 || GET_CODE (insn
) != INSN
4937 || GET_CODE (PATTERN (insn
)) == USE
4938 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4941 attr
= get_attr_cirrus (insn
);
4943 return attr
!= CIRRUS_NOT
;
4946 /* Cirrus reorg for invalid instruction combinations. */
4948 cirrus_reorg (rtx first
)
4950 enum attr_cirrus attr
;
4951 rtx body
= PATTERN (first
);
4955 /* Any branch must be followed by 2 non Cirrus instructions. */
4956 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4959 t
= next_nonnote_insn (first
);
4961 if (arm_cirrus_insn_p (t
))
4964 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4968 emit_insn_after (gen_nop (), first
);
4973 /* (float (blah)) is in parallel with a clobber. */
4974 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4975 body
= XVECEXP (body
, 0, 0);
4977 if (GET_CODE (body
) == SET
)
4979 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4981 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4982 be followed by a non Cirrus insn. */
4983 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4985 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4986 emit_insn_after (gen_nop (), first
);
4990 else if (arm_memory_load_p (first
))
4992 unsigned int arm_regno
;
4994 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4995 ldr/cfmv64hr combination where the Rd field is the same
4996 in both instructions must be split with a non Cirrus
5003 /* Get Arm register number for ldr insn. */
5004 if (GET_CODE (lhs
) == REG
)
5005 arm_regno
= REGNO (lhs
);
5006 else if (GET_CODE (rhs
) == REG
)
5007 arm_regno
= REGNO (rhs
);
5012 first
= next_nonnote_insn (first
);
5014 if (! arm_cirrus_insn_p (first
))
5017 body
= PATTERN (first
);
5019 /* (float (blah)) is in parallel with a clobber. */
5020 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5021 body
= XVECEXP (body
, 0, 0);
5023 if (GET_CODE (body
) == FLOAT
)
5024 body
= XEXP (body
, 0);
5026 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5027 && GET_CODE (XEXP (body
, 1)) == REG
5028 && arm_regno
== REGNO (XEXP (body
, 1)))
5029 emit_insn_after (gen_nop (), first
);
5035 /* get_attr aborts on USE and CLOBBER. */
5037 || GET_CODE (first
) != INSN
5038 || GET_CODE (PATTERN (first
)) == USE
5039 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5042 attr
= get_attr_cirrus (first
);
5044 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5045 must be followed by a non-coprocessor instruction. */
5046 if (attr
== CIRRUS_COMPARE
)
5050 t
= next_nonnote_insn (first
);
5052 if (arm_cirrus_insn_p (t
))
5055 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5059 emit_insn_after (gen_nop (), first
);
5065 /* Return TRUE if X references a SYMBOL_REF. */
5067 symbol_mentioned_p (rtx x
)
5072 if (GET_CODE (x
) == SYMBOL_REF
)
5075 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5077 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5083 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5084 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5087 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5094 /* Return TRUE if X references a LABEL_REF. */
5096 label_mentioned_p (rtx x
)
5101 if (GET_CODE (x
) == LABEL_REF
)
5104 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5105 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5111 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5112 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5115 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5125 enum rtx_code code
= GET_CODE (x
);
5129 else if (code
== SMIN
)
5131 else if (code
== UMIN
)
5133 else if (code
== UMAX
)
5139 /* Return 1 if memory locations are adjacent. */
5141 adjacent_mem_locations (rtx a
, rtx b
)
5143 /* We don't guarantee to preserve the order of these memory refs. */
5144 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5147 if ((GET_CODE (XEXP (a
, 0)) == REG
5148 || (GET_CODE (XEXP (a
, 0)) == PLUS
5149 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5150 && (GET_CODE (XEXP (b
, 0)) == REG
5151 || (GET_CODE (XEXP (b
, 0)) == PLUS
5152 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5154 HOST_WIDE_INT val0
= 0, val1
= 0;
5158 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5160 reg0
= XEXP (XEXP (a
, 0), 0);
5161 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5166 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5168 reg1
= XEXP (XEXP (b
, 0), 0);
5169 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5174 /* Don't accept any offset that will require multiple
5175 instructions to handle, since this would cause the
5176 arith_adjacentmem pattern to output an overlong sequence. */
5177 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5180 /* Don't allow an eliminable register: register elimination can make
5181 the offset too large. */
5182 if (arm_eliminable_register (reg0
))
5185 val_diff
= val1
- val0
;
5189 /* If the target has load delay slots, then there's no benefit
5190 to using an ldm instruction unless the offset is zero and
5191 we are optimizing for size. */
5192 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5193 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5194 && (val_diff
== 4 || val_diff
== -4));
5197 return ((REGNO (reg0
) == REGNO (reg1
))
5198 && (val_diff
== 4 || val_diff
== -4));
5205 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5206 HOST_WIDE_INT
*load_offset
)
5208 int unsorted_regs
[4];
5209 HOST_WIDE_INT unsorted_offsets
[4];
5214 /* Can only handle 2, 3, or 4 insns at present,
5215 though could be easily extended if required. */
5216 if (nops
< 2 || nops
> 4)
5219 /* Loop over the operands and check that the memory references are
5220 suitable (i.e. immediate offsets from the same base register). At
5221 the same time, extract the target register, and the memory
5223 for (i
= 0; i
< nops
; i
++)
5228 /* Convert a subreg of a mem into the mem itself. */
5229 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5230 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5232 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5235 /* Don't reorder volatile memory references; it doesn't seem worth
5236 looking for the case where the order is ok anyway. */
5237 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5240 offset
= const0_rtx
;
5242 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5243 || (GET_CODE (reg
) == SUBREG
5244 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5245 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5246 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5248 || (GET_CODE (reg
) == SUBREG
5249 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5250 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5255 base_reg
= REGNO (reg
);
5256 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5257 ? REGNO (operands
[i
])
5258 : REGNO (SUBREG_REG (operands
[i
])));
5263 if (base_reg
!= (int) REGNO (reg
))
5264 /* Not addressed from the same base register. */
5267 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5268 ? REGNO (operands
[i
])
5269 : REGNO (SUBREG_REG (operands
[i
])));
5270 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5274 /* If it isn't an integer register, or if it overwrites the
5275 base register but isn't the last insn in the list, then
5276 we can't do this. */
5277 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5278 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5281 unsorted_offsets
[i
] = INTVAL (offset
);
5284 /* Not a suitable memory address. */
5288 /* All the useful information has now been extracted from the
5289 operands into unsorted_regs and unsorted_offsets; additionally,
5290 order[0] has been set to the lowest numbered register in the
5291 list. Sort the registers into order, and check that the memory
5292 offsets are ascending and adjacent. */
5294 for (i
= 1; i
< nops
; i
++)
5298 order
[i
] = order
[i
- 1];
5299 for (j
= 0; j
< nops
; j
++)
5300 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5301 && (order
[i
] == order
[i
- 1]
5302 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5305 /* Have we found a suitable register? if not, one must be used more
5307 if (order
[i
] == order
[i
- 1])
5310 /* Is the memory address adjacent and ascending? */
5311 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5319 for (i
= 0; i
< nops
; i
++)
5320 regs
[i
] = unsorted_regs
[order
[i
]];
5322 *load_offset
= unsorted_offsets
[order
[0]];
5325 if (unsorted_offsets
[order
[0]] == 0)
5326 return 1; /* ldmia */
5328 if (unsorted_offsets
[order
[0]] == 4)
5329 return 2; /* ldmib */
5331 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5332 return 3; /* ldmda */
5334 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5335 return 4; /* ldmdb */
5337 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5338 if the offset isn't small enough. The reason 2 ldrs are faster
5339 is because these ARMs are able to do more than one cache access
5340 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5341 whilst the ARM8 has a double bandwidth cache. This means that
5342 these cores can do both an instruction fetch and a data fetch in
5343 a single cycle, so the trick of calculating the address into a
5344 scratch register (one of the result regs) and then doing a load
5345 multiple actually becomes slower (and no smaller in code size).
5346 That is the transformation
5348 ldr rd1, [rbase + offset]
5349 ldr rd2, [rbase + offset + 4]
5353 add rd1, rbase, offset
5354 ldmia rd1, {rd1, rd2}
5356 produces worse code -- '3 cycles + any stalls on rd2' instead of
5357 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5358 access per cycle, the first sequence could never complete in less
5359 than 6 cycles, whereas the ldm sequence would only take 5 and
5360 would make better use of sequential accesses if not hitting the
5363 We cheat here and test 'arm_ld_sched' which we currently know to
5364 only be true for the ARM8, ARM9 and StrongARM. If this ever
5365 changes, then the test below needs to be reworked. */
5366 if (nops
== 2 && arm_ld_sched
)
5369 /* Can't do it without setting up the offset, only do this if it takes
5370 no more than one insn. */
5371 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5372 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5376 emit_ldm_seq (rtx
*operands
, int nops
)
5380 HOST_WIDE_INT offset
;
5384 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5387 strcpy (buf
, "ldm%?ia\t");
5391 strcpy (buf
, "ldm%?ib\t");
5395 strcpy (buf
, "ldm%?da\t");
5399 strcpy (buf
, "ldm%?db\t");
5404 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5405 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5408 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5409 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5411 output_asm_insn (buf
, operands
);
5413 strcpy (buf
, "ldm%?ia\t");
5420 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5421 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5423 for (i
= 1; i
< nops
; i
++)
5424 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5425 reg_names
[regs
[i
]]);
5427 strcat (buf
, "}\t%@ phole ldm");
5429 output_asm_insn (buf
, operands
);
5434 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5435 HOST_WIDE_INT
* load_offset
)
5437 int unsorted_regs
[4];
5438 HOST_WIDE_INT unsorted_offsets
[4];
5443 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5444 extended if required. */
5445 if (nops
< 2 || nops
> 4)
5448 /* Loop over the operands and check that the memory references are
5449 suitable (i.e. immediate offsets from the same base register). At
5450 the same time, extract the target register, and the memory
5452 for (i
= 0; i
< nops
; i
++)
5457 /* Convert a subreg of a mem into the mem itself. */
5458 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5459 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5461 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5464 /* Don't reorder volatile memory references; it doesn't seem worth
5465 looking for the case where the order is ok anyway. */
5466 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5469 offset
= const0_rtx
;
5471 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5472 || (GET_CODE (reg
) == SUBREG
5473 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5474 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5475 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5477 || (GET_CODE (reg
) == SUBREG
5478 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5479 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5484 base_reg
= REGNO (reg
);
5485 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5486 ? REGNO (operands
[i
])
5487 : REGNO (SUBREG_REG (operands
[i
])));
5492 if (base_reg
!= (int) REGNO (reg
))
5493 /* Not addressed from the same base register. */
5496 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5497 ? REGNO (operands
[i
])
5498 : REGNO (SUBREG_REG (operands
[i
])));
5499 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5503 /* If it isn't an integer register, then we can't do this. */
5504 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5507 unsorted_offsets
[i
] = INTVAL (offset
);
5510 /* Not a suitable memory address. */
5514 /* All the useful information has now been extracted from the
5515 operands into unsorted_regs and unsorted_offsets; additionally,
5516 order[0] has been set to the lowest numbered register in the
5517 list. Sort the registers into order, and check that the memory
5518 offsets are ascending and adjacent. */
5520 for (i
= 1; i
< nops
; i
++)
5524 order
[i
] = order
[i
- 1];
5525 for (j
= 0; j
< nops
; j
++)
5526 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5527 && (order
[i
] == order
[i
- 1]
5528 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5531 /* Have we found a suitable register? if not, one must be used more
5533 if (order
[i
] == order
[i
- 1])
5536 /* Is the memory address adjacent and ascending? */
5537 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5545 for (i
= 0; i
< nops
; i
++)
5546 regs
[i
] = unsorted_regs
[order
[i
]];
5548 *load_offset
= unsorted_offsets
[order
[0]];
5551 if (unsorted_offsets
[order
[0]] == 0)
5552 return 1; /* stmia */
5554 if (unsorted_offsets
[order
[0]] == 4)
5555 return 2; /* stmib */
5557 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5558 return 3; /* stmda */
5560 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5561 return 4; /* stmdb */
5567 emit_stm_seq (rtx
*operands
, int nops
)
5571 HOST_WIDE_INT offset
;
5575 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5578 strcpy (buf
, "stm%?ia\t");
5582 strcpy (buf
, "stm%?ib\t");
5586 strcpy (buf
, "stm%?da\t");
5590 strcpy (buf
, "stm%?db\t");
5597 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5598 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5600 for (i
= 1; i
< nops
; i
++)
5601 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5602 reg_names
[regs
[i
]]);
5604 strcat (buf
, "}\t%@ phole stm");
5606 output_asm_insn (buf
, operands
);
5611 /* Routines for use in generating RTL. */
5614 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5615 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
5617 HOST_WIDE_INT offset
= *offsetp
;
5620 int sign
= up
? 1 : -1;
5623 /* XScale has load-store double instructions, but they have stricter
5624 alignment requirements than load-store multiple, so we cannot
5627 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5628 the pipeline until completion.
5636 An ldr instruction takes 1-3 cycles, but does not block the
5645 Best case ldr will always win. However, the more ldr instructions
5646 we issue, the less likely we are to be able to schedule them well.
5647 Using ldr instructions also increases code size.
5649 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5650 for counts of 3 or 4 regs. */
5651 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5657 for (i
= 0; i
< count
; i
++)
5659 addr
= plus_constant (from
, i
* 4 * sign
);
5660 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
5661 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5667 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5677 result
= gen_rtx_PARALLEL (VOIDmode
,
5678 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5681 XVECEXP (result
, 0, 0)
5682 = gen_rtx_SET (GET_MODE (from
), from
,
5683 plus_constant (from
, count
* 4 * sign
));
5688 for (j
= 0; i
< count
; i
++, j
++)
5690 addr
= plus_constant (from
, j
* 4 * sign
);
5691 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
5692 XVECEXP (result
, 0, i
)
5693 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5704 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5705 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
5707 HOST_WIDE_INT offset
= *offsetp
;
5710 int sign
= up
? 1 : -1;
5713 /* See arm_gen_load_multiple for discussion of
5714 the pros/cons of ldm/stm usage for XScale. */
5715 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5721 for (i
= 0; i
< count
; i
++)
5723 addr
= plus_constant (to
, i
* 4 * sign
);
5724 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
5725 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5731 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5741 result
= gen_rtx_PARALLEL (VOIDmode
,
5742 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5745 XVECEXP (result
, 0, 0)
5746 = gen_rtx_SET (GET_MODE (to
), to
,
5747 plus_constant (to
, count
* 4 * sign
));
5752 for (j
= 0; i
< count
; i
++, j
++)
5754 addr
= plus_constant (to
, j
* 4 * sign
);
5755 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
5756 XVECEXP (result
, 0, i
)
5757 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5768 arm_gen_movmemqi (rtx
*operands
)
5770 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5771 HOST_WIDE_INT srcoffset
, dstoffset
;
5773 rtx src
, dst
, srcbase
, dstbase
;
5774 rtx part_bytes_reg
= NULL
;
5777 if (GET_CODE (operands
[2]) != CONST_INT
5778 || GET_CODE (operands
[3]) != CONST_INT
5779 || INTVAL (operands
[2]) > 64
5780 || INTVAL (operands
[3]) & 3)
5783 dstbase
= operands
[0];
5784 srcbase
= operands
[1];
5786 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
5787 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
5789 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5790 out_words_to_go
= INTVAL (operands
[2]) / 4;
5791 last_bytes
= INTVAL (operands
[2]) & 3;
5792 dstoffset
= srcoffset
= 0;
5794 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5795 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5797 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5799 if (in_words_to_go
> 4)
5800 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5801 srcbase
, &srcoffset
));
5803 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5804 FALSE
, srcbase
, &srcoffset
));
5806 if (out_words_to_go
)
5808 if (out_words_to_go
> 4)
5809 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5810 dstbase
, &dstoffset
));
5811 else if (out_words_to_go
!= 1)
5812 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
5816 dstbase
, &dstoffset
));
5819 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
5820 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
5821 if (last_bytes
!= 0)
5823 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
5829 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
5830 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
5833 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5834 if (out_words_to_go
)
5838 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
5839 sreg
= copy_to_reg (mem
);
5841 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
5842 emit_move_insn (mem
, sreg
);
5845 if (in_words_to_go
) /* Sanity check */
5851 if (in_words_to_go
< 0)
5854 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
5855 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
5858 if (last_bytes
&& part_bytes_reg
== NULL
)
5861 if (BYTES_BIG_ENDIAN
&& last_bytes
)
5863 rtx tmp
= gen_reg_rtx (SImode
);
5865 /* The bytes we want are in the top end of the word. */
5866 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
5867 GEN_INT (8 * (4 - last_bytes
))));
5868 part_bytes_reg
= tmp
;
5872 mem
= adjust_automodify_address (dstbase
, QImode
,
5873 plus_constant (dst
, last_bytes
- 1),
5874 dstoffset
+ last_bytes
- 1);
5875 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5879 tmp
= gen_reg_rtx (SImode
);
5880 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
5881 part_bytes_reg
= tmp
;
5890 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
5891 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
5895 rtx tmp
= gen_reg_rtx (SImode
);
5896 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
5897 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
5898 part_bytes_reg
= tmp
;
5905 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
5906 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5913 /* Generate a memory reference for a half word, such that it will be loaded
5914 into the top 16 bits of the word. We can assume that the address is
5915 known to be alignable and of the form reg, or plus (reg, const). */
5918 arm_gen_rotated_half_load (rtx memref
)
5920 HOST_WIDE_INT offset
= 0;
5921 rtx base
= XEXP (memref
, 0);
5923 if (GET_CODE (base
) == PLUS
)
5925 offset
= INTVAL (XEXP (base
, 1));
5926 base
= XEXP (base
, 0);
5929 /* If we aren't allowed to generate unaligned addresses, then fail. */
5930 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0))
5933 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
5935 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
5938 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
5941 /* Select a dominance comparison mode if possible for a test of the general
5942 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5943 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5944 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5945 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5946 In all cases OP will be either EQ or NE, but we don't need to know which
5947 here. If we are unable to support a dominance comparison we return
5948 CC mode. This will then fail to match for the RTL expressions that
5949 generate this call. */
5951 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
5953 enum rtx_code cond1
, cond2
;
5956 /* Currently we will probably get the wrong result if the individual
5957 comparisons are not simple. This also ensures that it is safe to
5958 reverse a comparison if necessary. */
5959 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
5961 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
5965 /* The if_then_else variant of this tests the second condition if the
5966 first passes, but is true if the first fails. Reverse the first
5967 condition to get a true "inclusive-or" expression. */
5968 if (cond_or
== DOM_CC_NX_OR_Y
)
5969 cond1
= reverse_condition (cond1
);
5971 /* If the comparisons are not equal, and one doesn't dominate the other,
5972 then we can't do this. */
5974 && !comparison_dominates_p (cond1
, cond2
)
5975 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
5980 enum rtx_code temp
= cond1
;
5988 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
5993 case LE
: return CC_DLEmode
;
5994 case LEU
: return CC_DLEUmode
;
5995 case GE
: return CC_DGEmode
;
5996 case GEU
: return CC_DGEUmode
;
6003 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
6012 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
6021 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
6030 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
6038 /* The remaining cases only occur when both comparisons are the
6063 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6065 /* All floating point compares return CCFP if it is an equality
6066 comparison, and CCFPE otherwise. */
6067 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6087 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6096 /* A compare with a shifted operand. Because of canonicalization, the
6097 comparison will have to be swapped when we emit the assembler. */
6098 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6099 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6100 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6101 || GET_CODE (x
) == ROTATERT
))
6104 /* This operation is performed swapped, but since we only rely on the Z
6105 flag we don't need an additional mode. */
6106 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6107 && GET_CODE (x
) == NEG
6108 && (op
== EQ
|| op
== NE
))
6111 /* This is a special case that is used by combine to allow a
6112 comparison of a shifted byte load to be split into a zero-extend
6113 followed by a comparison of the shifted integer (only valid for
6114 equalities and unsigned inequalities). */
6115 if (GET_MODE (x
) == SImode
6116 && GET_CODE (x
) == ASHIFT
6117 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6118 && GET_CODE (XEXP (x
, 0)) == SUBREG
6119 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6120 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6121 && (op
== EQ
|| op
== NE
6122 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6123 && GET_CODE (y
) == CONST_INT
)
6126 /* A construct for a conditional compare, if the false arm contains
6127 0, then both conditions must be true, otherwise either condition
6128 must be true. Not all conditions are possible, so CCmode is
6129 returned if it can't be done. */
6130 if (GET_CODE (x
) == IF_THEN_ELSE
6131 && (XEXP (x
, 2) == const0_rtx
6132 || XEXP (x
, 2) == const1_rtx
)
6133 && COMPARISON_P (XEXP (x
, 0))
6134 && COMPARISON_P (XEXP (x
, 1)))
6135 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6136 INTVAL (XEXP (x
, 2)));
6138 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6139 if (GET_CODE (x
) == AND
6140 && COMPARISON_P (XEXP (x
, 0))
6141 && COMPARISON_P (XEXP (x
, 1)))
6142 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6145 if (GET_CODE (x
) == IOR
6146 && COMPARISON_P (XEXP (x
, 0))
6147 && COMPARISON_P (XEXP (x
, 1)))
6148 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6151 /* An operation (on Thumb) where we want to test for a single bit.
6152 This is done by shifting that bit up into the top bit of a
6153 scratch register; we can then branch on the sign bit. */
6155 && GET_MODE (x
) == SImode
6156 && (op
== EQ
|| op
== NE
)
6157 && (GET_CODE (x
) == ZERO_EXTRACT
))
6160 /* An operation that sets the condition codes as a side-effect, the
6161 V flag is not set correctly, so we can only use comparisons where
6162 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6164 if (GET_MODE (x
) == SImode
6166 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6167 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6168 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6169 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6170 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6171 || GET_CODE (x
) == LSHIFTRT
6172 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6173 || GET_CODE (x
) == ROTATERT
6174 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6177 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6180 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6181 && GET_CODE (x
) == PLUS
6182 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6188 /* X and Y are two things to compare using CODE. Emit the compare insn and
6189 return the rtx for register 0 in the proper mode. FP means this is a
6190 floating point compare: I don't think that it is needed on the arm. */
6192 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6194 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6195 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6197 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6198 gen_rtx_COMPARE (mode
, x
, y
)));
6203 /* Generate a sequence of insns that will generate the correct return
6204 address mask depending on the physical architecture that the program
6207 arm_gen_return_addr_mask (void)
6209 rtx reg
= gen_reg_rtx (Pmode
);
6211 emit_insn (gen_return_addr_mask (reg
));
6216 arm_reload_in_hi (rtx
*operands
)
6218 rtx ref
= operands
[1];
6220 HOST_WIDE_INT offset
= 0;
6222 if (GET_CODE (ref
) == SUBREG
)
6224 offset
= SUBREG_BYTE (ref
);
6225 ref
= SUBREG_REG (ref
);
6228 if (GET_CODE (ref
) == REG
)
6230 /* We have a pseudo which has been spilt onto the stack; there
6231 are two cases here: the first where there is a simple
6232 stack-slot replacement and a second where the stack-slot is
6233 out of range, or is used as a subreg. */
6234 if (reg_equiv_mem
[REGNO (ref
)])
6236 ref
= reg_equiv_mem
[REGNO (ref
)];
6237 base
= find_replacement (&XEXP (ref
, 0));
6240 /* The slot is out of range, or was dressed up in a SUBREG. */
6241 base
= reg_equiv_address
[REGNO (ref
)];
6244 base
= find_replacement (&XEXP (ref
, 0));
6246 /* Handle the case where the address is too complex to be offset by 1. */
6247 if (GET_CODE (base
) == MINUS
6248 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6250 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6252 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6255 else if (GET_CODE (base
) == PLUS
)
6257 /* The addend must be CONST_INT, or we would have dealt with it above. */
6258 HOST_WIDE_INT hi
, lo
;
6260 offset
+= INTVAL (XEXP (base
, 1));
6261 base
= XEXP (base
, 0);
6263 /* Rework the address into a legal sequence of insns. */
6264 /* Valid range for lo is -4095 -> 4095 */
6267 : -((-offset
) & 0xfff));
6269 /* Corner case, if lo is the max offset then we would be out of range
6270 once we have added the additional 1 below, so bump the msb into the
6271 pre-loading insn(s). */
6275 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6276 ^ (HOST_WIDE_INT
) 0x80000000)
6277 - (HOST_WIDE_INT
) 0x80000000);
6279 if (hi
+ lo
!= offset
)
6284 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6286 /* Get the base address; addsi3 knows how to handle constants
6287 that require more than one insn. */
6288 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6294 /* Operands[2] may overlap operands[0] (though it won't overlap
6295 operands[1]), that's why we asked for a DImode reg -- so we can
6296 use the bit that does not overlap. */
6297 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6298 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6300 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6302 emit_insn (gen_zero_extendqisi2 (scratch
,
6303 gen_rtx_MEM (QImode
,
6304 plus_constant (base
,
6306 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6307 gen_rtx_MEM (QImode
,
6308 plus_constant (base
,
6310 if (!BYTES_BIG_ENDIAN
)
6311 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6312 gen_rtx_IOR (SImode
,
6315 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6319 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6320 gen_rtx_IOR (SImode
,
6321 gen_rtx_ASHIFT (SImode
, scratch
,
6323 gen_rtx_SUBREG (SImode
, operands
[0],
6327 /* Handle storing a half-word to memory during reload by synthesizing as two
6328 byte stores. Take care not to clobber the input values until after we
6329 have moved them somewhere safe. This code assumes that if the DImode
6330 scratch in operands[2] overlaps either the input value or output address
6331 in some way, then that value must die in this insn (we absolutely need
6332 two scratch registers for some corner cases). */
6334 arm_reload_out_hi (rtx
*operands
)
6336 rtx ref
= operands
[0];
6337 rtx outval
= operands
[1];
6339 HOST_WIDE_INT offset
= 0;
6341 if (GET_CODE (ref
) == SUBREG
)
6343 offset
= SUBREG_BYTE (ref
);
6344 ref
= SUBREG_REG (ref
);
6347 if (GET_CODE (ref
) == REG
)
6349 /* We have a pseudo which has been spilt onto the stack; there
6350 are two cases here: the first where there is a simple
6351 stack-slot replacement and a second where the stack-slot is
6352 out of range, or is used as a subreg. */
6353 if (reg_equiv_mem
[REGNO (ref
)])
6355 ref
= reg_equiv_mem
[REGNO (ref
)];
6356 base
= find_replacement (&XEXP (ref
, 0));
6359 /* The slot is out of range, or was dressed up in a SUBREG. */
6360 base
= reg_equiv_address
[REGNO (ref
)];
6363 base
= find_replacement (&XEXP (ref
, 0));
6365 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6367 /* Handle the case where the address is too complex to be offset by 1. */
6368 if (GET_CODE (base
) == MINUS
6369 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6371 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6373 /* Be careful not to destroy OUTVAL. */
6374 if (reg_overlap_mentioned_p (base_plus
, outval
))
6376 /* Updating base_plus might destroy outval, see if we can
6377 swap the scratch and base_plus. */
6378 if (!reg_overlap_mentioned_p (scratch
, outval
))
6381 scratch
= base_plus
;
6386 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6388 /* Be conservative and copy OUTVAL into the scratch now,
6389 this should only be necessary if outval is a subreg
6390 of something larger than a word. */
6391 /* XXX Might this clobber base? I can't see how it can,
6392 since scratch is known to overlap with OUTVAL, and
6393 must be wider than a word. */
6394 emit_insn (gen_movhi (scratch_hi
, outval
));
6395 outval
= scratch_hi
;
6399 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6402 else if (GET_CODE (base
) == PLUS
)
6404 /* The addend must be CONST_INT, or we would have dealt with it above. */
6405 HOST_WIDE_INT hi
, lo
;
6407 offset
+= INTVAL (XEXP (base
, 1));
6408 base
= XEXP (base
, 0);
6410 /* Rework the address into a legal sequence of insns. */
6411 /* Valid range for lo is -4095 -> 4095 */
6414 : -((-offset
) & 0xfff));
6416 /* Corner case, if lo is the max offset then we would be out of range
6417 once we have added the additional 1 below, so bump the msb into the
6418 pre-loading insn(s). */
6422 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6423 ^ (HOST_WIDE_INT
) 0x80000000)
6424 - (HOST_WIDE_INT
) 0x80000000);
6426 if (hi
+ lo
!= offset
)
6431 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6433 /* Be careful not to destroy OUTVAL. */
6434 if (reg_overlap_mentioned_p (base_plus
, outval
))
6436 /* Updating base_plus might destroy outval, see if we
6437 can swap the scratch and base_plus. */
6438 if (!reg_overlap_mentioned_p (scratch
, outval
))
6441 scratch
= base_plus
;
6446 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6448 /* Be conservative and copy outval into scratch now,
6449 this should only be necessary if outval is a
6450 subreg of something larger than a word. */
6451 /* XXX Might this clobber base? I can't see how it
6452 can, since scratch is known to overlap with
6454 emit_insn (gen_movhi (scratch_hi
, outval
));
6455 outval
= scratch_hi
;
6459 /* Get the base address; addsi3 knows how to handle constants
6460 that require more than one insn. */
6461 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6467 if (BYTES_BIG_ENDIAN
)
6469 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6470 plus_constant (base
, offset
+ 1)),
6471 gen_lowpart (QImode
, outval
)));
6472 emit_insn (gen_lshrsi3 (scratch
,
6473 gen_rtx_SUBREG (SImode
, outval
, 0),
6475 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6476 gen_lowpart (QImode
, scratch
)));
6480 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6481 gen_lowpart (QImode
, outval
)));
6482 emit_insn (gen_lshrsi3 (scratch
,
6483 gen_rtx_SUBREG (SImode
, outval
, 0),
6485 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6486 plus_constant (base
, offset
+ 1)),
6487 gen_lowpart (QImode
, scratch
)));
6491 /* Print a symbolic form of X to the debug file, F. */
6493 arm_print_value (FILE *f
, rtx x
)
6495 switch (GET_CODE (x
))
6498 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6502 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6510 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6512 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6513 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6521 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6525 fprintf (f
, "`%s'", XSTR (x
, 0));
6529 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6533 arm_print_value (f
, XEXP (x
, 0));
6537 arm_print_value (f
, XEXP (x
, 0));
6539 arm_print_value (f
, XEXP (x
, 1));
6547 fprintf (f
, "????");
6552 /* Routines for manipulation of the constant pool. */
6554 /* Arm instructions cannot load a large constant directly into a
6555 register; they have to come from a pc relative load. The constant
6556 must therefore be placed in the addressable range of the pc
6557 relative load. Depending on the precise pc relative load
6558 instruction the range is somewhere between 256 bytes and 4k. This
6559 means that we often have to dump a constant inside a function, and
6560 generate code to branch around it.
6562 It is important to minimize this, since the branches will slow
6563 things down and make the code larger.
6565 Normally we can hide the table after an existing unconditional
6566 branch so that there is no interruption of the flow, but in the
6567 worst case the code looks like this:
6585 We fix this by performing a scan after scheduling, which notices
6586 which instructions need to have their operands fetched from the
6587 constant table and builds the table.
6589 The algorithm starts by building a table of all the constants that
6590 need fixing up and all the natural barriers in the function (places
6591 where a constant table can be dropped without breaking the flow).
6592 For each fixup we note how far the pc-relative replacement will be
6593 able to reach and the offset of the instruction into the function.
6595 Having built the table we then group the fixes together to form
6596 tables that are as large as possible (subject to addressing
6597 constraints) and emit each table of constants after the last
6598 barrier that is within range of all the instructions in the group.
6599 If a group does not contain a barrier, then we forcibly create one
6600 by inserting a jump instruction into the flow. Once the table has
6601 been inserted, the insns are then modified to reference the
6602 relevant entry in the pool.
6604 Possible enhancements to the algorithm (not implemented) are:
6606 1) For some processors and object formats, there may be benefit in
6607 aligning the pools to the start of cache lines; this alignment
6608 would need to be taken into account when calculating addressability
6611 /* These typedefs are located at the start of this file, so that
6612 they can be used in the prototypes there. This comment is to
6613 remind readers of that fact so that the following structures
6614 can be understood more easily.
6616 typedef struct minipool_node Mnode;
6617 typedef struct minipool_fixup Mfix; */
6619 struct minipool_node
6621 /* Doubly linked chain of entries. */
6624 /* The maximum offset into the code that this entry can be placed. While
6625 pushing fixes for forward references, all entries are sorted in order
6626 of increasing max_address. */
6627 HOST_WIDE_INT max_address
;
6628 /* Similarly for an entry inserted for a backwards ref. */
6629 HOST_WIDE_INT min_address
;
6630 /* The number of fixes referencing this entry. This can become zero
6631 if we "unpush" an entry. In this case we ignore the entry when we
6632 come to emit the code. */
6634 /* The offset from the start of the minipool. */
6635 HOST_WIDE_INT offset
;
6636 /* The value in table. */
6638 /* The mode of value. */
6639 enum machine_mode mode
;
6640 /* The size of the value. With iWMMXt enabled
6641 sizes > 4 also imply an alignment of 8-bytes. */
6645 struct minipool_fixup
6649 HOST_WIDE_INT address
;
6651 enum machine_mode mode
;
6655 HOST_WIDE_INT forwards
;
6656 HOST_WIDE_INT backwards
;
6659 /* Fixes less than a word need padding out to a word boundary. */
6660 #define MINIPOOL_FIX_SIZE(mode) \
6661 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6663 static Mnode
* minipool_vector_head
;
6664 static Mnode
* minipool_vector_tail
;
6665 static rtx minipool_vector_label
;
6667 /* The linked list of all minipool fixes required for this function. */
6668 Mfix
* minipool_fix_head
;
6669 Mfix
* minipool_fix_tail
;
6670 /* The fix entry for the current minipool, once it has been placed. */
6671 Mfix
* minipool_barrier
;
6673 /* Determines if INSN is the start of a jump table. Returns the end
6674 of the TABLE or NULL_RTX. */
6676 is_jump_table (rtx insn
)
6680 if (GET_CODE (insn
) == JUMP_INSN
6681 && JUMP_LABEL (insn
) != NULL
6682 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6683 == next_real_insn (insn
))
6685 && GET_CODE (table
) == JUMP_INSN
6686 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6687 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6693 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6694 #define JUMP_TABLES_IN_TEXT_SECTION 0
6697 static HOST_WIDE_INT
6698 get_jump_table_size (rtx insn
)
6700 /* ADDR_VECs only take room if read-only data does into the text
6702 if (JUMP_TABLES_IN_TEXT_SECTION
6703 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6708 rtx body
= PATTERN (insn
);
6709 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6711 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6717 /* Move a minipool fix MP from its current location to before MAX_MP.
6718 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6719 constraints may need updating. */
6721 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6722 HOST_WIDE_INT max_address
)
6724 /* This should never be true and the code below assumes these are
6731 if (max_address
< mp
->max_address
)
6732 mp
->max_address
= max_address
;
6736 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6737 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6739 mp
->max_address
= max_address
;
6741 /* Unlink MP from its current position. Since max_mp is non-null,
6742 mp->prev must be non-null. */
6743 mp
->prev
->next
= mp
->next
;
6744 if (mp
->next
!= NULL
)
6745 mp
->next
->prev
= mp
->prev
;
6747 minipool_vector_tail
= mp
->prev
;
6749 /* Re-insert it before MAX_MP. */
6751 mp
->prev
= max_mp
->prev
;
6754 if (mp
->prev
!= NULL
)
6755 mp
->prev
->next
= mp
;
6757 minipool_vector_head
= mp
;
6760 /* Save the new entry. */
6763 /* Scan over the preceding entries and adjust their addresses as
6765 while (mp
->prev
!= NULL
6766 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6768 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6775 /* Add a constant to the minipool for a forward reference. Returns the
6776 node added or NULL if the constant will not fit in this pool. */
6778 add_minipool_forward_ref (Mfix
*fix
)
6780 /* If set, max_mp is the first pool_entry that has a lower
6781 constraint than the one we are trying to add. */
6782 Mnode
* max_mp
= NULL
;
6783 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6786 /* If this fix's address is greater than the address of the first
6787 entry, then we can't put the fix in this pool. We subtract the
6788 size of the current fix to ensure that if the table is fully
6789 packed we still have enough room to insert this value by suffling
6790 the other fixes forwards. */
6791 if (minipool_vector_head
&&
6792 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
6795 /* Scan the pool to see if a constant with the same value has
6796 already been added. While we are doing this, also note the
6797 location where we must insert the constant if it doesn't already
6799 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6801 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6802 && fix
->mode
== mp
->mode
6803 && (GET_CODE (fix
->value
) != CODE_LABEL
6804 || (CODE_LABEL_NUMBER (fix
->value
)
6805 == CODE_LABEL_NUMBER (mp
->value
)))
6806 && rtx_equal_p (fix
->value
, mp
->value
))
6808 /* More than one fix references this entry. */
6810 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
6813 /* Note the insertion point if necessary. */
6815 && mp
->max_address
> max_address
)
6818 /* If we are inserting an 8-bytes aligned quantity and
6819 we have not already found an insertion point, then
6820 make sure that all such 8-byte aligned quantities are
6821 placed at the start of the pool. */
6822 if (ARM_DOUBLEWORD_ALIGN
6824 && fix
->fix_size
== 8
6825 && mp
->fix_size
!= 8)
6828 max_address
= mp
->max_address
;
6832 /* The value is not currently in the minipool, so we need to create
6833 a new entry for it. If MAX_MP is NULL, the entry will be put on
6834 the end of the list since the placement is less constrained than
6835 any existing entry. Otherwise, we insert the new fix before
6836 MAX_MP and, if necessary, adjust the constraints on the other
6838 mp
= xmalloc (sizeof (* mp
));
6839 mp
->fix_size
= fix
->fix_size
;
6840 mp
->mode
= fix
->mode
;
6841 mp
->value
= fix
->value
;
6843 /* Not yet required for a backwards ref. */
6844 mp
->min_address
= -65536;
6848 mp
->max_address
= max_address
;
6850 mp
->prev
= minipool_vector_tail
;
6852 if (mp
->prev
== NULL
)
6854 minipool_vector_head
= mp
;
6855 minipool_vector_label
= gen_label_rtx ();
6858 mp
->prev
->next
= mp
;
6860 minipool_vector_tail
= mp
;
6864 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6865 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6867 mp
->max_address
= max_address
;
6870 mp
->prev
= max_mp
->prev
;
6872 if (mp
->prev
!= NULL
)
6873 mp
->prev
->next
= mp
;
6875 minipool_vector_head
= mp
;
6878 /* Save the new entry. */
6881 /* Scan over the preceding entries and adjust their addresses as
6883 while (mp
->prev
!= NULL
6884 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6886 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6894 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
6895 HOST_WIDE_INT min_address
)
6897 HOST_WIDE_INT offset
;
6899 /* This should never be true, and the code below assumes these are
6906 if (min_address
> mp
->min_address
)
6907 mp
->min_address
= min_address
;
6911 /* We will adjust this below if it is too loose. */
6912 mp
->min_address
= min_address
;
6914 /* Unlink MP from its current position. Since min_mp is non-null,
6915 mp->next must be non-null. */
6916 mp
->next
->prev
= mp
->prev
;
6917 if (mp
->prev
!= NULL
)
6918 mp
->prev
->next
= mp
->next
;
6920 minipool_vector_head
= mp
->next
;
6922 /* Reinsert it after MIN_MP. */
6924 mp
->next
= min_mp
->next
;
6926 if (mp
->next
!= NULL
)
6927 mp
->next
->prev
= mp
;
6929 minipool_vector_tail
= mp
;
6935 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6937 mp
->offset
= offset
;
6938 if (mp
->refcount
> 0)
6939 offset
+= mp
->fix_size
;
6941 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6942 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6948 /* Add a constant to the minipool for a backward reference. Returns the
6949 node added or NULL if the constant will not fit in this pool.
6951 Note that the code for insertion for a backwards reference can be
6952 somewhat confusing because the calculated offsets for each fix do
6953 not take into account the size of the pool (which is still under
6956 add_minipool_backward_ref (Mfix
*fix
)
6958 /* If set, min_mp is the last pool_entry that has a lower constraint
6959 than the one we are trying to add. */
6960 Mnode
*min_mp
= NULL
;
6961 /* This can be negative, since it is only a constraint. */
6962 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
6965 /* If we can't reach the current pool from this insn, or if we can't
6966 insert this entry at the end of the pool without pushing other
6967 fixes out of range, then we don't try. This ensures that we
6968 can't fail later on. */
6969 if (min_address
>= minipool_barrier
->address
6970 || (minipool_vector_tail
->min_address
+ fix
->fix_size
6971 >= minipool_barrier
->address
))
6974 /* Scan the pool to see if a constant with the same value has
6975 already been added. While we are doing this, also note the
6976 location where we must insert the constant if it doesn't already
6978 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
6980 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6981 && fix
->mode
== mp
->mode
6982 && (GET_CODE (fix
->value
) != CODE_LABEL
6983 || (CODE_LABEL_NUMBER (fix
->value
)
6984 == CODE_LABEL_NUMBER (mp
->value
)))
6985 && rtx_equal_p (fix
->value
, mp
->value
)
6986 /* Check that there is enough slack to move this entry to the
6987 end of the table (this is conservative). */
6989 > (minipool_barrier
->address
6990 + minipool_vector_tail
->offset
6991 + minipool_vector_tail
->fix_size
)))
6994 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
6998 mp
->min_address
+= fix
->fix_size
;
7001 /* Note the insertion point if necessary. */
7002 if (mp
->min_address
< min_address
)
7004 /* For now, we do not allow the insertion of 8-byte alignment
7005 requiring nodes anywhere but at the start of the pool. */
7006 if (ARM_DOUBLEWORD_ALIGN
7007 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7012 else if (mp
->max_address
7013 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7015 /* Inserting before this entry would push the fix beyond
7016 its maximum address (which can happen if we have
7017 re-located a forwards fix); force the new fix to come
7020 min_address
= mp
->min_address
+ fix
->fix_size
;
7022 /* If we are inserting an 8-bytes aligned quantity and
7023 we have not already found an insertion point, then
7024 make sure that all such 8-byte aligned quantities are
7025 placed at the start of the pool. */
7026 else if (ARM_DOUBLEWORD_ALIGN
7028 && fix
->fix_size
== 8
7029 && mp
->fix_size
< 8)
7032 min_address
= mp
->min_address
+ fix
->fix_size
;
7037 /* We need to create a new entry. */
7038 mp
= xmalloc (sizeof (* mp
));
7039 mp
->fix_size
= fix
->fix_size
;
7040 mp
->mode
= fix
->mode
;
7041 mp
->value
= fix
->value
;
7043 mp
->max_address
= minipool_barrier
->address
+ 65536;
7045 mp
->min_address
= min_address
;
7050 mp
->next
= minipool_vector_head
;
7052 if (mp
->next
== NULL
)
7054 minipool_vector_tail
= mp
;
7055 minipool_vector_label
= gen_label_rtx ();
7058 mp
->next
->prev
= mp
;
7060 minipool_vector_head
= mp
;
7064 mp
->next
= min_mp
->next
;
7068 if (mp
->next
!= NULL
)
7069 mp
->next
->prev
= mp
;
7071 minipool_vector_tail
= mp
;
7074 /* Save the new entry. */
7082 /* Scan over the following entries and adjust their offsets. */
7083 while (mp
->next
!= NULL
)
7085 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7086 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7089 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7091 mp
->next
->offset
= mp
->offset
;
7100 assign_minipool_offsets (Mfix
*barrier
)
7102 HOST_WIDE_INT offset
= 0;
7105 minipool_barrier
= barrier
;
7107 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7109 mp
->offset
= offset
;
7111 if (mp
->refcount
> 0)
7112 offset
+= mp
->fix_size
;
7116 /* Output the literal table */
7118 dump_minipool (rtx scan
)
7124 if (ARM_DOUBLEWORD_ALIGN
)
7125 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7126 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7134 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7135 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7137 scan
= emit_label_after (gen_label_rtx (), scan
);
7138 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7139 scan
= emit_label_after (minipool_vector_label
, scan
);
7141 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7143 if (mp
->refcount
> 0)
7148 ";; Offset %u, min %ld, max %ld ",
7149 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7150 (unsigned long) mp
->max_address
);
7151 arm_print_value (dump_file
, mp
->value
);
7152 fputc ('\n', dump_file
);
7155 switch (mp
->fix_size
)
7157 #ifdef HAVE_consttable_1
7159 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7163 #ifdef HAVE_consttable_2
7165 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7169 #ifdef HAVE_consttable_4
7171 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7175 #ifdef HAVE_consttable_8
7177 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7191 minipool_vector_head
= minipool_vector_tail
= NULL
;
7192 scan
= emit_insn_after (gen_consttable_end (), scan
);
7193 scan
= emit_barrier_after (scan
);
7196 /* Return the cost of forcibly inserting a barrier after INSN. */
7198 arm_barrier_cost (rtx insn
)
7200 /* Basing the location of the pool on the loop depth is preferable,
7201 but at the moment, the basic block information seems to be
7202 corrupt by this stage of the compilation. */
7204 rtx next
= next_nonnote_insn (insn
);
7206 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7209 switch (GET_CODE (insn
))
7212 /* It will always be better to place the table before the label, rather
7221 return base_cost
- 10;
7224 return base_cost
+ 10;
7228 /* Find the best place in the insn stream in the range
7229 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7230 Create the barrier by inserting a jump and add a new fix entry for
7233 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7235 HOST_WIDE_INT count
= 0;
7237 rtx from
= fix
->insn
;
7238 rtx selected
= from
;
7240 HOST_WIDE_INT selected_address
;
7242 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7243 rtx label
= gen_label_rtx ();
7245 selected_cost
= arm_barrier_cost (from
);
7246 selected_address
= fix
->address
;
7248 while (from
&& count
< max_count
)
7253 /* This code shouldn't have been called if there was a natural barrier
7255 if (GET_CODE (from
) == BARRIER
)
7258 /* Count the length of this insn. */
7259 count
+= get_attr_length (from
);
7261 /* If there is a jump table, add its length. */
7262 tmp
= is_jump_table (from
);
7265 count
+= get_jump_table_size (tmp
);
7267 /* Jump tables aren't in a basic block, so base the cost on
7268 the dispatch insn. If we select this location, we will
7269 still put the pool after the table. */
7270 new_cost
= arm_barrier_cost (from
);
7272 if (count
< max_count
&& new_cost
<= selected_cost
)
7275 selected_cost
= new_cost
;
7276 selected_address
= fix
->address
+ count
;
7279 /* Continue after the dispatch table. */
7280 from
= NEXT_INSN (tmp
);
7284 new_cost
= arm_barrier_cost (from
);
7286 if (count
< max_count
&& new_cost
<= selected_cost
)
7289 selected_cost
= new_cost
;
7290 selected_address
= fix
->address
+ count
;
7293 from
= NEXT_INSN (from
);
7296 /* Create a new JUMP_INSN that branches around a barrier. */
7297 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7298 JUMP_LABEL (from
) = label
;
7299 barrier
= emit_barrier_after (from
);
7300 emit_label_after (label
, barrier
);
7302 /* Create a minipool barrier entry for the new barrier. */
7303 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7304 new_fix
->insn
= barrier
;
7305 new_fix
->address
= selected_address
;
7306 new_fix
->next
= fix
->next
;
7307 fix
->next
= new_fix
;
7312 /* Record that there is a natural barrier in the insn stream at
7315 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7317 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7320 fix
->address
= address
;
7323 if (minipool_fix_head
!= NULL
)
7324 minipool_fix_tail
->next
= fix
;
7326 minipool_fix_head
= fix
;
7328 minipool_fix_tail
= fix
;
7331 /* Record INSN, which will need fixing up to load a value from the
7332 minipool. ADDRESS is the offset of the insn since the start of the
7333 function; LOC is a pointer to the part of the insn which requires
7334 fixing; VALUE is the constant that must be loaded, which is of type
7337 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7338 enum machine_mode mode
, rtx value
)
7340 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7342 #ifdef AOF_ASSEMBLER
7343 /* PIC symbol references need to be converted into offsets into the
7345 /* XXX This shouldn't be done here. */
7346 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7347 value
= aof_pic_entry (value
);
7348 #endif /* AOF_ASSEMBLER */
7351 fix
->address
= address
;
7354 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7356 fix
->forwards
= get_attr_pool_range (insn
);
7357 fix
->backwards
= get_attr_neg_pool_range (insn
);
7358 fix
->minipool
= NULL
;
7360 /* If an insn doesn't have a range defined for it, then it isn't
7361 expecting to be reworked by this code. Better to abort now than
7362 to generate duff assembly code. */
7363 if (fix
->forwards
== 0 && fix
->backwards
== 0)
7366 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7367 So there might be an empty word before the start of the pool.
7368 Hence we reduce the forward range by 4 to allow for this
7370 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7376 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7377 GET_MODE_NAME (mode
),
7378 INSN_UID (insn
), (unsigned long) address
,
7379 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7380 arm_print_value (dump_file
, fix
->value
);
7381 fprintf (dump_file
, "\n");
7384 /* Add it to the chain of fixes. */
7387 if (minipool_fix_head
!= NULL
)
7388 minipool_fix_tail
->next
= fix
;
7390 minipool_fix_head
= fix
;
7392 minipool_fix_tail
= fix
;
7395 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7396 Returns the number of insns needed, or 99 if we don't know how to
7399 arm_const_double_inline_cost (rtx val
)
7401 rtx lowpart
, highpart
;
7402 enum machine_mode mode
;
7404 mode
= GET_MODE (val
);
7406 if (mode
== VOIDmode
)
7409 gcc_assert (GET_MODE_SIZE (mode
) == 8);
7411 lowpart
= gen_lowpart (SImode
, val
);
7412 highpart
= gen_highpart_mode (SImode
, mode
, val
);
7414 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
7415 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
7417 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
7418 NULL_RTX
, NULL_RTX
, 0, 0)
7419 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
7420 NULL_RTX
, NULL_RTX
, 0, 0));
7423 /* Return true if it is worthwhile to split a 64-bit constant into two
7424 32-bit operations. This is the case if optimizing for size, or
7425 if we have load delay slots, or if one 32-bit part can be done with
7426 a single data operation. */
7428 arm_const_double_by_parts (rtx val
)
7430 enum machine_mode mode
= GET_MODE (val
);
7433 if (optimize_size
|| arm_ld_sched
)
7436 if (mode
== VOIDmode
)
7439 part
= gen_highpart_mode (SImode
, mode
, val
);
7441 gcc_assert (GET_CODE (part
) == CONST_INT
);
7443 if (const_ok_for_arm (INTVAL (part
))
7444 || const_ok_for_arm (~INTVAL (part
)))
7447 part
= gen_lowpart (SImode
, val
);
7449 gcc_assert (GET_CODE (part
) == CONST_INT
);
7451 if (const_ok_for_arm (INTVAL (part
))
7452 || const_ok_for_arm (~INTVAL (part
)))
7458 /* Scan INSN and note any of its operands that need fixing.
7459 If DO_PUSHES is false we do not actually push any of the fixups
7460 needed. The function returns TRUE if any fixups were needed/pushed.
7461 This is used by arm_memory_load_p() which needs to know about loads
7462 of constants that will be converted into minipool loads. */
7464 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
7466 bool result
= false;
7469 extract_insn (insn
);
7471 if (!constrain_operands (1))
7472 fatal_insn_not_found (insn
);
7474 if (recog_data
.n_alternatives
== 0)
7477 /* Fill in recog_op_alt with information about the constraints of
7479 preprocess_constraints ();
7481 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7483 /* Things we need to fix can only occur in inputs. */
7484 if (recog_data
.operand_type
[opno
] != OP_IN
)
7487 /* If this alternative is a memory reference, then any mention
7488 of constants in this alternative is really to fool reload
7489 into allowing us to accept one there. We need to fix them up
7490 now so that we output the right code. */
7491 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
7493 rtx op
= recog_data
.operand
[opno
];
7495 if (CONSTANT_P (op
))
7498 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
7499 recog_data
.operand_mode
[opno
], op
);
7502 else if (GET_CODE (op
) == MEM
7503 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
7504 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
7508 rtx cop
= avoid_constant_pool_reference (op
);
7510 /* Casting the address of something to a mode narrower
7511 than a word can cause avoid_constant_pool_reference()
7512 to return the pool reference itself. That's no good to
7513 us here. Lets just hope that we can use the
7514 constant pool value directly. */
7516 cop
= get_pool_constant (XEXP (op
, 0));
7518 push_minipool_fix (insn
, address
,
7519 recog_data
.operand_loc
[opno
],
7520 recog_data
.operand_mode
[opno
], cop
);
7531 /* Gcc puts the pool in the wrong place for ARM, since we can only
7532 load addresses a limited distance around the pc. We do some
7533 special munging to move the constant pool values to the correct
7534 point in the code. */
7539 HOST_WIDE_INT address
= 0;
7542 minipool_fix_head
= minipool_fix_tail
= NULL
;
7544 /* The first insn must always be a note, or the code below won't
7545 scan it properly. */
7546 insn
= get_insns ();
7547 if (GET_CODE (insn
) != NOTE
)
7550 /* Scan all the insns and record the operands that will need fixing. */
7551 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7553 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7554 && (arm_cirrus_insn_p (insn
)
7555 || GET_CODE (insn
) == JUMP_INSN
7556 || arm_memory_load_p (insn
)))
7557 cirrus_reorg (insn
);
7559 if (GET_CODE (insn
) == BARRIER
)
7560 push_minipool_barrier (insn
, address
);
7561 else if (INSN_P (insn
))
7565 note_invalid_constants (insn
, address
, true);
7566 address
+= get_attr_length (insn
);
7568 /* If the insn is a vector jump, add the size of the table
7569 and skip the table. */
7570 if ((table
= is_jump_table (insn
)) != NULL
)
7572 address
+= get_jump_table_size (table
);
7578 fix
= minipool_fix_head
;
7580 /* Now scan the fixups and perform the required changes. */
7585 Mfix
* last_added_fix
;
7586 Mfix
* last_barrier
= NULL
;
7589 /* Skip any further barriers before the next fix. */
7590 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7593 /* No more fixes. */
7597 last_added_fix
= NULL
;
7599 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7601 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7603 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7606 last_barrier
= ftmp
;
7608 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7611 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7614 /* If we found a barrier, drop back to that; any fixes that we
7615 could have reached but come after the barrier will now go in
7616 the next mini-pool. */
7617 if (last_barrier
!= NULL
)
7619 /* Reduce the refcount for those fixes that won't go into this
7621 for (fdel
= last_barrier
->next
;
7622 fdel
&& fdel
!= ftmp
;
7625 fdel
->minipool
->refcount
--;
7626 fdel
->minipool
= NULL
;
7629 ftmp
= last_barrier
;
7633 /* ftmp is first fix that we can't fit into this pool and
7634 there no natural barriers that we could use. Insert a
7635 new barrier in the code somewhere between the previous
7636 fix and this one, and arrange to jump around it. */
7637 HOST_WIDE_INT max_address
;
7639 /* The last item on the list of fixes must be a barrier, so
7640 we can never run off the end of the list of fixes without
7641 last_barrier being set. */
7645 max_address
= minipool_vector_head
->max_address
;
7646 /* Check that there isn't another fix that is in range that
7647 we couldn't fit into this pool because the pool was
7648 already too large: we need to put the pool before such an
7650 if (ftmp
->address
< max_address
)
7651 max_address
= ftmp
->address
;
7653 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7656 assign_minipool_offsets (last_barrier
);
7660 if (GET_CODE (ftmp
->insn
) != BARRIER
7661 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7668 /* Scan over the fixes we have identified for this pool, fixing them
7669 up and adding the constants to the pool itself. */
7670 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7671 this_fix
= this_fix
->next
)
7672 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7675 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7676 minipool_vector_label
),
7677 this_fix
->minipool
->offset
);
7678 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7681 dump_minipool (last_barrier
->insn
);
7685 /* From now on we must synthesize any constants that we can't handle
7686 directly. This can happen if the RTL gets split during final
7687 instruction generation. */
7688 after_arm_reorg
= 1;
7690 /* Free the minipool memory. */
7691 obstack_free (&minipool_obstack
, minipool_startobj
);
7694 /* Routines to output assembly language. */
7696 /* If the rtx is the correct value then return the string of the number.
7697 In this way we can ensure that valid double constants are generated even
7698 when cross compiling. */
7700 fp_immediate_constant (rtx x
)
7705 if (!fp_consts_inited
)
7708 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7709 for (i
= 0; i
< 8; i
++)
7710 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7711 return strings_fp
[i
];
7716 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7718 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7722 if (!fp_consts_inited
)
7725 for (i
= 0; i
< 8; i
++)
7726 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
7727 return strings_fp
[i
];
7732 /* Output the operands of a LDM/STM instruction to STREAM.
7733 MASK is the ARM register set mask of which only bits 0-15 are important.
7734 REG is the base register, either the frame pointer or the stack pointer,
7735 INSTR is the possibly suffixed load or store instruction. */
7738 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
7742 bool not_first
= FALSE
;
7744 fputc ('\t', stream
);
7745 asm_fprintf (stream
, instr
, reg
);
7746 fputs (", {", stream
);
7748 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7749 if (mask
& (1 << i
))
7752 fprintf (stream
, ", ");
7754 asm_fprintf (stream
, "%r", i
);
7758 fprintf (stream
, "}\n");
7762 /* Output a FLDMX instruction to STREAM.
7763 BASE if the register containing the address.
7764 REG and COUNT specify the register range.
7765 Extra registers may be added to avoid hardware bugs. */
7768 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
7772 /* Workaround ARM10 VFPr1 bug. */
7773 if (count
== 2 && !arm_arch6
)
7780 fputc ('\t', stream
);
7781 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
7783 for (i
= reg
; i
< reg
+ count
; i
++)
7786 fputs (", ", stream
);
7787 asm_fprintf (stream
, "d%d", i
);
7789 fputs ("}\n", stream
);
7794 /* Output the assembly for a store multiple. */
7797 vfp_output_fstmx (rtx
* operands
)
7804 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
7805 p
= strlen (pattern
);
7807 if (GET_CODE (operands
[1]) != REG
)
7810 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
7811 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
7813 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
7815 strcpy (&pattern
[p
], "}");
7817 output_asm_insn (pattern
, operands
);
7822 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7823 number of bytes pushed. */
7826 vfp_emit_fstmx (int base_reg
, int count
)
7833 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7834 register pairs are stored by a store multiple insn. We avoid this
7835 by pushing an extra pair. */
7836 if (count
== 2 && !arm_arch6
)
7838 if (base_reg
== LAST_VFP_REGNUM
- 3)
7843 /* ??? The frame layout is implementation defined. We describe
7844 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7845 We really need some way of representing the whole block so that the
7846 unwinder can figure it out at runtime. */
7847 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7848 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
7850 reg
= gen_rtx_REG (DFmode
, base_reg
);
7854 = gen_rtx_SET (VOIDmode
,
7855 gen_rtx_MEM (BLKmode
,
7856 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7857 gen_rtx_UNSPEC (BLKmode
,
7861 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7862 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
7863 GEN_INT (-(count
* 8 + 4))));
7864 RTX_FRAME_RELATED_P (tmp
) = 1;
7865 XVECEXP (dwarf
, 0, 0) = tmp
;
7867 tmp
= gen_rtx_SET (VOIDmode
,
7868 gen_rtx_MEM (DFmode
, stack_pointer_rtx
),
7870 RTX_FRAME_RELATED_P (tmp
) = 1;
7871 XVECEXP (dwarf
, 0, 1) = tmp
;
7873 for (i
= 1; i
< count
; i
++)
7875 reg
= gen_rtx_REG (DFmode
, base_reg
);
7877 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
7879 tmp
= gen_rtx_SET (VOIDmode
,
7880 gen_rtx_MEM (DFmode
,
7881 gen_rtx_PLUS (SImode
,
7885 RTX_FRAME_RELATED_P (tmp
) = 1;
7886 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
7889 par
= emit_insn (par
);
7890 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
7892 RTX_FRAME_RELATED_P (par
) = 1;
7894 return count
* 8 + 4;
7898 /* Output a 'call' insn. */
7900 output_call (rtx
*operands
)
7903 abort (); /* Patterns should call blx <reg> directly. */
7905 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7906 if (REGNO (operands
[0]) == LR_REGNUM
)
7908 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
7909 output_asm_insn ("mov%?\t%0, %|lr", operands
);
7912 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7914 if (TARGET_INTERWORK
|| arm_arch4t
)
7915 output_asm_insn ("bx%?\t%0", operands
);
7917 output_asm_insn ("mov%?\t%|pc, %0", operands
);
7922 /* Output a 'call' insn that is a reference in memory. */
7924 output_call_mem (rtx
*operands
)
7926 if (TARGET_INTERWORK
&& !arm_arch5
)
7928 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7929 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7930 output_asm_insn ("bx%?\t%|ip", operands
);
7932 else if (regno_use_in (LR_REGNUM
, operands
[0]))
7934 /* LR is used in the memory address. We load the address in the
7935 first instruction. It's safe to use IP as the target of the
7936 load since the call will kill it anyway. */
7937 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7939 output_asm_insn ("blx%?\t%|ip", operands
);
7942 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7944 output_asm_insn ("bx%?\t%|ip", operands
);
7946 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
7951 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7952 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
7959 /* Output a move from arm registers to an fpa registers.
7960 OPERANDS[0] is an fpa register.
7961 OPERANDS[1] is the first registers of an arm register pair. */
7963 output_mov_long_double_fpa_from_arm (rtx
*operands
)
7965 int arm_reg0
= REGNO (operands
[1]);
7968 if (arm_reg0
== IP_REGNUM
)
7971 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7972 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7973 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7975 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7976 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
7981 /* Output a move from an fpa register to arm registers.
7982 OPERANDS[0] is the first registers of an arm register pair.
7983 OPERANDS[1] is an fpa register. */
7985 output_mov_long_double_arm_from_fpa (rtx
*operands
)
7987 int arm_reg0
= REGNO (operands
[0]);
7990 if (arm_reg0
== IP_REGNUM
)
7993 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7994 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7995 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7997 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
7998 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8002 /* Output a move from arm registers to arm registers of a long double
8003 OPERANDS[0] is the destination.
8004 OPERANDS[1] is the source. */
8006 output_mov_long_double_arm_from_arm (rtx
*operands
)
8008 /* We have to be careful here because the two might overlap. */
8009 int dest_start
= REGNO (operands
[0]);
8010 int src_start
= REGNO (operands
[1]);
8014 if (dest_start
< src_start
)
8016 for (i
= 0; i
< 3; i
++)
8018 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8019 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8020 output_asm_insn ("mov%?\t%0, %1", ops
);
8025 for (i
= 2; i
>= 0; i
--)
8027 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8028 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8029 output_asm_insn ("mov%?\t%0, %1", ops
);
8037 /* Output a move from arm registers to an fpa registers.
8038 OPERANDS[0] is an fpa register.
8039 OPERANDS[1] is the first registers of an arm register pair. */
8041 output_mov_double_fpa_from_arm (rtx
*operands
)
8043 int arm_reg0
= REGNO (operands
[1]);
8046 if (arm_reg0
== IP_REGNUM
)
8049 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8050 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8051 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8052 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8056 /* Output a move from an fpa register to arm registers.
8057 OPERANDS[0] is the first registers of an arm register pair.
8058 OPERANDS[1] is an fpa register. */
8060 output_mov_double_arm_from_fpa (rtx
*operands
)
8062 int arm_reg0
= REGNO (operands
[0]);
8065 if (arm_reg0
== IP_REGNUM
)
8068 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8069 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8070 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8071 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8075 /* Output a move between double words.
8076 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8077 or MEM<-REG and all MEMs must be offsettable addresses. */
8079 output_move_double (rtx
*operands
)
8081 enum rtx_code code0
= GET_CODE (operands
[0]);
8082 enum rtx_code code1
= GET_CODE (operands
[1]);
8087 int reg0
= REGNO (operands
[0]);
8089 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8093 switch (GET_CODE (XEXP (operands
[1], 0)))
8096 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8101 abort (); /* Should never happen now. */
8102 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8106 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8110 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8115 abort (); /* Should never happen now. */
8116 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8121 otherops
[0] = operands
[0];
8122 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8123 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8125 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8127 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8129 /* Registers overlap so split out the increment. */
8130 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8131 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8134 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8138 /* We only allow constant increments, so this is safe. */
8139 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8145 output_asm_insn ("adr%?\t%0, %1", operands
);
8146 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8150 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8151 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8153 otherops
[0] = operands
[0];
8154 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8155 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8157 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8159 if (GET_CODE (otherops
[2]) == CONST_INT
)
8161 switch ((int) INTVAL (otherops
[2]))
8164 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8167 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8170 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8175 && (GET_CODE (otherops
[2]) == REG
8176 || (GET_CODE (otherops
[2]) == CONST_INT
8177 && INTVAL (otherops
[2]) > -256
8178 && INTVAL (otherops
[2]) < 256)))
8180 if (reg_overlap_mentioned_p (otherops
[0],
8183 /* Swap base and index registers over to
8184 avoid a conflict. */
8185 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8186 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8189 /* If both registers conflict, it will usually
8190 have been fixed by a splitter. */
8191 if (reg_overlap_mentioned_p (otherops
[0],
8194 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8195 output_asm_insn ("ldr%?d\t%0, [%1]",
8201 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8206 if (GET_CODE (otherops
[2]) == CONST_INT
)
8208 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8209 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8211 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8214 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8217 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8219 return "ldm%?ia\t%0, %M0";
8223 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8224 /* Take care of overlapping base/data reg. */
8225 if (reg_mentioned_p (operands
[0], operands
[1]))
8227 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8228 output_asm_insn ("ldr%?\t%0, %1", operands
);
8232 output_asm_insn ("ldr%?\t%0, %1", operands
);
8233 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8239 abort (); /* Constraints should prevent this. */
8241 else if (code0
== MEM
&& code1
== REG
)
8243 if (REGNO (operands
[1]) == IP_REGNUM
)
8246 switch (GET_CODE (XEXP (operands
[0], 0)))
8249 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8254 abort (); /* Should never happen now. */
8255 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8259 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8263 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8268 abort (); /* Should never happen now. */
8269 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8274 otherops
[0] = operands
[1];
8275 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8276 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8278 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8279 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8281 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8285 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8286 if (GET_CODE (otherops
[2]) == CONST_INT
)
8288 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8291 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8295 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8299 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8304 && (GET_CODE (otherops
[2]) == REG
8305 || (GET_CODE (otherops
[2]) == CONST_INT
8306 && INTVAL (otherops
[2]) > -256
8307 && INTVAL (otherops
[2]) < 256)))
8309 otherops
[0] = operands
[1];
8310 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8311 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8317 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8318 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8319 output_asm_insn ("str%?\t%1, %0", operands
);
8320 output_asm_insn ("str%?\t%1, %0", otherops
);
8324 /* Constraints should prevent this. */
8330 /* Output an ADD r, s, #n where n may be too big for one instruction.
8331 If adding zero to one register, output nothing. */
8333 output_add_immediate (rtx
*operands
)
8335 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8337 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8340 output_multi_immediate (operands
,
8341 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8344 output_multi_immediate (operands
,
8345 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8352 /* Output a multiple immediate operation.
8353 OPERANDS is the vector of operands referred to in the output patterns.
8354 INSTR1 is the output pattern to use for the first constant.
8355 INSTR2 is the output pattern to use for subsequent constants.
8356 IMMED_OP is the index of the constant slot in OPERANDS.
8357 N is the constant value. */
8359 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8360 int immed_op
, HOST_WIDE_INT n
)
8362 #if HOST_BITS_PER_WIDE_INT > 32
8368 /* Quick and easy output. */
8369 operands
[immed_op
] = const0_rtx
;
8370 output_asm_insn (instr1
, operands
);
8375 const char * instr
= instr1
;
8377 /* Note that n is never zero here (which would give no output). */
8378 for (i
= 0; i
< 32; i
+= 2)
8382 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8383 output_asm_insn (instr
, operands
);
8393 /* Return the appropriate ARM instruction for the operation code.
8394 The returned result should not be overwritten. OP is the rtx of the
8395 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8398 arithmetic_instr (rtx op
, int shift_first_arg
)
8400 switch (GET_CODE (op
))
8406 return shift_first_arg
? "rsb" : "sub";
8422 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8423 for the operation code. The returned result should not be overwritten.
8424 OP is the rtx code of the shift.
8425 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8428 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8431 enum rtx_code code
= GET_CODE (op
);
8433 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
8435 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
8436 *amountp
= INTVAL (XEXP (op
, 1));
8457 *amountp
= 32 - *amountp
;
8466 /* We never have to worry about the amount being other than a
8467 power of 2, since this case can never be reloaded from a reg. */
8469 *amountp
= int_log2 (*amountp
);
8480 /* This is not 100% correct, but follows from the desire to merge
8481 multiplication by a power of 2 with the recognizer for a
8482 shift. >=32 is not a valid shift for "asl", so we must try and
8483 output a shift that produces the correct arithmetical result.
8484 Using lsr #32 is identical except for the fact that the carry bit
8485 is not set correctly if we set the flags; but we never use the
8486 carry bit from such an operation, so we can ignore that. */
8487 if (code
== ROTATERT
)
8488 /* Rotate is just modulo 32. */
8490 else if (*amountp
!= (*amountp
& 31))
8497 /* Shifts of 0 are no-ops. */
8505 /* Obtain the shift from the POWER of two. */
8507 static HOST_WIDE_INT
8508 int_log2 (HOST_WIDE_INT power
)
8510 HOST_WIDE_INT shift
= 0;
8512 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
8522 /* Output a .ascii pseudo-op, keeping track of lengths. This is
8523 because /bin/as is horribly restrictive. The judgement about
8524 whether or not each character is 'printable' (and can be output as
8525 is) or not (and must be printed with an octal escape) must be made
8526 with reference to the *host* character set -- the situation is
8527 similar to that discussed in the comments above pp_c_char in
8528 c-pretty-print.c. */
8530 #define MAX_ASCII_LEN 51
8533 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
8538 fputs ("\t.ascii\t\"", stream
);
8540 for (i
= 0; i
< len
; i
++)
8544 if (len_so_far
>= MAX_ASCII_LEN
)
8546 fputs ("\"\n\t.ascii\t\"", stream
);
8552 if (c
== '\\' || c
== '\"')
8554 putc ('\\', stream
);
8562 fprintf (stream
, "\\%03o", c
);
8567 fputs ("\"\n", stream
);
8570 /* Compute the register save mask for registers 0 through 12
8571 inclusive. This code is used by arm_compute_save_reg_mask. */
8573 static unsigned long
8574 arm_compute_save_reg0_reg12_mask (void)
8576 unsigned long func_type
= arm_current_func_type ();
8577 unsigned long save_reg_mask
= 0;
8580 if (IS_INTERRUPT (func_type
))
8582 unsigned int max_reg
;
8583 /* Interrupt functions must not corrupt any registers,
8584 even call clobbered ones. If this is a leaf function
8585 we can just examine the registers used by the RTL, but
8586 otherwise we have to assume that whatever function is
8587 called might clobber anything, and so we have to save
8588 all the call-clobbered registers as well. */
8589 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
8590 /* FIQ handlers have registers r8 - r12 banked, so
8591 we only need to check r0 - r7, Normal ISRs only
8592 bank r14 and r15, so we must check up to r12.
8593 r13 is the stack pointer which is always preserved,
8594 so we do not need to consider it here. */
8599 for (reg
= 0; reg
<= max_reg
; reg
++)
8600 if (regs_ever_live
[reg
]
8601 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
8602 save_reg_mask
|= (1 << reg
);
8604 /* Also save the pic base register if necessary. */
8606 && !TARGET_SINGLE_PIC_BASE
8607 && current_function_uses_pic_offset_table
)
8608 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8612 /* In the normal case we only need to save those registers
8613 which are call saved and which are used by this function. */
8614 for (reg
= 0; reg
<= 10; reg
++)
8615 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8616 save_reg_mask
|= (1 << reg
);
8618 /* Handle the frame pointer as a special case. */
8619 if (! TARGET_APCS_FRAME
8620 && ! frame_pointer_needed
8621 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
8622 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
8623 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
8625 /* If we aren't loading the PIC register,
8626 don't stack it even though it may be live. */
8628 && !TARGET_SINGLE_PIC_BASE
8629 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
8630 || current_function_uses_pic_offset_table
))
8631 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8634 /* Save registers so the exception handler can modify them. */
8635 if (current_function_calls_eh_return
)
8641 reg
= EH_RETURN_DATA_REGNO (i
);
8642 if (reg
== INVALID_REGNUM
)
8644 save_reg_mask
|= 1 << reg
;
8648 return save_reg_mask
;
8651 /* Compute a bit mask of which registers need to be
8652 saved on the stack for the current function. */
8654 static unsigned long
8655 arm_compute_save_reg_mask (void)
8657 unsigned int save_reg_mask
= 0;
8658 unsigned long func_type
= arm_current_func_type ();
8660 if (IS_NAKED (func_type
))
8661 /* This should never really happen. */
8664 /* If we are creating a stack frame, then we must save the frame pointer,
8665 IP (which will hold the old stack pointer), LR and the PC. */
8666 if (frame_pointer_needed
)
8668 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
8673 /* Volatile functions do not return, so there
8674 is no need to save any other registers. */
8675 if (IS_VOLATILE (func_type
))
8676 return save_reg_mask
;
8678 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
8680 /* Decide if we need to save the link register.
8681 Interrupt routines have their own banked link register,
8682 so they never need to save it.
8683 Otherwise if we do not use the link register we do not need to save
8684 it. If we are pushing other registers onto the stack however, we
8685 can save an instruction in the epilogue by pushing the link register
8686 now and then popping it back into the PC. This incurs extra memory
8687 accesses though, so we only do it when optimizing for size, and only
8688 if we know that we will not need a fancy return sequence. */
8689 if (regs_ever_live
[LR_REGNUM
]
8692 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8693 && !current_function_calls_eh_return
))
8694 save_reg_mask
|= 1 << LR_REGNUM
;
8696 if (cfun
->machine
->lr_save_eliminated
)
8697 save_reg_mask
&= ~ (1 << LR_REGNUM
);
8699 if (TARGET_REALLY_IWMMXT
8700 && ((bit_count (save_reg_mask
)
8701 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
8705 /* The total number of registers that are going to be pushed
8706 onto the stack is odd. We need to ensure that the stack
8707 is 64-bit aligned before we start to save iWMMXt registers,
8708 and also before we start to create locals. (A local variable
8709 might be a double or long long which we will load/store using
8710 an iWMMXt instruction). Therefore we need to push another
8711 ARM register, so that the stack will be 64-bit aligned. We
8712 try to avoid using the arg registers (r0 -r3) as they might be
8713 used to pass values in a tail call. */
8714 for (reg
= 4; reg
<= 12; reg
++)
8715 if ((save_reg_mask
& (1 << reg
)) == 0)
8719 save_reg_mask
|= (1 << reg
);
8722 cfun
->machine
->sibcall_blocked
= 1;
8723 save_reg_mask
|= (1 << 3);
8727 return save_reg_mask
;
8731 /* Compute a bit mask of which registers need to be
8732 saved on the stack for the current function. */
8733 static unsigned long
8734 thumb_compute_save_reg_mask (void)
8740 for (reg
= 0; reg
< 12; reg
++)
8741 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8744 if (flag_pic
&& !TARGET_SINGLE_PIC_BASE
)
8745 mask
|= (1 << PIC_OFFSET_TABLE_REGNUM
);
8747 if (TARGET_SINGLE_PIC_BASE
)
8748 mask
&= ~(1 << arm_pic_register
);
8750 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
8751 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
8752 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
8754 /* LR will also be pushed if any lo regs are pushed. */
8755 if (mask
& 0xff || thumb_force_lr_save ())
8756 mask
|= (1 << LR_REGNUM
);
8758 /* Make sure we have a low work register if we need one.
8759 We will need one if we are going to push a high register,
8760 but we are not currently intending to push a low register. */
8761 if ((mask
& 0xff) == 0
8762 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
8764 /* Use thumb_find_work_register to choose which register
8765 we will use. If the register is live then we will
8766 have to push it. Use LAST_LO_REGNUM as our fallback
8767 choice for the register to select. */
8768 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
8770 if (! call_used_regs
[reg
])
8778 /* Return the number of bytes required to save VFP registers. */
8780 arm_get_vfp_saved_size (void)
8787 /* Space for saved VFP registers. */
8788 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
8791 for (regno
= FIRST_VFP_REGNUM
;
8792 regno
< LAST_VFP_REGNUM
;
8795 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
8796 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
8800 /* Workaround ARM10 VFPr1 bug. */
8801 if (count
== 2 && !arm_arch6
)
8803 saved
+= count
* 8 + 4;
8812 if (count
== 2 && !arm_arch6
)
8814 saved
+= count
* 8 + 4;
8821 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8822 everything bar the final return instruction. */
8824 output_return_instruction (rtx operand
, int really_return
, int reverse
)
8826 char conditional
[10];
8829 unsigned long live_regs_mask
;
8830 unsigned long func_type
;
8831 arm_stack_offsets
*offsets
;
8833 func_type
= arm_current_func_type ();
8835 if (IS_NAKED (func_type
))
8838 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8840 /* If this function was declared non-returning, and we have
8841 found a tail call, then we have to trust that the called
8842 function won't return. */
8847 /* Otherwise, trap an attempted return by aborting. */
8849 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
8851 assemble_external_libcall (ops
[1]);
8852 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
8858 if (current_function_calls_alloca
&& !really_return
)
8861 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
8863 return_used_this_function
= 1;
8865 live_regs_mask
= arm_compute_save_reg_mask ();
8869 const char * return_reg
;
8871 /* If we do not have any special requirements for function exit
8872 (e.g. interworking, or ISR) then we can load the return address
8873 directly into the PC. Otherwise we must load it into LR. */
8875 && ! TARGET_INTERWORK
)
8876 return_reg
= reg_names
[PC_REGNUM
];
8878 return_reg
= reg_names
[LR_REGNUM
];
8880 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
8882 /* There are three possible reasons for the IP register
8883 being saved. 1) a stack frame was created, in which case
8884 IP contains the old stack pointer, or 2) an ISR routine
8885 corrupted it, or 3) it was saved to align the stack on
8886 iWMMXt. In case 1, restore IP into SP, otherwise just
8888 if (frame_pointer_needed
)
8890 live_regs_mask
&= ~ (1 << IP_REGNUM
);
8891 live_regs_mask
|= (1 << SP_REGNUM
);
8895 if (! IS_INTERRUPT (func_type
)
8896 && ! TARGET_REALLY_IWMMXT
)
8901 /* On some ARM architectures it is faster to use LDR rather than
8902 LDM to load a single register. On other architectures, the
8903 cost is the same. In 26 bit mode, or for exception handlers,
8904 we have to use LDM to load the PC so that the CPSR is also
8906 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8907 if (live_regs_mask
== (1U << reg
))
8910 if (reg
<= LAST_ARM_REGNUM
8911 && (reg
!= LR_REGNUM
8913 || ! IS_INTERRUPT (func_type
)))
8915 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
8916 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
8923 /* Generate the load multiple instruction to restore the
8924 registers. Note we can get here, even if
8925 frame_pointer_needed is true, but only if sp already
8926 points to the base of the saved core registers. */
8927 if (live_regs_mask
& (1 << SP_REGNUM
))
8929 unsigned HOST_WIDE_INT stack_adjust
;
8931 offsets
= arm_get_frame_offsets ();
8932 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
8933 if (stack_adjust
!= 0 && stack_adjust
!= 4)
8936 if (stack_adjust
&& arm_arch5
)
8937 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
8940 /* If we can't use ldmib (SA110 bug),
8941 then try to pop r3 instead. */
8943 live_regs_mask
|= 1 << 3;
8944 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
8948 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
8950 p
= instr
+ strlen (instr
);
8952 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
8953 if (live_regs_mask
& (1 << reg
))
8955 int l
= strlen (reg_names
[reg
]);
8961 memcpy (p
, ", ", 2);
8965 memcpy (p
, "%|", 2);
8966 memcpy (p
+ 2, reg_names
[reg
], l
);
8970 if (live_regs_mask
& (1 << LR_REGNUM
))
8972 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
8973 /* If returning from an interrupt, restore the CPSR. */
8974 if (IS_INTERRUPT (func_type
))
8981 output_asm_insn (instr
, & operand
);
8983 /* See if we need to generate an extra instruction to
8984 perform the actual function return. */
8986 && func_type
!= ARM_FT_INTERWORKED
8987 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8989 /* The return has already been handled
8990 by loading the LR into the PC. */
8997 switch ((int) ARM_FUNC_TYPE (func_type
))
9001 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9004 case ARM_FT_INTERWORKED
:
9005 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9008 case ARM_FT_EXCEPTION
:
9009 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9013 /* Use bx if it's available. */
9014 if (arm_arch5
|| arm_arch4t
)
9015 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9017 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9021 output_asm_insn (instr
, & operand
);
9027 /* Write the function name into the code section, directly preceding
9028 the function prologue.
9030 Code will be output similar to this:
9032 .ascii "arm_poke_function_name", 0
9035 .word 0xff000000 + (t1 - t0)
9036 arm_poke_function_name
9038 stmfd sp!, {fp, ip, lr, pc}
9041 When performing a stack backtrace, code can inspect the value
9042 of 'pc' stored at 'fp' + 0. If the trace function then looks
9043 at location pc - 12 and the top 8 bits are set, then we know
9044 that there is a function name embedded immediately preceding this
9045 location and has length ((pc[-3]) & 0xff000000).
9047 We assume that pc is declared as a pointer to an unsigned long.
9049 It is of no benefit to output the function name if we are assembling
9050 a leaf function. These function types will not contain a stack
9051 backtrace structure, therefore it is not possible to determine the
9054 arm_poke_function_name (FILE *stream
, const char *name
)
9056 unsigned long alignlength
;
9057 unsigned long length
;
9060 length
= strlen (name
) + 1;
9061 alignlength
= ROUND_UP_WORD (length
);
9063 ASM_OUTPUT_ASCII (stream
, name
, length
);
9064 ASM_OUTPUT_ALIGN (stream
, 2);
9065 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9066 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9069 /* Place some comments into the assembler stream
9070 describing the current function. */
9072 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9074 unsigned long func_type
;
9078 thumb_output_function_prologue (f
, frame_size
);
9083 if (arm_ccfsm_state
|| arm_target_insn
)
9086 func_type
= arm_current_func_type ();
9088 switch ((int) ARM_FUNC_TYPE (func_type
))
9093 case ARM_FT_INTERWORKED
:
9094 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9097 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9100 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9102 case ARM_FT_EXCEPTION
:
9103 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9107 if (IS_NAKED (func_type
))
9108 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9110 if (IS_VOLATILE (func_type
))
9111 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9113 if (IS_NESTED (func_type
))
9114 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9116 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9117 current_function_args_size
,
9118 current_function_pretend_args_size
, frame_size
);
9120 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9121 frame_pointer_needed
,
9122 cfun
->machine
->uses_anonymous_args
);
9124 if (cfun
->machine
->lr_save_eliminated
)
9125 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9127 if (current_function_calls_eh_return
)
9128 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9130 #ifdef AOF_ASSEMBLER
9132 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9135 return_used_this_function
= 0;
9139 arm_output_epilogue (rtx sibling
)
9142 unsigned long saved_regs_mask
;
9143 unsigned long func_type
;
9144 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9145 frame that is $fp + 4 for a non-variadic function. */
9146 int floats_offset
= 0;
9148 FILE * f
= asm_out_file
;
9149 unsigned int lrm_count
= 0;
9150 int really_return
= (sibling
== NULL
);
9152 arm_stack_offsets
*offsets
;
9154 /* If we have already generated the return instruction
9155 then it is futile to generate anything else. */
9156 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9159 func_type
= arm_current_func_type ();
9161 if (IS_NAKED (func_type
))
9162 /* Naked functions don't have epilogues. */
9165 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9169 /* A volatile function should never return. Call abort. */
9170 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9171 assemble_external_libcall (op
);
9172 output_asm_insn ("bl\t%a0", &op
);
9177 if (current_function_calls_eh_return
9179 /* If we are throwing an exception, then we really must
9180 be doing a return, so we can't tail-call. */
9183 offsets
= arm_get_frame_offsets ();
9184 saved_regs_mask
= arm_compute_save_reg_mask ();
9187 lrm_count
= bit_count (saved_regs_mask
);
9189 floats_offset
= offsets
->saved_args
;
9190 /* Compute how far away the floats will be. */
9191 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9192 if (saved_regs_mask
& (1 << reg
))
9195 if (frame_pointer_needed
)
9197 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9198 int vfp_offset
= offsets
->frame
;
9200 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9202 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9203 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9205 floats_offset
+= 12;
9206 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9207 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9212 start_reg
= LAST_FPA_REGNUM
;
9214 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9216 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9218 floats_offset
+= 12;
9220 /* We can't unstack more than four registers at once. */
9221 if (start_reg
- reg
== 3)
9223 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9224 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9225 start_reg
= reg
- 1;
9230 if (reg
!= start_reg
)
9231 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9232 reg
+ 1, start_reg
- reg
,
9233 FP_REGNUM
, floats_offset
- vfp_offset
);
9234 start_reg
= reg
- 1;
9238 /* Just in case the last register checked also needs unstacking. */
9239 if (reg
!= start_reg
)
9240 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9241 reg
+ 1, start_reg
- reg
,
9242 FP_REGNUM
, floats_offset
- vfp_offset
);
9245 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9249 /* The fldmx insn does not have base+offset addressing modes,
9250 so we use IP to hold the address. */
9251 saved_size
= arm_get_vfp_saved_size ();
9255 floats_offset
+= saved_size
;
9256 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9257 FP_REGNUM
, floats_offset
- vfp_offset
);
9259 start_reg
= FIRST_VFP_REGNUM
;
9260 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9262 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9263 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9265 if (start_reg
!= reg
)
9266 arm_output_fldmx (f
, IP_REGNUM
,
9267 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9268 (reg
- start_reg
) / 2);
9269 start_reg
= reg
+ 2;
9272 if (start_reg
!= reg
)
9273 arm_output_fldmx (f
, IP_REGNUM
,
9274 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9275 (reg
- start_reg
) / 2);
9280 /* The frame pointer is guaranteed to be non-double-word aligned.
9281 This is because it is set to (old_stack_pointer - 4) and the
9282 old_stack_pointer was double word aligned. Thus the offset to
9283 the iWMMXt registers to be loaded must also be non-double-word
9284 sized, so that the resultant address *is* double-word aligned.
9285 We can ignore floats_offset since that was already included in
9286 the live_regs_mask. */
9287 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9289 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9290 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9292 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9293 reg
, FP_REGNUM
, lrm_count
* 4);
9298 /* saved_regs_mask should contain the IP, which at the time of stack
9299 frame generation actually contains the old stack pointer. So a
9300 quick way to unwind the stack is just pop the IP register directly
9301 into the stack pointer. */
9302 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
9304 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9305 saved_regs_mask
|= (1 << SP_REGNUM
);
9307 /* There are two registers left in saved_regs_mask - LR and PC. We
9308 only need to restore the LR register (the return address), but to
9309 save time we can load it directly into the PC, unless we need a
9310 special function exit sequence, or we are not really returning. */
9312 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9313 && !current_function_calls_eh_return
)
9314 /* Delete the LR from the register mask, so that the LR on
9315 the stack is loaded into the PC in the register mask. */
9316 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9318 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9320 /* We must use SP as the base register, because SP is one of the
9321 registers being restored. If an interrupt or page fault
9322 happens in the ldm instruction, the SP might or might not
9323 have been restored. That would be bad, as then SP will no
9324 longer indicate the safe area of stack, and we can get stack
9325 corruption. Using SP as the base register means that it will
9326 be reset correctly to the original value, should an interrupt
9327 occur. If the stack pointer already points at the right
9328 place, then omit the subtraction. */
9329 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9330 || current_function_calls_alloca
)
9331 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9332 4 * bit_count (saved_regs_mask
));
9333 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9335 if (IS_INTERRUPT (func_type
))
9336 /* Interrupt handlers will have pushed the
9337 IP onto the stack, so restore it now. */
9338 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9342 /* Restore stack pointer if necessary. */
9343 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9345 operands
[0] = operands
[1] = stack_pointer_rtx
;
9346 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9347 output_add_immediate (operands
);
9350 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9352 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9353 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9354 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9359 start_reg
= FIRST_FPA_REGNUM
;
9361 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9363 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9365 if (reg
- start_reg
== 3)
9367 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9368 start_reg
, SP_REGNUM
);
9369 start_reg
= reg
+ 1;
9374 if (reg
!= start_reg
)
9375 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9376 start_reg
, reg
- start_reg
,
9379 start_reg
= reg
+ 1;
9383 /* Just in case the last register checked also needs unstacking. */
9384 if (reg
!= start_reg
)
9385 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9386 start_reg
, reg
- start_reg
, SP_REGNUM
);
9389 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9391 start_reg
= FIRST_VFP_REGNUM
;
9392 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9394 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9395 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9397 if (start_reg
!= reg
)
9398 arm_output_fldmx (f
, SP_REGNUM
,
9399 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9400 (reg
- start_reg
) / 2);
9401 start_reg
= reg
+ 2;
9404 if (start_reg
!= reg
)
9405 arm_output_fldmx (f
, SP_REGNUM
,
9406 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9407 (reg
- start_reg
) / 2);
9410 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9411 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9412 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9414 /* If we can, restore the LR into the PC. */
9415 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9417 && current_function_pretend_args_size
== 0
9418 && saved_regs_mask
& (1 << LR_REGNUM
)
9419 && !current_function_calls_eh_return
)
9421 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9422 saved_regs_mask
|= (1 << PC_REGNUM
);
9425 /* Load the registers off the stack. If we only have one register
9426 to load use the LDR instruction - it is faster. */
9427 if (saved_regs_mask
== (1 << LR_REGNUM
))
9429 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9431 else if (saved_regs_mask
)
9433 if (saved_regs_mask
& (1 << SP_REGNUM
))
9434 /* Note - write back to the stack register is not enabled
9435 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9436 in the list of registers and if we add writeback the
9437 instruction becomes UNPREDICTABLE. */
9438 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9440 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9443 if (current_function_pretend_args_size
)
9445 /* Unwind the pre-pushed regs. */
9446 operands
[0] = operands
[1] = stack_pointer_rtx
;
9447 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9448 output_add_immediate (operands
);
9452 /* We may have already restored PC directly from the stack. */
9453 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
9456 /* Stack adjustment for exception handler. */
9457 if (current_function_calls_eh_return
)
9458 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
9459 ARM_EH_STACKADJ_REGNUM
);
9461 /* Generate the return instruction. */
9462 switch ((int) ARM_FUNC_TYPE (func_type
))
9466 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
9469 case ARM_FT_EXCEPTION
:
9470 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9473 case ARM_FT_INTERWORKED
:
9474 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9478 if (arm_arch5
|| arm_arch4t
)
9479 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9481 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9489 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9490 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
9492 arm_stack_offsets
*offsets
;
9498 /* Emit any call-via-reg trampolines that are needed for v4t support
9499 of call_reg and call_value_reg type insns. */
9500 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
9502 rtx label
= cfun
->machine
->call_via
[regno
];
9506 function_section (current_function_decl
);
9507 targetm
.asm_out
.internal_label (asm_out_file
, "L",
9508 CODE_LABEL_NUMBER (label
));
9509 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
9513 /* ??? Probably not safe to set this here, since it assumes that a
9514 function will be emitted as assembly immediately after we generate
9515 RTL for it. This does not happen for inline functions. */
9516 return_used_this_function
= 0;
9520 /* We need to take into account any stack-frame rounding. */
9521 offsets
= arm_get_frame_offsets ();
9523 if (use_return_insn (FALSE
, NULL
)
9524 && return_used_this_function
9525 && offsets
->saved_regs
!= offsets
->outgoing_args
9526 && !frame_pointer_needed
)
9529 /* Reset the ARM-specific per-function variables. */
9530 after_arm_reorg
= 0;
9534 /* Generate and emit an insn that we will recognize as a push_multi.
9535 Unfortunately, since this insn does not reflect very well the actual
9536 semantics of the operation, we need to annotate the insn for the benefit
9537 of DWARF2 frame unwind information. */
9539 emit_multi_reg_push (unsigned long mask
)
9546 int dwarf_par_index
;
9549 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9550 if (mask
& (1 << i
))
9553 if (num_regs
== 0 || num_regs
> 16)
9556 /* We don't record the PC in the dwarf frame information. */
9557 num_dwarf_regs
= num_regs
;
9558 if (mask
& (1 << PC_REGNUM
))
9561 /* For the body of the insn we are going to generate an UNSPEC in
9562 parallel with several USEs. This allows the insn to be recognized
9563 by the push_multi pattern in the arm.md file. The insn looks
9564 something like this:
9567 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9568 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9569 (use (reg:SI 11 fp))
9570 (use (reg:SI 12 ip))
9571 (use (reg:SI 14 lr))
9572 (use (reg:SI 15 pc))
9575 For the frame note however, we try to be more explicit and actually
9576 show each register being stored into the stack frame, plus a (single)
9577 decrement of the stack pointer. We do it this way in order to be
9578 friendly to the stack unwinding code, which only wants to see a single
9579 stack decrement per instruction. The RTL we generate for the note looks
9580 something like this:
9583 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9584 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9585 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9586 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9587 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9590 This sequence is used both by the code to support stack unwinding for
9591 exceptions handlers and the code to generate dwarf2 frame debugging. */
9593 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
9594 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
9595 dwarf_par_index
= 1;
9597 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9599 if (mask
& (1 << i
))
9601 reg
= gen_rtx_REG (SImode
, i
);
9604 = gen_rtx_SET (VOIDmode
,
9605 gen_rtx_MEM (BLKmode
,
9606 gen_rtx_PRE_DEC (BLKmode
,
9607 stack_pointer_rtx
)),
9608 gen_rtx_UNSPEC (BLKmode
,
9614 tmp
= gen_rtx_SET (VOIDmode
,
9615 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
9617 RTX_FRAME_RELATED_P (tmp
) = 1;
9618 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
9626 for (j
= 1, i
++; j
< num_regs
; i
++)
9628 if (mask
& (1 << i
))
9630 reg
= gen_rtx_REG (SImode
, i
);
9632 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
9636 tmp
= gen_rtx_SET (VOIDmode
,
9637 gen_rtx_MEM (SImode
,
9638 plus_constant (stack_pointer_rtx
,
9641 RTX_FRAME_RELATED_P (tmp
) = 1;
9642 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
9649 par
= emit_insn (par
);
9651 tmp
= gen_rtx_SET (SImode
,
9653 gen_rtx_PLUS (SImode
,
9655 GEN_INT (-4 * num_regs
)));
9656 RTX_FRAME_RELATED_P (tmp
) = 1;
9657 XVECEXP (dwarf
, 0, 0) = tmp
;
9659 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9665 emit_sfm (int base_reg
, int count
)
9672 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
9673 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
9675 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9678 = gen_rtx_SET (VOIDmode
,
9679 gen_rtx_MEM (BLKmode
,
9680 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
9681 gen_rtx_UNSPEC (BLKmode
,
9684 tmp
= gen_rtx_SET (VOIDmode
,
9685 gen_rtx_MEM (XFmode
, stack_pointer_rtx
), reg
);
9686 RTX_FRAME_RELATED_P (tmp
) = 1;
9687 XVECEXP (dwarf
, 0, 1) = tmp
;
9689 for (i
= 1; i
< count
; i
++)
9691 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9692 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
9694 tmp
= gen_rtx_SET (VOIDmode
,
9695 gen_rtx_MEM (XFmode
,
9696 plus_constant (stack_pointer_rtx
,
9699 RTX_FRAME_RELATED_P (tmp
) = 1;
9700 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
9703 tmp
= gen_rtx_SET (VOIDmode
,
9705 gen_rtx_PLUS (SImode
,
9707 GEN_INT (-12 * count
)));
9708 RTX_FRAME_RELATED_P (tmp
) = 1;
9709 XVECEXP (dwarf
, 0, 0) = tmp
;
9711 par
= emit_insn (par
);
9712 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9718 /* Return true if the current function needs to save/restore LR. */
9721 thumb_force_lr_save (void)
9723 return !cfun
->machine
->lr_save_eliminated
9724 && (!leaf_function_p ()
9725 || thumb_far_jump_used_p ()
9726 || regs_ever_live
[LR_REGNUM
]);
9730 /* Compute the distance from register FROM to register TO.
9731 These can be the arg pointer (26), the soft frame pointer (25),
9732 the stack pointer (13) or the hard frame pointer (11).
9733 In thumb mode r7 is used as the soft frame pointer, if needed.
9734 Typical stack layout looks like this:
9736 old stack pointer -> | |
9739 | | saved arguments for
9740 | | vararg functions
9743 hard FP & arg pointer -> | | \
9751 soft frame pointer -> | | /
9761 current stack pointer -> | | /
9764 For a given function some or all of these stack components
9765 may not be needed, giving rise to the possibility of
9766 eliminating some of the registers.
9768 The values returned by this function must reflect the behavior
9769 of arm_expand_prologue() and arm_compute_save_reg_mask().
9771 The sign of the number returned reflects the direction of stack
9772 growth, so the values are positive for all eliminations except
9773 from the soft frame pointer to the hard frame pointer.
9775 SFP may point just inside the local variables block to ensure correct
9779 /* Calculate stack offsets. These are used to calculate register elimination
9780 offsets and in prologue/epilogue code. */
9782 static arm_stack_offsets
*
9783 arm_get_frame_offsets (void)
9785 struct arm_stack_offsets
*offsets
;
9786 unsigned long func_type
;
9789 HOST_WIDE_INT frame_size
;
9791 offsets
= &cfun
->machine
->stack_offsets
;
9793 /* We need to know if we are a leaf function. Unfortunately, it
9794 is possible to be called after start_sequence has been called,
9795 which causes get_insns to return the insns for the sequence,
9796 not the function, which will cause leaf_function_p to return
9797 the incorrect result.
9799 to know about leaf functions once reload has completed, and the
9800 frame size cannot be changed after that time, so we can safely
9801 use the cached value. */
9803 if (reload_completed
)
9806 /* Initially this is the size of the local variables. It will translated
9807 into an offset once we have determined the size of preceding data. */
9808 frame_size
= ROUND_UP_WORD (get_frame_size ());
9810 leaf
= leaf_function_p ();
9812 /* Space for variadic functions. */
9813 offsets
->saved_args
= current_function_pretend_args_size
;
9815 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
9821 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
9823 /* We know that SP will be doubleword aligned on entry, and we must
9824 preserve that condition at any subroutine call. We also require the
9825 soft frame pointer to be doubleword aligned. */
9827 if (TARGET_REALLY_IWMMXT
)
9829 /* Check for the call-saved iWMMXt registers. */
9830 for (regno
= FIRST_IWMMXT_REGNUM
;
9831 regno
<= LAST_IWMMXT_REGNUM
;
9833 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9837 func_type
= arm_current_func_type ();
9838 if (! IS_VOLATILE (func_type
))
9840 /* Space for saved FPA registers. */
9841 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
9842 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9845 /* Space for saved VFP registers. */
9846 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9847 saved
+= arm_get_vfp_saved_size ();
9850 else /* TARGET_THUMB */
9852 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
9853 if (TARGET_BACKTRACE
)
9857 /* Saved registers include the stack frame. */
9858 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
9859 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
9860 /* A leaf function does not need any stack alignment if it has nothing
9862 if (leaf
&& frame_size
== 0)
9864 offsets
->outgoing_args
= offsets
->soft_frame
;
9868 /* Ensure SFP has the correct alignment. */
9869 if (ARM_DOUBLEWORD_ALIGN
9870 && (offsets
->soft_frame
& 7))
9871 offsets
->soft_frame
+= 4;
9873 offsets
->outgoing_args
= offsets
->soft_frame
+ frame_size
9874 + current_function_outgoing_args_size
;
9876 if (ARM_DOUBLEWORD_ALIGN
)
9878 /* Ensure SP remains doubleword aligned. */
9879 if (offsets
->outgoing_args
& 7)
9880 offsets
->outgoing_args
+= 4;
9881 if (offsets
->outgoing_args
& 7)
9889 /* Calculate the relative offsets for the different stack pointers. Positive
9890 offsets are in the direction of stack growth. */
9893 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
9895 arm_stack_offsets
*offsets
;
9897 offsets
= arm_get_frame_offsets ();
9899 /* OK, now we have enough information to compute the distances.
9900 There must be an entry in these switch tables for each pair
9901 of registers in ELIMINABLE_REGS, even if some of the entries
9902 seem to be redundant or useless. */
9905 case ARG_POINTER_REGNUM
:
9908 case THUMB_HARD_FRAME_POINTER_REGNUM
:
9911 case FRAME_POINTER_REGNUM
:
9912 /* This is the reverse of the soft frame pointer
9913 to hard frame pointer elimination below. */
9914 return offsets
->soft_frame
- offsets
->saved_args
;
9916 case ARM_HARD_FRAME_POINTER_REGNUM
:
9917 /* If there is no stack frame then the hard
9918 frame pointer and the arg pointer coincide. */
9919 if (offsets
->frame
== offsets
->saved_regs
)
9921 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9922 return (frame_pointer_needed
9923 && cfun
->static_chain_decl
!= NULL
9924 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
9926 case STACK_POINTER_REGNUM
:
9927 /* If nothing has been pushed on the stack at all
9928 then this will return -4. This *is* correct! */
9929 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
9936 case FRAME_POINTER_REGNUM
:
9939 case THUMB_HARD_FRAME_POINTER_REGNUM
:
9942 case ARM_HARD_FRAME_POINTER_REGNUM
:
9943 /* The hard frame pointer points to the top entry in the
9944 stack frame. The soft frame pointer to the bottom entry
9945 in the stack frame. If there is no stack frame at all,
9946 then they are identical. */
9948 return offsets
->frame
- offsets
->soft_frame
;
9950 case STACK_POINTER_REGNUM
:
9951 return offsets
->outgoing_args
- offsets
->soft_frame
;
9959 /* You cannot eliminate from the stack pointer.
9960 In theory you could eliminate from the hard frame
9961 pointer to the stack pointer, but this will never
9962 happen, since if a stack frame is not needed the
9963 hard frame pointer will never be used. */
9969 /* Generate the prologue instructions for entry into an ARM function. */
9971 arm_expand_prologue (void)
9977 unsigned long live_regs_mask
;
9978 unsigned long func_type
;
9980 int saved_pretend_args
= 0;
9982 unsigned HOST_WIDE_INT args_to_push
;
9983 arm_stack_offsets
*offsets
;
9985 func_type
= arm_current_func_type ();
9987 /* Naked functions don't have prologues. */
9988 if (IS_NAKED (func_type
))
9991 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9992 args_to_push
= current_function_pretend_args_size
;
9994 /* Compute which register we will have to save onto the stack. */
9995 live_regs_mask
= arm_compute_save_reg_mask ();
9997 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
9999 if (frame_pointer_needed
)
10001 if (IS_INTERRUPT (func_type
))
10003 /* Interrupt functions must not corrupt any registers.
10004 Creating a frame pointer however, corrupts the IP
10005 register, so we must push it first. */
10006 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10008 /* Do not set RTX_FRAME_RELATED_P on this insn.
10009 The dwarf stack unwinding code only wants to see one
10010 stack decrement per function, and this is not it. If
10011 this instruction is labeled as being part of the frame
10012 creation sequence then dwarf2out_frame_debug_expr will
10013 abort when it encounters the assignment of IP to FP
10014 later on, since the use of SP here establishes SP as
10015 the CFA register and not IP.
10017 Anyway this instruction is not really part of the stack
10018 frame creation although it is part of the prologue. */
10020 else if (IS_NESTED (func_type
))
10022 /* The Static chain register is the same as the IP register
10023 used as a scratch register during stack frame creation.
10024 To get around this need to find somewhere to store IP
10025 whilst the frame is being created. We try the following
10028 1. The last argument register.
10029 2. A slot on the stack above the frame. (This only
10030 works if the function is not a varargs function).
10031 3. Register r3, after pushing the argument registers
10034 Note - we only need to tell the dwarf2 backend about the SP
10035 adjustment in the second variant; the static chain register
10036 doesn't need to be unwound, as it doesn't contain a value
10037 inherited from the caller. */
10039 if (regs_ever_live
[3] == 0)
10041 insn
= gen_rtx_REG (SImode
, 3);
10042 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10043 insn
= emit_insn (insn
);
10045 else if (args_to_push
== 0)
10048 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10049 insn
= gen_rtx_MEM (SImode
, insn
);
10050 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10051 insn
= emit_insn (insn
);
10055 /* Just tell the dwarf backend that we adjusted SP. */
10056 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10057 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10058 GEN_INT (-fp_offset
)));
10059 RTX_FRAME_RELATED_P (insn
) = 1;
10060 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10061 dwarf
, REG_NOTES (insn
));
10065 /* Store the args on the stack. */
10066 if (cfun
->machine
->uses_anonymous_args
)
10067 insn
= emit_multi_reg_push
10068 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10071 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10072 GEN_INT (- args_to_push
)));
10074 RTX_FRAME_RELATED_P (insn
) = 1;
10076 saved_pretend_args
= 1;
10077 fp_offset
= args_to_push
;
10080 /* Now reuse r3 to preserve IP. */
10081 insn
= gen_rtx_REG (SImode
, 3);
10082 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10083 (void) emit_insn (insn
);
10089 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10090 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10093 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10095 insn
= emit_insn (insn
);
10096 RTX_FRAME_RELATED_P (insn
) = 1;
10101 /* Push the argument registers, or reserve space for them. */
10102 if (cfun
->machine
->uses_anonymous_args
)
10103 insn
= emit_multi_reg_push
10104 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10107 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10108 GEN_INT (- args_to_push
)));
10109 RTX_FRAME_RELATED_P (insn
) = 1;
10112 /* If this is an interrupt service routine, and the link register
10113 is going to be pushed, and we are not creating a stack frame,
10114 (which would involve an extra push of IP and a pop in the epilogue)
10115 subtracting four from LR now will mean that the function return
10116 can be done with a single instruction. */
10117 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10118 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10119 && ! frame_pointer_needed
)
10120 emit_insn (gen_rtx_SET (SImode
,
10121 gen_rtx_REG (SImode
, LR_REGNUM
),
10122 gen_rtx_PLUS (SImode
,
10123 gen_rtx_REG (SImode
, LR_REGNUM
),
10126 if (live_regs_mask
)
10128 insn
= emit_multi_reg_push (live_regs_mask
);
10129 saved_regs
+= bit_count (live_regs_mask
) * 4;
10130 RTX_FRAME_RELATED_P (insn
) = 1;
10134 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10135 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10137 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10138 insn
= gen_rtx_MEM (V2SImode
, insn
);
10139 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10140 gen_rtx_REG (V2SImode
, reg
)));
10141 RTX_FRAME_RELATED_P (insn
) = 1;
10145 if (! IS_VOLATILE (func_type
))
10149 /* Save any floating point call-saved registers used by this
10151 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10153 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10154 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10156 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10157 insn
= gen_rtx_MEM (XFmode
, insn
);
10158 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10159 gen_rtx_REG (XFmode
, reg
)));
10160 RTX_FRAME_RELATED_P (insn
) = 1;
10166 start_reg
= LAST_FPA_REGNUM
;
10168 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10170 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10172 if (start_reg
- reg
== 3)
10174 insn
= emit_sfm (reg
, 4);
10175 RTX_FRAME_RELATED_P (insn
) = 1;
10177 start_reg
= reg
- 1;
10182 if (start_reg
!= reg
)
10184 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10185 RTX_FRAME_RELATED_P (insn
) = 1;
10186 saved_regs
+= (start_reg
- reg
) * 12;
10188 start_reg
= reg
- 1;
10192 if (start_reg
!= reg
)
10194 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10195 saved_regs
+= (start_reg
- reg
) * 12;
10196 RTX_FRAME_RELATED_P (insn
) = 1;
10199 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10201 start_reg
= FIRST_VFP_REGNUM
;
10203 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10205 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10206 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10208 if (start_reg
!= reg
)
10209 saved_regs
+= vfp_emit_fstmx (start_reg
,
10210 (reg
- start_reg
) / 2);
10211 start_reg
= reg
+ 2;
10214 if (start_reg
!= reg
)
10215 saved_regs
+= vfp_emit_fstmx (start_reg
,
10216 (reg
- start_reg
) / 2);
10220 if (frame_pointer_needed
)
10222 /* Create the new frame pointer. */
10223 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10224 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10225 RTX_FRAME_RELATED_P (insn
) = 1;
10227 if (IS_NESTED (func_type
))
10229 /* Recover the static chain register. */
10230 if (regs_ever_live
[3] == 0
10231 || saved_pretend_args
)
10232 insn
= gen_rtx_REG (SImode
, 3);
10233 else /* if (current_function_pretend_args_size == 0) */
10235 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10237 insn
= gen_rtx_MEM (SImode
, insn
);
10240 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10241 /* Add a USE to stop propagate_one_insn() from barfing. */
10242 emit_insn (gen_prologue_use (ip_rtx
));
10246 offsets
= arm_get_frame_offsets ();
10247 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10249 /* This add can produce multiple insns for a large constant, so we
10250 need to get tricky. */
10251 rtx last
= get_last_insn ();
10253 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10254 - offsets
->outgoing_args
);
10256 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10260 last
= last
? NEXT_INSN (last
) : get_insns ();
10261 RTX_FRAME_RELATED_P (last
) = 1;
10263 while (last
!= insn
);
10265 /* If the frame pointer is needed, emit a special barrier that
10266 will prevent the scheduler from moving stores to the frame
10267 before the stack adjustment. */
10268 if (frame_pointer_needed
)
10269 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10270 hard_frame_pointer_rtx
));
10275 arm_load_pic_register (INVALID_REGNUM
);
10277 /* If we are profiling, make sure no instructions are scheduled before
10278 the call to mcount. Similarly if the user has requested no
10279 scheduling in the prolog. */
10280 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10281 emit_insn (gen_blockage ());
10283 /* If the link register is being kept alive, with the return address in it,
10284 then make sure that it does not get reused by the ce2 pass. */
10285 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10287 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10288 cfun
->machine
->lr_save_eliminated
= 1;
10292 /* If CODE is 'd', then the X is a condition operand and the instruction
10293 should only be executed if the condition is true.
10294 if CODE is 'D', then the X is a condition operand and the instruction
10295 should only be executed if the condition is false: however, if the mode
10296 of the comparison is CCFPEmode, then always execute the instruction -- we
10297 do this because in these circumstances !GE does not necessarily imply LT;
10298 in these cases the instruction pattern will take care to make sure that
10299 an instruction containing %d will follow, thereby undoing the effects of
10300 doing this instruction unconditionally.
10301 If CODE is 'N' then X is a floating point operand that must be negated
10303 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10304 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10306 arm_print_operand (FILE *stream
, rtx x
, int code
)
10311 fputs (ASM_COMMENT_START
, stream
);
10315 fputs (user_label_prefix
, stream
);
10319 fputs (REGISTER_PREFIX
, stream
);
10323 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10327 output_operand_lossage ("predicated Thumb instruction");
10330 if (current_insn_predicate
!= NULL
)
10332 output_operand_lossage
10333 ("predicated instruction in conditional sequence");
10337 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10339 else if (current_insn_predicate
)
10341 enum arm_cond_code code
;
10345 output_operand_lossage ("predicated Thumb instruction");
10349 code
= get_arm_condition_code (current_insn_predicate
);
10350 fputs (arm_condition_codes
[code
], stream
);
10357 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10358 r
= REAL_VALUE_NEGATE (r
);
10359 fprintf (stream
, "%s", fp_const_from_val (&r
));
10364 if (GET_CODE (x
) == CONST_INT
)
10367 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10368 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10372 putc ('~', stream
);
10373 output_addr_const (stream
, x
);
10378 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10381 /* Truncate Cirrus shift counts. */
10383 if (GET_CODE (x
) == CONST_INT
)
10385 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10388 arm_print_operand (stream
, x
, 0);
10392 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10398 const char * shift
= shift_op (x
, &val
);
10402 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10404 arm_print_operand (stream
, XEXP (x
, 1), 0);
10406 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10411 /* An explanation of the 'Q', 'R' and 'H' register operands:
10413 In a pair of registers containing a DI or DF value the 'Q'
10414 operand returns the register number of the register containing
10415 the least significant part of the value. The 'R' operand returns
10416 the register number of the register containing the most
10417 significant part of the value.
10419 The 'H' operand returns the higher of the two register numbers.
10420 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10421 same as the 'Q' operand, since the most significant part of the
10422 value is held in the lower number register. The reverse is true
10423 on systems where WORDS_BIG_ENDIAN is false.
10425 The purpose of these operands is to distinguish between cases
10426 where the endian-ness of the values is important (for example
10427 when they are added together), and cases where the endian-ness
10428 is irrelevant, but the order of register operations is important.
10429 For example when loading a value from memory into a register
10430 pair, the endian-ness does not matter. Provided that the value
10431 from the lower memory address is put into the lower numbered
10432 register, and the value from the higher address is put into the
10433 higher numbered register, the load will work regardless of whether
10434 the value being loaded is big-wordian or little-wordian. The
10435 order of the two register loads can matter however, if the address
10436 of the memory location is actually held in one of the registers
10437 being overwritten by the load. */
10439 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10441 output_operand_lossage ("invalid operand for code '%c'", code
);
10445 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
10449 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10451 output_operand_lossage ("invalid operand for code '%c'", code
);
10455 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
10459 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10461 output_operand_lossage ("invalid operand for code '%c'", code
);
10465 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
10469 asm_fprintf (stream
, "%r",
10470 GET_CODE (XEXP (x
, 0)) == REG
10471 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
10475 asm_fprintf (stream
, "{%r-%r}",
10477 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
10481 /* CONST_TRUE_RTX means always -- that's the default. */
10482 if (x
== const_true_rtx
)
10485 if (!COMPARISON_P (x
))
10487 output_operand_lossage ("invalid operand for code '%c'", code
);
10491 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
10496 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
10497 want to do that. */
10498 if (x
== const_true_rtx
)
10500 output_operand_lossage ("instruction never exectued");
10503 if (!COMPARISON_P (x
))
10505 output_operand_lossage ("invalid operand for code '%c'", code
);
10509 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
10510 (get_arm_condition_code (x
))],
10514 /* Cirrus registers can be accessed in a variety of ways:
10515 single floating point (f)
10516 double floating point (d)
10518 64bit integer (dx). */
10519 case 'W': /* Cirrus register in F mode. */
10520 case 'X': /* Cirrus register in D mode. */
10521 case 'Y': /* Cirrus register in FX mode. */
10522 case 'Z': /* Cirrus register in DX mode. */
10523 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10526 fprintf (stream
, "mv%s%s",
10528 : code
== 'X' ? "d"
10529 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
10533 /* Print cirrus register in the mode specified by the register's mode. */
10536 int mode
= GET_MODE (x
);
10538 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10540 output_operand_lossage ("invalid operand for code '%c'", code
);
10544 fprintf (stream
, "mv%s%s",
10545 mode
== DFmode
? "d"
10546 : mode
== SImode
? "fx"
10547 : mode
== DImode
? "dx"
10548 : "f", reg_names
[REGNO (x
)] + 2);
10554 if (GET_CODE (x
) != REG
10555 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
10556 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
10557 /* Bad value for wCG register number. */
10559 output_operand_lossage ("invalid operand for code '%c'", code
);
10564 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
10567 /* Print an iWMMXt control register name. */
10569 if (GET_CODE (x
) != CONST_INT
10571 || INTVAL (x
) >= 16)
10572 /* Bad value for wC register number. */
10574 output_operand_lossage ("invalid operand for code '%c'", code
);
10580 static const char * wc_reg_names
[16] =
10582 "wCID", "wCon", "wCSSF", "wCASF",
10583 "wC4", "wC5", "wC6", "wC7",
10584 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10585 "wC12", "wC13", "wC14", "wC15"
10588 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
10592 /* Print a VFP double precision register name. */
10595 int mode
= GET_MODE (x
);
10598 if (mode
!= DImode
&& mode
!= DFmode
)
10600 output_operand_lossage ("invalid operand for code '%c'", code
);
10604 if (GET_CODE (x
) != REG
10605 || !IS_VFP_REGNUM (REGNO (x
)))
10607 output_operand_lossage ("invalid operand for code '%c'", code
);
10611 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
10614 output_operand_lossage ("invalid operand for code '%c'", code
);
10618 fprintf (stream
, "d%d", num
>> 1);
10625 output_operand_lossage ("missing operand");
10629 if (GET_CODE (x
) == REG
)
10630 asm_fprintf (stream
, "%r", REGNO (x
));
10631 else if (GET_CODE (x
) == MEM
)
10633 output_memory_reference_mode
= GET_MODE (x
);
10634 output_address (XEXP (x
, 0));
10636 else if (GET_CODE (x
) == CONST_DOUBLE
)
10637 fprintf (stream
, "#%s", fp_immediate_constant (x
));
10638 else if (GET_CODE (x
) == NEG
)
10639 abort (); /* This should never happen now. */
10642 fputc ('#', stream
);
10643 output_addr_const (stream
, x
);
10648 #ifndef AOF_ASSEMBLER
10649 /* Target hook for assembling integer objects. The ARM version needs to
10650 handle word-sized values specially. */
10652 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10654 if (size
== UNITS_PER_WORD
&& aligned_p
)
10656 fputs ("\t.word\t", asm_out_file
);
10657 output_addr_const (asm_out_file
, x
);
10659 /* Mark symbols as position independent. We only do this in the
10660 .text segment, not in the .data segment. */
10661 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
10662 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
10664 if (GET_CODE (x
) == SYMBOL_REF
10665 && (CONSTANT_POOL_ADDRESS_P (x
)
10666 || SYMBOL_REF_LOCAL_P (x
)))
10667 fputs ("(GOTOFF)", asm_out_file
);
10668 else if (GET_CODE (x
) == LABEL_REF
)
10669 fputs ("(GOTOFF)", asm_out_file
);
10671 fputs ("(GOT)", asm_out_file
);
10673 fputc ('\n', asm_out_file
);
10677 if (arm_vector_mode_supported_p (GET_MODE (x
)))
10681 if (GET_CODE (x
) != CONST_VECTOR
)
10684 units
= CONST_VECTOR_NUNITS (x
);
10686 switch (GET_MODE (x
))
10688 case V2SImode
: size
= 4; break;
10689 case V4HImode
: size
= 2; break;
10690 case V8QImode
: size
= 1; break;
10695 for (i
= 0; i
< units
; i
++)
10699 elt
= CONST_VECTOR_ELT (x
, i
);
10701 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
10707 return default_assemble_integer (x
, size
, aligned_p
);
10711 /* A finite state machine takes care of noticing whether or not instructions
10712 can be conditionally executed, and thus decrease execution time and code
10713 size by deleting branch instructions. The fsm is controlled by
10714 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10716 /* The state of the fsm controlling condition codes are:
10717 0: normal, do nothing special
10718 1: make ASM_OUTPUT_OPCODE not output this instruction
10719 2: make ASM_OUTPUT_OPCODE not output this instruction
10720 3: make instructions conditional
10721 4: make instructions conditional
10723 State transitions (state->state by whom under condition):
10724 0 -> 1 final_prescan_insn if the `target' is a label
10725 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10726 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10727 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10728 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10729 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10730 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10731 (the target insn is arm_target_insn).
10733 If the jump clobbers the conditions then we use states 2 and 4.
10735 A similar thing can be done with conditional return insns.
10737 XXX In case the `target' is an unconditional branch, this conditionalising
10738 of the instructions always reduces code size, but not always execution
10739 time. But then, I want to reduce the code size to somewhere near what
10740 /bin/cc produces. */
10742 /* Returns the index of the ARM condition code string in
10743 `arm_condition_codes'. COMPARISON should be an rtx like
10744 `(eq (...) (...))'. */
10745 static enum arm_cond_code
10746 get_arm_condition_code (rtx comparison
)
10748 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
10750 enum rtx_code comp_code
= GET_CODE (comparison
);
10752 if (GET_MODE_CLASS (mode
) != MODE_CC
)
10753 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
10754 XEXP (comparison
, 1));
10758 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
10759 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
10760 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
10761 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
10762 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
10763 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
10764 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
10765 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
10766 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
10767 case CC_DLTUmode
: code
= ARM_CC
;
10770 if (comp_code
!= EQ
&& comp_code
!= NE
)
10773 if (comp_code
== EQ
)
10774 return ARM_INVERSE_CONDITION_CODE (code
);
10780 case NE
: return ARM_NE
;
10781 case EQ
: return ARM_EQ
;
10782 case GE
: return ARM_PL
;
10783 case LT
: return ARM_MI
;
10790 case NE
: return ARM_NE
;
10791 case EQ
: return ARM_EQ
;
10798 case NE
: return ARM_MI
;
10799 case EQ
: return ARM_PL
;
10805 /* These encodings assume that AC=1 in the FPA system control
10806 byte. This allows us to handle all cases except UNEQ and
10810 case GE
: return ARM_GE
;
10811 case GT
: return ARM_GT
;
10812 case LE
: return ARM_LS
;
10813 case LT
: return ARM_MI
;
10814 case NE
: return ARM_NE
;
10815 case EQ
: return ARM_EQ
;
10816 case ORDERED
: return ARM_VC
;
10817 case UNORDERED
: return ARM_VS
;
10818 case UNLT
: return ARM_LT
;
10819 case UNLE
: return ARM_LE
;
10820 case UNGT
: return ARM_HI
;
10821 case UNGE
: return ARM_PL
;
10822 /* UNEQ and LTGT do not have a representation. */
10823 case UNEQ
: /* Fall through. */
10824 case LTGT
: /* Fall through. */
10831 case NE
: return ARM_NE
;
10832 case EQ
: return ARM_EQ
;
10833 case GE
: return ARM_LE
;
10834 case GT
: return ARM_LT
;
10835 case LE
: return ARM_GE
;
10836 case LT
: return ARM_GT
;
10837 case GEU
: return ARM_LS
;
10838 case GTU
: return ARM_CC
;
10839 case LEU
: return ARM_CS
;
10840 case LTU
: return ARM_HI
;
10847 case LTU
: return ARM_CS
;
10848 case GEU
: return ARM_CC
;
10855 case NE
: return ARM_NE
;
10856 case EQ
: return ARM_EQ
;
10857 case GE
: return ARM_GE
;
10858 case GT
: return ARM_GT
;
10859 case LE
: return ARM_LE
;
10860 case LT
: return ARM_LT
;
10861 case GEU
: return ARM_CS
;
10862 case GTU
: return ARM_HI
;
10863 case LEU
: return ARM_LS
;
10864 case LTU
: return ARM_CC
;
10875 arm_final_prescan_insn (rtx insn
)
10877 /* BODY will hold the body of INSN. */
10878 rtx body
= PATTERN (insn
);
10880 /* This will be 1 if trying to repeat the trick, and things need to be
10881 reversed if it appears to fail. */
10884 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10885 taken are clobbered, even if the rtl suggests otherwise. It also
10886 means that we have to grub around within the jump expression to find
10887 out what the conditions are when the jump isn't taken. */
10888 int jump_clobbers
= 0;
10890 /* If we start with a return insn, we only succeed if we find another one. */
10891 int seeking_return
= 0;
10893 /* START_INSN will hold the insn from where we start looking. This is the
10894 first insn after the following code_label if REVERSE is true. */
10895 rtx start_insn
= insn
;
10897 /* If in state 4, check if the target branch is reached, in order to
10898 change back to state 0. */
10899 if (arm_ccfsm_state
== 4)
10901 if (insn
== arm_target_insn
)
10903 arm_target_insn
= NULL
;
10904 arm_ccfsm_state
= 0;
10909 /* If in state 3, it is possible to repeat the trick, if this insn is an
10910 unconditional branch to a label, and immediately following this branch
10911 is the previous target label which is only used once, and the label this
10912 branch jumps to is not too far off. */
10913 if (arm_ccfsm_state
== 3)
10915 if (simplejump_p (insn
))
10917 start_insn
= next_nonnote_insn (start_insn
);
10918 if (GET_CODE (start_insn
) == BARRIER
)
10920 /* XXX Isn't this always a barrier? */
10921 start_insn
= next_nonnote_insn (start_insn
);
10923 if (GET_CODE (start_insn
) == CODE_LABEL
10924 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
10925 && LABEL_NUSES (start_insn
) == 1)
10930 else if (GET_CODE (body
) == RETURN
)
10932 start_insn
= next_nonnote_insn (start_insn
);
10933 if (GET_CODE (start_insn
) == BARRIER
)
10934 start_insn
= next_nonnote_insn (start_insn
);
10935 if (GET_CODE (start_insn
) == CODE_LABEL
10936 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
10937 && LABEL_NUSES (start_insn
) == 1)
10940 seeking_return
= 1;
10949 if (arm_ccfsm_state
!= 0 && !reverse
)
10951 if (GET_CODE (insn
) != JUMP_INSN
)
10954 /* This jump might be paralleled with a clobber of the condition codes
10955 the jump should always come first */
10956 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
10957 body
= XVECEXP (body
, 0, 0);
10960 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
10961 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
10964 int fail
= FALSE
, succeed
= FALSE
;
10965 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10966 int then_not_else
= TRUE
;
10967 rtx this_insn
= start_insn
, label
= 0;
10969 /* If the jump cannot be done with one instruction, we cannot
10970 conditionally execute the instruction in the inverse case. */
10971 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
10977 /* Register the insn jumped to. */
10980 if (!seeking_return
)
10981 label
= XEXP (SET_SRC (body
), 0);
10983 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
10984 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
10985 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
10987 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
10988 then_not_else
= FALSE
;
10990 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
10991 seeking_return
= 1;
10992 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
10994 seeking_return
= 1;
10995 then_not_else
= FALSE
;
11000 /* See how many insns this branch skips, and what kind of insns. If all
11001 insns are okay, and the label or unconditional branch to the same
11002 label is not too far away, succeed. */
11003 for (insns_skipped
= 0;
11004 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11008 this_insn
= next_nonnote_insn (this_insn
);
11012 switch (GET_CODE (this_insn
))
11015 /* Succeed if it is the target label, otherwise fail since
11016 control falls in from somewhere else. */
11017 if (this_insn
== label
)
11021 arm_ccfsm_state
= 2;
11022 this_insn
= next_nonnote_insn (this_insn
);
11025 arm_ccfsm_state
= 1;
11033 /* Succeed if the following insn is the target label.
11035 If return insns are used then the last insn in a function
11036 will be a barrier. */
11037 this_insn
= next_nonnote_insn (this_insn
);
11038 if (this_insn
&& this_insn
== label
)
11042 arm_ccfsm_state
= 2;
11043 this_insn
= next_nonnote_insn (this_insn
);
11046 arm_ccfsm_state
= 1;
11054 /* The AAPCS says that conditional calls should not be
11055 used since they make interworking inefficient (the
11056 linker can't transform BL<cond> into BLX). That's
11057 only a problem if the machine has BLX. */
11064 /* Succeed if the following insn is the target label, or
11065 if the following two insns are a barrier and the
11067 this_insn
= next_nonnote_insn (this_insn
);
11068 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11069 this_insn
= next_nonnote_insn (this_insn
);
11071 if (this_insn
&& this_insn
== label
11072 && insns_skipped
< max_insns_skipped
)
11076 arm_ccfsm_state
= 2;
11077 this_insn
= next_nonnote_insn (this_insn
);
11080 arm_ccfsm_state
= 1;
11088 /* If this is an unconditional branch to the same label, succeed.
11089 If it is to another label, do nothing. If it is conditional,
11091 /* XXX Probably, the tests for SET and the PC are
11094 scanbody
= PATTERN (this_insn
);
11095 if (GET_CODE (scanbody
) == SET
11096 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11098 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11099 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11101 arm_ccfsm_state
= 2;
11104 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11107 /* Fail if a conditional return is undesirable (e.g. on a
11108 StrongARM), but still allow this if optimizing for size. */
11109 else if (GET_CODE (scanbody
) == RETURN
11110 && !use_return_insn (TRUE
, NULL
)
11113 else if (GET_CODE (scanbody
) == RETURN
11116 arm_ccfsm_state
= 2;
11119 else if (GET_CODE (scanbody
) == PARALLEL
)
11121 switch (get_attr_conds (this_insn
))
11131 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11136 /* Instructions using or affecting the condition codes make it
11138 scanbody
= PATTERN (this_insn
);
11139 if (!(GET_CODE (scanbody
) == SET
11140 || GET_CODE (scanbody
) == PARALLEL
)
11141 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11144 /* A conditional cirrus instruction must be followed by
11145 a non Cirrus instruction. However, since we
11146 conditionalize instructions in this function and by
11147 the time we get here we can't add instructions
11148 (nops), because shorten_branches() has already been
11149 called, we will disable conditionalizing Cirrus
11150 instructions to be safe. */
11151 if (GET_CODE (scanbody
) != USE
11152 && GET_CODE (scanbody
) != CLOBBER
11153 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11163 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11164 arm_target_label
= CODE_LABEL_NUMBER (label
);
11165 else if (seeking_return
|| arm_ccfsm_state
== 2)
11167 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11169 this_insn
= next_nonnote_insn (this_insn
);
11170 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
11171 || GET_CODE (this_insn
) == CODE_LABEL
))
11176 /* Oh, dear! we ran off the end.. give up. */
11177 recog (PATTERN (insn
), insn
, NULL
);
11178 arm_ccfsm_state
= 0;
11179 arm_target_insn
= NULL
;
11182 arm_target_insn
= this_insn
;
11191 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11193 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11194 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11195 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11196 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11200 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11203 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11207 if (reverse
|| then_not_else
)
11208 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11211 /* Restore recog_data (getting the attributes of other insns can
11212 destroy this array, but final.c assumes that it remains intact
11213 across this call; since the insn has been recognized already we
11214 call recog direct). */
11215 recog (PATTERN (insn
), insn
, NULL
);
11219 /* Returns true if REGNO is a valid register
11220 for holding a quantity of type MODE. */
11222 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11224 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11225 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11228 /* For the Thumb we only allow values bigger than SImode in
11229 registers 0 - 6, so that there is always a second low
11230 register available to hold the upper part of the value.
11231 We probably we ought to ensure that the register is the
11232 start of an even numbered register pair. */
11233 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11235 if (IS_CIRRUS_REGNUM (regno
))
11236 /* We have outlawed SI values in Cirrus registers because they
11237 reside in the lower 32 bits, but SF values reside in the
11238 upper 32 bits. This causes gcc all sorts of grief. We can't
11239 even split the registers into pairs because Cirrus SI values
11240 get sign extended to 64bits-- aldyh. */
11241 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11243 if (IS_VFP_REGNUM (regno
))
11245 if (mode
== SFmode
|| mode
== SImode
)
11248 /* DFmode values are only valid in even register pairs. */
11249 if (mode
== DFmode
)
11250 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11254 if (IS_IWMMXT_GR_REGNUM (regno
))
11255 return mode
== SImode
;
11257 if (IS_IWMMXT_REGNUM (regno
))
11258 return VALID_IWMMXT_REG_MODE (mode
);
11260 /* We allow any value to be stored in the general registers.
11261 Restrict doubleword quantities to even register pairs so that we can
11263 if (regno
<= LAST_ARM_REGNUM
)
11264 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11266 if ( regno
== FRAME_POINTER_REGNUM
11267 || regno
== ARG_POINTER_REGNUM
)
11268 /* We only allow integers in the fake hard registers. */
11269 return GET_MODE_CLASS (mode
) == MODE_INT
;
11271 /* The only registers left are the FPA registers
11272 which we only allow to hold FP values. */
11273 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11274 && regno
>= FIRST_FPA_REGNUM
11275 && regno
<= LAST_FPA_REGNUM
;
11279 arm_regno_class (int regno
)
11283 if (regno
== STACK_POINTER_REGNUM
)
11285 if (regno
== CC_REGNUM
)
11292 if ( regno
<= LAST_ARM_REGNUM
11293 || regno
== FRAME_POINTER_REGNUM
11294 || regno
== ARG_POINTER_REGNUM
)
11295 return GENERAL_REGS
;
11297 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11300 if (IS_CIRRUS_REGNUM (regno
))
11301 return CIRRUS_REGS
;
11303 if (IS_VFP_REGNUM (regno
))
11306 if (IS_IWMMXT_REGNUM (regno
))
11307 return IWMMXT_REGS
;
11309 if (IS_IWMMXT_GR_REGNUM (regno
))
11310 return IWMMXT_GR_REGS
;
11315 /* Handle a special case when computing the offset
11316 of an argument from the frame pointer. */
11318 arm_debugger_arg_offset (int value
, rtx addr
)
11322 /* We are only interested if dbxout_parms() failed to compute the offset. */
11326 /* We can only cope with the case where the address is held in a register. */
11327 if (GET_CODE (addr
) != REG
)
11330 /* If we are using the frame pointer to point at the argument, then
11331 an offset of 0 is correct. */
11332 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11335 /* If we are using the stack pointer to point at the
11336 argument, then an offset of 0 is correct. */
11337 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11338 && REGNO (addr
) == SP_REGNUM
)
11341 /* Oh dear. The argument is pointed to by a register rather
11342 than being held in a register, or being stored at a known
11343 offset from the frame pointer. Since GDB only understands
11344 those two kinds of argument we must translate the address
11345 held in the register into an offset from the frame pointer.
11346 We do this by searching through the insns for the function
11347 looking to see where this register gets its value. If the
11348 register is initialized from the frame pointer plus an offset
11349 then we are in luck and we can continue, otherwise we give up.
11351 This code is exercised by producing debugging information
11352 for a function with arguments like this:
11354 double func (double a, double b, int c, double d) {return d;}
11356 Without this code the stab for parameter 'd' will be set to
11357 an offset of 0 from the frame pointer, rather than 8. */
11359 /* The if() statement says:
11361 If the insn is a normal instruction
11362 and if the insn is setting the value in a register
11363 and if the register being set is the register holding the address of the argument
11364 and if the address is computing by an addition
11365 that involves adding to a register
11366 which is the frame pointer
11371 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11373 if ( GET_CODE (insn
) == INSN
11374 && GET_CODE (PATTERN (insn
)) == SET
11375 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11376 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11377 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11378 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11379 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11382 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11391 warning ("unable to compute real location of stacked parameter");
11392 value
= 8; /* XXX magic hack */
11398 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11401 if ((MASK) & insn_flags) \
11402 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11403 BUILT_IN_MD, NULL, NULL_TREE); \
11407 struct builtin_description
11409 const unsigned int mask
;
11410 const enum insn_code icode
;
11411 const char * const name
;
11412 const enum arm_builtins code
;
11413 const enum rtx_code comparison
;
11414 const unsigned int flag
;
11417 static const struct builtin_description bdesc_2arg
[] =
11419 #define IWMMXT_BUILTIN(code, string, builtin) \
11420 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11421 ARM_BUILTIN_##builtin, 0, 0 },
11423 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
11424 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
11425 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
11426 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
11427 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
11428 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
11429 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
11430 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
11431 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
11432 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
11433 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
11434 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
11435 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
11436 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
11437 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
11438 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
11439 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
11440 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
11441 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
11442 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
11443 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
11444 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
11445 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
11446 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
11447 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
11448 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
11449 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
11450 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
11451 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
11452 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
11453 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
11454 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
11455 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
11456 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
11457 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
11458 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
11459 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
11460 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
11461 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
11462 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
11463 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
11464 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
11465 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
11466 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
11467 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
11468 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
11469 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
11470 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
11471 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
11472 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
11473 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
11474 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
11475 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
11476 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
11477 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
11478 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
11479 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
11480 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
11482 #define IWMMXT_BUILTIN2(code, builtin) \
11483 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11485 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
11486 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
11487 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
11488 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
11489 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
11490 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
11491 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
11492 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
11493 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
11494 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
11495 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
11496 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
11497 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
11498 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
11499 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
11500 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
11501 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
11502 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
11503 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
11504 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
11505 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
11506 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
11507 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
11508 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
11509 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
11510 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
11511 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
11512 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
11513 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
11514 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
11515 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
11516 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
11519 static const struct builtin_description bdesc_1arg
[] =
11521 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
11522 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
11523 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
11524 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
11525 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
11526 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
11527 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
11528 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
11529 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
11530 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
11531 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
11532 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
11533 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
11534 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
11535 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
11536 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
11537 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
11538 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
11541 /* Set up all the iWMMXt builtins. This is
11542 not called if TARGET_IWMMXT is zero. */
11545 arm_init_iwmmxt_builtins (void)
11547 const struct builtin_description
* d
;
11549 tree endlink
= void_list_node
;
11551 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
11552 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
11553 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
11556 = build_function_type (integer_type_node
,
11557 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
11558 tree v8qi_ftype_v8qi_v8qi_int
11559 = build_function_type (V8QI_type_node
,
11560 tree_cons (NULL_TREE
, V8QI_type_node
,
11561 tree_cons (NULL_TREE
, V8QI_type_node
,
11562 tree_cons (NULL_TREE
,
11565 tree v4hi_ftype_v4hi_int
11566 = build_function_type (V4HI_type_node
,
11567 tree_cons (NULL_TREE
, V4HI_type_node
,
11568 tree_cons (NULL_TREE
, integer_type_node
,
11570 tree v2si_ftype_v2si_int
11571 = build_function_type (V2SI_type_node
,
11572 tree_cons (NULL_TREE
, V2SI_type_node
,
11573 tree_cons (NULL_TREE
, integer_type_node
,
11575 tree v2si_ftype_di_di
11576 = build_function_type (V2SI_type_node
,
11577 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11578 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11580 tree di_ftype_di_int
11581 = build_function_type (long_long_integer_type_node
,
11582 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11583 tree_cons (NULL_TREE
, integer_type_node
,
11585 tree di_ftype_di_int_int
11586 = build_function_type (long_long_integer_type_node
,
11587 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11588 tree_cons (NULL_TREE
, integer_type_node
,
11589 tree_cons (NULL_TREE
,
11592 tree int_ftype_v8qi
11593 = build_function_type (integer_type_node
,
11594 tree_cons (NULL_TREE
, V8QI_type_node
,
11596 tree int_ftype_v4hi
11597 = build_function_type (integer_type_node
,
11598 tree_cons (NULL_TREE
, V4HI_type_node
,
11600 tree int_ftype_v2si
11601 = build_function_type (integer_type_node
,
11602 tree_cons (NULL_TREE
, V2SI_type_node
,
11604 tree int_ftype_v8qi_int
11605 = build_function_type (integer_type_node
,
11606 tree_cons (NULL_TREE
, V8QI_type_node
,
11607 tree_cons (NULL_TREE
, integer_type_node
,
11609 tree int_ftype_v4hi_int
11610 = build_function_type (integer_type_node
,
11611 tree_cons (NULL_TREE
, V4HI_type_node
,
11612 tree_cons (NULL_TREE
, integer_type_node
,
11614 tree int_ftype_v2si_int
11615 = build_function_type (integer_type_node
,
11616 tree_cons (NULL_TREE
, V2SI_type_node
,
11617 tree_cons (NULL_TREE
, integer_type_node
,
11619 tree v8qi_ftype_v8qi_int_int
11620 = build_function_type (V8QI_type_node
,
11621 tree_cons (NULL_TREE
, V8QI_type_node
,
11622 tree_cons (NULL_TREE
, integer_type_node
,
11623 tree_cons (NULL_TREE
,
11626 tree v4hi_ftype_v4hi_int_int
11627 = build_function_type (V4HI_type_node
,
11628 tree_cons (NULL_TREE
, V4HI_type_node
,
11629 tree_cons (NULL_TREE
, integer_type_node
,
11630 tree_cons (NULL_TREE
,
11633 tree v2si_ftype_v2si_int_int
11634 = build_function_type (V2SI_type_node
,
11635 tree_cons (NULL_TREE
, V2SI_type_node
,
11636 tree_cons (NULL_TREE
, integer_type_node
,
11637 tree_cons (NULL_TREE
,
11640 /* Miscellaneous. */
11641 tree v8qi_ftype_v4hi_v4hi
11642 = build_function_type (V8QI_type_node
,
11643 tree_cons (NULL_TREE
, V4HI_type_node
,
11644 tree_cons (NULL_TREE
, V4HI_type_node
,
11646 tree v4hi_ftype_v2si_v2si
11647 = build_function_type (V4HI_type_node
,
11648 tree_cons (NULL_TREE
, V2SI_type_node
,
11649 tree_cons (NULL_TREE
, V2SI_type_node
,
11651 tree v2si_ftype_v4hi_v4hi
11652 = build_function_type (V2SI_type_node
,
11653 tree_cons (NULL_TREE
, V4HI_type_node
,
11654 tree_cons (NULL_TREE
, V4HI_type_node
,
11656 tree v2si_ftype_v8qi_v8qi
11657 = build_function_type (V2SI_type_node
,
11658 tree_cons (NULL_TREE
, V8QI_type_node
,
11659 tree_cons (NULL_TREE
, V8QI_type_node
,
11661 tree v4hi_ftype_v4hi_di
11662 = build_function_type (V4HI_type_node
,
11663 tree_cons (NULL_TREE
, V4HI_type_node
,
11664 tree_cons (NULL_TREE
,
11665 long_long_integer_type_node
,
11667 tree v2si_ftype_v2si_di
11668 = build_function_type (V2SI_type_node
,
11669 tree_cons (NULL_TREE
, V2SI_type_node
,
11670 tree_cons (NULL_TREE
,
11671 long_long_integer_type_node
,
11673 tree void_ftype_int_int
11674 = build_function_type (void_type_node
,
11675 tree_cons (NULL_TREE
, integer_type_node
,
11676 tree_cons (NULL_TREE
, integer_type_node
,
11679 = build_function_type (long_long_unsigned_type_node
, endlink
);
11681 = build_function_type (long_long_integer_type_node
,
11682 tree_cons (NULL_TREE
, V8QI_type_node
,
11685 = build_function_type (long_long_integer_type_node
,
11686 tree_cons (NULL_TREE
, V4HI_type_node
,
11689 = build_function_type (long_long_integer_type_node
,
11690 tree_cons (NULL_TREE
, V2SI_type_node
,
11692 tree v2si_ftype_v4hi
11693 = build_function_type (V2SI_type_node
,
11694 tree_cons (NULL_TREE
, V4HI_type_node
,
11696 tree v4hi_ftype_v8qi
11697 = build_function_type (V4HI_type_node
,
11698 tree_cons (NULL_TREE
, V8QI_type_node
,
11701 tree di_ftype_di_v4hi_v4hi
11702 = build_function_type (long_long_unsigned_type_node
,
11703 tree_cons (NULL_TREE
,
11704 long_long_unsigned_type_node
,
11705 tree_cons (NULL_TREE
, V4HI_type_node
,
11706 tree_cons (NULL_TREE
,
11710 tree di_ftype_v4hi_v4hi
11711 = build_function_type (long_long_unsigned_type_node
,
11712 tree_cons (NULL_TREE
, V4HI_type_node
,
11713 tree_cons (NULL_TREE
, V4HI_type_node
,
11716 /* Normal vector binops. */
11717 tree v8qi_ftype_v8qi_v8qi
11718 = build_function_type (V8QI_type_node
,
11719 tree_cons (NULL_TREE
, V8QI_type_node
,
11720 tree_cons (NULL_TREE
, V8QI_type_node
,
11722 tree v4hi_ftype_v4hi_v4hi
11723 = build_function_type (V4HI_type_node
,
11724 tree_cons (NULL_TREE
, V4HI_type_node
,
11725 tree_cons (NULL_TREE
, V4HI_type_node
,
11727 tree v2si_ftype_v2si_v2si
11728 = build_function_type (V2SI_type_node
,
11729 tree_cons (NULL_TREE
, V2SI_type_node
,
11730 tree_cons (NULL_TREE
, V2SI_type_node
,
11732 tree di_ftype_di_di
11733 = build_function_type (long_long_unsigned_type_node
,
11734 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
11735 tree_cons (NULL_TREE
,
11736 long_long_unsigned_type_node
,
11739 /* Add all builtins that are more or less simple operations on two
11741 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11743 /* Use one of the operands; the target can have a different mode for
11744 mask-generating compares. */
11745 enum machine_mode mode
;
11751 mode
= insn_data
[d
->icode
].operand
[1].mode
;
11756 type
= v8qi_ftype_v8qi_v8qi
;
11759 type
= v4hi_ftype_v4hi_v4hi
;
11762 type
= v2si_ftype_v2si_v2si
;
11765 type
= di_ftype_di_di
;
11772 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
11775 /* Add the remaining MMX insns with somewhat more complicated types. */
11776 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
11777 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
11778 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
11780 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
11781 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
11782 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
11783 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
11784 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
11785 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
11787 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
11788 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
11789 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
11790 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
11791 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
11792 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
11794 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
11795 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
11796 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
11797 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
11798 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
11799 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
11801 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
11802 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
11803 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
11804 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
11805 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
11806 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
11808 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
11810 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
11811 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
11812 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
11813 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
11815 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
11816 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
11817 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
11818 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
11819 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
11820 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
11821 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
11822 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
11823 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
11825 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
11826 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
11827 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
11829 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
11830 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
11831 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
11833 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
11834 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
11835 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
11836 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
11837 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
11838 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
11840 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
11841 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
11842 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
11843 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
11844 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
11845 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
11846 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
11847 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
11848 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
11849 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
11850 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
11851 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
11853 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
11854 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
11855 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
11856 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
11858 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
11859 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
11860 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
11861 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
11862 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
11863 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
11864 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
11868 arm_init_builtins (void)
11870 if (TARGET_REALLY_IWMMXT
)
11871 arm_init_iwmmxt_builtins ();
11874 /* Errors in the source file can cause expand_expr to return const0_rtx
11875 where we expect a vector. To avoid crashing, use one of the vector
11876 clear instructions. */
11879 safe_vector_operand (rtx x
, enum machine_mode mode
)
11881 if (x
!= const0_rtx
)
11883 x
= gen_reg_rtx (mode
);
11885 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
11886 : gen_rtx_SUBREG (DImode
, x
, 0)));
11890 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11893 arm_expand_binop_builtin (enum insn_code icode
,
11894 tree arglist
, rtx target
)
11897 tree arg0
= TREE_VALUE (arglist
);
11898 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11899 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11900 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11901 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11902 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11903 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11905 if (VECTOR_MODE_P (mode0
))
11906 op0
= safe_vector_operand (op0
, mode0
);
11907 if (VECTOR_MODE_P (mode1
))
11908 op1
= safe_vector_operand (op1
, mode1
);
11911 || GET_MODE (target
) != tmode
11912 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11913 target
= gen_reg_rtx (tmode
);
11915 /* In case the insn wants input operands in modes different from
11916 the result, abort. */
11917 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
11920 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11921 op0
= copy_to_mode_reg (mode0
, op0
);
11922 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11923 op1
= copy_to_mode_reg (mode1
, op1
);
11925 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11932 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11935 arm_expand_unop_builtin (enum insn_code icode
,
11936 tree arglist
, rtx target
, int do_load
)
11939 tree arg0
= TREE_VALUE (arglist
);
11940 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11941 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11942 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11945 || GET_MODE (target
) != tmode
11946 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11947 target
= gen_reg_rtx (tmode
);
11949 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11952 if (VECTOR_MODE_P (mode0
))
11953 op0
= safe_vector_operand (op0
, mode0
);
11955 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11956 op0
= copy_to_mode_reg (mode0
, op0
);
11959 pat
= GEN_FCN (icode
) (target
, op0
);
11966 /* Expand an expression EXP that calls a built-in function,
11967 with result going to TARGET if that's convenient
11968 (and in mode MODE if that's convenient).
11969 SUBTARGET may be used as the target for computing one of EXP's operands.
11970 IGNORE is nonzero if the value is to be ignored. */
11973 arm_expand_builtin (tree exp
,
11975 rtx subtarget ATTRIBUTE_UNUSED
,
11976 enum machine_mode mode ATTRIBUTE_UNUSED
,
11977 int ignore ATTRIBUTE_UNUSED
)
11979 const struct builtin_description
* d
;
11980 enum insn_code icode
;
11981 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
11982 tree arglist
= TREE_OPERAND (exp
, 1);
11990 int fcode
= DECL_FUNCTION_CODE (fndecl
);
11992 enum machine_mode tmode
;
11993 enum machine_mode mode0
;
11994 enum machine_mode mode1
;
11995 enum machine_mode mode2
;
11999 case ARM_BUILTIN_TEXTRMSB
:
12000 case ARM_BUILTIN_TEXTRMUB
:
12001 case ARM_BUILTIN_TEXTRMSH
:
12002 case ARM_BUILTIN_TEXTRMUH
:
12003 case ARM_BUILTIN_TEXTRMSW
:
12004 case ARM_BUILTIN_TEXTRMUW
:
12005 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12006 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12007 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12008 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12009 : CODE_FOR_iwmmxt_textrmw
);
12011 arg0
= TREE_VALUE (arglist
);
12012 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12013 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12014 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12015 tmode
= insn_data
[icode
].operand
[0].mode
;
12016 mode0
= insn_data
[icode
].operand
[1].mode
;
12017 mode1
= insn_data
[icode
].operand
[2].mode
;
12019 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12020 op0
= copy_to_mode_reg (mode0
, op0
);
12021 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12023 /* @@@ better error message */
12024 error ("selector must be an immediate");
12025 return gen_reg_rtx (tmode
);
12028 || GET_MODE (target
) != tmode
12029 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12030 target
= gen_reg_rtx (tmode
);
12031 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12037 case ARM_BUILTIN_TINSRB
:
12038 case ARM_BUILTIN_TINSRH
:
12039 case ARM_BUILTIN_TINSRW
:
12040 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12041 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12042 : CODE_FOR_iwmmxt_tinsrw
);
12043 arg0
= TREE_VALUE (arglist
);
12044 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12045 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12046 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12047 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12048 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12049 tmode
= insn_data
[icode
].operand
[0].mode
;
12050 mode0
= insn_data
[icode
].operand
[1].mode
;
12051 mode1
= insn_data
[icode
].operand
[2].mode
;
12052 mode2
= insn_data
[icode
].operand
[3].mode
;
12054 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12055 op0
= copy_to_mode_reg (mode0
, op0
);
12056 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12057 op1
= copy_to_mode_reg (mode1
, op1
);
12058 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12060 /* @@@ better error message */
12061 error ("selector must be an immediate");
12065 || GET_MODE (target
) != tmode
12066 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12067 target
= gen_reg_rtx (tmode
);
12068 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12074 case ARM_BUILTIN_SETWCX
:
12075 arg0
= TREE_VALUE (arglist
);
12076 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12077 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12078 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12079 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12082 case ARM_BUILTIN_GETWCX
:
12083 arg0
= TREE_VALUE (arglist
);
12084 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12085 target
= gen_reg_rtx (SImode
);
12086 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12089 case ARM_BUILTIN_WSHUFH
:
12090 icode
= CODE_FOR_iwmmxt_wshufh
;
12091 arg0
= TREE_VALUE (arglist
);
12092 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12093 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12094 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12095 tmode
= insn_data
[icode
].operand
[0].mode
;
12096 mode1
= insn_data
[icode
].operand
[1].mode
;
12097 mode2
= insn_data
[icode
].operand
[2].mode
;
12099 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12100 op0
= copy_to_mode_reg (mode1
, op0
);
12101 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12103 /* @@@ better error message */
12104 error ("mask must be an immediate");
12108 || GET_MODE (target
) != tmode
12109 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12110 target
= gen_reg_rtx (tmode
);
12111 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12117 case ARM_BUILTIN_WSADB
:
12118 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12119 case ARM_BUILTIN_WSADH
:
12120 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12121 case ARM_BUILTIN_WSADBZ
:
12122 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12123 case ARM_BUILTIN_WSADHZ
:
12124 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12126 /* Several three-argument builtins. */
12127 case ARM_BUILTIN_WMACS
:
12128 case ARM_BUILTIN_WMACU
:
12129 case ARM_BUILTIN_WALIGN
:
12130 case ARM_BUILTIN_TMIA
:
12131 case ARM_BUILTIN_TMIAPH
:
12132 case ARM_BUILTIN_TMIATT
:
12133 case ARM_BUILTIN_TMIATB
:
12134 case ARM_BUILTIN_TMIABT
:
12135 case ARM_BUILTIN_TMIABB
:
12136 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12137 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12138 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12139 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12140 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12141 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12142 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12143 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12144 : CODE_FOR_iwmmxt_walign
);
12145 arg0
= TREE_VALUE (arglist
);
12146 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12147 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12148 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12149 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12150 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12151 tmode
= insn_data
[icode
].operand
[0].mode
;
12152 mode0
= insn_data
[icode
].operand
[1].mode
;
12153 mode1
= insn_data
[icode
].operand
[2].mode
;
12154 mode2
= insn_data
[icode
].operand
[3].mode
;
12156 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12157 op0
= copy_to_mode_reg (mode0
, op0
);
12158 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12159 op1
= copy_to_mode_reg (mode1
, op1
);
12160 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12161 op2
= copy_to_mode_reg (mode2
, op2
);
12163 || GET_MODE (target
) != tmode
12164 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12165 target
= gen_reg_rtx (tmode
);
12166 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12172 case ARM_BUILTIN_WZERO
:
12173 target
= gen_reg_rtx (DImode
);
12174 emit_insn (gen_iwmmxt_clrdi (target
));
12181 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12182 if (d
->code
== (const enum arm_builtins
) fcode
)
12183 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12185 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12186 if (d
->code
== (const enum arm_builtins
) fcode
)
12187 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12189 /* @@@ Should really do something sensible here. */
12193 /* Return the number (counting from 0) of
12194 the least significant set bit in MASK. */
12197 number_of_first_bit_set (unsigned mask
)
12202 (mask
& (1 << bit
)) == 0;
12209 /* Emit code to push or pop registers to or from the stack. F is the
12210 assembly file. MASK is the registers to push or pop. PUSH is
12211 nonzero if we should push, and zero if we should pop. For debugging
12212 output, if pushing, adjust CFA_OFFSET by the amount of space added
12213 to the stack. REAL_REGS should have the same number of bits set as
12214 MASK, and will be used instead (in the same order) to describe which
12215 registers were saved - this is used to mark the save slots when we
12216 push high registers after moving them to low registers. */
12218 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12219 unsigned long real_regs
)
12222 int lo_mask
= mask
& 0xFF;
12223 int pushed_words
= 0;
12228 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12230 /* Special case. Do not generate a POP PC statement here, do it in
12232 thumb_exit (f
, -1);
12236 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12238 /* Look at the low registers first. */
12239 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12243 asm_fprintf (f
, "%r", regno
);
12245 if ((lo_mask
& ~1) != 0)
12252 if (push
&& (mask
& (1 << LR_REGNUM
)))
12254 /* Catch pushing the LR. */
12258 asm_fprintf (f
, "%r", LR_REGNUM
);
12262 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12264 /* Catch popping the PC. */
12265 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12266 || current_function_calls_eh_return
)
12268 /* The PC is never poped directly, instead
12269 it is popped into r3 and then BX is used. */
12270 fprintf (f
, "}\n");
12272 thumb_exit (f
, -1);
12281 asm_fprintf (f
, "%r", PC_REGNUM
);
12285 fprintf (f
, "}\n");
12287 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12289 char *l
= dwarf2out_cfi_label ();
12290 int pushed_mask
= real_regs
;
12292 *cfa_offset
+= pushed_words
* 4;
12293 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12296 pushed_mask
= real_regs
;
12297 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12299 if (pushed_mask
& 1)
12300 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12305 /* Generate code to return from a thumb function.
12306 If 'reg_containing_return_addr' is -1, then the return address is
12307 actually on the stack, at the stack pointer. */
12309 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12311 unsigned regs_available_for_popping
;
12312 unsigned regs_to_pop
;
12314 unsigned available
;
12318 int restore_a4
= FALSE
;
12320 /* Compute the registers we need to pop. */
12324 if (reg_containing_return_addr
== -1)
12326 regs_to_pop
|= 1 << LR_REGNUM
;
12330 if (TARGET_BACKTRACE
)
12332 /* Restore the (ARM) frame pointer and stack pointer. */
12333 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12337 /* If there is nothing to pop then just emit the BX instruction and
12339 if (pops_needed
== 0)
12341 if (current_function_calls_eh_return
)
12342 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12344 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12347 /* Otherwise if we are not supporting interworking and we have not created
12348 a backtrace structure and the function was not entered in ARM mode then
12349 just pop the return address straight into the PC. */
12350 else if (!TARGET_INTERWORK
12351 && !TARGET_BACKTRACE
12352 && !is_called_in_ARM_mode (current_function_decl
)
12353 && !current_function_calls_eh_return
)
12355 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12359 /* Find out how many of the (return) argument registers we can corrupt. */
12360 regs_available_for_popping
= 0;
12362 /* If returning via __builtin_eh_return, the bottom three registers
12363 all contain information needed for the return. */
12364 if (current_function_calls_eh_return
)
12368 /* If we can deduce the registers used from the function's
12369 return value. This is more reliable that examining
12370 regs_ever_live[] because that will be set if the register is
12371 ever used in the function, not just if the register is used
12372 to hold a return value. */
12374 if (current_function_return_rtx
!= 0)
12375 mode
= GET_MODE (current_function_return_rtx
);
12377 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12379 size
= GET_MODE_SIZE (mode
);
12383 /* In a void function we can use any argument register.
12384 In a function that returns a structure on the stack
12385 we can use the second and third argument registers. */
12386 if (mode
== VOIDmode
)
12387 regs_available_for_popping
=
12388 (1 << ARG_REGISTER (1))
12389 | (1 << ARG_REGISTER (2))
12390 | (1 << ARG_REGISTER (3));
12392 regs_available_for_popping
=
12393 (1 << ARG_REGISTER (2))
12394 | (1 << ARG_REGISTER (3));
12396 else if (size
<= 4)
12397 regs_available_for_popping
=
12398 (1 << ARG_REGISTER (2))
12399 | (1 << ARG_REGISTER (3));
12400 else if (size
<= 8)
12401 regs_available_for_popping
=
12402 (1 << ARG_REGISTER (3));
12405 /* Match registers to be popped with registers into which we pop them. */
12406 for (available
= regs_available_for_popping
,
12407 required
= regs_to_pop
;
12408 required
!= 0 && available
!= 0;
12409 available
&= ~(available
& - available
),
12410 required
&= ~(required
& - required
))
12413 /* If we have any popping registers left over, remove them. */
12415 regs_available_for_popping
&= ~available
;
12417 /* Otherwise if we need another popping register we can use
12418 the fourth argument register. */
12419 else if (pops_needed
)
12421 /* If we have not found any free argument registers and
12422 reg a4 contains the return address, we must move it. */
12423 if (regs_available_for_popping
== 0
12424 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
12426 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12427 reg_containing_return_addr
= LR_REGNUM
;
12429 else if (size
> 12)
12431 /* Register a4 is being used to hold part of the return value,
12432 but we have dire need of a free, low register. */
12435 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
12438 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
12440 /* The fourth argument register is available. */
12441 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
12447 /* Pop as many registers as we can. */
12448 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12449 regs_available_for_popping
);
12451 /* Process the registers we popped. */
12452 if (reg_containing_return_addr
== -1)
12454 /* The return address was popped into the lowest numbered register. */
12455 regs_to_pop
&= ~(1 << LR_REGNUM
);
12457 reg_containing_return_addr
=
12458 number_of_first_bit_set (regs_available_for_popping
);
12460 /* Remove this register for the mask of available registers, so that
12461 the return address will not be corrupted by further pops. */
12462 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
12465 /* If we popped other registers then handle them here. */
12466 if (regs_available_for_popping
)
12470 /* Work out which register currently contains the frame pointer. */
12471 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12473 /* Move it into the correct place. */
12474 asm_fprintf (f
, "\tmov\t%r, %r\n",
12475 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
12477 /* (Temporarily) remove it from the mask of popped registers. */
12478 regs_available_for_popping
&= ~(1 << frame_pointer
);
12479 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
12481 if (regs_available_for_popping
)
12485 /* We popped the stack pointer as well,
12486 find the register that contains it. */
12487 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12489 /* Move it into the stack register. */
12490 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
12492 /* At this point we have popped all necessary registers, so
12493 do not worry about restoring regs_available_for_popping
12494 to its correct value:
12496 assert (pops_needed == 0)
12497 assert (regs_available_for_popping == (1 << frame_pointer))
12498 assert (regs_to_pop == (1 << STACK_POINTER)) */
12502 /* Since we have just move the popped value into the frame
12503 pointer, the popping register is available for reuse, and
12504 we know that we still have the stack pointer left to pop. */
12505 regs_available_for_popping
|= (1 << frame_pointer
);
12509 /* If we still have registers left on the stack, but we no longer have
12510 any registers into which we can pop them, then we must move the return
12511 address into the link register and make available the register that
12513 if (regs_available_for_popping
== 0 && pops_needed
> 0)
12515 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
12517 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
12518 reg_containing_return_addr
);
12520 reg_containing_return_addr
= LR_REGNUM
;
12523 /* If we have registers left on the stack then pop some more.
12524 We know that at most we will want to pop FP and SP. */
12525 if (pops_needed
> 0)
12530 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12531 regs_available_for_popping
);
12533 /* We have popped either FP or SP.
12534 Move whichever one it is into the correct register. */
12535 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12536 move_to
= number_of_first_bit_set (regs_to_pop
);
12538 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
12540 regs_to_pop
&= ~(1 << move_to
);
12545 /* If we still have not popped everything then we must have only
12546 had one register available to us and we are now popping the SP. */
12547 if (pops_needed
> 0)
12551 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12552 regs_available_for_popping
);
12554 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12556 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
12558 assert (regs_to_pop == (1 << STACK_POINTER))
12559 assert (pops_needed == 1)
12563 /* If necessary restore the a4 register. */
12566 if (reg_containing_return_addr
!= LR_REGNUM
)
12568 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12569 reg_containing_return_addr
= LR_REGNUM
;
12572 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12575 if (current_function_calls_eh_return
)
12576 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12578 /* Return to caller. */
12579 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12584 thumb_final_prescan_insn (rtx insn
)
12586 if (flag_print_asm_name
)
12587 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
12588 INSN_ADDRESSES (INSN_UID (insn
)));
12592 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
12594 unsigned HOST_WIDE_INT mask
= 0xff;
12597 if (val
== 0) /* XXX */
12600 for (i
= 0; i
< 25; i
++)
12601 if ((val
& (mask
<< i
)) == val
)
12607 /* Returns nonzero if the current function contains,
12608 or might contain a far jump. */
12610 thumb_far_jump_used_p (void)
12614 /* This test is only important for leaf functions. */
12615 /* assert (!leaf_function_p ()); */
12617 /* If we have already decided that far jumps may be used,
12618 do not bother checking again, and always return true even if
12619 it turns out that they are not being used. Once we have made
12620 the decision that far jumps are present (and that hence the link
12621 register will be pushed onto the stack) we cannot go back on it. */
12622 if (cfun
->machine
->far_jump_used
)
12625 /* If this function is not being called from the prologue/epilogue
12626 generation code then it must be being called from the
12627 INITIAL_ELIMINATION_OFFSET macro. */
12628 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
12630 /* In this case we know that we are being asked about the elimination
12631 of the arg pointer register. If that register is not being used,
12632 then there are no arguments on the stack, and we do not have to
12633 worry that a far jump might force the prologue to push the link
12634 register, changing the stack offsets. In this case we can just
12635 return false, since the presence of far jumps in the function will
12636 not affect stack offsets.
12638 If the arg pointer is live (or if it was live, but has now been
12639 eliminated and so set to dead) then we do have to test to see if
12640 the function might contain a far jump. This test can lead to some
12641 false negatives, since before reload is completed, then length of
12642 branch instructions is not known, so gcc defaults to returning their
12643 longest length, which in turn sets the far jump attribute to true.
12645 A false negative will not result in bad code being generated, but it
12646 will result in a needless push and pop of the link register. We
12647 hope that this does not occur too often.
12649 If we need doubleword stack alignment this could affect the other
12650 elimination offsets so we can't risk getting it wrong. */
12651 if (regs_ever_live
[ARG_POINTER_REGNUM
])
12652 cfun
->machine
->arg_pointer_live
= 1;
12653 else if (!cfun
->machine
->arg_pointer_live
)
12657 /* Check to see if the function contains a branch
12658 insn with the far jump attribute set. */
12659 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12661 if (GET_CODE (insn
) == JUMP_INSN
12662 /* Ignore tablejump patterns. */
12663 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
12664 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
12665 && get_attr_far_jump (insn
) == FAR_JUMP_YES
12668 /* Record the fact that we have decided that
12669 the function does use far jumps. */
12670 cfun
->machine
->far_jump_used
= 1;
12678 /* Return nonzero if FUNC must be entered in ARM mode. */
12680 is_called_in_ARM_mode (tree func
)
12682 if (TREE_CODE (func
) != FUNCTION_DECL
)
12685 /* Ignore the problem about functions whoes address is taken. */
12686 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
12690 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
12696 /* The bits which aren't usefully expanded as rtl. */
12698 thumb_unexpanded_epilogue (void)
12701 unsigned long live_regs_mask
= 0;
12702 int high_regs_pushed
= 0;
12703 int had_to_push_lr
;
12707 if (return_used_this_function
)
12710 if (IS_NAKED (arm_current_func_type ()))
12713 live_regs_mask
= thumb_compute_save_reg_mask ();
12714 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
12716 /* If we can deduce the registers used from the function's return value.
12717 This is more reliable that examining regs_ever_live[] because that
12718 will be set if the register is ever used in the function, not just if
12719 the register is used to hold a return value. */
12721 if (current_function_return_rtx
!= 0)
12722 mode
= GET_MODE (current_function_return_rtx
);
12724 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12726 size
= GET_MODE_SIZE (mode
);
12728 /* The prolog may have pushed some high registers to use as
12729 work registers. e.g. the testsuite file:
12730 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12731 compiles to produce:
12732 push {r4, r5, r6, r7, lr}
12736 as part of the prolog. We have to undo that pushing here. */
12738 if (high_regs_pushed
)
12740 unsigned long mask
= live_regs_mask
& 0xff;
12743 /* The available low registers depend on the size of the value we are
12751 /* Oh dear! We have no low registers into which we can pop
12754 ("no low registers available for popping high registers");
12756 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
12757 if (live_regs_mask
& (1 << next_hi_reg
))
12760 while (high_regs_pushed
)
12762 /* Find lo register(s) into which the high register(s) can
12764 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12766 if (mask
& (1 << regno
))
12767 high_regs_pushed
--;
12768 if (high_regs_pushed
== 0)
12772 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
12774 /* Pop the values into the low register(s). */
12775 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
12777 /* Move the value(s) into the high registers. */
12778 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12780 if (mask
& (1 << regno
))
12782 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
12785 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
12786 if (live_regs_mask
& (1 << next_hi_reg
))
12791 live_regs_mask
&= ~0x0f00;
12794 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
12795 live_regs_mask
&= 0xff;
12797 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
12799 /* Pop the return address into the PC. */
12800 if (had_to_push_lr
)
12801 live_regs_mask
|= 1 << PC_REGNUM
;
12803 /* Either no argument registers were pushed or a backtrace
12804 structure was created which includes an adjusted stack
12805 pointer, so just pop everything. */
12806 if (live_regs_mask
)
12807 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
12810 /* We have either just popped the return address into the
12811 PC or it is was kept in LR for the entire function. */
12812 if (!had_to_push_lr
)
12813 thumb_exit (asm_out_file
, LR_REGNUM
);
12817 /* Pop everything but the return address. */
12818 if (live_regs_mask
)
12819 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
12822 if (had_to_push_lr
)
12826 /* We have no free low regs, so save one. */
12827 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
12831 /* Get the return address into a temporary register. */
12832 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
12833 1 << LAST_ARG_REGNUM
);
12837 /* Move the return address to lr. */
12838 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
12840 /* Restore the low register. */
12841 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
12846 regno
= LAST_ARG_REGNUM
;
12851 /* Remove the argument registers that were pushed onto the stack. */
12852 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
12853 SP_REGNUM
, SP_REGNUM
,
12854 current_function_pretend_args_size
);
12856 thumb_exit (asm_out_file
, regno
);
12862 /* Functions to save and restore machine-specific function data. */
12863 static struct machine_function
*
12864 arm_init_machine_status (void)
12866 struct machine_function
*machine
;
12867 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
12869 #if ARM_FT_UNKNOWN != 0
12870 machine
->func_type
= ARM_FT_UNKNOWN
;
12875 /* Return an RTX indicating where the return address to the
12876 calling function can be found. */
12878 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
12883 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
12886 /* Do anything needed before RTL is emitted for each function. */
12888 arm_init_expanders (void)
12890 /* Arrange to initialize and mark the machine per-function status. */
12891 init_machine_status
= arm_init_machine_status
;
12893 /* This is to stop the combine pass optimizing away the alignment
12894 adjustment of va_arg. */
12895 /* ??? It is claimed that this should not be necessary. */
12897 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
12901 /* Like arm_compute_initial_elimination offset. Simpler because
12902 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
12905 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
12907 arm_stack_offsets
*offsets
;
12909 offsets
= arm_get_frame_offsets ();
12913 case ARG_POINTER_REGNUM
:
12916 case STACK_POINTER_REGNUM
:
12917 return offsets
->outgoing_args
- offsets
->saved_args
;
12919 case FRAME_POINTER_REGNUM
:
12920 return offsets
->soft_frame
- offsets
->saved_args
;
12922 case THUMB_HARD_FRAME_POINTER_REGNUM
:
12923 case ARM_HARD_FRAME_POINTER_REGNUM
:
12924 return offsets
->saved_regs
- offsets
->saved_args
;
12931 case FRAME_POINTER_REGNUM
:
12934 case STACK_POINTER_REGNUM
:
12935 return offsets
->outgoing_args
- offsets
->soft_frame
;
12937 case THUMB_HARD_FRAME_POINTER_REGNUM
:
12938 case ARM_HARD_FRAME_POINTER_REGNUM
:
12939 return offsets
->saved_regs
- offsets
->soft_frame
;
12952 /* Generate the rest of a function's prologue. */
12954 thumb_expand_prologue (void)
12958 HOST_WIDE_INT amount
;
12959 arm_stack_offsets
*offsets
;
12960 unsigned long func_type
;
12962 unsigned long live_regs_mask
;
12964 func_type
= arm_current_func_type ();
12966 /* Naked functions don't have prologues. */
12967 if (IS_NAKED (func_type
))
12970 if (IS_INTERRUPT (func_type
))
12972 error ("interrupt Service Routines cannot be coded in Thumb mode");
12976 live_regs_mask
= thumb_compute_save_reg_mask ();
12977 /* Load the pic register before setting the frame pointer,
12978 so we can use r7 as a temporary work register. */
12980 arm_load_pic_register (thumb_find_work_register (live_regs_mask
));
12982 offsets
= arm_get_frame_offsets ();
12984 if (frame_pointer_needed
)
12986 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
12987 stack_pointer_rtx
));
12988 RTX_FRAME_RELATED_P (insn
) = 1;
12990 else if (CALLER_INTERWORKING_SLOT_SIZE
> 0)
12991 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
12992 stack_pointer_rtx
);
12994 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
12999 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13000 GEN_INT (- amount
)));
13001 RTX_FRAME_RELATED_P (insn
) = 1;
13007 /* The stack decrement is too big for an immediate value in a single
13008 insn. In theory we could issue multiple subtracts, but after
13009 three of them it becomes more space efficient to place the full
13010 value in the constant pool and load into a register. (Also the
13011 ARM debugger really likes to see only one stack decrement per
13012 function). So instead we look for a scratch register into which
13013 we can load the decrement, and then we subtract this from the
13014 stack pointer. Unfortunately on the thumb the only available
13015 scratch registers are the argument registers, and we cannot use
13016 these as they may hold arguments to the function. Instead we
13017 attempt to locate a call preserved register which is used by this
13018 function. If we can find one, then we know that it will have
13019 been pushed at the start of the prologue and so we can corrupt
13021 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13022 if (live_regs_mask
& (1 << regno
)
13023 && !(frame_pointer_needed
13024 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13027 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13029 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13031 /* Choose an arbitrary, non-argument low register. */
13032 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13034 /* Save it by copying it into a high, scratch register. */
13035 emit_insn (gen_movsi (spare
, reg
));
13036 /* Add a USE to stop propagate_one_insn() from barfing. */
13037 emit_insn (gen_prologue_use (spare
));
13039 /* Decrement the stack. */
13040 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13041 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13042 stack_pointer_rtx
, reg
));
13043 RTX_FRAME_RELATED_P (insn
) = 1;
13044 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13045 plus_constant (stack_pointer_rtx
,
13047 RTX_FRAME_RELATED_P (dwarf
) = 1;
13049 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13052 /* Restore the low register's original value. */
13053 emit_insn (gen_movsi (reg
, spare
));
13055 /* Emit a USE of the restored scratch register, so that flow
13056 analysis will not consider the restore redundant. The
13057 register won't be used again in this function and isn't
13058 restored by the epilogue. */
13059 emit_insn (gen_prologue_use (reg
));
13063 reg
= gen_rtx_REG (SImode
, regno
);
13065 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13067 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13068 stack_pointer_rtx
, reg
));
13069 RTX_FRAME_RELATED_P (insn
) = 1;
13070 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13071 plus_constant (stack_pointer_rtx
,
13073 RTX_FRAME_RELATED_P (dwarf
) = 1;
13075 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13079 /* If the frame pointer is needed, emit a special barrier that
13080 will prevent the scheduler from moving stores to the frame
13081 before the stack adjustment. */
13082 if (frame_pointer_needed
)
13083 emit_insn (gen_stack_tie (stack_pointer_rtx
,
13084 hard_frame_pointer_rtx
));
13087 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13088 emit_insn (gen_blockage ());
13090 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13091 if (live_regs_mask
& 0xff)
13092 cfun
->machine
->lr_save_eliminated
= 0;
13094 /* If the link register is being kept alive, with the return address in it,
13095 then make sure that it does not get reused by the ce2 pass. */
13096 if (cfun
->machine
->lr_save_eliminated
)
13097 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13102 thumb_expand_epilogue (void)
13104 HOST_WIDE_INT amount
;
13105 arm_stack_offsets
*offsets
;
13108 /* Naked functions don't have prologues. */
13109 if (IS_NAKED (arm_current_func_type ()))
13112 offsets
= arm_get_frame_offsets ();
13113 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13115 if (frame_pointer_needed
)
13116 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13120 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13121 GEN_INT (amount
)));
13124 /* r3 is always free in the epilogue. */
13125 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13127 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13128 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13132 /* Emit a USE (stack_pointer_rtx), so that
13133 the stack adjustment will not be deleted. */
13134 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13136 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13137 emit_insn (gen_blockage ());
13139 /* Emit a clobber for each insn that will be restored in the epilogue,
13140 so that flow2 will get register lifetimes correct. */
13141 for (regno
= 0; regno
< 13; regno
++)
13142 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13143 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13145 if (! regs_ever_live
[LR_REGNUM
])
13146 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13150 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13152 unsigned long live_regs_mask
= 0;
13153 unsigned long l_mask
;
13154 unsigned high_regs_pushed
= 0;
13155 int cfa_offset
= 0;
13158 if (IS_NAKED (arm_current_func_type ()))
13161 if (is_called_in_ARM_mode (current_function_decl
))
13165 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
13167 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
13169 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13171 /* Generate code sequence to switch us into Thumb mode. */
13172 /* The .code 32 directive has already been emitted by
13173 ASM_DECLARE_FUNCTION_NAME. */
13174 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13175 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13177 /* Generate a label, so that the debugger will notice the
13178 change in instruction sets. This label is also used by
13179 the assembler to bypass the ARM code when this function
13180 is called from a Thumb encoded function elsewhere in the
13181 same file. Hence the definition of STUB_NAME here must
13182 agree with the definition in gas/config/tc-arm.c. */
13184 #define STUB_NAME ".real_start_of"
13186 fprintf (f
, "\t.code\t16\n");
13188 if (arm_dllexport_name_p (name
))
13189 name
= arm_strip_name_encoding (name
);
13191 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13192 fprintf (f
, "\t.thumb_func\n");
13193 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13196 if (current_function_pretend_args_size
)
13198 if (cfun
->machine
->uses_anonymous_args
)
13202 fprintf (f
, "\tpush\t{");
13204 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13206 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13207 regno
<= LAST_ARG_REGNUM
;
13209 asm_fprintf (f
, "%r%s", regno
,
13210 regno
== LAST_ARG_REGNUM
? "" : ", ");
13212 fprintf (f
, "}\n");
13215 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13216 SP_REGNUM
, SP_REGNUM
,
13217 current_function_pretend_args_size
);
13219 /* We don't need to record the stores for unwinding (would it
13220 help the debugger any if we did?), but record the change in
13221 the stack pointer. */
13222 if (dwarf2out_do_frame ())
13224 char *l
= dwarf2out_cfi_label ();
13226 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13227 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13231 /* Get the registers we are going to push. */
13232 live_regs_mask
= thumb_compute_save_reg_mask ();
13233 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13234 l_mask
= live_regs_mask
& 0x40ff;
13235 /* Then count how many other high registers will need to be pushed. */
13236 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13238 if (TARGET_BACKTRACE
)
13241 unsigned work_register
;
13243 /* We have been asked to create a stack backtrace structure.
13244 The code looks like this:
13248 0 sub SP, #16 Reserve space for 4 registers.
13249 2 push {R7} Push low registers.
13250 4 add R7, SP, #20 Get the stack pointer before the push.
13251 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13252 8 mov R7, PC Get hold of the start of this code plus 12.
13253 10 str R7, [SP, #16] Store it.
13254 12 mov R7, FP Get hold of the current frame pointer.
13255 14 str R7, [SP, #4] Store it.
13256 16 mov R7, LR Get hold of the current return address.
13257 18 str R7, [SP, #12] Store it.
13258 20 add R7, SP, #16 Point at the start of the backtrace structure.
13259 22 mov FP, R7 Put this value into the frame pointer. */
13261 work_register
= thumb_find_work_register (live_regs_mask
);
13264 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13265 SP_REGNUM
, SP_REGNUM
);
13267 if (dwarf2out_do_frame ())
13269 char *l
= dwarf2out_cfi_label ();
13271 cfa_offset
= cfa_offset
+ 16;
13272 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13277 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13278 offset
= bit_count (l_mask
);
13283 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13284 offset
+ 16 + current_function_pretend_args_size
);
13286 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13289 /* Make sure that the instruction fetching the PC is in the right place
13290 to calculate "start of backtrace creation code + 12". */
13293 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13294 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13296 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13297 ARM_HARD_FRAME_POINTER_REGNUM
);
13298 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13303 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13304 ARM_HARD_FRAME_POINTER_REGNUM
);
13305 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13307 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13308 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13312 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13313 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13315 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13317 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13318 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13320 /* Optimisation: If we are not pushing any low registers but we are going
13321 to push some high registers then delay our first push. This will just
13322 be a push of LR and we can combine it with the push of the first high
13324 else if ((l_mask
& 0xff) != 0
13325 || (high_regs_pushed
== 0 && l_mask
))
13326 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13328 if (high_regs_pushed
)
13330 unsigned pushable_regs
;
13331 unsigned next_hi_reg
;
13333 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13334 if (live_regs_mask
& (1 << next_hi_reg
))
13337 pushable_regs
= l_mask
& 0xff;
13339 if (pushable_regs
== 0)
13340 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13342 while (high_regs_pushed
> 0)
13344 unsigned long real_regs_mask
= 0;
13346 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13348 if (pushable_regs
& (1 << regno
))
13350 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13352 high_regs_pushed
--;
13353 real_regs_mask
|= (1 << next_hi_reg
);
13355 if (high_regs_pushed
)
13357 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13359 if (live_regs_mask
& (1 << next_hi_reg
))
13364 pushable_regs
&= ~((1 << regno
) - 1);
13370 /* If we had to find a work register and we have not yet
13371 saved the LR then add it to the list of regs to push. */
13372 if (l_mask
== (1 << LR_REGNUM
))
13374 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
13376 real_regs_mask
| (1 << LR_REGNUM
));
13380 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
13385 /* Handle the case of a double word load into a low register from
13386 a computed memory address. The computed address may involve a
13387 register which is overwritten by the load. */
13389 thumb_load_double_from_address (rtx
*operands
)
13397 if (GET_CODE (operands
[0]) != REG
)
13400 if (GET_CODE (operands
[1]) != MEM
)
13403 /* Get the memory address. */
13404 addr
= XEXP (operands
[1], 0);
13406 /* Work out how the memory address is computed. */
13407 switch (GET_CODE (addr
))
13410 operands
[2] = gen_rtx_MEM (SImode
,
13411 plus_constant (XEXP (operands
[1], 0), 4));
13413 if (REGNO (operands
[0]) == REGNO (addr
))
13415 output_asm_insn ("ldr\t%H0, %2", operands
);
13416 output_asm_insn ("ldr\t%0, %1", operands
);
13420 output_asm_insn ("ldr\t%0, %1", operands
);
13421 output_asm_insn ("ldr\t%H0, %2", operands
);
13426 /* Compute <address> + 4 for the high order load. */
13427 operands
[2] = gen_rtx_MEM (SImode
,
13428 plus_constant (XEXP (operands
[1], 0), 4));
13430 output_asm_insn ("ldr\t%0, %1", operands
);
13431 output_asm_insn ("ldr\t%H0, %2", operands
);
13435 arg1
= XEXP (addr
, 0);
13436 arg2
= XEXP (addr
, 1);
13438 if (CONSTANT_P (arg1
))
13439 base
= arg2
, offset
= arg1
;
13441 base
= arg1
, offset
= arg2
;
13443 if (GET_CODE (base
) != REG
)
13446 /* Catch the case of <address> = <reg> + <reg> */
13447 if (GET_CODE (offset
) == REG
)
13449 int reg_offset
= REGNO (offset
);
13450 int reg_base
= REGNO (base
);
13451 int reg_dest
= REGNO (operands
[0]);
13453 /* Add the base and offset registers together into the
13454 higher destination register. */
13455 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
13456 reg_dest
+ 1, reg_base
, reg_offset
);
13458 /* Load the lower destination register from the address in
13459 the higher destination register. */
13460 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
13461 reg_dest
, reg_dest
+ 1);
13463 /* Load the higher destination register from its own address
13465 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
13466 reg_dest
+ 1, reg_dest
+ 1);
13470 /* Compute <address> + 4 for the high order load. */
13471 operands
[2] = gen_rtx_MEM (SImode
,
13472 plus_constant (XEXP (operands
[1], 0), 4));
13474 /* If the computed address is held in the low order register
13475 then load the high order register first, otherwise always
13476 load the low order register first. */
13477 if (REGNO (operands
[0]) == REGNO (base
))
13479 output_asm_insn ("ldr\t%H0, %2", operands
);
13480 output_asm_insn ("ldr\t%0, %1", operands
);
13484 output_asm_insn ("ldr\t%0, %1", operands
);
13485 output_asm_insn ("ldr\t%H0, %2", operands
);
13491 /* With no registers to worry about we can just load the value
13493 operands
[2] = gen_rtx_MEM (SImode
,
13494 plus_constant (XEXP (operands
[1], 0), 4));
13496 output_asm_insn ("ldr\t%H0, %2", operands
);
13497 output_asm_insn ("ldr\t%0, %1", operands
);
13509 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
13516 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13519 operands
[4] = operands
[5];
13522 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
13523 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
13527 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13530 operands
[4] = operands
[5];
13533 if (REGNO (operands
[5]) > REGNO (operands
[6]))
13536 operands
[5] = operands
[6];
13539 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13542 operands
[4] = operands
[5];
13546 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
13547 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
13557 /* Output a call-via instruction for thumb state. */
13559 thumb_call_via_reg (rtx reg
)
13561 int regno
= REGNO (reg
);
13564 gcc_assert (regno
< LR_REGNUM
);
13566 /* If we are in the normal text section we can use a single instance
13567 per compilation unit. If we are doing function sections, then we need
13568 an entry per section, since we can't rely on reachability. */
13569 if (in_text_section ())
13571 thumb_call_reg_needed
= 1;
13573 if (thumb_call_via_label
[regno
] == NULL
)
13574 thumb_call_via_label
[regno
] = gen_label_rtx ();
13575 labelp
= thumb_call_via_label
+ regno
;
13579 if (cfun
->machine
->call_via
[regno
] == NULL
)
13580 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
13581 labelp
= cfun
->machine
->call_via
+ regno
;
13584 output_asm_insn ("bl\t%a0", labelp
);
13588 /* Routines for generating rtl. */
13590 thumb_expand_movmemqi (rtx
*operands
)
13592 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
13593 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
13594 HOST_WIDE_INT len
= INTVAL (operands
[2]);
13595 HOST_WIDE_INT offset
= 0;
13599 emit_insn (gen_movmem12b (out
, in
, out
, in
));
13605 emit_insn (gen_movmem8b (out
, in
, out
, in
));
13611 rtx reg
= gen_reg_rtx (SImode
);
13612 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
13613 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
13620 rtx reg
= gen_reg_rtx (HImode
);
13621 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
13622 plus_constant (in
, offset
))));
13623 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
13631 rtx reg
= gen_reg_rtx (QImode
);
13632 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
13633 plus_constant (in
, offset
))));
13634 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
13640 thumb_reload_out_hi (rtx
*operands
)
13642 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
13645 /* Handle reading a half-word from memory during reload. */
13647 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
13652 /* Return the length of a function name prefix
13653 that starts with the character 'c'. */
13655 arm_get_strip_length (int c
)
13659 ARM_NAME_ENCODING_LENGTHS
13664 /* Return a pointer to a function's name with any
13665 and all prefix encodings stripped from it. */
13667 arm_strip_name_encoding (const char *name
)
13671 while ((skip
= arm_get_strip_length (* name
)))
13677 /* If there is a '*' anywhere in the name's prefix, then
13678 emit the stripped name verbatim, otherwise prepend an
13679 underscore if leading underscores are being used. */
13681 arm_asm_output_labelref (FILE *stream
, const char *name
)
13686 while ((skip
= arm_get_strip_length (* name
)))
13688 verbatim
|= (*name
== '*');
13693 fputs (name
, stream
);
13695 asm_fprintf (stream
, "%U%s", name
);
13699 arm_file_end (void)
13703 if (! thumb_call_reg_needed
)
13707 asm_fprintf (asm_out_file
, "\t.code 16\n");
13708 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
13710 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
13712 rtx label
= thumb_call_via_label
[regno
];
13716 targetm
.asm_out
.internal_label (asm_out_file
, "L",
13717 CODE_LABEL_NUMBER (label
));
13718 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
13725 #ifdef AOF_ASSEMBLER
13726 /* Special functions only needed when producing AOF syntax assembler. */
13730 struct pic_chain
* next
;
13731 const char * symname
;
13734 static struct pic_chain
* aof_pic_chain
= NULL
;
13737 aof_pic_entry (rtx x
)
13739 struct pic_chain
** chainp
;
13742 if (aof_pic_label
== NULL_RTX
)
13744 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
13747 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
13748 offset
+= 4, chainp
= &(*chainp
)->next
)
13749 if ((*chainp
)->symname
== XSTR (x
, 0))
13750 return plus_constant (aof_pic_label
, offset
);
13752 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
13753 (*chainp
)->next
= NULL
;
13754 (*chainp
)->symname
= XSTR (x
, 0);
13755 return plus_constant (aof_pic_label
, offset
);
13759 aof_dump_pic_table (FILE *f
)
13761 struct pic_chain
* chain
;
13763 if (aof_pic_chain
== NULL
)
13766 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
13767 PIC_OFFSET_TABLE_REGNUM
,
13768 PIC_OFFSET_TABLE_REGNUM
);
13769 fputs ("|x$adcons|\n", f
);
13771 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
13773 fputs ("\tDCD\t", f
);
13774 assemble_name (f
, chain
->symname
);
13779 int arm_text_section_count
= 1;
13782 aof_text_section (void )
13784 static char buf
[100];
13785 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
13786 arm_text_section_count
++);
13788 strcat (buf
, ", PIC, REENTRANT");
13792 static int arm_data_section_count
= 1;
13795 aof_data_section (void)
13797 static char buf
[100];
13798 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
13802 /* The AOF assembler is religiously strict about declarations of
13803 imported and exported symbols, so that it is impossible to declare
13804 a function as imported near the beginning of the file, and then to
13805 export it later on. It is, however, possible to delay the decision
13806 until all the functions in the file have been compiled. To get
13807 around this, we maintain a list of the imports and exports, and
13808 delete from it any that are subsequently defined. At the end of
13809 compilation we spit the remainder of the list out before the END
13814 struct import
* next
;
13818 static struct import
* imports_list
= NULL
;
13821 aof_add_import (const char *name
)
13823 struct import
* new;
13825 for (new = imports_list
; new; new = new->next
)
13826 if (new->name
== name
)
13829 new = (struct import
*) xmalloc (sizeof (struct import
));
13830 new->next
= imports_list
;
13831 imports_list
= new;
13836 aof_delete_import (const char *name
)
13838 struct import
** old
;
13840 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
13842 if ((*old
)->name
== name
)
13844 *old
= (*old
)->next
;
13850 int arm_main_function
= 0;
13853 aof_dump_imports (FILE *f
)
13855 /* The AOF assembler needs this to cause the startup code to be extracted
13856 from the library. Brining in __main causes the whole thing to work
13858 if (arm_main_function
)
13861 fputs ("\tIMPORT __main\n", f
);
13862 fputs ("\tDCD __main\n", f
);
13865 /* Now dump the remaining imports. */
13866 while (imports_list
)
13868 fprintf (f
, "\tIMPORT\t");
13869 assemble_name (f
, imports_list
->name
);
13871 imports_list
= imports_list
->next
;
13876 aof_globalize_label (FILE *stream
, const char *name
)
13878 default_globalize_label (stream
, name
);
13879 if (! strcmp (name
, "main"))
13880 arm_main_function
= 1;
13884 aof_file_start (void)
13886 fputs ("__r0\tRN\t0\n", asm_out_file
);
13887 fputs ("__a1\tRN\t0\n", asm_out_file
);
13888 fputs ("__a2\tRN\t1\n", asm_out_file
);
13889 fputs ("__a3\tRN\t2\n", asm_out_file
);
13890 fputs ("__a4\tRN\t3\n", asm_out_file
);
13891 fputs ("__v1\tRN\t4\n", asm_out_file
);
13892 fputs ("__v2\tRN\t5\n", asm_out_file
);
13893 fputs ("__v3\tRN\t6\n", asm_out_file
);
13894 fputs ("__v4\tRN\t7\n", asm_out_file
);
13895 fputs ("__v5\tRN\t8\n", asm_out_file
);
13896 fputs ("__v6\tRN\t9\n", asm_out_file
);
13897 fputs ("__sl\tRN\t10\n", asm_out_file
);
13898 fputs ("__fp\tRN\t11\n", asm_out_file
);
13899 fputs ("__ip\tRN\t12\n", asm_out_file
);
13900 fputs ("__sp\tRN\t13\n", asm_out_file
);
13901 fputs ("__lr\tRN\t14\n", asm_out_file
);
13902 fputs ("__pc\tRN\t15\n", asm_out_file
);
13903 fputs ("__f0\tFN\t0\n", asm_out_file
);
13904 fputs ("__f1\tFN\t1\n", asm_out_file
);
13905 fputs ("__f2\tFN\t2\n", asm_out_file
);
13906 fputs ("__f3\tFN\t3\n", asm_out_file
);
13907 fputs ("__f4\tFN\t4\n", asm_out_file
);
13908 fputs ("__f5\tFN\t5\n", asm_out_file
);
13909 fputs ("__f6\tFN\t6\n", asm_out_file
);
13910 fputs ("__f7\tFN\t7\n", asm_out_file
);
13915 aof_file_end (void)
13918 aof_dump_pic_table (asm_out_file
);
13920 aof_dump_imports (asm_out_file
);
13921 fputs ("\tEND\n", asm_out_file
);
13923 #endif /* AOF_ASSEMBLER */
13926 /* Symbols in the text segment can be accessed without indirecting via the
13927 constant pool; it may take an extra binary operation, but this is still
13928 faster than indirecting via memory. Don't do this when not optimizing,
13929 since we won't be calculating al of the offsets necessary to do this
13933 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
13935 /* This doesn't work with AOF syntax, since the string table may be in
13936 a different AREA. */
13937 #ifndef AOF_ASSEMBLER
13938 if (optimize
> 0 && TREE_CONSTANT (decl
))
13939 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
13942 /* If we are referencing a function that is weak then encode a long call
13943 flag in the function name, otherwise if the function is static or
13944 or known to be defined in this file then encode a short call flag. */
13945 if (first
&& DECL_P (decl
))
13947 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
13948 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
13949 else if (! TREE_PUBLIC (decl
))
13950 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
13953 #endif /* !ARM_PE */
13956 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
13958 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
13959 && !strcmp (prefix
, "L"))
13961 arm_ccfsm_state
= 0;
13962 arm_target_insn
= NULL
;
13964 default_internal_label (stream
, prefix
, labelno
);
13967 /* Output code to add DELTA to the first argument, and then jump
13968 to FUNCTION. Used for C++ multiple inheritance. */
13970 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
13971 HOST_WIDE_INT delta
,
13972 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
13975 static int thunk_label
= 0;
13977 int mi_delta
= delta
;
13978 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
13980 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
13983 mi_delta
= - mi_delta
;
13986 int labelno
= thunk_label
++;
13987 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
13988 fputs ("\tldr\tr12, ", file
);
13989 assemble_name (file
, label
);
13990 fputc ('\n', file
);
13992 while (mi_delta
!= 0)
13994 if ((mi_delta
& (3 << shift
)) == 0)
13998 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
13999 mi_op
, this_regno
, this_regno
,
14000 mi_delta
& (0xff << shift
));
14001 mi_delta
&= ~(0xff << shift
);
14007 fprintf (file
, "\tbx\tr12\n");
14008 ASM_OUTPUT_ALIGN (file
, 2);
14009 assemble_name (file
, label
);
14010 fputs (":\n", file
);
14011 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14015 fputs ("\tb\t", file
);
14016 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14017 if (NEED_PLT_RELOC
)
14018 fputs ("(PLT)", file
);
14019 fputc ('\n', file
);
14024 arm_emit_vector_const (FILE *file
, rtx x
)
14027 const char * pattern
;
14029 if (GET_CODE (x
) != CONST_VECTOR
)
14032 switch (GET_MODE (x
))
14034 case V2SImode
: pattern
= "%08x"; break;
14035 case V4HImode
: pattern
= "%04x"; break;
14036 case V8QImode
: pattern
= "%02x"; break;
14040 fprintf (file
, "0x");
14041 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14045 element
= CONST_VECTOR_ELT (x
, i
);
14046 fprintf (file
, pattern
, INTVAL (element
));
14053 arm_output_load_gr (rtx
*operands
)
14060 if (GET_CODE (operands
[1]) != MEM
14061 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14062 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14063 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14064 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14065 return "wldrw%?\t%0, %1";
14067 /* Fix up an out-of-range load of a GR register. */
14068 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14069 wcgr
= operands
[0];
14071 output_asm_insn ("ldr%?\t%0, %1", operands
);
14073 operands
[0] = wcgr
;
14075 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14076 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14082 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14083 int incoming ATTRIBUTE_UNUSED
)
14086 /* FIXME: The ARM backend has special code to handle structure
14087 returns, and will reserve its own hidden first argument. So
14088 if this macro is enabled a *second* hidden argument will be
14089 reserved, which will break binary compatibility with old
14090 toolchains and also thunk handling. One day this should be
14094 /* Register in which address to store a structure value
14095 is passed to a function. */
14096 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14100 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14102 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14103 named arg and all anonymous args onto the stack.
14104 XXX I know the prologue shouldn't be pushing registers, but it is faster
14108 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14109 enum machine_mode mode ATTRIBUTE_UNUSED
,
14110 tree type ATTRIBUTE_UNUSED
,
14112 int second_time ATTRIBUTE_UNUSED
)
14114 cfun
->machine
->uses_anonymous_args
= 1;
14115 if (cum
->nregs
< NUM_ARG_REGS
)
14116 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14119 /* Return nonzero if the CONSUMER instruction (a store) does not need
14120 PRODUCER's value to calculate the address. */
14123 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14125 rtx value
= PATTERN (producer
);
14126 rtx addr
= PATTERN (consumer
);
14128 if (GET_CODE (value
) == COND_EXEC
)
14129 value
= COND_EXEC_CODE (value
);
14130 if (GET_CODE (value
) == PARALLEL
)
14131 value
= XVECEXP (value
, 0, 0);
14132 value
= XEXP (value
, 0);
14133 if (GET_CODE (addr
) == COND_EXEC
)
14134 addr
= COND_EXEC_CODE (addr
);
14135 if (GET_CODE (addr
) == PARALLEL
)
14136 addr
= XVECEXP (addr
, 0, 0);
14137 addr
= XEXP (addr
, 0);
14139 return !reg_overlap_mentioned_p (value
, addr
);
14142 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14143 have an early register shift value or amount dependency on the
14144 result of PRODUCER. */
14147 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14149 rtx value
= PATTERN (producer
);
14150 rtx op
= PATTERN (consumer
);
14153 if (GET_CODE (value
) == COND_EXEC
)
14154 value
= COND_EXEC_CODE (value
);
14155 if (GET_CODE (value
) == PARALLEL
)
14156 value
= XVECEXP (value
, 0, 0);
14157 value
= XEXP (value
, 0);
14158 if (GET_CODE (op
) == COND_EXEC
)
14159 op
= COND_EXEC_CODE (op
);
14160 if (GET_CODE (op
) == PARALLEL
)
14161 op
= XVECEXP (op
, 0, 0);
14164 early_op
= XEXP (op
, 0);
14165 /* This is either an actual independent shift, or a shift applied to
14166 the first operand of another operation. We want the whole shift
14168 if (GET_CODE (early_op
) == REG
)
14171 return !reg_overlap_mentioned_p (value
, early_op
);
14174 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14175 have an early register shift value dependency on the result of
14179 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14181 rtx value
= PATTERN (producer
);
14182 rtx op
= PATTERN (consumer
);
14185 if (GET_CODE (value
) == COND_EXEC
)
14186 value
= COND_EXEC_CODE (value
);
14187 if (GET_CODE (value
) == PARALLEL
)
14188 value
= XVECEXP (value
, 0, 0);
14189 value
= XEXP (value
, 0);
14190 if (GET_CODE (op
) == COND_EXEC
)
14191 op
= COND_EXEC_CODE (op
);
14192 if (GET_CODE (op
) == PARALLEL
)
14193 op
= XVECEXP (op
, 0, 0);
14196 early_op
= XEXP (op
, 0);
14198 /* This is either an actual independent shift, or a shift applied to
14199 the first operand of another operation. We want the value being
14200 shifted, in either case. */
14201 if (GET_CODE (early_op
) != REG
)
14202 early_op
= XEXP (early_op
, 0);
14204 return !reg_overlap_mentioned_p (value
, early_op
);
14207 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14208 have an early register mult dependency on the result of
14212 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14214 rtx value
= PATTERN (producer
);
14215 rtx op
= PATTERN (consumer
);
14217 if (GET_CODE (value
) == COND_EXEC
)
14218 value
= COND_EXEC_CODE (value
);
14219 if (GET_CODE (value
) == PARALLEL
)
14220 value
= XVECEXP (value
, 0, 0);
14221 value
= XEXP (value
, 0);
14222 if (GET_CODE (op
) == COND_EXEC
)
14223 op
= COND_EXEC_CODE (op
);
14224 if (GET_CODE (op
) == PARALLEL
)
14225 op
= XVECEXP (op
, 0, 0);
14228 return (GET_CODE (op
) == PLUS
14229 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14233 /* We can't rely on the caller doing the proper promotion when
14234 using APCS or ATPCS. */
14237 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14239 return !TARGET_AAPCS_BASED
;
14243 /* AAPCS based ABIs use short enums by default. */
14246 arm_default_short_enums (void)
14248 return TARGET_AAPCS_BASED
;
14252 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14255 arm_align_anon_bitfield (void)
14257 return TARGET_AAPCS_BASED
;
14261 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14264 arm_cxx_guard_type (void)
14266 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14270 /* The EABI says test the least significan bit of a guard variable. */
14273 arm_cxx_guard_mask_bit (void)
14275 return TARGET_AAPCS_BASED
;
14279 /* The EABI specifies that all array cookies are 8 bytes long. */
14282 arm_get_cookie_size (tree type
)
14286 if (!TARGET_AAPCS_BASED
)
14287 return default_cxx_get_cookie_size (type
);
14289 size
= build_int_cst (sizetype
, 8);
14294 /* The EABI says that array cookies should also contain the element size. */
14297 arm_cookie_has_size (void)
14299 return TARGET_AAPCS_BASED
;
14303 /* The EABI says constructors and destructors should return a pointer to
14304 the object constructed/destroyed. */
14307 arm_cxx_cdtor_returns_this (void)
14309 return TARGET_AAPCS_BASED
;
14312 /* The EABI says that an inline function may never be the key
14316 arm_cxx_key_method_may_be_inline (void)
14318 return !TARGET_AAPCS_BASED
;
14321 /* The EABI says that the virtual table, etc., for a class must be
14322 exported if it has a key method. The EABI does not specific the
14323 behavior if there is no key method, but there is no harm in
14324 exporting the class data in that case too. */
14327 arm_cxx_export_class_data (void)
14329 return TARGET_AAPCS_BASED
;
14333 arm_set_return_address (rtx source
, rtx scratch
)
14335 arm_stack_offsets
*offsets
;
14336 HOST_WIDE_INT delta
;
14338 unsigned long saved_regs
;
14340 saved_regs
= arm_compute_save_reg_mask ();
14342 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14343 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14346 if (frame_pointer_needed
)
14347 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
14350 /* LR will be the first saved register. */
14351 offsets
= arm_get_frame_offsets ();
14352 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
14357 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
14358 GEN_INT (delta
& ~4095)));
14363 addr
= stack_pointer_rtx
;
14365 addr
= plus_constant (addr
, delta
);
14367 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14373 thumb_set_return_address (rtx source
, rtx scratch
)
14375 arm_stack_offsets
*offsets
;
14376 HOST_WIDE_INT delta
;
14379 unsigned long mask
;
14381 emit_insn (gen_rtx_USE (VOIDmode
, source
));
14383 mask
= thumb_compute_save_reg_mask ();
14384 if (mask
& (1 << LR_REGNUM
))
14386 offsets
= arm_get_frame_offsets ();
14388 /* Find the saved regs. */
14389 if (frame_pointer_needed
)
14391 delta
= offsets
->soft_frame
- offsets
->saved_args
;
14392 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
14396 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
14399 /* Allow for the stack frame. */
14400 if (TARGET_BACKTRACE
)
14402 /* The link register is always the first saved register. */
14405 /* Construct the address. */
14406 addr
= gen_rtx_REG (SImode
, reg
);
14407 if ((reg
!= SP_REGNUM
&& delta
>= 128)
14410 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
14411 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
14415 addr
= plus_constant (addr
, delta
);
14417 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14420 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14423 /* Implements target hook vector_mode_supported_p. */
14425 arm_vector_mode_supported_p (enum machine_mode mode
)
14427 if ((mode
== V2SImode
)
14428 || (mode
== V4HImode
)
14429 || (mode
== V8QImode
))
14435 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
14436 ARM insns and therefore guarantee that the shift count is modulo 256.
14437 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
14438 guarantee no particular behavior for out-of-range counts. */
14440 static unsigned HOST_WIDE_INT
14441 arm_shift_truncation_mask (enum machine_mode mode
)
14443 return mode
== SImode
? 255 : 0;
14447 /* Map internal gcc register numbers to DWARF2 register numbers. */
14450 arm_dbx_register_number (unsigned int regno
)
14455 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
14456 compatibility. The EABI defines them as registers 96-103. */
14457 if (IS_FPA_REGNUM (regno
))
14458 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
14460 if (IS_VFP_REGNUM (regno
))
14461 return 64 + regno
- FIRST_VFP_REGNUM
;
14463 if (IS_IWMMXT_GR_REGNUM (regno
))
14464 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
14466 if (IS_IWMMXT_REGNUM (regno
))
14467 return 112 + regno
- FIRST_IWMMXT_REGNUM
;