1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx
, int);
152 static void arm_encode_section_info (tree
, rtx
, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx
arm_struct_value_rtx (tree
, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
168 enum machine_mode
, tree
, bool);
169 static bool arm_promote_prototypes (tree
);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree
);
173 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx
);
176 static bool arm_output_ttype (rtx
);
179 static tree
arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree
arm_get_cookie_size (tree
);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree
);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
192 /* Initialize the GCC target structure. */
193 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
194 #undef TARGET_MERGE_DECL_ATTRIBUTES
195 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
198 #undef TARGET_ATTRIBUTE_TABLE
199 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
201 #undef TARGET_ASM_FILE_END
202 #define TARGET_ASM_FILE_END arm_file_end
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP "\tDCB\t"
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
211 #undef TARGET_ASM_GLOBALIZE_LABEL
212 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
213 #undef TARGET_ASM_FILE_START
214 #define TARGET_ASM_FILE_START aof_file_start
215 #undef TARGET_ASM_FILE_END
216 #define TARGET_ASM_FILE_END aof_file_end
218 #undef TARGET_ASM_ALIGNED_SI_OP
219 #define TARGET_ASM_ALIGNED_SI_OP NULL
220 #undef TARGET_ASM_INTEGER
221 #define TARGET_ASM_INTEGER arm_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
230 #undef TARGET_DEFAULT_TARGET_FLAGS
231 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
232 #undef TARGET_HANDLE_OPTION
233 #define TARGET_HANDLE_OPTION arm_handle_option
235 #undef TARGET_COMP_TYPE_ATTRIBUTES
236 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
238 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
239 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
244 #undef TARGET_ENCODE_SECTION_INFO
246 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
248 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
251 #undef TARGET_STRIP_NAME_ENCODING
252 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
254 #undef TARGET_ASM_INTERNAL_LABEL
255 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
257 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
258 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
260 #undef TARGET_ASM_OUTPUT_MI_THUNK
261 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
262 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
263 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
265 /* This will be overridden in arm_override_options. */
266 #undef TARGET_RTX_COSTS
267 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
268 #undef TARGET_ADDRESS_COST
269 #define TARGET_ADDRESS_COST arm_address_cost
271 #undef TARGET_SHIFT_TRUNCATION_MASK
272 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
273 #undef TARGET_VECTOR_MODE_SUPPORTED_P
274 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
276 #undef TARGET_MACHINE_DEPENDENT_REORG
277 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
279 #undef TARGET_INIT_BUILTINS
280 #define TARGET_INIT_BUILTINS arm_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
284 #undef TARGET_INIT_LIBFUNCS
285 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
287 #undef TARGET_PROMOTE_FUNCTION_ARGS
288 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
289 #undef TARGET_PROMOTE_FUNCTION_RETURN
290 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
291 #undef TARGET_PROMOTE_PROTOTYPES
292 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
293 #undef TARGET_PASS_BY_REFERENCE
294 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
295 #undef TARGET_ARG_PARTIAL_BYTES
296 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
298 #undef TARGET_STRUCT_VALUE_RTX
299 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
301 #undef TARGET_SETUP_INCOMING_VARARGS
302 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
304 #undef TARGET_DEFAULT_SHORT_ENUMS
305 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
307 #undef TARGET_ALIGN_ANON_BITFIELD
308 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
310 #undef TARGET_CXX_GUARD_TYPE
311 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
313 #undef TARGET_CXX_GUARD_MASK_BIT
314 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
316 #undef TARGET_CXX_GET_COOKIE_SIZE
317 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
319 #undef TARGET_CXX_COOKIE_HAS_SIZE
320 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
322 #undef TARGET_CXX_CDTOR_RETURNS_THIS
323 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
325 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
326 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
328 #undef TARGET_CXX_USE_AEABI_ATEXIT
329 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
331 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
332 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
333 arm_cxx_determine_class_data_visibility
335 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
336 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
338 #undef TARGET_RETURN_IN_MSB
339 #define TARGET_RETURN_IN_MSB arm_return_in_msb
341 #undef TARGET_MUST_PASS_IN_STACK
342 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
344 #ifdef TARGET_UNWIND_INFO
345 #undef TARGET_UNWIND_EMIT
346 #define TARGET_UNWIND_EMIT arm_unwind_emit
348 /* EABI unwinding tables use a different format for the typeinfo tables. */
349 #undef TARGET_ASM_TTYPE
350 #define TARGET_ASM_TTYPE arm_output_ttype
352 #undef TARGET_ARM_EABI_UNWINDER
353 #define TARGET_ARM_EABI_UNWINDER true
354 #endif /* TARGET_UNWIND_INFO */
356 struct gcc_target targetm
= TARGET_INITIALIZER
;
358 /* Obstack for minipool constant handling. */
359 static struct obstack minipool_obstack
;
360 static char * minipool_startobj
;
362 /* The maximum number of insns skipped which
363 will be conditionalised if possible. */
364 static int max_insns_skipped
= 5;
366 extern FILE * asm_out_file
;
368 /* True if we are currently building a constant table. */
369 int making_const_table
;
371 /* Define the information needed to generate branch insns. This is
372 stored from the compare operation. */
373 rtx arm_compare_op0
, arm_compare_op1
;
375 /* The processor for which instructions should be scheduled. */
376 enum processor_type arm_tune
= arm_none
;
378 /* Which floating point model to use. */
379 enum arm_fp_model arm_fp_model
;
381 /* Which floating point hardware is available. */
382 enum fputype arm_fpu_arch
;
384 /* Which floating point hardware to schedule for. */
385 enum fputype arm_fpu_tune
;
387 /* Whether to use floating point hardware. */
388 enum float_abi_type arm_float_abi
;
390 /* Which ABI to use. */
391 enum arm_abi_type arm_abi
;
393 /* Used to parse -mstructure_size_boundary command line option. */
394 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
396 /* Used for Thumb call_via trampolines. */
397 rtx thumb_call_via_label
[14];
398 static int thumb_call_reg_needed
;
400 /* Bit values used to identify processor capabilities. */
401 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
402 #define FL_ARCH3M (1 << 1) /* Extended multiply */
403 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
404 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
405 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
406 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
407 #define FL_THUMB (1 << 6) /* Thumb aware */
408 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
409 #define FL_STRONG (1 << 8) /* StrongARM */
410 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
411 #define FL_XSCALE (1 << 10) /* XScale */
412 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
413 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
414 media instructions. */
415 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
416 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
417 Note: ARM6 & 7 derivatives only. */
419 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
421 #define FL_FOR_ARCH2 0
422 #define FL_FOR_ARCH3 FL_MODE32
423 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
424 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
425 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
426 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
427 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
428 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
429 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
430 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
431 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
432 #define FL_FOR_ARCH6J FL_FOR_ARCH6
433 #define FL_FOR_ARCH6K FL_FOR_ARCH6
434 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
435 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6
437 /* The bits in this mask specify which
438 instructions we are allowed to generate. */
439 static unsigned long insn_flags
= 0;
441 /* The bits in this mask specify which instruction scheduling options should
443 static unsigned long tune_flags
= 0;
445 /* The following are used in the arm.md file as equivalents to bits
446 in the above two flag variables. */
448 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
451 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
454 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
457 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
460 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
463 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
466 /* Nonzero if this chip can benefit from load scheduling. */
467 int arm_ld_sched
= 0;
469 /* Nonzero if this chip is a StrongARM. */
470 int arm_tune_strongarm
= 0;
472 /* Nonzero if this chip is a Cirrus variant. */
473 int arm_arch_cirrus
= 0;
475 /* Nonzero if this chip supports Intel Wireless MMX technology. */
476 int arm_arch_iwmmxt
= 0;
478 /* Nonzero if this chip is an XScale. */
479 int arm_arch_xscale
= 0;
481 /* Nonzero if tuning for XScale */
482 int arm_tune_xscale
= 0;
484 /* Nonzero if we want to tune for stores that access the write-buffer.
485 This typically means an ARM6 or ARM7 with MMU or MPU. */
486 int arm_tune_wbuf
= 0;
488 /* Nonzero if generating Thumb instructions. */
491 /* Nonzero if we should define __THUMB_INTERWORK__ in the
493 XXX This is a bit of a hack, it's intended to help work around
494 problems in GLD which doesn't understand that armv5t code is
495 interworking clean. */
496 int arm_cpp_interwork
= 0;
498 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
499 must report the mode of the memory reference from PRINT_OPERAND to
500 PRINT_OPERAND_ADDRESS. */
501 enum machine_mode output_memory_reference_mode
;
503 /* The register number to be used for the PIC offset register. */
504 int arm_pic_register
= INVALID_REGNUM
;
506 /* Set to 1 when a return insn is output, this means that the epilogue
508 int return_used_this_function
;
510 /* Set to 1 after arm_reorg has started. Reset to start at the start of
511 the next function. */
512 static int after_arm_reorg
= 0;
514 /* The maximum number of insns to be used when loading a constant. */
515 static int arm_constant_limit
= 3;
517 /* For an explanation of these variables, see final_prescan_insn below. */
519 enum arm_cond_code arm_current_cc
;
521 int arm_target_label
;
523 /* The condition codes of the ARM, and the inverse function. */
524 static const char * const arm_condition_codes
[] =
526 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
527 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
530 #define streq(string1, string2) (strcmp (string1, string2) == 0)
532 /* Initialization code. */
536 const char *const name
;
537 enum processor_type core
;
539 const unsigned long flags
;
540 bool (* rtx_costs
) (rtx
, int, int, int *);
543 /* Not all of these give usefully different compilation alternatives,
544 but there is no simple way of generalizing them. */
545 static const struct processors all_cores
[] =
548 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
549 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
550 #include "arm-cores.def"
552 {NULL
, arm_none
, NULL
, 0, NULL
}
555 static const struct processors all_architectures
[] =
557 /* ARM Architectures */
558 /* We don't specify rtx_costs here as it will be figured out
561 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
562 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
563 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
564 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
565 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
566 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
567 implementations that support it, so we will leave it out for now. */
568 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
569 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
570 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
571 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
572 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
573 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
574 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
575 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
576 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
577 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
578 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
579 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
580 {NULL
, arm_none
, NULL
, 0 , NULL
}
583 struct arm_cpu_select
587 const struct processors
* processors
;
590 /* This is a magic structure. The 'string' field is magically filled in
591 with a pointer to the value specified by the user on the command line
592 assuming that the user has specified such a value. */
594 static struct arm_cpu_select arm_select
[] =
596 /* string name processors */
597 { NULL
, "-mcpu=", all_cores
},
598 { NULL
, "-march=", all_architectures
},
599 { NULL
, "-mtune=", all_cores
}
602 /* Defines representing the indexes into the above table. */
603 #define ARM_OPT_SET_CPU 0
604 #define ARM_OPT_SET_ARCH 1
605 #define ARM_OPT_SET_TUNE 2
607 /* The name of the proprocessor macro to define for this architecture. */
609 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
618 /* Available values for for -mfpu=. */
620 static const struct fpu_desc all_fpus
[] =
622 {"fpa", FPUTYPE_FPA
},
623 {"fpe2", FPUTYPE_FPA_EMU2
},
624 {"fpe3", FPUTYPE_FPA_EMU2
},
625 {"maverick", FPUTYPE_MAVERICK
},
630 /* Floating point models used by the different hardware.
631 See fputype in arm.h. */
633 static const enum fputype fp_model_for_fpu
[] =
635 /* No FP hardware. */
636 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
637 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
638 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
639 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
640 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
641 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
648 enum float_abi_type abi_type
;
652 /* Available values for -mfloat-abi=. */
654 static const struct float_abi all_float_abis
[] =
656 {"soft", ARM_FLOAT_ABI_SOFT
},
657 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
658 {"hard", ARM_FLOAT_ABI_HARD
}
665 enum arm_abi_type abi_type
;
669 /* Available values for -mabi=. */
671 static const struct abi_name arm_all_abis
[] =
673 {"apcs-gnu", ARM_ABI_APCS
},
674 {"atpcs", ARM_ABI_ATPCS
},
675 {"aapcs", ARM_ABI_AAPCS
},
676 {"iwmmxt", ARM_ABI_IWMMXT
}
679 /* Return the number of bits set in VALUE. */
681 bit_count (unsigned long value
)
683 unsigned long count
= 0;
688 value
&= value
- 1; /* Clear the least-significant set bit. */
694 /* Set up library functions unique to ARM. */
697 arm_init_libfuncs (void)
699 /* There are no special library functions unless we are using the
704 /* The functions below are described in Section 4 of the "Run-Time
705 ABI for the ARM architecture", Version 1.0. */
707 /* Double-precision floating-point arithmetic. Table 2. */
708 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
709 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
710 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
711 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
712 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
714 /* Double-precision comparisons. Table 3. */
715 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
716 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
717 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
718 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
719 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
720 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
721 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
723 /* Single-precision floating-point arithmetic. Table 4. */
724 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
725 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
726 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
727 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
728 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
730 /* Single-precision comparisons. Table 5. */
731 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
732 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
733 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
734 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
735 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
736 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
737 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
739 /* Floating-point to integer conversions. Table 6. */
740 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
741 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
742 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
743 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
744 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
745 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
746 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
747 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
749 /* Conversions between floating types. Table 7. */
750 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
751 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
753 /* Integer to floating-point conversions. Table 8. */
754 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
755 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
756 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
757 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
758 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
759 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
760 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
761 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
763 /* Long long. Table 9. */
764 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
765 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
766 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
767 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
768 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
769 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
770 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
771 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
773 /* Integer (32/32->32) division. \S 4.3.1. */
774 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
775 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
777 /* The divmod functions are designed so that they can be used for
778 plain division, even though they return both the quotient and the
779 remainder. The quotient is returned in the usual location (i.e.,
780 r0 for SImode, {r0, r1} for DImode), just as would be expected
781 for an ordinary division routine. Because the AAPCS calling
782 conventions specify that all of { r0, r1, r2, r3 } are
783 callee-saved registers, there is no need to tell the compiler
784 explicitly that those registers are clobbered by these
786 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
787 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
788 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idivmod");
789 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidivmod");
791 /* We don't have mod libcalls. Fortunately gcc knows how to use the
792 divmod libcalls instead. */
793 set_optab_libfunc (smod_optab
, DImode
, NULL
);
794 set_optab_libfunc (umod_optab
, DImode
, NULL
);
795 set_optab_libfunc (smod_optab
, SImode
, NULL
);
796 set_optab_libfunc (umod_optab
, SImode
, NULL
);
799 /* Implement TARGET_HANDLE_OPTION. */
802 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
807 arm_select
[1].string
= arg
;
811 arm_select
[0].string
= arg
;
814 case OPT_mhard_float
:
815 target_float_abi_name
= "hard";
818 case OPT_msoft_float
:
819 target_float_abi_name
= "soft";
823 arm_select
[2].string
= arg
;
831 /* Fix up any incompatible options that the user has specified.
832 This has now turned into a maze. */
834 arm_override_options (void)
837 enum processor_type target_arch_cpu
= arm_none
;
839 /* Set up the flags based on the cpu/architecture selected by the user. */
840 for (i
= ARRAY_SIZE (arm_select
); i
--;)
842 struct arm_cpu_select
* ptr
= arm_select
+ i
;
844 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
846 const struct processors
* sel
;
848 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
849 if (streq (ptr
->string
, sel
->name
))
851 /* Set the architecture define. */
852 if (i
!= ARM_OPT_SET_TUNE
)
853 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
855 /* Determine the processor core for which we should
856 tune code-generation. */
857 if (/* -mcpu= is a sensible default. */
859 /* -mtune= overrides -mcpu= and -march=. */
860 || i
== ARM_OPT_SET_TUNE
)
861 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
863 /* Remember the CPU associated with this architecture.
864 If no other option is used to set the CPU type,
865 we'll use this to guess the most suitable tuning
867 if (i
== ARM_OPT_SET_ARCH
)
868 target_arch_cpu
= sel
->core
;
870 if (i
!= ARM_OPT_SET_TUNE
)
872 /* If we have been given an architecture and a processor
873 make sure that they are compatible. We only generate
874 a warning though, and we prefer the CPU over the
876 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
877 warning (0, "switch -mcpu=%s conflicts with -march= switch",
880 insn_flags
= sel
->flags
;
886 if (sel
->name
== NULL
)
887 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
891 /* Guess the tuning options from the architecture if necessary. */
892 if (arm_tune
== arm_none
)
893 arm_tune
= target_arch_cpu
;
895 /* If the user did not specify a processor, choose one for them. */
898 const struct processors
* sel
;
900 enum processor_type cpu
;
902 cpu
= TARGET_CPU_DEFAULT
;
905 #ifdef SUBTARGET_CPU_DEFAULT
906 /* Use the subtarget default CPU if none was specified by
908 cpu
= SUBTARGET_CPU_DEFAULT
;
910 /* Default to ARM6. */
914 sel
= &all_cores
[cpu
];
916 insn_flags
= sel
->flags
;
918 /* Now check to see if the user has specified some command line
919 switch that require certain abilities from the cpu. */
922 if (TARGET_INTERWORK
|| TARGET_THUMB
)
924 sought
|= (FL_THUMB
| FL_MODE32
);
926 /* There are no ARM processors that support both APCS-26 and
927 interworking. Therefore we force FL_MODE26 to be removed
928 from insn_flags here (if it was set), so that the search
929 below will always be able to find a compatible processor. */
930 insn_flags
&= ~FL_MODE26
;
933 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
935 /* Try to locate a CPU type that supports all of the abilities
936 of the default CPU, plus the extra abilities requested by
938 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
939 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
942 if (sel
->name
== NULL
)
944 unsigned current_bit_count
= 0;
945 const struct processors
* best_fit
= NULL
;
947 /* Ideally we would like to issue an error message here
948 saying that it was not possible to find a CPU compatible
949 with the default CPU, but which also supports the command
950 line options specified by the programmer, and so they
951 ought to use the -mcpu=<name> command line option to
952 override the default CPU type.
954 If we cannot find a cpu that has both the
955 characteristics of the default cpu and the given
956 command line options we scan the array again looking
958 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
959 if ((sel
->flags
& sought
) == sought
)
963 count
= bit_count (sel
->flags
& insn_flags
);
965 if (count
>= current_bit_count
)
968 current_bit_count
= count
;
972 gcc_assert (best_fit
);
976 insn_flags
= sel
->flags
;
978 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
979 if (arm_tune
== arm_none
)
980 arm_tune
= (enum processor_type
) (sel
- all_cores
);
983 /* The processor for which we should tune should now have been
985 gcc_assert (arm_tune
!= arm_none
);
987 tune_flags
= all_cores
[(int)arm_tune
].flags
;
989 targetm
.rtx_costs
= arm_size_rtx_costs
;
991 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
993 /* Make sure that the processor choice does not conflict with any of the
994 other command line choices. */
995 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
997 warning (0, "target CPU does not support interworking" );
998 target_flags
&= ~MASK_INTERWORK
;
1001 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1003 warning (0, "target CPU does not support THUMB instructions");
1004 target_flags
&= ~MASK_THUMB
;
1007 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1009 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1010 target_flags
&= ~MASK_APCS_FRAME
;
1013 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1014 from here where no function is being compiled currently. */
1015 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1016 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1018 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1019 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1021 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1022 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1024 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1026 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1027 target_flags
|= MASK_APCS_FRAME
;
1030 if (TARGET_POKE_FUNCTION_NAME
)
1031 target_flags
|= MASK_APCS_FRAME
;
1033 if (TARGET_APCS_REENT
&& flag_pic
)
1034 error ("-fpic and -mapcs-reent are incompatible");
1036 if (TARGET_APCS_REENT
)
1037 warning (0, "APCS reentrant code not supported. Ignored");
1039 /* If this target is normally configured to use APCS frames, warn if they
1040 are turned off and debugging is turned on. */
1042 && write_symbols
!= NO_DEBUG
1043 && !TARGET_APCS_FRAME
1044 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1045 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1047 /* If stack checking is disabled, we can use r10 as the PIC register,
1048 which keeps r9 available. */
1050 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1052 if (TARGET_APCS_FLOAT
)
1053 warning (0, "passing floating point arguments in fp regs not yet supported");
1055 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1056 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1057 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1058 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1059 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1060 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1061 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1062 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1063 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1065 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1066 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1067 thumb_code
= (TARGET_ARM
== 0);
1068 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1069 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1070 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1072 /* V5 code we generate is completely interworking capable, so we turn off
1073 TARGET_INTERWORK here to avoid many tests later on. */
1075 /* XXX However, we must pass the right pre-processor defines to CPP
1076 or GLD can get confused. This is a hack. */
1077 if (TARGET_INTERWORK
)
1078 arm_cpp_interwork
= 1;
1081 target_flags
&= ~MASK_INTERWORK
;
1083 if (target_abi_name
)
1085 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1087 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1089 arm_abi
= arm_all_abis
[i
].abi_type
;
1093 if (i
== ARRAY_SIZE (arm_all_abis
))
1094 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1097 arm_abi
= ARM_DEFAULT_ABI
;
1099 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1100 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1102 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1103 error ("iwmmxt abi requires an iwmmxt capable cpu");
1105 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1106 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1108 if (streq (target_fpe_name
, "2"))
1109 target_fpu_name
= "fpe2";
1110 else if (streq (target_fpe_name
, "3"))
1111 target_fpu_name
= "fpe3";
1113 error ("invalid floating point emulation option: -mfpe=%s",
1116 if (target_fpu_name
!= NULL
)
1118 /* The user specified a FPU. */
1119 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1121 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1123 arm_fpu_arch
= all_fpus
[i
].fpu
;
1124 arm_fpu_tune
= arm_fpu_arch
;
1125 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1129 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1130 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1134 #ifdef FPUTYPE_DEFAULT
1135 /* Use the default if it is specified for this platform. */
1136 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1137 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1139 /* Pick one based on CPU type. */
1140 /* ??? Some targets assume FPA is the default.
1141 if ((insn_flags & FL_VFP) != 0)
1142 arm_fpu_arch = FPUTYPE_VFP;
1145 if (arm_arch_cirrus
)
1146 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1148 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1150 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1151 arm_fpu_tune
= FPUTYPE_FPA
;
1153 arm_fpu_tune
= arm_fpu_arch
;
1154 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1155 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1158 if (target_float_abi_name
!= NULL
)
1160 /* The user specified a FP ABI. */
1161 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1163 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1165 arm_float_abi
= all_float_abis
[i
].abi_type
;
1169 if (i
== ARRAY_SIZE (all_float_abis
))
1170 error ("invalid floating point abi: -mfloat-abi=%s",
1171 target_float_abi_name
);
1174 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1176 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1177 sorry ("-mfloat-abi=hard and VFP");
1179 /* If soft-float is specified then don't use FPU. */
1180 if (TARGET_SOFT_FLOAT
)
1181 arm_fpu_arch
= FPUTYPE_NONE
;
1183 /* For arm2/3 there is no need to do any scheduling if there is only
1184 a floating point emulator, or we are doing software floating-point. */
1185 if ((TARGET_SOFT_FLOAT
1186 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1187 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1188 && (tune_flags
& FL_MODE32
) == 0)
1189 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1191 /* Override the default structure alignment for AAPCS ABI. */
1192 if (arm_abi
== ARM_ABI_AAPCS
)
1193 arm_structure_size_boundary
= 8;
1195 if (structure_size_string
!= NULL
)
1197 int size
= strtol (structure_size_string
, NULL
, 0);
1199 if (size
== 8 || size
== 32
1200 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1201 arm_structure_size_boundary
= size
;
1203 warning (0, "structure size boundary can only be set to %s",
1204 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1207 if (arm_pic_register_string
!= NULL
)
1209 int pic_register
= decode_reg_name (arm_pic_register_string
);
1212 warning (0, "-mpic-register= is useless without -fpic");
1214 /* Prevent the user from choosing an obviously stupid PIC register. */
1215 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1216 || pic_register
== HARD_FRAME_POINTER_REGNUM
1217 || pic_register
== STACK_POINTER_REGNUM
1218 || pic_register
>= PC_REGNUM
)
1219 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1221 arm_pic_register
= pic_register
;
1224 if (TARGET_THUMB
&& flag_schedule_insns
)
1226 /* Don't warn since it's on by default in -O2. */
1227 flag_schedule_insns
= 0;
1232 /* There's some dispute as to whether this should be 1 or 2. However,
1233 experiments seem to show that in pathological cases a setting of
1234 1 degrades less severely than a setting of 2. This could change if
1235 other parts of the compiler change their behavior. */
1236 arm_constant_limit
= 1;
1238 /* If optimizing for size, bump the number of instructions that we
1239 are prepared to conditionally execute (even on a StrongARM). */
1240 max_insns_skipped
= 6;
1244 /* For processors with load scheduling, it never costs more than
1245 2 cycles to load a constant, and the load scheduler may well
1246 reduce that to 1. */
1248 arm_constant_limit
= 1;
1250 /* On XScale the longer latency of a load makes it more difficult
1251 to achieve a good schedule, so it's faster to synthesize
1252 constants that can be done in two insns. */
1253 if (arm_tune_xscale
)
1254 arm_constant_limit
= 2;
1256 /* StrongARM has early execution of branches, so a sequence
1257 that is worth skipping is shorter. */
1258 if (arm_tune_strongarm
)
1259 max_insns_skipped
= 3;
1262 /* Register global variables with the garbage collector. */
1263 arm_add_gc_roots ();
1267 arm_add_gc_roots (void)
1269 gcc_obstack_init(&minipool_obstack
);
1270 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1273 /* A table of known ARM exception types.
1274 For use with the interrupt function attribute. */
1278 const char *const arg
;
1279 const unsigned long return_value
;
1283 static const isr_attribute_arg isr_attribute_args
[] =
1285 { "IRQ", ARM_FT_ISR
},
1286 { "irq", ARM_FT_ISR
},
1287 { "FIQ", ARM_FT_FIQ
},
1288 { "fiq", ARM_FT_FIQ
},
1289 { "ABORT", ARM_FT_ISR
},
1290 { "abort", ARM_FT_ISR
},
1291 { "ABORT", ARM_FT_ISR
},
1292 { "abort", ARM_FT_ISR
},
1293 { "UNDEF", ARM_FT_EXCEPTION
},
1294 { "undef", ARM_FT_EXCEPTION
},
1295 { "SWI", ARM_FT_EXCEPTION
},
1296 { "swi", ARM_FT_EXCEPTION
},
1297 { NULL
, ARM_FT_NORMAL
}
1300 /* Returns the (interrupt) function type of the current
1301 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1303 static unsigned long
1304 arm_isr_value (tree argument
)
1306 const isr_attribute_arg
* ptr
;
1309 /* No argument - default to IRQ. */
1310 if (argument
== NULL_TREE
)
1313 /* Get the value of the argument. */
1314 if (TREE_VALUE (argument
) == NULL_TREE
1315 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1316 return ARM_FT_UNKNOWN
;
1318 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1320 /* Check it against the list of known arguments. */
1321 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1322 if (streq (arg
, ptr
->arg
))
1323 return ptr
->return_value
;
1325 /* An unrecognized interrupt type. */
1326 return ARM_FT_UNKNOWN
;
1329 /* Computes the type of the current function. */
1331 static unsigned long
1332 arm_compute_func_type (void)
1334 unsigned long type
= ARM_FT_UNKNOWN
;
1338 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1340 /* Decide if the current function is volatile. Such functions
1341 never return, and many memory cycles can be saved by not storing
1342 register values that will never be needed again. This optimization
1343 was added to speed up context switching in a kernel application. */
1345 && TREE_NOTHROW (current_function_decl
)
1346 && TREE_THIS_VOLATILE (current_function_decl
))
1347 type
|= ARM_FT_VOLATILE
;
1349 if (cfun
->static_chain_decl
!= NULL
)
1350 type
|= ARM_FT_NESTED
;
1352 attr
= DECL_ATTRIBUTES (current_function_decl
);
1354 a
= lookup_attribute ("naked", attr
);
1356 type
|= ARM_FT_NAKED
;
1358 a
= lookup_attribute ("isr", attr
);
1360 a
= lookup_attribute ("interrupt", attr
);
1363 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1365 type
|= arm_isr_value (TREE_VALUE (a
));
1370 /* Returns the type of the current function. */
1373 arm_current_func_type (void)
1375 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1376 cfun
->machine
->func_type
= arm_compute_func_type ();
1378 return cfun
->machine
->func_type
;
1381 /* Return 1 if it is possible to return using a single instruction.
1382 If SIBLING is non-null, this is a test for a return before a sibling
1383 call. SIBLING is the call insn, so we can examine its register usage. */
1386 use_return_insn (int iscond
, rtx sibling
)
1389 unsigned int func_type
;
1390 unsigned long saved_int_regs
;
1391 unsigned HOST_WIDE_INT stack_adjust
;
1392 arm_stack_offsets
*offsets
;
1394 /* Never use a return instruction before reload has run. */
1395 if (!reload_completed
)
1398 func_type
= arm_current_func_type ();
1400 /* Naked functions and volatile functions need special
1402 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1405 /* So do interrupt functions that use the frame pointer. */
1406 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1409 offsets
= arm_get_frame_offsets ();
1410 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1412 /* As do variadic functions. */
1413 if (current_function_pretend_args_size
1414 || cfun
->machine
->uses_anonymous_args
1415 /* Or if the function calls __builtin_eh_return () */
1416 || current_function_calls_eh_return
1417 /* Or if the function calls alloca */
1418 || current_function_calls_alloca
1419 /* Or if there is a stack adjustment. However, if the stack pointer
1420 is saved on the stack, we can use a pre-incrementing stack load. */
1421 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1424 saved_int_regs
= arm_compute_save_reg_mask ();
1426 /* Unfortunately, the insn
1428 ldmib sp, {..., sp, ...}
1430 triggers a bug on most SA-110 based devices, such that the stack
1431 pointer won't be correctly restored if the instruction takes a
1432 page fault. We work around this problem by popping r3 along with
1433 the other registers, since that is never slower than executing
1434 another instruction.
1436 We test for !arm_arch5 here, because code for any architecture
1437 less than this could potentially be run on one of the buggy
1439 if (stack_adjust
== 4 && !arm_arch5
)
1441 /* Validate that r3 is a call-clobbered register (always true in
1442 the default abi) ... */
1443 if (!call_used_regs
[3])
1446 /* ... that it isn't being used for a return value ... */
1447 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1450 /* ... or for a tail-call argument ... */
1453 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1455 if (find_regno_fusage (sibling
, USE
, 3))
1459 /* ... and that there are no call-saved registers in r0-r2
1460 (always true in the default ABI). */
1461 if (saved_int_regs
& 0x7)
1465 /* Can't be done if interworking with Thumb, and any registers have been
1467 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1470 /* On StrongARM, conditional returns are expensive if they aren't
1471 taken and multiple registers have been stacked. */
1472 if (iscond
&& arm_tune_strongarm
)
1474 /* Conditional return when just the LR is stored is a simple
1475 conditional-load instruction, that's not expensive. */
1476 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1479 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1483 /* If there are saved registers but the LR isn't saved, then we need
1484 two instructions for the return. */
1485 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1488 /* Can't be done if any of the FPA regs are pushed,
1489 since this also requires an insn. */
1490 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1491 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1492 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1495 /* Likewise VFP regs. */
1496 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1497 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1498 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1501 if (TARGET_REALLY_IWMMXT
)
1502 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1503 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1509 /* Return TRUE if int I is a valid immediate ARM constant. */
1512 const_ok_for_arm (HOST_WIDE_INT i
)
1516 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1517 be all zero, or all one. */
1518 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1519 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1520 != ((~(unsigned HOST_WIDE_INT
) 0)
1521 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1524 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1526 /* Fast return for 0 and small values. We must do this for zero, since
1527 the code below can't handle that one case. */
1528 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1531 /* Get the number of trailing zeros, rounded down to the nearest even
1533 lowbit
= (ffs ((int) i
) - 1) & ~1;
1535 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1537 else if (lowbit
<= 4
1538 && ((i
& ~0xc000003f) == 0
1539 || (i
& ~0xf000000f) == 0
1540 || (i
& ~0xfc000003) == 0))
1546 /* Return true if I is a valid constant for the operation CODE. */
1548 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1550 if (const_ok_for_arm (i
))
1556 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1558 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1564 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1571 /* Emit a sequence of insns to handle a large constant.
1572 CODE is the code of the operation required, it can be any of SET, PLUS,
1573 IOR, AND, XOR, MINUS;
1574 MODE is the mode in which the operation is being performed;
1575 VAL is the integer to operate on;
1576 SOURCE is the other operand (a register, or a null-pointer for SET);
1577 SUBTARGETS means it is safe to create scratch registers if that will
1578 either produce a simpler sequence, or we will want to cse the values.
1579 Return value is the number of insns emitted. */
1582 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1583 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1587 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1588 cond
= COND_EXEC_TEST (PATTERN (insn
));
1592 if (subtargets
|| code
== SET
1593 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1594 && REGNO (target
) != REGNO (source
)))
1596 /* After arm_reorg has been called, we can't fix up expensive
1597 constants by pushing them into memory so we must synthesize
1598 them in-line, regardless of the cost. This is only likely to
1599 be more costly on chips that have load delay slots and we are
1600 compiling without running the scheduler (so no splitting
1601 occurred before the final instruction emission).
1603 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1605 if (!after_arm_reorg
1607 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1609 > arm_constant_limit
+ (code
!= SET
)))
1613 /* Currently SET is the only monadic value for CODE, all
1614 the rest are diadic. */
1615 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1620 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1622 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1623 /* For MINUS, the value is subtracted from, since we never
1624 have subtraction of a constant. */
1626 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1627 gen_rtx_MINUS (mode
, temp
, source
)));
1629 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1630 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1636 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1641 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1643 HOST_WIDE_INT temp1
;
1651 if (remainder
& (3 << (i
- 2)))
1656 temp1
= remainder
& ((0x0ff << end
)
1657 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1658 remainder
&= ~temp1
;
1663 } while (remainder
);
1667 /* Emit an instruction with the indicated PATTERN. If COND is
1668 non-NULL, conditionalize the execution of the instruction on COND
1672 emit_constant_insn (rtx cond
, rtx pattern
)
1675 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1676 emit_insn (pattern
);
1679 /* As above, but extra parameter GENERATE which, if clear, suppresses
1683 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1684 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1689 int can_negate_initial
= 0;
1692 int num_bits_set
= 0;
1693 int set_sign_bit_copies
= 0;
1694 int clear_sign_bit_copies
= 0;
1695 int clear_zero_bit_copies
= 0;
1696 int set_zero_bit_copies
= 0;
1698 unsigned HOST_WIDE_INT temp1
, temp2
;
1699 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1701 /* Find out which operations are safe for a given CODE. Also do a quick
1702 check for degenerate cases; these can occur when DImode operations
1714 can_negate_initial
= 1;
1718 if (remainder
== 0xffffffff)
1721 emit_constant_insn (cond
,
1722 gen_rtx_SET (VOIDmode
, target
,
1723 GEN_INT (ARM_SIGN_EXTEND (val
))));
1728 if (reload_completed
&& rtx_equal_p (target
, source
))
1731 emit_constant_insn (cond
,
1732 gen_rtx_SET (VOIDmode
, target
, source
));
1741 emit_constant_insn (cond
,
1742 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1745 if (remainder
== 0xffffffff)
1747 if (reload_completed
&& rtx_equal_p (target
, source
))
1750 emit_constant_insn (cond
,
1751 gen_rtx_SET (VOIDmode
, target
, source
));
1760 if (reload_completed
&& rtx_equal_p (target
, source
))
1763 emit_constant_insn (cond
,
1764 gen_rtx_SET (VOIDmode
, target
, source
));
1768 /* We don't know how to handle other cases yet. */
1769 gcc_assert (remainder
== 0xffffffff);
1772 emit_constant_insn (cond
,
1773 gen_rtx_SET (VOIDmode
, target
,
1774 gen_rtx_NOT (mode
, source
)));
1778 /* We treat MINUS as (val - source), since (source - val) is always
1779 passed as (source + (-val)). */
1783 emit_constant_insn (cond
,
1784 gen_rtx_SET (VOIDmode
, target
,
1785 gen_rtx_NEG (mode
, source
)));
1788 if (const_ok_for_arm (val
))
1791 emit_constant_insn (cond
,
1792 gen_rtx_SET (VOIDmode
, target
,
1793 gen_rtx_MINUS (mode
, GEN_INT (val
),
1805 /* If we can do it in one insn get out quickly. */
1806 if (const_ok_for_arm (val
)
1807 || (can_negate_initial
&& const_ok_for_arm (-val
))
1808 || (can_invert
&& const_ok_for_arm (~val
)))
1811 emit_constant_insn (cond
,
1812 gen_rtx_SET (VOIDmode
, target
,
1814 ? gen_rtx_fmt_ee (code
, mode
, source
,
1820 /* Calculate a few attributes that may be useful for specific
1822 for (i
= 31; i
>= 0; i
--)
1824 if ((remainder
& (1 << i
)) == 0)
1825 clear_sign_bit_copies
++;
1830 for (i
= 31; i
>= 0; i
--)
1832 if ((remainder
& (1 << i
)) != 0)
1833 set_sign_bit_copies
++;
1838 for (i
= 0; i
<= 31; i
++)
1840 if ((remainder
& (1 << i
)) == 0)
1841 clear_zero_bit_copies
++;
1846 for (i
= 0; i
<= 31; i
++)
1848 if ((remainder
& (1 << i
)) != 0)
1849 set_zero_bit_copies
++;
1857 /* See if we can do this by sign_extending a constant that is known
1858 to be negative. This is a good, way of doing it, since the shift
1859 may well merge into a subsequent insn. */
1860 if (set_sign_bit_copies
> 1)
1862 if (const_ok_for_arm
1863 (temp1
= ARM_SIGN_EXTEND (remainder
1864 << (set_sign_bit_copies
- 1))))
1868 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1869 emit_constant_insn (cond
,
1870 gen_rtx_SET (VOIDmode
, new_src
,
1872 emit_constant_insn (cond
,
1873 gen_ashrsi3 (target
, new_src
,
1874 GEN_INT (set_sign_bit_copies
- 1)));
1878 /* For an inverted constant, we will need to set the low bits,
1879 these will be shifted out of harm's way. */
1880 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1881 if (const_ok_for_arm (~temp1
))
1885 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1886 emit_constant_insn (cond
,
1887 gen_rtx_SET (VOIDmode
, new_src
,
1889 emit_constant_insn (cond
,
1890 gen_ashrsi3 (target
, new_src
,
1891 GEN_INT (set_sign_bit_copies
- 1)));
1897 /* See if we can calculate the value as the difference between two
1898 valid immediates. */
1899 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1901 int topshift
= clear_sign_bit_copies
& ~1;
1903 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1904 & (0xff000000 >> topshift
));
1906 /* If temp1 is zero, then that means the 9 most significant
1907 bits of remainder were 1 and we've caused it to overflow.
1908 When topshift is 0 we don't need to do anything since we
1909 can borrow from 'bit 32'. */
1910 if (temp1
== 0 && topshift
!= 0)
1911 temp1
= 0x80000000 >> (topshift
- 1);
1913 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1915 if (const_ok_for_arm (temp2
))
1919 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1920 emit_constant_insn (cond
,
1921 gen_rtx_SET (VOIDmode
, new_src
,
1923 emit_constant_insn (cond
,
1924 gen_addsi3 (target
, new_src
,
1932 /* See if we can generate this by setting the bottom (or the top)
1933 16 bits, and then shifting these into the other half of the
1934 word. We only look for the simplest cases, to do more would cost
1935 too much. Be careful, however, not to generate this when the
1936 alternative would take fewer insns. */
1937 if (val
& 0xffff0000)
1939 temp1
= remainder
& 0xffff0000;
1940 temp2
= remainder
& 0x0000ffff;
1942 /* Overlaps outside this range are best done using other methods. */
1943 for (i
= 9; i
< 24; i
++)
1945 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1946 && !const_ok_for_arm (temp2
))
1948 rtx new_src
= (subtargets
1949 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1951 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
1952 source
, subtargets
, generate
);
1960 gen_rtx_ASHIFT (mode
, source
,
1967 /* Don't duplicate cases already considered. */
1968 for (i
= 17; i
< 24; i
++)
1970 if (((temp1
| (temp1
>> i
)) == remainder
)
1971 && !const_ok_for_arm (temp1
))
1973 rtx new_src
= (subtargets
1974 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1976 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
1977 source
, subtargets
, generate
);
1982 gen_rtx_SET (VOIDmode
, target
,
1985 gen_rtx_LSHIFTRT (mode
, source
,
1996 /* If we have IOR or XOR, and the constant can be loaded in a
1997 single instruction, and we can find a temporary to put it in,
1998 then this can be done in two instructions instead of 3-4. */
2000 /* TARGET can't be NULL if SUBTARGETS is 0 */
2001 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2003 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2007 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2009 emit_constant_insn (cond
,
2010 gen_rtx_SET (VOIDmode
, sub
,
2012 emit_constant_insn (cond
,
2013 gen_rtx_SET (VOIDmode
, target
,
2014 gen_rtx_fmt_ee (code
, mode
,
2024 if (set_sign_bit_copies
> 8
2025 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2029 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2030 rtx shift
= GEN_INT (set_sign_bit_copies
);
2034 gen_rtx_SET (VOIDmode
, sub
,
2036 gen_rtx_ASHIFT (mode
,
2041 gen_rtx_SET (VOIDmode
, target
,
2043 gen_rtx_LSHIFTRT (mode
, sub
,
2049 if (set_zero_bit_copies
> 8
2050 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2054 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2055 rtx shift
= GEN_INT (set_zero_bit_copies
);
2059 gen_rtx_SET (VOIDmode
, sub
,
2061 gen_rtx_LSHIFTRT (mode
,
2066 gen_rtx_SET (VOIDmode
, target
,
2068 gen_rtx_ASHIFT (mode
, sub
,
2074 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2078 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2079 emit_constant_insn (cond
,
2080 gen_rtx_SET (VOIDmode
, sub
,
2081 gen_rtx_NOT (mode
, source
)));
2084 sub
= gen_reg_rtx (mode
);
2085 emit_constant_insn (cond
,
2086 gen_rtx_SET (VOIDmode
, sub
,
2087 gen_rtx_AND (mode
, source
,
2089 emit_constant_insn (cond
,
2090 gen_rtx_SET (VOIDmode
, target
,
2091 gen_rtx_NOT (mode
, sub
)));
2098 /* See if two shifts will do 2 or more insn's worth of work. */
2099 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2101 HOST_WIDE_INT shift_mask
= ((0xffffffff
2102 << (32 - clear_sign_bit_copies
))
2105 if ((remainder
| shift_mask
) != 0xffffffff)
2109 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2110 insns
= arm_gen_constant (AND
, mode
, cond
,
2111 remainder
| shift_mask
,
2112 new_src
, source
, subtargets
, 1);
2117 rtx targ
= subtargets
? NULL_RTX
: target
;
2118 insns
= arm_gen_constant (AND
, mode
, cond
,
2119 remainder
| shift_mask
,
2120 targ
, source
, subtargets
, 0);
2126 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2127 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2129 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2130 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2136 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2138 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2140 if ((remainder
| shift_mask
) != 0xffffffff)
2144 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2146 insns
= arm_gen_constant (AND
, mode
, cond
,
2147 remainder
| shift_mask
,
2148 new_src
, source
, subtargets
, 1);
2153 rtx targ
= subtargets
? NULL_RTX
: target
;
2155 insns
= arm_gen_constant (AND
, mode
, cond
,
2156 remainder
| shift_mask
,
2157 targ
, source
, subtargets
, 0);
2163 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2164 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2166 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2167 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2179 for (i
= 0; i
< 32; i
++)
2180 if (remainder
& (1 << i
))
2183 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2184 remainder
= (~remainder
) & 0xffffffff;
2185 else if (code
== PLUS
&& num_bits_set
> 16)
2186 remainder
= (-remainder
) & 0xffffffff;
2193 /* Now try and find a way of doing the job in either two or three
2195 We start by looking for the largest block of zeros that are aligned on
2196 a 2-bit boundary, we then fill up the temps, wrapping around to the
2197 top of the word when we drop off the bottom.
2198 In the worst case this code should produce no more than four insns. */
2201 int best_consecutive_zeros
= 0;
2203 for (i
= 0; i
< 32; i
+= 2)
2205 int consecutive_zeros
= 0;
2207 if (!(remainder
& (3 << i
)))
2209 while ((i
< 32) && !(remainder
& (3 << i
)))
2211 consecutive_zeros
+= 2;
2214 if (consecutive_zeros
> best_consecutive_zeros
)
2216 best_consecutive_zeros
= consecutive_zeros
;
2217 best_start
= i
- consecutive_zeros
;
2223 /* So long as it won't require any more insns to do so, it's
2224 desirable to emit a small constant (in bits 0...9) in the last
2225 insn. This way there is more chance that it can be combined with
2226 a later addressing insn to form a pre-indexed load or store
2227 operation. Consider:
2229 *((volatile int *)0xe0000100) = 1;
2230 *((volatile int *)0xe0000110) = 2;
2232 We want this to wind up as:
2236 str rB, [rA, #0x100]
2238 str rB, [rA, #0x110]
2240 rather than having to synthesize both large constants from scratch.
2242 Therefore, we calculate how many insns would be required to emit
2243 the constant starting from `best_start', and also starting from
2244 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2245 yield a shorter sequence, we may as well use zero. */
2247 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2248 && (count_insns_for_constant (remainder
, 0) <=
2249 count_insns_for_constant (remainder
, best_start
)))
2252 /* Now start emitting the insns. */
2260 if (remainder
& (3 << (i
- 2)))
2265 temp1
= remainder
& ((0x0ff << end
)
2266 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2267 remainder
&= ~temp1
;
2271 rtx new_src
, temp1_rtx
;
2273 if (code
== SET
|| code
== MINUS
)
2275 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2276 if (can_invert
&& code
!= MINUS
)
2281 if (remainder
&& subtargets
)
2282 new_src
= gen_reg_rtx (mode
);
2287 else if (can_negate
)
2291 temp1
= trunc_int_for_mode (temp1
, mode
);
2292 temp1_rtx
= GEN_INT (temp1
);
2296 else if (code
== MINUS
)
2297 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2299 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2301 emit_constant_insn (cond
,
2302 gen_rtx_SET (VOIDmode
, new_src
,
2312 else if (code
== MINUS
)
2326 /* Canonicalize a comparison so that we are more likely to recognize it.
2327 This can be done for a few constant compares, where we can make the
2328 immediate value easier to load. */
2331 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2334 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2335 unsigned HOST_WIDE_INT maxval
;
2336 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2347 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2349 *op1
= GEN_INT (i
+ 1);
2350 return code
== GT
? GE
: LT
;
2357 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2359 *op1
= GEN_INT (i
- 1);
2360 return code
== GE
? GT
: LE
;
2366 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2367 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2369 *op1
= GEN_INT (i
+ 1);
2370 return code
== GTU
? GEU
: LTU
;
2377 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2379 *op1
= GEN_INT (i
- 1);
2380 return code
== GEU
? GTU
: LEU
;
2392 /* Define how to find the value returned by a function. */
2395 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2397 enum machine_mode mode
;
2398 int unsignedp ATTRIBUTE_UNUSED
;
2399 rtx r ATTRIBUTE_UNUSED
;
2401 mode
= TYPE_MODE (type
);
2402 /* Promote integer types. */
2403 if (INTEGRAL_TYPE_P (type
))
2404 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2406 /* Promotes small structs returned in a register to full-word size
2407 for big-endian AAPCS. */
2408 if (arm_return_in_msb (type
))
2410 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2411 if (size
% UNITS_PER_WORD
!= 0)
2413 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2414 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2418 return LIBCALL_VALUE(mode
);
2421 /* Determine the amount of memory needed to store the possible return
2422 registers of an untyped call. */
2424 arm_apply_result_size (void)
2430 if (TARGET_HARD_FLOAT_ABI
)
2434 if (TARGET_MAVERICK
)
2437 if (TARGET_IWMMXT_ABI
)
2444 /* Decide whether a type should be returned in memory (true)
2445 or in a register (false). This is called by the macro
2446 RETURN_IN_MEMORY. */
2448 arm_return_in_memory (tree type
)
2452 if (!AGGREGATE_TYPE_P (type
) &&
2453 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2454 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2455 /* All simple types are returned in registers.
2456 For AAPCS, complex types are treated the same as aggregates. */
2459 size
= int_size_in_bytes (type
);
2461 if (arm_abi
!= ARM_ABI_APCS
)
2463 /* ATPCS and later return aggregate types in memory only if they are
2464 larger than a word (or are variable size). */
2465 return (size
< 0 || size
> UNITS_PER_WORD
);
2468 /* To maximize backwards compatibility with previous versions of gcc,
2469 return vectors up to 4 words in registers. */
2470 if (TREE_CODE (type
) == VECTOR_TYPE
)
2471 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2473 /* For the arm-wince targets we choose to be compatible with Microsoft's
2474 ARM and Thumb compilers, which always return aggregates in memory. */
2476 /* All structures/unions bigger than one word are returned in memory.
2477 Also catch the case where int_size_in_bytes returns -1. In this case
2478 the aggregate is either huge or of variable size, and in either case
2479 we will want to return it via memory and not in a register. */
2480 if (size
< 0 || size
> UNITS_PER_WORD
)
2483 if (TREE_CODE (type
) == RECORD_TYPE
)
2487 /* For a struct the APCS says that we only return in a register
2488 if the type is 'integer like' and every addressable element
2489 has an offset of zero. For practical purposes this means
2490 that the structure can have at most one non bit-field element
2491 and that this element must be the first one in the structure. */
2493 /* Find the first field, ignoring non FIELD_DECL things which will
2494 have been created by C++. */
2495 for (field
= TYPE_FIELDS (type
);
2496 field
&& TREE_CODE (field
) != FIELD_DECL
;
2497 field
= TREE_CHAIN (field
))
2501 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2503 /* Check that the first field is valid for returning in a register. */
2505 /* ... Floats are not allowed */
2506 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2509 /* ... Aggregates that are not themselves valid for returning in
2510 a register are not allowed. */
2511 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2514 /* Now check the remaining fields, if any. Only bitfields are allowed,
2515 since they are not addressable. */
2516 for (field
= TREE_CHAIN (field
);
2518 field
= TREE_CHAIN (field
))
2520 if (TREE_CODE (field
) != FIELD_DECL
)
2523 if (!DECL_BIT_FIELD_TYPE (field
))
2530 if (TREE_CODE (type
) == UNION_TYPE
)
2534 /* Unions can be returned in registers if every element is
2535 integral, or can be returned in an integer register. */
2536 for (field
= TYPE_FIELDS (type
);
2538 field
= TREE_CHAIN (field
))
2540 if (TREE_CODE (field
) != FIELD_DECL
)
2543 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2546 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2552 #endif /* not ARM_WINCE */
2554 /* Return all other types in memory. */
2558 /* Indicate whether or not words of a double are in big-endian order. */
2561 arm_float_words_big_endian (void)
2563 if (TARGET_MAVERICK
)
2566 /* For FPA, float words are always big-endian. For VFP, floats words
2567 follow the memory system mode. */
2575 return (TARGET_BIG_END
? 1 : 0);
2580 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2581 for a call to a function whose data type is FNTYPE.
2582 For a library call, FNTYPE is NULL. */
2584 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2585 rtx libname ATTRIBUTE_UNUSED
,
2586 tree fndecl ATTRIBUTE_UNUSED
)
2588 /* On the ARM, the offset starts at 0. */
2589 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2590 pcum
->iwmmxt_nregs
= 0;
2591 pcum
->can_split
= true;
2593 pcum
->call_cookie
= CALL_NORMAL
;
2595 if (TARGET_LONG_CALLS
)
2596 pcum
->call_cookie
= CALL_LONG
;
2598 /* Check for long call/short call attributes. The attributes
2599 override any command line option. */
2602 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2603 pcum
->call_cookie
= CALL_SHORT
;
2604 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2605 pcum
->call_cookie
= CALL_LONG
;
2608 /* Varargs vectors are treated the same as long long.
2609 named_count avoids having to change the way arm handles 'named' */
2610 pcum
->named_count
= 0;
2613 if (TARGET_REALLY_IWMMXT
&& fntype
)
2617 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2619 fn_arg
= TREE_CHAIN (fn_arg
))
2620 pcum
->named_count
+= 1;
2622 if (! pcum
->named_count
)
2623 pcum
->named_count
= INT_MAX
;
2628 /* Return true if mode/type need doubleword alignment. */
2630 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2632 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2633 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2637 /* Determine where to put an argument to a function.
2638 Value is zero to push the argument on the stack,
2639 or a hard register in which to store the argument.
2641 MODE is the argument's machine mode.
2642 TYPE is the data type of the argument (as a tree).
2643 This is null for libcalls where that information may
2645 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2646 the preceding args and about the function being called.
2647 NAMED is nonzero if this argument is a named parameter
2648 (otherwise it is an extra parameter matching an ellipsis). */
2651 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2652 tree type
, int named
)
2656 /* Varargs vectors are treated the same as long long.
2657 named_count avoids having to change the way arm handles 'named' */
2658 if (TARGET_IWMMXT_ABI
2659 && arm_vector_mode_supported_p (mode
)
2660 && pcum
->named_count
> pcum
->nargs
+ 1)
2662 if (pcum
->iwmmxt_nregs
<= 9)
2663 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2666 pcum
->can_split
= false;
2671 /* Put doubleword aligned quantities in even register pairs. */
2673 && ARM_DOUBLEWORD_ALIGN
2674 && arm_needs_doubleword_align (mode
, type
))
2677 if (mode
== VOIDmode
)
2678 /* Compute operand 2 of the call insn. */
2679 return GEN_INT (pcum
->call_cookie
);
2681 /* Only allow splitting an arg between regs and memory if all preceding
2682 args were allocated to regs. For args passed by reference we only count
2683 the reference pointer. */
2684 if (pcum
->can_split
)
2687 nregs
= ARM_NUM_REGS2 (mode
, type
);
2689 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2692 return gen_rtx_REG (mode
, pcum
->nregs
);
2696 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2697 tree type
, bool named ATTRIBUTE_UNUSED
)
2699 int nregs
= pcum
->nregs
;
2701 if (arm_vector_mode_supported_p (mode
))
2704 if (NUM_ARG_REGS
> nregs
2705 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2707 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2712 /* Variable sized types are passed by reference. This is a GCC
2713 extension to the ARM ABI. */
2716 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2717 enum machine_mode mode ATTRIBUTE_UNUSED
,
2718 tree type
, bool named ATTRIBUTE_UNUSED
)
2720 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2723 /* Encode the current state of the #pragma [no_]long_calls. */
2726 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2727 LONG
, /* #pragma long_calls is in effect. */
2728 SHORT
/* #pragma no_long_calls is in effect. */
2731 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2734 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2736 arm_pragma_long_calls
= LONG
;
2740 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2742 arm_pragma_long_calls
= SHORT
;
2746 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2748 arm_pragma_long_calls
= OFF
;
2751 /* Table of machine attributes. */
2752 const struct attribute_spec arm_attribute_table
[] =
2754 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2755 /* Function calls made to this symbol must be done indirectly, because
2756 it may lie outside of the 26 bit addressing range of a normal function
2758 { "long_call", 0, 0, false, true, true, NULL
},
2759 /* Whereas these functions are always known to reside within the 26 bit
2760 addressing range. */
2761 { "short_call", 0, 0, false, true, true, NULL
},
2762 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2763 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2764 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2765 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2767 /* ARM/PE has three new attributes:
2769 dllexport - for exporting a function/variable that will live in a dll
2770 dllimport - for importing a function/variable from a dll
2772 Microsoft allows multiple declspecs in one __declspec, separating
2773 them with spaces. We do NOT support this. Instead, use __declspec
2776 { "dllimport", 0, 0, true, false, false, NULL
},
2777 { "dllexport", 0, 0, true, false, false, NULL
},
2778 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2779 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2780 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2781 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2782 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2784 { NULL
, 0, 0, false, false, false, NULL
}
2787 /* Handle an attribute requiring a FUNCTION_DECL;
2788 arguments as in struct attribute_spec.handler. */
2790 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2791 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2793 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2795 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2796 IDENTIFIER_POINTER (name
));
2797 *no_add_attrs
= true;
2803 /* Handle an "interrupt" or "isr" attribute;
2804 arguments as in struct attribute_spec.handler. */
2806 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2811 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2813 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2814 IDENTIFIER_POINTER (name
));
2815 *no_add_attrs
= true;
2817 /* FIXME: the argument if any is checked for type attributes;
2818 should it be checked for decl ones? */
2822 if (TREE_CODE (*node
) == FUNCTION_TYPE
2823 || TREE_CODE (*node
) == METHOD_TYPE
)
2825 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2827 warning (OPT_Wattributes
, "%qs attribute ignored",
2828 IDENTIFIER_POINTER (name
));
2829 *no_add_attrs
= true;
2832 else if (TREE_CODE (*node
) == POINTER_TYPE
2833 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2834 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2835 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2837 *node
= build_variant_type_copy (*node
);
2838 TREE_TYPE (*node
) = build_type_attribute_variant
2840 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2841 *no_add_attrs
= true;
2845 /* Possibly pass this attribute on from the type to a decl. */
2846 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2847 | (int) ATTR_FLAG_FUNCTION_NEXT
2848 | (int) ATTR_FLAG_ARRAY_NEXT
))
2850 *no_add_attrs
= true;
2851 return tree_cons (name
, args
, NULL_TREE
);
2855 warning (OPT_Wattributes
, "%qs attribute ignored",
2856 IDENTIFIER_POINTER (name
));
2864 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2865 /* Handle the "notshared" attribute. This attribute is another way of
2866 requesting hidden visibility. ARM's compiler supports
2867 "__declspec(notshared)"; we support the same thing via an
2871 arm_handle_notshared_attribute (tree
*node
,
2872 tree name ATTRIBUTE_UNUSED
,
2873 tree args ATTRIBUTE_UNUSED
,
2874 int flags ATTRIBUTE_UNUSED
,
2877 tree decl
= TYPE_NAME (*node
);
2881 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2882 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2883 *no_add_attrs
= false;
2889 /* Return 0 if the attributes for two types are incompatible, 1 if they
2890 are compatible, and 2 if they are nearly compatible (which causes a
2891 warning to be generated). */
2893 arm_comp_type_attributes (tree type1
, tree type2
)
2897 /* Check for mismatch of non-default calling convention. */
2898 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2901 /* Check for mismatched call attributes. */
2902 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2903 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2904 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2905 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2907 /* Only bother to check if an attribute is defined. */
2908 if (l1
| l2
| s1
| s2
)
2910 /* If one type has an attribute, the other must have the same attribute. */
2911 if ((l1
!= l2
) || (s1
!= s2
))
2914 /* Disallow mixed attributes. */
2915 if ((l1
& s2
) || (l2
& s1
))
2919 /* Check for mismatched ISR attribute. */
2920 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2922 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2923 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2925 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2932 /* Encode long_call or short_call attribute by prefixing
2933 symbol name in DECL with a special character FLAG. */
2935 arm_encode_call_attribute (tree decl
, int flag
)
2937 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2938 int len
= strlen (str
);
2941 /* Do not allow weak functions to be treated as short call. */
2942 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2945 newstr
= alloca (len
+ 2);
2947 strcpy (newstr
+ 1, str
);
2949 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2950 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2953 /* Assigns default attributes to newly defined type. This is used to
2954 set short_call/long_call attributes for function types of
2955 functions defined inside corresponding #pragma scopes. */
2957 arm_set_default_type_attributes (tree type
)
2959 /* Add __attribute__ ((long_call)) to all functions, when
2960 inside #pragma long_calls or __attribute__ ((short_call)),
2961 when inside #pragma no_long_calls. */
2962 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2964 tree type_attr_list
, attr_name
;
2965 type_attr_list
= TYPE_ATTRIBUTES (type
);
2967 if (arm_pragma_long_calls
== LONG
)
2968 attr_name
= get_identifier ("long_call");
2969 else if (arm_pragma_long_calls
== SHORT
)
2970 attr_name
= get_identifier ("short_call");
2974 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2975 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2979 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2980 defined within the current compilation unit. If this cannot be
2981 determined, then 0 is returned. */
2983 current_file_function_operand (rtx sym_ref
)
2985 /* This is a bit of a fib. A function will have a short call flag
2986 applied to its name if it has the short call attribute, or it has
2987 already been defined within the current compilation unit. */
2988 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2991 /* The current function is always defined within the current compilation
2992 unit. If it s a weak definition however, then this may not be the real
2993 definition of the function, and so we have to say no. */
2994 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2995 && !DECL_WEAK (current_function_decl
))
2998 /* We cannot make the determination - default to returning 0. */
3002 /* Return nonzero if a 32 bit "long_call" should be generated for
3003 this call. We generate a long_call if the function:
3005 a. has an __attribute__((long call))
3006 or b. is within the scope of a #pragma long_calls
3007 or c. the -mlong-calls command line switch has been specified
3009 1. -ffunction-sections is in effect
3010 or 2. the current function has __attribute__ ((section))
3011 or 3. the target function has __attribute__ ((section))
3013 However we do not generate a long call if the function:
3015 d. has an __attribute__ ((short_call))
3016 or e. is inside the scope of a #pragma no_long_calls
3017 or f. is defined within the current compilation unit.
3019 This function will be called by C fragments contained in the machine
3020 description file. SYM_REF and CALL_COOKIE correspond to the matched
3021 rtl operands. CALL_SYMBOL is used to distinguish between
3022 two different callers of the function. It is set to 1 in the
3023 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3024 and "call_value" patterns. This is because of the difference in the
3025 SYM_REFs passed by these patterns. */
3027 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3031 if (GET_CODE (sym_ref
) != MEM
)
3034 sym_ref
= XEXP (sym_ref
, 0);
3037 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3040 if (call_cookie
& CALL_SHORT
)
3043 if (TARGET_LONG_CALLS
)
3045 if (flag_function_sections
3046 || DECL_SECTION_NAME (current_function_decl
))
3047 /* c.3 is handled by the definition of the
3048 ARM_DECLARE_FUNCTION_SIZE macro. */
3052 if (current_file_function_operand (sym_ref
))
3055 return (call_cookie
& CALL_LONG
)
3056 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3057 || TARGET_LONG_CALLS
;
3060 /* Return nonzero if it is ok to make a tail-call to DECL. */
3062 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3064 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3066 if (cfun
->machine
->sibcall_blocked
)
3069 /* Never tailcall something for which we have no decl, or if we
3070 are in Thumb mode. */
3071 if (decl
== NULL
|| TARGET_THUMB
)
3074 /* Get the calling method. */
3075 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3076 call_type
= CALL_SHORT
;
3077 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3078 call_type
= CALL_LONG
;
3080 /* Cannot tail-call to long calls, since these are out of range of
3081 a branch instruction. However, if not compiling PIC, we know
3082 we can reach the symbol if it is in this compilation unit. */
3083 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3086 /* If we are interworking and the function is not declared static
3087 then we can't tail-call it unless we know that it exists in this
3088 compilation unit (since it might be a Thumb routine). */
3089 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3092 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3093 if (IS_INTERRUPT (arm_current_func_type ()))
3096 /* Everything else is ok. */
3101 /* Addressing mode support functions. */
3103 /* Return nonzero if X is a legitimate immediate operand when compiling
3106 legitimate_pic_operand_p (rtx x
)
3110 && (GET_CODE (x
) == SYMBOL_REF
3111 || (GET_CODE (x
) == CONST
3112 && GET_CODE (XEXP (x
, 0)) == PLUS
3113 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
3120 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3122 if (GET_CODE (orig
) == SYMBOL_REF
3123 || GET_CODE (orig
) == LABEL_REF
)
3125 #ifndef AOF_ASSEMBLER
3126 rtx pic_ref
, address
;
3133 gcc_assert (!no_new_pseudos
);
3134 reg
= gen_reg_rtx (Pmode
);
3139 #ifdef AOF_ASSEMBLER
3140 /* The AOF assembler can generate relocations for these directly, and
3141 understands that the PIC register has to be added into the offset. */
3142 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3145 address
= gen_reg_rtx (Pmode
);
3150 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3152 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3154 if ((GET_CODE (orig
) == LABEL_REF
3155 || (GET_CODE (orig
) == SYMBOL_REF
&&
3156 SYMBOL_REF_LOCAL_P (orig
)))
3158 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
3161 pic_ref
= gen_const_mem (Pmode
,
3162 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3166 insn
= emit_move_insn (reg
, pic_ref
);
3168 current_function_uses_pic_offset_table
= 1;
3169 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3171 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3175 else if (GET_CODE (orig
) == CONST
)
3179 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3180 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3185 gcc_assert (!no_new_pseudos
);
3186 reg
= gen_reg_rtx (Pmode
);
3189 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3191 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3192 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3193 base
== reg
? 0 : reg
);
3195 if (GET_CODE (offset
) == CONST_INT
)
3197 /* The base register doesn't really matter, we only want to
3198 test the index for the appropriate mode. */
3199 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3201 gcc_assert (!no_new_pseudos
);
3202 offset
= force_reg (Pmode
, offset
);
3205 if (GET_CODE (offset
) == CONST_INT
)
3206 return plus_constant (base
, INTVAL (offset
));
3209 if (GET_MODE_SIZE (mode
) > 4
3210 && (GET_MODE_CLASS (mode
) == MODE_INT
3211 || TARGET_SOFT_FLOAT
))
3213 emit_insn (gen_addsi3 (reg
, base
, offset
));
3217 return gen_rtx_PLUS (Pmode
, base
, offset
);
3224 /* Find a spare low register to use during the prolog of a function. */
3227 thumb_find_work_register (unsigned long pushed_regs_mask
)
3231 /* Check the argument registers first as these are call-used. The
3232 register allocation order means that sometimes r3 might be used
3233 but earlier argument registers might not, so check them all. */
3234 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3235 if (!regs_ever_live
[reg
])
3238 /* Before going on to check the call-saved registers we can try a couple
3239 more ways of deducing that r3 is available. The first is when we are
3240 pushing anonymous arguments onto the stack and we have less than 4
3241 registers worth of fixed arguments(*). In this case r3 will be part of
3242 the variable argument list and so we can be sure that it will be
3243 pushed right at the start of the function. Hence it will be available
3244 for the rest of the prologue.
3245 (*): ie current_function_pretend_args_size is greater than 0. */
3246 if (cfun
->machine
->uses_anonymous_args
3247 && current_function_pretend_args_size
> 0)
3248 return LAST_ARG_REGNUM
;
3250 /* The other case is when we have fixed arguments but less than 4 registers
3251 worth. In this case r3 might be used in the body of the function, but
3252 it is not being used to convey an argument into the function. In theory
3253 we could just check current_function_args_size to see how many bytes are
3254 being passed in argument registers, but it seems that it is unreliable.
3255 Sometimes it will have the value 0 when in fact arguments are being
3256 passed. (See testcase execute/20021111-1.c for an example). So we also
3257 check the args_info.nregs field as well. The problem with this field is
3258 that it makes no allowances for arguments that are passed to the
3259 function but which are not used. Hence we could miss an opportunity
3260 when a function has an unused argument in r3. But it is better to be
3261 safe than to be sorry. */
3262 if (! cfun
->machine
->uses_anonymous_args
3263 && current_function_args_size
>= 0
3264 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3265 && cfun
->args_info
.nregs
< 4)
3266 return LAST_ARG_REGNUM
;
3268 /* Otherwise look for a call-saved register that is going to be pushed. */
3269 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3270 if (pushed_regs_mask
& (1 << reg
))
3273 /* Something went wrong - thumb_compute_save_reg_mask()
3274 should have arranged for a suitable register to be pushed. */
3279 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3283 arm_load_pic_register (unsigned int scratch
)
3285 #ifndef AOF_ASSEMBLER
3286 rtx l1
, pic_tmp
, pic_tmp2
, pic_rtx
;
3287 rtx global_offset_table
;
3289 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3292 gcc_assert (flag_pic
);
3294 l1
= gen_label_rtx ();
3296 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3297 /* On the ARM the PC register contains 'dot + 8' at the time of the
3298 addition, on the Thumb it is 'dot + 4'. */
3299 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
3301 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3302 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3304 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3306 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3310 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3311 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
3315 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3317 /* We will have pushed the pic register, so should always be
3318 able to find a work register. */
3319 pic_tmp
= gen_rtx_REG (SImode
, scratch
);
3320 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3321 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3324 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3325 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
3328 /* Need to emit this whether or not we obey regdecls,
3329 since setjmp/longjmp can cause life info to screw up. */
3330 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3331 #endif /* AOF_ASSEMBLER */
3335 /* Return nonzero if X is valid as an ARM state addressing register. */
3337 arm_address_register_rtx_p (rtx x
, int strict_p
)
3341 if (GET_CODE (x
) != REG
)
3347 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3349 return (regno
<= LAST_ARM_REGNUM
3350 || regno
>= FIRST_PSEUDO_REGISTER
3351 || regno
== FRAME_POINTER_REGNUM
3352 || regno
== ARG_POINTER_REGNUM
);
3355 /* Return nonzero if X is a valid ARM state address operand. */
3357 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3361 enum rtx_code code
= GET_CODE (x
);
3363 if (arm_address_register_rtx_p (x
, strict_p
))
3366 use_ldrd
= (TARGET_LDRD
3368 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3370 if (code
== POST_INC
|| code
== PRE_DEC
3371 || ((code
== PRE_INC
|| code
== POST_DEC
)
3372 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3373 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3375 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3376 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3377 && GET_CODE (XEXP (x
, 1)) == PLUS
3378 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3380 rtx addend
= XEXP (XEXP (x
, 1), 1);
3382 /* Don't allow ldrd post increment by register because it's hard
3383 to fixup invalid register choices. */
3385 && GET_CODE (x
) == POST_MODIFY
3386 && GET_CODE (addend
) == REG
)
3389 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3390 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3393 /* After reload constants split into minipools will have addresses
3394 from a LABEL_REF. */
3395 else if (reload_completed
3396 && (code
== LABEL_REF
3398 && GET_CODE (XEXP (x
, 0)) == PLUS
3399 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3400 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3403 else if (mode
== TImode
)
3406 else if (code
== PLUS
)
3408 rtx xop0
= XEXP (x
, 0);
3409 rtx xop1
= XEXP (x
, 1);
3411 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3412 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3413 || (arm_address_register_rtx_p (xop1
, strict_p
)
3414 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3418 /* Reload currently can't handle MINUS, so disable this for now */
3419 else if (GET_CODE (x
) == MINUS
)
3421 rtx xop0
= XEXP (x
, 0);
3422 rtx xop1
= XEXP (x
, 1);
3424 return (arm_address_register_rtx_p (xop0
, strict_p
)
3425 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3429 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3430 && code
== SYMBOL_REF
3431 && CONSTANT_POOL_ADDRESS_P (x
)
3433 && symbol_mentioned_p (get_pool_constant (x
))))
3439 /* Return nonzero if INDEX is valid for an address index operand in
3442 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3445 HOST_WIDE_INT range
;
3446 enum rtx_code code
= GET_CODE (index
);
3448 /* Standard coprocessor addressing modes. */
3449 if (TARGET_HARD_FLOAT
3450 && (TARGET_FPA
|| TARGET_MAVERICK
)
3451 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3452 || (TARGET_MAVERICK
&& mode
== DImode
)))
3453 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3454 && INTVAL (index
) > -1024
3455 && (INTVAL (index
) & 3) == 0);
3457 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3458 return (code
== CONST_INT
3459 && INTVAL (index
) < 1024
3460 && INTVAL (index
) > -1024
3461 && (INTVAL (index
) & 3) == 0);
3463 if (arm_address_register_rtx_p (index
, strict_p
)
3464 && (GET_MODE_SIZE (mode
) <= 4))
3467 if (mode
== DImode
|| mode
== DFmode
)
3469 if (code
== CONST_INT
)
3471 HOST_WIDE_INT val
= INTVAL (index
);
3474 return val
> -256 && val
< 256;
3476 return val
> -4096 && val
< 4092;
3479 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3482 if (GET_MODE_SIZE (mode
) <= 4
3485 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3489 rtx xiop0
= XEXP (index
, 0);
3490 rtx xiop1
= XEXP (index
, 1);
3492 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3493 && power_of_two_operand (xiop1
, SImode
))
3494 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3495 && power_of_two_operand (xiop0
, SImode
)));
3497 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3498 || code
== ASHIFT
|| code
== ROTATERT
)
3500 rtx op
= XEXP (index
, 1);
3502 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3503 && GET_CODE (op
) == CONST_INT
3505 && INTVAL (op
) <= 31);
3509 /* For ARM v4 we may be doing a sign-extend operation during the
3513 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3519 range
= (mode
== HImode
) ? 4095 : 4096;
3521 return (code
== CONST_INT
3522 && INTVAL (index
) < range
3523 && INTVAL (index
) > -range
);
3526 /* Return nonzero if X is valid as a Thumb state base register. */
3528 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3532 if (GET_CODE (x
) != REG
)
3538 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3540 return (regno
<= LAST_LO_REGNUM
3541 || regno
> LAST_VIRTUAL_REGISTER
3542 || regno
== FRAME_POINTER_REGNUM
3543 || (GET_MODE_SIZE (mode
) >= 4
3544 && (regno
== STACK_POINTER_REGNUM
3545 || regno
>= FIRST_PSEUDO_REGISTER
3546 || x
== hard_frame_pointer_rtx
3547 || x
== arg_pointer_rtx
)));
3550 /* Return nonzero if x is a legitimate index register. This is the case
3551 for any base register that can access a QImode object. */
3553 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3555 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3558 /* Return nonzero if x is a legitimate Thumb-state address.
3560 The AP may be eliminated to either the SP or the FP, so we use the
3561 least common denominator, e.g. SImode, and offsets from 0 to 64.
3563 ??? Verify whether the above is the right approach.
3565 ??? Also, the FP may be eliminated to the SP, so perhaps that
3566 needs special handling also.
3568 ??? Look at how the mips16 port solves this problem. It probably uses
3569 better ways to solve some of these problems.
3571 Although it is not incorrect, we don't accept QImode and HImode
3572 addresses based on the frame pointer or arg pointer until the
3573 reload pass starts. This is so that eliminating such addresses
3574 into stack based ones won't produce impossible code. */
3576 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3578 /* ??? Not clear if this is right. Experiment. */
3579 if (GET_MODE_SIZE (mode
) < 4
3580 && !(reload_in_progress
|| reload_completed
)
3581 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3582 || reg_mentioned_p (arg_pointer_rtx
, x
)
3583 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3584 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3585 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3586 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3589 /* Accept any base register. SP only in SImode or larger. */
3590 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3593 /* This is PC relative data before arm_reorg runs. */
3594 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3595 && GET_CODE (x
) == SYMBOL_REF
3596 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3599 /* This is PC relative data after arm_reorg runs. */
3600 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3601 && (GET_CODE (x
) == LABEL_REF
3602 || (GET_CODE (x
) == CONST
3603 && GET_CODE (XEXP (x
, 0)) == PLUS
3604 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3605 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3608 /* Post-inc indexing only supported for SImode and larger. */
3609 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3610 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3613 else if (GET_CODE (x
) == PLUS
)
3615 /* REG+REG address can be any two index registers. */
3616 /* We disallow FRAME+REG addressing since we know that FRAME
3617 will be replaced with STACK, and SP relative addressing only
3618 permits SP+OFFSET. */
3619 if (GET_MODE_SIZE (mode
) <= 4
3620 && XEXP (x
, 0) != frame_pointer_rtx
3621 && XEXP (x
, 1) != frame_pointer_rtx
3622 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3623 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3626 /* REG+const has 5-7 bit offset for non-SP registers. */
3627 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3628 || XEXP (x
, 0) == arg_pointer_rtx
)
3629 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3630 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3633 /* REG+const has 10 bit offset for SP, but only SImode and
3634 larger is supported. */
3635 /* ??? Should probably check for DI/DFmode overflow here
3636 just like GO_IF_LEGITIMATE_OFFSET does. */
3637 else if (GET_CODE (XEXP (x
, 0)) == REG
3638 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3639 && GET_MODE_SIZE (mode
) >= 4
3640 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3641 && INTVAL (XEXP (x
, 1)) >= 0
3642 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3643 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3646 else if (GET_CODE (XEXP (x
, 0)) == REG
3647 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3648 && GET_MODE_SIZE (mode
) >= 4
3649 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3650 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3654 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3655 && GET_MODE_SIZE (mode
) == 4
3656 && GET_CODE (x
) == SYMBOL_REF
3657 && CONSTANT_POOL_ADDRESS_P (x
)
3659 && symbol_mentioned_p (get_pool_constant (x
))))
3665 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3666 instruction of mode MODE. */
3668 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3670 switch (GET_MODE_SIZE (mode
))
3673 return val
>= 0 && val
< 32;
3676 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3680 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3685 /* Try machine-dependent ways of modifying an illegitimate address
3686 to be legitimate. If we find one, return the new, valid address. */
3688 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3690 if (GET_CODE (x
) == PLUS
)
3692 rtx xop0
= XEXP (x
, 0);
3693 rtx xop1
= XEXP (x
, 1);
3695 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3696 xop0
= force_reg (SImode
, xop0
);
3698 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3699 xop1
= force_reg (SImode
, xop1
);
3701 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3702 && GET_CODE (xop1
) == CONST_INT
)
3704 HOST_WIDE_INT n
, low_n
;
3708 /* VFP addressing modes actually allow greater offsets, but for
3709 now we just stick with the lowest common denominator. */
3711 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3723 low_n
= ((mode
) == TImode
? 0
3724 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3728 base_reg
= gen_reg_rtx (SImode
);
3729 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3730 GEN_INT (n
)), NULL_RTX
);
3731 emit_move_insn (base_reg
, val
);
3732 x
= (low_n
== 0 ? base_reg
3733 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3735 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3736 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3739 /* XXX We don't allow MINUS any more -- see comment in
3740 arm_legitimate_address_p (). */
3741 else if (GET_CODE (x
) == MINUS
)
3743 rtx xop0
= XEXP (x
, 0);
3744 rtx xop1
= XEXP (x
, 1);
3746 if (CONSTANT_P (xop0
))
3747 xop0
= force_reg (SImode
, xop0
);
3749 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3750 xop1
= force_reg (SImode
, xop1
);
3752 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3753 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3758 /* We need to find and carefully transform any SYMBOL and LABEL
3759 references; so go back to the original address expression. */
3760 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3762 if (new_x
!= orig_x
)
3770 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3771 to be legitimate. If we find one, return the new, valid address. */
3773 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3775 if (GET_CODE (x
) == PLUS
3776 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3777 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
3778 || INTVAL (XEXP (x
, 1)) < 0))
3780 rtx xop0
= XEXP (x
, 0);
3781 rtx xop1
= XEXP (x
, 1);
3782 HOST_WIDE_INT offset
= INTVAL (xop1
);
3784 /* Try and fold the offset into a biasing of the base register and
3785 then offsetting that. Don't do this when optimizing for space
3786 since it can cause too many CSEs. */
3787 if (optimize_size
&& offset
>= 0
3788 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
3790 HOST_WIDE_INT delta
;
3793 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
3794 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
3795 delta
= 31 * GET_MODE_SIZE (mode
);
3797 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
3799 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
3801 x
= plus_constant (xop0
, delta
);
3803 else if (offset
< 0 && offset
> -256)
3804 /* Small negative offsets are best done with a subtract before the
3805 dereference, forcing these into a register normally takes two
3807 x
= force_operand (x
, NULL_RTX
);
3810 /* For the remaining cases, force the constant into a register. */
3811 xop1
= force_reg (SImode
, xop1
);
3812 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3815 else if (GET_CODE (x
) == PLUS
3816 && s_register_operand (XEXP (x
, 1), SImode
)
3817 && !s_register_operand (XEXP (x
, 0), SImode
))
3819 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
3821 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
3826 /* We need to find and carefully transform any SYMBOL and LABEL
3827 references; so go back to the original address expression. */
3828 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3830 if (new_x
!= orig_x
)
3839 #define REG_OR_SUBREG_REG(X) \
3840 (GET_CODE (X) == REG \
3841 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3843 #define REG_OR_SUBREG_RTX(X) \
3844 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3846 #ifndef COSTS_N_INSNS
3847 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3850 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3852 enum machine_mode mode
= GET_MODE (x
);
3865 return COSTS_N_INSNS (1);
3868 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3871 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3878 return COSTS_N_INSNS (2) + cycles
;
3880 return COSTS_N_INSNS (1) + 16;
3883 return (COSTS_N_INSNS (1)
3884 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3885 + GET_CODE (SET_DEST (x
)) == MEM
));
3890 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3892 if (thumb_shiftable_const (INTVAL (x
)))
3893 return COSTS_N_INSNS (2);
3894 return COSTS_N_INSNS (3);
3896 else if ((outer
== PLUS
|| outer
== COMPARE
)
3897 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3899 else if (outer
== AND
3900 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3901 return COSTS_N_INSNS (1);
3902 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3903 || outer
== LSHIFTRT
)
3905 return COSTS_N_INSNS (2);
3911 return COSTS_N_INSNS (3);
3929 /* XXX another guess. */
3930 /* Memory costs quite a lot for the first word, but subsequent words
3931 load at the equivalent of a single insn each. */
3932 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3933 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3938 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3943 /* XXX still guessing. */
3944 switch (GET_MODE (XEXP (x
, 0)))
3947 return (1 + (mode
== DImode
? 4 : 0)
3948 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3951 return (4 + (mode
== DImode
? 4 : 0)
3952 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3955 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3967 /* Worker routine for arm_rtx_costs. */
3969 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3971 enum machine_mode mode
= GET_MODE (x
);
3972 enum rtx_code subcode
;
3978 /* Memory costs quite a lot for the first word, but subsequent words
3979 load at the equivalent of a single insn each. */
3980 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3981 + (GET_CODE (x
) == SYMBOL_REF
3982 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3988 return optimize_size
? COSTS_N_INSNS (2) : 100;
3991 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3998 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4000 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4001 + ((GET_CODE (XEXP (x
, 0)) == REG
4002 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4003 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4005 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4006 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4007 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4009 + ((GET_CODE (XEXP (x
, 1)) == REG
4010 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4011 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4012 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4017 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4018 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4019 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4020 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4023 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4024 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4025 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4026 && arm_const_double_rtx (XEXP (x
, 1))))
4028 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4029 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4030 && arm_const_double_rtx (XEXP (x
, 0))))
4033 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4034 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4035 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4036 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4037 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4038 || subcode
== ROTATE
|| subcode
== ROTATERT
4040 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4041 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4042 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4043 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4044 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4045 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4046 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4051 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4052 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4053 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4054 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4055 && arm_const_double_rtx (XEXP (x
, 1))))
4059 case AND
: case XOR
: case IOR
:
4062 /* Normally the frame registers will be spilt into reg+const during
4063 reload, so it is a bad idea to combine them with other instructions,
4064 since then they might not be moved outside of loops. As a compromise
4065 we allow integration with ops that have a constant as their second
4067 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4068 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4069 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4070 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4071 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4075 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4076 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4077 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4078 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4081 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4082 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4083 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4084 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4085 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4088 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4089 return (1 + extra_cost
4090 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4091 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4092 || subcode
== ROTATE
|| subcode
== ROTATERT
4094 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4095 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4096 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4097 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4098 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4099 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4105 /* This should have been handled by the CPU specific routines. */
4109 if (arm_arch3m
&& mode
== SImode
4110 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4111 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4112 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4113 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4114 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4115 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4120 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4121 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4125 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4127 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4130 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4138 return 4 + (mode
== DImode
? 4 : 0);
4141 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4142 return (4 + (mode
== DImode
? 4 : 0)
4143 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4146 switch (GET_MODE (XEXP (x
, 0)))
4149 return (1 + (mode
== DImode
? 4 : 0)
4150 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4153 return (4 + (mode
== DImode
? 4 : 0)
4154 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4157 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4172 if (const_ok_for_arm (INTVAL (x
)))
4173 return outer
== SET
? 2 : -1;
4174 else if (outer
== AND
4175 && const_ok_for_arm (~INTVAL (x
)))
4177 else if ((outer
== COMPARE
4178 || outer
== PLUS
|| outer
== MINUS
)
4179 && const_ok_for_arm (-INTVAL (x
)))
4190 if (arm_const_double_rtx (x
))
4191 return outer
== SET
? 2 : -1;
4192 else if ((outer
== COMPARE
|| outer
== PLUS
)
4193 && neg_const_double_rtx_ok_for_fpa (x
))
4202 /* RTX costs when optimizing for size. */
4204 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4206 enum machine_mode mode
= GET_MODE (x
);
4210 /* XXX TBD. For now, use the standard costs. */
4211 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4218 /* A memory access costs 1 insn if the mode is small, or the address is
4219 a single register, otherwise it costs one insn per word. */
4220 if (REG_P (XEXP (x
, 0)))
4221 *total
= COSTS_N_INSNS (1);
4223 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4230 /* Needs a libcall, so it costs about this. */
4231 *total
= COSTS_N_INSNS (2);
4235 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4237 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4245 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4247 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4250 else if (mode
== SImode
)
4252 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4253 /* Slightly disparage register shifts, but not by much. */
4254 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4255 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4259 /* Needs a libcall. */
4260 *total
= COSTS_N_INSNS (2);
4264 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4266 *total
= COSTS_N_INSNS (1);
4272 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4273 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4275 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4276 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4277 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4278 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4279 || subcode1
== ASHIFTRT
)
4281 /* It's just the cost of the two operands. */
4286 *total
= COSTS_N_INSNS (1);
4290 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4294 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4296 *total
= COSTS_N_INSNS (1);
4301 case AND
: case XOR
: case IOR
:
4304 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4306 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4307 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4308 || (code
== AND
&& subcode
== NOT
))
4310 /* It's just the cost of the two operands. */
4316 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4320 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4324 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4325 *total
= COSTS_N_INSNS (1);
4328 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4337 if (cc_register (XEXP (x
, 0), VOIDmode
))
4340 *total
= COSTS_N_INSNS (1);
4344 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4345 *total
= COSTS_N_INSNS (1);
4347 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4352 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4354 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4355 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4358 *total
+= COSTS_N_INSNS (1);
4363 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4365 switch (GET_MODE (XEXP (x
, 0)))
4368 *total
+= COSTS_N_INSNS (1);
4372 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4378 *total
+= COSTS_N_INSNS (2);
4383 *total
+= COSTS_N_INSNS (1);
4388 if (const_ok_for_arm (INTVAL (x
)))
4389 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4390 else if (const_ok_for_arm (~INTVAL (x
)))
4391 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4392 else if (const_ok_for_arm (-INTVAL (x
)))
4394 if (outer_code
== COMPARE
|| outer_code
== PLUS
4395 || outer_code
== MINUS
)
4398 *total
= COSTS_N_INSNS (1);
4401 *total
= COSTS_N_INSNS (2);
4407 *total
= COSTS_N_INSNS (2);
4411 *total
= COSTS_N_INSNS (4);
4415 if (mode
!= VOIDmode
)
4416 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4418 *total
= COSTS_N_INSNS (4); /* How knows? */
4423 /* RTX costs for cores with a slow MUL implementation. */
4426 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4428 enum machine_mode mode
= GET_MODE (x
);
4432 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4439 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4446 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4448 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4449 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4450 int cost
, const_ok
= const_ok_for_arm (i
);
4451 int j
, booth_unit_size
;
4453 /* Tune as appropriate. */
4454 cost
= const_ok
? 4 : 8;
4455 booth_unit_size
= 2;
4456 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4458 i
>>= booth_unit_size
;
4466 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4467 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4471 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4477 /* RTX cost for cores with a fast multiply unit (M variants). */
4480 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4482 enum machine_mode mode
= GET_MODE (x
);
4486 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4493 /* There is no point basing this on the tuning, since it is always the
4494 fast variant if it exists at all. */
4496 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4497 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4498 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4505 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4512 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4514 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4515 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4516 int cost
, const_ok
= const_ok_for_arm (i
);
4517 int j
, booth_unit_size
;
4519 /* Tune as appropriate. */
4520 cost
= const_ok
? 4 : 8;
4521 booth_unit_size
= 8;
4522 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4524 i
>>= booth_unit_size
;
4532 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4533 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4537 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4543 /* RTX cost for XScale CPUs. */
4546 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4548 enum machine_mode mode
= GET_MODE (x
);
4552 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4559 /* There is no point basing this on the tuning, since it is always the
4560 fast variant if it exists at all. */
4562 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4563 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4564 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4571 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4578 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4580 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4581 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4582 int cost
, const_ok
= const_ok_for_arm (i
);
4583 unsigned HOST_WIDE_INT masked_const
;
4585 /* The cost will be related to two insns.
4586 First a load of the constant (MOV or LDR), then a multiply. */
4589 cost
+= 1; /* LDR is probably more expensive because
4590 of longer result latency. */
4591 masked_const
= i
& 0xffff8000;
4592 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4594 masked_const
= i
& 0xf8000000;
4595 if (masked_const
== 0 || masked_const
== 0xf8000000)
4604 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4605 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4609 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4610 will stall until the multiplication is complete. */
4611 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4612 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
4614 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4618 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4624 /* RTX costs for 9e (and later) cores. */
4627 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4629 enum machine_mode mode
= GET_MODE (x
);
4638 *total
= COSTS_N_INSNS (3);
4642 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4650 /* There is no point basing this on the tuning, since it is always the
4651 fast variant if it exists at all. */
4653 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4654 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4655 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4662 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4679 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
4680 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
4684 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4688 /* All address computations that can be done are free, but rtx cost returns
4689 the same for practically all of them. So we weight the different types
4690 of address here in the order (most pref first):
4691 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4693 arm_arm_address_cost (rtx x
)
4695 enum rtx_code c
= GET_CODE (x
);
4697 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
4699 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
4702 if (c
== PLUS
|| c
== MINUS
)
4704 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4707 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
4717 arm_thumb_address_cost (rtx x
)
4719 enum rtx_code c
= GET_CODE (x
);
4724 && GET_CODE (XEXP (x
, 0)) == REG
4725 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4732 arm_address_cost (rtx x
)
4734 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
4738 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
4742 /* Some true dependencies can have a higher cost depending
4743 on precisely how certain input operands are used. */
4745 && REG_NOTE_KIND (link
) == 0
4746 && recog_memoized (insn
) >= 0
4747 && recog_memoized (dep
) >= 0)
4749 int shift_opnum
= get_attr_shift (insn
);
4750 enum attr_type attr_type
= get_attr_type (dep
);
4752 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4753 operand for INSN. If we have a shifted input operand and the
4754 instruction we depend on is another ALU instruction, then we may
4755 have to account for an additional stall. */
4756 if (shift_opnum
!= 0
4757 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
4759 rtx shifted_operand
;
4762 /* Get the shifted operand. */
4763 extract_insn (insn
);
4764 shifted_operand
= recog_data
.operand
[shift_opnum
];
4766 /* Iterate over all the operands in DEP. If we write an operand
4767 that overlaps with SHIFTED_OPERAND, then we have increase the
4768 cost of this dependency. */
4770 preprocess_constraints ();
4771 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4773 /* We can ignore strict inputs. */
4774 if (recog_data
.operand_type
[opno
] == OP_IN
)
4777 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
4784 /* XXX This is not strictly true for the FPA. */
4785 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
4786 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4789 /* Call insns don't incur a stall, even if they follow a load. */
4790 if (REG_NOTE_KIND (link
) == 0
4791 && GET_CODE (insn
) == CALL_INSN
)
4794 if ((i_pat
= single_set (insn
)) != NULL
4795 && GET_CODE (SET_SRC (i_pat
)) == MEM
4796 && (d_pat
= single_set (dep
)) != NULL
4797 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
4799 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
4800 /* This is a load after a store, there is no conflict if the load reads
4801 from a cached area. Assume that loads from the stack, and from the
4802 constant pool are cached, and that others will miss. This is a
4805 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
4806 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
4807 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
4808 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
4815 static int fp_consts_inited
= 0;
4817 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4818 static const char * const strings_fp
[8] =
4821 "4", "5", "0.5", "10"
4824 static REAL_VALUE_TYPE values_fp
[8];
4827 init_fp_table (void)
4833 fp_consts_inited
= 1;
4835 fp_consts_inited
= 8;
4837 for (i
= 0; i
< fp_consts_inited
; i
++)
4839 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
4844 /* Return TRUE if rtx X is a valid immediate FP constant. */
4846 arm_const_double_rtx (rtx x
)
4851 if (!fp_consts_inited
)
4854 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4855 if (REAL_VALUE_MINUS_ZERO (r
))
4858 for (i
= 0; i
< fp_consts_inited
; i
++)
4859 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4865 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4867 neg_const_double_rtx_ok_for_fpa (rtx x
)
4872 if (!fp_consts_inited
)
4875 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4876 r
= REAL_VALUE_NEGATE (r
);
4877 if (REAL_VALUE_MINUS_ZERO (r
))
4880 for (i
= 0; i
< 8; i
++)
4881 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4887 /* Predicates for `match_operand' and `match_operator'. */
4889 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4891 cirrus_memory_offset (rtx op
)
4893 /* Reject eliminable registers. */
4894 if (! (reload_in_progress
|| reload_completed
)
4895 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4896 || reg_mentioned_p (arg_pointer_rtx
, op
)
4897 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4898 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4899 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4900 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4903 if (GET_CODE (op
) == MEM
)
4909 /* Match: (mem (reg)). */
4910 if (GET_CODE (ind
) == REG
)
4916 if (GET_CODE (ind
) == PLUS
4917 && GET_CODE (XEXP (ind
, 0)) == REG
4918 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4919 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4926 /* Return TRUE if OP is a valid VFP memory address pattern.
4927 WB if true if writeback address modes are allowed. */
4930 arm_coproc_mem_operand (rtx op
, bool wb
)
4934 /* Reject eliminable registers. */
4935 if (! (reload_in_progress
|| reload_completed
)
4936 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4937 || reg_mentioned_p (arg_pointer_rtx
, op
)
4938 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4939 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4940 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4941 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4944 /* Constants are converted into offsets from labels. */
4945 if (GET_CODE (op
) != MEM
)
4950 if (reload_completed
4951 && (GET_CODE (ind
) == LABEL_REF
4952 || (GET_CODE (ind
) == CONST
4953 && GET_CODE (XEXP (ind
, 0)) == PLUS
4954 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
4955 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
4958 /* Match: (mem (reg)). */
4959 if (GET_CODE (ind
) == REG
)
4960 return arm_address_register_rtx_p (ind
, 0);
4962 /* Autoincremment addressing modes. */
4964 && (GET_CODE (ind
) == PRE_INC
4965 || GET_CODE (ind
) == POST_INC
4966 || GET_CODE (ind
) == PRE_DEC
4967 || GET_CODE (ind
) == POST_DEC
))
4968 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
4971 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
4972 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
4973 && GET_CODE (XEXP (ind
, 1)) == PLUS
4974 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
4975 ind
= XEXP (ind
, 1);
4980 if (GET_CODE (ind
) == PLUS
4981 && GET_CODE (XEXP (ind
, 0)) == REG
4982 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4983 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
4984 && INTVAL (XEXP (ind
, 1)) > -1024
4985 && INTVAL (XEXP (ind
, 1)) < 1024
4986 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
4992 /* Return true if X is a register that will be eliminated later on. */
4994 arm_eliminable_register (rtx x
)
4996 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
4997 || REGNO (x
) == ARG_POINTER_REGNUM
4998 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
4999 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5002 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5003 VFP registers. Otherwise return NO_REGS. */
5006 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5008 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5011 return GENERAL_REGS
;
5014 /* Values which must be returned in the most-significant end of the return
5018 arm_return_in_msb (tree valtype
)
5020 return (TARGET_AAPCS_BASED
5022 && (AGGREGATE_TYPE_P (valtype
)
5023 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5026 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5027 Use by the Cirrus Maverick code which has to workaround
5028 a hardware bug triggered by such instructions. */
5030 arm_memory_load_p (rtx insn
)
5032 rtx body
, lhs
, rhs
;;
5034 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5037 body
= PATTERN (insn
);
5039 if (GET_CODE (body
) != SET
)
5042 lhs
= XEXP (body
, 0);
5043 rhs
= XEXP (body
, 1);
5045 lhs
= REG_OR_SUBREG_RTX (lhs
);
5047 /* If the destination is not a general purpose
5048 register we do not have to worry. */
5049 if (GET_CODE (lhs
) != REG
5050 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5053 /* As well as loads from memory we also have to react
5054 to loads of invalid constants which will be turned
5055 into loads from the minipool. */
5056 return (GET_CODE (rhs
) == MEM
5057 || GET_CODE (rhs
) == SYMBOL_REF
5058 || note_invalid_constants (insn
, -1, false));
5061 /* Return TRUE if INSN is a Cirrus instruction. */
5063 arm_cirrus_insn_p (rtx insn
)
5065 enum attr_cirrus attr
;
5067 /* get_attr cannot accept USE or CLOBBER. */
5069 || GET_CODE (insn
) != INSN
5070 || GET_CODE (PATTERN (insn
)) == USE
5071 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5074 attr
= get_attr_cirrus (insn
);
5076 return attr
!= CIRRUS_NOT
;
5079 /* Cirrus reorg for invalid instruction combinations. */
5081 cirrus_reorg (rtx first
)
5083 enum attr_cirrus attr
;
5084 rtx body
= PATTERN (first
);
5088 /* Any branch must be followed by 2 non Cirrus instructions. */
5089 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5092 t
= next_nonnote_insn (first
);
5094 if (arm_cirrus_insn_p (t
))
5097 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5101 emit_insn_after (gen_nop (), first
);
5106 /* (float (blah)) is in parallel with a clobber. */
5107 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5108 body
= XVECEXP (body
, 0, 0);
5110 if (GET_CODE (body
) == SET
)
5112 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5114 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5115 be followed by a non Cirrus insn. */
5116 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5118 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5119 emit_insn_after (gen_nop (), first
);
5123 else if (arm_memory_load_p (first
))
5125 unsigned int arm_regno
;
5127 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5128 ldr/cfmv64hr combination where the Rd field is the same
5129 in both instructions must be split with a non Cirrus
5136 /* Get Arm register number for ldr insn. */
5137 if (GET_CODE (lhs
) == REG
)
5138 arm_regno
= REGNO (lhs
);
5141 gcc_assert (GET_CODE (rhs
) == REG
);
5142 arm_regno
= REGNO (rhs
);
5146 first
= next_nonnote_insn (first
);
5148 if (! arm_cirrus_insn_p (first
))
5151 body
= PATTERN (first
);
5153 /* (float (blah)) is in parallel with a clobber. */
5154 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5155 body
= XVECEXP (body
, 0, 0);
5157 if (GET_CODE (body
) == FLOAT
)
5158 body
= XEXP (body
, 0);
5160 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5161 && GET_CODE (XEXP (body
, 1)) == REG
5162 && arm_regno
== REGNO (XEXP (body
, 1)))
5163 emit_insn_after (gen_nop (), first
);
5169 /* get_attr cannot accept USE or CLOBBER. */
5171 || GET_CODE (first
) != INSN
5172 || GET_CODE (PATTERN (first
)) == USE
5173 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5176 attr
= get_attr_cirrus (first
);
5178 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5179 must be followed by a non-coprocessor instruction. */
5180 if (attr
== CIRRUS_COMPARE
)
5184 t
= next_nonnote_insn (first
);
5186 if (arm_cirrus_insn_p (t
))
5189 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5193 emit_insn_after (gen_nop (), first
);
5199 /* Return TRUE if X references a SYMBOL_REF. */
5201 symbol_mentioned_p (rtx x
)
5206 if (GET_CODE (x
) == SYMBOL_REF
)
5209 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5211 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5217 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5218 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5221 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5228 /* Return TRUE if X references a LABEL_REF. */
5230 label_mentioned_p (rtx x
)
5235 if (GET_CODE (x
) == LABEL_REF
)
5238 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5239 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5245 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5246 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5249 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5259 enum rtx_code code
= GET_CODE (x
);
5276 /* Return 1 if memory locations are adjacent. */
5278 adjacent_mem_locations (rtx a
, rtx b
)
5280 /* We don't guarantee to preserve the order of these memory refs. */
5281 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5284 if ((GET_CODE (XEXP (a
, 0)) == REG
5285 || (GET_CODE (XEXP (a
, 0)) == PLUS
5286 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5287 && (GET_CODE (XEXP (b
, 0)) == REG
5288 || (GET_CODE (XEXP (b
, 0)) == PLUS
5289 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5291 HOST_WIDE_INT val0
= 0, val1
= 0;
5295 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5297 reg0
= XEXP (XEXP (a
, 0), 0);
5298 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5303 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5305 reg1
= XEXP (XEXP (b
, 0), 0);
5306 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5311 /* Don't accept any offset that will require multiple
5312 instructions to handle, since this would cause the
5313 arith_adjacentmem pattern to output an overlong sequence. */
5314 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5317 /* Don't allow an eliminable register: register elimination can make
5318 the offset too large. */
5319 if (arm_eliminable_register (reg0
))
5322 val_diff
= val1
- val0
;
5326 /* If the target has load delay slots, then there's no benefit
5327 to using an ldm instruction unless the offset is zero and
5328 we are optimizing for size. */
5329 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5330 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5331 && (val_diff
== 4 || val_diff
== -4));
5334 return ((REGNO (reg0
) == REGNO (reg1
))
5335 && (val_diff
== 4 || val_diff
== -4));
5342 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5343 HOST_WIDE_INT
*load_offset
)
5345 int unsorted_regs
[4];
5346 HOST_WIDE_INT unsorted_offsets
[4];
5351 /* Can only handle 2, 3, or 4 insns at present,
5352 though could be easily extended if required. */
5353 gcc_assert (nops
>= 2 && nops
<= 4);
5355 /* Loop over the operands and check that the memory references are
5356 suitable (i.e. immediate offsets from the same base register). At
5357 the same time, extract the target register, and the memory
5359 for (i
= 0; i
< nops
; i
++)
5364 /* Convert a subreg of a mem into the mem itself. */
5365 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5366 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5368 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5370 /* Don't reorder volatile memory references; it doesn't seem worth
5371 looking for the case where the order is ok anyway. */
5372 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5375 offset
= const0_rtx
;
5377 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5378 || (GET_CODE (reg
) == SUBREG
5379 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5380 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5381 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5383 || (GET_CODE (reg
) == SUBREG
5384 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5385 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5390 base_reg
= REGNO (reg
);
5391 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5392 ? REGNO (operands
[i
])
5393 : REGNO (SUBREG_REG (operands
[i
])));
5398 if (base_reg
!= (int) REGNO (reg
))
5399 /* Not addressed from the same base register. */
5402 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5403 ? REGNO (operands
[i
])
5404 : REGNO (SUBREG_REG (operands
[i
])));
5405 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5409 /* If it isn't an integer register, or if it overwrites the
5410 base register but isn't the last insn in the list, then
5411 we can't do this. */
5412 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5413 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5416 unsorted_offsets
[i
] = INTVAL (offset
);
5419 /* Not a suitable memory address. */
5423 /* All the useful information has now been extracted from the
5424 operands into unsorted_regs and unsorted_offsets; additionally,
5425 order[0] has been set to the lowest numbered register in the
5426 list. Sort the registers into order, and check that the memory
5427 offsets are ascending and adjacent. */
5429 for (i
= 1; i
< nops
; i
++)
5433 order
[i
] = order
[i
- 1];
5434 for (j
= 0; j
< nops
; j
++)
5435 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5436 && (order
[i
] == order
[i
- 1]
5437 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5440 /* Have we found a suitable register? if not, one must be used more
5442 if (order
[i
] == order
[i
- 1])
5445 /* Is the memory address adjacent and ascending? */
5446 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5454 for (i
= 0; i
< nops
; i
++)
5455 regs
[i
] = unsorted_regs
[order
[i
]];
5457 *load_offset
= unsorted_offsets
[order
[0]];
5460 if (unsorted_offsets
[order
[0]] == 0)
5461 return 1; /* ldmia */
5463 if (unsorted_offsets
[order
[0]] == 4)
5464 return 2; /* ldmib */
5466 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5467 return 3; /* ldmda */
5469 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5470 return 4; /* ldmdb */
5472 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5473 if the offset isn't small enough. The reason 2 ldrs are faster
5474 is because these ARMs are able to do more than one cache access
5475 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5476 whilst the ARM8 has a double bandwidth cache. This means that
5477 these cores can do both an instruction fetch and a data fetch in
5478 a single cycle, so the trick of calculating the address into a
5479 scratch register (one of the result regs) and then doing a load
5480 multiple actually becomes slower (and no smaller in code size).
5481 That is the transformation
5483 ldr rd1, [rbase + offset]
5484 ldr rd2, [rbase + offset + 4]
5488 add rd1, rbase, offset
5489 ldmia rd1, {rd1, rd2}
5491 produces worse code -- '3 cycles + any stalls on rd2' instead of
5492 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5493 access per cycle, the first sequence could never complete in less
5494 than 6 cycles, whereas the ldm sequence would only take 5 and
5495 would make better use of sequential accesses if not hitting the
5498 We cheat here and test 'arm_ld_sched' which we currently know to
5499 only be true for the ARM8, ARM9 and StrongARM. If this ever
5500 changes, then the test below needs to be reworked. */
5501 if (nops
== 2 && arm_ld_sched
)
5504 /* Can't do it without setting up the offset, only do this if it takes
5505 no more than one insn. */
5506 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5507 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5511 emit_ldm_seq (rtx
*operands
, int nops
)
5515 HOST_WIDE_INT offset
;
5519 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5522 strcpy (buf
, "ldm%?ia\t");
5526 strcpy (buf
, "ldm%?ib\t");
5530 strcpy (buf
, "ldm%?da\t");
5534 strcpy (buf
, "ldm%?db\t");
5539 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5540 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5543 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5544 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5546 output_asm_insn (buf
, operands
);
5548 strcpy (buf
, "ldm%?ia\t");
5555 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5556 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5558 for (i
= 1; i
< nops
; i
++)
5559 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5560 reg_names
[regs
[i
]]);
5562 strcat (buf
, "}\t%@ phole ldm");
5564 output_asm_insn (buf
, operands
);
5569 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5570 HOST_WIDE_INT
* load_offset
)
5572 int unsorted_regs
[4];
5573 HOST_WIDE_INT unsorted_offsets
[4];
5578 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5579 extended if required. */
5580 gcc_assert (nops
>= 2 && nops
<= 4);
5582 /* Loop over the operands and check that the memory references are
5583 suitable (i.e. immediate offsets from the same base register). At
5584 the same time, extract the target register, and the memory
5586 for (i
= 0; i
< nops
; i
++)
5591 /* Convert a subreg of a mem into the mem itself. */
5592 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5593 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5595 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5597 /* Don't reorder volatile memory references; it doesn't seem worth
5598 looking for the case where the order is ok anyway. */
5599 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5602 offset
= const0_rtx
;
5604 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5605 || (GET_CODE (reg
) == SUBREG
5606 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5607 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5608 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5610 || (GET_CODE (reg
) == SUBREG
5611 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5612 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5617 base_reg
= REGNO (reg
);
5618 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5619 ? REGNO (operands
[i
])
5620 : REGNO (SUBREG_REG (operands
[i
])));
5625 if (base_reg
!= (int) REGNO (reg
))
5626 /* Not addressed from the same base register. */
5629 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5630 ? REGNO (operands
[i
])
5631 : REGNO (SUBREG_REG (operands
[i
])));
5632 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5636 /* If it isn't an integer register, then we can't do this. */
5637 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5640 unsorted_offsets
[i
] = INTVAL (offset
);
5643 /* Not a suitable memory address. */
5647 /* All the useful information has now been extracted from the
5648 operands into unsorted_regs and unsorted_offsets; additionally,
5649 order[0] has been set to the lowest numbered register in the
5650 list. Sort the registers into order, and check that the memory
5651 offsets are ascending and adjacent. */
5653 for (i
= 1; i
< nops
; i
++)
5657 order
[i
] = order
[i
- 1];
5658 for (j
= 0; j
< nops
; j
++)
5659 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5660 && (order
[i
] == order
[i
- 1]
5661 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5664 /* Have we found a suitable register? if not, one must be used more
5666 if (order
[i
] == order
[i
- 1])
5669 /* Is the memory address adjacent and ascending? */
5670 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5678 for (i
= 0; i
< nops
; i
++)
5679 regs
[i
] = unsorted_regs
[order
[i
]];
5681 *load_offset
= unsorted_offsets
[order
[0]];
5684 if (unsorted_offsets
[order
[0]] == 0)
5685 return 1; /* stmia */
5687 if (unsorted_offsets
[order
[0]] == 4)
5688 return 2; /* stmib */
5690 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5691 return 3; /* stmda */
5693 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5694 return 4; /* stmdb */
5700 emit_stm_seq (rtx
*operands
, int nops
)
5704 HOST_WIDE_INT offset
;
5708 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5711 strcpy (buf
, "stm%?ia\t");
5715 strcpy (buf
, "stm%?ib\t");
5719 strcpy (buf
, "stm%?da\t");
5723 strcpy (buf
, "stm%?db\t");
5730 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5731 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5733 for (i
= 1; i
< nops
; i
++)
5734 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5735 reg_names
[regs
[i
]]);
5737 strcat (buf
, "}\t%@ phole stm");
5739 output_asm_insn (buf
, operands
);
5744 /* Routines for use in generating RTL. */
5747 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5748 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
5750 HOST_WIDE_INT offset
= *offsetp
;
5753 int sign
= up
? 1 : -1;
5756 /* XScale has load-store double instructions, but they have stricter
5757 alignment requirements than load-store multiple, so we cannot
5760 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5761 the pipeline until completion.
5769 An ldr instruction takes 1-3 cycles, but does not block the
5778 Best case ldr will always win. However, the more ldr instructions
5779 we issue, the less likely we are to be able to schedule them well.
5780 Using ldr instructions also increases code size.
5782 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5783 for counts of 3 or 4 regs. */
5784 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5790 for (i
= 0; i
< count
; i
++)
5792 addr
= plus_constant (from
, i
* 4 * sign
);
5793 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
5794 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5800 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5810 result
= gen_rtx_PARALLEL (VOIDmode
,
5811 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5814 XVECEXP (result
, 0, 0)
5815 = gen_rtx_SET (GET_MODE (from
), from
,
5816 plus_constant (from
, count
* 4 * sign
));
5821 for (j
= 0; i
< count
; i
++, j
++)
5823 addr
= plus_constant (from
, j
* 4 * sign
);
5824 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
5825 XVECEXP (result
, 0, i
)
5826 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5837 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5838 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
5840 HOST_WIDE_INT offset
= *offsetp
;
5843 int sign
= up
? 1 : -1;
5846 /* See arm_gen_load_multiple for discussion of
5847 the pros/cons of ldm/stm usage for XScale. */
5848 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5854 for (i
= 0; i
< count
; i
++)
5856 addr
= plus_constant (to
, i
* 4 * sign
);
5857 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
5858 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5864 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5874 result
= gen_rtx_PARALLEL (VOIDmode
,
5875 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5878 XVECEXP (result
, 0, 0)
5879 = gen_rtx_SET (GET_MODE (to
), to
,
5880 plus_constant (to
, count
* 4 * sign
));
5885 for (j
= 0; i
< count
; i
++, j
++)
5887 addr
= plus_constant (to
, j
* 4 * sign
);
5888 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
5889 XVECEXP (result
, 0, i
)
5890 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5901 arm_gen_movmemqi (rtx
*operands
)
5903 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5904 HOST_WIDE_INT srcoffset
, dstoffset
;
5906 rtx src
, dst
, srcbase
, dstbase
;
5907 rtx part_bytes_reg
= NULL
;
5910 if (GET_CODE (operands
[2]) != CONST_INT
5911 || GET_CODE (operands
[3]) != CONST_INT
5912 || INTVAL (operands
[2]) > 64
5913 || INTVAL (operands
[3]) & 3)
5916 dstbase
= operands
[0];
5917 srcbase
= operands
[1];
5919 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
5920 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
5922 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5923 out_words_to_go
= INTVAL (operands
[2]) / 4;
5924 last_bytes
= INTVAL (operands
[2]) & 3;
5925 dstoffset
= srcoffset
= 0;
5927 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5928 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5930 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5932 if (in_words_to_go
> 4)
5933 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5934 srcbase
, &srcoffset
));
5936 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5937 FALSE
, srcbase
, &srcoffset
));
5939 if (out_words_to_go
)
5941 if (out_words_to_go
> 4)
5942 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5943 dstbase
, &dstoffset
));
5944 else if (out_words_to_go
!= 1)
5945 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
5949 dstbase
, &dstoffset
));
5952 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
5953 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
5954 if (last_bytes
!= 0)
5956 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
5962 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
5963 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
5966 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5967 if (out_words_to_go
)
5971 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
5972 sreg
= copy_to_reg (mem
);
5974 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
5975 emit_move_insn (mem
, sreg
);
5978 gcc_assert (!in_words_to_go
); /* Sanity check */
5983 gcc_assert (in_words_to_go
> 0);
5985 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
5986 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
5989 gcc_assert (!last_bytes
|| part_bytes_reg
);
5991 if (BYTES_BIG_ENDIAN
&& last_bytes
)
5993 rtx tmp
= gen_reg_rtx (SImode
);
5995 /* The bytes we want are in the top end of the word. */
5996 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
5997 GEN_INT (8 * (4 - last_bytes
))));
5998 part_bytes_reg
= tmp
;
6002 mem
= adjust_automodify_address (dstbase
, QImode
,
6003 plus_constant (dst
, last_bytes
- 1),
6004 dstoffset
+ last_bytes
- 1);
6005 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6009 tmp
= gen_reg_rtx (SImode
);
6010 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6011 part_bytes_reg
= tmp
;
6020 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6021 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6025 rtx tmp
= gen_reg_rtx (SImode
);
6026 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6027 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6028 part_bytes_reg
= tmp
;
6035 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6036 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6043 /* Generate a memory reference for a half word, such that it will be loaded
6044 into the top 16 bits of the word. We can assume that the address is
6045 known to be alignable and of the form reg, or plus (reg, const). */
6048 arm_gen_rotated_half_load (rtx memref
)
6050 HOST_WIDE_INT offset
= 0;
6051 rtx base
= XEXP (memref
, 0);
6053 if (GET_CODE (base
) == PLUS
)
6055 offset
= INTVAL (XEXP (base
, 1));
6056 base
= XEXP (base
, 0);
6059 /* If we aren't allowed to generate unaligned addresses, then fail. */
6060 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0))
6063 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
6065 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
6068 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
6071 /* Select a dominance comparison mode if possible for a test of the general
6072 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6073 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6074 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6075 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6076 In all cases OP will be either EQ or NE, but we don't need to know which
6077 here. If we are unable to support a dominance comparison we return
6078 CC mode. This will then fail to match for the RTL expressions that
6079 generate this call. */
6081 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6083 enum rtx_code cond1
, cond2
;
6086 /* Currently we will probably get the wrong result if the individual
6087 comparisons are not simple. This also ensures that it is safe to
6088 reverse a comparison if necessary. */
6089 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6091 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6095 /* The if_then_else variant of this tests the second condition if the
6096 first passes, but is true if the first fails. Reverse the first
6097 condition to get a true "inclusive-or" expression. */
6098 if (cond_or
== DOM_CC_NX_OR_Y
)
6099 cond1
= reverse_condition (cond1
);
6101 /* If the comparisons are not equal, and one doesn't dominate the other,
6102 then we can't do this. */
6104 && !comparison_dominates_p (cond1
, cond2
)
6105 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6110 enum rtx_code temp
= cond1
;
6118 if (cond_or
== DOM_CC_X_AND_Y
)
6123 case EQ
: return CC_DEQmode
;
6124 case LE
: return CC_DLEmode
;
6125 case LEU
: return CC_DLEUmode
;
6126 case GE
: return CC_DGEmode
;
6127 case GEU
: return CC_DGEUmode
;
6128 default: gcc_unreachable ();
6132 if (cond_or
== DOM_CC_X_AND_Y
)
6148 if (cond_or
== DOM_CC_X_AND_Y
)
6164 if (cond_or
== DOM_CC_X_AND_Y
)
6180 if (cond_or
== DOM_CC_X_AND_Y
)
6195 /* The remaining cases only occur when both comparisons are the
6198 gcc_assert (cond1
== cond2
);
6202 gcc_assert (cond1
== cond2
);
6206 gcc_assert (cond1
== cond2
);
6210 gcc_assert (cond1
== cond2
);
6214 gcc_assert (cond1
== cond2
);
6223 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6225 /* All floating point compares return CCFP if it is an equality
6226 comparison, and CCFPE otherwise. */
6227 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6247 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6256 /* A compare with a shifted operand. Because of canonicalization, the
6257 comparison will have to be swapped when we emit the assembler. */
6258 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6259 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6260 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6261 || GET_CODE (x
) == ROTATERT
))
6264 /* This operation is performed swapped, but since we only rely on the Z
6265 flag we don't need an additional mode. */
6266 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6267 && GET_CODE (x
) == NEG
6268 && (op
== EQ
|| op
== NE
))
6271 /* This is a special case that is used by combine to allow a
6272 comparison of a shifted byte load to be split into a zero-extend
6273 followed by a comparison of the shifted integer (only valid for
6274 equalities and unsigned inequalities). */
6275 if (GET_MODE (x
) == SImode
6276 && GET_CODE (x
) == ASHIFT
6277 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6278 && GET_CODE (XEXP (x
, 0)) == SUBREG
6279 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6280 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6281 && (op
== EQ
|| op
== NE
6282 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6283 && GET_CODE (y
) == CONST_INT
)
6286 /* A construct for a conditional compare, if the false arm contains
6287 0, then both conditions must be true, otherwise either condition
6288 must be true. Not all conditions are possible, so CCmode is
6289 returned if it can't be done. */
6290 if (GET_CODE (x
) == IF_THEN_ELSE
6291 && (XEXP (x
, 2) == const0_rtx
6292 || XEXP (x
, 2) == const1_rtx
)
6293 && COMPARISON_P (XEXP (x
, 0))
6294 && COMPARISON_P (XEXP (x
, 1)))
6295 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6296 INTVAL (XEXP (x
, 2)));
6298 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6299 if (GET_CODE (x
) == AND
6300 && COMPARISON_P (XEXP (x
, 0))
6301 && COMPARISON_P (XEXP (x
, 1)))
6302 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6305 if (GET_CODE (x
) == IOR
6306 && COMPARISON_P (XEXP (x
, 0))
6307 && COMPARISON_P (XEXP (x
, 1)))
6308 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6311 /* An operation (on Thumb) where we want to test for a single bit.
6312 This is done by shifting that bit up into the top bit of a
6313 scratch register; we can then branch on the sign bit. */
6315 && GET_MODE (x
) == SImode
6316 && (op
== EQ
|| op
== NE
)
6317 && (GET_CODE (x
) == ZERO_EXTRACT
))
6320 /* An operation that sets the condition codes as a side-effect, the
6321 V flag is not set correctly, so we can only use comparisons where
6322 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6324 if (GET_MODE (x
) == SImode
6326 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6327 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6328 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6329 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6330 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6331 || GET_CODE (x
) == LSHIFTRT
6332 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6333 || GET_CODE (x
) == ROTATERT
6334 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6337 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6340 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6341 && GET_CODE (x
) == PLUS
6342 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6348 /* X and Y are two things to compare using CODE. Emit the compare insn and
6349 return the rtx for register 0 in the proper mode. FP means this is a
6350 floating point compare: I don't think that it is needed on the arm. */
6352 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6354 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6355 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6357 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6358 gen_rtx_COMPARE (mode
, x
, y
)));
6363 /* Generate a sequence of insns that will generate the correct return
6364 address mask depending on the physical architecture that the program
6367 arm_gen_return_addr_mask (void)
6369 rtx reg
= gen_reg_rtx (Pmode
);
6371 emit_insn (gen_return_addr_mask (reg
));
6376 arm_reload_in_hi (rtx
*operands
)
6378 rtx ref
= operands
[1];
6380 HOST_WIDE_INT offset
= 0;
6382 if (GET_CODE (ref
) == SUBREG
)
6384 offset
= SUBREG_BYTE (ref
);
6385 ref
= SUBREG_REG (ref
);
6388 if (GET_CODE (ref
) == REG
)
6390 /* We have a pseudo which has been spilt onto the stack; there
6391 are two cases here: the first where there is a simple
6392 stack-slot replacement and a second where the stack-slot is
6393 out of range, or is used as a subreg. */
6394 if (reg_equiv_mem
[REGNO (ref
)])
6396 ref
= reg_equiv_mem
[REGNO (ref
)];
6397 base
= find_replacement (&XEXP (ref
, 0));
6400 /* The slot is out of range, or was dressed up in a SUBREG. */
6401 base
= reg_equiv_address
[REGNO (ref
)];
6404 base
= find_replacement (&XEXP (ref
, 0));
6406 /* Handle the case where the address is too complex to be offset by 1. */
6407 if (GET_CODE (base
) == MINUS
6408 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6410 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6412 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6415 else if (GET_CODE (base
) == PLUS
)
6417 /* The addend must be CONST_INT, or we would have dealt with it above. */
6418 HOST_WIDE_INT hi
, lo
;
6420 offset
+= INTVAL (XEXP (base
, 1));
6421 base
= XEXP (base
, 0);
6423 /* Rework the address into a legal sequence of insns. */
6424 /* Valid range for lo is -4095 -> 4095 */
6427 : -((-offset
) & 0xfff));
6429 /* Corner case, if lo is the max offset then we would be out of range
6430 once we have added the additional 1 below, so bump the msb into the
6431 pre-loading insn(s). */
6435 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6436 ^ (HOST_WIDE_INT
) 0x80000000)
6437 - (HOST_WIDE_INT
) 0x80000000);
6439 gcc_assert (hi
+ lo
== offset
);
6443 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6445 /* Get the base address; addsi3 knows how to handle constants
6446 that require more than one insn. */
6447 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6453 /* Operands[2] may overlap operands[0] (though it won't overlap
6454 operands[1]), that's why we asked for a DImode reg -- so we can
6455 use the bit that does not overlap. */
6456 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6457 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6459 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6461 emit_insn (gen_zero_extendqisi2 (scratch
,
6462 gen_rtx_MEM (QImode
,
6463 plus_constant (base
,
6465 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6466 gen_rtx_MEM (QImode
,
6467 plus_constant (base
,
6469 if (!BYTES_BIG_ENDIAN
)
6470 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6471 gen_rtx_IOR (SImode
,
6474 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6478 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6479 gen_rtx_IOR (SImode
,
6480 gen_rtx_ASHIFT (SImode
, scratch
,
6482 gen_rtx_SUBREG (SImode
, operands
[0],
6486 /* Handle storing a half-word to memory during reload by synthesizing as two
6487 byte stores. Take care not to clobber the input values until after we
6488 have moved them somewhere safe. This code assumes that if the DImode
6489 scratch in operands[2] overlaps either the input value or output address
6490 in some way, then that value must die in this insn (we absolutely need
6491 two scratch registers for some corner cases). */
6493 arm_reload_out_hi (rtx
*operands
)
6495 rtx ref
= operands
[0];
6496 rtx outval
= operands
[1];
6498 HOST_WIDE_INT offset
= 0;
6500 if (GET_CODE (ref
) == SUBREG
)
6502 offset
= SUBREG_BYTE (ref
);
6503 ref
= SUBREG_REG (ref
);
6506 if (GET_CODE (ref
) == REG
)
6508 /* We have a pseudo which has been spilt onto the stack; there
6509 are two cases here: the first where there is a simple
6510 stack-slot replacement and a second where the stack-slot is
6511 out of range, or is used as a subreg. */
6512 if (reg_equiv_mem
[REGNO (ref
)])
6514 ref
= reg_equiv_mem
[REGNO (ref
)];
6515 base
= find_replacement (&XEXP (ref
, 0));
6518 /* The slot is out of range, or was dressed up in a SUBREG. */
6519 base
= reg_equiv_address
[REGNO (ref
)];
6522 base
= find_replacement (&XEXP (ref
, 0));
6524 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6526 /* Handle the case where the address is too complex to be offset by 1. */
6527 if (GET_CODE (base
) == MINUS
6528 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6530 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6532 /* Be careful not to destroy OUTVAL. */
6533 if (reg_overlap_mentioned_p (base_plus
, outval
))
6535 /* Updating base_plus might destroy outval, see if we can
6536 swap the scratch and base_plus. */
6537 if (!reg_overlap_mentioned_p (scratch
, outval
))
6540 scratch
= base_plus
;
6545 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6547 /* Be conservative and copy OUTVAL into the scratch now,
6548 this should only be necessary if outval is a subreg
6549 of something larger than a word. */
6550 /* XXX Might this clobber base? I can't see how it can,
6551 since scratch is known to overlap with OUTVAL, and
6552 must be wider than a word. */
6553 emit_insn (gen_movhi (scratch_hi
, outval
));
6554 outval
= scratch_hi
;
6558 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6561 else if (GET_CODE (base
) == PLUS
)
6563 /* The addend must be CONST_INT, or we would have dealt with it above. */
6564 HOST_WIDE_INT hi
, lo
;
6566 offset
+= INTVAL (XEXP (base
, 1));
6567 base
= XEXP (base
, 0);
6569 /* Rework the address into a legal sequence of insns. */
6570 /* Valid range for lo is -4095 -> 4095 */
6573 : -((-offset
) & 0xfff));
6575 /* Corner case, if lo is the max offset then we would be out of range
6576 once we have added the additional 1 below, so bump the msb into the
6577 pre-loading insn(s). */
6581 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6582 ^ (HOST_WIDE_INT
) 0x80000000)
6583 - (HOST_WIDE_INT
) 0x80000000);
6585 gcc_assert (hi
+ lo
== offset
);
6589 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6591 /* Be careful not to destroy OUTVAL. */
6592 if (reg_overlap_mentioned_p (base_plus
, outval
))
6594 /* Updating base_plus might destroy outval, see if we
6595 can swap the scratch and base_plus. */
6596 if (!reg_overlap_mentioned_p (scratch
, outval
))
6599 scratch
= base_plus
;
6604 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6606 /* Be conservative and copy outval into scratch now,
6607 this should only be necessary if outval is a
6608 subreg of something larger than a word. */
6609 /* XXX Might this clobber base? I can't see how it
6610 can, since scratch is known to overlap with
6612 emit_insn (gen_movhi (scratch_hi
, outval
));
6613 outval
= scratch_hi
;
6617 /* Get the base address; addsi3 knows how to handle constants
6618 that require more than one insn. */
6619 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6625 if (BYTES_BIG_ENDIAN
)
6627 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6628 plus_constant (base
, offset
+ 1)),
6629 gen_lowpart (QImode
, outval
)));
6630 emit_insn (gen_lshrsi3 (scratch
,
6631 gen_rtx_SUBREG (SImode
, outval
, 0),
6633 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6634 gen_lowpart (QImode
, scratch
)));
6638 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6639 gen_lowpart (QImode
, outval
)));
6640 emit_insn (gen_lshrsi3 (scratch
,
6641 gen_rtx_SUBREG (SImode
, outval
, 0),
6643 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6644 plus_constant (base
, offset
+ 1)),
6645 gen_lowpart (QImode
, scratch
)));
6649 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
6650 (padded to the size of a word) should be passed in a register. */
6653 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
6655 if (TARGET_AAPCS_BASED
)
6656 return must_pass_in_stack_var_size (mode
, type
);
6658 return must_pass_in_stack_var_size_or_pad (mode
, type
);
6662 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
6663 Return true if an argument passed on the stack should be padded upwards,
6664 i.e. if the least-significant byte has useful data.
6665 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
6666 aggregate types are placed in the lowest memory address. */
6669 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
6671 if (!TARGET_AAPCS_BASED
)
6672 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
6674 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
6681 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
6682 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
6683 byte of the register has useful data, and return the opposite if the
6684 most significant byte does.
6685 For AAPCS, small aggregates and small complex types are always padded
6689 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
6690 tree type
, int first ATTRIBUTE_UNUSED
)
6692 if (TARGET_AAPCS_BASED
6694 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
6695 && int_size_in_bytes (type
) <= 4)
6698 /* Otherwise, use default padding. */
6699 return !BYTES_BIG_ENDIAN
;
6704 /* Print a symbolic form of X to the debug file, F. */
6706 arm_print_value (FILE *f
, rtx x
)
6708 switch (GET_CODE (x
))
6711 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6715 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6723 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6725 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6726 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6734 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6738 fprintf (f
, "`%s'", XSTR (x
, 0));
6742 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6746 arm_print_value (f
, XEXP (x
, 0));
6750 arm_print_value (f
, XEXP (x
, 0));
6752 arm_print_value (f
, XEXP (x
, 1));
6760 fprintf (f
, "????");
6765 /* Routines for manipulation of the constant pool. */
6767 /* Arm instructions cannot load a large constant directly into a
6768 register; they have to come from a pc relative load. The constant
6769 must therefore be placed in the addressable range of the pc
6770 relative load. Depending on the precise pc relative load
6771 instruction the range is somewhere between 256 bytes and 4k. This
6772 means that we often have to dump a constant inside a function, and
6773 generate code to branch around it.
6775 It is important to minimize this, since the branches will slow
6776 things down and make the code larger.
6778 Normally we can hide the table after an existing unconditional
6779 branch so that there is no interruption of the flow, but in the
6780 worst case the code looks like this:
6798 We fix this by performing a scan after scheduling, which notices
6799 which instructions need to have their operands fetched from the
6800 constant table and builds the table.
6802 The algorithm starts by building a table of all the constants that
6803 need fixing up and all the natural barriers in the function (places
6804 where a constant table can be dropped without breaking the flow).
6805 For each fixup we note how far the pc-relative replacement will be
6806 able to reach and the offset of the instruction into the function.
6808 Having built the table we then group the fixes together to form
6809 tables that are as large as possible (subject to addressing
6810 constraints) and emit each table of constants after the last
6811 barrier that is within range of all the instructions in the group.
6812 If a group does not contain a barrier, then we forcibly create one
6813 by inserting a jump instruction into the flow. Once the table has
6814 been inserted, the insns are then modified to reference the
6815 relevant entry in the pool.
6817 Possible enhancements to the algorithm (not implemented) are:
6819 1) For some processors and object formats, there may be benefit in
6820 aligning the pools to the start of cache lines; this alignment
6821 would need to be taken into account when calculating addressability
6824 /* These typedefs are located at the start of this file, so that
6825 they can be used in the prototypes there. This comment is to
6826 remind readers of that fact so that the following structures
6827 can be understood more easily.
6829 typedef struct minipool_node Mnode;
6830 typedef struct minipool_fixup Mfix; */
6832 struct minipool_node
6834 /* Doubly linked chain of entries. */
6837 /* The maximum offset into the code that this entry can be placed. While
6838 pushing fixes for forward references, all entries are sorted in order
6839 of increasing max_address. */
6840 HOST_WIDE_INT max_address
;
6841 /* Similarly for an entry inserted for a backwards ref. */
6842 HOST_WIDE_INT min_address
;
6843 /* The number of fixes referencing this entry. This can become zero
6844 if we "unpush" an entry. In this case we ignore the entry when we
6845 come to emit the code. */
6847 /* The offset from the start of the minipool. */
6848 HOST_WIDE_INT offset
;
6849 /* The value in table. */
6851 /* The mode of value. */
6852 enum machine_mode mode
;
6853 /* The size of the value. With iWMMXt enabled
6854 sizes > 4 also imply an alignment of 8-bytes. */
6858 struct minipool_fixup
6862 HOST_WIDE_INT address
;
6864 enum machine_mode mode
;
6868 HOST_WIDE_INT forwards
;
6869 HOST_WIDE_INT backwards
;
6872 /* Fixes less than a word need padding out to a word boundary. */
6873 #define MINIPOOL_FIX_SIZE(mode) \
6874 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6876 static Mnode
* minipool_vector_head
;
6877 static Mnode
* minipool_vector_tail
;
6878 static rtx minipool_vector_label
;
6880 /* The linked list of all minipool fixes required for this function. */
6881 Mfix
* minipool_fix_head
;
6882 Mfix
* minipool_fix_tail
;
6883 /* The fix entry for the current minipool, once it has been placed. */
6884 Mfix
* minipool_barrier
;
6886 /* Determines if INSN is the start of a jump table. Returns the end
6887 of the TABLE or NULL_RTX. */
6889 is_jump_table (rtx insn
)
6893 if (GET_CODE (insn
) == JUMP_INSN
6894 && JUMP_LABEL (insn
) != NULL
6895 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6896 == next_real_insn (insn
))
6898 && GET_CODE (table
) == JUMP_INSN
6899 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6900 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6906 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6907 #define JUMP_TABLES_IN_TEXT_SECTION 0
6910 static HOST_WIDE_INT
6911 get_jump_table_size (rtx insn
)
6913 /* ADDR_VECs only take room if read-only data does into the text
6915 if (JUMP_TABLES_IN_TEXT_SECTION
6916 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6921 rtx body
= PATTERN (insn
);
6922 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6924 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6930 /* Move a minipool fix MP from its current location to before MAX_MP.
6931 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6932 constraints may need updating. */
6934 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6935 HOST_WIDE_INT max_address
)
6937 /* The code below assumes these are different. */
6938 gcc_assert (mp
!= max_mp
);
6942 if (max_address
< mp
->max_address
)
6943 mp
->max_address
= max_address
;
6947 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6948 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6950 mp
->max_address
= max_address
;
6952 /* Unlink MP from its current position. Since max_mp is non-null,
6953 mp->prev must be non-null. */
6954 mp
->prev
->next
= mp
->next
;
6955 if (mp
->next
!= NULL
)
6956 mp
->next
->prev
= mp
->prev
;
6958 minipool_vector_tail
= mp
->prev
;
6960 /* Re-insert it before MAX_MP. */
6962 mp
->prev
= max_mp
->prev
;
6965 if (mp
->prev
!= NULL
)
6966 mp
->prev
->next
= mp
;
6968 minipool_vector_head
= mp
;
6971 /* Save the new entry. */
6974 /* Scan over the preceding entries and adjust their addresses as
6976 while (mp
->prev
!= NULL
6977 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6979 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6986 /* Add a constant to the minipool for a forward reference. Returns the
6987 node added or NULL if the constant will not fit in this pool. */
6989 add_minipool_forward_ref (Mfix
*fix
)
6991 /* If set, max_mp is the first pool_entry that has a lower
6992 constraint than the one we are trying to add. */
6993 Mnode
* max_mp
= NULL
;
6994 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6997 /* If this fix's address is greater than the address of the first
6998 entry, then we can't put the fix in this pool. We subtract the
6999 size of the current fix to ensure that if the table is fully
7000 packed we still have enough room to insert this value by shuffling
7001 the other fixes forwards. */
7002 if (minipool_vector_head
&&
7003 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7006 /* Scan the pool to see if a constant with the same value has
7007 already been added. While we are doing this, also note the
7008 location where we must insert the constant if it doesn't already
7010 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7012 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7013 && fix
->mode
== mp
->mode
7014 && (GET_CODE (fix
->value
) != CODE_LABEL
7015 || (CODE_LABEL_NUMBER (fix
->value
)
7016 == CODE_LABEL_NUMBER (mp
->value
)))
7017 && rtx_equal_p (fix
->value
, mp
->value
))
7019 /* More than one fix references this entry. */
7021 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7024 /* Note the insertion point if necessary. */
7026 && mp
->max_address
> max_address
)
7029 /* If we are inserting an 8-bytes aligned quantity and
7030 we have not already found an insertion point, then
7031 make sure that all such 8-byte aligned quantities are
7032 placed at the start of the pool. */
7033 if (ARM_DOUBLEWORD_ALIGN
7035 && fix
->fix_size
== 8
7036 && mp
->fix_size
!= 8)
7039 max_address
= mp
->max_address
;
7043 /* The value is not currently in the minipool, so we need to create
7044 a new entry for it. If MAX_MP is NULL, the entry will be put on
7045 the end of the list since the placement is less constrained than
7046 any existing entry. Otherwise, we insert the new fix before
7047 MAX_MP and, if necessary, adjust the constraints on the other
7049 mp
= xmalloc (sizeof (* mp
));
7050 mp
->fix_size
= fix
->fix_size
;
7051 mp
->mode
= fix
->mode
;
7052 mp
->value
= fix
->value
;
7054 /* Not yet required for a backwards ref. */
7055 mp
->min_address
= -65536;
7059 mp
->max_address
= max_address
;
7061 mp
->prev
= minipool_vector_tail
;
7063 if (mp
->prev
== NULL
)
7065 minipool_vector_head
= mp
;
7066 minipool_vector_label
= gen_label_rtx ();
7069 mp
->prev
->next
= mp
;
7071 minipool_vector_tail
= mp
;
7075 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7076 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7078 mp
->max_address
= max_address
;
7081 mp
->prev
= max_mp
->prev
;
7083 if (mp
->prev
!= NULL
)
7084 mp
->prev
->next
= mp
;
7086 minipool_vector_head
= mp
;
7089 /* Save the new entry. */
7092 /* Scan over the preceding entries and adjust their addresses as
7094 while (mp
->prev
!= NULL
7095 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7097 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7105 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7106 HOST_WIDE_INT min_address
)
7108 HOST_WIDE_INT offset
;
7110 /* The code below assumes these are different. */
7111 gcc_assert (mp
!= min_mp
);
7115 if (min_address
> mp
->min_address
)
7116 mp
->min_address
= min_address
;
7120 /* We will adjust this below if it is too loose. */
7121 mp
->min_address
= min_address
;
7123 /* Unlink MP from its current position. Since min_mp is non-null,
7124 mp->next must be non-null. */
7125 mp
->next
->prev
= mp
->prev
;
7126 if (mp
->prev
!= NULL
)
7127 mp
->prev
->next
= mp
->next
;
7129 minipool_vector_head
= mp
->next
;
7131 /* Reinsert it after MIN_MP. */
7133 mp
->next
= min_mp
->next
;
7135 if (mp
->next
!= NULL
)
7136 mp
->next
->prev
= mp
;
7138 minipool_vector_tail
= mp
;
7144 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7146 mp
->offset
= offset
;
7147 if (mp
->refcount
> 0)
7148 offset
+= mp
->fix_size
;
7150 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7151 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7157 /* Add a constant to the minipool for a backward reference. Returns the
7158 node added or NULL if the constant will not fit in this pool.
7160 Note that the code for insertion for a backwards reference can be
7161 somewhat confusing because the calculated offsets for each fix do
7162 not take into account the size of the pool (which is still under
7165 add_minipool_backward_ref (Mfix
*fix
)
7167 /* If set, min_mp is the last pool_entry that has a lower constraint
7168 than the one we are trying to add. */
7169 Mnode
*min_mp
= NULL
;
7170 /* This can be negative, since it is only a constraint. */
7171 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7174 /* If we can't reach the current pool from this insn, or if we can't
7175 insert this entry at the end of the pool without pushing other
7176 fixes out of range, then we don't try. This ensures that we
7177 can't fail later on. */
7178 if (min_address
>= minipool_barrier
->address
7179 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7180 >= minipool_barrier
->address
))
7183 /* Scan the pool to see if a constant with the same value has
7184 already been added. While we are doing this, also note the
7185 location where we must insert the constant if it doesn't already
7187 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7189 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7190 && fix
->mode
== mp
->mode
7191 && (GET_CODE (fix
->value
) != CODE_LABEL
7192 || (CODE_LABEL_NUMBER (fix
->value
)
7193 == CODE_LABEL_NUMBER (mp
->value
)))
7194 && rtx_equal_p (fix
->value
, mp
->value
)
7195 /* Check that there is enough slack to move this entry to the
7196 end of the table (this is conservative). */
7198 > (minipool_barrier
->address
7199 + minipool_vector_tail
->offset
7200 + minipool_vector_tail
->fix_size
)))
7203 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7207 mp
->min_address
+= fix
->fix_size
;
7210 /* Note the insertion point if necessary. */
7211 if (mp
->min_address
< min_address
)
7213 /* For now, we do not allow the insertion of 8-byte alignment
7214 requiring nodes anywhere but at the start of the pool. */
7215 if (ARM_DOUBLEWORD_ALIGN
7216 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7221 else if (mp
->max_address
7222 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7224 /* Inserting before this entry would push the fix beyond
7225 its maximum address (which can happen if we have
7226 re-located a forwards fix); force the new fix to come
7229 min_address
= mp
->min_address
+ fix
->fix_size
;
7231 /* If we are inserting an 8-bytes aligned quantity and
7232 we have not already found an insertion point, then
7233 make sure that all such 8-byte aligned quantities are
7234 placed at the start of the pool. */
7235 else if (ARM_DOUBLEWORD_ALIGN
7237 && fix
->fix_size
== 8
7238 && mp
->fix_size
< 8)
7241 min_address
= mp
->min_address
+ fix
->fix_size
;
7246 /* We need to create a new entry. */
7247 mp
= xmalloc (sizeof (* mp
));
7248 mp
->fix_size
= fix
->fix_size
;
7249 mp
->mode
= fix
->mode
;
7250 mp
->value
= fix
->value
;
7252 mp
->max_address
= minipool_barrier
->address
+ 65536;
7254 mp
->min_address
= min_address
;
7259 mp
->next
= minipool_vector_head
;
7261 if (mp
->next
== NULL
)
7263 minipool_vector_tail
= mp
;
7264 minipool_vector_label
= gen_label_rtx ();
7267 mp
->next
->prev
= mp
;
7269 minipool_vector_head
= mp
;
7273 mp
->next
= min_mp
->next
;
7277 if (mp
->next
!= NULL
)
7278 mp
->next
->prev
= mp
;
7280 minipool_vector_tail
= mp
;
7283 /* Save the new entry. */
7291 /* Scan over the following entries and adjust their offsets. */
7292 while (mp
->next
!= NULL
)
7294 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7295 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7298 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7300 mp
->next
->offset
= mp
->offset
;
7309 assign_minipool_offsets (Mfix
*barrier
)
7311 HOST_WIDE_INT offset
= 0;
7314 minipool_barrier
= barrier
;
7316 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7318 mp
->offset
= offset
;
7320 if (mp
->refcount
> 0)
7321 offset
+= mp
->fix_size
;
7325 /* Output the literal table */
7327 dump_minipool (rtx scan
)
7333 if (ARM_DOUBLEWORD_ALIGN
)
7334 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7335 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7343 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7344 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7346 scan
= emit_label_after (gen_label_rtx (), scan
);
7347 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7348 scan
= emit_label_after (minipool_vector_label
, scan
);
7350 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7352 if (mp
->refcount
> 0)
7357 ";; Offset %u, min %ld, max %ld ",
7358 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7359 (unsigned long) mp
->max_address
);
7360 arm_print_value (dump_file
, mp
->value
);
7361 fputc ('\n', dump_file
);
7364 switch (mp
->fix_size
)
7366 #ifdef HAVE_consttable_1
7368 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7372 #ifdef HAVE_consttable_2
7374 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7378 #ifdef HAVE_consttable_4
7380 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7384 #ifdef HAVE_consttable_8
7386 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7399 minipool_vector_head
= minipool_vector_tail
= NULL
;
7400 scan
= emit_insn_after (gen_consttable_end (), scan
);
7401 scan
= emit_barrier_after (scan
);
7404 /* Return the cost of forcibly inserting a barrier after INSN. */
7406 arm_barrier_cost (rtx insn
)
7408 /* Basing the location of the pool on the loop depth is preferable,
7409 but at the moment, the basic block information seems to be
7410 corrupt by this stage of the compilation. */
7412 rtx next
= next_nonnote_insn (insn
);
7414 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7417 switch (GET_CODE (insn
))
7420 /* It will always be better to place the table before the label, rather
7429 return base_cost
- 10;
7432 return base_cost
+ 10;
7436 /* Find the best place in the insn stream in the range
7437 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7438 Create the barrier by inserting a jump and add a new fix entry for
7441 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7443 HOST_WIDE_INT count
= 0;
7445 rtx from
= fix
->insn
;
7446 rtx selected
= from
;
7448 HOST_WIDE_INT selected_address
;
7450 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7451 rtx label
= gen_label_rtx ();
7453 selected_cost
= arm_barrier_cost (from
);
7454 selected_address
= fix
->address
;
7456 while (from
&& count
< max_count
)
7461 /* This code shouldn't have been called if there was a natural barrier
7463 gcc_assert (GET_CODE (from
) != BARRIER
);
7465 /* Count the length of this insn. */
7466 count
+= get_attr_length (from
);
7468 /* If there is a jump table, add its length. */
7469 tmp
= is_jump_table (from
);
7472 count
+= get_jump_table_size (tmp
);
7474 /* Jump tables aren't in a basic block, so base the cost on
7475 the dispatch insn. If we select this location, we will
7476 still put the pool after the table. */
7477 new_cost
= arm_barrier_cost (from
);
7479 if (count
< max_count
&& new_cost
<= selected_cost
)
7482 selected_cost
= new_cost
;
7483 selected_address
= fix
->address
+ count
;
7486 /* Continue after the dispatch table. */
7487 from
= NEXT_INSN (tmp
);
7491 new_cost
= arm_barrier_cost (from
);
7493 if (count
< max_count
&& new_cost
<= selected_cost
)
7496 selected_cost
= new_cost
;
7497 selected_address
= fix
->address
+ count
;
7500 from
= NEXT_INSN (from
);
7503 /* Create a new JUMP_INSN that branches around a barrier. */
7504 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7505 JUMP_LABEL (from
) = label
;
7506 barrier
= emit_barrier_after (from
);
7507 emit_label_after (label
, barrier
);
7509 /* Create a minipool barrier entry for the new barrier. */
7510 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7511 new_fix
->insn
= barrier
;
7512 new_fix
->address
= selected_address
;
7513 new_fix
->next
= fix
->next
;
7514 fix
->next
= new_fix
;
7519 /* Record that there is a natural barrier in the insn stream at
7522 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7524 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7527 fix
->address
= address
;
7530 if (minipool_fix_head
!= NULL
)
7531 minipool_fix_tail
->next
= fix
;
7533 minipool_fix_head
= fix
;
7535 minipool_fix_tail
= fix
;
7538 /* Record INSN, which will need fixing up to load a value from the
7539 minipool. ADDRESS is the offset of the insn since the start of the
7540 function; LOC is a pointer to the part of the insn which requires
7541 fixing; VALUE is the constant that must be loaded, which is of type
7544 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7545 enum machine_mode mode
, rtx value
)
7547 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7549 #ifdef AOF_ASSEMBLER
7550 /* PIC symbol references need to be converted into offsets into the
7552 /* XXX This shouldn't be done here. */
7553 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7554 value
= aof_pic_entry (value
);
7555 #endif /* AOF_ASSEMBLER */
7558 fix
->address
= address
;
7561 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7563 fix
->forwards
= get_attr_pool_range (insn
);
7564 fix
->backwards
= get_attr_neg_pool_range (insn
);
7565 fix
->minipool
= NULL
;
7567 /* If an insn doesn't have a range defined for it, then it isn't
7568 expecting to be reworked by this code. Better to stop now than
7569 to generate duff assembly code. */
7570 gcc_assert (fix
->forwards
|| fix
->backwards
);
7572 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7573 So there might be an empty word before the start of the pool.
7574 Hence we reduce the forward range by 4 to allow for this
7576 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7582 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7583 GET_MODE_NAME (mode
),
7584 INSN_UID (insn
), (unsigned long) address
,
7585 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7586 arm_print_value (dump_file
, fix
->value
);
7587 fprintf (dump_file
, "\n");
7590 /* Add it to the chain of fixes. */
7593 if (minipool_fix_head
!= NULL
)
7594 minipool_fix_tail
->next
= fix
;
7596 minipool_fix_head
= fix
;
7598 minipool_fix_tail
= fix
;
7601 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7602 Returns the number of insns needed, or 99 if we don't know how to
7605 arm_const_double_inline_cost (rtx val
)
7607 rtx lowpart
, highpart
;
7608 enum machine_mode mode
;
7610 mode
= GET_MODE (val
);
7612 if (mode
== VOIDmode
)
7615 gcc_assert (GET_MODE_SIZE (mode
) == 8);
7617 lowpart
= gen_lowpart (SImode
, val
);
7618 highpart
= gen_highpart_mode (SImode
, mode
, val
);
7620 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
7621 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
7623 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
7624 NULL_RTX
, NULL_RTX
, 0, 0)
7625 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
7626 NULL_RTX
, NULL_RTX
, 0, 0));
7629 /* Return true if it is worthwhile to split a 64-bit constant into two
7630 32-bit operations. This is the case if optimizing for size, or
7631 if we have load delay slots, or if one 32-bit part can be done with
7632 a single data operation. */
7634 arm_const_double_by_parts (rtx val
)
7636 enum machine_mode mode
= GET_MODE (val
);
7639 if (optimize_size
|| arm_ld_sched
)
7642 if (mode
== VOIDmode
)
7645 part
= gen_highpart_mode (SImode
, mode
, val
);
7647 gcc_assert (GET_CODE (part
) == CONST_INT
);
7649 if (const_ok_for_arm (INTVAL (part
))
7650 || const_ok_for_arm (~INTVAL (part
)))
7653 part
= gen_lowpart (SImode
, val
);
7655 gcc_assert (GET_CODE (part
) == CONST_INT
);
7657 if (const_ok_for_arm (INTVAL (part
))
7658 || const_ok_for_arm (~INTVAL (part
)))
7664 /* Scan INSN and note any of its operands that need fixing.
7665 If DO_PUSHES is false we do not actually push any of the fixups
7666 needed. The function returns TRUE if any fixups were needed/pushed.
7667 This is used by arm_memory_load_p() which needs to know about loads
7668 of constants that will be converted into minipool loads. */
7670 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
7672 bool result
= false;
7675 extract_insn (insn
);
7677 if (!constrain_operands (1))
7678 fatal_insn_not_found (insn
);
7680 if (recog_data
.n_alternatives
== 0)
7683 /* Fill in recog_op_alt with information about the constraints of
7685 preprocess_constraints ();
7687 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7689 /* Things we need to fix can only occur in inputs. */
7690 if (recog_data
.operand_type
[opno
] != OP_IN
)
7693 /* If this alternative is a memory reference, then any mention
7694 of constants in this alternative is really to fool reload
7695 into allowing us to accept one there. We need to fix them up
7696 now so that we output the right code. */
7697 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
7699 rtx op
= recog_data
.operand
[opno
];
7701 if (CONSTANT_P (op
))
7704 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
7705 recog_data
.operand_mode
[opno
], op
);
7708 else if (GET_CODE (op
) == MEM
7709 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
7710 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
7714 rtx cop
= avoid_constant_pool_reference (op
);
7716 /* Casting the address of something to a mode narrower
7717 than a word can cause avoid_constant_pool_reference()
7718 to return the pool reference itself. That's no good to
7719 us here. Lets just hope that we can use the
7720 constant pool value directly. */
7722 cop
= get_pool_constant (XEXP (op
, 0));
7724 push_minipool_fix (insn
, address
,
7725 recog_data
.operand_loc
[opno
],
7726 recog_data
.operand_mode
[opno
], cop
);
7737 /* Gcc puts the pool in the wrong place for ARM, since we can only
7738 load addresses a limited distance around the pc. We do some
7739 special munging to move the constant pool values to the correct
7740 point in the code. */
7745 HOST_WIDE_INT address
= 0;
7748 minipool_fix_head
= minipool_fix_tail
= NULL
;
7750 /* The first insn must always be a note, or the code below won't
7751 scan it properly. */
7752 insn
= get_insns ();
7753 gcc_assert (GET_CODE (insn
) == NOTE
);
7755 /* Scan all the insns and record the operands that will need fixing. */
7756 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7758 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7759 && (arm_cirrus_insn_p (insn
)
7760 || GET_CODE (insn
) == JUMP_INSN
7761 || arm_memory_load_p (insn
)))
7762 cirrus_reorg (insn
);
7764 if (GET_CODE (insn
) == BARRIER
)
7765 push_minipool_barrier (insn
, address
);
7766 else if (INSN_P (insn
))
7770 note_invalid_constants (insn
, address
, true);
7771 address
+= get_attr_length (insn
);
7773 /* If the insn is a vector jump, add the size of the table
7774 and skip the table. */
7775 if ((table
= is_jump_table (insn
)) != NULL
)
7777 address
+= get_jump_table_size (table
);
7783 fix
= minipool_fix_head
;
7785 /* Now scan the fixups and perform the required changes. */
7790 Mfix
* last_added_fix
;
7791 Mfix
* last_barrier
= NULL
;
7794 /* Skip any further barriers before the next fix. */
7795 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7798 /* No more fixes. */
7802 last_added_fix
= NULL
;
7804 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7806 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7808 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7811 last_barrier
= ftmp
;
7813 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7816 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7819 /* If we found a barrier, drop back to that; any fixes that we
7820 could have reached but come after the barrier will now go in
7821 the next mini-pool. */
7822 if (last_barrier
!= NULL
)
7824 /* Reduce the refcount for those fixes that won't go into this
7826 for (fdel
= last_barrier
->next
;
7827 fdel
&& fdel
!= ftmp
;
7830 fdel
->minipool
->refcount
--;
7831 fdel
->minipool
= NULL
;
7834 ftmp
= last_barrier
;
7838 /* ftmp is first fix that we can't fit into this pool and
7839 there no natural barriers that we could use. Insert a
7840 new barrier in the code somewhere between the previous
7841 fix and this one, and arrange to jump around it. */
7842 HOST_WIDE_INT max_address
;
7844 /* The last item on the list of fixes must be a barrier, so
7845 we can never run off the end of the list of fixes without
7846 last_barrier being set. */
7849 max_address
= minipool_vector_head
->max_address
;
7850 /* Check that there isn't another fix that is in range that
7851 we couldn't fit into this pool because the pool was
7852 already too large: we need to put the pool before such an
7854 if (ftmp
->address
< max_address
)
7855 max_address
= ftmp
->address
;
7857 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7860 assign_minipool_offsets (last_barrier
);
7864 if (GET_CODE (ftmp
->insn
) != BARRIER
7865 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7872 /* Scan over the fixes we have identified for this pool, fixing them
7873 up and adding the constants to the pool itself. */
7874 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7875 this_fix
= this_fix
->next
)
7876 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7879 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7880 minipool_vector_label
),
7881 this_fix
->minipool
->offset
);
7882 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7885 dump_minipool (last_barrier
->insn
);
7889 /* From now on we must synthesize any constants that we can't handle
7890 directly. This can happen if the RTL gets split during final
7891 instruction generation. */
7892 after_arm_reorg
= 1;
7894 /* Free the minipool memory. */
7895 obstack_free (&minipool_obstack
, minipool_startobj
);
7898 /* Routines to output assembly language. */
7900 /* If the rtx is the correct value then return the string of the number.
7901 In this way we can ensure that valid double constants are generated even
7902 when cross compiling. */
7904 fp_immediate_constant (rtx x
)
7909 if (!fp_consts_inited
)
7912 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7913 for (i
= 0; i
< 8; i
++)
7914 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7915 return strings_fp
[i
];
7920 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7922 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7926 if (!fp_consts_inited
)
7929 for (i
= 0; i
< 8; i
++)
7930 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
7931 return strings_fp
[i
];
7936 /* Output the operands of a LDM/STM instruction to STREAM.
7937 MASK is the ARM register set mask of which only bits 0-15 are important.
7938 REG is the base register, either the frame pointer or the stack pointer,
7939 INSTR is the possibly suffixed load or store instruction. */
7942 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
7946 bool not_first
= FALSE
;
7948 fputc ('\t', stream
);
7949 asm_fprintf (stream
, instr
, reg
);
7950 fputs (", {", stream
);
7952 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7953 if (mask
& (1 << i
))
7956 fprintf (stream
, ", ");
7958 asm_fprintf (stream
, "%r", i
);
7962 fprintf (stream
, "}\n");
7966 /* Output a FLDMX instruction to STREAM.
7967 BASE if the register containing the address.
7968 REG and COUNT specify the register range.
7969 Extra registers may be added to avoid hardware bugs. */
7972 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
7976 /* Workaround ARM10 VFPr1 bug. */
7977 if (count
== 2 && !arm_arch6
)
7984 fputc ('\t', stream
);
7985 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
7987 for (i
= reg
; i
< reg
+ count
; i
++)
7990 fputs (", ", stream
);
7991 asm_fprintf (stream
, "d%d", i
);
7993 fputs ("}\n", stream
);
7998 /* Output the assembly for a store multiple. */
8001 vfp_output_fstmx (rtx
* operands
)
8008 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8009 p
= strlen (pattern
);
8011 gcc_assert (GET_CODE (operands
[1]) == REG
);
8013 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8014 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8016 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8018 strcpy (&pattern
[p
], "}");
8020 output_asm_insn (pattern
, operands
);
8025 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8026 number of bytes pushed. */
8029 vfp_emit_fstmx (int base_reg
, int count
)
8036 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8037 register pairs are stored by a store multiple insn. We avoid this
8038 by pushing an extra pair. */
8039 if (count
== 2 && !arm_arch6
)
8041 if (base_reg
== LAST_VFP_REGNUM
- 3)
8046 /* ??? The frame layout is implementation defined. We describe
8047 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8048 We really need some way of representing the whole block so that the
8049 unwinder can figure it out at runtime. */
8050 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8051 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8053 reg
= gen_rtx_REG (DFmode
, base_reg
);
8057 = gen_rtx_SET (VOIDmode
,
8058 gen_rtx_MEM (BLKmode
,
8059 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8060 gen_rtx_UNSPEC (BLKmode
,
8064 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8065 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8066 GEN_INT (-(count
* 8 + 4))));
8067 RTX_FRAME_RELATED_P (tmp
) = 1;
8068 XVECEXP (dwarf
, 0, 0) = tmp
;
8070 tmp
= gen_rtx_SET (VOIDmode
,
8071 gen_rtx_MEM (DFmode
, stack_pointer_rtx
),
8073 RTX_FRAME_RELATED_P (tmp
) = 1;
8074 XVECEXP (dwarf
, 0, 1) = tmp
;
8076 for (i
= 1; i
< count
; i
++)
8078 reg
= gen_rtx_REG (DFmode
, base_reg
);
8080 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8082 tmp
= gen_rtx_SET (VOIDmode
,
8083 gen_rtx_MEM (DFmode
,
8084 gen_rtx_PLUS (SImode
,
8088 RTX_FRAME_RELATED_P (tmp
) = 1;
8089 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8092 par
= emit_insn (par
);
8093 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8095 RTX_FRAME_RELATED_P (par
) = 1;
8097 return count
* 8 + 4;
8101 /* Output a 'call' insn. */
8103 output_call (rtx
*operands
)
8105 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8107 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8108 if (REGNO (operands
[0]) == LR_REGNUM
)
8110 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8111 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8114 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8116 if (TARGET_INTERWORK
|| arm_arch4t
)
8117 output_asm_insn ("bx%?\t%0", operands
);
8119 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8124 /* Output a 'call' insn that is a reference in memory. */
8126 output_call_mem (rtx
*operands
)
8128 if (TARGET_INTERWORK
&& !arm_arch5
)
8130 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8131 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8132 output_asm_insn ("bx%?\t%|ip", operands
);
8134 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8136 /* LR is used in the memory address. We load the address in the
8137 first instruction. It's safe to use IP as the target of the
8138 load since the call will kill it anyway. */
8139 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8141 output_asm_insn ("blx%?\t%|ip", operands
);
8144 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8146 output_asm_insn ("bx%?\t%|ip", operands
);
8148 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8153 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8154 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8161 /* Output a move from arm registers to an fpa registers.
8162 OPERANDS[0] is an fpa register.
8163 OPERANDS[1] is the first registers of an arm register pair. */
8165 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8167 int arm_reg0
= REGNO (operands
[1]);
8170 gcc_assert (arm_reg0
!= IP_REGNUM
);
8172 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8173 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8174 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8176 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8177 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8182 /* Output a move from an fpa register to arm registers.
8183 OPERANDS[0] is the first registers of an arm register pair.
8184 OPERANDS[1] is an fpa register. */
8186 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8188 int arm_reg0
= REGNO (operands
[0]);
8191 gcc_assert (arm_reg0
!= IP_REGNUM
);
8193 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8194 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8195 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8197 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8198 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8202 /* Output a move from arm registers to arm registers of a long double
8203 OPERANDS[0] is the destination.
8204 OPERANDS[1] is the source. */
8206 output_mov_long_double_arm_from_arm (rtx
*operands
)
8208 /* We have to be careful here because the two might overlap. */
8209 int dest_start
= REGNO (operands
[0]);
8210 int src_start
= REGNO (operands
[1]);
8214 if (dest_start
< src_start
)
8216 for (i
= 0; i
< 3; i
++)
8218 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8219 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8220 output_asm_insn ("mov%?\t%0, %1", ops
);
8225 for (i
= 2; i
>= 0; i
--)
8227 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8228 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8229 output_asm_insn ("mov%?\t%0, %1", ops
);
8237 /* Output a move from arm registers to an fpa registers.
8238 OPERANDS[0] is an fpa register.
8239 OPERANDS[1] is the first registers of an arm register pair. */
8241 output_mov_double_fpa_from_arm (rtx
*operands
)
8243 int arm_reg0
= REGNO (operands
[1]);
8246 gcc_assert (arm_reg0
!= IP_REGNUM
);
8248 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8249 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8250 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8251 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8255 /* Output a move from an fpa register to arm registers.
8256 OPERANDS[0] is the first registers of an arm register pair.
8257 OPERANDS[1] is an fpa register. */
8259 output_mov_double_arm_from_fpa (rtx
*operands
)
8261 int arm_reg0
= REGNO (operands
[0]);
8264 gcc_assert (arm_reg0
!= IP_REGNUM
);
8266 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8267 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8268 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8269 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8273 /* Output a move between double words.
8274 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8275 or MEM<-REG and all MEMs must be offsettable addresses. */
8277 output_move_double (rtx
*operands
)
8279 enum rtx_code code0
= GET_CODE (operands
[0]);
8280 enum rtx_code code1
= GET_CODE (operands
[1]);
8285 int reg0
= REGNO (operands
[0]);
8287 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8289 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8291 switch (GET_CODE (XEXP (operands
[1], 0)))
8294 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8298 gcc_assert (TARGET_LDRD
);
8299 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8303 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8307 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8311 gcc_assert (TARGET_LDRD
);
8312 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8317 otherops
[0] = operands
[0];
8318 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8319 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8321 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8323 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8325 /* Registers overlap so split out the increment. */
8326 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8327 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8330 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8334 /* We only allow constant increments, so this is safe. */
8335 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8341 output_asm_insn ("adr%?\t%0, %1", operands
);
8342 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8346 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8347 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8349 otherops
[0] = operands
[0];
8350 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8351 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8353 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8355 if (GET_CODE (otherops
[2]) == CONST_INT
)
8357 switch ((int) INTVAL (otherops
[2]))
8360 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8363 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8366 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8371 && (GET_CODE (otherops
[2]) == REG
8372 || (GET_CODE (otherops
[2]) == CONST_INT
8373 && INTVAL (otherops
[2]) > -256
8374 && INTVAL (otherops
[2]) < 256)))
8376 if (reg_overlap_mentioned_p (otherops
[0],
8379 /* Swap base and index registers over to
8380 avoid a conflict. */
8381 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8382 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8385 /* If both registers conflict, it will usually
8386 have been fixed by a splitter. */
8387 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8389 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8390 output_asm_insn ("ldr%?d\t%0, [%1]",
8394 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8398 if (GET_CODE (otherops
[2]) == CONST_INT
)
8400 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8401 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8403 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8406 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8409 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8411 return "ldm%?ia\t%0, %M0";
8415 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8416 /* Take care of overlapping base/data reg. */
8417 if (reg_mentioned_p (operands
[0], operands
[1]))
8419 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8420 output_asm_insn ("ldr%?\t%0, %1", operands
);
8424 output_asm_insn ("ldr%?\t%0, %1", operands
);
8425 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8432 /* Constraints should ensure this. */
8433 gcc_assert (code0
== MEM
&& code1
== REG
);
8434 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8436 switch (GET_CODE (XEXP (operands
[0], 0)))
8439 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8443 gcc_assert (TARGET_LDRD
);
8444 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8448 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8452 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8456 gcc_assert (TARGET_LDRD
);
8457 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8462 otherops
[0] = operands
[1];
8463 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8464 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8466 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8467 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8469 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8473 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8474 if (GET_CODE (otherops
[2]) == CONST_INT
)
8476 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8479 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8483 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8487 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8492 && (GET_CODE (otherops
[2]) == REG
8493 || (GET_CODE (otherops
[2]) == CONST_INT
8494 && INTVAL (otherops
[2]) > -256
8495 && INTVAL (otherops
[2]) < 256)))
8497 otherops
[0] = operands
[1];
8498 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8499 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8505 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8506 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8507 output_asm_insn ("str%?\t%1, %0", operands
);
8508 output_asm_insn ("str%?\t%1, %0", otherops
);
8515 /* Output an ADD r, s, #n where n may be too big for one instruction.
8516 If adding zero to one register, output nothing. */
8518 output_add_immediate (rtx
*operands
)
8520 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8522 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8525 output_multi_immediate (operands
,
8526 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8529 output_multi_immediate (operands
,
8530 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8537 /* Output a multiple immediate operation.
8538 OPERANDS is the vector of operands referred to in the output patterns.
8539 INSTR1 is the output pattern to use for the first constant.
8540 INSTR2 is the output pattern to use for subsequent constants.
8541 IMMED_OP is the index of the constant slot in OPERANDS.
8542 N is the constant value. */
8544 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8545 int immed_op
, HOST_WIDE_INT n
)
8547 #if HOST_BITS_PER_WIDE_INT > 32
8553 /* Quick and easy output. */
8554 operands
[immed_op
] = const0_rtx
;
8555 output_asm_insn (instr1
, operands
);
8560 const char * instr
= instr1
;
8562 /* Note that n is never zero here (which would give no output). */
8563 for (i
= 0; i
< 32; i
+= 2)
8567 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8568 output_asm_insn (instr
, operands
);
8578 /* Return the appropriate ARM instruction for the operation code.
8579 The returned result should not be overwritten. OP is the rtx of the
8580 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8583 arithmetic_instr (rtx op
, int shift_first_arg
)
8585 switch (GET_CODE (op
))
8591 return shift_first_arg
? "rsb" : "sub";
8607 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8608 for the operation code. The returned result should not be overwritten.
8609 OP is the rtx code of the shift.
8610 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8613 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8616 enum rtx_code code
= GET_CODE (op
);
8618 switch (GET_CODE (XEXP (op
, 1)))
8626 *amountp
= INTVAL (XEXP (op
, 1));
8648 gcc_assert (*amountp
!= -1);
8649 *amountp
= 32 - *amountp
;
8658 /* We never have to worry about the amount being other than a
8659 power of 2, since this case can never be reloaded from a reg. */
8660 gcc_assert (*amountp
!= -1);
8661 *amountp
= int_log2 (*amountp
);
8670 /* This is not 100% correct, but follows from the desire to merge
8671 multiplication by a power of 2 with the recognizer for a
8672 shift. >=32 is not a valid shift for "asl", so we must try and
8673 output a shift that produces the correct arithmetical result.
8674 Using lsr #32 is identical except for the fact that the carry bit
8675 is not set correctly if we set the flags; but we never use the
8676 carry bit from such an operation, so we can ignore that. */
8677 if (code
== ROTATERT
)
8678 /* Rotate is just modulo 32. */
8680 else if (*amountp
!= (*amountp
& 31))
8687 /* Shifts of 0 are no-ops. */
8695 /* Obtain the shift from the POWER of two. */
8697 static HOST_WIDE_INT
8698 int_log2 (HOST_WIDE_INT power
)
8700 HOST_WIDE_INT shift
= 0;
8702 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
8704 gcc_assert (shift
<= 31);
8711 /* Output a .ascii pseudo-op, keeping track of lengths. This is
8712 because /bin/as is horribly restrictive. The judgement about
8713 whether or not each character is 'printable' (and can be output as
8714 is) or not (and must be printed with an octal escape) must be made
8715 with reference to the *host* character set -- the situation is
8716 similar to that discussed in the comments above pp_c_char in
8717 c-pretty-print.c. */
8719 #define MAX_ASCII_LEN 51
8722 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
8727 fputs ("\t.ascii\t\"", stream
);
8729 for (i
= 0; i
< len
; i
++)
8733 if (len_so_far
>= MAX_ASCII_LEN
)
8735 fputs ("\"\n\t.ascii\t\"", stream
);
8741 if (c
== '\\' || c
== '\"')
8743 putc ('\\', stream
);
8751 fprintf (stream
, "\\%03o", c
);
8756 fputs ("\"\n", stream
);
8759 /* Compute the register save mask for registers 0 through 12
8760 inclusive. This code is used by arm_compute_save_reg_mask. */
8762 static unsigned long
8763 arm_compute_save_reg0_reg12_mask (void)
8765 unsigned long func_type
= arm_current_func_type ();
8766 unsigned long save_reg_mask
= 0;
8769 if (IS_INTERRUPT (func_type
))
8771 unsigned int max_reg
;
8772 /* Interrupt functions must not corrupt any registers,
8773 even call clobbered ones. If this is a leaf function
8774 we can just examine the registers used by the RTL, but
8775 otherwise we have to assume that whatever function is
8776 called might clobber anything, and so we have to save
8777 all the call-clobbered registers as well. */
8778 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
8779 /* FIQ handlers have registers r8 - r12 banked, so
8780 we only need to check r0 - r7, Normal ISRs only
8781 bank r14 and r15, so we must check up to r12.
8782 r13 is the stack pointer which is always preserved,
8783 so we do not need to consider it here. */
8788 for (reg
= 0; reg
<= max_reg
; reg
++)
8789 if (regs_ever_live
[reg
]
8790 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
8791 save_reg_mask
|= (1 << reg
);
8793 /* Also save the pic base register if necessary. */
8795 && !TARGET_SINGLE_PIC_BASE
8796 && current_function_uses_pic_offset_table
)
8797 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8801 /* In the normal case we only need to save those registers
8802 which are call saved and which are used by this function. */
8803 for (reg
= 0; reg
<= 10; reg
++)
8804 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8805 save_reg_mask
|= (1 << reg
);
8807 /* Handle the frame pointer as a special case. */
8808 if (! TARGET_APCS_FRAME
8809 && ! frame_pointer_needed
8810 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
8811 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
8812 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
8814 /* If we aren't loading the PIC register,
8815 don't stack it even though it may be live. */
8817 && !TARGET_SINGLE_PIC_BASE
8818 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
8819 || current_function_uses_pic_offset_table
))
8820 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8823 /* Save registers so the exception handler can modify them. */
8824 if (current_function_calls_eh_return
)
8830 reg
= EH_RETURN_DATA_REGNO (i
);
8831 if (reg
== INVALID_REGNUM
)
8833 save_reg_mask
|= 1 << reg
;
8837 return save_reg_mask
;
8840 /* Compute a bit mask of which registers need to be
8841 saved on the stack for the current function. */
8843 static unsigned long
8844 arm_compute_save_reg_mask (void)
8846 unsigned int save_reg_mask
= 0;
8847 unsigned long func_type
= arm_current_func_type ();
8849 if (IS_NAKED (func_type
))
8850 /* This should never really happen. */
8853 /* If we are creating a stack frame, then we must save the frame pointer,
8854 IP (which will hold the old stack pointer), LR and the PC. */
8855 if (frame_pointer_needed
)
8857 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
8862 /* Volatile functions do not return, so there
8863 is no need to save any other registers. */
8864 if (IS_VOLATILE (func_type
))
8865 return save_reg_mask
;
8867 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
8869 /* Decide if we need to save the link register.
8870 Interrupt routines have their own banked link register,
8871 so they never need to save it.
8872 Otherwise if we do not use the link register we do not need to save
8873 it. If we are pushing other registers onto the stack however, we
8874 can save an instruction in the epilogue by pushing the link register
8875 now and then popping it back into the PC. This incurs extra memory
8876 accesses though, so we only do it when optimizing for size, and only
8877 if we know that we will not need a fancy return sequence. */
8878 if (regs_ever_live
[LR_REGNUM
]
8881 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8882 && !current_function_calls_eh_return
))
8883 save_reg_mask
|= 1 << LR_REGNUM
;
8885 if (cfun
->machine
->lr_save_eliminated
)
8886 save_reg_mask
&= ~ (1 << LR_REGNUM
);
8888 if (TARGET_REALLY_IWMMXT
8889 && ((bit_count (save_reg_mask
)
8890 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
8894 /* The total number of registers that are going to be pushed
8895 onto the stack is odd. We need to ensure that the stack
8896 is 64-bit aligned before we start to save iWMMXt registers,
8897 and also before we start to create locals. (A local variable
8898 might be a double or long long which we will load/store using
8899 an iWMMXt instruction). Therefore we need to push another
8900 ARM register, so that the stack will be 64-bit aligned. We
8901 try to avoid using the arg registers (r0 -r3) as they might be
8902 used to pass values in a tail call. */
8903 for (reg
= 4; reg
<= 12; reg
++)
8904 if ((save_reg_mask
& (1 << reg
)) == 0)
8908 save_reg_mask
|= (1 << reg
);
8911 cfun
->machine
->sibcall_blocked
= 1;
8912 save_reg_mask
|= (1 << 3);
8916 return save_reg_mask
;
8920 /* Compute a bit mask of which registers need to be
8921 saved on the stack for the current function. */
8922 static unsigned long
8923 thumb_compute_save_reg_mask (void)
8929 for (reg
= 0; reg
< 12; reg
++)
8930 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8933 if (flag_pic
&& !TARGET_SINGLE_PIC_BASE
)
8934 mask
|= (1 << PIC_OFFSET_TABLE_REGNUM
);
8936 if (TARGET_SINGLE_PIC_BASE
)
8937 mask
&= ~(1 << arm_pic_register
);
8939 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
8940 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
8941 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
8943 /* LR will also be pushed if any lo regs are pushed. */
8944 if (mask
& 0xff || thumb_force_lr_save ())
8945 mask
|= (1 << LR_REGNUM
);
8947 /* Make sure we have a low work register if we need one.
8948 We will need one if we are going to push a high register,
8949 but we are not currently intending to push a low register. */
8950 if ((mask
& 0xff) == 0
8951 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
8953 /* Use thumb_find_work_register to choose which register
8954 we will use. If the register is live then we will
8955 have to push it. Use LAST_LO_REGNUM as our fallback
8956 choice for the register to select. */
8957 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
8959 if (! call_used_regs
[reg
])
8967 /* Return the number of bytes required to save VFP registers. */
8969 arm_get_vfp_saved_size (void)
8976 /* Space for saved VFP registers. */
8977 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
8980 for (regno
= FIRST_VFP_REGNUM
;
8981 regno
< LAST_VFP_REGNUM
;
8984 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
8985 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
8989 /* Workaround ARM10 VFPr1 bug. */
8990 if (count
== 2 && !arm_arch6
)
8992 saved
+= count
* 8 + 4;
9001 if (count
== 2 && !arm_arch6
)
9003 saved
+= count
* 8 + 4;
9010 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9011 everything bar the final return instruction. */
9013 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9015 char conditional
[10];
9018 unsigned long live_regs_mask
;
9019 unsigned long func_type
;
9020 arm_stack_offsets
*offsets
;
9022 func_type
= arm_current_func_type ();
9024 if (IS_NAKED (func_type
))
9027 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9029 /* If this function was declared non-returning, and we have
9030 found a tail call, then we have to trust that the called
9031 function won't return. */
9036 /* Otherwise, trap an attempted return by aborting. */
9038 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9040 assemble_external_libcall (ops
[1]);
9041 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9047 gcc_assert (!current_function_calls_alloca
|| really_return
);
9049 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9051 return_used_this_function
= 1;
9053 live_regs_mask
= arm_compute_save_reg_mask ();
9057 const char * return_reg
;
9059 /* If we do not have any special requirements for function exit
9060 (e.g. interworking, or ISR) then we can load the return address
9061 directly into the PC. Otherwise we must load it into LR. */
9063 && ! TARGET_INTERWORK
)
9064 return_reg
= reg_names
[PC_REGNUM
];
9066 return_reg
= reg_names
[LR_REGNUM
];
9068 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9070 /* There are three possible reasons for the IP register
9071 being saved. 1) a stack frame was created, in which case
9072 IP contains the old stack pointer, or 2) an ISR routine
9073 corrupted it, or 3) it was saved to align the stack on
9074 iWMMXt. In case 1, restore IP into SP, otherwise just
9076 if (frame_pointer_needed
)
9078 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9079 live_regs_mask
|= (1 << SP_REGNUM
);
9082 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9085 /* On some ARM architectures it is faster to use LDR rather than
9086 LDM to load a single register. On other architectures, the
9087 cost is the same. In 26 bit mode, or for exception handlers,
9088 we have to use LDM to load the PC so that the CPSR is also
9090 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9091 if (live_regs_mask
== (1U << reg
))
9094 if (reg
<= LAST_ARM_REGNUM
9095 && (reg
!= LR_REGNUM
9097 || ! IS_INTERRUPT (func_type
)))
9099 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9100 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9107 /* Generate the load multiple instruction to restore the
9108 registers. Note we can get here, even if
9109 frame_pointer_needed is true, but only if sp already
9110 points to the base of the saved core registers. */
9111 if (live_regs_mask
& (1 << SP_REGNUM
))
9113 unsigned HOST_WIDE_INT stack_adjust
;
9115 offsets
= arm_get_frame_offsets ();
9116 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9117 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9119 if (stack_adjust
&& arm_arch5
)
9120 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9123 /* If we can't use ldmib (SA110 bug),
9124 then try to pop r3 instead. */
9126 live_regs_mask
|= 1 << 3;
9127 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9131 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9133 p
= instr
+ strlen (instr
);
9135 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9136 if (live_regs_mask
& (1 << reg
))
9138 int l
= strlen (reg_names
[reg
]);
9144 memcpy (p
, ", ", 2);
9148 memcpy (p
, "%|", 2);
9149 memcpy (p
+ 2, reg_names
[reg
], l
);
9153 if (live_regs_mask
& (1 << LR_REGNUM
))
9155 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9156 /* If returning from an interrupt, restore the CPSR. */
9157 if (IS_INTERRUPT (func_type
))
9164 output_asm_insn (instr
, & operand
);
9166 /* See if we need to generate an extra instruction to
9167 perform the actual function return. */
9169 && func_type
!= ARM_FT_INTERWORKED
9170 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9172 /* The return has already been handled
9173 by loading the LR into the PC. */
9180 switch ((int) ARM_FUNC_TYPE (func_type
))
9184 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9187 case ARM_FT_INTERWORKED
:
9188 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9191 case ARM_FT_EXCEPTION
:
9192 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9196 /* Use bx if it's available. */
9197 if (arm_arch5
|| arm_arch4t
)
9198 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9200 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9204 output_asm_insn (instr
, & operand
);
9210 /* Write the function name into the code section, directly preceding
9211 the function prologue.
9213 Code will be output similar to this:
9215 .ascii "arm_poke_function_name", 0
9218 .word 0xff000000 + (t1 - t0)
9219 arm_poke_function_name
9221 stmfd sp!, {fp, ip, lr, pc}
9224 When performing a stack backtrace, code can inspect the value
9225 of 'pc' stored at 'fp' + 0. If the trace function then looks
9226 at location pc - 12 and the top 8 bits are set, then we know
9227 that there is a function name embedded immediately preceding this
9228 location and has length ((pc[-3]) & 0xff000000).
9230 We assume that pc is declared as a pointer to an unsigned long.
9232 It is of no benefit to output the function name if we are assembling
9233 a leaf function. These function types will not contain a stack
9234 backtrace structure, therefore it is not possible to determine the
9237 arm_poke_function_name (FILE *stream
, const char *name
)
9239 unsigned long alignlength
;
9240 unsigned long length
;
9243 length
= strlen (name
) + 1;
9244 alignlength
= ROUND_UP_WORD (length
);
9246 ASM_OUTPUT_ASCII (stream
, name
, length
);
9247 ASM_OUTPUT_ALIGN (stream
, 2);
9248 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9249 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9252 /* Place some comments into the assembler stream
9253 describing the current function. */
9255 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9257 unsigned long func_type
;
9261 thumb_output_function_prologue (f
, frame_size
);
9266 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9268 func_type
= arm_current_func_type ();
9270 switch ((int) ARM_FUNC_TYPE (func_type
))
9275 case ARM_FT_INTERWORKED
:
9276 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9279 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9282 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9284 case ARM_FT_EXCEPTION
:
9285 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9289 if (IS_NAKED (func_type
))
9290 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9292 if (IS_VOLATILE (func_type
))
9293 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9295 if (IS_NESTED (func_type
))
9296 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9298 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9299 current_function_args_size
,
9300 current_function_pretend_args_size
, frame_size
);
9302 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9303 frame_pointer_needed
,
9304 cfun
->machine
->uses_anonymous_args
);
9306 if (cfun
->machine
->lr_save_eliminated
)
9307 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9309 if (current_function_calls_eh_return
)
9310 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9312 #ifdef AOF_ASSEMBLER
9314 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9317 return_used_this_function
= 0;
9321 arm_output_epilogue (rtx sibling
)
9324 unsigned long saved_regs_mask
;
9325 unsigned long func_type
;
9326 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9327 frame that is $fp + 4 for a non-variadic function. */
9328 int floats_offset
= 0;
9330 FILE * f
= asm_out_file
;
9331 unsigned int lrm_count
= 0;
9332 int really_return
= (sibling
== NULL
);
9334 arm_stack_offsets
*offsets
;
9336 /* If we have already generated the return instruction
9337 then it is futile to generate anything else. */
9338 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9341 func_type
= arm_current_func_type ();
9343 if (IS_NAKED (func_type
))
9344 /* Naked functions don't have epilogues. */
9347 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9351 /* A volatile function should never return. Call abort. */
9352 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9353 assemble_external_libcall (op
);
9354 output_asm_insn ("bl\t%a0", &op
);
9359 /* If we are throwing an exception, then we really must be doing a
9360 return, so we can't tail-call. */
9361 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9363 offsets
= arm_get_frame_offsets ();
9364 saved_regs_mask
= arm_compute_save_reg_mask ();
9367 lrm_count
= bit_count (saved_regs_mask
);
9369 floats_offset
= offsets
->saved_args
;
9370 /* Compute how far away the floats will be. */
9371 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9372 if (saved_regs_mask
& (1 << reg
))
9375 if (frame_pointer_needed
)
9377 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9378 int vfp_offset
= offsets
->frame
;
9380 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9382 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9383 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9385 floats_offset
+= 12;
9386 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9387 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9392 start_reg
= LAST_FPA_REGNUM
;
9394 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9396 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9398 floats_offset
+= 12;
9400 /* We can't unstack more than four registers at once. */
9401 if (start_reg
- reg
== 3)
9403 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9404 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9405 start_reg
= reg
- 1;
9410 if (reg
!= start_reg
)
9411 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9412 reg
+ 1, start_reg
- reg
,
9413 FP_REGNUM
, floats_offset
- vfp_offset
);
9414 start_reg
= reg
- 1;
9418 /* Just in case the last register checked also needs unstacking. */
9419 if (reg
!= start_reg
)
9420 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9421 reg
+ 1, start_reg
- reg
,
9422 FP_REGNUM
, floats_offset
- vfp_offset
);
9425 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9429 /* The fldmx insn does not have base+offset addressing modes,
9430 so we use IP to hold the address. */
9431 saved_size
= arm_get_vfp_saved_size ();
9435 floats_offset
+= saved_size
;
9436 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9437 FP_REGNUM
, floats_offset
- vfp_offset
);
9439 start_reg
= FIRST_VFP_REGNUM
;
9440 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9442 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9443 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9445 if (start_reg
!= reg
)
9446 arm_output_fldmx (f
, IP_REGNUM
,
9447 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9448 (reg
- start_reg
) / 2);
9449 start_reg
= reg
+ 2;
9452 if (start_reg
!= reg
)
9453 arm_output_fldmx (f
, IP_REGNUM
,
9454 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9455 (reg
- start_reg
) / 2);
9460 /* The frame pointer is guaranteed to be non-double-word aligned.
9461 This is because it is set to (old_stack_pointer - 4) and the
9462 old_stack_pointer was double word aligned. Thus the offset to
9463 the iWMMXt registers to be loaded must also be non-double-word
9464 sized, so that the resultant address *is* double-word aligned.
9465 We can ignore floats_offset since that was already included in
9466 the live_regs_mask. */
9467 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9469 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9470 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9472 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9473 reg
, FP_REGNUM
, lrm_count
* 4);
9478 /* saved_regs_mask should contain the IP, which at the time of stack
9479 frame generation actually contains the old stack pointer. So a
9480 quick way to unwind the stack is just pop the IP register directly
9481 into the stack pointer. */
9482 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9483 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9484 saved_regs_mask
|= (1 << SP_REGNUM
);
9486 /* There are two registers left in saved_regs_mask - LR and PC. We
9487 only need to restore the LR register (the return address), but to
9488 save time we can load it directly into the PC, unless we need a
9489 special function exit sequence, or we are not really returning. */
9491 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9492 && !current_function_calls_eh_return
)
9493 /* Delete the LR from the register mask, so that the LR on
9494 the stack is loaded into the PC in the register mask. */
9495 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9497 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9499 /* We must use SP as the base register, because SP is one of the
9500 registers being restored. If an interrupt or page fault
9501 happens in the ldm instruction, the SP might or might not
9502 have been restored. That would be bad, as then SP will no
9503 longer indicate the safe area of stack, and we can get stack
9504 corruption. Using SP as the base register means that it will
9505 be reset correctly to the original value, should an interrupt
9506 occur. If the stack pointer already points at the right
9507 place, then omit the subtraction. */
9508 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9509 || current_function_calls_alloca
)
9510 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9511 4 * bit_count (saved_regs_mask
));
9512 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9514 if (IS_INTERRUPT (func_type
))
9515 /* Interrupt handlers will have pushed the
9516 IP onto the stack, so restore it now. */
9517 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9521 /* Restore stack pointer if necessary. */
9522 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9524 operands
[0] = operands
[1] = stack_pointer_rtx
;
9525 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9526 output_add_immediate (operands
);
9529 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9531 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9532 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9533 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9538 start_reg
= FIRST_FPA_REGNUM
;
9540 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9542 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9544 if (reg
- start_reg
== 3)
9546 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9547 start_reg
, SP_REGNUM
);
9548 start_reg
= reg
+ 1;
9553 if (reg
!= start_reg
)
9554 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9555 start_reg
, reg
- start_reg
,
9558 start_reg
= reg
+ 1;
9562 /* Just in case the last register checked also needs unstacking. */
9563 if (reg
!= start_reg
)
9564 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9565 start_reg
, reg
- start_reg
, SP_REGNUM
);
9568 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9570 start_reg
= FIRST_VFP_REGNUM
;
9571 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9573 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9574 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9576 if (start_reg
!= reg
)
9577 arm_output_fldmx (f
, SP_REGNUM
,
9578 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9579 (reg
- start_reg
) / 2);
9580 start_reg
= reg
+ 2;
9583 if (start_reg
!= reg
)
9584 arm_output_fldmx (f
, SP_REGNUM
,
9585 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9586 (reg
- start_reg
) / 2);
9589 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9590 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9591 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9593 /* If we can, restore the LR into the PC. */
9594 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9596 && current_function_pretend_args_size
== 0
9597 && saved_regs_mask
& (1 << LR_REGNUM
)
9598 && !current_function_calls_eh_return
)
9600 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9601 saved_regs_mask
|= (1 << PC_REGNUM
);
9604 /* Load the registers off the stack. If we only have one register
9605 to load use the LDR instruction - it is faster. */
9606 if (saved_regs_mask
== (1 << LR_REGNUM
))
9608 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9610 else if (saved_regs_mask
)
9612 if (saved_regs_mask
& (1 << SP_REGNUM
))
9613 /* Note - write back to the stack register is not enabled
9614 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9615 in the list of registers and if we add writeback the
9616 instruction becomes UNPREDICTABLE. */
9617 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9619 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9622 if (current_function_pretend_args_size
)
9624 /* Unwind the pre-pushed regs. */
9625 operands
[0] = operands
[1] = stack_pointer_rtx
;
9626 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9627 output_add_immediate (operands
);
9631 /* We may have already restored PC directly from the stack. */
9632 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
9635 /* Stack adjustment for exception handler. */
9636 if (current_function_calls_eh_return
)
9637 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
9638 ARM_EH_STACKADJ_REGNUM
);
9640 /* Generate the return instruction. */
9641 switch ((int) ARM_FUNC_TYPE (func_type
))
9645 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
9648 case ARM_FT_EXCEPTION
:
9649 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9652 case ARM_FT_INTERWORKED
:
9653 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9657 if (arm_arch5
|| arm_arch4t
)
9658 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9660 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9668 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9669 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
9671 arm_stack_offsets
*offsets
;
9677 /* Emit any call-via-reg trampolines that are needed for v4t support
9678 of call_reg and call_value_reg type insns. */
9679 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
9681 rtx label
= cfun
->machine
->call_via
[regno
];
9685 function_section (current_function_decl
);
9686 targetm
.asm_out
.internal_label (asm_out_file
, "L",
9687 CODE_LABEL_NUMBER (label
));
9688 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
9692 /* ??? Probably not safe to set this here, since it assumes that a
9693 function will be emitted as assembly immediately after we generate
9694 RTL for it. This does not happen for inline functions. */
9695 return_used_this_function
= 0;
9699 /* We need to take into account any stack-frame rounding. */
9700 offsets
= arm_get_frame_offsets ();
9702 gcc_assert (!use_return_insn (FALSE
, NULL
)
9703 || !return_used_this_function
9704 || offsets
->saved_regs
== offsets
->outgoing_args
9705 || frame_pointer_needed
);
9707 /* Reset the ARM-specific per-function variables. */
9708 after_arm_reorg
= 0;
9712 /* Generate and emit an insn that we will recognize as a push_multi.
9713 Unfortunately, since this insn does not reflect very well the actual
9714 semantics of the operation, we need to annotate the insn for the benefit
9715 of DWARF2 frame unwind information. */
9717 emit_multi_reg_push (unsigned long mask
)
9724 int dwarf_par_index
;
9727 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9728 if (mask
& (1 << i
))
9731 gcc_assert (num_regs
&& num_regs
<= 16);
9733 /* We don't record the PC in the dwarf frame information. */
9734 num_dwarf_regs
= num_regs
;
9735 if (mask
& (1 << PC_REGNUM
))
9738 /* For the body of the insn we are going to generate an UNSPEC in
9739 parallel with several USEs. This allows the insn to be recognized
9740 by the push_multi pattern in the arm.md file. The insn looks
9741 something like this:
9744 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9745 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9746 (use (reg:SI 11 fp))
9747 (use (reg:SI 12 ip))
9748 (use (reg:SI 14 lr))
9749 (use (reg:SI 15 pc))
9752 For the frame note however, we try to be more explicit and actually
9753 show each register being stored into the stack frame, plus a (single)
9754 decrement of the stack pointer. We do it this way in order to be
9755 friendly to the stack unwinding code, which only wants to see a single
9756 stack decrement per instruction. The RTL we generate for the note looks
9757 something like this:
9760 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9761 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9762 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9763 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9764 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9767 This sequence is used both by the code to support stack unwinding for
9768 exceptions handlers and the code to generate dwarf2 frame debugging. */
9770 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
9771 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
9772 dwarf_par_index
= 1;
9774 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9776 if (mask
& (1 << i
))
9778 reg
= gen_rtx_REG (SImode
, i
);
9781 = gen_rtx_SET (VOIDmode
,
9782 gen_rtx_MEM (BLKmode
,
9783 gen_rtx_PRE_DEC (BLKmode
,
9784 stack_pointer_rtx
)),
9785 gen_rtx_UNSPEC (BLKmode
,
9791 tmp
= gen_rtx_SET (VOIDmode
,
9792 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
9794 RTX_FRAME_RELATED_P (tmp
) = 1;
9795 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
9803 for (j
= 1, i
++; j
< num_regs
; i
++)
9805 if (mask
& (1 << i
))
9807 reg
= gen_rtx_REG (SImode
, i
);
9809 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
9813 tmp
= gen_rtx_SET (VOIDmode
,
9814 gen_rtx_MEM (SImode
,
9815 plus_constant (stack_pointer_rtx
,
9818 RTX_FRAME_RELATED_P (tmp
) = 1;
9819 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
9826 par
= emit_insn (par
);
9828 tmp
= gen_rtx_SET (SImode
,
9830 gen_rtx_PLUS (SImode
,
9832 GEN_INT (-4 * num_regs
)));
9833 RTX_FRAME_RELATED_P (tmp
) = 1;
9834 XVECEXP (dwarf
, 0, 0) = tmp
;
9836 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9841 /* Calculate the size of the return value that is passed in registers. */
9843 arm_size_return_regs (void)
9845 enum machine_mode mode
;
9847 if (current_function_return_rtx
!= 0)
9848 mode
= GET_MODE (current_function_return_rtx
);
9850 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9852 return GET_MODE_SIZE (mode
);
9856 emit_sfm (int base_reg
, int count
)
9863 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
9864 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
9866 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9869 = gen_rtx_SET (VOIDmode
,
9870 gen_rtx_MEM (BLKmode
,
9871 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
9872 gen_rtx_UNSPEC (BLKmode
,
9875 tmp
= gen_rtx_SET (VOIDmode
,
9876 gen_rtx_MEM (XFmode
, stack_pointer_rtx
), reg
);
9877 RTX_FRAME_RELATED_P (tmp
) = 1;
9878 XVECEXP (dwarf
, 0, 1) = tmp
;
9880 for (i
= 1; i
< count
; i
++)
9882 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9883 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
9885 tmp
= gen_rtx_SET (VOIDmode
,
9886 gen_rtx_MEM (XFmode
,
9887 plus_constant (stack_pointer_rtx
,
9890 RTX_FRAME_RELATED_P (tmp
) = 1;
9891 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
9894 tmp
= gen_rtx_SET (VOIDmode
,
9896 gen_rtx_PLUS (SImode
,
9898 GEN_INT (-12 * count
)));
9899 RTX_FRAME_RELATED_P (tmp
) = 1;
9900 XVECEXP (dwarf
, 0, 0) = tmp
;
9902 par
= emit_insn (par
);
9903 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9909 /* Return true if the current function needs to save/restore LR. */
9912 thumb_force_lr_save (void)
9914 return !cfun
->machine
->lr_save_eliminated
9915 && (!leaf_function_p ()
9916 || thumb_far_jump_used_p ()
9917 || regs_ever_live
[LR_REGNUM
]);
9921 /* Compute the distance from register FROM to register TO.
9922 These can be the arg pointer (26), the soft frame pointer (25),
9923 the stack pointer (13) or the hard frame pointer (11).
9924 In thumb mode r7 is used as the soft frame pointer, if needed.
9925 Typical stack layout looks like this:
9927 old stack pointer -> | |
9930 | | saved arguments for
9931 | | vararg functions
9934 hard FP & arg pointer -> | | \
9942 soft frame pointer -> | | /
9952 current stack pointer -> | | /
9955 For a given function some or all of these stack components
9956 may not be needed, giving rise to the possibility of
9957 eliminating some of the registers.
9959 The values returned by this function must reflect the behavior
9960 of arm_expand_prologue() and arm_compute_save_reg_mask().
9962 The sign of the number returned reflects the direction of stack
9963 growth, so the values are positive for all eliminations except
9964 from the soft frame pointer to the hard frame pointer.
9966 SFP may point just inside the local variables block to ensure correct
9970 /* Calculate stack offsets. These are used to calculate register elimination
9971 offsets and in prologue/epilogue code. */
9973 static arm_stack_offsets
*
9974 arm_get_frame_offsets (void)
9976 struct arm_stack_offsets
*offsets
;
9977 unsigned long func_type
;
9980 HOST_WIDE_INT frame_size
;
9982 offsets
= &cfun
->machine
->stack_offsets
;
9984 /* We need to know if we are a leaf function. Unfortunately, it
9985 is possible to be called after start_sequence has been called,
9986 which causes get_insns to return the insns for the sequence,
9987 not the function, which will cause leaf_function_p to return
9988 the incorrect result.
9990 to know about leaf functions once reload has completed, and the
9991 frame size cannot be changed after that time, so we can safely
9992 use the cached value. */
9994 if (reload_completed
)
9997 /* Initially this is the size of the local variables. It will translated
9998 into an offset once we have determined the size of preceding data. */
9999 frame_size
= ROUND_UP_WORD (get_frame_size ());
10001 leaf
= leaf_function_p ();
10003 /* Space for variadic functions. */
10004 offsets
->saved_args
= current_function_pretend_args_size
;
10006 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10010 unsigned int regno
;
10012 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10014 /* We know that SP will be doubleword aligned on entry, and we must
10015 preserve that condition at any subroutine call. We also require the
10016 soft frame pointer to be doubleword aligned. */
10018 if (TARGET_REALLY_IWMMXT
)
10020 /* Check for the call-saved iWMMXt registers. */
10021 for (regno
= FIRST_IWMMXT_REGNUM
;
10022 regno
<= LAST_IWMMXT_REGNUM
;
10024 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10028 func_type
= arm_current_func_type ();
10029 if (! IS_VOLATILE (func_type
))
10031 /* Space for saved FPA registers. */
10032 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10033 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10036 /* Space for saved VFP registers. */
10037 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10038 saved
+= arm_get_vfp_saved_size ();
10041 else /* TARGET_THUMB */
10043 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10044 if (TARGET_BACKTRACE
)
10048 /* Saved registers include the stack frame. */
10049 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10050 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10051 /* A leaf function does not need any stack alignment if it has nothing
10053 if (leaf
&& frame_size
== 0)
10055 offsets
->outgoing_args
= offsets
->soft_frame
;
10059 /* Ensure SFP has the correct alignment. */
10060 if (ARM_DOUBLEWORD_ALIGN
10061 && (offsets
->soft_frame
& 7))
10062 offsets
->soft_frame
+= 4;
10064 offsets
->outgoing_args
= offsets
->soft_frame
+ frame_size
10065 + current_function_outgoing_args_size
;
10067 if (ARM_DOUBLEWORD_ALIGN
)
10069 /* Ensure SP remains doubleword aligned. */
10070 if (offsets
->outgoing_args
& 7)
10071 offsets
->outgoing_args
+= 4;
10072 gcc_assert (!(offsets
->outgoing_args
& 7));
10079 /* Calculate the relative offsets for the different stack pointers. Positive
10080 offsets are in the direction of stack growth. */
10083 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10085 arm_stack_offsets
*offsets
;
10087 offsets
= arm_get_frame_offsets ();
10089 /* OK, now we have enough information to compute the distances.
10090 There must be an entry in these switch tables for each pair
10091 of registers in ELIMINABLE_REGS, even if some of the entries
10092 seem to be redundant or useless. */
10095 case ARG_POINTER_REGNUM
:
10098 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10101 case FRAME_POINTER_REGNUM
:
10102 /* This is the reverse of the soft frame pointer
10103 to hard frame pointer elimination below. */
10104 return offsets
->soft_frame
- offsets
->saved_args
;
10106 case ARM_HARD_FRAME_POINTER_REGNUM
:
10107 /* If there is no stack frame then the hard
10108 frame pointer and the arg pointer coincide. */
10109 if (offsets
->frame
== offsets
->saved_regs
)
10111 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10112 return (frame_pointer_needed
10113 && cfun
->static_chain_decl
!= NULL
10114 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10116 case STACK_POINTER_REGNUM
:
10117 /* If nothing has been pushed on the stack at all
10118 then this will return -4. This *is* correct! */
10119 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10122 gcc_unreachable ();
10124 gcc_unreachable ();
10126 case FRAME_POINTER_REGNUM
:
10129 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10132 case ARM_HARD_FRAME_POINTER_REGNUM
:
10133 /* The hard frame pointer points to the top entry in the
10134 stack frame. The soft frame pointer to the bottom entry
10135 in the stack frame. If there is no stack frame at all,
10136 then they are identical. */
10138 return offsets
->frame
- offsets
->soft_frame
;
10140 case STACK_POINTER_REGNUM
:
10141 return offsets
->outgoing_args
- offsets
->soft_frame
;
10144 gcc_unreachable ();
10146 gcc_unreachable ();
10149 /* You cannot eliminate from the stack pointer.
10150 In theory you could eliminate from the hard frame
10151 pointer to the stack pointer, but this will never
10152 happen, since if a stack frame is not needed the
10153 hard frame pointer will never be used. */
10154 gcc_unreachable ();
10159 /* Generate the prologue instructions for entry into an ARM function. */
10161 arm_expand_prologue (void)
10167 unsigned long live_regs_mask
;
10168 unsigned long func_type
;
10170 int saved_pretend_args
= 0;
10171 int saved_regs
= 0;
10172 unsigned HOST_WIDE_INT args_to_push
;
10173 arm_stack_offsets
*offsets
;
10175 func_type
= arm_current_func_type ();
10177 /* Naked functions don't have prologues. */
10178 if (IS_NAKED (func_type
))
10181 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10182 args_to_push
= current_function_pretend_args_size
;
10184 /* Compute which register we will have to save onto the stack. */
10185 live_regs_mask
= arm_compute_save_reg_mask ();
10187 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10189 if (frame_pointer_needed
)
10191 if (IS_INTERRUPT (func_type
))
10193 /* Interrupt functions must not corrupt any registers.
10194 Creating a frame pointer however, corrupts the IP
10195 register, so we must push it first. */
10196 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10198 /* Do not set RTX_FRAME_RELATED_P on this insn.
10199 The dwarf stack unwinding code only wants to see one
10200 stack decrement per function, and this is not it. If
10201 this instruction is labeled as being part of the frame
10202 creation sequence then dwarf2out_frame_debug_expr will
10203 die when it encounters the assignment of IP to FP
10204 later on, since the use of SP here establishes SP as
10205 the CFA register and not IP.
10207 Anyway this instruction is not really part of the stack
10208 frame creation although it is part of the prologue. */
10210 else if (IS_NESTED (func_type
))
10212 /* The Static chain register is the same as the IP register
10213 used as a scratch register during stack frame creation.
10214 To get around this need to find somewhere to store IP
10215 whilst the frame is being created. We try the following
10218 1. The last argument register.
10219 2. A slot on the stack above the frame. (This only
10220 works if the function is not a varargs function).
10221 3. Register r3, after pushing the argument registers
10224 Note - we only need to tell the dwarf2 backend about the SP
10225 adjustment in the second variant; the static chain register
10226 doesn't need to be unwound, as it doesn't contain a value
10227 inherited from the caller. */
10229 if (regs_ever_live
[3] == 0)
10231 insn
= gen_rtx_REG (SImode
, 3);
10232 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10233 insn
= emit_insn (insn
);
10235 else if (args_to_push
== 0)
10238 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10239 insn
= gen_rtx_MEM (SImode
, insn
);
10240 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10241 insn
= emit_insn (insn
);
10245 /* Just tell the dwarf backend that we adjusted SP. */
10246 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10247 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10248 GEN_INT (-fp_offset
)));
10249 RTX_FRAME_RELATED_P (insn
) = 1;
10250 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10251 dwarf
, REG_NOTES (insn
));
10255 /* Store the args on the stack. */
10256 if (cfun
->machine
->uses_anonymous_args
)
10257 insn
= emit_multi_reg_push
10258 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10261 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10262 GEN_INT (- args_to_push
)));
10264 RTX_FRAME_RELATED_P (insn
) = 1;
10266 saved_pretend_args
= 1;
10267 fp_offset
= args_to_push
;
10270 /* Now reuse r3 to preserve IP. */
10271 insn
= gen_rtx_REG (SImode
, 3);
10272 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10273 (void) emit_insn (insn
);
10279 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10280 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10283 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10285 insn
= emit_insn (insn
);
10286 RTX_FRAME_RELATED_P (insn
) = 1;
10291 /* Push the argument registers, or reserve space for them. */
10292 if (cfun
->machine
->uses_anonymous_args
)
10293 insn
= emit_multi_reg_push
10294 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10297 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10298 GEN_INT (- args_to_push
)));
10299 RTX_FRAME_RELATED_P (insn
) = 1;
10302 /* If this is an interrupt service routine, and the link register
10303 is going to be pushed, and we are not creating a stack frame,
10304 (which would involve an extra push of IP and a pop in the epilogue)
10305 subtracting four from LR now will mean that the function return
10306 can be done with a single instruction. */
10307 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10308 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10309 && ! frame_pointer_needed
)
10310 emit_insn (gen_rtx_SET (SImode
,
10311 gen_rtx_REG (SImode
, LR_REGNUM
),
10312 gen_rtx_PLUS (SImode
,
10313 gen_rtx_REG (SImode
, LR_REGNUM
),
10316 if (live_regs_mask
)
10318 insn
= emit_multi_reg_push (live_regs_mask
);
10319 saved_regs
+= bit_count (live_regs_mask
) * 4;
10320 RTX_FRAME_RELATED_P (insn
) = 1;
10324 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10325 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10327 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10328 insn
= gen_rtx_MEM (V2SImode
, insn
);
10329 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10330 gen_rtx_REG (V2SImode
, reg
)));
10331 RTX_FRAME_RELATED_P (insn
) = 1;
10335 if (! IS_VOLATILE (func_type
))
10339 /* Save any floating point call-saved registers used by this
10341 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10343 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10344 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10346 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10347 insn
= gen_rtx_MEM (XFmode
, insn
);
10348 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10349 gen_rtx_REG (XFmode
, reg
)));
10350 RTX_FRAME_RELATED_P (insn
) = 1;
10356 start_reg
= LAST_FPA_REGNUM
;
10358 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10360 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10362 if (start_reg
- reg
== 3)
10364 insn
= emit_sfm (reg
, 4);
10365 RTX_FRAME_RELATED_P (insn
) = 1;
10367 start_reg
= reg
- 1;
10372 if (start_reg
!= reg
)
10374 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10375 RTX_FRAME_RELATED_P (insn
) = 1;
10376 saved_regs
+= (start_reg
- reg
) * 12;
10378 start_reg
= reg
- 1;
10382 if (start_reg
!= reg
)
10384 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10385 saved_regs
+= (start_reg
- reg
) * 12;
10386 RTX_FRAME_RELATED_P (insn
) = 1;
10389 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10391 start_reg
= FIRST_VFP_REGNUM
;
10393 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10395 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10396 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10398 if (start_reg
!= reg
)
10399 saved_regs
+= vfp_emit_fstmx (start_reg
,
10400 (reg
- start_reg
) / 2);
10401 start_reg
= reg
+ 2;
10404 if (start_reg
!= reg
)
10405 saved_regs
+= vfp_emit_fstmx (start_reg
,
10406 (reg
- start_reg
) / 2);
10410 if (frame_pointer_needed
)
10412 /* Create the new frame pointer. */
10413 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10414 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10415 RTX_FRAME_RELATED_P (insn
) = 1;
10417 if (IS_NESTED (func_type
))
10419 /* Recover the static chain register. */
10420 if (regs_ever_live
[3] == 0
10421 || saved_pretend_args
)
10422 insn
= gen_rtx_REG (SImode
, 3);
10423 else /* if (current_function_pretend_args_size == 0) */
10425 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10427 insn
= gen_rtx_MEM (SImode
, insn
);
10430 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10431 /* Add a USE to stop propagate_one_insn() from barfing. */
10432 emit_insn (gen_prologue_use (ip_rtx
));
10436 offsets
= arm_get_frame_offsets ();
10437 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10439 /* This add can produce multiple insns for a large constant, so we
10440 need to get tricky. */
10441 rtx last
= get_last_insn ();
10443 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10444 - offsets
->outgoing_args
);
10446 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10450 last
= last
? NEXT_INSN (last
) : get_insns ();
10451 RTX_FRAME_RELATED_P (last
) = 1;
10453 while (last
!= insn
);
10455 /* If the frame pointer is needed, emit a special barrier that
10456 will prevent the scheduler from moving stores to the frame
10457 before the stack adjustment. */
10458 if (frame_pointer_needed
)
10459 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10460 hard_frame_pointer_rtx
));
10465 arm_load_pic_register (INVALID_REGNUM
);
10467 /* If we are profiling, make sure no instructions are scheduled before
10468 the call to mcount. Similarly if the user has requested no
10469 scheduling in the prolog. */
10470 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
10471 emit_insn (gen_blockage ());
10473 /* If the link register is being kept alive, with the return address in it,
10474 then make sure that it does not get reused by the ce2 pass. */
10475 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10477 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10478 cfun
->machine
->lr_save_eliminated
= 1;
10482 /* If CODE is 'd', then the X is a condition operand and the instruction
10483 should only be executed if the condition is true.
10484 if CODE is 'D', then the X is a condition operand and the instruction
10485 should only be executed if the condition is false: however, if the mode
10486 of the comparison is CCFPEmode, then always execute the instruction -- we
10487 do this because in these circumstances !GE does not necessarily imply LT;
10488 in these cases the instruction pattern will take care to make sure that
10489 an instruction containing %d will follow, thereby undoing the effects of
10490 doing this instruction unconditionally.
10491 If CODE is 'N' then X is a floating point operand that must be negated
10493 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10494 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10496 arm_print_operand (FILE *stream
, rtx x
, int code
)
10501 fputs (ASM_COMMENT_START
, stream
);
10505 fputs (user_label_prefix
, stream
);
10509 fputs (REGISTER_PREFIX
, stream
);
10513 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10517 output_operand_lossage ("predicated Thumb instruction");
10520 if (current_insn_predicate
!= NULL
)
10522 output_operand_lossage
10523 ("predicated instruction in conditional sequence");
10527 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10529 else if (current_insn_predicate
)
10531 enum arm_cond_code code
;
10535 output_operand_lossage ("predicated Thumb instruction");
10539 code
= get_arm_condition_code (current_insn_predicate
);
10540 fputs (arm_condition_codes
[code
], stream
);
10547 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10548 r
= REAL_VALUE_NEGATE (r
);
10549 fprintf (stream
, "%s", fp_const_from_val (&r
));
10554 if (GET_CODE (x
) == CONST_INT
)
10557 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10558 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10562 putc ('~', stream
);
10563 output_addr_const (stream
, x
);
10568 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10571 /* Truncate Cirrus shift counts. */
10573 if (GET_CODE (x
) == CONST_INT
)
10575 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10578 arm_print_operand (stream
, x
, 0);
10582 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10588 const char * shift
= shift_op (x
, &val
);
10592 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10594 arm_print_operand (stream
, XEXP (x
, 1), 0);
10596 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10601 /* An explanation of the 'Q', 'R' and 'H' register operands:
10603 In a pair of registers containing a DI or DF value the 'Q'
10604 operand returns the register number of the register containing
10605 the least significant part of the value. The 'R' operand returns
10606 the register number of the register containing the most
10607 significant part of the value.
10609 The 'H' operand returns the higher of the two register numbers.
10610 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10611 same as the 'Q' operand, since the most significant part of the
10612 value is held in the lower number register. The reverse is true
10613 on systems where WORDS_BIG_ENDIAN is false.
10615 The purpose of these operands is to distinguish between cases
10616 where the endian-ness of the values is important (for example
10617 when they are added together), and cases where the endian-ness
10618 is irrelevant, but the order of register operations is important.
10619 For example when loading a value from memory into a register
10620 pair, the endian-ness does not matter. Provided that the value
10621 from the lower memory address is put into the lower numbered
10622 register, and the value from the higher address is put into the
10623 higher numbered register, the load will work regardless of whether
10624 the value being loaded is big-wordian or little-wordian. The
10625 order of the two register loads can matter however, if the address
10626 of the memory location is actually held in one of the registers
10627 being overwritten by the load. */
10629 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10631 output_operand_lossage ("invalid operand for code '%c'", code
);
10635 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
10639 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10641 output_operand_lossage ("invalid operand for code '%c'", code
);
10645 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
10649 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10651 output_operand_lossage ("invalid operand for code '%c'", code
);
10655 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
10659 asm_fprintf (stream
, "%r",
10660 GET_CODE (XEXP (x
, 0)) == REG
10661 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
10665 asm_fprintf (stream
, "{%r-%r}",
10667 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
10671 /* CONST_TRUE_RTX means always -- that's the default. */
10672 if (x
== const_true_rtx
)
10675 if (!COMPARISON_P (x
))
10677 output_operand_lossage ("invalid operand for code '%c'", code
);
10681 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
10686 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
10687 want to do that. */
10688 if (x
== const_true_rtx
)
10690 output_operand_lossage ("instruction never exectued");
10693 if (!COMPARISON_P (x
))
10695 output_operand_lossage ("invalid operand for code '%c'", code
);
10699 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
10700 (get_arm_condition_code (x
))],
10704 /* Cirrus registers can be accessed in a variety of ways:
10705 single floating point (f)
10706 double floating point (d)
10708 64bit integer (dx). */
10709 case 'W': /* Cirrus register in F mode. */
10710 case 'X': /* Cirrus register in D mode. */
10711 case 'Y': /* Cirrus register in FX mode. */
10712 case 'Z': /* Cirrus register in DX mode. */
10713 gcc_assert (GET_CODE (x
) == REG
10714 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
10716 fprintf (stream
, "mv%s%s",
10718 : code
== 'X' ? "d"
10719 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
10723 /* Print cirrus register in the mode specified by the register's mode. */
10726 int mode
= GET_MODE (x
);
10728 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10730 output_operand_lossage ("invalid operand for code '%c'", code
);
10734 fprintf (stream
, "mv%s%s",
10735 mode
== DFmode
? "d"
10736 : mode
== SImode
? "fx"
10737 : mode
== DImode
? "dx"
10738 : "f", reg_names
[REGNO (x
)] + 2);
10744 if (GET_CODE (x
) != REG
10745 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
10746 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
10747 /* Bad value for wCG register number. */
10749 output_operand_lossage ("invalid operand for code '%c'", code
);
10754 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
10757 /* Print an iWMMXt control register name. */
10759 if (GET_CODE (x
) != CONST_INT
10761 || INTVAL (x
) >= 16)
10762 /* Bad value for wC register number. */
10764 output_operand_lossage ("invalid operand for code '%c'", code
);
10770 static const char * wc_reg_names
[16] =
10772 "wCID", "wCon", "wCSSF", "wCASF",
10773 "wC4", "wC5", "wC6", "wC7",
10774 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10775 "wC12", "wC13", "wC14", "wC15"
10778 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
10782 /* Print a VFP double precision register name. */
10785 int mode
= GET_MODE (x
);
10788 if (mode
!= DImode
&& mode
!= DFmode
)
10790 output_operand_lossage ("invalid operand for code '%c'", code
);
10794 if (GET_CODE (x
) != REG
10795 || !IS_VFP_REGNUM (REGNO (x
)))
10797 output_operand_lossage ("invalid operand for code '%c'", code
);
10801 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
10804 output_operand_lossage ("invalid operand for code '%c'", code
);
10808 fprintf (stream
, "d%d", num
>> 1);
10815 output_operand_lossage ("missing operand");
10819 switch (GET_CODE (x
))
10822 asm_fprintf (stream
, "%r", REGNO (x
));
10826 output_memory_reference_mode
= GET_MODE (x
);
10827 output_address (XEXP (x
, 0));
10831 fprintf (stream
, "#%s", fp_immediate_constant (x
));
10835 gcc_assert (GET_CODE (x
) != NEG
);
10836 fputc ('#', stream
);
10837 output_addr_const (stream
, x
);
10843 #ifndef AOF_ASSEMBLER
10844 /* Target hook for assembling integer objects. The ARM version needs to
10845 handle word-sized values specially. */
10847 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10849 if (size
== UNITS_PER_WORD
&& aligned_p
)
10851 fputs ("\t.word\t", asm_out_file
);
10852 output_addr_const (asm_out_file
, x
);
10854 /* Mark symbols as position independent. We only do this in the
10855 .text segment, not in the .data segment. */
10856 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
10857 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
10859 if (GET_CODE (x
) == SYMBOL_REF
10860 && (CONSTANT_POOL_ADDRESS_P (x
)
10861 || SYMBOL_REF_LOCAL_P (x
)))
10862 fputs ("(GOTOFF)", asm_out_file
);
10863 else if (GET_CODE (x
) == LABEL_REF
)
10864 fputs ("(GOTOFF)", asm_out_file
);
10866 fputs ("(GOT)", asm_out_file
);
10868 fputc ('\n', asm_out_file
);
10872 if (arm_vector_mode_supported_p (GET_MODE (x
)))
10876 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
10878 units
= CONST_VECTOR_NUNITS (x
);
10880 switch (GET_MODE (x
))
10882 case V2SImode
: size
= 4; break;
10883 case V4HImode
: size
= 2; break;
10884 case V8QImode
: size
= 1; break;
10886 gcc_unreachable ();
10889 for (i
= 0; i
< units
; i
++)
10893 elt
= CONST_VECTOR_ELT (x
, i
);
10895 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
10901 return default_assemble_integer (x
, size
, aligned_p
);
10905 /* Add a function to the list of static constructors. */
10908 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
10910 if (!TARGET_AAPCS_BASED
)
10912 default_named_section_asm_out_constructor (symbol
, priority
);
10916 /* Put these in the .init_array section, using a special relocation. */
10918 assemble_align (POINTER_SIZE
);
10919 fputs ("\t.word\t", asm_out_file
);
10920 output_addr_const (asm_out_file
, symbol
);
10921 fputs ("(target1)\n", asm_out_file
);
10925 /* A finite state machine takes care of noticing whether or not instructions
10926 can be conditionally executed, and thus decrease execution time and code
10927 size by deleting branch instructions. The fsm is controlled by
10928 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10930 /* The state of the fsm controlling condition codes are:
10931 0: normal, do nothing special
10932 1: make ASM_OUTPUT_OPCODE not output this instruction
10933 2: make ASM_OUTPUT_OPCODE not output this instruction
10934 3: make instructions conditional
10935 4: make instructions conditional
10937 State transitions (state->state by whom under condition):
10938 0 -> 1 final_prescan_insn if the `target' is a label
10939 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10940 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10941 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10942 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10943 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10944 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10945 (the target insn is arm_target_insn).
10947 If the jump clobbers the conditions then we use states 2 and 4.
10949 A similar thing can be done with conditional return insns.
10951 XXX In case the `target' is an unconditional branch, this conditionalising
10952 of the instructions always reduces code size, but not always execution
10953 time. But then, I want to reduce the code size to somewhere near what
10954 /bin/cc produces. */
10956 /* Returns the index of the ARM condition code string in
10957 `arm_condition_codes'. COMPARISON should be an rtx like
10958 `(eq (...) (...))'. */
10959 static enum arm_cond_code
10960 get_arm_condition_code (rtx comparison
)
10962 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
10964 enum rtx_code comp_code
= GET_CODE (comparison
);
10966 if (GET_MODE_CLASS (mode
) != MODE_CC
)
10967 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
10968 XEXP (comparison
, 1));
10972 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
10973 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
10974 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
10975 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
10976 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
10977 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
10978 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
10979 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
10980 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
10981 case CC_DLTUmode
: code
= ARM_CC
;
10984 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
10986 if (comp_code
== EQ
)
10987 return ARM_INVERSE_CONDITION_CODE (code
);
10993 case NE
: return ARM_NE
;
10994 case EQ
: return ARM_EQ
;
10995 case GE
: return ARM_PL
;
10996 case LT
: return ARM_MI
;
10997 default: gcc_unreachable ();
11003 case NE
: return ARM_NE
;
11004 case EQ
: return ARM_EQ
;
11005 default: gcc_unreachable ();
11011 case NE
: return ARM_MI
;
11012 case EQ
: return ARM_PL
;
11013 default: gcc_unreachable ();
11018 /* These encodings assume that AC=1 in the FPA system control
11019 byte. This allows us to handle all cases except UNEQ and
11023 case GE
: return ARM_GE
;
11024 case GT
: return ARM_GT
;
11025 case LE
: return ARM_LS
;
11026 case LT
: return ARM_MI
;
11027 case NE
: return ARM_NE
;
11028 case EQ
: return ARM_EQ
;
11029 case ORDERED
: return ARM_VC
;
11030 case UNORDERED
: return ARM_VS
;
11031 case UNLT
: return ARM_LT
;
11032 case UNLE
: return ARM_LE
;
11033 case UNGT
: return ARM_HI
;
11034 case UNGE
: return ARM_PL
;
11035 /* UNEQ and LTGT do not have a representation. */
11036 case UNEQ
: /* Fall through. */
11037 case LTGT
: /* Fall through. */
11038 default: gcc_unreachable ();
11044 case NE
: return ARM_NE
;
11045 case EQ
: return ARM_EQ
;
11046 case GE
: return ARM_LE
;
11047 case GT
: return ARM_LT
;
11048 case LE
: return ARM_GE
;
11049 case LT
: return ARM_GT
;
11050 case GEU
: return ARM_LS
;
11051 case GTU
: return ARM_CC
;
11052 case LEU
: return ARM_CS
;
11053 case LTU
: return ARM_HI
;
11054 default: gcc_unreachable ();
11060 case LTU
: return ARM_CS
;
11061 case GEU
: return ARM_CC
;
11062 default: gcc_unreachable ();
11068 case NE
: return ARM_NE
;
11069 case EQ
: return ARM_EQ
;
11070 case GE
: return ARM_GE
;
11071 case GT
: return ARM_GT
;
11072 case LE
: return ARM_LE
;
11073 case LT
: return ARM_LT
;
11074 case GEU
: return ARM_CS
;
11075 case GTU
: return ARM_HI
;
11076 case LEU
: return ARM_LS
;
11077 case LTU
: return ARM_CC
;
11078 default: gcc_unreachable ();
11081 default: gcc_unreachable ();
11086 arm_final_prescan_insn (rtx insn
)
11088 /* BODY will hold the body of INSN. */
11089 rtx body
= PATTERN (insn
);
11091 /* This will be 1 if trying to repeat the trick, and things need to be
11092 reversed if it appears to fail. */
11095 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11096 taken are clobbered, even if the rtl suggests otherwise. It also
11097 means that we have to grub around within the jump expression to find
11098 out what the conditions are when the jump isn't taken. */
11099 int jump_clobbers
= 0;
11101 /* If we start with a return insn, we only succeed if we find another one. */
11102 int seeking_return
= 0;
11104 /* START_INSN will hold the insn from where we start looking. This is the
11105 first insn after the following code_label if REVERSE is true. */
11106 rtx start_insn
= insn
;
11108 /* If in state 4, check if the target branch is reached, in order to
11109 change back to state 0. */
11110 if (arm_ccfsm_state
== 4)
11112 if (insn
== arm_target_insn
)
11114 arm_target_insn
= NULL
;
11115 arm_ccfsm_state
= 0;
11120 /* If in state 3, it is possible to repeat the trick, if this insn is an
11121 unconditional branch to a label, and immediately following this branch
11122 is the previous target label which is only used once, and the label this
11123 branch jumps to is not too far off. */
11124 if (arm_ccfsm_state
== 3)
11126 if (simplejump_p (insn
))
11128 start_insn
= next_nonnote_insn (start_insn
);
11129 if (GET_CODE (start_insn
) == BARRIER
)
11131 /* XXX Isn't this always a barrier? */
11132 start_insn
= next_nonnote_insn (start_insn
);
11134 if (GET_CODE (start_insn
) == CODE_LABEL
11135 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11136 && LABEL_NUSES (start_insn
) == 1)
11141 else if (GET_CODE (body
) == RETURN
)
11143 start_insn
= next_nonnote_insn (start_insn
);
11144 if (GET_CODE (start_insn
) == BARRIER
)
11145 start_insn
= next_nonnote_insn (start_insn
);
11146 if (GET_CODE (start_insn
) == CODE_LABEL
11147 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11148 && LABEL_NUSES (start_insn
) == 1)
11151 seeking_return
= 1;
11160 gcc_assert (!arm_ccfsm_state
|| reverse
);
11161 if (GET_CODE (insn
) != JUMP_INSN
)
11164 /* This jump might be paralleled with a clobber of the condition codes
11165 the jump should always come first */
11166 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11167 body
= XVECEXP (body
, 0, 0);
11170 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11171 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11174 int fail
= FALSE
, succeed
= FALSE
;
11175 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11176 int then_not_else
= TRUE
;
11177 rtx this_insn
= start_insn
, label
= 0;
11179 /* If the jump cannot be done with one instruction, we cannot
11180 conditionally execute the instruction in the inverse case. */
11181 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11187 /* Register the insn jumped to. */
11190 if (!seeking_return
)
11191 label
= XEXP (SET_SRC (body
), 0);
11193 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11194 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11195 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11197 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11198 then_not_else
= FALSE
;
11200 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11201 seeking_return
= 1;
11202 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11204 seeking_return
= 1;
11205 then_not_else
= FALSE
;
11208 gcc_unreachable ();
11210 /* See how many insns this branch skips, and what kind of insns. If all
11211 insns are okay, and the label or unconditional branch to the same
11212 label is not too far away, succeed. */
11213 for (insns_skipped
= 0;
11214 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11218 this_insn
= next_nonnote_insn (this_insn
);
11222 switch (GET_CODE (this_insn
))
11225 /* Succeed if it is the target label, otherwise fail since
11226 control falls in from somewhere else. */
11227 if (this_insn
== label
)
11231 arm_ccfsm_state
= 2;
11232 this_insn
= next_nonnote_insn (this_insn
);
11235 arm_ccfsm_state
= 1;
11243 /* Succeed if the following insn is the target label.
11245 If return insns are used then the last insn in a function
11246 will be a barrier. */
11247 this_insn
= next_nonnote_insn (this_insn
);
11248 if (this_insn
&& this_insn
== label
)
11252 arm_ccfsm_state
= 2;
11253 this_insn
= next_nonnote_insn (this_insn
);
11256 arm_ccfsm_state
= 1;
11264 /* The AAPCS says that conditional calls should not be
11265 used since they make interworking inefficient (the
11266 linker can't transform BL<cond> into BLX). That's
11267 only a problem if the machine has BLX. */
11274 /* Succeed if the following insn is the target label, or
11275 if the following two insns are a barrier and the
11277 this_insn
= next_nonnote_insn (this_insn
);
11278 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11279 this_insn
= next_nonnote_insn (this_insn
);
11281 if (this_insn
&& this_insn
== label
11282 && insns_skipped
< max_insns_skipped
)
11286 arm_ccfsm_state
= 2;
11287 this_insn
= next_nonnote_insn (this_insn
);
11290 arm_ccfsm_state
= 1;
11298 /* If this is an unconditional branch to the same label, succeed.
11299 If it is to another label, do nothing. If it is conditional,
11301 /* XXX Probably, the tests for SET and the PC are
11304 scanbody
= PATTERN (this_insn
);
11305 if (GET_CODE (scanbody
) == SET
11306 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11308 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11309 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11311 arm_ccfsm_state
= 2;
11314 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11317 /* Fail if a conditional return is undesirable (e.g. on a
11318 StrongARM), but still allow this if optimizing for size. */
11319 else if (GET_CODE (scanbody
) == RETURN
11320 && !use_return_insn (TRUE
, NULL
)
11323 else if (GET_CODE (scanbody
) == RETURN
11326 arm_ccfsm_state
= 2;
11329 else if (GET_CODE (scanbody
) == PARALLEL
)
11331 switch (get_attr_conds (this_insn
))
11341 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11346 /* Instructions using or affecting the condition codes make it
11348 scanbody
= PATTERN (this_insn
);
11349 if (!(GET_CODE (scanbody
) == SET
11350 || GET_CODE (scanbody
) == PARALLEL
)
11351 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11354 /* A conditional cirrus instruction must be followed by
11355 a non Cirrus instruction. However, since we
11356 conditionalize instructions in this function and by
11357 the time we get here we can't add instructions
11358 (nops), because shorten_branches() has already been
11359 called, we will disable conditionalizing Cirrus
11360 instructions to be safe. */
11361 if (GET_CODE (scanbody
) != USE
11362 && GET_CODE (scanbody
) != CLOBBER
11363 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11373 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11374 arm_target_label
= CODE_LABEL_NUMBER (label
);
11377 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11379 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11381 this_insn
= next_nonnote_insn (this_insn
);
11382 gcc_assert (!this_insn
11383 || (GET_CODE (this_insn
) != BARRIER
11384 && GET_CODE (this_insn
) != CODE_LABEL
));
11388 /* Oh, dear! we ran off the end.. give up. */
11389 recog (PATTERN (insn
), insn
, NULL
);
11390 arm_ccfsm_state
= 0;
11391 arm_target_insn
= NULL
;
11394 arm_target_insn
= this_insn
;
11398 gcc_assert (!reverse
);
11400 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11402 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11403 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11404 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11405 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11409 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11412 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11416 if (reverse
|| then_not_else
)
11417 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11420 /* Restore recog_data (getting the attributes of other insns can
11421 destroy this array, but final.c assumes that it remains intact
11422 across this call; since the insn has been recognized already we
11423 call recog direct). */
11424 recog (PATTERN (insn
), insn
, NULL
);
11428 /* Returns true if REGNO is a valid register
11429 for holding a quantity of type MODE. */
11431 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11433 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11434 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11437 /* For the Thumb we only allow values bigger than SImode in
11438 registers 0 - 6, so that there is always a second low
11439 register available to hold the upper part of the value.
11440 We probably we ought to ensure that the register is the
11441 start of an even numbered register pair. */
11442 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11444 if (IS_CIRRUS_REGNUM (regno
))
11445 /* We have outlawed SI values in Cirrus registers because they
11446 reside in the lower 32 bits, but SF values reside in the
11447 upper 32 bits. This causes gcc all sorts of grief. We can't
11448 even split the registers into pairs because Cirrus SI values
11449 get sign extended to 64bits-- aldyh. */
11450 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11452 if (IS_VFP_REGNUM (regno
))
11454 if (mode
== SFmode
|| mode
== SImode
)
11457 /* DFmode values are only valid in even register pairs. */
11458 if (mode
== DFmode
)
11459 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11463 if (IS_IWMMXT_GR_REGNUM (regno
))
11464 return mode
== SImode
;
11466 if (IS_IWMMXT_REGNUM (regno
))
11467 return VALID_IWMMXT_REG_MODE (mode
);
11469 /* We allow any value to be stored in the general registers.
11470 Restrict doubleword quantities to even register pairs so that we can
11472 if (regno
<= LAST_ARM_REGNUM
)
11473 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11475 if ( regno
== FRAME_POINTER_REGNUM
11476 || regno
== ARG_POINTER_REGNUM
)
11477 /* We only allow integers in the fake hard registers. */
11478 return GET_MODE_CLASS (mode
) == MODE_INT
;
11480 /* The only registers left are the FPA registers
11481 which we only allow to hold FP values. */
11482 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11483 && regno
>= FIRST_FPA_REGNUM
11484 && regno
<= LAST_FPA_REGNUM
;
11488 arm_regno_class (int regno
)
11492 if (regno
== STACK_POINTER_REGNUM
)
11494 if (regno
== CC_REGNUM
)
11501 if ( regno
<= LAST_ARM_REGNUM
11502 || regno
== FRAME_POINTER_REGNUM
11503 || regno
== ARG_POINTER_REGNUM
)
11504 return GENERAL_REGS
;
11506 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11509 if (IS_CIRRUS_REGNUM (regno
))
11510 return CIRRUS_REGS
;
11512 if (IS_VFP_REGNUM (regno
))
11515 if (IS_IWMMXT_REGNUM (regno
))
11516 return IWMMXT_REGS
;
11518 if (IS_IWMMXT_GR_REGNUM (regno
))
11519 return IWMMXT_GR_REGS
;
11524 /* Handle a special case when computing the offset
11525 of an argument from the frame pointer. */
11527 arm_debugger_arg_offset (int value
, rtx addr
)
11531 /* We are only interested if dbxout_parms() failed to compute the offset. */
11535 /* We can only cope with the case where the address is held in a register. */
11536 if (GET_CODE (addr
) != REG
)
11539 /* If we are using the frame pointer to point at the argument, then
11540 an offset of 0 is correct. */
11541 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11544 /* If we are using the stack pointer to point at the
11545 argument, then an offset of 0 is correct. */
11546 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11547 && REGNO (addr
) == SP_REGNUM
)
11550 /* Oh dear. The argument is pointed to by a register rather
11551 than being held in a register, or being stored at a known
11552 offset from the frame pointer. Since GDB only understands
11553 those two kinds of argument we must translate the address
11554 held in the register into an offset from the frame pointer.
11555 We do this by searching through the insns for the function
11556 looking to see where this register gets its value. If the
11557 register is initialized from the frame pointer plus an offset
11558 then we are in luck and we can continue, otherwise we give up.
11560 This code is exercised by producing debugging information
11561 for a function with arguments like this:
11563 double func (double a, double b, int c, double d) {return d;}
11565 Without this code the stab for parameter 'd' will be set to
11566 an offset of 0 from the frame pointer, rather than 8. */
11568 /* The if() statement says:
11570 If the insn is a normal instruction
11571 and if the insn is setting the value in a register
11572 and if the register being set is the register holding the address of the argument
11573 and if the address is computing by an addition
11574 that involves adding to a register
11575 which is the frame pointer
11580 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11582 if ( GET_CODE (insn
) == INSN
11583 && GET_CODE (PATTERN (insn
)) == SET
11584 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11585 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11586 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11587 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11588 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11591 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11600 warning (0, "unable to compute real location of stacked parameter");
11601 value
= 8; /* XXX magic hack */
11607 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11610 if ((MASK) & insn_flags) \
11611 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11612 BUILT_IN_MD, NULL, NULL_TREE); \
11616 struct builtin_description
11618 const unsigned int mask
;
11619 const enum insn_code icode
;
11620 const char * const name
;
11621 const enum arm_builtins code
;
11622 const enum rtx_code comparison
;
11623 const unsigned int flag
;
11626 static const struct builtin_description bdesc_2arg
[] =
11628 #define IWMMXT_BUILTIN(code, string, builtin) \
11629 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11630 ARM_BUILTIN_##builtin, 0, 0 },
11632 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
11633 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
11634 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
11635 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
11636 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
11637 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
11638 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
11639 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
11640 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
11641 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
11642 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
11643 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
11644 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
11645 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
11646 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
11647 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
11648 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
11649 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
11650 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
11651 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
11652 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
11653 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
11654 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
11655 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
11656 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
11657 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
11658 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
11659 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
11660 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
11661 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
11662 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
11663 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
11664 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
11665 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
11666 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
11667 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
11668 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
11669 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
11670 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
11671 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
11672 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
11673 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
11674 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
11675 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
11676 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
11677 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
11678 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
11679 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
11680 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
11681 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
11682 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
11683 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
11684 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
11685 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
11686 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
11687 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
11688 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
11689 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
11691 #define IWMMXT_BUILTIN2(code, builtin) \
11692 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11694 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
11695 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
11696 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
11697 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
11698 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
11699 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
11700 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
11701 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
11702 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
11703 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
11704 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
11705 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
11706 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
11707 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
11708 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
11709 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
11710 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
11711 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
11712 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
11713 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
11714 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
11715 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
11716 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
11717 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
11718 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
11719 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
11720 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
11721 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
11722 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
11723 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
11724 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
11725 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
11728 static const struct builtin_description bdesc_1arg
[] =
11730 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
11731 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
11732 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
11733 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
11734 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
11735 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
11736 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
11737 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
11738 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
11739 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
11740 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
11741 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
11742 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
11743 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
11744 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
11745 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
11746 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
11747 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
11750 /* Set up all the iWMMXt builtins. This is
11751 not called if TARGET_IWMMXT is zero. */
11754 arm_init_iwmmxt_builtins (void)
11756 const struct builtin_description
* d
;
11758 tree endlink
= void_list_node
;
11760 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
11761 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
11762 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
11765 = build_function_type (integer_type_node
,
11766 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
11767 tree v8qi_ftype_v8qi_v8qi_int
11768 = build_function_type (V8QI_type_node
,
11769 tree_cons (NULL_TREE
, V8QI_type_node
,
11770 tree_cons (NULL_TREE
, V8QI_type_node
,
11771 tree_cons (NULL_TREE
,
11774 tree v4hi_ftype_v4hi_int
11775 = build_function_type (V4HI_type_node
,
11776 tree_cons (NULL_TREE
, V4HI_type_node
,
11777 tree_cons (NULL_TREE
, integer_type_node
,
11779 tree v2si_ftype_v2si_int
11780 = build_function_type (V2SI_type_node
,
11781 tree_cons (NULL_TREE
, V2SI_type_node
,
11782 tree_cons (NULL_TREE
, integer_type_node
,
11784 tree v2si_ftype_di_di
11785 = build_function_type (V2SI_type_node
,
11786 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11787 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11789 tree di_ftype_di_int
11790 = build_function_type (long_long_integer_type_node
,
11791 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11792 tree_cons (NULL_TREE
, integer_type_node
,
11794 tree di_ftype_di_int_int
11795 = build_function_type (long_long_integer_type_node
,
11796 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11797 tree_cons (NULL_TREE
, integer_type_node
,
11798 tree_cons (NULL_TREE
,
11801 tree int_ftype_v8qi
11802 = build_function_type (integer_type_node
,
11803 tree_cons (NULL_TREE
, V8QI_type_node
,
11805 tree int_ftype_v4hi
11806 = build_function_type (integer_type_node
,
11807 tree_cons (NULL_TREE
, V4HI_type_node
,
11809 tree int_ftype_v2si
11810 = build_function_type (integer_type_node
,
11811 tree_cons (NULL_TREE
, V2SI_type_node
,
11813 tree int_ftype_v8qi_int
11814 = build_function_type (integer_type_node
,
11815 tree_cons (NULL_TREE
, V8QI_type_node
,
11816 tree_cons (NULL_TREE
, integer_type_node
,
11818 tree int_ftype_v4hi_int
11819 = build_function_type (integer_type_node
,
11820 tree_cons (NULL_TREE
, V4HI_type_node
,
11821 tree_cons (NULL_TREE
, integer_type_node
,
11823 tree int_ftype_v2si_int
11824 = build_function_type (integer_type_node
,
11825 tree_cons (NULL_TREE
, V2SI_type_node
,
11826 tree_cons (NULL_TREE
, integer_type_node
,
11828 tree v8qi_ftype_v8qi_int_int
11829 = build_function_type (V8QI_type_node
,
11830 tree_cons (NULL_TREE
, V8QI_type_node
,
11831 tree_cons (NULL_TREE
, integer_type_node
,
11832 tree_cons (NULL_TREE
,
11835 tree v4hi_ftype_v4hi_int_int
11836 = build_function_type (V4HI_type_node
,
11837 tree_cons (NULL_TREE
, V4HI_type_node
,
11838 tree_cons (NULL_TREE
, integer_type_node
,
11839 tree_cons (NULL_TREE
,
11842 tree v2si_ftype_v2si_int_int
11843 = build_function_type (V2SI_type_node
,
11844 tree_cons (NULL_TREE
, V2SI_type_node
,
11845 tree_cons (NULL_TREE
, integer_type_node
,
11846 tree_cons (NULL_TREE
,
11849 /* Miscellaneous. */
11850 tree v8qi_ftype_v4hi_v4hi
11851 = build_function_type (V8QI_type_node
,
11852 tree_cons (NULL_TREE
, V4HI_type_node
,
11853 tree_cons (NULL_TREE
, V4HI_type_node
,
11855 tree v4hi_ftype_v2si_v2si
11856 = build_function_type (V4HI_type_node
,
11857 tree_cons (NULL_TREE
, V2SI_type_node
,
11858 tree_cons (NULL_TREE
, V2SI_type_node
,
11860 tree v2si_ftype_v4hi_v4hi
11861 = build_function_type (V2SI_type_node
,
11862 tree_cons (NULL_TREE
, V4HI_type_node
,
11863 tree_cons (NULL_TREE
, V4HI_type_node
,
11865 tree v2si_ftype_v8qi_v8qi
11866 = build_function_type (V2SI_type_node
,
11867 tree_cons (NULL_TREE
, V8QI_type_node
,
11868 tree_cons (NULL_TREE
, V8QI_type_node
,
11870 tree v4hi_ftype_v4hi_di
11871 = build_function_type (V4HI_type_node
,
11872 tree_cons (NULL_TREE
, V4HI_type_node
,
11873 tree_cons (NULL_TREE
,
11874 long_long_integer_type_node
,
11876 tree v2si_ftype_v2si_di
11877 = build_function_type (V2SI_type_node
,
11878 tree_cons (NULL_TREE
, V2SI_type_node
,
11879 tree_cons (NULL_TREE
,
11880 long_long_integer_type_node
,
11882 tree void_ftype_int_int
11883 = build_function_type (void_type_node
,
11884 tree_cons (NULL_TREE
, integer_type_node
,
11885 tree_cons (NULL_TREE
, integer_type_node
,
11888 = build_function_type (long_long_unsigned_type_node
, endlink
);
11890 = build_function_type (long_long_integer_type_node
,
11891 tree_cons (NULL_TREE
, V8QI_type_node
,
11894 = build_function_type (long_long_integer_type_node
,
11895 tree_cons (NULL_TREE
, V4HI_type_node
,
11898 = build_function_type (long_long_integer_type_node
,
11899 tree_cons (NULL_TREE
, V2SI_type_node
,
11901 tree v2si_ftype_v4hi
11902 = build_function_type (V2SI_type_node
,
11903 tree_cons (NULL_TREE
, V4HI_type_node
,
11905 tree v4hi_ftype_v8qi
11906 = build_function_type (V4HI_type_node
,
11907 tree_cons (NULL_TREE
, V8QI_type_node
,
11910 tree di_ftype_di_v4hi_v4hi
11911 = build_function_type (long_long_unsigned_type_node
,
11912 tree_cons (NULL_TREE
,
11913 long_long_unsigned_type_node
,
11914 tree_cons (NULL_TREE
, V4HI_type_node
,
11915 tree_cons (NULL_TREE
,
11919 tree di_ftype_v4hi_v4hi
11920 = build_function_type (long_long_unsigned_type_node
,
11921 tree_cons (NULL_TREE
, V4HI_type_node
,
11922 tree_cons (NULL_TREE
, V4HI_type_node
,
11925 /* Normal vector binops. */
11926 tree v8qi_ftype_v8qi_v8qi
11927 = build_function_type (V8QI_type_node
,
11928 tree_cons (NULL_TREE
, V8QI_type_node
,
11929 tree_cons (NULL_TREE
, V8QI_type_node
,
11931 tree v4hi_ftype_v4hi_v4hi
11932 = build_function_type (V4HI_type_node
,
11933 tree_cons (NULL_TREE
, V4HI_type_node
,
11934 tree_cons (NULL_TREE
, V4HI_type_node
,
11936 tree v2si_ftype_v2si_v2si
11937 = build_function_type (V2SI_type_node
,
11938 tree_cons (NULL_TREE
, V2SI_type_node
,
11939 tree_cons (NULL_TREE
, V2SI_type_node
,
11941 tree di_ftype_di_di
11942 = build_function_type (long_long_unsigned_type_node
,
11943 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
11944 tree_cons (NULL_TREE
,
11945 long_long_unsigned_type_node
,
11948 /* Add all builtins that are more or less simple operations on two
11950 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11952 /* Use one of the operands; the target can have a different mode for
11953 mask-generating compares. */
11954 enum machine_mode mode
;
11960 mode
= insn_data
[d
->icode
].operand
[1].mode
;
11965 type
= v8qi_ftype_v8qi_v8qi
;
11968 type
= v4hi_ftype_v4hi_v4hi
;
11971 type
= v2si_ftype_v2si_v2si
;
11974 type
= di_ftype_di_di
;
11978 gcc_unreachable ();
11981 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
11984 /* Add the remaining MMX insns with somewhat more complicated types. */
11985 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
11986 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
11987 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
11989 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
11990 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
11991 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
11992 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
11993 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
11994 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
11996 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
11997 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
11998 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
11999 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12000 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12001 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12003 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12004 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12005 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12006 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12007 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12008 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12010 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12011 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12012 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12013 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12014 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12015 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12017 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12019 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12020 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12021 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12022 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12024 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12025 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12026 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12027 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12028 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12029 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12030 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12031 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12032 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12034 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12035 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12036 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12038 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12039 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12040 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12042 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12043 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12044 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12045 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12046 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12047 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12049 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12050 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12051 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12052 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12053 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12054 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12055 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12056 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12057 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12058 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12059 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12060 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12062 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12063 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12064 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12065 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12067 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12068 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12069 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12070 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12071 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12072 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12073 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12077 arm_init_builtins (void)
12079 if (TARGET_REALLY_IWMMXT
)
12080 arm_init_iwmmxt_builtins ();
12083 /* Errors in the source file can cause expand_expr to return const0_rtx
12084 where we expect a vector. To avoid crashing, use one of the vector
12085 clear instructions. */
12088 safe_vector_operand (rtx x
, enum machine_mode mode
)
12090 if (x
!= const0_rtx
)
12092 x
= gen_reg_rtx (mode
);
12094 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12095 : gen_rtx_SUBREG (DImode
, x
, 0)));
12099 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12102 arm_expand_binop_builtin (enum insn_code icode
,
12103 tree arglist
, rtx target
)
12106 tree arg0
= TREE_VALUE (arglist
);
12107 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12108 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12109 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12110 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12111 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12112 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12114 if (VECTOR_MODE_P (mode0
))
12115 op0
= safe_vector_operand (op0
, mode0
);
12116 if (VECTOR_MODE_P (mode1
))
12117 op1
= safe_vector_operand (op1
, mode1
);
12120 || GET_MODE (target
) != tmode
12121 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12122 target
= gen_reg_rtx (tmode
);
12124 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12126 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12127 op0
= copy_to_mode_reg (mode0
, op0
);
12128 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12129 op1
= copy_to_mode_reg (mode1
, op1
);
12131 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12138 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12141 arm_expand_unop_builtin (enum insn_code icode
,
12142 tree arglist
, rtx target
, int do_load
)
12145 tree arg0
= TREE_VALUE (arglist
);
12146 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12147 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12148 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12151 || GET_MODE (target
) != tmode
12152 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12153 target
= gen_reg_rtx (tmode
);
12155 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12158 if (VECTOR_MODE_P (mode0
))
12159 op0
= safe_vector_operand (op0
, mode0
);
12161 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12162 op0
= copy_to_mode_reg (mode0
, op0
);
12165 pat
= GEN_FCN (icode
) (target
, op0
);
12172 /* Expand an expression EXP that calls a built-in function,
12173 with result going to TARGET if that's convenient
12174 (and in mode MODE if that's convenient).
12175 SUBTARGET may be used as the target for computing one of EXP's operands.
12176 IGNORE is nonzero if the value is to be ignored. */
12179 arm_expand_builtin (tree exp
,
12181 rtx subtarget ATTRIBUTE_UNUSED
,
12182 enum machine_mode mode ATTRIBUTE_UNUSED
,
12183 int ignore ATTRIBUTE_UNUSED
)
12185 const struct builtin_description
* d
;
12186 enum insn_code icode
;
12187 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12188 tree arglist
= TREE_OPERAND (exp
, 1);
12196 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12198 enum machine_mode tmode
;
12199 enum machine_mode mode0
;
12200 enum machine_mode mode1
;
12201 enum machine_mode mode2
;
12205 case ARM_BUILTIN_TEXTRMSB
:
12206 case ARM_BUILTIN_TEXTRMUB
:
12207 case ARM_BUILTIN_TEXTRMSH
:
12208 case ARM_BUILTIN_TEXTRMUH
:
12209 case ARM_BUILTIN_TEXTRMSW
:
12210 case ARM_BUILTIN_TEXTRMUW
:
12211 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12212 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12213 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12214 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12215 : CODE_FOR_iwmmxt_textrmw
);
12217 arg0
= TREE_VALUE (arglist
);
12218 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12219 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12220 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12221 tmode
= insn_data
[icode
].operand
[0].mode
;
12222 mode0
= insn_data
[icode
].operand
[1].mode
;
12223 mode1
= insn_data
[icode
].operand
[2].mode
;
12225 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12226 op0
= copy_to_mode_reg (mode0
, op0
);
12227 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12229 /* @@@ better error message */
12230 error ("selector must be an immediate");
12231 return gen_reg_rtx (tmode
);
12234 || GET_MODE (target
) != tmode
12235 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12236 target
= gen_reg_rtx (tmode
);
12237 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12243 case ARM_BUILTIN_TINSRB
:
12244 case ARM_BUILTIN_TINSRH
:
12245 case ARM_BUILTIN_TINSRW
:
12246 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12247 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12248 : CODE_FOR_iwmmxt_tinsrw
);
12249 arg0
= TREE_VALUE (arglist
);
12250 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12251 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12252 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12253 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12254 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12255 tmode
= insn_data
[icode
].operand
[0].mode
;
12256 mode0
= insn_data
[icode
].operand
[1].mode
;
12257 mode1
= insn_data
[icode
].operand
[2].mode
;
12258 mode2
= insn_data
[icode
].operand
[3].mode
;
12260 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12261 op0
= copy_to_mode_reg (mode0
, op0
);
12262 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12263 op1
= copy_to_mode_reg (mode1
, op1
);
12264 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12266 /* @@@ better error message */
12267 error ("selector must be an immediate");
12271 || GET_MODE (target
) != tmode
12272 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12273 target
= gen_reg_rtx (tmode
);
12274 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12280 case ARM_BUILTIN_SETWCX
:
12281 arg0
= TREE_VALUE (arglist
);
12282 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12283 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12284 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12285 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12288 case ARM_BUILTIN_GETWCX
:
12289 arg0
= TREE_VALUE (arglist
);
12290 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12291 target
= gen_reg_rtx (SImode
);
12292 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12295 case ARM_BUILTIN_WSHUFH
:
12296 icode
= CODE_FOR_iwmmxt_wshufh
;
12297 arg0
= TREE_VALUE (arglist
);
12298 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12299 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12300 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12301 tmode
= insn_data
[icode
].operand
[0].mode
;
12302 mode1
= insn_data
[icode
].operand
[1].mode
;
12303 mode2
= insn_data
[icode
].operand
[2].mode
;
12305 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12306 op0
= copy_to_mode_reg (mode1
, op0
);
12307 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12309 /* @@@ better error message */
12310 error ("mask must be an immediate");
12314 || GET_MODE (target
) != tmode
12315 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12316 target
= gen_reg_rtx (tmode
);
12317 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12323 case ARM_BUILTIN_WSADB
:
12324 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12325 case ARM_BUILTIN_WSADH
:
12326 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12327 case ARM_BUILTIN_WSADBZ
:
12328 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12329 case ARM_BUILTIN_WSADHZ
:
12330 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12332 /* Several three-argument builtins. */
12333 case ARM_BUILTIN_WMACS
:
12334 case ARM_BUILTIN_WMACU
:
12335 case ARM_BUILTIN_WALIGN
:
12336 case ARM_BUILTIN_TMIA
:
12337 case ARM_BUILTIN_TMIAPH
:
12338 case ARM_BUILTIN_TMIATT
:
12339 case ARM_BUILTIN_TMIATB
:
12340 case ARM_BUILTIN_TMIABT
:
12341 case ARM_BUILTIN_TMIABB
:
12342 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12343 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12344 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12345 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12346 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12347 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12348 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12349 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12350 : CODE_FOR_iwmmxt_walign
);
12351 arg0
= TREE_VALUE (arglist
);
12352 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12353 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12354 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12355 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12356 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12357 tmode
= insn_data
[icode
].operand
[0].mode
;
12358 mode0
= insn_data
[icode
].operand
[1].mode
;
12359 mode1
= insn_data
[icode
].operand
[2].mode
;
12360 mode2
= insn_data
[icode
].operand
[3].mode
;
12362 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12363 op0
= copy_to_mode_reg (mode0
, op0
);
12364 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12365 op1
= copy_to_mode_reg (mode1
, op1
);
12366 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12367 op2
= copy_to_mode_reg (mode2
, op2
);
12369 || GET_MODE (target
) != tmode
12370 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12371 target
= gen_reg_rtx (tmode
);
12372 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12378 case ARM_BUILTIN_WZERO
:
12379 target
= gen_reg_rtx (DImode
);
12380 emit_insn (gen_iwmmxt_clrdi (target
));
12387 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12388 if (d
->code
== (const enum arm_builtins
) fcode
)
12389 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12391 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12392 if (d
->code
== (const enum arm_builtins
) fcode
)
12393 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12395 /* @@@ Should really do something sensible here. */
12399 /* Return the number (counting from 0) of
12400 the least significant set bit in MASK. */
12403 number_of_first_bit_set (unsigned mask
)
12408 (mask
& (1 << bit
)) == 0;
12415 /* Emit code to push or pop registers to or from the stack. F is the
12416 assembly file. MASK is the registers to push or pop. PUSH is
12417 nonzero if we should push, and zero if we should pop. For debugging
12418 output, if pushing, adjust CFA_OFFSET by the amount of space added
12419 to the stack. REAL_REGS should have the same number of bits set as
12420 MASK, and will be used instead (in the same order) to describe which
12421 registers were saved - this is used to mark the save slots when we
12422 push high registers after moving them to low registers. */
12424 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12425 unsigned long real_regs
)
12428 int lo_mask
= mask
& 0xFF;
12429 int pushed_words
= 0;
12433 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12435 /* Special case. Do not generate a POP PC statement here, do it in
12437 thumb_exit (f
, -1);
12441 if (ARM_EABI_UNWIND_TABLES
&& push
)
12443 fprintf (f
, "\t.save\t{");
12444 for (regno
= 0; regno
< 15; regno
++)
12446 if (real_regs
& (1 << regno
))
12448 if (real_regs
& ((1 << regno
) -1))
12450 asm_fprintf (f
, "%r", regno
);
12453 fprintf (f
, "}\n");
12456 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12458 /* Look at the low registers first. */
12459 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12463 asm_fprintf (f
, "%r", regno
);
12465 if ((lo_mask
& ~1) != 0)
12472 if (push
&& (mask
& (1 << LR_REGNUM
)))
12474 /* Catch pushing the LR. */
12478 asm_fprintf (f
, "%r", LR_REGNUM
);
12482 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12484 /* Catch popping the PC. */
12485 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12486 || current_function_calls_eh_return
)
12488 /* The PC is never poped directly, instead
12489 it is popped into r3 and then BX is used. */
12490 fprintf (f
, "}\n");
12492 thumb_exit (f
, -1);
12501 asm_fprintf (f
, "%r", PC_REGNUM
);
12505 fprintf (f
, "}\n");
12507 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12509 char *l
= dwarf2out_cfi_label ();
12510 int pushed_mask
= real_regs
;
12512 *cfa_offset
+= pushed_words
* 4;
12513 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12516 pushed_mask
= real_regs
;
12517 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12519 if (pushed_mask
& 1)
12520 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12525 /* Generate code to return from a thumb function.
12526 If 'reg_containing_return_addr' is -1, then the return address is
12527 actually on the stack, at the stack pointer. */
12529 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12531 unsigned regs_available_for_popping
;
12532 unsigned regs_to_pop
;
12534 unsigned available
;
12538 int restore_a4
= FALSE
;
12540 /* Compute the registers we need to pop. */
12544 if (reg_containing_return_addr
== -1)
12546 regs_to_pop
|= 1 << LR_REGNUM
;
12550 if (TARGET_BACKTRACE
)
12552 /* Restore the (ARM) frame pointer and stack pointer. */
12553 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12557 /* If there is nothing to pop then just emit the BX instruction and
12559 if (pops_needed
== 0)
12561 if (current_function_calls_eh_return
)
12562 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12564 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12567 /* Otherwise if we are not supporting interworking and we have not created
12568 a backtrace structure and the function was not entered in ARM mode then
12569 just pop the return address straight into the PC. */
12570 else if (!TARGET_INTERWORK
12571 && !TARGET_BACKTRACE
12572 && !is_called_in_ARM_mode (current_function_decl
)
12573 && !current_function_calls_eh_return
)
12575 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12579 /* Find out how many of the (return) argument registers we can corrupt. */
12580 regs_available_for_popping
= 0;
12582 /* If returning via __builtin_eh_return, the bottom three registers
12583 all contain information needed for the return. */
12584 if (current_function_calls_eh_return
)
12588 /* If we can deduce the registers used from the function's
12589 return value. This is more reliable that examining
12590 regs_ever_live[] because that will be set if the register is
12591 ever used in the function, not just if the register is used
12592 to hold a return value. */
12594 if (current_function_return_rtx
!= 0)
12595 mode
= GET_MODE (current_function_return_rtx
);
12597 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12599 size
= GET_MODE_SIZE (mode
);
12603 /* In a void function we can use any argument register.
12604 In a function that returns a structure on the stack
12605 we can use the second and third argument registers. */
12606 if (mode
== VOIDmode
)
12607 regs_available_for_popping
=
12608 (1 << ARG_REGISTER (1))
12609 | (1 << ARG_REGISTER (2))
12610 | (1 << ARG_REGISTER (3));
12612 regs_available_for_popping
=
12613 (1 << ARG_REGISTER (2))
12614 | (1 << ARG_REGISTER (3));
12616 else if (size
<= 4)
12617 regs_available_for_popping
=
12618 (1 << ARG_REGISTER (2))
12619 | (1 << ARG_REGISTER (3));
12620 else if (size
<= 8)
12621 regs_available_for_popping
=
12622 (1 << ARG_REGISTER (3));
12625 /* Match registers to be popped with registers into which we pop them. */
12626 for (available
= regs_available_for_popping
,
12627 required
= regs_to_pop
;
12628 required
!= 0 && available
!= 0;
12629 available
&= ~(available
& - available
),
12630 required
&= ~(required
& - required
))
12633 /* If we have any popping registers left over, remove them. */
12635 regs_available_for_popping
&= ~available
;
12637 /* Otherwise if we need another popping register we can use
12638 the fourth argument register. */
12639 else if (pops_needed
)
12641 /* If we have not found any free argument registers and
12642 reg a4 contains the return address, we must move it. */
12643 if (regs_available_for_popping
== 0
12644 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
12646 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12647 reg_containing_return_addr
= LR_REGNUM
;
12649 else if (size
> 12)
12651 /* Register a4 is being used to hold part of the return value,
12652 but we have dire need of a free, low register. */
12655 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
12658 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
12660 /* The fourth argument register is available. */
12661 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
12667 /* Pop as many registers as we can. */
12668 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12669 regs_available_for_popping
);
12671 /* Process the registers we popped. */
12672 if (reg_containing_return_addr
== -1)
12674 /* The return address was popped into the lowest numbered register. */
12675 regs_to_pop
&= ~(1 << LR_REGNUM
);
12677 reg_containing_return_addr
=
12678 number_of_first_bit_set (regs_available_for_popping
);
12680 /* Remove this register for the mask of available registers, so that
12681 the return address will not be corrupted by further pops. */
12682 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
12685 /* If we popped other registers then handle them here. */
12686 if (regs_available_for_popping
)
12690 /* Work out which register currently contains the frame pointer. */
12691 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12693 /* Move it into the correct place. */
12694 asm_fprintf (f
, "\tmov\t%r, %r\n",
12695 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
12697 /* (Temporarily) remove it from the mask of popped registers. */
12698 regs_available_for_popping
&= ~(1 << frame_pointer
);
12699 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
12701 if (regs_available_for_popping
)
12705 /* We popped the stack pointer as well,
12706 find the register that contains it. */
12707 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12709 /* Move it into the stack register. */
12710 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
12712 /* At this point we have popped all necessary registers, so
12713 do not worry about restoring regs_available_for_popping
12714 to its correct value:
12716 assert (pops_needed == 0)
12717 assert (regs_available_for_popping == (1 << frame_pointer))
12718 assert (regs_to_pop == (1 << STACK_POINTER)) */
12722 /* Since we have just move the popped value into the frame
12723 pointer, the popping register is available for reuse, and
12724 we know that we still have the stack pointer left to pop. */
12725 regs_available_for_popping
|= (1 << frame_pointer
);
12729 /* If we still have registers left on the stack, but we no longer have
12730 any registers into which we can pop them, then we must move the return
12731 address into the link register and make available the register that
12733 if (regs_available_for_popping
== 0 && pops_needed
> 0)
12735 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
12737 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
12738 reg_containing_return_addr
);
12740 reg_containing_return_addr
= LR_REGNUM
;
12743 /* If we have registers left on the stack then pop some more.
12744 We know that at most we will want to pop FP and SP. */
12745 if (pops_needed
> 0)
12750 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12751 regs_available_for_popping
);
12753 /* We have popped either FP or SP.
12754 Move whichever one it is into the correct register. */
12755 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12756 move_to
= number_of_first_bit_set (regs_to_pop
);
12758 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
12760 regs_to_pop
&= ~(1 << move_to
);
12765 /* If we still have not popped everything then we must have only
12766 had one register available to us and we are now popping the SP. */
12767 if (pops_needed
> 0)
12771 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12772 regs_available_for_popping
);
12774 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12776 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
12778 assert (regs_to_pop == (1 << STACK_POINTER))
12779 assert (pops_needed == 1)
12783 /* If necessary restore the a4 register. */
12786 if (reg_containing_return_addr
!= LR_REGNUM
)
12788 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12789 reg_containing_return_addr
= LR_REGNUM
;
12792 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12795 if (current_function_calls_eh_return
)
12796 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12798 /* Return to caller. */
12799 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12804 thumb_final_prescan_insn (rtx insn
)
12806 if (flag_print_asm_name
)
12807 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
12808 INSN_ADDRESSES (INSN_UID (insn
)));
12812 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
12814 unsigned HOST_WIDE_INT mask
= 0xff;
12817 if (val
== 0) /* XXX */
12820 for (i
= 0; i
< 25; i
++)
12821 if ((val
& (mask
<< i
)) == val
)
12827 /* Returns nonzero if the current function contains,
12828 or might contain a far jump. */
12830 thumb_far_jump_used_p (void)
12834 /* This test is only important for leaf functions. */
12835 /* assert (!leaf_function_p ()); */
12837 /* If we have already decided that far jumps may be used,
12838 do not bother checking again, and always return true even if
12839 it turns out that they are not being used. Once we have made
12840 the decision that far jumps are present (and that hence the link
12841 register will be pushed onto the stack) we cannot go back on it. */
12842 if (cfun
->machine
->far_jump_used
)
12845 /* If this function is not being called from the prologue/epilogue
12846 generation code then it must be being called from the
12847 INITIAL_ELIMINATION_OFFSET macro. */
12848 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
12850 /* In this case we know that we are being asked about the elimination
12851 of the arg pointer register. If that register is not being used,
12852 then there are no arguments on the stack, and we do not have to
12853 worry that a far jump might force the prologue to push the link
12854 register, changing the stack offsets. In this case we can just
12855 return false, since the presence of far jumps in the function will
12856 not affect stack offsets.
12858 If the arg pointer is live (or if it was live, but has now been
12859 eliminated and so set to dead) then we do have to test to see if
12860 the function might contain a far jump. This test can lead to some
12861 false negatives, since before reload is completed, then length of
12862 branch instructions is not known, so gcc defaults to returning their
12863 longest length, which in turn sets the far jump attribute to true.
12865 A false negative will not result in bad code being generated, but it
12866 will result in a needless push and pop of the link register. We
12867 hope that this does not occur too often.
12869 If we need doubleword stack alignment this could affect the other
12870 elimination offsets so we can't risk getting it wrong. */
12871 if (regs_ever_live
[ARG_POINTER_REGNUM
])
12872 cfun
->machine
->arg_pointer_live
= 1;
12873 else if (!cfun
->machine
->arg_pointer_live
)
12877 /* Check to see if the function contains a branch
12878 insn with the far jump attribute set. */
12879 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12881 if (GET_CODE (insn
) == JUMP_INSN
12882 /* Ignore tablejump patterns. */
12883 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
12884 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
12885 && get_attr_far_jump (insn
) == FAR_JUMP_YES
12888 /* Record the fact that we have decided that
12889 the function does use far jumps. */
12890 cfun
->machine
->far_jump_used
= 1;
12898 /* Return nonzero if FUNC must be entered in ARM mode. */
12900 is_called_in_ARM_mode (tree func
)
12902 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
12904 /* Ignore the problem about functions whose address is taken. */
12905 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
12909 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
12915 /* The bits which aren't usefully expanded as rtl. */
12917 thumb_unexpanded_epilogue (void)
12920 unsigned long live_regs_mask
= 0;
12921 int high_regs_pushed
= 0;
12922 int had_to_push_lr
;
12925 if (return_used_this_function
)
12928 if (IS_NAKED (arm_current_func_type ()))
12931 live_regs_mask
= thumb_compute_save_reg_mask ();
12932 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
12934 /* If we can deduce the registers used from the function's return value.
12935 This is more reliable that examining regs_ever_live[] because that
12936 will be set if the register is ever used in the function, not just if
12937 the register is used to hold a return value. */
12938 size
= arm_size_return_regs ();
12940 /* The prolog may have pushed some high registers to use as
12941 work registers. e.g. the testsuite file:
12942 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12943 compiles to produce:
12944 push {r4, r5, r6, r7, lr}
12948 as part of the prolog. We have to undo that pushing here. */
12950 if (high_regs_pushed
)
12952 unsigned long mask
= live_regs_mask
& 0xff;
12955 /* The available low registers depend on the size of the value we are
12963 /* Oh dear! We have no low registers into which we can pop
12966 ("no low registers available for popping high registers");
12968 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
12969 if (live_regs_mask
& (1 << next_hi_reg
))
12972 while (high_regs_pushed
)
12974 /* Find lo register(s) into which the high register(s) can
12976 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12978 if (mask
& (1 << regno
))
12979 high_regs_pushed
--;
12980 if (high_regs_pushed
== 0)
12984 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
12986 /* Pop the values into the low register(s). */
12987 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
12989 /* Move the value(s) into the high registers. */
12990 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12992 if (mask
& (1 << regno
))
12994 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
12997 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
12998 if (live_regs_mask
& (1 << next_hi_reg
))
13003 live_regs_mask
&= ~0x0f00;
13006 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13007 live_regs_mask
&= 0xff;
13009 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13011 /* Pop the return address into the PC. */
13012 if (had_to_push_lr
)
13013 live_regs_mask
|= 1 << PC_REGNUM
;
13015 /* Either no argument registers were pushed or a backtrace
13016 structure was created which includes an adjusted stack
13017 pointer, so just pop everything. */
13018 if (live_regs_mask
)
13019 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13022 /* We have either just popped the return address into the
13023 PC or it is was kept in LR for the entire function. */
13024 if (!had_to_push_lr
)
13025 thumb_exit (asm_out_file
, LR_REGNUM
);
13029 /* Pop everything but the return address. */
13030 if (live_regs_mask
)
13031 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13034 if (had_to_push_lr
)
13038 /* We have no free low regs, so save one. */
13039 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13043 /* Get the return address into a temporary register. */
13044 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13045 1 << LAST_ARG_REGNUM
);
13049 /* Move the return address to lr. */
13050 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13052 /* Restore the low register. */
13053 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13058 regno
= LAST_ARG_REGNUM
;
13063 /* Remove the argument registers that were pushed onto the stack. */
13064 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13065 SP_REGNUM
, SP_REGNUM
,
13066 current_function_pretend_args_size
);
13068 thumb_exit (asm_out_file
, regno
);
13074 /* Functions to save and restore machine-specific function data. */
13075 static struct machine_function
*
13076 arm_init_machine_status (void)
13078 struct machine_function
*machine
;
13079 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13081 #if ARM_FT_UNKNOWN != 0
13082 machine
->func_type
= ARM_FT_UNKNOWN
;
13087 /* Return an RTX indicating where the return address to the
13088 calling function can be found. */
13090 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13095 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13098 /* Do anything needed before RTL is emitted for each function. */
13100 arm_init_expanders (void)
13102 /* Arrange to initialize and mark the machine per-function status. */
13103 init_machine_status
= arm_init_machine_status
;
13105 /* This is to stop the combine pass optimizing away the alignment
13106 adjustment of va_arg. */
13107 /* ??? It is claimed that this should not be necessary. */
13109 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13113 /* Like arm_compute_initial_elimination offset. Simpler because
13114 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13117 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13119 arm_stack_offsets
*offsets
;
13121 offsets
= arm_get_frame_offsets ();
13125 case ARG_POINTER_REGNUM
:
13128 case STACK_POINTER_REGNUM
:
13129 return offsets
->outgoing_args
- offsets
->saved_args
;
13131 case FRAME_POINTER_REGNUM
:
13132 return offsets
->soft_frame
- offsets
->saved_args
;
13134 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13135 case ARM_HARD_FRAME_POINTER_REGNUM
:
13136 return offsets
->saved_regs
- offsets
->saved_args
;
13139 gcc_unreachable ();
13143 case FRAME_POINTER_REGNUM
:
13146 case STACK_POINTER_REGNUM
:
13147 return offsets
->outgoing_args
- offsets
->soft_frame
;
13149 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13150 case ARM_HARD_FRAME_POINTER_REGNUM
:
13151 return offsets
->saved_regs
- offsets
->soft_frame
;
13154 gcc_unreachable ();
13159 gcc_unreachable ();
13164 /* Generate the rest of a function's prologue. */
13166 thumb_expand_prologue (void)
13170 HOST_WIDE_INT amount
;
13171 arm_stack_offsets
*offsets
;
13172 unsigned long func_type
;
13174 unsigned long live_regs_mask
;
13176 func_type
= arm_current_func_type ();
13178 /* Naked functions don't have prologues. */
13179 if (IS_NAKED (func_type
))
13182 if (IS_INTERRUPT (func_type
))
13184 error ("interrupt Service Routines cannot be coded in Thumb mode");
13188 live_regs_mask
= thumb_compute_save_reg_mask ();
13189 /* Load the pic register before setting the frame pointer,
13190 so we can use r7 as a temporary work register. */
13192 arm_load_pic_register (thumb_find_work_register (live_regs_mask
));
13194 offsets
= arm_get_frame_offsets ();
13196 if (frame_pointer_needed
)
13198 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
13199 stack_pointer_rtx
));
13200 RTX_FRAME_RELATED_P (insn
) = 1;
13202 else if (CALLER_INTERWORKING_SLOT_SIZE
> 0)
13203 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13204 stack_pointer_rtx
);
13206 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13211 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13212 GEN_INT (- amount
)));
13213 RTX_FRAME_RELATED_P (insn
) = 1;
13219 /* The stack decrement is too big for an immediate value in a single
13220 insn. In theory we could issue multiple subtracts, but after
13221 three of them it becomes more space efficient to place the full
13222 value in the constant pool and load into a register. (Also the
13223 ARM debugger really likes to see only one stack decrement per
13224 function). So instead we look for a scratch register into which
13225 we can load the decrement, and then we subtract this from the
13226 stack pointer. Unfortunately on the thumb the only available
13227 scratch registers are the argument registers, and we cannot use
13228 these as they may hold arguments to the function. Instead we
13229 attempt to locate a call preserved register which is used by this
13230 function. If we can find one, then we know that it will have
13231 been pushed at the start of the prologue and so we can corrupt
13233 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13234 if (live_regs_mask
& (1 << regno
)
13235 && !(frame_pointer_needed
13236 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13239 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13241 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13243 /* Choose an arbitrary, non-argument low register. */
13244 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13246 /* Save it by copying it into a high, scratch register. */
13247 emit_insn (gen_movsi (spare
, reg
));
13248 /* Add a USE to stop propagate_one_insn() from barfing. */
13249 emit_insn (gen_prologue_use (spare
));
13251 /* Decrement the stack. */
13252 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13253 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13254 stack_pointer_rtx
, reg
));
13255 RTX_FRAME_RELATED_P (insn
) = 1;
13256 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13257 plus_constant (stack_pointer_rtx
,
13259 RTX_FRAME_RELATED_P (dwarf
) = 1;
13261 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13264 /* Restore the low register's original value. */
13265 emit_insn (gen_movsi (reg
, spare
));
13267 /* Emit a USE of the restored scratch register, so that flow
13268 analysis will not consider the restore redundant. The
13269 register won't be used again in this function and isn't
13270 restored by the epilogue. */
13271 emit_insn (gen_prologue_use (reg
));
13275 reg
= gen_rtx_REG (SImode
, regno
);
13277 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13279 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13280 stack_pointer_rtx
, reg
));
13281 RTX_FRAME_RELATED_P (insn
) = 1;
13282 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13283 plus_constant (stack_pointer_rtx
,
13285 RTX_FRAME_RELATED_P (dwarf
) = 1;
13287 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13291 /* If the frame pointer is needed, emit a special barrier that
13292 will prevent the scheduler from moving stores to the frame
13293 before the stack adjustment. */
13294 if (frame_pointer_needed
)
13295 emit_insn (gen_stack_tie (stack_pointer_rtx
,
13296 hard_frame_pointer_rtx
));
13299 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13300 emit_insn (gen_blockage ());
13302 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13303 if (live_regs_mask
& 0xff)
13304 cfun
->machine
->lr_save_eliminated
= 0;
13306 /* If the link register is being kept alive, with the return address in it,
13307 then make sure that it does not get reused by the ce2 pass. */
13308 if (cfun
->machine
->lr_save_eliminated
)
13309 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13314 thumb_expand_epilogue (void)
13316 HOST_WIDE_INT amount
;
13317 arm_stack_offsets
*offsets
;
13320 /* Naked functions don't have prologues. */
13321 if (IS_NAKED (arm_current_func_type ()))
13324 offsets
= arm_get_frame_offsets ();
13325 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13327 if (frame_pointer_needed
)
13328 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13332 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13333 GEN_INT (amount
)));
13336 /* r3 is always free in the epilogue. */
13337 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13339 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13340 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13344 /* Emit a USE (stack_pointer_rtx), so that
13345 the stack adjustment will not be deleted. */
13346 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13348 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13349 emit_insn (gen_blockage ());
13351 /* Emit a clobber for each insn that will be restored in the epilogue,
13352 so that flow2 will get register lifetimes correct. */
13353 for (regno
= 0; regno
< 13; regno
++)
13354 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13355 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13357 if (! regs_ever_live
[LR_REGNUM
])
13358 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13362 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13364 unsigned long live_regs_mask
= 0;
13365 unsigned long l_mask
;
13366 unsigned high_regs_pushed
= 0;
13367 int cfa_offset
= 0;
13370 if (IS_NAKED (arm_current_func_type ()))
13373 if (is_called_in_ARM_mode (current_function_decl
))
13377 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13378 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13380 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13382 /* Generate code sequence to switch us into Thumb mode. */
13383 /* The .code 32 directive has already been emitted by
13384 ASM_DECLARE_FUNCTION_NAME. */
13385 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13386 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13388 /* Generate a label, so that the debugger will notice the
13389 change in instruction sets. This label is also used by
13390 the assembler to bypass the ARM code when this function
13391 is called from a Thumb encoded function elsewhere in the
13392 same file. Hence the definition of STUB_NAME here must
13393 agree with the definition in gas/config/tc-arm.c. */
13395 #define STUB_NAME ".real_start_of"
13397 fprintf (f
, "\t.code\t16\n");
13399 if (arm_dllexport_name_p (name
))
13400 name
= arm_strip_name_encoding (name
);
13402 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13403 fprintf (f
, "\t.thumb_func\n");
13404 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13407 if (current_function_pretend_args_size
)
13409 /* Output unwind directive for the stack adjustment. */
13410 if (ARM_EABI_UNWIND_TABLES
)
13411 fprintf (f
, "\t.pad #%d\n",
13412 current_function_pretend_args_size
);
13414 if (cfun
->machine
->uses_anonymous_args
)
13418 fprintf (f
, "\tpush\t{");
13420 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13422 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13423 regno
<= LAST_ARG_REGNUM
;
13425 asm_fprintf (f
, "%r%s", regno
,
13426 regno
== LAST_ARG_REGNUM
? "" : ", ");
13428 fprintf (f
, "}\n");
13431 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13432 SP_REGNUM
, SP_REGNUM
,
13433 current_function_pretend_args_size
);
13435 /* We don't need to record the stores for unwinding (would it
13436 help the debugger any if we did?), but record the change in
13437 the stack pointer. */
13438 if (dwarf2out_do_frame ())
13440 char *l
= dwarf2out_cfi_label ();
13442 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13443 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13447 /* Get the registers we are going to push. */
13448 live_regs_mask
= thumb_compute_save_reg_mask ();
13449 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13450 l_mask
= live_regs_mask
& 0x40ff;
13451 /* Then count how many other high registers will need to be pushed. */
13452 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13454 if (TARGET_BACKTRACE
)
13457 unsigned work_register
;
13459 /* We have been asked to create a stack backtrace structure.
13460 The code looks like this:
13464 0 sub SP, #16 Reserve space for 4 registers.
13465 2 push {R7} Push low registers.
13466 4 add R7, SP, #20 Get the stack pointer before the push.
13467 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13468 8 mov R7, PC Get hold of the start of this code plus 12.
13469 10 str R7, [SP, #16] Store it.
13470 12 mov R7, FP Get hold of the current frame pointer.
13471 14 str R7, [SP, #4] Store it.
13472 16 mov R7, LR Get hold of the current return address.
13473 18 str R7, [SP, #12] Store it.
13474 20 add R7, SP, #16 Point at the start of the backtrace structure.
13475 22 mov FP, R7 Put this value into the frame pointer. */
13477 work_register
= thumb_find_work_register (live_regs_mask
);
13479 if (ARM_EABI_UNWIND_TABLES
)
13480 asm_fprintf (f
, "\t.pad #16\n");
13483 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13484 SP_REGNUM
, SP_REGNUM
);
13486 if (dwarf2out_do_frame ())
13488 char *l
= dwarf2out_cfi_label ();
13490 cfa_offset
= cfa_offset
+ 16;
13491 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13496 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13497 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13502 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13503 offset
+ 16 + current_function_pretend_args_size
);
13505 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13508 /* Make sure that the instruction fetching the PC is in the right place
13509 to calculate "start of backtrace creation code + 12". */
13512 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13513 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13515 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13516 ARM_HARD_FRAME_POINTER_REGNUM
);
13517 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13522 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13523 ARM_HARD_FRAME_POINTER_REGNUM
);
13524 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13526 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13527 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13531 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13532 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13534 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13536 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13537 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13539 /* Optimization: If we are not pushing any low registers but we are going
13540 to push some high registers then delay our first push. This will just
13541 be a push of LR and we can combine it with the push of the first high
13543 else if ((l_mask
& 0xff) != 0
13544 || (high_regs_pushed
== 0 && l_mask
))
13545 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13547 if (high_regs_pushed
)
13549 unsigned pushable_regs
;
13550 unsigned next_hi_reg
;
13552 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13553 if (live_regs_mask
& (1 << next_hi_reg
))
13556 pushable_regs
= l_mask
& 0xff;
13558 if (pushable_regs
== 0)
13559 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13561 while (high_regs_pushed
> 0)
13563 unsigned long real_regs_mask
= 0;
13565 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13567 if (pushable_regs
& (1 << regno
))
13569 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13571 high_regs_pushed
--;
13572 real_regs_mask
|= (1 << next_hi_reg
);
13574 if (high_regs_pushed
)
13576 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13578 if (live_regs_mask
& (1 << next_hi_reg
))
13583 pushable_regs
&= ~((1 << regno
) - 1);
13589 /* If we had to find a work register and we have not yet
13590 saved the LR then add it to the list of regs to push. */
13591 if (l_mask
== (1 << LR_REGNUM
))
13593 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
13595 real_regs_mask
| (1 << LR_REGNUM
));
13599 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
13604 /* Handle the case of a double word load into a low register from
13605 a computed memory address. The computed address may involve a
13606 register which is overwritten by the load. */
13608 thumb_load_double_from_address (rtx
*operands
)
13616 gcc_assert (GET_CODE (operands
[0]) == REG
);
13617 gcc_assert (GET_CODE (operands
[1]) == MEM
);
13619 /* Get the memory address. */
13620 addr
= XEXP (operands
[1], 0);
13622 /* Work out how the memory address is computed. */
13623 switch (GET_CODE (addr
))
13626 operands
[2] = gen_rtx_MEM (SImode
,
13627 plus_constant (XEXP (operands
[1], 0), 4));
13629 if (REGNO (operands
[0]) == REGNO (addr
))
13631 output_asm_insn ("ldr\t%H0, %2", operands
);
13632 output_asm_insn ("ldr\t%0, %1", operands
);
13636 output_asm_insn ("ldr\t%0, %1", operands
);
13637 output_asm_insn ("ldr\t%H0, %2", operands
);
13642 /* Compute <address> + 4 for the high order load. */
13643 operands
[2] = gen_rtx_MEM (SImode
,
13644 plus_constant (XEXP (operands
[1], 0), 4));
13646 output_asm_insn ("ldr\t%0, %1", operands
);
13647 output_asm_insn ("ldr\t%H0, %2", operands
);
13651 arg1
= XEXP (addr
, 0);
13652 arg2
= XEXP (addr
, 1);
13654 if (CONSTANT_P (arg1
))
13655 base
= arg2
, offset
= arg1
;
13657 base
= arg1
, offset
= arg2
;
13659 gcc_assert (GET_CODE (base
) == REG
);
13661 /* Catch the case of <address> = <reg> + <reg> */
13662 if (GET_CODE (offset
) == REG
)
13664 int reg_offset
= REGNO (offset
);
13665 int reg_base
= REGNO (base
);
13666 int reg_dest
= REGNO (operands
[0]);
13668 /* Add the base and offset registers together into the
13669 higher destination register. */
13670 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
13671 reg_dest
+ 1, reg_base
, reg_offset
);
13673 /* Load the lower destination register from the address in
13674 the higher destination register. */
13675 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
13676 reg_dest
, reg_dest
+ 1);
13678 /* Load the higher destination register from its own address
13680 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
13681 reg_dest
+ 1, reg_dest
+ 1);
13685 /* Compute <address> + 4 for the high order load. */
13686 operands
[2] = gen_rtx_MEM (SImode
,
13687 plus_constant (XEXP (operands
[1], 0), 4));
13689 /* If the computed address is held in the low order register
13690 then load the high order register first, otherwise always
13691 load the low order register first. */
13692 if (REGNO (operands
[0]) == REGNO (base
))
13694 output_asm_insn ("ldr\t%H0, %2", operands
);
13695 output_asm_insn ("ldr\t%0, %1", operands
);
13699 output_asm_insn ("ldr\t%0, %1", operands
);
13700 output_asm_insn ("ldr\t%H0, %2", operands
);
13706 /* With no registers to worry about we can just load the value
13708 operands
[2] = gen_rtx_MEM (SImode
,
13709 plus_constant (XEXP (operands
[1], 0), 4));
13711 output_asm_insn ("ldr\t%H0, %2", operands
);
13712 output_asm_insn ("ldr\t%0, %1", operands
);
13716 gcc_unreachable ();
13723 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
13730 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13733 operands
[4] = operands
[5];
13736 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
13737 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
13741 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13744 operands
[4] = operands
[5];
13747 if (REGNO (operands
[5]) > REGNO (operands
[6]))
13750 operands
[5] = operands
[6];
13753 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13756 operands
[4] = operands
[5];
13760 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
13761 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
13765 gcc_unreachable ();
13771 /* Output a call-via instruction for thumb state. */
13773 thumb_call_via_reg (rtx reg
)
13775 int regno
= REGNO (reg
);
13778 gcc_assert (regno
< LR_REGNUM
);
13780 /* If we are in the normal text section we can use a single instance
13781 per compilation unit. If we are doing function sections, then we need
13782 an entry per section, since we can't rely on reachability. */
13783 if (in_text_section ())
13785 thumb_call_reg_needed
= 1;
13787 if (thumb_call_via_label
[regno
] == NULL
)
13788 thumb_call_via_label
[regno
] = gen_label_rtx ();
13789 labelp
= thumb_call_via_label
+ regno
;
13793 if (cfun
->machine
->call_via
[regno
] == NULL
)
13794 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
13795 labelp
= cfun
->machine
->call_via
+ regno
;
13798 output_asm_insn ("bl\t%a0", labelp
);
13802 /* Routines for generating rtl. */
13804 thumb_expand_movmemqi (rtx
*operands
)
13806 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
13807 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
13808 HOST_WIDE_INT len
= INTVAL (operands
[2]);
13809 HOST_WIDE_INT offset
= 0;
13813 emit_insn (gen_movmem12b (out
, in
, out
, in
));
13819 emit_insn (gen_movmem8b (out
, in
, out
, in
));
13825 rtx reg
= gen_reg_rtx (SImode
);
13826 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
13827 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
13834 rtx reg
= gen_reg_rtx (HImode
);
13835 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
13836 plus_constant (in
, offset
))));
13837 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
13845 rtx reg
= gen_reg_rtx (QImode
);
13846 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
13847 plus_constant (in
, offset
))));
13848 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
13854 thumb_reload_out_hi (rtx
*operands
)
13856 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
13859 /* Handle reading a half-word from memory during reload. */
13861 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
13863 gcc_unreachable ();
13866 /* Return the length of a function name prefix
13867 that starts with the character 'c'. */
13869 arm_get_strip_length (int c
)
13873 ARM_NAME_ENCODING_LENGTHS
13878 /* Return a pointer to a function's name with any
13879 and all prefix encodings stripped from it. */
13881 arm_strip_name_encoding (const char *name
)
13885 while ((skip
= arm_get_strip_length (* name
)))
13891 /* If there is a '*' anywhere in the name's prefix, then
13892 emit the stripped name verbatim, otherwise prepend an
13893 underscore if leading underscores are being used. */
13895 arm_asm_output_labelref (FILE *stream
, const char *name
)
13900 while ((skip
= arm_get_strip_length (* name
)))
13902 verbatim
|= (*name
== '*');
13907 fputs (name
, stream
);
13909 asm_fprintf (stream
, "%U%s", name
);
13913 arm_file_end (void)
13917 if (! thumb_call_reg_needed
)
13921 asm_fprintf (asm_out_file
, "\t.code 16\n");
13922 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
13924 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
13926 rtx label
= thumb_call_via_label
[regno
];
13930 targetm
.asm_out
.internal_label (asm_out_file
, "L",
13931 CODE_LABEL_NUMBER (label
));
13932 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
13939 #ifdef AOF_ASSEMBLER
13940 /* Special functions only needed when producing AOF syntax assembler. */
13944 struct pic_chain
* next
;
13945 const char * symname
;
13948 static struct pic_chain
* aof_pic_chain
= NULL
;
13951 aof_pic_entry (rtx x
)
13953 struct pic_chain
** chainp
;
13956 if (aof_pic_label
== NULL_RTX
)
13958 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
13961 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
13962 offset
+= 4, chainp
= &(*chainp
)->next
)
13963 if ((*chainp
)->symname
== XSTR (x
, 0))
13964 return plus_constant (aof_pic_label
, offset
);
13966 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
13967 (*chainp
)->next
= NULL
;
13968 (*chainp
)->symname
= XSTR (x
, 0);
13969 return plus_constant (aof_pic_label
, offset
);
13973 aof_dump_pic_table (FILE *f
)
13975 struct pic_chain
* chain
;
13977 if (aof_pic_chain
== NULL
)
13980 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
13981 PIC_OFFSET_TABLE_REGNUM
,
13982 PIC_OFFSET_TABLE_REGNUM
);
13983 fputs ("|x$adcons|\n", f
);
13985 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
13987 fputs ("\tDCD\t", f
);
13988 assemble_name (f
, chain
->symname
);
13993 int arm_text_section_count
= 1;
13996 aof_text_section (void )
13998 static char buf
[100];
13999 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14000 arm_text_section_count
++);
14002 strcat (buf
, ", PIC, REENTRANT");
14006 static int arm_data_section_count
= 1;
14009 aof_data_section (void)
14011 static char buf
[100];
14012 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14016 /* The AOF assembler is religiously strict about declarations of
14017 imported and exported symbols, so that it is impossible to declare
14018 a function as imported near the beginning of the file, and then to
14019 export it later on. It is, however, possible to delay the decision
14020 until all the functions in the file have been compiled. To get
14021 around this, we maintain a list of the imports and exports, and
14022 delete from it any that are subsequently defined. At the end of
14023 compilation we spit the remainder of the list out before the END
14028 struct import
* next
;
14032 static struct import
* imports_list
= NULL
;
14035 aof_add_import (const char *name
)
14037 struct import
* new;
14039 for (new = imports_list
; new; new = new->next
)
14040 if (new->name
== name
)
14043 new = (struct import
*) xmalloc (sizeof (struct import
));
14044 new->next
= imports_list
;
14045 imports_list
= new;
14050 aof_delete_import (const char *name
)
14052 struct import
** old
;
14054 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14056 if ((*old
)->name
== name
)
14058 *old
= (*old
)->next
;
14064 int arm_main_function
= 0;
14067 aof_dump_imports (FILE *f
)
14069 /* The AOF assembler needs this to cause the startup code to be extracted
14070 from the library. Brining in __main causes the whole thing to work
14072 if (arm_main_function
)
14075 fputs ("\tIMPORT __main\n", f
);
14076 fputs ("\tDCD __main\n", f
);
14079 /* Now dump the remaining imports. */
14080 while (imports_list
)
14082 fprintf (f
, "\tIMPORT\t");
14083 assemble_name (f
, imports_list
->name
);
14085 imports_list
= imports_list
->next
;
14090 aof_globalize_label (FILE *stream
, const char *name
)
14092 default_globalize_label (stream
, name
);
14093 if (! strcmp (name
, "main"))
14094 arm_main_function
= 1;
14098 aof_file_start (void)
14100 fputs ("__r0\tRN\t0\n", asm_out_file
);
14101 fputs ("__a1\tRN\t0\n", asm_out_file
);
14102 fputs ("__a2\tRN\t1\n", asm_out_file
);
14103 fputs ("__a3\tRN\t2\n", asm_out_file
);
14104 fputs ("__a4\tRN\t3\n", asm_out_file
);
14105 fputs ("__v1\tRN\t4\n", asm_out_file
);
14106 fputs ("__v2\tRN\t5\n", asm_out_file
);
14107 fputs ("__v3\tRN\t6\n", asm_out_file
);
14108 fputs ("__v4\tRN\t7\n", asm_out_file
);
14109 fputs ("__v5\tRN\t8\n", asm_out_file
);
14110 fputs ("__v6\tRN\t9\n", asm_out_file
);
14111 fputs ("__sl\tRN\t10\n", asm_out_file
);
14112 fputs ("__fp\tRN\t11\n", asm_out_file
);
14113 fputs ("__ip\tRN\t12\n", asm_out_file
);
14114 fputs ("__sp\tRN\t13\n", asm_out_file
);
14115 fputs ("__lr\tRN\t14\n", asm_out_file
);
14116 fputs ("__pc\tRN\t15\n", asm_out_file
);
14117 fputs ("__f0\tFN\t0\n", asm_out_file
);
14118 fputs ("__f1\tFN\t1\n", asm_out_file
);
14119 fputs ("__f2\tFN\t2\n", asm_out_file
);
14120 fputs ("__f3\tFN\t3\n", asm_out_file
);
14121 fputs ("__f4\tFN\t4\n", asm_out_file
);
14122 fputs ("__f5\tFN\t5\n", asm_out_file
);
14123 fputs ("__f6\tFN\t6\n", asm_out_file
);
14124 fputs ("__f7\tFN\t7\n", asm_out_file
);
14129 aof_file_end (void)
14132 aof_dump_pic_table (asm_out_file
);
14134 aof_dump_imports (asm_out_file
);
14135 fputs ("\tEND\n", asm_out_file
);
14137 #endif /* AOF_ASSEMBLER */
14140 /* Symbols in the text segment can be accessed without indirecting via the
14141 constant pool; it may take an extra binary operation, but this is still
14142 faster than indirecting via memory. Don't do this when not optimizing,
14143 since we won't be calculating al of the offsets necessary to do this
14147 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14149 /* This doesn't work with AOF syntax, since the string table may be in
14150 a different AREA. */
14151 #ifndef AOF_ASSEMBLER
14152 if (optimize
> 0 && TREE_CONSTANT (decl
))
14153 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14156 /* If we are referencing a function that is weak then encode a long call
14157 flag in the function name, otherwise if the function is static or
14158 or known to be defined in this file then encode a short call flag. */
14159 if (first
&& DECL_P (decl
))
14161 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14162 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14163 else if (! TREE_PUBLIC (decl
))
14164 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14167 #endif /* !ARM_PE */
14170 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14172 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14173 && !strcmp (prefix
, "L"))
14175 arm_ccfsm_state
= 0;
14176 arm_target_insn
= NULL
;
14178 default_internal_label (stream
, prefix
, labelno
);
14181 /* Output code to add DELTA to the first argument, and then jump
14182 to FUNCTION. Used for C++ multiple inheritance. */
14184 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14185 HOST_WIDE_INT delta
,
14186 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14189 static int thunk_label
= 0;
14191 int mi_delta
= delta
;
14192 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14194 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14197 mi_delta
= - mi_delta
;
14200 int labelno
= thunk_label
++;
14201 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14202 fputs ("\tldr\tr12, ", file
);
14203 assemble_name (file
, label
);
14204 fputc ('\n', file
);
14206 while (mi_delta
!= 0)
14208 if ((mi_delta
& (3 << shift
)) == 0)
14212 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14213 mi_op
, this_regno
, this_regno
,
14214 mi_delta
& (0xff << shift
));
14215 mi_delta
&= ~(0xff << shift
);
14221 fprintf (file
, "\tbx\tr12\n");
14222 ASM_OUTPUT_ALIGN (file
, 2);
14223 assemble_name (file
, label
);
14224 fputs (":\n", file
);
14225 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14229 fputs ("\tb\t", file
);
14230 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14231 if (NEED_PLT_RELOC
)
14232 fputs ("(PLT)", file
);
14233 fputc ('\n', file
);
14238 arm_emit_vector_const (FILE *file
, rtx x
)
14241 const char * pattern
;
14243 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14245 switch (GET_MODE (x
))
14247 case V2SImode
: pattern
= "%08x"; break;
14248 case V4HImode
: pattern
= "%04x"; break;
14249 case V8QImode
: pattern
= "%02x"; break;
14250 default: gcc_unreachable ();
14253 fprintf (file
, "0x");
14254 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14258 element
= CONST_VECTOR_ELT (x
, i
);
14259 fprintf (file
, pattern
, INTVAL (element
));
14266 arm_output_load_gr (rtx
*operands
)
14273 if (GET_CODE (operands
[1]) != MEM
14274 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14275 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14276 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14277 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14278 return "wldrw%?\t%0, %1";
14280 /* Fix up an out-of-range load of a GR register. */
14281 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14282 wcgr
= operands
[0];
14284 output_asm_insn ("ldr%?\t%0, %1", operands
);
14286 operands
[0] = wcgr
;
14288 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14289 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14295 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14296 int incoming ATTRIBUTE_UNUSED
)
14299 /* FIXME: The ARM backend has special code to handle structure
14300 returns, and will reserve its own hidden first argument. So
14301 if this macro is enabled a *second* hidden argument will be
14302 reserved, which will break binary compatibility with old
14303 toolchains and also thunk handling. One day this should be
14307 /* Register in which address to store a structure value
14308 is passed to a function. */
14309 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14313 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14315 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14316 named arg and all anonymous args onto the stack.
14317 XXX I know the prologue shouldn't be pushing registers, but it is faster
14321 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14322 enum machine_mode mode ATTRIBUTE_UNUSED
,
14323 tree type ATTRIBUTE_UNUSED
,
14325 int second_time ATTRIBUTE_UNUSED
)
14327 cfun
->machine
->uses_anonymous_args
= 1;
14328 if (cum
->nregs
< NUM_ARG_REGS
)
14329 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14332 /* Return nonzero if the CONSUMER instruction (a store) does not need
14333 PRODUCER's value to calculate the address. */
14336 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14338 rtx value
= PATTERN (producer
);
14339 rtx addr
= PATTERN (consumer
);
14341 if (GET_CODE (value
) == COND_EXEC
)
14342 value
= COND_EXEC_CODE (value
);
14343 if (GET_CODE (value
) == PARALLEL
)
14344 value
= XVECEXP (value
, 0, 0);
14345 value
= XEXP (value
, 0);
14346 if (GET_CODE (addr
) == COND_EXEC
)
14347 addr
= COND_EXEC_CODE (addr
);
14348 if (GET_CODE (addr
) == PARALLEL
)
14349 addr
= XVECEXP (addr
, 0, 0);
14350 addr
= XEXP (addr
, 0);
14352 return !reg_overlap_mentioned_p (value
, addr
);
14355 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14356 have an early register shift value or amount dependency on the
14357 result of PRODUCER. */
14360 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14362 rtx value
= PATTERN (producer
);
14363 rtx op
= PATTERN (consumer
);
14366 if (GET_CODE (value
) == COND_EXEC
)
14367 value
= COND_EXEC_CODE (value
);
14368 if (GET_CODE (value
) == PARALLEL
)
14369 value
= XVECEXP (value
, 0, 0);
14370 value
= XEXP (value
, 0);
14371 if (GET_CODE (op
) == COND_EXEC
)
14372 op
= COND_EXEC_CODE (op
);
14373 if (GET_CODE (op
) == PARALLEL
)
14374 op
= XVECEXP (op
, 0, 0);
14377 early_op
= XEXP (op
, 0);
14378 /* This is either an actual independent shift, or a shift applied to
14379 the first operand of another operation. We want the whole shift
14381 if (GET_CODE (early_op
) == REG
)
14384 return !reg_overlap_mentioned_p (value
, early_op
);
14387 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14388 have an early register shift value dependency on the result of
14392 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14394 rtx value
= PATTERN (producer
);
14395 rtx op
= PATTERN (consumer
);
14398 if (GET_CODE (value
) == COND_EXEC
)
14399 value
= COND_EXEC_CODE (value
);
14400 if (GET_CODE (value
) == PARALLEL
)
14401 value
= XVECEXP (value
, 0, 0);
14402 value
= XEXP (value
, 0);
14403 if (GET_CODE (op
) == COND_EXEC
)
14404 op
= COND_EXEC_CODE (op
);
14405 if (GET_CODE (op
) == PARALLEL
)
14406 op
= XVECEXP (op
, 0, 0);
14409 early_op
= XEXP (op
, 0);
14411 /* This is either an actual independent shift, or a shift applied to
14412 the first operand of another operation. We want the value being
14413 shifted, in either case. */
14414 if (GET_CODE (early_op
) != REG
)
14415 early_op
= XEXP (early_op
, 0);
14417 return !reg_overlap_mentioned_p (value
, early_op
);
14420 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14421 have an early register mult dependency on the result of
14425 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14427 rtx value
= PATTERN (producer
);
14428 rtx op
= PATTERN (consumer
);
14430 if (GET_CODE (value
) == COND_EXEC
)
14431 value
= COND_EXEC_CODE (value
);
14432 if (GET_CODE (value
) == PARALLEL
)
14433 value
= XVECEXP (value
, 0, 0);
14434 value
= XEXP (value
, 0);
14435 if (GET_CODE (op
) == COND_EXEC
)
14436 op
= COND_EXEC_CODE (op
);
14437 if (GET_CODE (op
) == PARALLEL
)
14438 op
= XVECEXP (op
, 0, 0);
14441 return (GET_CODE (op
) == PLUS
14442 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14446 /* We can't rely on the caller doing the proper promotion when
14447 using APCS or ATPCS. */
14450 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14452 return !TARGET_AAPCS_BASED
;
14456 /* AAPCS based ABIs use short enums by default. */
14459 arm_default_short_enums (void)
14461 return TARGET_AAPCS_BASED
;
14465 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14468 arm_align_anon_bitfield (void)
14470 return TARGET_AAPCS_BASED
;
14474 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14477 arm_cxx_guard_type (void)
14479 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14483 /* The EABI says test the least significant bit of a guard variable. */
14486 arm_cxx_guard_mask_bit (void)
14488 return TARGET_AAPCS_BASED
;
14492 /* The EABI specifies that all array cookies are 8 bytes long. */
14495 arm_get_cookie_size (tree type
)
14499 if (!TARGET_AAPCS_BASED
)
14500 return default_cxx_get_cookie_size (type
);
14502 size
= build_int_cst (sizetype
, 8);
14507 /* The EABI says that array cookies should also contain the element size. */
14510 arm_cookie_has_size (void)
14512 return TARGET_AAPCS_BASED
;
14516 /* The EABI says constructors and destructors should return a pointer to
14517 the object constructed/destroyed. */
14520 arm_cxx_cdtor_returns_this (void)
14522 return TARGET_AAPCS_BASED
;
14525 /* The EABI says that an inline function may never be the key
14529 arm_cxx_key_method_may_be_inline (void)
14531 return !TARGET_AAPCS_BASED
;
14535 arm_cxx_determine_class_data_visibility (tree decl
)
14537 if (!TARGET_AAPCS_BASED
)
14540 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14541 is exported. However, on systems without dynamic vague linkage,
14542 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14543 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
14544 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
14546 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
14547 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
14551 arm_cxx_class_data_always_comdat (void)
14553 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14554 vague linkage if the class has no key function. */
14555 return !TARGET_AAPCS_BASED
;
14559 /* The EABI says __aeabi_atexit should be used to register static
14563 arm_cxx_use_aeabi_atexit (void)
14565 return TARGET_AAPCS_BASED
;
14570 arm_set_return_address (rtx source
, rtx scratch
)
14572 arm_stack_offsets
*offsets
;
14573 HOST_WIDE_INT delta
;
14575 unsigned long saved_regs
;
14577 saved_regs
= arm_compute_save_reg_mask ();
14579 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14580 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14583 if (frame_pointer_needed
)
14584 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
14587 /* LR will be the first saved register. */
14588 offsets
= arm_get_frame_offsets ();
14589 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
14594 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
14595 GEN_INT (delta
& ~4095)));
14600 addr
= stack_pointer_rtx
;
14602 addr
= plus_constant (addr
, delta
);
14604 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14610 thumb_set_return_address (rtx source
, rtx scratch
)
14612 arm_stack_offsets
*offsets
;
14613 HOST_WIDE_INT delta
;
14616 unsigned long mask
;
14618 emit_insn (gen_rtx_USE (VOIDmode
, source
));
14620 mask
= thumb_compute_save_reg_mask ();
14621 if (mask
& (1 << LR_REGNUM
))
14623 offsets
= arm_get_frame_offsets ();
14625 /* Find the saved regs. */
14626 if (frame_pointer_needed
)
14628 delta
= offsets
->soft_frame
- offsets
->saved_args
;
14629 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
14633 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
14636 /* Allow for the stack frame. */
14637 if (TARGET_BACKTRACE
)
14639 /* The link register is always the first saved register. */
14642 /* Construct the address. */
14643 addr
= gen_rtx_REG (SImode
, reg
);
14644 if ((reg
!= SP_REGNUM
&& delta
>= 128)
14647 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
14648 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
14652 addr
= plus_constant (addr
, delta
);
14654 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14657 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14660 /* Implements target hook vector_mode_supported_p. */
14662 arm_vector_mode_supported_p (enum machine_mode mode
)
14664 if ((mode
== V2SImode
)
14665 || (mode
== V4HImode
)
14666 || (mode
== V8QImode
))
14672 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
14673 ARM insns and therefore guarantee that the shift count is modulo 256.
14674 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
14675 guarantee no particular behavior for out-of-range counts. */
14677 static unsigned HOST_WIDE_INT
14678 arm_shift_truncation_mask (enum machine_mode mode
)
14680 return mode
== SImode
? 255 : 0;
14684 /* Map internal gcc register numbers to DWARF2 register numbers. */
14687 arm_dbx_register_number (unsigned int regno
)
14692 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
14693 compatibility. The EABI defines them as registers 96-103. */
14694 if (IS_FPA_REGNUM (regno
))
14695 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
14697 if (IS_VFP_REGNUM (regno
))
14698 return 64 + regno
- FIRST_VFP_REGNUM
;
14700 if (IS_IWMMXT_GR_REGNUM (regno
))
14701 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
14703 if (IS_IWMMXT_REGNUM (regno
))
14704 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
14706 gcc_unreachable ();
14710 #ifdef TARGET_UNWIND_INFO
14711 /* Emit unwind directives for a store-multiple instruction. This should
14712 only ever be generated by the function prologue code, so we expect it
14713 to have a particular form. */
14716 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
14719 HOST_WIDE_INT offset
;
14720 HOST_WIDE_INT nregs
;
14726 /* First insn will adjust the stack pointer. */
14727 e
= XVECEXP (p
, 0, 0);
14728 if (GET_CODE (e
) != SET
14729 || GET_CODE (XEXP (e
, 0)) != REG
14730 || REGNO (XEXP (e
, 0)) != SP_REGNUM
14731 || GET_CODE (XEXP (e
, 1)) != PLUS
)
14734 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
14735 nregs
= XVECLEN (p
, 0) - 1;
14737 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
14740 /* The function prologue may also push pc, but not annotate it as it is
14741 never restored. We turn this into an stack pointer adjustment. */
14742 if (nregs
* 4 == offset
- 4)
14744 fprintf (asm_out_file
, "\t.pad #4\n");
14749 else if (IS_VFP_REGNUM (reg
))
14751 /* FPA register saves use an additional word. */
14755 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
14757 /* FPA registers are done differently. */
14758 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
14762 /* Unknown register type. */
14765 /* If the stack increment doesn't match the size of the saved registers,
14766 something has gone horribly wrong. */
14767 if (offset
!= nregs
* reg_size
)
14770 fprintf (asm_out_file
, "\t.save {");
14774 /* The remaining insns will describe the stores. */
14775 for (i
= 1; i
<= nregs
; i
++)
14777 /* Expect (set (mem <addr>) (reg)).
14778 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
14779 e
= XVECEXP (p
, 0, i
);
14780 if (GET_CODE (e
) != SET
14781 || GET_CODE (XEXP (e
, 0)) != MEM
14782 || GET_CODE (XEXP (e
, 1)) != REG
)
14785 reg
= REGNO (XEXP (e
, 1));
14790 fprintf (asm_out_file
, ", ");
14791 /* We can't use %r for vfp because we need to use the
14792 double precision register names. */
14793 if (IS_VFP_REGNUM (reg
))
14794 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
14796 asm_fprintf (asm_out_file
, "%r", reg
);
14798 #ifdef ENABLE_CHECKING
14799 /* Check that the addresses are consecutive. */
14800 e
= XEXP (XEXP (e
, 0), 0);
14801 if (GET_CODE (e
) == PLUS
)
14803 offset
+= reg_size
;
14804 if (GET_CODE (XEXP (e
, 0)) != REG
14805 || REGNO (XEXP (e
, 0)) != SP_REGNUM
14806 || GET_CODE (XEXP (e
, 1)) != CONST_INT
14807 || offset
!= INTVAL (XEXP (e
, 1)))
14811 || GET_CODE (e
) != REG
14812 || REGNO (e
) != SP_REGNUM
)
14816 fprintf (asm_out_file
, "}\n");
14819 /* Emit unwind directives for a SET. */
14822 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
14829 switch (GET_CODE (e0
))
14832 /* Pushing a single register. */
14833 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
14834 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
14835 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
14838 asm_fprintf (asm_out_file
, "\t.save ");
14839 if (IS_VFP_REGNUM (REGNO (e1
)))
14840 asm_fprintf(asm_out_file
, "{d%d}\n",
14841 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
14843 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
14847 if (REGNO (e0
) == SP_REGNUM
)
14849 /* A stack increment. */
14850 if (GET_CODE (e1
) != PLUS
14851 || GET_CODE (XEXP (e1
, 0)) != REG
14852 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
14853 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
14856 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
14857 -INTVAL (XEXP (e1
, 1)));
14859 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
14861 HOST_WIDE_INT offset
;
14864 if (GET_CODE (e1
) == PLUS
)
14866 if (GET_CODE (XEXP (e1
, 0)) != REG
14867 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
14869 reg
= REGNO (XEXP (e1
, 0));
14870 offset
= INTVAL (XEXP (e1
, 1));
14871 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
14872 HARD_FRAME_POINTER_REGNUM
, reg
,
14873 INTVAL (XEXP (e1
, 1)));
14875 else if (GET_CODE (e1
) == REG
)
14878 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
14879 HARD_FRAME_POINTER_REGNUM
, reg
);
14884 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
14886 /* Move from sp to reg. */
14887 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
14899 /* Emit unwind directives for the given insn. */
14902 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
14906 if (!ARM_EABI_UNWIND_TABLES
)
14909 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
14912 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
14914 pat
= XEXP (pat
, 0);
14916 pat
= PATTERN (insn
);
14918 switch (GET_CODE (pat
))
14921 arm_unwind_emit_set (asm_out_file
, pat
);
14925 /* Store multiple. */
14926 arm_unwind_emit_stm (asm_out_file
, pat
);
14935 /* Output a reference from a function exception table to the type_info
14936 object X. The EABI specifies that the symbol should be relocated by
14937 an R_ARM_TARGET2 relocation. */
14940 arm_output_ttype (rtx x
)
14942 fputs ("\t.word\t", asm_out_file
);
14943 output_addr_const (asm_out_file
, x
);
14944 /* Use special relocations for symbol references. */
14945 if (GET_CODE (x
) != CONST_INT
)
14946 fputs ("(TARGET2)", asm_out_file
);
14947 fputc ('\n', asm_out_file
);
14951 #endif /* TARGET_UNWIND_INFO */
14954 /* Output unwind directives for the start/end of a function. */
14957 arm_output_fn_unwind (FILE * f
, bool prologue
)
14959 if (!ARM_EABI_UNWIND_TABLES
)
14963 fputs ("\t.fnstart\n", f
);
14965 fputs ("\t.fnend\n", f
);