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2005-04-01 Paul Brook <paul@codesourcery.com>
[official-gcc.git] / gcc / config / arm / arm.h
blob6e223c875b3a599287e593f39e6e9a49797f092c
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The architecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Run-time compilation parameters selecting different hardware subsets. */
121 extern int target_flags;
122 /* The floating point mode. */
123 extern const char *target_fpu_name;
124 /* For backwards compatibility. */
125 extern const char *target_fpe_name;
126 /* Whether to use floating point hardware. */
127 extern const char *target_float_abi_name;
128 /* For -m{soft,hard}-float. */
129 extern const char *target_float_switch;
130 /* Which ABI to use. */
131 extern const char *target_abi_name;
132 /* Define the information needed to generate branch insns. This is
133 stored from the compare operation. */
134 extern GTY(()) rtx arm_compare_op0;
135 extern GTY(()) rtx arm_compare_op1;
136 /* The label of the current constant pool. */
137 extern rtx pool_vector_label;
138 /* Set to 1 when a return insn is output, this means that the epilogue
139 is not needed. */
140 extern int return_used_this_function;
141 /* Used to produce AOF syntax assembler. */
142 extern GTY(()) rtx aof_pic_label;
143 \f
144 /* Just in case configure has failed to define anything. */
145 #ifndef TARGET_CPU_DEFAULT
146 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
147 #endif
148
149
150 #undef CPP_SPEC
151 #define CPP_SPEC "%(subtarget_cpp_spec) \
152 %{msoft-float:%{mhard-float: \
153 %e-msoft-float and -mhard_float may not be used together}} \
154 %{mbig-endian:%{mlittle-endian: \
155 %e-mbig-endian and -mlittle-endian may not be used together}}"
156
157 #ifndef CC1_SPEC
158 #define CC1_SPEC ""
159 #endif
160
161 /* This macro defines names of additional specifications to put in the specs
162 that can be used in various specifications like CC1_SPEC. Its definition
163 is an initializer with a subgrouping for each command option.
164
165 Each subgrouping contains a string constant, that defines the
166 specification name, and a string constant that used by the GCC driver
167 program.
168
169 Do not define this macro if it does not need to do anything. */
170 #define EXTRA_SPECS \
171 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
172 SUBTARGET_EXTRA_SPECS
173
174 #ifndef SUBTARGET_EXTRA_SPECS
175 #define SUBTARGET_EXTRA_SPECS
176 #endif
177
178 #ifndef SUBTARGET_CPP_SPEC
179 #define SUBTARGET_CPP_SPEC ""
180 #endif
181 \f
182 /* Run-time Target Specification. */
183 #ifndef TARGET_VERSION
184 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
185 #endif
186
187 /* Nonzero if the function prologue (and epilogue) should obey
188 the ARM Procedure Call Standard. */
189 #define ARM_FLAG_APCS_FRAME (1 << 0)
190
191 /* Nonzero if the function prologue should output the function name to enable
192 the post mortem debugger to print a backtrace (very useful on RISCOS,
193 unused on RISCiX). Specifying this flag also enables
194 -fno-omit-frame-pointer.
195 XXX Must still be implemented in the prologue. */
196 #define ARM_FLAG_POKE (1 << 1)
197
198 /* Nonzero if floating point instructions are emulated by the FPE, in which
199 case instruction scheduling becomes very uninteresting. */
200 #define ARM_FLAG_FPE (1 << 2)
201
202 /* FLAG 0x0008 now spare (used to be apcs-32 selection). */
203
204 /* Nonzero if stack checking should be performed on entry to each function
205 which allocates temporary variables on the stack. */
206 #define ARM_FLAG_APCS_STACK (1 << 4)
207
208 /* Nonzero if floating point parameters should be passed to functions in
209 floating point registers. */
210 #define ARM_FLAG_APCS_FLOAT (1 << 5)
211
212 /* Nonzero if re-entrant, position independent code should be generated.
213 This is equivalent to -fpic. */
214 #define ARM_FLAG_APCS_REENT (1 << 6)
215
216 /* FLAG 0x0080 now spare (used to be alignment traps). */
217 /* FLAG (1 << 8) is now spare (used to be soft-float). */
218
219 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
220 #define ARM_FLAG_BIG_END (1 << 9)
221
222 /* Nonzero if we should compile for Thumb interworking. */
223 #define ARM_FLAG_INTERWORK (1 << 10)
224
225 /* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
227 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
228
229 /* Nonzero if we need to protect the prolog from scheduling */
230 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
231
232 /* Nonzero if a call to abort should be generated if a noreturn
233 function tries to return. */
234 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
235
236 /* Nonzero if function prologues should not load the PIC register. */
237 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
238
239 /* Nonzero if all call instructions should be indirect. */
240 #define ARM_FLAG_LONG_CALLS (1 << 15)
241
242 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
243 #define ARM_FLAG_THUMB (1 << 16)
244
245 /* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247 #define THUMB_FLAG_BACKTRACE (1 << 17)
248
249 /* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
252
253 /* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
256
257 /* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
260
261 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
262 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
263
264 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
265 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
267 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
270 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
271 /* Use hardware floating point instructions. */
272 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
273 /* Use hardware floating point calling convention. */
274 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
275 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
276 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
277 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
278 #define TARGET_IWMMXT (arm_arch_iwmmxt)
279 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
280 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
281 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
282 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
283 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
284 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
285 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
286 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
287 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
288 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
289 #define TARGET_ARM (! TARGET_THUMB)
290 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
291 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
292 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
293 #define TARGET_BACKTRACE (leaf_function_p () \
294 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
295 : (target_flags & THUMB_FLAG_BACKTRACE))
296 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
297 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
298 #define TARGET_AAPCS_BASED \
299 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
300
301 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
302 then TARGET_AAPCS_BASED must be true -- but the converse does not
303 hold. TARGET_BPABI implies the use of the BPABI runtime library,
304 etc., in addition to just the AAPCS calling conventions. */
305 #ifndef TARGET_BPABI
306 #define TARGET_BPABI false
307 #endif
308
309 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
310 #ifndef SUBTARGET_SWITCHES
311 #define SUBTARGET_SWITCHES
312 #endif
313
314 #define TARGET_SWITCHES \
315 { \
316 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
317 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
318 N_("Generate APCS conformant stack frames") }, \
319 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
320 {"poke-function-name", ARM_FLAG_POKE, \
321 N_("Store function names in object code") }, \
322 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
323 {"fpe", ARM_FLAG_FPE, "" }, \
324 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
325 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
326 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
327 N_("Pass FP arguments in FP registers") }, \
328 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
329 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
330 N_("Generate re-entrant, PIC code") }, \
331 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
332 {"big-endian", ARM_FLAG_BIG_END, \
333 N_("Assume target CPU is configured as big endian") }, \
334 {"little-endian", -ARM_FLAG_BIG_END, \
335 N_("Assume target CPU is configured as little endian") }, \
336 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
337 N_("Assume big endian bytes, little endian words") }, \
338 {"thumb-interwork", ARM_FLAG_INTERWORK, \
339 N_("Support calls between Thumb and ARM instruction sets") }, \
340 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
341 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
342 N_("Generate a call to abort if a noreturn function returns")}, \
343 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
344 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
345 N_("Do not move instructions into a function's prologue") }, \
346 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
347 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
348 N_("Do not load the PIC register in function prologues") }, \
349 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
350 {"long-calls", ARM_FLAG_LONG_CALLS, \
351 N_("Generate call insns as indirect calls, if necessary") }, \
352 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
353 {"thumb", ARM_FLAG_THUMB, \
354 N_("Compile for the Thumb not the ARM") }, \
355 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
356 {"arm", -ARM_FLAG_THUMB, "" }, \
357 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
358 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
359 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
360 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
361 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
362 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
363 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
364 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
365 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
366 "" }, \
367 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
368 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
369 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
370 "" }, \
371 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
372 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
373 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
374 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
375 SUBTARGET_SWITCHES \
376 {"", TARGET_DEFAULT, "" } \
377 }
378
379 #define TARGET_OPTIONS \
380 { \
381 {"cpu=", & arm_select[0].string, \
382 N_("Specify the name of the target CPU"), 0}, \
383 {"arch=", & arm_select[1].string, \
384 N_("Specify the name of the target architecture"), 0}, \
385 {"tune=", & arm_select[2].string, "", 0}, \
386 {"fpe=", & target_fpe_name, "", 0}, \
387 {"fp=", & target_fpe_name, "", 0}, \
388 {"fpu=", & target_fpu_name, \
389 N_("Specify the name of the target floating point hardware/format"), 0}, \
390 {"float-abi=", & target_float_abi_name, \
391 N_("Specify if floating point hardware should be used"), 0}, \
392 {"structure-size-boundary=", & structure_size_string, \
393 N_("Specify the minimum bit alignment of structures"), 0}, \
394 {"pic-register=", & arm_pic_register_string, \
395 N_("Specify the register to be used for PIC addressing"), 0}, \
396 {"abi=", &target_abi_name, N_("Specify an ABI"), 0}, \
397 {"soft-float", &target_float_switch, \
398 N_("Alias for -mfloat-abi=soft"), "s"}, \
399 {"hard-float", &target_float_switch, \
400 N_("Alias for -mfloat-abi=hard"), "h"} \
401 }
402
403 /* Support for a compile-time default CPU, et cetera. The rules are:
404 --with-arch is ignored if -march or -mcpu are specified.
405 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
406 by --with-arch.
407 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
408 by -march).
409 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
410 specified.
411 --with-fpu is ignored if -mfpu is specified.
412 --with-abi is ignored is -mabi is specified. */
413 #define OPTION_DEFAULT_SPECS \
414 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
415 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
416 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
417 {"float", \
418 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
419 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
420 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
421
422 struct arm_cpu_select
423 {
424 const char * string;
425 const char * name;
426 const struct processors * processors;
427 };
428
429 /* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
432 extern struct arm_cpu_select arm_select[];
433
434 /* Which floating point model to use. */
435 enum arm_fp_model
436 {
437 ARM_FP_MODEL_UNKNOWN,
438 /* FPA model (Hardware or software). */
439 ARM_FP_MODEL_FPA,
440 /* Cirrus Maverick floating point model. */
441 ARM_FP_MODEL_MAVERICK,
442 /* VFP floating point model. */
443 ARM_FP_MODEL_VFP
444 };
445
446 extern enum arm_fp_model arm_fp_model;
447
448 /* Which floating point hardware is available. Also update
449 fp_model_for_fpu in arm.c when adding entries to this list. */
450 enum fputype
451 {
452 /* No FP hardware. */
453 FPUTYPE_NONE,
454 /* Full FPA support. */
455 FPUTYPE_FPA,
456 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
457 FPUTYPE_FPA_EMU2,
458 /* Emulated FPA hardware, Issue 3 emulator. */
459 FPUTYPE_FPA_EMU3,
460 /* Cirrus Maverick floating point co-processor. */
461 FPUTYPE_MAVERICK,
462 /* VFP. */
463 FPUTYPE_VFP
464 };
465
466 /* Recast the floating point class to be the floating point attribute. */
467 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
468
469 /* What type of floating point to tune for */
470 extern enum fputype arm_fpu_tune;
471
472 /* What type of floating point instructions are available */
473 extern enum fputype arm_fpu_arch;
474
475 enum float_abi_type
476 {
477 ARM_FLOAT_ABI_SOFT,
478 ARM_FLOAT_ABI_SOFTFP,
479 ARM_FLOAT_ABI_HARD
480 };
481
482 extern enum float_abi_type arm_float_abi;
483
484 #ifndef TARGET_DEFAULT_FLOAT_ABI
485 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
486 #endif
487
488 /* Which ABI to use. */
489 enum arm_abi_type
490 {
491 ARM_ABI_APCS,
492 ARM_ABI_ATPCS,
493 ARM_ABI_AAPCS,
494 ARM_ABI_IWMMXT
495 };
496
497 extern enum arm_abi_type arm_abi;
498
499 #ifndef ARM_DEFAULT_ABI
500 #define ARM_DEFAULT_ABI ARM_ABI_APCS
501 #endif
502
503 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
504 extern int arm_arch3m;
505
506 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
507 extern int arm_arch4;
508
509 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
510 extern int arm_arch4t;
511
512 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
513 extern int arm_arch5;
514
515 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
516 extern int arm_arch5e;
517
518 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
519 extern int arm_arch6;
520
521 /* Nonzero if this chip can benefit from load scheduling. */
522 extern int arm_ld_sched;
523
524 /* Nonzero if generating thumb code. */
525 extern int thumb_code;
526
527 /* Nonzero if this chip is a StrongARM. */
528 extern int arm_is_strong;
529
530 /* Nonzero if this chip is a Cirrus variant. */
531 extern int arm_arch_cirrus;
532
533 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
534 extern int arm_arch_iwmmxt;
535
536 /* Nonzero if this chip is an XScale. */
537 extern int arm_arch_xscale;
538
539 /* Nonzero if tuning for XScale */
540 extern int arm_tune_xscale;
541
542 /* Nonzero if this chip is an ARM6 or an ARM7. */
543 extern int arm_is_6_or_7;
544
545 /* Nonzero if we should define __THUMB_INTERWORK__ in the
546 preprocessor.
547 XXX This is a bit of a hack, it's intended to help work around
548 problems in GLD which doesn't understand that armv5t code is
549 interworking clean. */
550 extern int arm_cpp_interwork;
551
552 #ifndef TARGET_DEFAULT
553 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
554 #endif
555
556 /* The frame pointer register used in gcc has nothing to do with debugging;
557 that is controlled by the APCS-FRAME option. */
558 #define CAN_DEBUG_WITHOUT_FP
559
560 #define OVERRIDE_OPTIONS arm_override_options ()
561
562 /* Nonzero if PIC code requires explicit qualifiers to generate
563 PLT and GOT relocs rather than the assembler doing so implicitly.
564 Subtargets can override these if required. */
565 #ifndef NEED_GOT_RELOC
566 #define NEED_GOT_RELOC 0
567 #endif
568 #ifndef NEED_PLT_RELOC
569 #define NEED_PLT_RELOC 0
570 #endif
571
572 /* Nonzero if we need to refer to the GOT with a PC-relative
573 offset. In other words, generate
574
575 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
576
577 rather than
578
579 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
580
581 The default is true, which matches NetBSD. Subtargets can
582 override this if required. */
583 #ifndef GOT_PCREL
584 #define GOT_PCREL 1
585 #endif
586 \f
587 /* Target machine storage Layout. */
588
589
590 /* Define this macro if it is advisable to hold scalars in registers
591 in a wider mode than that declared by the program. In such cases,
592 the value is constrained to be within the bounds of the declared
593 type, but kept valid in the wider mode. The signedness of the
594 extension may differ from that of the type. */
595
596 /* It is far faster to zero extend chars than to sign extend them */
597
598 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
599 if (GET_MODE_CLASS (MODE) == MODE_INT \
600 && GET_MODE_SIZE (MODE) < 4) \
601 { \
602 if (MODE == QImode) \
603 UNSIGNEDP = 1; \
604 else if (MODE == HImode) \
605 UNSIGNEDP = 1; \
606 (MODE) = SImode; \
607 }
608
609 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
610 if (GET_MODE_CLASS (MODE) == MODE_INT \
611 && GET_MODE_SIZE (MODE) < 4) \
612 (MODE) = SImode; \
613
614 /* Define this if most significant bit is lowest numbered
615 in instructions that operate on numbered bit-fields. */
616 #define BITS_BIG_ENDIAN 0
617
618 /* Define this if most significant byte of a word is the lowest numbered.
619 Most ARM processors are run in little endian mode, so that is the default.
620 If you want to have it run-time selectable, change the definition in a
621 cover file to be TARGET_BIG_ENDIAN. */
622 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
623
624 /* Define this if most significant word of a multiword number is the lowest
625 numbered.
626 This is always false, even when in big-endian mode. */
627 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
628
629 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
630 on processor pre-defineds when compiling libgcc2.c. */
631 #if defined(__ARMEB__) && !defined(__ARMWEL__)
632 #define LIBGCC2_WORDS_BIG_ENDIAN 1
633 #else
634 #define LIBGCC2_WORDS_BIG_ENDIAN 0
635 #endif
636
637 /* Define this if most significant word of doubles is the lowest numbered.
638 The rules are different based on whether or not we use FPA-format,
639 VFP-format or some other floating point co-processor's format doubles. */
640 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
641
642 #define UNITS_PER_WORD 4
643
644 /* True if natural alignment is used for doubleword types. */
645 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
646
647 #define DOUBLEWORD_ALIGNMENT 64
648
649 #define PARM_BOUNDARY 32
650
651 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
652
653 #define PREFERRED_STACK_BOUNDARY \
654 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
655
656 #define FUNCTION_BOUNDARY 32
657
658 /* The lowest bit is used to indicate Thumb-mode functions, so the
659 vbit must go into the delta field of pointers to member
660 functions. */
661 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
662
663 #define EMPTY_FIELD_BOUNDARY 32
664
665 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
666
667 /* XXX Blah -- this macro is used directly by libobjc. Since it
668 supports no vector modes, cut out the complexity and fall back
669 on BIGGEST_FIELD_ALIGNMENT. */
670 #ifdef IN_TARGET_LIBS
671 #define BIGGEST_FIELD_ALIGNMENT 64
672 #endif
673
674 /* Make strings word-aligned so strcpy from constants will be faster. */
675 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
676
677 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
678 ((TREE_CODE (EXP) == STRING_CST \
679 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
680 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
681
682 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
683 value set in previous versions of this toolchain was 8, which produces more
684 compact structures. The command line option -mstructure_size_boundary=<n>
685 can be used to change this value. For compatibility with the ARM SDK
686 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
687 0020D) page 2-20 says "Structures are aligned on word boundaries".
688 The AAPCS specifies a value of 8. */
689 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
690 extern int arm_structure_size_boundary;
691
692 /* This is the value used to initialize arm_structure_size_boundary. If a
693 particular arm target wants to change the default value it should change
694 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
695 for an example of this. */
696 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
697 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
698 #endif
699
700 /* Used when parsing command line option -mstructure_size_boundary. */
701 extern const char * structure_size_string;
702
703 /* Nonzero if move instructions will actually fail to work
704 when given unaligned data. */
705 #define STRICT_ALIGNMENT 1
706
707 /* wchar_t is unsigned under the AAPCS. */
708 #ifndef WCHAR_TYPE
709 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
710
711 #define WCHAR_TYPE_SIZE BITS_PER_WORD
712 #endif
713
714 #ifndef SIZE_TYPE
715 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
716 #endif
717
718 /* AAPCS requires that structure alignment is affected by bitfields. */
719 #ifndef PCC_BITFIELD_TYPE_MATTERS
720 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
721 #endif
722
723 \f
724 /* Standard register usage. */
725
726 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
727 (S - saved over call).
728
729 r0 * argument word/integer result
730 r1-r3 argument word
731
732 r4-r8 S register variable
733 r9 S (rfp) register variable (real frame pointer)
734
735 r10 F S (sl) stack limit (used by -mapcs-stack-check)
736 r11 F S (fp) argument pointer
737 r12 (ip) temp workspace
738 r13 F S (sp) lower end of current stack frame
739 r14 (lr) link address/workspace
740 r15 F (pc) program counter
741
742 f0 floating point result
743 f1-f3 floating point scratch
744
745 f4-f7 S floating point variable
746
747 cc This is NOT a real register, but is used internally
748 to represent things that use or set the condition
749 codes.
750 sfp This isn't either. It is used during rtl generation
751 since the offset between the frame pointer and the
752 auto's isn't known until after register allocation.
753 afp Nor this, we only need this because of non-local
754 goto. Without it fp appears to be used and the
755 elimination code won't get rid of sfp. It tracks
756 fp exactly at all times.
757
758 *: See CONDITIONAL_REGISTER_USAGE */
759
760 /*
761 mvf0 Cirrus floating point result
762 mvf1-mvf3 Cirrus floating point scratch
763 mvf4-mvf15 S Cirrus floating point variable. */
764
765 /* s0-s15 VFP scratch (aka d0-d7).
766 s16-s31 S VFP variable (aka d8-d15).
767 vfpcc Not a real register. Represents the VFP condition
768 code flags. */
769
770 /* The stack backtrace structure is as follows:
771 fp points to here: | save code pointer | [fp]
772 | return link value | [fp, #-4]
773 | return sp value | [fp, #-8]
774 | return fp value | [fp, #-12]
775 [| saved r10 value |]
776 [| saved r9 value |]
777 [| saved r8 value |]
778 [| saved r7 value |]
779 [| saved r6 value |]
780 [| saved r5 value |]
781 [| saved r4 value |]
782 [| saved r3 value |]
783 [| saved r2 value |]
784 [| saved r1 value |]
785 [| saved r0 value |]
786 [| saved f7 value |] three words
787 [| saved f6 value |] three words
788 [| saved f5 value |] three words
789 [| saved f4 value |] three words
790 r0-r3 are not normally saved in a C function. */
791
792 /* 1 for registers that have pervasive standard uses
793 and are not available for the register allocator. */
794 #define FIXED_REGISTERS \
795 { \
796 0,0,0,0,0,0,0,0, \
797 0,0,0,0,0,1,0,1, \
798 0,0,0,0,0,0,0,0, \
799 1,1,1, \
800 1,1,1,1,1,1,1,1, \
801 1,1,1,1,1,1,1,1, \
802 1,1,1,1,1,1,1,1, \
803 1,1,1,1,1,1,1,1, \
804 1,1,1,1, \
805 1,1,1,1,1,1,1,1, \
806 1,1,1,1,1,1,1,1, \
807 1,1,1,1,1,1,1,1, \
808 1,1,1,1,1,1,1,1, \
809 1 \
810 }
811
812 /* 1 for registers not available across function calls.
813 These must include the FIXED_REGISTERS and also any
814 registers that can be used without being saved.
815 The latter must include the registers where values are returned
816 and the register where structure-value addresses are passed.
817 Aside from that, you can include as many other registers as you like.
818 The CC is not preserved over function calls on the ARM 6, so it is
819 easier to assume this for all. SFP is preserved, since FP is. */
820 #define CALL_USED_REGISTERS \
821 { \
822 1,1,1,1,0,0,0,0, \
823 0,0,0,0,1,1,1,1, \
824 1,1,1,1,0,0,0,0, \
825 1,1,1, \
826 1,1,1,1,1,1,1,1, \
827 1,1,1,1,1,1,1,1, \
828 1,1,1,1,1,1,1,1, \
829 1,1,1,1,1,1,1,1, \
830 1,1,1,1, \
831 1,1,1,1,1,1,1,1, \
832 1,1,1,1,1,1,1,1, \
833 1,1,1,1,1,1,1,1, \
834 1,1,1,1,1,1,1,1, \
835 1 \
836 }
837
838 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
839 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
840 #endif
841
842 #define CONDITIONAL_REGISTER_USAGE \
843 { \
844 int regno; \
845 \
846 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
847 { \
848 for (regno = FIRST_FPA_REGNUM; \
849 regno <= LAST_FPA_REGNUM; ++regno) \
850 fixed_regs[regno] = call_used_regs[regno] = 1; \
851 } \
852 \
853 if (TARGET_THUMB && optimize_size) \
854 { \
855 /* When optimizing for size, it's better not to use \
856 the HI regs, because of the overhead of stacking \
857 them. */ \
858 for (regno = FIRST_HI_REGNUM; \
859 regno <= LAST_HI_REGNUM; ++regno) \
860 fixed_regs[regno] = call_used_regs[regno] = 1; \
861 } \
862 \
863 /* The link register can be clobbered by any branch insn, \
864 but we have no way to track that at present, so mark \
865 it as unavailable. */ \
866 if (TARGET_THUMB) \
867 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
868 \
869 if (TARGET_ARM && TARGET_HARD_FLOAT) \
870 { \
871 if (TARGET_MAVERICK) \
872 { \
873 for (regno = FIRST_FPA_REGNUM; \
874 regno <= LAST_FPA_REGNUM; ++ regno) \
875 fixed_regs[regno] = call_used_regs[regno] = 1; \
876 for (regno = FIRST_CIRRUS_FP_REGNUM; \
877 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
878 { \
879 fixed_regs[regno] = 0; \
880 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
881 } \
882 } \
883 if (TARGET_VFP) \
884 { \
885 for (regno = FIRST_VFP_REGNUM; \
886 regno <= LAST_VFP_REGNUM; ++ regno) \
887 { \
888 fixed_regs[regno] = 0; \
889 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
890 } \
891 } \
892 } \
893 \
894 if (TARGET_REALLY_IWMMXT) \
895 { \
896 regno = FIRST_IWMMXT_GR_REGNUM; \
897 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
898 and wCG1 as call-preserved registers. The 2002/11/21 \
899 revision changed this so that all wCG registers are \
900 scratch registers. */ \
901 for (regno = FIRST_IWMMXT_GR_REGNUM; \
902 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
903 fixed_regs[regno] = 0; \
904 /* The XScale ABI has wR0 - wR9 as scratch registers, \
905 the rest as call-preserved registers. */ \
906 for (regno = FIRST_IWMMXT_REGNUM; \
907 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
908 { \
909 fixed_regs[regno] = 0; \
910 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
911 } \
912 } \
913 \
914 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
915 { \
916 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
917 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
918 } \
919 else if (TARGET_APCS_STACK) \
920 { \
921 fixed_regs[10] = 1; \
922 call_used_regs[10] = 1; \
923 } \
924 /* -mcaller-super-interworking reserves r11 for calls to \
925 _interwork_r11_call_via_rN(). Making the register global \
926 is an easy way of ensuring that it remains valid for all \
927 calls. */ \
928 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING) \
929 { \
930 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
931 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
932 if (TARGET_CALLER_INTERWORKING) \
933 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
934 } \
935 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
936 }
937
938 /* These are a couple of extensions to the formats accepted
939 by asm_fprintf:
940 %@ prints out ASM_COMMENT_START
941 %r prints out REGISTER_PREFIX reg_names[arg] */
942 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
943 case '@': \
944 fputs (ASM_COMMENT_START, FILE); \
945 break; \
946 \
947 case 'r': \
948 fputs (REGISTER_PREFIX, FILE); \
949 fputs (reg_names [va_arg (ARGS, int)], FILE); \
950 break;
951
952 /* Round X up to the nearest word. */
953 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
954
955 /* Convert fron bytes to ints. */
956 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
957
958 /* The number of (integer) registers required to hold a quantity of type MODE.
959 Also used for VFP registers. */
960 #define ARM_NUM_REGS(MODE) \
961 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
962
963 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
964 #define ARM_NUM_REGS2(MODE, TYPE) \
965 ARM_NUM_INTS ((MODE) == BLKmode ? \
966 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
967
968 /* The number of (integer) argument register available. */
969 #define NUM_ARG_REGS 4
970
971 /* Return the register number of the N'th (integer) argument. */
972 #define ARG_REGISTER(N) (N - 1)
973
974 /* Specify the registers used for certain standard purposes.
975 The values of these macros are register numbers. */
976
977 /* The number of the last argument register. */
978 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
979
980 /* The numbers of the Thumb register ranges. */
981 #define FIRST_LO_REGNUM 0
982 #define LAST_LO_REGNUM 7
983 #define FIRST_HI_REGNUM 8
984 #define LAST_HI_REGNUM 11
985
986 /* We use sjlj exceptions for backwards compatibility. */
987 #define MUST_USE_SJLJ_EXCEPTIONS 1
988 /* We can generate DWARF2 Unwind info, even though we don't use it. */
989 #define DWARF2_UNWIND_INFO 1
990
991 /* Use r0 and r1 to pass exception handling information. */
992 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
993
994 /* The register that holds the return address in exception handlers. */
995 #define ARM_EH_STACKADJ_REGNUM 2
996 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
997
998 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
999 as an invisible last argument (possible since varargs don't exist in
1000 Pascal), so the following is not true. */
1001 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1002
1003 /* Define this to be where the real frame pointer is if it is not possible to
1004 work out the offset between the frame pointer and the automatic variables
1005 until after register allocation has taken place. FRAME_POINTER_REGNUM
1006 should point to a special register that we will make sure is eliminated.
1007
1008 For the Thumb we have another problem. The TPCS defines the frame pointer
1009 as r11, and GCC believes that it is always possible to use the frame pointer
1010 as base register for addressing purposes. (See comments in
1011 find_reloads_address()). But - the Thumb does not allow high registers,
1012 including r11, to be used as base address registers. Hence our problem.
1013
1014 The solution used here, and in the old thumb port is to use r7 instead of
1015 r11 as the hard frame pointer and to have special code to generate
1016 backtrace structures on the stack (if required to do so via a command line
1017 option) using r11. This is the only 'user visible' use of r11 as a frame
1018 pointer. */
1019 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1020 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1021
1022 #define HARD_FRAME_POINTER_REGNUM \
1023 (TARGET_ARM \
1024 ? ARM_HARD_FRAME_POINTER_REGNUM \
1025 : THUMB_HARD_FRAME_POINTER_REGNUM)
1026
1027 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1028
1029 /* Register to use for pushing function arguments. */
1030 #define STACK_POINTER_REGNUM SP_REGNUM
1031
1032 /* ARM floating pointer registers. */
1033 #define FIRST_FPA_REGNUM 16
1034 #define LAST_FPA_REGNUM 23
1035 #define IS_FPA_REGNUM(REGNUM) \
1036 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
1037
1038 #define FIRST_IWMMXT_GR_REGNUM 43
1039 #define LAST_IWMMXT_GR_REGNUM 46
1040 #define FIRST_IWMMXT_REGNUM 47
1041 #define LAST_IWMMXT_REGNUM 62
1042 #define IS_IWMMXT_REGNUM(REGNUM) \
1043 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1044 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1045 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1046
1047 /* Base register for access to local variables of the function. */
1048 #define FRAME_POINTER_REGNUM 25
1049
1050 /* Base register for access to arguments of the function. */
1051 #define ARG_POINTER_REGNUM 26
1052
1053 #define FIRST_CIRRUS_FP_REGNUM 27
1054 #define LAST_CIRRUS_FP_REGNUM 42
1055 #define IS_CIRRUS_REGNUM(REGNUM) \
1056 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1057
1058 #define FIRST_VFP_REGNUM 63
1059 #define LAST_VFP_REGNUM 94
1060 #define IS_VFP_REGNUM(REGNUM) \
1061 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1062
1063 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1064 /* + 16 Cirrus registers take us up to 43. */
1065 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1066 /* VFP adds 32 + 1 more. */
1067 #define FIRST_PSEUDO_REGISTER 96
1068
1069 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1070
1071 /* Value should be nonzero if functions must have frame pointers.
1072 Zero means the frame pointer need not be set up (and parms may be accessed
1073 via the stack pointer) in functions that seem suitable.
1074 If we have to have a frame pointer we might as well make use of it.
1075 APCS says that the frame pointer does not need to be pushed in leaf
1076 functions, or simple tail call functions. */
1077 #define FRAME_POINTER_REQUIRED \
1078 (current_function_has_nonlocal_label \
1079 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1080
1081 /* Return number of consecutive hard regs needed starting at reg REGNO
1082 to hold something of mode MODE.
1083 This is ordinarily the length in words of a value of mode MODE
1084 but can be less for certain modes in special long registers.
1085
1086 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1087 mode. */
1088 #define HARD_REGNO_NREGS(REGNO, MODE) \
1089 ((TARGET_ARM \
1090 && REGNO >= FIRST_FPA_REGNUM \
1091 && REGNO != FRAME_POINTER_REGNUM \
1092 && REGNO != ARG_POINTER_REGNUM) \
1093 && !IS_VFP_REGNUM (REGNO) \
1094 ? 1 : ARM_NUM_REGS (MODE))
1095
1096 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1097 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1098 arm_hard_regno_mode_ok ((REGNO), (MODE))
1099
1100 /* Value is 1 if it is a good idea to tie two pseudo registers
1101 when one has mode MODE1 and one has mode MODE2.
1102 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1103 for any hard reg, then this must be 0 for correct output. */
1104 #define MODES_TIEABLE_P(MODE1, MODE2) \
1105 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1106
1107 #define VALID_IWMMXT_REG_MODE(MODE) \
1108 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1109
1110 /* The order in which register should be allocated. It is good to use ip
1111 since no saving is required (though calls clobber it) and it never contains
1112 function parameters. It is quite good to use lr since other calls may
1113 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1114 least likely to contain a function parameter; in addition results are
1115 returned in r0. */
1116
1117 #define REG_ALLOC_ORDER \
1118 { \
1119 3, 2, 1, 0, 12, 14, 4, 5, \
1120 6, 7, 8, 10, 9, 11, 13, 15, \
1121 16, 17, 18, 19, 20, 21, 22, 23, \
1122 27, 28, 29, 30, 31, 32, 33, 34, \
1123 35, 36, 37, 38, 39, 40, 41, 42, \
1124 43, 44, 45, 46, 47, 48, 49, 50, \
1125 51, 52, 53, 54, 55, 56, 57, 58, \
1126 59, 60, 61, 62, \
1127 24, 25, 26, \
1128 78, 77, 76, 75, 74, 73, 72, 71, \
1129 70, 69, 68, 67, 66, 65, 64, 63, \
1130 79, 80, 81, 82, 83, 84, 85, 86, \
1131 87, 88, 89, 90, 91, 92, 93, 94, \
1132 95 \
1133 }
1134
1135 /* Interrupt functions can only use registers that have already been
1136 saved by the prologue, even if they would normally be
1137 call-clobbered. */
1138 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1139 (! IS_INTERRUPT (cfun->machine->func_type) || \
1140 regs_ever_live[DST])
1141 \f
1142 /* Register and constant classes. */
1143
1144 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1145 Now that the Thumb is involved it has become more complicated. */
1146 enum reg_class
1147 {
1148 NO_REGS,
1149 FPA_REGS,
1150 CIRRUS_REGS,
1151 VFP_REGS,
1152 IWMMXT_GR_REGS,
1153 IWMMXT_REGS,
1154 LO_REGS,
1155 STACK_REG,
1156 BASE_REGS,
1157 HI_REGS,
1158 CC_REG,
1159 VFPCC_REG,
1160 GENERAL_REGS,
1161 ALL_REGS,
1162 LIM_REG_CLASSES
1163 };
1164
1165 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1166
1167 /* Give names of register classes as strings for dump file. */
1168 #define REG_CLASS_NAMES \
1169 { \
1170 "NO_REGS", \
1171 "FPA_REGS", \
1172 "CIRRUS_REGS", \
1173 "VFP_REGS", \
1174 "IWMMXT_GR_REGS", \
1175 "IWMMXT_REGS", \
1176 "LO_REGS", \
1177 "STACK_REG", \
1178 "BASE_REGS", \
1179 "HI_REGS", \
1180 "CC_REG", \
1181 "VFPCC_REG", \
1182 "GENERAL_REGS", \
1183 "ALL_REGS", \
1184 }
1185
1186 /* Define which registers fit in which classes.
1187 This is an initializer for a vector of HARD_REG_SET
1188 of length N_REG_CLASSES. */
1189 #define REG_CLASS_CONTENTS \
1190 { \
1191 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1192 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1193 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1194 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1195 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1196 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1197 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1198 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1199 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1200 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1201 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1202 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1203 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1204 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1205 }
1206
1207 /* The same information, inverted:
1208 Return the class number of the smallest class containing
1209 reg number REGNO. This could be a conditional expression
1210 or could index an array. */
1211 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1212
1213 /* FPA registers can't do subreg as all values are reformatted to internal
1214 precision. VFP registers may only be accessed in the mode they
1215 were set. */
1216 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1217 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1218 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1219 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1220 : 0)
1221
1222 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1223 using r0-r4 for function arguments, r7 for the stack frame and don't
1224 have enough left over to do doubleword arithmetic. */
1225 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1226 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1227 || (CLASS) == CC_REG)
1228
1229 /* The class value for index registers, and the one for base regs. */
1230 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1231 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1232
1233 /* For the Thumb the high registers cannot be used as base registers
1234 when addressing quantities in QI or HI mode; if we don't know the
1235 mode, then we must be conservative. */
1236 #define MODE_BASE_REG_CLASS(MODE) \
1237 (TARGET_ARM ? GENERAL_REGS : \
1238 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1239
1240 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1241 instead of BASE_REGS. */
1242 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1243
1244 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1245 registers explicitly used in the rtl to be used as spill registers
1246 but prevents the compiler from extending the lifetime of these
1247 registers. */
1248 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1249
1250 /* Get reg_class from a letter such as appears in the machine description.
1251 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1252 ARM, but several more letters for the Thumb. */
1253 #define REG_CLASS_FROM_LETTER(C) \
1254 ( (C) == 'f' ? FPA_REGS \
1255 : (C) == 'v' ? CIRRUS_REGS \
1256 : (C) == 'w' ? VFP_REGS \
1257 : (C) == 'y' ? IWMMXT_REGS \
1258 : (C) == 'z' ? IWMMXT_GR_REGS \
1259 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1260 : TARGET_ARM ? NO_REGS \
1261 : (C) == 'h' ? HI_REGS \
1262 : (C) == 'b' ? BASE_REGS \
1263 : (C) == 'k' ? STACK_REG \
1264 : (C) == 'c' ? CC_REG \
1265 : NO_REGS)
1266
1267 /* The letters I, J, K, L and M in a register constraint string
1268 can be used to stand for particular ranges of immediate operands.
1269 This macro defines what the ranges are.
1270 C is the letter, and VALUE is a constant value.
1271 Return 1 if VALUE is in the range specified by C.
1272 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1273 J: valid indexing constants.
1274 K: ~value ok in rhs argument of data operand.
1275 L: -value ok in rhs argument of data operand.
1276 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1277 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1278 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1279 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1280 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1281 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1282 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1283 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1284 : 0)
1285
1286 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1287 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1288 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1289 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1290 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1291 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1292 && ((VAL) & 3) == 0) : \
1293 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1294 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1295 : 0)
1296
1297 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1298 (TARGET_ARM ? \
1299 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1300
1301 /* Constant letter 'G' for the FP immediate constants.
1302 'H' means the same constant negated. */
1303 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1304 ((C) == 'G' ? arm_const_double_rtx (X) : \
1305 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1306
1307 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1308 (TARGET_ARM ? \
1309 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1310
1311 /* For the ARM, `Q' means that this is a memory operand that is just
1312 an offset from a register.
1313 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1314 address. This means that the symbol is in the text segment and can be
1315 accessed without using a load.
1316 'D' Prefixes a number of const_double operands where:
1317 'Da' is a constant that takes two ARM insns to load.
1318 'Db' takes three ARM insns.
1319 'Dc' takes four ARM insns, if we allow that in this compilation.
1320 'U' Prefixes an extended memory constraint where:
1321 'Uv' is an address valid for VFP load/store insns.
1322 'Uy' is an address valid for iwmmxt load/store insns.
1323 'Uq' is an address valid for ldrsb. */
1324
1325 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1326 (((C) == 'D') ? (GET_CODE (OP) == CONST_DOUBLE \
1327 && (((STR)[1] == 'a' \
1328 && arm_const_double_inline_cost (OP) == 2) \
1329 || ((STR)[1] == 'b' \
1330 && arm_const_double_inline_cost (OP) == 3) \
1331 || ((STR)[1] == 'c' \
1332 && arm_const_double_inline_cost (OP) == 4 \
1333 && !(optimize_size || arm_ld_sched)))) : \
1334 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1335 && GET_CODE (XEXP (OP, 0)) == REG) : \
1336 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1337 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1338 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1339 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1340 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1341 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1342 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1343 ((C) == 'U' && (STR)[1] == 'q') \
1344 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1345 : 0)
1346
1347 #define CONSTRAINT_LEN(C,STR) \
1348 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1349
1350 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1351 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1352 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1353
1354 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1355 (TARGET_ARM \
1356 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1357 : EXTRA_CONSTRAINT_THUMB (X, C))
1358
1359 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1360
1361 /* Given an rtx X being reloaded into a reg required to be
1362 in class CLASS, return the class of reg to actually use.
1363 In general this is just CLASS, but for the Thumb we prefer
1364 a LO_REGS class or a subset. */
1365 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1366 (TARGET_ARM ? (CLASS) : \
1367 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1368
1369 /* Must leave BASE_REGS reloads alone */
1370 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1371 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1372 ? ((true_regnum (X) == -1 ? LO_REGS \
1373 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1374 : NO_REGS)) \
1375 : NO_REGS)
1376
1377 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1378 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1379 ? ((true_regnum (X) == -1 ? LO_REGS \
1380 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1381 : NO_REGS)) \
1382 : NO_REGS)
1383
1384 /* Return the register class of a scratch register needed to copy IN into
1385 or out of a register in CLASS in MODE. If it can be done directly,
1386 NO_REGS is returned. */
1387 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1388 /* Restrict which direct reloads are allowed for VFP regs. */ \
1389 ((TARGET_VFP && TARGET_HARD_FLOAT \
1390 && (CLASS) == VFP_REGS) \
1391 ? vfp_secondary_reload_class (MODE, X) \
1392 : TARGET_ARM \
1393 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1394 ? GENERAL_REGS : NO_REGS) \
1395 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1396
1397 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1398 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1399 /* Restrict which direct reloads are allowed for VFP regs. */ \
1400 ((TARGET_VFP && TARGET_HARD_FLOAT \
1401 && (CLASS) == VFP_REGS) \
1402 ? vfp_secondary_reload_class (MODE, X) : \
1403 /* Cannot load constants into Cirrus registers. */ \
1404 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1405 && (CLASS) == CIRRUS_REGS \
1406 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1407 ? GENERAL_REGS : \
1408 (TARGET_ARM ? \
1409 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1410 && CONSTANT_P (X)) \
1411 ? GENERAL_REGS : \
1412 (((MODE) == HImode && ! arm_arch4 \
1413 && (GET_CODE (X) == MEM \
1414 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1415 && true_regnum (X) == -1))) \
1416 ? GENERAL_REGS : NO_REGS) \
1417 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1418
1419 /* Try a machine-dependent way of reloading an illegitimate address
1420 operand. If we find one, push the reload and jump to WIN. This
1421 macro is used in only one place: `find_reloads_address' in reload.c.
1422
1423 For the ARM, we wish to handle large displacements off a base
1424 register by splitting the addend across a MOV and the mem insn.
1425 This can cut the number of reloads needed. */
1426 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1427 do \
1428 { \
1429 if (GET_CODE (X) == PLUS \
1430 && GET_CODE (XEXP (X, 0)) == REG \
1431 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1432 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1433 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1434 { \
1435 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1436 HOST_WIDE_INT low, high; \
1437 \
1438 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1439 low = ((val & 0xf) ^ 0x8) - 0x8; \
1440 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1441 /* Need to be careful, -256 is not a valid offset. */ \
1442 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1443 else if (MODE == SImode \
1444 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1445 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1446 /* Need to be careful, -4096 is not a valid offset. */ \
1447 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1448 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1449 /* Need to be careful, -256 is not a valid offset. */ \
1450 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1451 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1452 && TARGET_HARD_FLOAT && TARGET_FPA) \
1453 /* Need to be careful, -1024 is not a valid offset. */ \
1454 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1455 else \
1456 break; \
1457 \
1458 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1459 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1460 - (unsigned HOST_WIDE_INT) 0x80000000); \
1461 /* Check for overflow or zero */ \
1462 if (low == 0 || high == 0 || (high + low != val)) \
1463 break; \
1464 \
1465 /* Reload the high part into a base reg; leave the low part \
1466 in the mem. */ \
1467 X = gen_rtx_PLUS (GET_MODE (X), \
1468 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1469 GEN_INT (high)), \
1470 GEN_INT (low)); \
1471 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1472 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1473 VOIDmode, 0, 0, OPNUM, TYPE); \
1474 goto WIN; \
1475 } \
1476 } \
1477 while (0)
1478
1479 /* XXX If an HImode FP+large_offset address is converted to an HImode
1480 SP+large_offset address, then reload won't know how to fix it. It sees
1481 only that SP isn't valid for HImode, and so reloads the SP into an index
1482 register, but the resulting address is still invalid because the offset
1483 is too big. We fix it here instead by reloading the entire address. */
1484 /* We could probably achieve better results by defining PROMOTE_MODE to help
1485 cope with the variances between the Thumb's signed and unsigned byte and
1486 halfword load instructions. */
1487 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1488 { \
1489 if (GET_CODE (X) == PLUS \
1490 && GET_MODE_SIZE (MODE) < 4 \
1491 && GET_CODE (XEXP (X, 0)) == REG \
1492 && XEXP (X, 0) == stack_pointer_rtx \
1493 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1494 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1495 { \
1496 rtx orig_X = X; \
1497 X = copy_rtx (X); \
1498 push_reload (orig_X, NULL_RTX, &X, NULL, \
1499 MODE_BASE_REG_CLASS (MODE), \
1500 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1501 goto WIN; \
1502 } \
1503 }
1504
1505 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1506 if (TARGET_ARM) \
1507 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1508 else \
1509 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1510
1511 /* Return the maximum number of consecutive registers
1512 needed to represent mode MODE in a register of class CLASS.
1513 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1514 #define CLASS_MAX_NREGS(CLASS, MODE) \
1515 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1516
1517 /* If defined, gives a class of registers that cannot be used as the
1518 operand of a SUBREG that changes the mode of the object illegally. */
1519
1520 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1521 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1522 (TARGET_ARM ? \
1523 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1524 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1525 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1526 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1527 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1528 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1529 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1530 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1531 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1532 2) \
1533 : \
1534 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1535 \f
1536 /* Stack layout; function entry, exit and calling. */
1537
1538 /* Define this if pushing a word on the stack
1539 makes the stack pointer a smaller address. */
1540 #define STACK_GROWS_DOWNWARD 1
1541
1542 /* Define this if the nominal address of the stack frame
1543 is at the high-address end of the local variables;
1544 that is, each additional local variable allocated
1545 goes at a more negative offset in the frame. */
1546 #define FRAME_GROWS_DOWNWARD 1
1547
1548 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1549 When present, it is one word in size, and sits at the top of the frame,
1550 between the soft frame pointer and either r7 or r11.
1551
1552 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1553 and only then if some outgoing arguments are passed on the stack. It would
1554 be tempting to also check whether the stack arguments are passed by indirect
1555 calls, but there seems to be no reason in principle why a post-reload pass
1556 couldn't convert a direct call into an indirect one. */
1557 #define CALLER_INTERWORKING_SLOT_SIZE \
1558 (TARGET_CALLER_INTERWORKING \
1559 && current_function_outgoing_args_size != 0 \
1560 ? UNITS_PER_WORD : 0)
1561
1562 /* Offset within stack frame to start allocating local variables at.
1563 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1564 first local allocated. Otherwise, it is the offset to the BEGINNING
1565 of the first local allocated. */
1566 #define STARTING_FRAME_OFFSET 0
1567
1568 /* If we generate an insn to push BYTES bytes,
1569 this says how many the stack pointer really advances by. */
1570 /* The push insns do not do this rounding implicitly.
1571 So don't define this. */
1572 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1573
1574 /* Define this if the maximum size of all the outgoing args is to be
1575 accumulated and pushed during the prologue. The amount can be
1576 found in the variable current_function_outgoing_args_size. */
1577 #define ACCUMULATE_OUTGOING_ARGS 1
1578
1579 /* Offset of first parameter from the argument pointer register value. */
1580 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1581
1582 /* Value is the number of byte of arguments automatically
1583 popped when returning from a subroutine call.
1584 FUNDECL is the declaration node of the function (as a tree),
1585 FUNTYPE is the data type of the function (as a tree),
1586 or for a library call it is an identifier node for the subroutine name.
1587 SIZE is the number of bytes of arguments passed on the stack.
1588
1589 On the ARM, the caller does not pop any of its arguments that were passed
1590 on the stack. */
1591 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1592
1593 /* Define how to find the value returned by a library function
1594 assuming the value has mode MODE. */
1595 #define LIBCALL_VALUE(MODE) \
1596 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1597 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1598 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1599 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1600 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1601 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1602 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1603 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1604 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1605
1606 /* Define how to find the value returned by a function.
1607 VALTYPE is the data type of the value (as a tree).
1608 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1609 otherwise, FUNC is 0. */
1610 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1611 arm_function_value (VALTYPE, FUNC);
1612
1613 /* 1 if N is a possible register number for a function value.
1614 On the ARM, only r0 and f0 can return results. */
1615 /* On a Cirrus chip, mvf0 can return results. */
1616 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1617 ((REGNO) == ARG_REGISTER (1) \
1618 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1619 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1620 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1621 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1622 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1623
1624 /* Amount of memory needed for an untyped call to save all possible return
1625 registers. */
1626 #define APPLY_RESULT_SIZE arm_apply_result_size()
1627
1628 /* How large values are returned */
1629 /* A C expression which can inhibit the returning of certain function values
1630 in registers, based on the type of value. */
1631 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1632
1633 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1634 values must be in memory. On the ARM, they need only do so if larger
1635 than a word, or if they contain elements offset from zero in the struct. */
1636 #define DEFAULT_PCC_STRUCT_RETURN 0
1637
1638 /* Flags for the call/call_value rtl operations set up by function_arg. */
1639 #define CALL_NORMAL 0x00000000 /* No special processing. */
1640 #define CALL_LONG 0x00000001 /* Always call indirect. */
1641 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1642
1643 /* These bits describe the different types of function supported
1644 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1645 normal function and an interworked function, for example. Knowing the
1646 type of a function is important for determining its prologue and
1647 epilogue sequences.
1648 Note value 7 is currently unassigned. Also note that the interrupt
1649 function types all have bit 2 set, so that they can be tested for easily.
1650 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1651 machine_function structure is initialized (to zero) func_type will
1652 default to unknown. This will force the first use of arm_current_func_type
1653 to call arm_compute_func_type. */
1654 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1655 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1656 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1657 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1658 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1659 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1660
1661 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1662
1663 /* In addition functions can have several type modifiers,
1664 outlined by these bit masks: */
1665 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1666 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1667 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1668 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1669
1670 /* Some macros to test these flags. */
1671 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1672 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1673 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1674 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1675 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1676
1677
1678 /* Structure used to hold the function stack frame layout. Offsets are
1679 relative to the stack pointer on function entry. Positive offsets are
1680 in the direction of stack growth.
1681 Only soft_frame is used in thumb mode. */
1682
1683 typedef struct arm_stack_offsets GTY(())
1684 {
1685 int saved_args; /* ARG_POINTER_REGNUM. */
1686 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1687 int saved_regs;
1688 int soft_frame; /* FRAME_POINTER_REGNUM. */
1689 int outgoing_args; /* STACK_POINTER_REGNUM. */
1690 }
1691 arm_stack_offsets;
1692
1693 /* A C structure for machine-specific, per-function data.
1694 This is added to the cfun structure. */
1695 typedef struct machine_function GTY(())
1696 {
1697 /* Additional stack adjustment in __builtin_eh_throw. */
1698 rtx eh_epilogue_sp_ofs;
1699 /* Records if LR has to be saved for far jumps. */
1700 int far_jump_used;
1701 /* Records if ARG_POINTER was ever live. */
1702 int arg_pointer_live;
1703 /* Records if the save of LR has been eliminated. */
1704 int lr_save_eliminated;
1705 /* The size of the stack frame. Only valid after reload. */
1706 arm_stack_offsets stack_offsets;
1707 /* Records the type of the current function. */
1708 unsigned long func_type;
1709 /* Record if the function has a variable argument list. */
1710 int uses_anonymous_args;
1711 /* Records if sibcalls are blocked because an argument
1712 register is needed to preserve stack alignment. */
1713 int sibcall_blocked;
1714 /* Labels for per-function Thumb call-via stubs. One per potential calling
1715 register. We can never call via LR or PC. We can call via SP if a
1716 trampoline happens to be on the top of the stack. */
1717 rtx call_via[14];
1718 }
1719 machine_function;
1720
1721 /* As in the machine_function, a global set of call-via labels, for code
1722 that is in text_section(). */
1723 extern GTY(()) rtx thumb_call_via_label[14];
1724
1725 /* A C type for declaring a variable that is used as the first argument of
1726 `FUNCTION_ARG' and other related values. For some target machines, the
1727 type `int' suffices and can hold the number of bytes of argument so far. */
1728 typedef struct
1729 {
1730 /* This is the number of registers of arguments scanned so far. */
1731 int nregs;
1732 /* This is the number of iWMMXt register arguments scanned so far. */
1733 int iwmmxt_nregs;
1734 int named_count;
1735 int nargs;
1736 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1737 int call_cookie;
1738 int can_split;
1739 } CUMULATIVE_ARGS;
1740
1741 /* Define where to put the arguments to a function.
1742 Value is zero to push the argument on the stack,
1743 or a hard register in which to store the argument.
1744
1745 MODE is the argument's machine mode.
1746 TYPE is the data type of the argument (as a tree).
1747 This is null for libcalls where that information may
1748 not be available.
1749 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1750 the preceding args and about the function being called.
1751 NAMED is nonzero if this argument is a named parameter
1752 (otherwise it is an extra parameter matching an ellipsis).
1753
1754 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1755 other arguments are passed on the stack. If (NAMED == 0) (which happens
1756 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1757 defined), say it is passed in the stack (function_prologue will
1758 indeed make it pass in the stack if necessary). */
1759 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1760 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1761
1762 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1763 for a call to a function whose data type is FNTYPE.
1764 For a library call, FNTYPE is 0.
1765 On the ARM, the offset starts at 0. */
1766 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1767 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1768
1769 /* Update the data in CUM to advance over an argument
1770 of mode MODE and data type TYPE.
1771 (TYPE is null for libcalls where that information may not be available.) */
1772 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1773 (CUM).nargs += 1; \
1774 if (arm_vector_mode_supported_p (MODE) \
1775 && (CUM).named_count > (CUM).nargs) \
1776 (CUM).iwmmxt_nregs += 1; \
1777 else \
1778 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1779
1780 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1781 argument with the specified mode and type. If it is not defined,
1782 `PARM_BOUNDARY' is used for all arguments. */
1783 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1784 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1785 ? DOUBLEWORD_ALIGNMENT \
1786 : PARM_BOUNDARY )
1787
1788 /* 1 if N is a possible register number for function argument passing.
1789 On the ARM, r0-r3 are used to pass args. */
1790 #define FUNCTION_ARG_REGNO_P(REGNO) \
1791 (IN_RANGE ((REGNO), 0, 3) \
1792 || (TARGET_IWMMXT_ABI \
1793 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1794
1795 \f
1796 /* If your target environment doesn't prefix user functions with an
1797 underscore, you may wish to re-define this to prevent any conflicts.
1798 e.g. AOF may prefix mcount with an underscore. */
1799 #ifndef ARM_MCOUNT_NAME
1800 #define ARM_MCOUNT_NAME "*mcount"
1801 #endif
1802
1803 /* Call the function profiler with a given profile label. The Acorn
1804 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1805 On the ARM the full profile code will look like:
1806 .data
1807 LP1
1808 .word 0
1809 .text
1810 mov ip, lr
1811 bl mcount
1812 .word LP1
1813
1814 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1815 will output the .text section.
1816
1817 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1818 ``prof'' doesn't seem to mind about this!
1819
1820 Note - this version of the code is designed to work in both ARM and
1821 Thumb modes. */
1822 #ifndef ARM_FUNCTION_PROFILER
1823 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1824 { \
1825 char temp[20]; \
1826 rtx sym; \
1827 \
1828 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1829 IP_REGNUM, LR_REGNUM); \
1830 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1831 fputc ('\n', STREAM); \
1832 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1833 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1834 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1835 }
1836 #endif
1837
1838 #ifdef THUMB_FUNCTION_PROFILER
1839 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1840 if (TARGET_ARM) \
1841 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1842 else \
1843 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1844 #else
1845 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1846 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1847 #endif
1848
1849 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1850 the stack pointer does not matter. The value is tested only in
1851 functions that have frame pointers.
1852 No definition is equivalent to always zero.
1853
1854 On the ARM, the function epilogue recovers the stack pointer from the
1855 frame. */
1856 #define EXIT_IGNORE_STACK 1
1857
1858 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1859
1860 /* Determine if the epilogue should be output as RTL.
1861 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1862 #define USE_RETURN_INSN(ISCOND) \
1863 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1864
1865 /* Definitions for register eliminations.
1866
1867 This is an array of structures. Each structure initializes one pair
1868 of eliminable registers. The "from" register number is given first,
1869 followed by "to". Eliminations of the same "from" register are listed
1870 in order of preference.
1871
1872 We have two registers that can be eliminated on the ARM. First, the
1873 arg pointer register can often be eliminated in favor of the stack
1874 pointer register. Secondly, the pseudo frame pointer register can always
1875 be eliminated; it is replaced with either the stack or the real frame
1876 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1877 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1878
1879 #define ELIMINABLE_REGS \
1880 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1881 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1882 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1883 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1884 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1885 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1886 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1887
1888 /* Given FROM and TO register numbers, say whether this elimination is
1889 allowed. Frame pointer elimination is automatically handled.
1890
1891 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1892 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1893 pointer, we must eliminate FRAME_POINTER_REGNUM into
1894 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1895 ARG_POINTER_REGNUM. */
1896 #define CAN_ELIMINATE(FROM, TO) \
1897 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1898 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1899 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1900 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1901 1)
1902
1903 /* Define the offset between two registers, one to be eliminated, and the
1904 other its replacement, at the start of a routine. */
1905 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1906 if (TARGET_ARM) \
1907 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1908 else \
1909 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1910
1911 /* Special case handling of the location of arguments passed on the stack. */
1912 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1913
1914 /* Initialize data used by insn expanders. This is called from insn_emit,
1915 once for every function before code is generated. */
1916 #define INIT_EXPANDERS arm_init_expanders ()
1917
1918 /* Output assembler code for a block containing the constant parts
1919 of a trampoline, leaving space for the variable parts.
1920
1921 On the ARM, (if r8 is the static chain regnum, and remembering that
1922 referencing pc adds an offset of 8) the trampoline looks like:
1923 ldr r8, [pc, #0]
1924 ldr pc, [pc]
1925 .word static chain value
1926 .word function's address
1927 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1928 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1929 { \
1930 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1931 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1932 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1933 PC_REGNUM, PC_REGNUM); \
1934 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1935 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1936 }
1937
1938 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1939 Why - because it is easier. This code will always be branched to via
1940 a BX instruction and since the compiler magically generates the address
1941 of the function the linker has no opportunity to ensure that the
1942 bottom bit is set. Thus the processor will be in ARM mode when it
1943 reaches this code. So we duplicate the ARM trampoline code and add
1944 a switch into Thumb mode as well. */
1945 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1946 { \
1947 fprintf (FILE, "\t.code 32\n"); \
1948 fprintf (FILE, ".Ltrampoline_start:\n"); \
1949 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1950 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1951 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1952 IP_REGNUM, PC_REGNUM); \
1953 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1954 IP_REGNUM, IP_REGNUM); \
1955 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1956 fprintf (FILE, "\t.word\t0\n"); \
1957 fprintf (FILE, "\t.word\t0\n"); \
1958 fprintf (FILE, "\t.code 16\n"); \
1959 }
1960
1961 #define TRAMPOLINE_TEMPLATE(FILE) \
1962 if (TARGET_ARM) \
1963 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1964 else \
1965 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1966
1967 /* Length in units of the trampoline for entering a nested function. */
1968 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1969
1970 /* Alignment required for a trampoline in bits. */
1971 #define TRAMPOLINE_ALIGNMENT 32
1972
1973 /* Emit RTL insns to initialize the variable parts of a trampoline.
1974 FNADDR is an RTX for the address of the function's pure code.
1975 CXT is an RTX for the static chain value for the function. */
1976 #ifndef INITIALIZE_TRAMPOLINE
1977 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1978 { \
1979 emit_move_insn (gen_rtx_MEM (SImode, \
1980 plus_constant (TRAMP, \
1981 TARGET_ARM ? 8 : 16)), \
1982 CXT); \
1983 emit_move_insn (gen_rtx_MEM (SImode, \
1984 plus_constant (TRAMP, \
1985 TARGET_ARM ? 12 : 20)), \
1986 FNADDR); \
1987 }
1988 #endif
1989
1990 \f
1991 /* Addressing modes, and classification of registers for them. */
1992 #define HAVE_POST_INCREMENT 1
1993 #define HAVE_PRE_INCREMENT TARGET_ARM
1994 #define HAVE_POST_DECREMENT TARGET_ARM
1995 #define HAVE_PRE_DECREMENT TARGET_ARM
1996 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1997 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1998 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1999 #define HAVE_POST_MODIFY_REG TARGET_ARM
2000
2001 /* Macros to check register numbers against specific register classes. */
2002
2003 /* These assume that REGNO is a hard or pseudo reg number.
2004 They give nonzero only if REGNO is a hard reg of the suitable class
2005 or a pseudo reg currently allocated to a suitable hard reg.
2006 Since they use reg_renumber, they are safe only once reg_renumber
2007 has been allocated, which happens in local-alloc.c. */
2008 #define TEST_REGNO(R, TEST, VALUE) \
2009 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2010
2011 /* On the ARM, don't allow the pc to be used. */
2012 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2013 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2014 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2015 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2016
2017 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2018 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2019 || (GET_MODE_SIZE (MODE) >= 4 \
2020 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2021
2022 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2023 (TARGET_THUMB \
2024 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2025 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2026
2027 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2028 For Thumb, we can not use SP + reg, so reject SP. */
2029 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2030 REGNO_OK_FOR_INDEX_P (X)
2031
2032 /* For ARM code, we don't care about the mode, but for Thumb, the index
2033 must be suitable for use in a QImode load. */
2034 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2035 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2036
2037 /* Maximum number of registers that can appear in a valid memory address.
2038 Shifts in addresses can't be by a register. */
2039 #define MAX_REGS_PER_ADDRESS 2
2040
2041 /* Recognize any constant value that is a valid address. */
2042 /* XXX We can address any constant, eventually... */
2043
2044 #ifdef AOF_ASSEMBLER
2045
2046 #define CONSTANT_ADDRESS_P(X) \
2047 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2048
2049 #else
2050
2051 #define CONSTANT_ADDRESS_P(X) \
2052 (GET_CODE (X) == SYMBOL_REF \
2053 && (CONSTANT_POOL_ADDRESS_P (X) \
2054 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2055
2056 #endif /* AOF_ASSEMBLER */
2057
2058 /* Nonzero if the constant value X is a legitimate general operand.
2059 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2060
2061 On the ARM, allow any integer (invalid ones are removed later by insn
2062 patterns), nice doubles and symbol_refs which refer to the function's
2063 constant pool XXX.
2064
2065 When generating pic allow anything. */
2066 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2067
2068 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2069 ( GET_CODE (X) == CONST_INT \
2070 || GET_CODE (X) == CONST_DOUBLE \
2071 || CONSTANT_ADDRESS_P (X) \
2072 || flag_pic)
2073
2074 #define LEGITIMATE_CONSTANT_P(X) \
2075 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2076
2077 /* Special characters prefixed to function names
2078 in order to encode attribute like information.
2079 Note, '@' and '*' have already been taken. */
2080 #define SHORT_CALL_FLAG_CHAR '^'
2081 #define LONG_CALL_FLAG_CHAR '#'
2082
2083 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2084 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2085
2086 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2087 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2088
2089 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2090 #define SUBTARGET_NAME_ENCODING_LENGTHS
2091 #endif
2092
2093 /* This is a C fragment for the inside of a switch statement.
2094 Each case label should return the number of characters to
2095 be stripped from the start of a function's name, if that
2096 name starts with the indicated character. */
2097 #define ARM_NAME_ENCODING_LENGTHS \
2098 case SHORT_CALL_FLAG_CHAR: return 1; \
2099 case LONG_CALL_FLAG_CHAR: return 1; \
2100 case '*': return 1; \
2101 SUBTARGET_NAME_ENCODING_LENGTHS
2102
2103 /* This is how to output a reference to a user-level label named NAME.
2104 `assemble_name' uses this. */
2105 #undef ASM_OUTPUT_LABELREF
2106 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2107 arm_asm_output_labelref (FILE, NAME)
2108
2109 /* Set the short-call flag for any function compiled in the current
2110 compilation unit. We skip this for functions with the section
2111 attribute when long-calls are in effect as this tells the compiler
2112 that the section might be placed a long way from the caller.
2113 See arm_is_longcall_p() for more information. */
2114 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2115 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
2116 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2117
2118 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2119 and check its validity for a certain class.
2120 We have two alternate definitions for each of them.
2121 The usual definition accepts all pseudo regs; the other rejects
2122 them unless they have been allocated suitable hard regs.
2123 The symbol REG_OK_STRICT causes the latter definition to be used. */
2124 #ifndef REG_OK_STRICT
2125
2126 #define ARM_REG_OK_FOR_BASE_P(X) \
2127 (REGNO (X) <= LAST_ARM_REGNUM \
2128 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2129 || REGNO (X) == FRAME_POINTER_REGNUM \
2130 || REGNO (X) == ARG_POINTER_REGNUM)
2131
2132 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2133 (REGNO (X) <= LAST_LO_REGNUM \
2134 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2135 || (GET_MODE_SIZE (MODE) >= 4 \
2136 && (REGNO (X) == STACK_POINTER_REGNUM \
2137 || (X) == hard_frame_pointer_rtx \
2138 || (X) == arg_pointer_rtx)))
2139
2140 #define REG_STRICT_P 0
2141
2142 #else /* REG_OK_STRICT */
2143
2144 #define ARM_REG_OK_FOR_BASE_P(X) \
2145 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2146
2147 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2148 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2149
2150 #define REG_STRICT_P 1
2151
2152 #endif /* REG_OK_STRICT */
2153
2154 /* Now define some helpers in terms of the above. */
2155
2156 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2157 (TARGET_THUMB \
2158 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2159 : ARM_REG_OK_FOR_BASE_P (X))
2160
2161 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2162
2163 /* For Thumb, a valid index register is anything that can be used in
2164 a byte load instruction. */
2165 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2166
2167 /* Nonzero if X is a hard reg that can be used as an index
2168 or if it is a pseudo reg. On the Thumb, the stack pointer
2169 is not suitable. */
2170 #define REG_OK_FOR_INDEX_P(X) \
2171 (TARGET_THUMB \
2172 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2173 : ARM_REG_OK_FOR_INDEX_P (X))
2174
2175 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2176 For Thumb, we can not use SP + reg, so reject SP. */
2177 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2178 REG_OK_FOR_INDEX_P (X)
2179 \f
2180 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2181 that is a valid memory address for an instruction.
2182 The MODE argument is the machine mode for the MEM expression
2183 that wants to use this address. */
2184
2185 #define ARM_BASE_REGISTER_RTX_P(X) \
2186 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2187
2188 #define ARM_INDEX_REGISTER_RTX_P(X) \
2189 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2190
2191 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2192 { \
2193 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2194 goto WIN; \
2195 }
2196
2197 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2198 { \
2199 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2200 goto WIN; \
2201 }
2202
2203 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2204 if (TARGET_ARM) \
2205 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2206 else /* if (TARGET_THUMB) */ \
2207 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2208
2209 \f
2210 /* Try machine-dependent ways of modifying an illegitimate address
2211 to be legitimate. If we find one, return the new, valid address. */
2212 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2213 do { \
2214 X = arm_legitimize_address (X, OLDX, MODE); \
2215 } while (0)
2216
2217 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2218 do { \
2219 X = thumb_legitimize_address (X, OLDX, MODE); \
2220 } while (0)
2221
2222 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2223 do { \
2224 if (TARGET_ARM) \
2225 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2226 else \
2227 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2228 \
2229 if (memory_address_p (MODE, X)) \
2230 goto WIN; \
2231 } while (0)
2232
2233 /* Go to LABEL if ADDR (a legitimate address expression)
2234 has an effect that depends on the machine mode it is used for. */
2235 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2236 { \
2237 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2238 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2239 goto LABEL; \
2240 }
2241
2242 /* Nothing helpful to do for the Thumb */
2243 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2244 if (TARGET_ARM) \
2245 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2246 \f
2247
2248 /* Specify the machine mode that this machine uses
2249 for the index in the tablejump instruction. */
2250 #define CASE_VECTOR_MODE Pmode
2251
2252 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2253 unsigned is probably best, but may break some code. */
2254 #ifndef DEFAULT_SIGNED_CHAR
2255 #define DEFAULT_SIGNED_CHAR 0
2256 #endif
2257
2258 /* Max number of bytes we can move from memory to memory
2259 in one reasonably fast instruction. */
2260 #define MOVE_MAX 4
2261
2262 #undef MOVE_RATIO
2263 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2264
2265 /* Define if operations between registers always perform the operation
2266 on the full register even if a narrower mode is specified. */
2267 #define WORD_REGISTER_OPERATIONS
2268
2269 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2270 will either zero-extend or sign-extend. The value of this macro should
2271 be the code that says which one of the two operations is implicitly
2272 done, UNKNOWN if none. */
2273 #define LOAD_EXTEND_OP(MODE) \
2274 (TARGET_THUMB ? ZERO_EXTEND : \
2275 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2276 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2277
2278 /* Nonzero if access to memory by bytes is slow and undesirable. */
2279 #define SLOW_BYTE_ACCESS 0
2280
2281 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2282
2283 /* Immediate shift counts are truncated by the output routines (or was it
2284 the assembler?). Shift counts in a register are truncated by ARM. Note
2285 that the native compiler puts too large (> 32) immediate shift counts
2286 into a register and shifts by the register, letting the ARM decide what
2287 to do instead of doing that itself. */
2288 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2289 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2290 On the arm, Y in a register is used modulo 256 for the shift. Only for
2291 rotates is modulo 32 used. */
2292 /* #define SHIFT_COUNT_TRUNCATED 1 */
2293
2294 /* All integers have the same format so truncation is easy. */
2295 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2296
2297 /* Calling from registers is a massive pain. */
2298 #define NO_FUNCTION_CSE 1
2299
2300 /* The machine modes of pointers and functions */
2301 #define Pmode SImode
2302 #define FUNCTION_MODE Pmode
2303
2304 #define ARM_FRAME_RTX(X) \
2305 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2306 || (X) == arg_pointer_rtx)
2307
2308 /* Moves to and from memory are quite expensive */
2309 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2310 (TARGET_ARM ? 10 : \
2311 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2312 * (CLASS == LO_REGS ? 1 : 2)))
2313
2314 /* Try to generate sequences that don't involve branches, we can then use
2315 conditional instructions */
2316 #define BRANCH_COST \
2317 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2318 \f
2319 /* Position Independent Code. */
2320 /* We decide which register to use based on the compilation options and
2321 the assembler in use; this is more general than the APCS restriction of
2322 using sb (r9) all the time. */
2323 extern int arm_pic_register;
2324
2325 /* Used when parsing command line option -mpic-register=. */
2326 extern const char * arm_pic_register_string;
2327
2328 /* The register number of the register used to address a table of static
2329 data addresses in memory. */
2330 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2331
2332 /* We can't directly access anything that contains a symbol,
2333 nor can we indirect via the constant pool. */
2334 #define LEGITIMATE_PIC_OPERAND_P(X) \
2335 (!(symbol_mentioned_p (X) \
2336 || label_mentioned_p (X) \
2337 || (GET_CODE (X) == SYMBOL_REF \
2338 && CONSTANT_POOL_ADDRESS_P (X) \
2339 && (symbol_mentioned_p (get_pool_constant (X)) \
2340 || label_mentioned_p (get_pool_constant (X))))))
2341
2342 /* We need to know when we are making a constant pool; this determines
2343 whether data needs to be in the GOT or can be referenced via a GOT
2344 offset. */
2345 extern int making_const_table;
2346 \f
2347 /* Handle pragmas for compatibility with Intel's compilers. */
2348 #define REGISTER_TARGET_PRAGMAS() do { \
2349 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2350 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2351 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2352 } while (0)
2353
2354 /* Condition code information. */
2355 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2356 return the mode to be used for the comparison. */
2357
2358 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2359
2360 #define REVERSIBLE_CC_MODE(MODE) 1
2361
2362 #define REVERSE_CONDITION(CODE,MODE) \
2363 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2364 ? reverse_condition_maybe_unordered (code) \
2365 : reverse_condition (code))
2366
2367 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2368 do \
2369 { \
2370 if (GET_CODE (OP1) == CONST_INT \
2371 && ! (const_ok_for_arm (INTVAL (OP1)) \
2372 || (const_ok_for_arm (- INTVAL (OP1))))) \
2373 { \
2374 rtx const_op = OP1; \
2375 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2376 OP1 = const_op; \
2377 } \
2378 } \
2379 while (0)
2380
2381 /* The arm5 clz instruction returns 32. */
2382 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2383 \f
2384 #undef ASM_APP_OFF
2385 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2386
2387 /* Output a push or a pop instruction (only used when profiling). */
2388 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2389 do \
2390 { \
2391 if (TARGET_ARM) \
2392 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2393 STACK_POINTER_REGNUM, REGNO); \
2394 else \
2395 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2396 } while (0)
2397
2398
2399 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2400 do \
2401 { \
2402 if (TARGET_ARM) \
2403 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2404 STACK_POINTER_REGNUM, REGNO); \
2405 else \
2406 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2407 } while (0)
2408
2409 /* This is how to output a label which precedes a jumptable. Since
2410 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2411 #undef ASM_OUTPUT_CASE_LABEL
2412 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2413 do \
2414 { \
2415 if (TARGET_THUMB) \
2416 ASM_OUTPUT_ALIGN (FILE, 2); \
2417 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2418 } \
2419 while (0)
2420
2421 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2422 do \
2423 { \
2424 if (TARGET_THUMB) \
2425 { \
2426 if (is_called_in_ARM_mode (DECL) \
2427 || current_function_is_thunk) \
2428 fprintf (STREAM, "\t.code 32\n") ; \
2429 else \
2430 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2431 } \
2432 if (TARGET_POKE_FUNCTION_NAME) \
2433 arm_poke_function_name (STREAM, (char *) NAME); \
2434 } \
2435 while (0)
2436
2437 /* For aliases of functions we use .thumb_set instead. */
2438 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2439 do \
2440 { \
2441 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2442 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2443 \
2444 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2445 { \
2446 fprintf (FILE, "\t.thumb_set "); \
2447 assemble_name (FILE, LABEL1); \
2448 fprintf (FILE, ","); \
2449 assemble_name (FILE, LABEL2); \
2450 fprintf (FILE, "\n"); \
2451 } \
2452 else \
2453 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2454 } \
2455 while (0)
2456
2457 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2458 /* To support -falign-* switches we need to use .p2align so
2459 that alignment directives in code sections will be padded
2460 with no-op instructions, rather than zeroes. */
2461 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2462 if ((LOG) != 0) \
2463 { \
2464 if ((MAX_SKIP) == 0) \
2465 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2466 else \
2467 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2468 (int) (LOG), (int) (MAX_SKIP)); \
2469 }
2470 #endif
2471 \f
2472 /* Only perform branch elimination (by making instructions conditional) if
2473 we're optimizing. Otherwise it's of no use anyway. */
2474 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2475 if (TARGET_ARM && optimize) \
2476 arm_final_prescan_insn (INSN); \
2477 else if (TARGET_THUMB) \
2478 thumb_final_prescan_insn (INSN)
2479
2480 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2481 (CODE == '@' || CODE == '|' \
2482 || (TARGET_ARM && (CODE == '?')) \
2483 || (TARGET_THUMB && (CODE == '_')))
2484
2485 /* Output an operand of an instruction. */
2486 #define PRINT_OPERAND(STREAM, X, CODE) \
2487 arm_print_operand (STREAM, X, CODE)
2488
2489 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2490 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2491 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2492 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2493 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2494 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2495 : 0))))
2496
2497 /* Output the address of an operand. */
2498 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2499 { \
2500 int is_minus = GET_CODE (X) == MINUS; \
2501 \
2502 if (GET_CODE (X) == REG) \
2503 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2504 else if (GET_CODE (X) == PLUS || is_minus) \
2505 { \
2506 rtx base = XEXP (X, 0); \
2507 rtx index = XEXP (X, 1); \
2508 HOST_WIDE_INT offset = 0; \
2509 if (GET_CODE (base) != REG) \
2510 { \
2511 /* Ensure that BASE is a register. */ \
2512 /* (one of them must be). */ \
2513 rtx temp = base; \
2514 base = index; \
2515 index = temp; \
2516 } \
2517 switch (GET_CODE (index)) \
2518 { \
2519 case CONST_INT: \
2520 offset = INTVAL (index); \
2521 if (is_minus) \
2522 offset = -offset; \
2523 asm_fprintf (STREAM, "[%r, #%wd]", \
2524 REGNO (base), offset); \
2525 break; \
2526 \
2527 case REG: \
2528 asm_fprintf (STREAM, "[%r, %s%r]", \
2529 REGNO (base), is_minus ? "-" : "", \
2530 REGNO (index)); \
2531 break; \
2532 \
2533 case MULT: \
2534 case ASHIFTRT: \
2535 case LSHIFTRT: \
2536 case ASHIFT: \
2537 case ROTATERT: \
2538 { \
2539 asm_fprintf (STREAM, "[%r, %s%r", \
2540 REGNO (base), is_minus ? "-" : "", \
2541 REGNO (XEXP (index, 0))); \
2542 arm_print_operand (STREAM, index, 'S'); \
2543 fputs ("]", STREAM); \
2544 break; \
2545 } \
2546 \
2547 default: \
2548 abort(); \
2549 } \
2550 } \
2551 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2552 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2553 { \
2554 extern enum machine_mode output_memory_reference_mode; \
2555 \
2556 if (GET_CODE (XEXP (X, 0)) != REG) \
2557 abort (); \
2558 \
2559 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2560 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2561 REGNO (XEXP (X, 0)), \
2562 GET_CODE (X) == PRE_DEC ? "-" : "", \
2563 GET_MODE_SIZE (output_memory_reference_mode)); \
2564 else \
2565 asm_fprintf (STREAM, "[%r], #%s%d", \
2566 REGNO (XEXP (X, 0)), \
2567 GET_CODE (X) == POST_DEC ? "-" : "", \
2568 GET_MODE_SIZE (output_memory_reference_mode)); \
2569 } \
2570 else if (GET_CODE (X) == PRE_MODIFY) \
2571 { \
2572 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2573 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2574 asm_fprintf (STREAM, "#%wd]!", \
2575 INTVAL (XEXP (XEXP (X, 1), 1))); \
2576 else \
2577 asm_fprintf (STREAM, "%r]!", \
2578 REGNO (XEXP (XEXP (X, 1), 1))); \
2579 } \
2580 else if (GET_CODE (X) == POST_MODIFY) \
2581 { \
2582 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2583 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2584 asm_fprintf (STREAM, "#%wd", \
2585 INTVAL (XEXP (XEXP (X, 1), 1))); \
2586 else \
2587 asm_fprintf (STREAM, "%r", \
2588 REGNO (XEXP (XEXP (X, 1), 1))); \
2589 } \
2590 else output_addr_const (STREAM, X); \
2591 }
2592
2593 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2594 { \
2595 if (GET_CODE (X) == REG) \
2596 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2597 else if (GET_CODE (X) == POST_INC) \
2598 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2599 else if (GET_CODE (X) == PLUS) \
2600 { \
2601 if (GET_CODE (XEXP (X, 0)) != REG) \
2602 abort (); \
2603 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2604 asm_fprintf (STREAM, "[%r, #%wd]", \
2605 REGNO (XEXP (X, 0)), \
2606 INTVAL (XEXP (X, 1))); \
2607 else \
2608 asm_fprintf (STREAM, "[%r, %r]", \
2609 REGNO (XEXP (X, 0)), \
2610 REGNO (XEXP (X, 1))); \
2611 } \
2612 else \
2613 output_addr_const (STREAM, X); \
2614 }
2615
2616 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2617 if (TARGET_ARM) \
2618 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2619 else \
2620 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2621
2622 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2623 if (GET_CODE (X) != CONST_VECTOR \
2624 || ! arm_emit_vector_const (FILE, X)) \
2625 goto FAIL;
2626
2627 /* A C expression whose value is RTL representing the value of the return
2628 address for the frame COUNT steps up from the current frame. */
2629
2630 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2631 arm_return_addr (COUNT, FRAME)
2632
2633 /* Mask of the bits in the PC that contain the real return address
2634 when running in 26-bit mode. */
2635 #define RETURN_ADDR_MASK26 (0x03fffffc)
2636
2637 /* Pick up the return address upon entry to a procedure. Used for
2638 dwarf2 unwind information. This also enables the table driven
2639 mechanism. */
2640 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2641 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2642
2643 /* Used to mask out junk bits from the return address, such as
2644 processor state, interrupt status, condition codes and the like. */
2645 #define MASK_RETURN_ADDR \
2646 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2647 in 26 bit mode, the condition codes must be masked out of the \
2648 return address. This does not apply to ARM6 and later processors \
2649 when running in 32 bit mode. */ \
2650 ((arm_arch4 || TARGET_THUMB) \
2651 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2652 : arm_gen_return_addr_mask ())
2653
2654 \f
2655 enum arm_builtins
2656 {
2657 ARM_BUILTIN_GETWCX,
2658 ARM_BUILTIN_SETWCX,
2659
2660 ARM_BUILTIN_WZERO,
2661
2662 ARM_BUILTIN_WAVG2BR,
2663 ARM_BUILTIN_WAVG2HR,
2664 ARM_BUILTIN_WAVG2B,
2665 ARM_BUILTIN_WAVG2H,
2666
2667 ARM_BUILTIN_WACCB,
2668 ARM_BUILTIN_WACCH,
2669 ARM_BUILTIN_WACCW,
2670
2671 ARM_BUILTIN_WMACS,
2672 ARM_BUILTIN_WMACSZ,
2673 ARM_BUILTIN_WMACU,
2674 ARM_BUILTIN_WMACUZ,
2675
2676 ARM_BUILTIN_WSADB,
2677 ARM_BUILTIN_WSADBZ,
2678 ARM_BUILTIN_WSADH,
2679 ARM_BUILTIN_WSADHZ,
2680
2681 ARM_BUILTIN_WALIGN,
2682
2683 ARM_BUILTIN_TMIA,
2684 ARM_BUILTIN_TMIAPH,
2685 ARM_BUILTIN_TMIABB,
2686 ARM_BUILTIN_TMIABT,
2687 ARM_BUILTIN_TMIATB,
2688 ARM_BUILTIN_TMIATT,
2689
2690 ARM_BUILTIN_TMOVMSKB,
2691 ARM_BUILTIN_TMOVMSKH,
2692 ARM_BUILTIN_TMOVMSKW,
2693
2694 ARM_BUILTIN_TBCSTB,
2695 ARM_BUILTIN_TBCSTH,
2696 ARM_BUILTIN_TBCSTW,
2697
2698 ARM_BUILTIN_WMADDS,
2699 ARM_BUILTIN_WMADDU,
2700
2701 ARM_BUILTIN_WPACKHSS,
2702 ARM_BUILTIN_WPACKWSS,
2703 ARM_BUILTIN_WPACKDSS,
2704 ARM_BUILTIN_WPACKHUS,
2705 ARM_BUILTIN_WPACKWUS,
2706 ARM_BUILTIN_WPACKDUS,
2707
2708 ARM_BUILTIN_WADDB,
2709 ARM_BUILTIN_WADDH,
2710 ARM_BUILTIN_WADDW,
2711 ARM_BUILTIN_WADDSSB,
2712 ARM_BUILTIN_WADDSSH,
2713 ARM_BUILTIN_WADDSSW,
2714 ARM_BUILTIN_WADDUSB,
2715 ARM_BUILTIN_WADDUSH,
2716 ARM_BUILTIN_WADDUSW,
2717 ARM_BUILTIN_WSUBB,
2718 ARM_BUILTIN_WSUBH,
2719 ARM_BUILTIN_WSUBW,
2720 ARM_BUILTIN_WSUBSSB,
2721 ARM_BUILTIN_WSUBSSH,
2722 ARM_BUILTIN_WSUBSSW,
2723 ARM_BUILTIN_WSUBUSB,
2724 ARM_BUILTIN_WSUBUSH,
2725 ARM_BUILTIN_WSUBUSW,
2726
2727 ARM_BUILTIN_WAND,
2728 ARM_BUILTIN_WANDN,
2729 ARM_BUILTIN_WOR,
2730 ARM_BUILTIN_WXOR,
2731
2732 ARM_BUILTIN_WCMPEQB,
2733 ARM_BUILTIN_WCMPEQH,
2734 ARM_BUILTIN_WCMPEQW,
2735 ARM_BUILTIN_WCMPGTUB,
2736 ARM_BUILTIN_WCMPGTUH,
2737 ARM_BUILTIN_WCMPGTUW,
2738 ARM_BUILTIN_WCMPGTSB,
2739 ARM_BUILTIN_WCMPGTSH,
2740 ARM_BUILTIN_WCMPGTSW,
2741
2742 ARM_BUILTIN_TEXTRMSB,
2743 ARM_BUILTIN_TEXTRMSH,
2744 ARM_BUILTIN_TEXTRMSW,
2745 ARM_BUILTIN_TEXTRMUB,
2746 ARM_BUILTIN_TEXTRMUH,
2747 ARM_BUILTIN_TEXTRMUW,
2748 ARM_BUILTIN_TINSRB,
2749 ARM_BUILTIN_TINSRH,
2750 ARM_BUILTIN_TINSRW,
2751
2752 ARM_BUILTIN_WMAXSW,
2753 ARM_BUILTIN_WMAXSH,
2754 ARM_BUILTIN_WMAXSB,
2755 ARM_BUILTIN_WMAXUW,
2756 ARM_BUILTIN_WMAXUH,
2757 ARM_BUILTIN_WMAXUB,
2758 ARM_BUILTIN_WMINSW,
2759 ARM_BUILTIN_WMINSH,
2760 ARM_BUILTIN_WMINSB,
2761 ARM_BUILTIN_WMINUW,
2762 ARM_BUILTIN_WMINUH,
2763 ARM_BUILTIN_WMINUB,
2764
2765 ARM_BUILTIN_WMULUM,
2766 ARM_BUILTIN_WMULSM,
2767 ARM_BUILTIN_WMULUL,
2768
2769 ARM_BUILTIN_PSADBH,
2770 ARM_BUILTIN_WSHUFH,
2771
2772 ARM_BUILTIN_WSLLH,
2773 ARM_BUILTIN_WSLLW,
2774 ARM_BUILTIN_WSLLD,
2775 ARM_BUILTIN_WSRAH,
2776 ARM_BUILTIN_WSRAW,
2777 ARM_BUILTIN_WSRAD,
2778 ARM_BUILTIN_WSRLH,
2779 ARM_BUILTIN_WSRLW,
2780 ARM_BUILTIN_WSRLD,
2781 ARM_BUILTIN_WRORH,
2782 ARM_BUILTIN_WRORW,
2783 ARM_BUILTIN_WRORD,
2784 ARM_BUILTIN_WSLLHI,
2785 ARM_BUILTIN_WSLLWI,
2786 ARM_BUILTIN_WSLLDI,
2787 ARM_BUILTIN_WSRAHI,
2788 ARM_BUILTIN_WSRAWI,
2789 ARM_BUILTIN_WSRADI,
2790 ARM_BUILTIN_WSRLHI,
2791 ARM_BUILTIN_WSRLWI,
2792 ARM_BUILTIN_WSRLDI,
2793 ARM_BUILTIN_WRORHI,
2794 ARM_BUILTIN_WRORWI,
2795 ARM_BUILTIN_WRORDI,
2796
2797 ARM_BUILTIN_WUNPCKIHB,
2798 ARM_BUILTIN_WUNPCKIHH,
2799 ARM_BUILTIN_WUNPCKIHW,
2800 ARM_BUILTIN_WUNPCKILB,
2801 ARM_BUILTIN_WUNPCKILH,
2802 ARM_BUILTIN_WUNPCKILW,
2803
2804 ARM_BUILTIN_WUNPCKEHSB,
2805 ARM_BUILTIN_WUNPCKEHSH,
2806 ARM_BUILTIN_WUNPCKEHSW,
2807 ARM_BUILTIN_WUNPCKEHUB,
2808 ARM_BUILTIN_WUNPCKEHUH,
2809 ARM_BUILTIN_WUNPCKEHUW,
2810 ARM_BUILTIN_WUNPCKELSB,
2811 ARM_BUILTIN_WUNPCKELSH,
2812 ARM_BUILTIN_WUNPCKELSW,
2813 ARM_BUILTIN_WUNPCKELUB,
2814 ARM_BUILTIN_WUNPCKELUH,
2815 ARM_BUILTIN_WUNPCKELUW,
2816
2817 ARM_BUILTIN_MAX
2818 };
2819 #endif /* ! GCC_ARM_H */
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