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* config/arm/arm.h (REG_CLASS_NAMES): Add missing comma.
[official-gcc.git] / gcc / config / arm / arm.h
blobd2986ff4928ec11280ae50eb43fd7500cd8a1ead
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 /* Define __arm__ even when in thumb mode, for \
34 consistency with armcc. */ \
35 builtin_define ("__arm__"); \
36 if (TARGET_THUMB) \
37 builtin_define ("__thumb__"); \
38 \
39 if (TARGET_BIG_END) \
40 { \
41 builtin_define ("__ARMEB__"); \
42 if (TARGET_THUMB) \
43 builtin_define ("__THUMBEB__"); \
44 if (TARGET_LITTLE_WORDS) \
45 builtin_define ("__ARMWEL__"); \
46 } \
47 else \
48 { \
49 builtin_define ("__ARMEL__"); \
50 if (TARGET_THUMB) \
51 builtin_define ("__THUMBEL__"); \
52 } \
53 \
54 if (TARGET_APCS_32) \
55 builtin_define ("__APCS_32__"); \
56 else \
57 builtin_define ("__APCS_26__"); \
58 \
59 if (TARGET_SOFT_FLOAT) \
60 builtin_define ("__SOFTFP__"); \
61 \
62 if (TARGET_VFP) \
63 builtin_define ("__VFP_FP__"); \
64 \
65 /* Add a define for interworking. \
66 Needed when building libgcc.a. */ \
67 if (TARGET_INTERWORK) \
68 builtin_define ("__THUMB_INTERWORK__"); \
69 \
70 builtin_assert ("cpu=arm"); \
71 builtin_assert ("machine=arm"); \
72 } while (0)
73
74 #define TARGET_CPU_arm2 0x0000
75 #define TARGET_CPU_arm250 0x0000
76 #define TARGET_CPU_arm3 0x0000
77 #define TARGET_CPU_arm6 0x0001
78 #define TARGET_CPU_arm600 0x0001
79 #define TARGET_CPU_arm610 0x0002
80 #define TARGET_CPU_arm7 0x0001
81 #define TARGET_CPU_arm7m 0x0004
82 #define TARGET_CPU_arm7dm 0x0004
83 #define TARGET_CPU_arm7dmi 0x0004
84 #define TARGET_CPU_arm700 0x0001
85 #define TARGET_CPU_arm710 0x0002
86 #define TARGET_CPU_arm7100 0x0002
87 #define TARGET_CPU_arm7500 0x0002
88 #define TARGET_CPU_arm7500fe 0x1001
89 #define TARGET_CPU_arm7tdmi 0x0008
90 #define TARGET_CPU_arm8 0x0010
91 #define TARGET_CPU_arm810 0x0020
92 #define TARGET_CPU_strongarm 0x0040
93 #define TARGET_CPU_strongarm110 0x0040
94 #define TARGET_CPU_strongarm1100 0x0040
95 #define TARGET_CPU_arm9 0x0080
96 #define TARGET_CPU_arm9tdmi 0x0080
97 #define TARGET_CPU_xscale 0x0100
98 #define TARGET_CPU_ep9312 0x0200
99 #define TARGET_CPU_iwmmxt 0x0400
100 #define TARGET_CPU_arm926ejs 0x0800
101 #define TARGET_CPU_arm1026ejs 0x1000
102 #define TARGET_CPU_arm1136js 0x2000
103 #define TARGET_CPU_arm1136jfs 0x4000
104 /* Configure didn't specify. */
105 #define TARGET_CPU_generic 0x8000
106
107 /* The various ARM cores. */
108 enum processor_type
109 {
110 #define ARM_CORE(NAME, FLAGS, COSTS) \
111 NAME,
112 #include "arm-cores.def"
113 #undef ARM_CORE
114 /* Used to indicate that no processor has been specified. */
115 arm_none
116 };
117
118 /* The processor for which instructions should be scheduled. */
119 extern enum processor_type arm_tune;
120
121 typedef enum arm_cond_code
122 {
123 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
124 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
125 }
126 arm_cc;
127
128 extern arm_cc arm_current_cc;
129
130 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
131
132 extern int arm_target_label;
133 extern int arm_ccfsm_state;
134 extern GTY(()) rtx arm_target_insn;
135 /* Run-time compilation parameters selecting different hardware subsets. */
136 extern int target_flags;
137 /* The floating point mode. */
138 extern const char *target_fpu_name;
139 /* For backwards compatibility. */
140 extern const char *target_fpe_name;
141 /* Whether to use floating point hardware. */
142 extern const char *target_float_abi_name;
143 /* Define the information needed to generate branch insns. This is
144 stored from the compare operation. */
145 extern GTY(()) rtx arm_compare_op0;
146 extern GTY(()) rtx arm_compare_op1;
147 /* The label of the current constant pool. */
148 extern rtx pool_vector_label;
149 /* Set to 1 when a return insn is output, this means that the epilogue
150 is not needed. */
151 extern int return_used_this_function;
152 /* Used to produce AOF syntax assembler. */
153 extern GTY(()) rtx aof_pic_label;
154 \f
155 /* Just in case configure has failed to define anything. */
156 #ifndef TARGET_CPU_DEFAULT
157 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
158 #endif
159
160 /* If the configuration file doesn't specify the cpu, the subtarget may
161 override it. If it doesn't, then default to an ARM6. */
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
163 #undef TARGET_CPU_DEFAULT
164
165 #ifdef SUBTARGET_CPU_DEFAULT
166 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
167 #else
168 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
169 #endif
170 #endif
171
172 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
173 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
174 #else
175 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
176 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
177 #else
178 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
179 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
180 #else
181 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
182 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
183 #else
184 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
185 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
186 #else
187 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
188 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
189 #else
190 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
191 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__"
192 /* Set TARGET_DEFAULT to the default, but without soft-float. */
193 #ifdef TARGET_DEFAULT
194 #undef TARGET_DEFAULT
195 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
196 #endif
197 #else
198 #if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
199 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__"
200 #else
201 #if (TARGET_CPU_DEFAULT == TARGET_CPU_arm926ejs || \
202 TARGET_CPU_DEFAULT == TARGET_CPU_arm1026ejs)
203 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TEJ__"
204 #else
205 #if (TARGET_CPU_DEFAULT == TARGET_CPU_arm1136js || \
206 TARGET_CPU_DEFAULT == TARGET_CPU_arm1136jfs)
207 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_6J__"
208 #else
209 #error Unrecognized value in TARGET_CPU_DEFAULT.
210 #endif
211 #endif
212 #endif
213 #endif
214 #endif
215 #endif
216 #endif
217 #endif
218 #endif
219 #endif
220
221 #undef CPP_SPEC
222 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
223 %{mapcs-32:%{mapcs-26: \
224 %e-mapcs-26 and -mapcs-32 may not be used together}} \
225 %{msoft-float:%{mhard-float: \
226 %e-msoft-float and -mhard_float may not be used together}} \
227 %{mbig-endian:%{mlittle-endian: \
228 %e-mbig-endian and -mlittle-endian may not be used together}}"
229
230 /* Set the architecture define -- if -march= is set, then it overrides
231 the -mcpu= setting. */
232 #define CPP_CPU_ARCH_SPEC "\
233 %{march=arm2:-D__ARM_ARCH_2__} \
234 %{march=arm250:-D__ARM_ARCH_2__} \
235 %{march=arm3:-D__ARM_ARCH_2__} \
236 %{march=arm6:-D__ARM_ARCH_3__} \
237 %{march=arm600:-D__ARM_ARCH_3__} \
238 %{march=arm610:-D__ARM_ARCH_3__} \
239 %{march=arm7:-D__ARM_ARCH_3__} \
240 %{march=arm700:-D__ARM_ARCH_3__} \
241 %{march=arm710:-D__ARM_ARCH_3__} \
242 %{march=arm720:-D__ARM_ARCH_3__} \
243 %{march=arm7100:-D__ARM_ARCH_3__} \
244 %{march=arm7500:-D__ARM_ARCH_3__} \
245 %{march=arm7500fe:-D__ARM_ARCH_3__} \
246 %{march=arm7m:-D__ARM_ARCH_3M__} \
247 %{march=arm7dm:-D__ARM_ARCH_3M__} \
248 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
249 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
250 %{march=arm8:-D__ARM_ARCH_4__} \
251 %{march=arm810:-D__ARM_ARCH_4__} \
252 %{march=arm9:-D__ARM_ARCH_4T__} \
253 %{march=arm920:-D__ARM_ARCH_4__} \
254 %{march=arm920t:-D__ARM_ARCH_4T__} \
255 %{march=arm926ejs:-D__ARM_ARCH_5TEJ__} \
256 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
257 %{march=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
258 %{march=arm1136js:-D__ARM_ARCH_6J__} \
259 %{march=arm1136jfs:-D__ARM_ARCH_6J__} \
260 %{march=strongarm:-D__ARM_ARCH_4__} \
261 %{march=strongarm110:-D__ARM_ARCH_4__} \
262 %{march=strongarm1100:-D__ARM_ARCH_4__} \
263 %{march=xscale:-D__ARM_ARCH_5TE__} \
264 %{march=xscale:-D__XSCALE__} \
265 %{march=ep9312:-D__ARM_ARCH_4T__} \
266 %{march=ep9312:-D__MAVERICK__} \
267 %{march=armv2:-D__ARM_ARCH_2__} \
268 %{march=armv2a:-D__ARM_ARCH_2__} \
269 %{march=armv3:-D__ARM_ARCH_3__} \
270 %{march=armv3m:-D__ARM_ARCH_3M__} \
271 %{march=armv4:-D__ARM_ARCH_4__} \
272 %{march=armv4t:-D__ARM_ARCH_4T__} \
273 %{march=armv5:-D__ARM_ARCH_5__} \
274 %{march=armv5t:-D__ARM_ARCH_5T__} \
275 %{march=armv5e:-D__ARM_ARCH_5E__} \
276 %{march=armv5te:-D__ARM_ARCH_5TE__} \
277 %{march=armv6:-D__ARM_ARCH6__} \
278 %{march=armv6j:-D__ARM_ARCH6J__} \
279 %{!march=*: \
280 %{mcpu=arm2:-D__ARM_ARCH_2__} \
281 %{mcpu=arm250:-D__ARM_ARCH_2__} \
282 %{mcpu=arm3:-D__ARM_ARCH_2__} \
283 %{mcpu=arm6:-D__ARM_ARCH_3__} \
284 %{mcpu=arm600:-D__ARM_ARCH_3__} \
285 %{mcpu=arm610:-D__ARM_ARCH_3__} \
286 %{mcpu=arm7:-D__ARM_ARCH_3__} \
287 %{mcpu=arm700:-D__ARM_ARCH_3__} \
288 %{mcpu=arm710:-D__ARM_ARCH_3__} \
289 %{mcpu=arm720:-D__ARM_ARCH_3__} \
290 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
291 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
292 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
293 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
294 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
295 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
296 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
297 %{mcpu=arm8:-D__ARM_ARCH_4__} \
298 %{mcpu=arm810:-D__ARM_ARCH_4__} \
299 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
300 %{mcpu=arm920:-D__ARM_ARCH_4__} \
301 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
302 %{mcpu=arm926ejs:-D__ARM_ARCH_5TEJ__} \
303 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
304 %{mcpu=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
305 %{mcpu=arm1136js:-D__ARM_ARCH_6J__} \
306 %{mcpu=arm1136jfs:-D__ARM_ARCH_6J__} \
307 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
308 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
309 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
310 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
311 %{mcpu=xscale:-D__XSCALE__} \
312 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
313 %{mcpu=ep9312:-D__MAVERICK__} \
314 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
315 %{mcpu=iwmmxt:-D__XSCALE__} \
316 %{mcpu=iwmmxt:-D__IWMMXT__} \
317 %{!mcpu*:%(cpp_cpu_arch_default)}} \
318 "
319
320 #ifndef CC1_SPEC
321 #define CC1_SPEC ""
322 #endif
323
324 /* This macro defines names of additional specifications to put in the specs
325 that can be used in various specifications like CC1_SPEC. Its definition
326 is an initializer with a subgrouping for each command option.
327
328 Each subgrouping contains a string constant, that defines the
329 specification name, and a string constant that used by the GCC driver
330 program.
331
332 Do not define this macro if it does not need to do anything. */
333 #define EXTRA_SPECS \
334 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
335 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
336 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
337 SUBTARGET_EXTRA_SPECS
338
339 #ifndef SUBTARGET_EXTRA_SPECS
340 #define SUBTARGET_EXTRA_SPECS
341 #endif
342
343 #ifndef SUBTARGET_CPP_SPEC
344 #define SUBTARGET_CPP_SPEC ""
345 #endif
346 \f
347 /* Run-time Target Specification. */
348 #ifndef TARGET_VERSION
349 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
350 #endif
351
352 /* Nonzero if the function prologue (and epilogue) should obey
353 the ARM Procedure Call Standard. */
354 #define ARM_FLAG_APCS_FRAME (1 << 0)
355
356 /* Nonzero if the function prologue should output the function name to enable
357 the post mortem debugger to print a backtrace (very useful on RISCOS,
358 unused on RISCiX). Specifying this flag also enables
359 -fno-omit-frame-pointer.
360 XXX Must still be implemented in the prologue. */
361 #define ARM_FLAG_POKE (1 << 1)
362
363 /* Nonzero if floating point instructions are emulated by the FPE, in which
364 case instruction scheduling becomes very uninteresting. */
365 #define ARM_FLAG_FPE (1 << 2)
366
367 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
368 that assume restoration of the condition flags when returning from a
369 branch and link (ie a function). */
370 #define ARM_FLAG_APCS_32 (1 << 3)
371
372 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
373
374 /* Nonzero if stack checking should be performed on entry to each function
375 which allocates temporary variables on the stack. */
376 #define ARM_FLAG_APCS_STACK (1 << 4)
377
378 /* Nonzero if floating point parameters should be passed to functions in
379 floating point registers. */
380 #define ARM_FLAG_APCS_FLOAT (1 << 5)
381
382 /* Nonzero if re-entrant, position independent code should be generated.
383 This is equivalent to -fpic. */
384 #define ARM_FLAG_APCS_REENT (1 << 6)
385
386 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
387 be loaded using either LDRH or LDRB instructions. */
388 #define ARM_FLAG_MMU_TRAPS (1 << 7)
389
390 /* Nonzero if all floating point instructions are missing (and there is no
391 emulator either). Generate function calls for all ops in this case. */
392 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
393
394 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
395 #define ARM_FLAG_BIG_END (1 << 9)
396
397 /* Nonzero if we should compile for Thumb interworking. */
398 #define ARM_FLAG_INTERWORK (1 << 10)
399
400 /* Nonzero if we should have little-endian words even when compiling for
401 big-endian (for backwards compatibility with older versions of GCC). */
402 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
403
404 /* Nonzero if we need to protect the prolog from scheduling */
405 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
406
407 /* Nonzero if a call to abort should be generated if a noreturn
408 function tries to return. */
409 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
410
411 /* Nonzero if function prologues should not load the PIC register. */
412 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
413
414 /* Nonzero if all call instructions should be indirect. */
415 #define ARM_FLAG_LONG_CALLS (1 << 15)
416
417 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
418 #define ARM_FLAG_THUMB (1 << 16)
419
420 /* Set if a TPCS style stack frame should be generated, for non-leaf
421 functions, even if they do not need one. */
422 #define THUMB_FLAG_BACKTRACE (1 << 17)
423
424 /* Set if a TPCS style stack frame should be generated, for leaf
425 functions, even if they do not need one. */
426 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
427
428 /* Set if externally visible functions should assume that they
429 might be called in ARM mode, from a non-thumb aware code. */
430 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
431
432 /* Set if calls via function pointers should assume that their
433 destination is non-Thumb aware. */
434 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
435
436 /* Nonzero means target uses VFP FP. */
437 #define ARM_FLAG_VFP (1 << 21)
438
439 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
440 #define ARM_FLAG_ATPCS (1 << 22)
441
442 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
443 #define CIRRUS_FIX_INVALID_INSNS (1 << 23)
444
445 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
446 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
447 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
448 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
449 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
450 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
451 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
452 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
453 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
454 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
455 #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
456 #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
457 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
458 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
459 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
460 #define TARGET_IWMMXT (arm_arch_iwmmxt)
461 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
462 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
463 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
464 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
465 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
466 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
467 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
468 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
469 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
470 #define TARGET_ARM (! TARGET_THUMB)
471 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
472 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
473 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
474 #define TARGET_BACKTRACE (leaf_function_p () \
475 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
476 : (target_flags & THUMB_FLAG_BACKTRACE))
477 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
478
479 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
480 #ifndef SUBTARGET_SWITCHES
481 #define SUBTARGET_SWITCHES
482 #endif
483
484 #define TARGET_SWITCHES \
485 { \
486 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
487 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
488 N_("Generate APCS conformant stack frames") }, \
489 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
490 {"poke-function-name", ARM_FLAG_POKE, \
491 N_("Store function names in object code") }, \
492 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
493 {"fpe", ARM_FLAG_FPE, "" }, \
494 {"apcs-32", ARM_FLAG_APCS_32, \
495 N_("Use the 32-bit version of the APCS") }, \
496 {"apcs-26", -ARM_FLAG_APCS_32, \
497 N_("Use the 26-bit version of the APCS") }, \
498 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
499 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
500 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
501 N_("Pass FP arguments in FP registers") }, \
502 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
503 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
504 N_("Generate re-entrant, PIC code") }, \
505 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
506 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
507 N_("The MMU will trap on unaligned accesses") }, \
508 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
509 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
510 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
511 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
512 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
513 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
514 N_("Use library calls to perform FP operations") }, \
515 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
516 N_("Use hardware floating point instructions") }, \
517 {"big-endian", ARM_FLAG_BIG_END, \
518 N_("Assume target CPU is configured as big endian") }, \
519 {"little-endian", -ARM_FLAG_BIG_END, \
520 N_("Assume target CPU is configured as little endian") }, \
521 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
522 N_("Assume big endian bytes, little endian words") }, \
523 {"thumb-interwork", ARM_FLAG_INTERWORK, \
524 N_("Support calls between Thumb and ARM instruction sets") }, \
525 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
526 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
527 N_("Generate a call to abort if a noreturn function returns")}, \
528 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
529 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
530 N_("Do not move instructions into a function's prologue") }, \
531 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
532 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
533 N_("Do not load the PIC register in function prologues") }, \
534 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
535 {"long-calls", ARM_FLAG_LONG_CALLS, \
536 N_("Generate call insns as indirect calls, if necessary") }, \
537 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
538 {"thumb", ARM_FLAG_THUMB, \
539 N_("Compile for the Thumb not the ARM") }, \
540 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
541 {"arm", -ARM_FLAG_THUMB, "" }, \
542 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
543 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
544 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
545 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
546 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
547 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
548 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
549 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
550 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
551 "" }, \
552 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
553 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
554 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
555 "" }, \
556 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
557 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
558 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
559 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
560 SUBTARGET_SWITCHES \
561 {"", TARGET_DEFAULT, "" } \
562 }
563
564 #define TARGET_OPTIONS \
565 { \
566 {"cpu=", & arm_select[0].string, \
567 N_("Specify the name of the target CPU"), 0}, \
568 {"arch=", & arm_select[1].string, \
569 N_("Specify the name of the target architecture"), 0}, \
570 {"tune=", & arm_select[2].string, "", 0}, \
571 {"fpe=", & target_fpe_name, "", 0}, \
572 {"fp=", & target_fpe_name, "", 0}, \
573 {"fpu=", & target_fpu_name, \
574 N_("Specify the name of the target floating point hardware/format"), 0}, \
575 {"float-abi=", & target_float_abi_name, \
576 N_("Specify if floating point hardware should be used"), 0}, \
577 {"structure-size-boundary=", & structure_size_string, \
578 N_("Specify the minimum bit alignment of structures"), 0}, \
579 {"pic-register=", & arm_pic_register_string, \
580 N_("Specify the register to be used for PIC addressing"), 0} \
581 }
582
583 /* Support for a compile-time default CPU, et cetera. The rules are:
584 --with-arch is ignored if -march or -mcpu are specified.
585 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
586 by --with-arch.
587 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
588 by -march).
589 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
590 specified.
591 --with-fpu is ignored if -mfpu is specified. */
592 #define OPTION_DEFAULT_SPECS \
593 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
594 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
595 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
596 {"float", \
597 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
598 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"},
599
600 struct arm_cpu_select
601 {
602 const char * string;
603 const char * name;
604 const struct processors * processors;
605 };
606
607 /* This is a magic array. If the user specifies a command line switch
608 which matches one of the entries in TARGET_OPTIONS then the corresponding
609 string pointer will be set to the value specified by the user. */
610 extern struct arm_cpu_select arm_select[];
611
612 enum prog_mode_type
613 {
614 prog_mode26,
615 prog_mode32
616 };
617
618 /* Recast the program mode class to be the prog_mode attribute. */
619 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
620
621 extern enum prog_mode_type arm_prgmode;
622
623 /* Which floating point model to use. */
624 enum arm_fp_model
625 {
626 ARM_FP_MODEL_UNKNOWN,
627 /* FPA model (Hardware or software). */
628 ARM_FP_MODEL_FPA,
629 /* Cirrus Maverick floating point model. */
630 ARM_FP_MODEL_MAVERICK,
631 /* VFP floating point model. */
632 ARM_FP_MODEL_VFP
633 };
634
635 extern enum arm_fp_model arm_fp_model;
636
637 /* Which floating point hardware is available. Also update
638 fp_model_for_fpu in arm.c when adding entries to this list. */
639 enum fputype
640 {
641 /* No FP hardware. */
642 FPUTYPE_NONE,
643 /* Full FPA support. */
644 FPUTYPE_FPA,
645 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
646 FPUTYPE_FPA_EMU2,
647 /* Emulated FPA hardware, Issue 3 emulator. */
648 FPUTYPE_FPA_EMU3,
649 /* Cirrus Maverick floating point co-processor. */
650 FPUTYPE_MAVERICK,
651 /* VFP. */
652 FPUTYPE_VFP
653 };
654
655 /* Recast the floating point class to be the floating point attribute. */
656 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
657
658 /* What type of floating point to tune for */
659 extern enum fputype arm_fpu_tune;
660
661 /* What type of floating point instructions are available */
662 extern enum fputype arm_fpu_arch;
663
664 enum float_abi_type
665 {
666 ARM_FLOAT_ABI_SOFT,
667 ARM_FLOAT_ABI_SOFTFP,
668 ARM_FLOAT_ABI_HARD
669 };
670
671 extern enum float_abi_type arm_float_abi;
672
673 /* Default floating point architecture. Override in sub-target if
674 necessary.
675 FIXME: Is this still necessary/desirable? Do we want VFP chips to
676 default to VFP unless overridden by a subtarget? If so it would be best
677 to remove these definitions. It also assumes there is only one cpu model
678 with a Maverick fpu. */
679 #ifndef FPUTYPE_DEFAULT
680 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
681 #endif
682
683 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
684 #undef FPUTYPE_DEFAULT
685 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
686 #endif
687
688 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
689 extern int arm_arch3m;
690
691 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
692 extern int arm_arch4;
693
694 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
695 extern int arm_arch5;
696
697 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
698 extern int arm_arch5e;
699
700 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
701 extern int arm_arch6;
702
703 /* Nonzero if this chip can benefit from load scheduling. */
704 extern int arm_ld_sched;
705
706 /* Nonzero if generating thumb code. */
707 extern int thumb_code;
708
709 /* Nonzero if this chip is a StrongARM. */
710 extern int arm_is_strong;
711
712 /* Nonzero if this chip is a Cirrus variant. */
713 extern int arm_is_cirrus;
714
715 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
716 extern int arm_arch_iwmmxt;
717
718 /* Nonzero if this chip is an XScale. */
719 extern int arm_arch_xscale;
720
721 /* Nonzero if tuning for XScale */
722 extern int arm_tune_xscale;
723
724 /* Nonzero if this chip is an ARM6 or an ARM7. */
725 extern int arm_is_6_or_7;
726
727 #ifndef TARGET_DEFAULT
728 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
729 #endif
730
731 /* The frame pointer register used in gcc has nothing to do with debugging;
732 that is controlled by the APCS-FRAME option. */
733 #define CAN_DEBUG_WITHOUT_FP
734
735 #undef TARGET_MEM_FUNCTIONS
736 #define TARGET_MEM_FUNCTIONS 1
737
738 #define OVERRIDE_OPTIONS arm_override_options ()
739
740 /* Nonzero if PIC code requires explicit qualifiers to generate
741 PLT and GOT relocs rather than the assembler doing so implicitly.
742 Subtargets can override these if required. */
743 #ifndef NEED_GOT_RELOC
744 #define NEED_GOT_RELOC 0
745 #endif
746 #ifndef NEED_PLT_RELOC
747 #define NEED_PLT_RELOC 0
748 #endif
749
750 /* Nonzero if we need to refer to the GOT with a PC-relative
751 offset. In other words, generate
752
753 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
754
755 rather than
756
757 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
758
759 The default is true, which matches NetBSD. Subtargets can
760 override this if required. */
761 #ifndef GOT_PCREL
762 #define GOT_PCREL 1
763 #endif
764 \f
765 /* Target machine storage Layout. */
766
767
768 /* Define this macro if it is advisable to hold scalars in registers
769 in a wider mode than that declared by the program. In such cases,
770 the value is constrained to be within the bounds of the declared
771 type, but kept valid in the wider mode. The signedness of the
772 extension may differ from that of the type. */
773
774 /* It is far faster to zero extend chars than to sign extend them */
775
776 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
777 if (GET_MODE_CLASS (MODE) == MODE_INT \
778 && GET_MODE_SIZE (MODE) < 4) \
779 { \
780 if (MODE == QImode) \
781 UNSIGNEDP = 1; \
782 else if (MODE == HImode) \
783 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
784 (MODE) = SImode; \
785 }
786
787 /* Define this if most significant bit is lowest numbered
788 in instructions that operate on numbered bit-fields. */
789 #define BITS_BIG_ENDIAN 0
790
791 /* Define this if most significant byte of a word is the lowest numbered.
792 Most ARM processors are run in little endian mode, so that is the default.
793 If you want to have it run-time selectable, change the definition in a
794 cover file to be TARGET_BIG_ENDIAN. */
795 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
796
797 /* Define this if most significant word of a multiword number is the lowest
798 numbered.
799 This is always false, even when in big-endian mode. */
800 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
801
802 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
803 on processor pre-defineds when compiling libgcc2.c. */
804 #if defined(__ARMEB__) && !defined(__ARMWEL__)
805 #define LIBGCC2_WORDS_BIG_ENDIAN 1
806 #else
807 #define LIBGCC2_WORDS_BIG_ENDIAN 0
808 #endif
809
810 /* Define this if most significant word of doubles is the lowest numbered.
811 The rules are different based on whether or not we use FPA-format,
812 VFP-format or some other floating point co-processor's format doubles. */
813 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
814
815 #define UNITS_PER_WORD 4
816
817 #define PARM_BOUNDARY 32
818
819 #define IWMMXT_ALIGNMENT 64
820
821 #define STACK_BOUNDARY 32
822
823 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
824
825 #define FUNCTION_BOUNDARY 32
826
827 /* The lowest bit is used to indicate Thumb-mode functions, so the
828 vbit must go into the delta field of pointers to member
829 functions. */
830 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
831
832 #define EMPTY_FIELD_BOUNDARY 32
833
834 #define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32)
835
836 #define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \
837 (TARGET_REALLY_IWMMXT \
838 && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode)))
839
840 /* XXX Blah -- this macro is used directly by libobjc. Since it
841 supports no vector modes, cut out the complexity and fall back
842 on BIGGEST_FIELD_ALIGNMENT. */
843 #ifdef IN_TARGET_LIBS
844 #define BIGGEST_FIELD_ALIGNMENT 64
845 #else
846 /* An expression for the alignment of a structure field FIELD if the
847 alignment computed in the usual way is COMPUTED. GCC uses this
848 value instead of the value in `BIGGEST_ALIGNMENT' or
849 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
850 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
851 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \
852 ? IWMMXT_ALIGNMENT \
853 : (COMPUTED))
854 #endif
855
856 /* If defined, a C expression to compute the alignment for a static variable.
857 TYPE is the data type, and ALIGN is the alignment that the object
858 would ordinarily have. The value of this macro is used instead of that
859 alignment to align the object.
860
861 If this macro is not defined, then ALIGN is used. */
862 #define DATA_ALIGNMENT(TYPE, ALIGN) \
863 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
864
865 /* If defined, a C expression to compute the alignment for a
866 variables in the local store. TYPE is the data type, and
867 BASIC-ALIGN is the alignment that the object would ordinarily
868 have. The value of this macro is used instead of that alignment
869 to align the object.
870
871 If this macro is not defined, then BASIC-ALIGN is used. */
872 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
873 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
874
875 /* Make strings word-aligned so strcpy from constants will be faster. */
876 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
877
878 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
879 ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \
880 (TREE_CODE (EXP) == STRING_CST \
881 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
882 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
883
884 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
885 value set in previous versions of this toolchain was 8, which produces more
886 compact structures. The command line option -mstructure_size_boundary=<n>
887 can be used to change this value. For compatibility with the ARM SDK
888 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
889 0020D) page 2-20 says "Structures are aligned on word boundaries". */
890 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
891 extern int arm_structure_size_boundary;
892
893 /* This is the value used to initialize arm_structure_size_boundary. If a
894 particular arm target wants to change the default value it should change
895 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
896 for an example of this. */
897 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
898 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
899 #endif
900
901 /* Used when parsing command line option -mstructure_size_boundary. */
902 extern const char * structure_size_string;
903
904 /* Nonzero if move instructions will actually fail to work
905 when given unaligned data. */
906 #define STRICT_ALIGNMENT 1
907 \f
908 /* Standard register usage. */
909
910 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
911 (S - saved over call).
912
913 r0 * argument word/integer result
914 r1-r3 argument word
915
916 r4-r8 S register variable
917 r9 S (rfp) register variable (real frame pointer)
918
919 r10 F S (sl) stack limit (used by -mapcs-stack-check)
920 r11 F S (fp) argument pointer
921 r12 (ip) temp workspace
922 r13 F S (sp) lower end of current stack frame
923 r14 (lr) link address/workspace
924 r15 F (pc) program counter
925
926 f0 floating point result
927 f1-f3 floating point scratch
928
929 f4-f7 S floating point variable
930
931 cc This is NOT a real register, but is used internally
932 to represent things that use or set the condition
933 codes.
934 sfp This isn't either. It is used during rtl generation
935 since the offset between the frame pointer and the
936 auto's isn't known until after register allocation.
937 afp Nor this, we only need this because of non-local
938 goto. Without it fp appears to be used and the
939 elimination code won't get rid of sfp. It tracks
940 fp exactly at all times.
941
942 *: See CONDITIONAL_REGISTER_USAGE */
943
944 /*
945 mvf0 Cirrus floating point result
946 mvf1-mvf3 Cirrus floating point scratch
947 mvf4-mvf15 S Cirrus floating point variable. */
948
949 /* s0-s15 VFP scratch (aka d0-d7).
950 s16-s31 S VFP variable (aka d8-d15).
951 vfpcc Not a real register. Represents the VFP condition
952 code flags. */
953
954 /* The stack backtrace structure is as follows:
955 fp points to here: | save code pointer | [fp]
956 | return link value | [fp, #-4]
957 | return sp value | [fp, #-8]
958 | return fp value | [fp, #-12]
959 [| saved r10 value |]
960 [| saved r9 value |]
961 [| saved r8 value |]
962 [| saved r7 value |]
963 [| saved r6 value |]
964 [| saved r5 value |]
965 [| saved r4 value |]
966 [| saved r3 value |]
967 [| saved r2 value |]
968 [| saved r1 value |]
969 [| saved r0 value |]
970 [| saved f7 value |] three words
971 [| saved f6 value |] three words
972 [| saved f5 value |] three words
973 [| saved f4 value |] three words
974 r0-r3 are not normally saved in a C function. */
975
976 /* 1 for registers that have pervasive standard uses
977 and are not available for the register allocator. */
978 #define FIXED_REGISTERS \
979 { \
980 0,0,0,0,0,0,0,0, \
981 0,0,0,0,0,1,0,1, \
982 0,0,0,0,0,0,0,0, \
983 1,1,1, \
984 1,1,1,1,1,1,1,1, \
985 1,1,1,1,1,1,1,1, \
986 1,1,1,1,1,1,1,1, \
987 1,1,1,1,1,1,1,1, \
988 1,1,1,1, \
989 1,1,1,1,1,1,1,1, \
990 1,1,1,1,1,1,1,1, \
991 1,1,1,1,1,1,1,1, \
992 1,1,1,1,1,1,1,1, \
993 1 \
994 }
995
996 /* 1 for registers not available across function calls.
997 These must include the FIXED_REGISTERS and also any
998 registers that can be used without being saved.
999 The latter must include the registers where values are returned
1000 and the register where structure-value addresses are passed.
1001 Aside from that, you can include as many other registers as you like.
1002 The CC is not preserved over function calls on the ARM 6, so it is
1003 easier to assume this for all. SFP is preserved, since FP is. */
1004 #define CALL_USED_REGISTERS \
1005 { \
1006 1,1,1,1,0,0,0,0, \
1007 0,0,0,0,1,1,1,1, \
1008 1,1,1,1,0,0,0,0, \
1009 1,1,1, \
1010 1,1,1,1,1,1,1,1, \
1011 1,1,1,1,1,1,1,1, \
1012 1,1,1,1,1,1,1,1, \
1013 1,1,1,1,1,1,1,1, \
1014 1,1,1,1, \
1015 1,1,1,1,1,1,1,1, \
1016 1,1,1,1,1,1,1,1, \
1017 1,1,1,1,1,1,1,1, \
1018 1,1,1,1,1,1,1,1, \
1019 1 \
1020 }
1021
1022 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
1023 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
1024 #endif
1025
1026 #define CONDITIONAL_REGISTER_USAGE \
1027 { \
1028 int regno; \
1029 \
1030 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
1031 { \
1032 for (regno = FIRST_FPA_REGNUM; \
1033 regno <= LAST_FPA_REGNUM; ++regno) \
1034 fixed_regs[regno] = call_used_regs[regno] = 1; \
1035 } \
1036 \
1037 if (TARGET_THUMB && optimize_size) \
1038 { \
1039 /* When optimizing for size, it's better not to use \
1040 the HI regs, because of the overhead of stacking \
1041 them. */ \
1042 for (regno = FIRST_HI_REGNUM; \
1043 regno <= LAST_HI_REGNUM; ++regno) \
1044 fixed_regs[regno] = call_used_regs[regno] = 1; \
1045 } \
1046 \
1047 /* The link register can be clobbered by any branch insn, \
1048 but we have no way to track that at present, so mark \
1049 it as unavailable. */ \
1050 if (TARGET_THUMB) \
1051 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
1052 \
1053 if (TARGET_ARM && TARGET_HARD_FLOAT) \
1054 { \
1055 if (TARGET_MAVERICK) \
1056 { \
1057 for (regno = FIRST_FPA_REGNUM; \
1058 regno <= LAST_FPA_REGNUM; ++ regno) \
1059 fixed_regs[regno] = call_used_regs[regno] = 1; \
1060 for (regno = FIRST_CIRRUS_FP_REGNUM; \
1061 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
1062 { \
1063 fixed_regs[regno] = 0; \
1064 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
1065 } \
1066 } \
1067 if (TARGET_VFP) \
1068 { \
1069 for (regno = FIRST_VFP_REGNUM; \
1070 regno <= LAST_VFP_REGNUM; ++ regno) \
1071 { \
1072 fixed_regs[regno] = 0; \
1073 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
1074 } \
1075 } \
1076 } \
1077 \
1078 if (TARGET_REALLY_IWMMXT) \
1079 { \
1080 regno = FIRST_IWMMXT_GR_REGNUM; \
1081 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
1082 and wCG1 as call-preserved registers. The 2002/11/21 \
1083 revision changed this so that all wCG registers are \
1084 scratch registers. */ \
1085 for (regno = FIRST_IWMMXT_GR_REGNUM; \
1086 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
1087 fixed_regs[regno] = call_used_regs[regno] = 0; \
1088 /* The XScale ABI has wR0 - wR9 as scratch registers, \
1089 the rest as call-preserved registers. */ \
1090 for (regno = FIRST_IWMMXT_REGNUM; \
1091 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
1092 { \
1093 fixed_regs[regno] = 0; \
1094 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
1095 } \
1096 } \
1097 \
1098 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1099 { \
1100 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1101 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1102 } \
1103 else if (TARGET_APCS_STACK) \
1104 { \
1105 fixed_regs[10] = 1; \
1106 call_used_regs[10] = 1; \
1107 } \
1108 if (TARGET_APCS_FRAME) \
1109 { \
1110 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1111 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1112 } \
1113 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
1114 }
1115
1116 /* These are a couple of extensions to the formats accepted
1117 by asm_fprintf:
1118 %@ prints out ASM_COMMENT_START
1119 %r prints out REGISTER_PREFIX reg_names[arg] */
1120 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
1121 case '@': \
1122 fputs (ASM_COMMENT_START, FILE); \
1123 break; \
1124 \
1125 case 'r': \
1126 fputs (REGISTER_PREFIX, FILE); \
1127 fputs (reg_names [va_arg (ARGS, int)], FILE); \
1128 break;
1129
1130 /* Round X up to the nearest word. */
1131 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
1132
1133 /* Convert fron bytes to ints. */
1134 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1135
1136 /* The number of (integer) registers required to hold a quantity of type MODE.
1137 Also used for VFP registers. */
1138 #define ARM_NUM_REGS(MODE) \
1139 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
1140
1141 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
1142 #define ARM_NUM_REGS2(MODE, TYPE) \
1143 ARM_NUM_INTS ((MODE) == BLKmode ? \
1144 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1145
1146 /* The number of (integer) argument register available. */
1147 #define NUM_ARG_REGS 4
1148
1149 /* Return the register number of the N'th (integer) argument. */
1150 #define ARG_REGISTER(N) (N - 1)
1151
1152 /* Specify the registers used for certain standard purposes.
1153 The values of these macros are register numbers. */
1154
1155 /* The number of the last argument register. */
1156 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
1157
1158 /* The numbers of the Thumb register ranges. */
1159 #define FIRST_LO_REGNUM 0
1160 #define LAST_LO_REGNUM 7
1161 #define FIRST_HI_REGNUM 8
1162 #define LAST_HI_REGNUM 11
1163
1164 /* The register that holds the return address in exception handlers. */
1165 #define EXCEPTION_LR_REGNUM 2
1166
1167 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1168 as an invisible last argument (possible since varargs don't exist in
1169 Pascal), so the following is not true. */
1170 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1171
1172 /* Define this to be where the real frame pointer is if it is not possible to
1173 work out the offset between the frame pointer and the automatic variables
1174 until after register allocation has taken place. FRAME_POINTER_REGNUM
1175 should point to a special register that we will make sure is eliminated.
1176
1177 For the Thumb we have another problem. The TPCS defines the frame pointer
1178 as r11, and GCC believes that it is always possible to use the frame pointer
1179 as base register for addressing purposes. (See comments in
1180 find_reloads_address()). But - the Thumb does not allow high registers,
1181 including r11, to be used as base address registers. Hence our problem.
1182
1183 The solution used here, and in the old thumb port is to use r7 instead of
1184 r11 as the hard frame pointer and to have special code to generate
1185 backtrace structures on the stack (if required to do so via a command line
1186 option) using r11. This is the only 'user visible' use of r11 as a frame
1187 pointer. */
1188 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1189 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1190
1191 #define HARD_FRAME_POINTER_REGNUM \
1192 (TARGET_ARM \
1193 ? ARM_HARD_FRAME_POINTER_REGNUM \
1194 : THUMB_HARD_FRAME_POINTER_REGNUM)
1195
1196 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1197
1198 /* Register to use for pushing function arguments. */
1199 #define STACK_POINTER_REGNUM SP_REGNUM
1200
1201 /* ARM floating pointer registers. */
1202 #define FIRST_FPA_REGNUM 16
1203 #define LAST_FPA_REGNUM 23
1204
1205 #define FIRST_IWMMXT_GR_REGNUM 43
1206 #define LAST_IWMMXT_GR_REGNUM 46
1207 #define FIRST_IWMMXT_REGNUM 47
1208 #define LAST_IWMMXT_REGNUM 62
1209 #define IS_IWMMXT_REGNUM(REGNUM) \
1210 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1211 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1212 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1213
1214 /* Base register for access to local variables of the function. */
1215 #define FRAME_POINTER_REGNUM 25
1216
1217 /* Base register for access to arguments of the function. */
1218 #define ARG_POINTER_REGNUM 26
1219
1220 #define FIRST_CIRRUS_FP_REGNUM 27
1221 #define LAST_CIRRUS_FP_REGNUM 42
1222 #define IS_CIRRUS_REGNUM(REGNUM) \
1223 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1224
1225 #define FIRST_VFP_REGNUM 63
1226 #define LAST_VFP_REGNUM 94
1227 #define IS_VFP_REGNUM(REGNUM) \
1228 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1229
1230 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1231 /* + 16 Cirrus registers take us up to 43. */
1232 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1233 /* VFP adds 32 + 1 more. */
1234 #define FIRST_PSEUDO_REGISTER 96
1235
1236 /* Value should be nonzero if functions must have frame pointers.
1237 Zero means the frame pointer need not be set up (and parms may be accessed
1238 via the stack pointer) in functions that seem suitable.
1239 If we have to have a frame pointer we might as well make use of it.
1240 APCS says that the frame pointer does not need to be pushed in leaf
1241 functions, or simple tail call functions. */
1242 #define FRAME_POINTER_REQUIRED \
1243 (current_function_has_nonlocal_label \
1244 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1245
1246 /* Return number of consecutive hard regs needed starting at reg REGNO
1247 to hold something of mode MODE.
1248 This is ordinarily the length in words of a value of mode MODE
1249 but can be less for certain modes in special long registers.
1250
1251 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1252 mode. */
1253 #define HARD_REGNO_NREGS(REGNO, MODE) \
1254 ((TARGET_ARM \
1255 && REGNO >= FIRST_FPA_REGNUM \
1256 && REGNO != FRAME_POINTER_REGNUM \
1257 && REGNO != ARG_POINTER_REGNUM) \
1258 && !IS_VFP_REGNUM (REGNO) \
1259 ? 1 : ARM_NUM_REGS (MODE))
1260
1261 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1262 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1263 arm_hard_regno_mode_ok ((REGNO), (MODE))
1264
1265 /* Value is 1 if it is a good idea to tie two pseudo registers
1266 when one has mode MODE1 and one has mode MODE2.
1267 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1268 for any hard reg, then this must be 0 for correct output. */
1269 #define MODES_TIEABLE_P(MODE1, MODE2) \
1270 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1271
1272 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1273 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1274
1275 #define VALID_IWMMXT_REG_MODE(MODE) \
1276 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1277
1278 /* The order in which register should be allocated. It is good to use ip
1279 since no saving is required (though calls clobber it) and it never contains
1280 function parameters. It is quite good to use lr since other calls may
1281 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1282 least likely to contain a function parameter; in addition results are
1283 returned in r0. */
1284
1285 #define REG_ALLOC_ORDER \
1286 { \
1287 3, 2, 1, 0, 12, 14, 4, 5, \
1288 6, 7, 8, 10, 9, 11, 13, 15, \
1289 16, 17, 18, 19, 20, 21, 22, 23, \
1290 27, 28, 29, 30, 31, 32, 33, 34, \
1291 35, 36, 37, 38, 39, 40, 41, 42, \
1292 43, 44, 45, 46, 47, 48, 49, 50, \
1293 51, 52, 53, 54, 55, 56, 57, 58, \
1294 59, 60, 61, 62, \
1295 24, 25, 26, \
1296 78, 77, 76, 75, 74, 73, 72, 71, \
1297 70, 69, 68, 67, 66, 65, 64, 63, \
1298 79, 80, 81, 82, 83, 84, 85, 86, \
1299 87, 88, 89, 90, 91, 92, 93, 94, \
1300 95 \
1301 }
1302
1303 /* Interrupt functions can only use registers that have already been
1304 saved by the prologue, even if they would normally be
1305 call-clobbered. */
1306 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1307 (! IS_INTERRUPT (cfun->machine->func_type) || \
1308 regs_ever_live[DST])
1309 \f
1310 /* Register and constant classes. */
1311
1312 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1313 Now that the Thumb is involved it has become more complicated. */
1314 enum reg_class
1315 {
1316 NO_REGS,
1317 FPA_REGS,
1318 CIRRUS_REGS,
1319 VFP_REGS,
1320 IWMMXT_GR_REGS,
1321 IWMMXT_REGS,
1322 LO_REGS,
1323 STACK_REG,
1324 BASE_REGS,
1325 HI_REGS,
1326 CC_REG,
1327 VFPCC_REG,
1328 GENERAL_REGS,
1329 ALL_REGS,
1330 LIM_REG_CLASSES
1331 };
1332
1333 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1334
1335 /* Give names of register classes as strings for dump file. */
1336 #define REG_CLASS_NAMES \
1337 { \
1338 "NO_REGS", \
1339 "FPA_REGS", \
1340 "CIRRUS_REGS", \
1341 "VFP_REGS", \
1342 "IWMMXT_GR_REGS", \
1343 "IWMMXT_REGS", \
1344 "LO_REGS", \
1345 "STACK_REG", \
1346 "BASE_REGS", \
1347 "HI_REGS", \
1348 "CC_REG", \
1349 "VFPCC_REG", \
1350 "GENERAL_REGS", \
1351 "ALL_REGS", \
1352 }
1353
1354 /* Define which registers fit in which classes.
1355 This is an initializer for a vector of HARD_REG_SET
1356 of length N_REG_CLASSES. */
1357 #define REG_CLASS_CONTENTS \
1358 { \
1359 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1360 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1361 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1362 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1363 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1364 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1365 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1366 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1367 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1368 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1369 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1370 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1371 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1372 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1373 }
1374
1375 /* The same information, inverted:
1376 Return the class number of the smallest class containing
1377 reg number REGNO. This could be a conditional expression
1378 or could index an array. */
1379 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1380
1381 /* FPA registers can't do subreg as all values are reformatted to internal
1382 precision. VFP registers may only be accessed in the mode they
1383 were set. */
1384 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1385 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1386 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1387 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1388 : 0)
1389
1390 /* The class value for index registers, and the one for base regs. */
1391 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1392 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1393
1394 /* For the Thumb the high registers cannot be used as base registers
1395 when addressing quantities in QI or HI mode; if we don't know the
1396 mode, then we must be conservative. After reload we must also be
1397 conservative, since we can't support SP+reg addressing, and we
1398 can't fix up any bad substitutions. */
1399 #define MODE_BASE_REG_CLASS(MODE) \
1400 (TARGET_ARM ? GENERAL_REGS : \
1401 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1402
1403 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1404 registers explicitly used in the rtl to be used as spill registers
1405 but prevents the compiler from extending the lifetime of these
1406 registers. */
1407 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1408
1409 /* Get reg_class from a letter such as appears in the machine description.
1410 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1411 ARM, but several more letters for the Thumb. */
1412 #define REG_CLASS_FROM_LETTER(C) \
1413 ( (C) == 'f' ? FPA_REGS \
1414 : (C) == 'v' ? CIRRUS_REGS \
1415 : (C) == 'w' ? VFP_REGS \
1416 : (C) == 'y' ? IWMMXT_REGS \
1417 : (C) == 'z' ? IWMMXT_GR_REGS \
1418 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1419 : TARGET_ARM ? NO_REGS \
1420 : (C) == 'h' ? HI_REGS \
1421 : (C) == 'b' ? BASE_REGS \
1422 : (C) == 'k' ? STACK_REG \
1423 : (C) == 'c' ? CC_REG \
1424 : NO_REGS)
1425
1426 /* The letters I, J, K, L and M in a register constraint string
1427 can be used to stand for particular ranges of immediate operands.
1428 This macro defines what the ranges are.
1429 C is the letter, and VALUE is a constant value.
1430 Return 1 if VALUE is in the range specified by C.
1431 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1432 J: valid indexing constants.
1433 K: ~value ok in rhs argument of data operand.
1434 L: -value ok in rhs argument of data operand.
1435 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1436 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1437 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1438 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1439 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1440 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1441 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1442 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1443 : 0)
1444
1445 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1446 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1447 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1448 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1449 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1450 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1451 && ((VAL) & 3) == 0) : \
1452 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1453 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1454 : 0)
1455
1456 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1457 (TARGET_ARM ? \
1458 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1459
1460 /* Constant letter 'G' for the FP immediate constants.
1461 'H' means the same constant negated. */
1462 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1463 ((C) == 'G' ? arm_const_double_rtx (X) : \
1464 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1465
1466 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1467 (TARGET_ARM ? \
1468 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1469
1470 /* For the ARM, `Q' means that this is a memory operand that is just
1471 an offset from a register.
1472 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1473 address. This means that the symbol is in the text segment and can be
1474 accessed without using a load.
1475 'U' is an address valid for VFP load/store insns. */
1476
1477 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1478 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1479 (C) == 'R' ? (GET_CODE (OP) == MEM \
1480 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1481 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1482 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1483 (C) == 'T' ? cirrus_memory_offset (OP) : \
1484 (C) == 'U' ? vfp_mem_operand (OP) : \
1485 0)
1486
1487 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1488 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1489 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1490
1491 #define EXTRA_CONSTRAINT(X, C) \
1492 (TARGET_ARM ? \
1493 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1494
1495 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1496
1497 /* Given an rtx X being reloaded into a reg required to be
1498 in class CLASS, return the class of reg to actually use.
1499 In general this is just CLASS, but for the Thumb we prefer
1500 a LO_REGS class or a subset. */
1501 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1502 (TARGET_ARM ? (CLASS) : \
1503 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1504
1505 /* Must leave BASE_REGS reloads alone */
1506 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1507 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1508 ? ((true_regnum (X) == -1 ? LO_REGS \
1509 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1510 : NO_REGS)) \
1511 : NO_REGS)
1512
1513 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1514 ((CLASS) != LO_REGS \
1515 ? ((true_regnum (X) == -1 ? LO_REGS \
1516 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1517 : NO_REGS)) \
1518 : NO_REGS)
1519
1520 /* Return the register class of a scratch register needed to copy IN into
1521 or out of a register in CLASS in MODE. If it can be done directly,
1522 NO_REGS is returned. */
1523 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1524 /* Restrict which direct reloads are allowed for VFP regs. */ \
1525 ((TARGET_VFP && TARGET_HARD_FLOAT \
1526 && (CLASS) == VFP_REGS) \
1527 ? vfp_secondary_reload_class (MODE, X) \
1528 : TARGET_ARM \
1529 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1530 ? GENERAL_REGS : NO_REGS) \
1531 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1532
1533 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1534 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1535 /* Restrict which direct reloads are allowed for VFP regs. */ \
1536 ((TARGET_VFP && TARGET_HARD_FLOAT \
1537 && (CLASS) == VFP_REGS) \
1538 ? vfp_secondary_reload_class (MODE, X) : \
1539 /* Cannot load constants into Cirrus registers. */ \
1540 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1541 && (CLASS) == CIRRUS_REGS \
1542 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1543 ? GENERAL_REGS : \
1544 (TARGET_ARM ? \
1545 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1546 && CONSTANT_P (X)) \
1547 ? GENERAL_REGS : \
1548 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1549 && (GET_CODE (X) == MEM \
1550 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1551 && true_regnum (X) == -1))) \
1552 ? GENERAL_REGS : NO_REGS) \
1553 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1554
1555 /* Try a machine-dependent way of reloading an illegitimate address
1556 operand. If we find one, push the reload and jump to WIN. This
1557 macro is used in only one place: `find_reloads_address' in reload.c.
1558
1559 For the ARM, we wish to handle large displacements off a base
1560 register by splitting the addend across a MOV and the mem insn.
1561 This can cut the number of reloads needed. */
1562 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1563 do \
1564 { \
1565 if (GET_CODE (X) == PLUS \
1566 && GET_CODE (XEXP (X, 0)) == REG \
1567 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1568 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1569 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1570 { \
1571 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1572 HOST_WIDE_INT low, high; \
1573 \
1574 if (MODE == DImode || (TARGET_SOFT_FLOAT && TARGET_FPA \
1575 && MODE == DFmode)) \
1576 low = ((val & 0xf) ^ 0x8) - 0x8; \
1577 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1578 /* Need to be careful, -256 is not a valid offset. */ \
1579 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1580 else if (MODE == SImode \
1581 || (MODE == SFmode && TARGET_SOFT_FLOAT && TARGET_FPA) \
1582 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1583 /* Need to be careful, -4096 is not a valid offset. */ \
1584 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1585 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1586 /* Need to be careful, -256 is not a valid offset. */ \
1587 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1588 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1589 && TARGET_HARD_FLOAT && TARGET_FPA) \
1590 /* Need to be careful, -1024 is not a valid offset. */ \
1591 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1592 else \
1593 break; \
1594 \
1595 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1596 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1597 - (unsigned HOST_WIDE_INT) 0x80000000); \
1598 /* Check for overflow or zero */ \
1599 if (low == 0 || high == 0 || (high + low != val)) \
1600 break; \
1601 \
1602 /* Reload the high part into a base reg; leave the low part \
1603 in the mem. */ \
1604 X = gen_rtx_PLUS (GET_MODE (X), \
1605 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1606 GEN_INT (high)), \
1607 GEN_INT (low)); \
1608 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1609 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1610 VOIDmode, 0, 0, OPNUM, TYPE); \
1611 goto WIN; \
1612 } \
1613 } \
1614 while (0)
1615
1616 /* XXX If an HImode FP+large_offset address is converted to an HImode
1617 SP+large_offset address, then reload won't know how to fix it. It sees
1618 only that SP isn't valid for HImode, and so reloads the SP into an index
1619 register, but the resulting address is still invalid because the offset
1620 is too big. We fix it here instead by reloading the entire address. */
1621 /* We could probably achieve better results by defining PROMOTE_MODE to help
1622 cope with the variances between the Thumb's signed and unsigned byte and
1623 halfword load instructions. */
1624 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1625 { \
1626 if (GET_CODE (X) == PLUS \
1627 && GET_MODE_SIZE (MODE) < 4 \
1628 && GET_CODE (XEXP (X, 0)) == REG \
1629 && XEXP (X, 0) == stack_pointer_rtx \
1630 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1631 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1632 { \
1633 rtx orig_X = X; \
1634 X = copy_rtx (X); \
1635 push_reload (orig_X, NULL_RTX, &X, NULL, \
1636 MODE_BASE_REG_CLASS (MODE), \
1637 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1638 goto WIN; \
1639 } \
1640 }
1641
1642 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1643 if (TARGET_ARM) \
1644 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1645 else \
1646 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1647
1648 /* Return the maximum number of consecutive registers
1649 needed to represent mode MODE in a register of class CLASS.
1650 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1651 #define CLASS_MAX_NREGS(CLASS, MODE) \
1652 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1653
1654 /* If defined, gives a class of registers that cannot be used as the
1655 operand of a SUBREG that changes the mode of the object illegally. */
1656
1657 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1658 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1659 (TARGET_ARM ? \
1660 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1661 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1662 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1663 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1664 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1665 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1666 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1667 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1668 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1669 2) \
1670 : \
1671 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1672 \f
1673 /* Stack layout; function entry, exit and calling. */
1674
1675 /* Define this if pushing a word on the stack
1676 makes the stack pointer a smaller address. */
1677 #define STACK_GROWS_DOWNWARD 1
1678
1679 /* Define this if the nominal address of the stack frame
1680 is at the high-address end of the local variables;
1681 that is, each additional local variable allocated
1682 goes at a more negative offset in the frame. */
1683 #define FRAME_GROWS_DOWNWARD 1
1684
1685 /* Offset within stack frame to start allocating local variables at.
1686 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1687 first local allocated. Otherwise, it is the offset to the BEGINNING
1688 of the first local allocated. */
1689 #define STARTING_FRAME_OFFSET 0
1690
1691 /* If we generate an insn to push BYTES bytes,
1692 this says how many the stack pointer really advances by. */
1693 /* The push insns do not do this rounding implicitly.
1694 So don't define this. */
1695 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1696
1697 /* Define this if the maximum size of all the outgoing args is to be
1698 accumulated and pushed during the prologue. The amount can be
1699 found in the variable current_function_outgoing_args_size. */
1700 #define ACCUMULATE_OUTGOING_ARGS 1
1701
1702 /* Offset of first parameter from the argument pointer register value. */
1703 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1704
1705 /* Value is the number of byte of arguments automatically
1706 popped when returning from a subroutine call.
1707 FUNDECL is the declaration node of the function (as a tree),
1708 FUNTYPE is the data type of the function (as a tree),
1709 or for a library call it is an identifier node for the subroutine name.
1710 SIZE is the number of bytes of arguments passed on the stack.
1711
1712 On the ARM, the caller does not pop any of its arguments that were passed
1713 on the stack. */
1714 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1715
1716 /* Define how to find the value returned by a library function
1717 assuming the value has mode MODE. */
1718 #define LIBCALL_VALUE(MODE) \
1719 (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
1720 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1721 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1722 : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
1723 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1724 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1725 : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \
1726 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1727 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1728
1729 /* Define how to find the value returned by a function.
1730 VALTYPE is the data type of the value (as a tree).
1731 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1732 otherwise, FUNC is 0. */
1733 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1734 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1735
1736 /* 1 if N is a possible register number for a function value.
1737 On the ARM, only r0 and f0 can return results. */
1738 /* On a Cirrus chip, mvf0 can return results. */
1739 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1740 ((REGNO) == ARG_REGISTER (1) \
1741 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1742 && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
1743 || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \
1744 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1745 && TARGET_HARD_FLOAT && TARGET_FPA))
1746
1747 /* How large values are returned */
1748 /* A C expression which can inhibit the returning of certain function values
1749 in registers, based on the type of value. */
1750 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1751
1752 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1753 values must be in memory. On the ARM, they need only do so if larger
1754 than a word, or if they contain elements offset from zero in the struct. */
1755 #define DEFAULT_PCC_STRUCT_RETURN 0
1756
1757 /* Flags for the call/call_value rtl operations set up by function_arg. */
1758 #define CALL_NORMAL 0x00000000 /* No special processing. */
1759 #define CALL_LONG 0x00000001 /* Always call indirect. */
1760 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1761
1762 /* These bits describe the different types of function supported
1763 by the ARM backend. They are exclusive. ie a function cannot be both a
1764 normal function and an interworked function, for example. Knowing the
1765 type of a function is important for determining its prologue and
1766 epilogue sequences.
1767 Note value 7 is currently unassigned. Also note that the interrupt
1768 function types all have bit 2 set, so that they can be tested for easily.
1769 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1770 machine_function structure is initialized (to zero) func_type will
1771 default to unknown. This will force the first use of arm_current_func_type
1772 to call arm_compute_func_type. */
1773 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1774 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1775 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1776 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1777 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1778 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1779 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1780
1781 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1782
1783 /* In addition functions can have several type modifiers,
1784 outlined by these bit masks: */
1785 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1786 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1787 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1788 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1789
1790 /* Some macros to test these flags. */
1791 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1792 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1793 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1794 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1795 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1796
1797 /* A C structure for machine-specific, per-function data.
1798 This is added to the cfun structure. */
1799 typedef struct machine_function GTY(())
1800 {
1801 /* Additional stack adjustment in __builtin_eh_throw. */
1802 rtx eh_epilogue_sp_ofs;
1803 /* Records if LR has to be saved for far jumps. */
1804 int far_jump_used;
1805 /* Records if ARG_POINTER was ever live. */
1806 int arg_pointer_live;
1807 /* Records if the save of LR has been eliminated. */
1808 int lr_save_eliminated;
1809 /* The size of the stack frame. Only valid after reload. */
1810 int frame_size;
1811 /* Records the type of the current function. */
1812 unsigned long func_type;
1813 /* Record if the function has a variable argument list. */
1814 int uses_anonymous_args;
1815 /* Records if sibcalls are blocked because an argument
1816 register is needed to preserve stack alignment. */
1817 int sibcall_blocked;
1818 }
1819 machine_function;
1820
1821 /* A C type for declaring a variable that is used as the first argument of
1822 `FUNCTION_ARG' and other related values. For some target machines, the
1823 type `int' suffices and can hold the number of bytes of argument so far. */
1824 typedef struct
1825 {
1826 /* This is the number of registers of arguments scanned so far. */
1827 int nregs;
1828 /* This is the number of iWMMXt register arguments scanned so far. */
1829 int iwmmxt_nregs;
1830 int named_count;
1831 int nargs;
1832 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1833 int call_cookie;
1834 } CUMULATIVE_ARGS;
1835
1836 /* Define where to put the arguments to a function.
1837 Value is zero to push the argument on the stack,
1838 or a hard register in which to store the argument.
1839
1840 MODE is the argument's machine mode.
1841 TYPE is the data type of the argument (as a tree).
1842 This is null for libcalls where that information may
1843 not be available.
1844 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1845 the preceding args and about the function being called.
1846 NAMED is nonzero if this argument is a named parameter
1847 (otherwise it is an extra parameter matching an ellipsis).
1848
1849 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1850 other arguments are passed on the stack. If (NAMED == 0) (which happens
1851 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1852 defined), say it is passed in the stack (function_prologue will
1853 indeed make it pass in the stack if necessary). */
1854 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1855 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1856
1857 /* For an arg passed partly in registers and partly in memory,
1858 this is the number of registers used.
1859 For args passed entirely in registers or entirely in memory, zero. */
1860 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1861 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1862 NUM_ARG_REGS > (CUM).nregs \
1863 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1864 ? NUM_ARG_REGS - (CUM).nregs : 0)
1865
1866 /* A C expression that indicates when an argument must be passed by
1867 reference. If nonzero for an argument, a copy of that argument is
1868 made in memory and a pointer to the argument is passed instead of
1869 the argument itself. The pointer is passed in whatever way is
1870 appropriate for passing a pointer to that type. */
1871 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1872 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1873
1874 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1875 for a call to a function whose data type is FNTYPE.
1876 For a library call, FNTYPE is 0.
1877 On the ARM, the offset starts at 0. */
1878 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1879 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1880
1881 /* Update the data in CUM to advance over an argument
1882 of mode MODE and data type TYPE.
1883 (TYPE is null for libcalls where that information may not be available.) */
1884 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1885 (CUM).nargs += 1; \
1886 if (VECTOR_MODE_SUPPORTED_P (MODE)) \
1887 if ((CUM).named_count <= (CUM).nargs) \
1888 (CUM).nregs += 2; \
1889 else \
1890 (CUM).iwmmxt_nregs += 1; \
1891 else \
1892 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1893
1894 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1895 argument with the specified mode and type. If it is not defined,
1896 `PARM_BOUNDARY' is used for all arguments. */
1897 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1898 (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \
1899 ? IWMMXT_ALIGNMENT : PARM_BOUNDARY)
1900
1901 /* 1 if N is a possible register number for function argument passing.
1902 On the ARM, r0-r3 are used to pass args. */
1903 #define FUNCTION_ARG_REGNO_P(REGNO) \
1904 (IN_RANGE ((REGNO), 0, 3) \
1905 || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1906
1907 /* Implement `va_arg'. */
1908 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1909 arm_va_arg (valist, type)
1910
1911 \f
1912 /* If your target environment doesn't prefix user functions with an
1913 underscore, you may wish to re-define this to prevent any conflicts.
1914 e.g. AOF may prefix mcount with an underscore. */
1915 #ifndef ARM_MCOUNT_NAME
1916 #define ARM_MCOUNT_NAME "*mcount"
1917 #endif
1918
1919 /* Call the function profiler with a given profile label. The Acorn
1920 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1921 On the ARM the full profile code will look like:
1922 .data
1923 LP1
1924 .word 0
1925 .text
1926 mov ip, lr
1927 bl mcount
1928 .word LP1
1929
1930 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1931 will output the .text section.
1932
1933 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1934 ``prof'' doesn't seem to mind about this!
1935
1936 Note - this version of the code is designed to work in both ARM and
1937 Thumb modes. */
1938 #ifndef ARM_FUNCTION_PROFILER
1939 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1940 { \
1941 char temp[20]; \
1942 rtx sym; \
1943 \
1944 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1945 IP_REGNUM, LR_REGNUM); \
1946 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1947 fputc ('\n', STREAM); \
1948 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1949 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1950 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1951 }
1952 #endif
1953
1954 #ifdef THUMB_FUNCTION_PROFILER
1955 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1956 if (TARGET_ARM) \
1957 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1958 else \
1959 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1960 #else
1961 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1962 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1963 #endif
1964
1965 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1966 the stack pointer does not matter. The value is tested only in
1967 functions that have frame pointers.
1968 No definition is equivalent to always zero.
1969
1970 On the ARM, the function epilogue recovers the stack pointer from the
1971 frame. */
1972 #define EXIT_IGNORE_STACK 1
1973
1974 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1975
1976 /* Determine if the epilogue should be output as RTL.
1977 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1978 #define USE_RETURN_INSN(ISCOND) \
1979 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1980
1981 /* Definitions for register eliminations.
1982
1983 This is an array of structures. Each structure initializes one pair
1984 of eliminable registers. The "from" register number is given first,
1985 followed by "to". Eliminations of the same "from" register are listed
1986 in order of preference.
1987
1988 We have two registers that can be eliminated on the ARM. First, the
1989 arg pointer register can often be eliminated in favor of the stack
1990 pointer register. Secondly, the pseudo frame pointer register can always
1991 be eliminated; it is replaced with either the stack or the real frame
1992 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1993 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1994
1995 #define ELIMINABLE_REGS \
1996 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1997 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1998 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1999 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
2000 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
2001 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
2002 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
2003
2004 /* Given FROM and TO register numbers, say whether this elimination is
2005 allowed. Frame pointer elimination is automatically handled.
2006
2007 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
2008 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
2009 pointer, we must eliminate FRAME_POINTER_REGNUM into
2010 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
2011 ARG_POINTER_REGNUM. */
2012 #define CAN_ELIMINATE(FROM, TO) \
2013 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
2014 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
2015 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
2016 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
2017 1)
2018
2019 #define THUMB_REG_PUSHED_P(reg) \
2020 (regs_ever_live [reg] \
2021 && (! call_used_regs [reg] \
2022 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
2023 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
2024
2025 /* Define the offset between two registers, one to be eliminated, and the
2026 other its replacement, at the start of a routine. */
2027 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2028 do \
2029 { \
2030 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
2031 } \
2032 while (0)
2033
2034 /* Note: This macro must match the code in thumb_function_prologue(). */
2035 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2036 { \
2037 (OFFSET) = 0; \
2038 if ((FROM) == ARG_POINTER_REGNUM) \
2039 { \
2040 int count_regs = 0; \
2041 int regno; \
2042 for (regno = 8; regno < 13; regno ++) \
2043 if (THUMB_REG_PUSHED_P (regno)) \
2044 count_regs ++; \
2045 if (count_regs) \
2046 (OFFSET) += 4 * count_regs; \
2047 count_regs = 0; \
2048 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
2049 if (THUMB_REG_PUSHED_P (regno)) \
2050 count_regs ++; \
2051 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
2052 (OFFSET) += 4 * (count_regs + 1); \
2053 if (TARGET_BACKTRACE) \
2054 { \
2055 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
2056 (OFFSET) += 20; \
2057 else \
2058 (OFFSET) += 16; \
2059 } \
2060 } \
2061 if ((TO) == STACK_POINTER_REGNUM) \
2062 { \
2063 (OFFSET) += current_function_outgoing_args_size; \
2064 (OFFSET) += thumb_get_frame_size (); \
2065 } \
2066 }
2067
2068 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2069 if (TARGET_ARM) \
2070 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
2071 else \
2072 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
2073
2074 /* Special case handling of the location of arguments passed on the stack. */
2075 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
2076
2077 /* Initialize data used by insn expanders. This is called from insn_emit,
2078 once for every function before code is generated. */
2079 #define INIT_EXPANDERS arm_init_expanders ()
2080
2081 /* Output assembler code for a block containing the constant parts
2082 of a trampoline, leaving space for the variable parts.
2083
2084 On the ARM, (if r8 is the static chain regnum, and remembering that
2085 referencing pc adds an offset of 8) the trampoline looks like:
2086 ldr r8, [pc, #0]
2087 ldr pc, [pc]
2088 .word static chain value
2089 .word function's address
2090 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
2091 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
2092 { \
2093 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
2094 STATIC_CHAIN_REGNUM, PC_REGNUM); \
2095 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
2096 PC_REGNUM, PC_REGNUM); \
2097 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
2098 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
2099 }
2100
2101 /* On the Thumb we always switch into ARM mode to execute the trampoline.
2102 Why - because it is easier. This code will always be branched to via
2103 a BX instruction and since the compiler magically generates the address
2104 of the function the linker has no opportunity to ensure that the
2105 bottom bit is set. Thus the processor will be in ARM mode when it
2106 reaches this code. So we duplicate the ARM trampoline code and add
2107 a switch into Thumb mode as well. */
2108 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
2109 { \
2110 fprintf (FILE, "\t.code 32\n"); \
2111 fprintf (FILE, ".Ltrampoline_start:\n"); \
2112 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2113 STATIC_CHAIN_REGNUM, PC_REGNUM); \
2114 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2115 IP_REGNUM, PC_REGNUM); \
2116 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
2117 IP_REGNUM, IP_REGNUM); \
2118 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
2119 fprintf (FILE, "\t.word\t0\n"); \
2120 fprintf (FILE, "\t.word\t0\n"); \
2121 fprintf (FILE, "\t.code 16\n"); \
2122 }
2123
2124 #define TRAMPOLINE_TEMPLATE(FILE) \
2125 if (TARGET_ARM) \
2126 ARM_TRAMPOLINE_TEMPLATE (FILE) \
2127 else \
2128 THUMB_TRAMPOLINE_TEMPLATE (FILE)
2129
2130 /* Length in units of the trampoline for entering a nested function. */
2131 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
2132
2133 /* Alignment required for a trampoline in bits. */
2134 #define TRAMPOLINE_ALIGNMENT 32
2135
2136 /* Emit RTL insns to initialize the variable parts of a trampoline.
2137 FNADDR is an RTX for the address of the function's pure code.
2138 CXT is an RTX for the static chain value for the function. */
2139 #ifndef INITIALIZE_TRAMPOLINE
2140 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2141 { \
2142 emit_move_insn (gen_rtx_MEM (SImode, \
2143 plus_constant (TRAMP, \
2144 TARGET_ARM ? 8 : 16)), \
2145 CXT); \
2146 emit_move_insn (gen_rtx_MEM (SImode, \
2147 plus_constant (TRAMP, \
2148 TARGET_ARM ? 12 : 20)), \
2149 FNADDR); \
2150 }
2151 #endif
2152
2153 \f
2154 /* Addressing modes, and classification of registers for them. */
2155 #define HAVE_POST_INCREMENT 1
2156 #define HAVE_PRE_INCREMENT TARGET_ARM
2157 #define HAVE_POST_DECREMENT TARGET_ARM
2158 #define HAVE_PRE_DECREMENT TARGET_ARM
2159 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2160 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2161 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2162 #define HAVE_POST_MODIFY_REG TARGET_ARM
2163
2164 /* Macros to check register numbers against specific register classes. */
2165
2166 /* These assume that REGNO is a hard or pseudo reg number.
2167 They give nonzero only if REGNO is a hard reg of the suitable class
2168 or a pseudo reg currently allocated to a suitable hard reg.
2169 Since they use reg_renumber, they are safe only once reg_renumber
2170 has been allocated, which happens in local-alloc.c. */
2171 #define TEST_REGNO(R, TEST, VALUE) \
2172 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2173
2174 /* On the ARM, don't allow the pc to be used. */
2175 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2176 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2177 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2178 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2179
2180 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2181 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2182 || (GET_MODE_SIZE (MODE) >= 4 \
2183 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2184
2185 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2186 (TARGET_THUMB \
2187 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2188 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2189
2190 /* For ARM code, we don't care about the mode, but for Thumb, the index
2191 must be suitable for use in a QImode load. */
2192 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2193 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2194
2195 /* Maximum number of registers that can appear in a valid memory address.
2196 Shifts in addresses can't be by a register. */
2197 #define MAX_REGS_PER_ADDRESS 2
2198
2199 /* Recognize any constant value that is a valid address. */
2200 /* XXX We can address any constant, eventually... */
2201
2202 #ifdef AOF_ASSEMBLER
2203
2204 #define CONSTANT_ADDRESS_P(X) \
2205 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2206
2207 #else
2208
2209 #define CONSTANT_ADDRESS_P(X) \
2210 (GET_CODE (X) == SYMBOL_REF \
2211 && (CONSTANT_POOL_ADDRESS_P (X) \
2212 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2213
2214 #endif /* AOF_ASSEMBLER */
2215
2216 /* Nonzero if the constant value X is a legitimate general operand.
2217 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2218
2219 On the ARM, allow any integer (invalid ones are removed later by insn
2220 patterns), nice doubles and symbol_refs which refer to the function's
2221 constant pool XXX.
2222
2223 When generating pic allow anything. */
2224 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2225
2226 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2227 ( GET_CODE (X) == CONST_INT \
2228 || GET_CODE (X) == CONST_DOUBLE \
2229 || GET_CODE (X) == CONSTANT_P_RTX \
2230 || CONSTANT_ADDRESS_P (X) \
2231 || flag_pic)
2232
2233 #define LEGITIMATE_CONSTANT_P(X) \
2234 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2235
2236 /* Special characters prefixed to function names
2237 in order to encode attribute like information.
2238 Note, '@' and '*' have already been taken. */
2239 #define SHORT_CALL_FLAG_CHAR '^'
2240 #define LONG_CALL_FLAG_CHAR '#'
2241
2242 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2243 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2244
2245 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2246 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2247
2248 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2249 #define SUBTARGET_NAME_ENCODING_LENGTHS
2250 #endif
2251
2252 /* This is a C fragment for the inside of a switch statement.
2253 Each case label should return the number of characters to
2254 be stripped from the start of a function's name, if that
2255 name starts with the indicated character. */
2256 #define ARM_NAME_ENCODING_LENGTHS \
2257 case SHORT_CALL_FLAG_CHAR: return 1; \
2258 case LONG_CALL_FLAG_CHAR: return 1; \
2259 case '*': return 1; \
2260 SUBTARGET_NAME_ENCODING_LENGTHS
2261
2262 /* This is how to output a reference to a user-level label named NAME.
2263 `assemble_name' uses this. */
2264 #undef ASM_OUTPUT_LABELREF
2265 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2266 arm_asm_output_labelref (FILE, NAME)
2267
2268 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2269 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2270
2271 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2272 and check its validity for a certain class.
2273 We have two alternate definitions for each of them.
2274 The usual definition accepts all pseudo regs; the other rejects
2275 them unless they have been allocated suitable hard regs.
2276 The symbol REG_OK_STRICT causes the latter definition to be used. */
2277 #ifndef REG_OK_STRICT
2278
2279 #define ARM_REG_OK_FOR_BASE_P(X) \
2280 (REGNO (X) <= LAST_ARM_REGNUM \
2281 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2282 || REGNO (X) == FRAME_POINTER_REGNUM \
2283 || REGNO (X) == ARG_POINTER_REGNUM)
2284
2285 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2286 (REGNO (X) <= LAST_LO_REGNUM \
2287 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2288 || (GET_MODE_SIZE (MODE) >= 4 \
2289 && (REGNO (X) == STACK_POINTER_REGNUM \
2290 || (X) == hard_frame_pointer_rtx \
2291 || (X) == arg_pointer_rtx)))
2292
2293 #define REG_STRICT_P 0
2294
2295 #else /* REG_OK_STRICT */
2296
2297 #define ARM_REG_OK_FOR_BASE_P(X) \
2298 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2299
2300 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2301 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2302
2303 #define REG_STRICT_P 1
2304
2305 #endif /* REG_OK_STRICT */
2306
2307 /* Now define some helpers in terms of the above. */
2308
2309 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2310 (TARGET_THUMB \
2311 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2312 : ARM_REG_OK_FOR_BASE_P (X))
2313
2314 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2315
2316 /* For Thumb, a valid index register is anything that can be used in
2317 a byte load instruction. */
2318 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2319
2320 /* Nonzero if X is a hard reg that can be used as an index
2321 or if it is a pseudo reg. On the Thumb, the stack pointer
2322 is not suitable. */
2323 #define REG_OK_FOR_INDEX_P(X) \
2324 (TARGET_THUMB \
2325 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2326 : ARM_REG_OK_FOR_INDEX_P (X))
2327
2328 \f
2329 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2330 that is a valid memory address for an instruction.
2331 The MODE argument is the machine mode for the MEM expression
2332 that wants to use this address. */
2333
2334 #define ARM_BASE_REGISTER_RTX_P(X) \
2335 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2336
2337 #define ARM_INDEX_REGISTER_RTX_P(X) \
2338 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2339
2340 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2341 { \
2342 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2343 goto WIN; \
2344 }
2345
2346 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2347 { \
2348 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2349 goto WIN; \
2350 }
2351
2352 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2353 if (TARGET_ARM) \
2354 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2355 else /* if (TARGET_THUMB) */ \
2356 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2357
2358 \f
2359 /* Try machine-dependent ways of modifying an illegitimate address
2360 to be legitimate. If we find one, return the new, valid address. */
2361 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2362 do { \
2363 X = arm_legitimize_address (X, OLDX, MODE); \
2364 \
2365 if (memory_address_p (MODE, X)) \
2366 goto WIN; \
2367 } while (0)
2368
2369 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2370 do { \
2371 if (flag_pic) \
2372 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2373 } while (0)
2374
2375 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2376 do { \
2377 if (TARGET_ARM) \
2378 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2379 else \
2380 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2381 } while (0)
2382
2383 /* Go to LABEL if ADDR (a legitimate address expression)
2384 has an effect that depends on the machine mode it is used for. */
2385 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2386 { \
2387 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2388 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2389 goto LABEL; \
2390 }
2391
2392 /* Nothing helpful to do for the Thumb */
2393 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2394 if (TARGET_ARM) \
2395 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2396 \f
2397
2398 /* Specify the machine mode that this machine uses
2399 for the index in the tablejump instruction. */
2400 #define CASE_VECTOR_MODE Pmode
2401
2402 /* Define as C expression which evaluates to nonzero if the tablejump
2403 instruction expects the table to contain offsets from the address of the
2404 table.
2405 Do not define this if the table should contain absolute addresses. */
2406 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2407
2408 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2409 unsigned is probably best, but may break some code. */
2410 #ifndef DEFAULT_SIGNED_CHAR
2411 #define DEFAULT_SIGNED_CHAR 0
2412 #endif
2413
2414 /* Don't cse the address of the function being compiled. */
2415 #define NO_RECURSIVE_FUNCTION_CSE 1
2416
2417 /* Max number of bytes we can move from memory to memory
2418 in one reasonably fast instruction. */
2419 #define MOVE_MAX 4
2420
2421 #undef MOVE_RATIO
2422 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2423
2424 /* Define if operations between registers always perform the operation
2425 on the full register even if a narrower mode is specified. */
2426 #define WORD_REGISTER_OPERATIONS
2427
2428 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2429 will either zero-extend or sign-extend. The value of this macro should
2430 be the code that says which one of the two operations is implicitly
2431 done, NIL if none. */
2432 #define LOAD_EXTEND_OP(MODE) \
2433 (TARGET_THUMB ? ZERO_EXTEND : \
2434 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2435 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2436
2437 /* Nonzero if access to memory by bytes is slow and undesirable. */
2438 #define SLOW_BYTE_ACCESS 0
2439
2440 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2441
2442 /* Immediate shift counts are truncated by the output routines (or was it
2443 the assembler?). Shift counts in a register are truncated by ARM. Note
2444 that the native compiler puts too large (> 32) immediate shift counts
2445 into a register and shifts by the register, letting the ARM decide what
2446 to do instead of doing that itself. */
2447 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2448 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2449 On the arm, Y in a register is used modulo 256 for the shift. Only for
2450 rotates is modulo 32 used. */
2451 /* #define SHIFT_COUNT_TRUNCATED 1 */
2452
2453 /* All integers have the same format so truncation is easy. */
2454 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2455
2456 /* Calling from registers is a massive pain. */
2457 #define NO_FUNCTION_CSE 1
2458
2459 /* The machine modes of pointers and functions */
2460 #define Pmode SImode
2461 #define FUNCTION_MODE Pmode
2462
2463 #define ARM_FRAME_RTX(X) \
2464 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2465 || (X) == arg_pointer_rtx)
2466
2467 /* Moves to and from memory are quite expensive */
2468 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2469 (TARGET_ARM ? 10 : \
2470 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2471 * (CLASS == LO_REGS ? 1 : 2)))
2472
2473 /* Try to generate sequences that don't involve branches, we can then use
2474 conditional instructions */
2475 #define BRANCH_COST \
2476 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2477 \f
2478 /* Position Independent Code. */
2479 /* We decide which register to use based on the compilation options and
2480 the assembler in use; this is more general than the APCS restriction of
2481 using sb (r9) all the time. */
2482 extern int arm_pic_register;
2483
2484 /* Used when parsing command line option -mpic-register=. */
2485 extern const char * arm_pic_register_string;
2486
2487 /* The register number of the register used to address a table of static
2488 data addresses in memory. */
2489 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2490
2491 #define FINALIZE_PIC arm_finalize_pic (1)
2492
2493 /* We can't directly access anything that contains a symbol,
2494 nor can we indirect via the constant pool. */
2495 #define LEGITIMATE_PIC_OPERAND_P(X) \
2496 (!(symbol_mentioned_p (X) \
2497 || label_mentioned_p (X) \
2498 || (GET_CODE (X) == SYMBOL_REF \
2499 && CONSTANT_POOL_ADDRESS_P (X) \
2500 && (symbol_mentioned_p (get_pool_constant (X)) \
2501 || label_mentioned_p (get_pool_constant (X))))))
2502
2503 /* We need to know when we are making a constant pool; this determines
2504 whether data needs to be in the GOT or can be referenced via a GOT
2505 offset. */
2506 extern int making_const_table;
2507 \f
2508 /* Handle pragmas for compatibility with Intel's compilers. */
2509 #define REGISTER_TARGET_PRAGMAS() do { \
2510 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2511 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2512 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2513 } while (0)
2514
2515 /* Condition code information. */
2516 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2517 return the mode to be used for the comparison. */
2518
2519 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2520
2521 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2522
2523 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2524 do \
2525 { \
2526 if (GET_CODE (OP1) == CONST_INT \
2527 && ! (const_ok_for_arm (INTVAL (OP1)) \
2528 || (const_ok_for_arm (- INTVAL (OP1))))) \
2529 { \
2530 rtx const_op = OP1; \
2531 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2532 OP1 = const_op; \
2533 } \
2534 } \
2535 while (0)
2536
2537 /* The arm5 clz instruction returns 32. */
2538 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2539 \f
2540 #undef ASM_APP_OFF
2541 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2542
2543 /* Output a push or a pop instruction (only used when profiling). */
2544 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2545 do \
2546 { \
2547 if (TARGET_ARM) \
2548 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2549 STACK_POINTER_REGNUM, REGNO); \
2550 else \
2551 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2552 } while (0)
2553
2554
2555 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2556 do \
2557 { \
2558 if (TARGET_ARM) \
2559 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2560 STACK_POINTER_REGNUM, REGNO); \
2561 else \
2562 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2563 } while (0)
2564
2565 /* This is how to output a label which precedes a jumptable. Since
2566 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2567 #undef ASM_OUTPUT_CASE_LABEL
2568 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2569 do \
2570 { \
2571 if (TARGET_THUMB) \
2572 ASM_OUTPUT_ALIGN (FILE, 2); \
2573 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2574 } \
2575 while (0)
2576
2577 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2578 do \
2579 { \
2580 if (TARGET_THUMB) \
2581 { \
2582 if (is_called_in_ARM_mode (DECL) \
2583 || current_function_is_thunk) \
2584 fprintf (STREAM, "\t.code 32\n") ; \
2585 else \
2586 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2587 } \
2588 if (TARGET_POKE_FUNCTION_NAME) \
2589 arm_poke_function_name (STREAM, (char *) NAME); \
2590 } \
2591 while (0)
2592
2593 /* For aliases of functions we use .thumb_set instead. */
2594 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2595 do \
2596 { \
2597 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2598 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2599 \
2600 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2601 { \
2602 fprintf (FILE, "\t.thumb_set "); \
2603 assemble_name (FILE, LABEL1); \
2604 fprintf (FILE, ","); \
2605 assemble_name (FILE, LABEL2); \
2606 fprintf (FILE, "\n"); \
2607 } \
2608 else \
2609 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2610 } \
2611 while (0)
2612
2613 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2614 /* To support -falign-* switches we need to use .p2align so
2615 that alignment directives in code sections will be padded
2616 with no-op instructions, rather than zeroes. */
2617 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2618 if ((LOG) != 0) \
2619 { \
2620 if ((MAX_SKIP) == 0) \
2621 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2622 else \
2623 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2624 (int) (LOG), (int) (MAX_SKIP)); \
2625 }
2626 #endif
2627 \f
2628 /* Only perform branch elimination (by making instructions conditional) if
2629 we're optimizing. Otherwise it's of no use anyway. */
2630 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2631 if (TARGET_ARM && optimize) \
2632 arm_final_prescan_insn (INSN); \
2633 else if (TARGET_THUMB) \
2634 thumb_final_prescan_insn (INSN)
2635
2636 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2637 (CODE == '@' || CODE == '|' \
2638 || (TARGET_ARM && (CODE == '?')) \
2639 || (TARGET_THUMB && (CODE == '_')))
2640
2641 /* Output an operand of an instruction. */
2642 #define PRINT_OPERAND(STREAM, X, CODE) \
2643 arm_print_operand (STREAM, X, CODE)
2644
2645 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2646 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2647 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2648 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2649 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2650 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2651 : 0))))
2652
2653 /* Output the address of an operand. */
2654 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2655 { \
2656 int is_minus = GET_CODE (X) == MINUS; \
2657 \
2658 if (GET_CODE (X) == REG) \
2659 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2660 else if (GET_CODE (X) == PLUS || is_minus) \
2661 { \
2662 rtx base = XEXP (X, 0); \
2663 rtx index = XEXP (X, 1); \
2664 HOST_WIDE_INT offset = 0; \
2665 if (GET_CODE (base) != REG) \
2666 { \
2667 /* Ensure that BASE is a register. */ \
2668 /* (one of them must be). */ \
2669 rtx temp = base; \
2670 base = index; \
2671 index = temp; \
2672 } \
2673 switch (GET_CODE (index)) \
2674 { \
2675 case CONST_INT: \
2676 offset = INTVAL (index); \
2677 if (is_minus) \
2678 offset = -offset; \
2679 asm_fprintf (STREAM, "[%r, #%wd]", \
2680 REGNO (base), offset); \
2681 break; \
2682 \
2683 case REG: \
2684 asm_fprintf (STREAM, "[%r, %s%r]", \
2685 REGNO (base), is_minus ? "-" : "", \
2686 REGNO (index)); \
2687 break; \
2688 \
2689 case MULT: \
2690 case ASHIFTRT: \
2691 case LSHIFTRT: \
2692 case ASHIFT: \
2693 case ROTATERT: \
2694 { \
2695 asm_fprintf (STREAM, "[%r, %s%r", \
2696 REGNO (base), is_minus ? "-" : "", \
2697 REGNO (XEXP (index, 0))); \
2698 arm_print_operand (STREAM, index, 'S'); \
2699 fputs ("]", STREAM); \
2700 break; \
2701 } \
2702 \
2703 default: \
2704 abort(); \
2705 } \
2706 } \
2707 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2708 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2709 { \
2710 extern enum machine_mode output_memory_reference_mode; \
2711 \
2712 if (GET_CODE (XEXP (X, 0)) != REG) \
2713 abort (); \
2714 \
2715 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2716 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2717 REGNO (XEXP (X, 0)), \
2718 GET_CODE (X) == PRE_DEC ? "-" : "", \
2719 GET_MODE_SIZE (output_memory_reference_mode)); \
2720 else \
2721 asm_fprintf (STREAM, "[%r], #%s%d", \
2722 REGNO (XEXP (X, 0)), \
2723 GET_CODE (X) == POST_DEC ? "-" : "", \
2724 GET_MODE_SIZE (output_memory_reference_mode)); \
2725 } \
2726 else if (GET_CODE (X) == PRE_MODIFY) \
2727 { \
2728 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2729 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2730 asm_fprintf (STREAM, "#%wd]!", \
2731 INTVAL (XEXP (XEXP (X, 1), 1))); \
2732 else \
2733 asm_fprintf (STREAM, "%r]!", \
2734 REGNO (XEXP (XEXP (X, 1), 1))); \
2735 } \
2736 else if (GET_CODE (X) == POST_MODIFY) \
2737 { \
2738 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2739 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2740 asm_fprintf (STREAM, "#%wd", \
2741 INTVAL (XEXP (XEXP (X, 1), 1))); \
2742 else \
2743 asm_fprintf (STREAM, "%r", \
2744 REGNO (XEXP (XEXP (X, 1), 1))); \
2745 } \
2746 else output_addr_const (STREAM, X); \
2747 }
2748
2749 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2750 { \
2751 if (GET_CODE (X) == REG) \
2752 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2753 else if (GET_CODE (X) == POST_INC) \
2754 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2755 else if (GET_CODE (X) == PLUS) \
2756 { \
2757 if (GET_CODE (XEXP (X, 0)) != REG) \
2758 abort (); \
2759 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2760 asm_fprintf (STREAM, "[%r, #%wd]", \
2761 REGNO (XEXP (X, 0)), \
2762 INTVAL (XEXP (X, 1))); \
2763 else \
2764 asm_fprintf (STREAM, "[%r, %r]", \
2765 REGNO (XEXP (X, 0)), \
2766 REGNO (XEXP (X, 1))); \
2767 } \
2768 else \
2769 output_addr_const (STREAM, X); \
2770 }
2771
2772 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2773 if (TARGET_ARM) \
2774 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2775 else \
2776 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2777
2778 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2779 if (GET_CODE (X) != CONST_VECTOR \
2780 || ! arm_emit_vector_const (FILE, X)) \
2781 goto FAIL;
2782
2783 /* A C expression whose value is RTL representing the value of the return
2784 address for the frame COUNT steps up from the current frame. */
2785
2786 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2787 arm_return_addr (COUNT, FRAME)
2788
2789 /* Mask of the bits in the PC that contain the real return address
2790 when running in 26-bit mode. */
2791 #define RETURN_ADDR_MASK26 (0x03fffffc)
2792
2793 /* Pick up the return address upon entry to a procedure. Used for
2794 dwarf2 unwind information. This also enables the table driven
2795 mechanism. */
2796 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2797 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2798
2799 /* Used to mask out junk bits from the return address, such as
2800 processor state, interrupt status, condition codes and the like. */
2801 #define MASK_RETURN_ADDR \
2802 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2803 in 26 bit mode, the condition codes must be masked out of the \
2804 return address. This does not apply to ARM6 and later processors \
2805 when running in 32 bit mode. */ \
2806 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2807 : (arm_arch4 || TARGET_THUMB) ? \
2808 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2809 : arm_gen_return_addr_mask ())
2810
2811 \f
2812 /* Define the codes that are matched by predicates in arm.c */
2813 #define PREDICATE_CODES \
2814 {"s_register_operand", {SUBREG, REG}}, \
2815 {"arm_general_register_operand", {SUBREG, REG}}, \
2816 {"arm_hard_register_operand", {REG}}, \
2817 {"f_register_operand", {SUBREG, REG}}, \
2818 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2819 {"arm_addimm_operand", {CONST_INT}}, \
2820 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2821 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2822 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2823 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2824 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2825 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2826 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2827 {"thumb_cmpneg_operand", {CONST_INT}}, \
2828 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2829 {"offsettable_memory_operand", {MEM}}, \
2830 {"bad_signed_byte_operand", {MEM}}, \
2831 {"alignable_memory_operand", {MEM}}, \
2832 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2833 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2834 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2835 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2836 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2837 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2838 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2839 {"load_multiple_operation", {PARALLEL}}, \
2840 {"store_multiple_operation", {PARALLEL}}, \
2841 {"equality_operator", {EQ, NE}}, \
2842 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2843 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2844 UNGE, UNGT}}, \
2845 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2846 {"const_shift_operand", {CONST_INT}}, \
2847 {"multi_register_push", {PARALLEL}}, \
2848 {"cc_register", {REG}}, \
2849 {"logical_binary_operator", {AND, IOR, XOR}}, \
2850 {"cirrus_register_operand", {REG}}, \
2851 {"cirrus_fp_register", {REG}}, \
2852 {"cirrus_shift_const", {CONST_INT}}, \
2853 {"dominant_cc_register", {REG}}, \
2854 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2855 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2856
2857 /* Define this if you have special predicates that know special things
2858 about modes. Genrecog will warn about certain forms of
2859 match_operand without a mode; if the operand predicate is listed in
2860 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2861 #define SPECIAL_MODE_PREDICATES \
2862 "cc_register", "dominant_cc_register",
2863
2864 enum arm_builtins
2865 {
2866 ARM_BUILTIN_GETWCX,
2867 ARM_BUILTIN_SETWCX,
2868
2869 ARM_BUILTIN_WZERO,
2870
2871 ARM_BUILTIN_WAVG2BR,
2872 ARM_BUILTIN_WAVG2HR,
2873 ARM_BUILTIN_WAVG2B,
2874 ARM_BUILTIN_WAVG2H,
2875
2876 ARM_BUILTIN_WACCB,
2877 ARM_BUILTIN_WACCH,
2878 ARM_BUILTIN_WACCW,
2879
2880 ARM_BUILTIN_WMACS,
2881 ARM_BUILTIN_WMACSZ,
2882 ARM_BUILTIN_WMACU,
2883 ARM_BUILTIN_WMACUZ,
2884
2885 ARM_BUILTIN_WSADB,
2886 ARM_BUILTIN_WSADBZ,
2887 ARM_BUILTIN_WSADH,
2888 ARM_BUILTIN_WSADHZ,
2889
2890 ARM_BUILTIN_WALIGN,
2891
2892 ARM_BUILTIN_TMIA,
2893 ARM_BUILTIN_TMIAPH,
2894 ARM_BUILTIN_TMIABB,
2895 ARM_BUILTIN_TMIABT,
2896 ARM_BUILTIN_TMIATB,
2897 ARM_BUILTIN_TMIATT,
2898
2899 ARM_BUILTIN_TMOVMSKB,
2900 ARM_BUILTIN_TMOVMSKH,
2901 ARM_BUILTIN_TMOVMSKW,
2902
2903 ARM_BUILTIN_TBCSTB,
2904 ARM_BUILTIN_TBCSTH,
2905 ARM_BUILTIN_TBCSTW,
2906
2907 ARM_BUILTIN_WMADDS,
2908 ARM_BUILTIN_WMADDU,
2909
2910 ARM_BUILTIN_WPACKHSS,
2911 ARM_BUILTIN_WPACKWSS,
2912 ARM_BUILTIN_WPACKDSS,
2913 ARM_BUILTIN_WPACKHUS,
2914 ARM_BUILTIN_WPACKWUS,
2915 ARM_BUILTIN_WPACKDUS,
2916
2917 ARM_BUILTIN_WADDB,
2918 ARM_BUILTIN_WADDH,
2919 ARM_BUILTIN_WADDW,
2920 ARM_BUILTIN_WADDSSB,
2921 ARM_BUILTIN_WADDSSH,
2922 ARM_BUILTIN_WADDSSW,
2923 ARM_BUILTIN_WADDUSB,
2924 ARM_BUILTIN_WADDUSH,
2925 ARM_BUILTIN_WADDUSW,
2926 ARM_BUILTIN_WSUBB,
2927 ARM_BUILTIN_WSUBH,
2928 ARM_BUILTIN_WSUBW,
2929 ARM_BUILTIN_WSUBSSB,
2930 ARM_BUILTIN_WSUBSSH,
2931 ARM_BUILTIN_WSUBSSW,
2932 ARM_BUILTIN_WSUBUSB,
2933 ARM_BUILTIN_WSUBUSH,
2934 ARM_BUILTIN_WSUBUSW,
2935
2936 ARM_BUILTIN_WAND,
2937 ARM_BUILTIN_WANDN,
2938 ARM_BUILTIN_WOR,
2939 ARM_BUILTIN_WXOR,
2940
2941 ARM_BUILTIN_WCMPEQB,
2942 ARM_BUILTIN_WCMPEQH,
2943 ARM_BUILTIN_WCMPEQW,
2944 ARM_BUILTIN_WCMPGTUB,
2945 ARM_BUILTIN_WCMPGTUH,
2946 ARM_BUILTIN_WCMPGTUW,
2947 ARM_BUILTIN_WCMPGTSB,
2948 ARM_BUILTIN_WCMPGTSH,
2949 ARM_BUILTIN_WCMPGTSW,
2950
2951 ARM_BUILTIN_TEXTRMSB,
2952 ARM_BUILTIN_TEXTRMSH,
2953 ARM_BUILTIN_TEXTRMSW,
2954 ARM_BUILTIN_TEXTRMUB,
2955 ARM_BUILTIN_TEXTRMUH,
2956 ARM_BUILTIN_TEXTRMUW,
2957 ARM_BUILTIN_TINSRB,
2958 ARM_BUILTIN_TINSRH,
2959 ARM_BUILTIN_TINSRW,
2960
2961 ARM_BUILTIN_WMAXSW,
2962 ARM_BUILTIN_WMAXSH,
2963 ARM_BUILTIN_WMAXSB,
2964 ARM_BUILTIN_WMAXUW,
2965 ARM_BUILTIN_WMAXUH,
2966 ARM_BUILTIN_WMAXUB,
2967 ARM_BUILTIN_WMINSW,
2968 ARM_BUILTIN_WMINSH,
2969 ARM_BUILTIN_WMINSB,
2970 ARM_BUILTIN_WMINUW,
2971 ARM_BUILTIN_WMINUH,
2972 ARM_BUILTIN_WMINUB,
2973
2974 ARM_BUILTIN_WMULUH,
2975 ARM_BUILTIN_WMULSH,
2976 ARM_BUILTIN_WMULUL,
2977
2978 ARM_BUILTIN_PSADBH,
2979 ARM_BUILTIN_WSHUFH,
2980
2981 ARM_BUILTIN_WSLLH,
2982 ARM_BUILTIN_WSLLW,
2983 ARM_BUILTIN_WSLLD,
2984 ARM_BUILTIN_WSRAH,
2985 ARM_BUILTIN_WSRAW,
2986 ARM_BUILTIN_WSRAD,
2987 ARM_BUILTIN_WSRLH,
2988 ARM_BUILTIN_WSRLW,
2989 ARM_BUILTIN_WSRLD,
2990 ARM_BUILTIN_WRORH,
2991 ARM_BUILTIN_WRORW,
2992 ARM_BUILTIN_WRORD,
2993 ARM_BUILTIN_WSLLHI,
2994 ARM_BUILTIN_WSLLWI,
2995 ARM_BUILTIN_WSLLDI,
2996 ARM_BUILTIN_WSRAHI,
2997 ARM_BUILTIN_WSRAWI,
2998 ARM_BUILTIN_WSRADI,
2999 ARM_BUILTIN_WSRLHI,
3000 ARM_BUILTIN_WSRLWI,
3001 ARM_BUILTIN_WSRLDI,
3002 ARM_BUILTIN_WRORHI,
3003 ARM_BUILTIN_WRORWI,
3004 ARM_BUILTIN_WRORDI,
3005
3006 ARM_BUILTIN_WUNPCKIHB,
3007 ARM_BUILTIN_WUNPCKIHH,
3008 ARM_BUILTIN_WUNPCKIHW,
3009 ARM_BUILTIN_WUNPCKILB,
3010 ARM_BUILTIN_WUNPCKILH,
3011 ARM_BUILTIN_WUNPCKILW,
3012
3013 ARM_BUILTIN_WUNPCKEHSB,
3014 ARM_BUILTIN_WUNPCKEHSH,
3015 ARM_BUILTIN_WUNPCKEHSW,
3016 ARM_BUILTIN_WUNPCKEHUB,
3017 ARM_BUILTIN_WUNPCKEHUH,
3018 ARM_BUILTIN_WUNPCKEHUW,
3019 ARM_BUILTIN_WUNPCKELSB,
3020 ARM_BUILTIN_WUNPCKELSH,
3021 ARM_BUILTIN_WUNPCKELSW,
3022 ARM_BUILTIN_WUNPCKELUB,
3023 ARM_BUILTIN_WUNPCKELUH,
3024 ARM_BUILTIN_WUNPCKELUW,
3025
3026 ARM_BUILTIN_MAX
3027 };
3028 #endif /* ! GCC_ARM_H */
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