1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx
, int);
152 static void arm_encode_section_info (tree
, rtx
, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx
arm_struct_value_rtx (tree
, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
168 enum machine_mode
, tree
, bool);
169 static bool arm_promote_prototypes (tree
);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree
);
173 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx
);
176 static bool arm_output_ttype (rtx
);
179 static tree
arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree
arm_get_cookie_size (tree
);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree
);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
192 /* Initialize the GCC target structure. */
193 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
194 #undef TARGET_MERGE_DECL_ATTRIBUTES
195 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
198 #undef TARGET_ATTRIBUTE_TABLE
199 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
201 #undef TARGET_ASM_FILE_END
202 #define TARGET_ASM_FILE_END arm_file_end
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP "\tDCB\t"
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
211 #undef TARGET_ASM_GLOBALIZE_LABEL
212 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
213 #undef TARGET_ASM_FILE_START
214 #define TARGET_ASM_FILE_START aof_file_start
215 #undef TARGET_ASM_FILE_END
216 #define TARGET_ASM_FILE_END aof_file_end
218 #undef TARGET_ASM_ALIGNED_SI_OP
219 #define TARGET_ASM_ALIGNED_SI_OP NULL
220 #undef TARGET_ASM_INTEGER
221 #define TARGET_ASM_INTEGER arm_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
230 #undef TARGET_DEFAULT_TARGET_FLAGS
231 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
232 #undef TARGET_HANDLE_OPTION
233 #define TARGET_HANDLE_OPTION arm_handle_option
235 #undef TARGET_COMP_TYPE_ATTRIBUTES
236 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
238 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
239 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
244 #undef TARGET_ENCODE_SECTION_INFO
246 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
248 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
251 #undef TARGET_STRIP_NAME_ENCODING
252 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
254 #undef TARGET_ASM_INTERNAL_LABEL
255 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
257 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
258 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
260 #undef TARGET_ASM_OUTPUT_MI_THUNK
261 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
262 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
263 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
265 /* This will be overridden in arm_override_options. */
266 #undef TARGET_RTX_COSTS
267 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
268 #undef TARGET_ADDRESS_COST
269 #define TARGET_ADDRESS_COST arm_address_cost
271 #undef TARGET_SHIFT_TRUNCATION_MASK
272 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
273 #undef TARGET_VECTOR_MODE_SUPPORTED_P
274 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
276 #undef TARGET_MACHINE_DEPENDENT_REORG
277 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
279 #undef TARGET_INIT_BUILTINS
280 #define TARGET_INIT_BUILTINS arm_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
284 #undef TARGET_INIT_LIBFUNCS
285 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
287 #undef TARGET_PROMOTE_FUNCTION_ARGS
288 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
289 #undef TARGET_PROMOTE_FUNCTION_RETURN
290 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
291 #undef TARGET_PROMOTE_PROTOTYPES
292 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
293 #undef TARGET_PASS_BY_REFERENCE
294 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
295 #undef TARGET_ARG_PARTIAL_BYTES
296 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
298 #undef TARGET_STRUCT_VALUE_RTX
299 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
301 #undef TARGET_SETUP_INCOMING_VARARGS
302 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
304 #undef TARGET_DEFAULT_SHORT_ENUMS
305 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
307 #undef TARGET_ALIGN_ANON_BITFIELD
308 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
310 #undef TARGET_CXX_GUARD_TYPE
311 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
313 #undef TARGET_CXX_GUARD_MASK_BIT
314 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
316 #undef TARGET_CXX_GET_COOKIE_SIZE
317 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
319 #undef TARGET_CXX_COOKIE_HAS_SIZE
320 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
322 #undef TARGET_CXX_CDTOR_RETURNS_THIS
323 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
325 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
326 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
328 #undef TARGET_CXX_USE_AEABI_ATEXIT
329 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
331 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
332 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
333 arm_cxx_determine_class_data_visibility
335 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
336 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
338 #undef TARGET_RETURN_IN_MSB
339 #define TARGET_RETURN_IN_MSB arm_return_in_msb
341 #undef TARGET_MUST_PASS_IN_STACK
342 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
344 #ifdef TARGET_UNWIND_INFO
345 #undef TARGET_UNWIND_EMIT
346 #define TARGET_UNWIND_EMIT arm_unwind_emit
348 /* EABI unwinding tables use a different format for the typeinfo tables. */
349 #undef TARGET_ASM_TTYPE
350 #define TARGET_ASM_TTYPE arm_output_ttype
352 #undef TARGET_ARM_EABI_UNWINDER
353 #define TARGET_ARM_EABI_UNWINDER true
354 #endif /* TARGET_UNWIND_INFO */
356 struct gcc_target targetm
= TARGET_INITIALIZER
;
358 /* Obstack for minipool constant handling. */
359 static struct obstack minipool_obstack
;
360 static char * minipool_startobj
;
362 /* The maximum number of insns skipped which
363 will be conditionalised if possible. */
364 static int max_insns_skipped
= 5;
366 extern FILE * asm_out_file
;
368 /* True if we are currently building a constant table. */
369 int making_const_table
;
371 /* Define the information needed to generate branch insns. This is
372 stored from the compare operation. */
373 rtx arm_compare_op0
, arm_compare_op1
;
375 /* The processor for which instructions should be scheduled. */
376 enum processor_type arm_tune
= arm_none
;
378 /* Which floating point model to use. */
379 enum arm_fp_model arm_fp_model
;
381 /* Which floating point hardware is available. */
382 enum fputype arm_fpu_arch
;
384 /* Which floating point hardware to schedule for. */
385 enum fputype arm_fpu_tune
;
387 /* Whether to use floating point hardware. */
388 enum float_abi_type arm_float_abi
;
390 /* Which ABI to use. */
391 enum arm_abi_type arm_abi
;
393 /* Used to parse -mstructure_size_boundary command line option. */
394 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
396 /* Used for Thumb call_via trampolines. */
397 rtx thumb_call_via_label
[14];
398 static int thumb_call_reg_needed
;
400 /* Bit values used to identify processor capabilities. */
401 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
402 #define FL_ARCH3M (1 << 1) /* Extended multiply */
403 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
404 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
405 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
406 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
407 #define FL_THUMB (1 << 6) /* Thumb aware */
408 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
409 #define FL_STRONG (1 << 8) /* StrongARM */
410 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
411 #define FL_XSCALE (1 << 10) /* XScale */
412 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
413 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
414 media instructions. */
415 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
416 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
417 Note: ARM6 & 7 derivatives only. */
419 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
421 #define FL_FOR_ARCH2 0
422 #define FL_FOR_ARCH3 FL_MODE32
423 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
424 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
425 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
426 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
427 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
428 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
429 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
430 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
431 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
432 #define FL_FOR_ARCH6J FL_FOR_ARCH6
433 #define FL_FOR_ARCH6K FL_FOR_ARCH6
434 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
435 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6
437 /* The bits in this mask specify which
438 instructions we are allowed to generate. */
439 static unsigned long insn_flags
= 0;
441 /* The bits in this mask specify which instruction scheduling options should
443 static unsigned long tune_flags
= 0;
445 /* The following are used in the arm.md file as equivalents to bits
446 in the above two flag variables. */
448 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
451 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
454 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
457 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
460 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
463 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
466 /* Nonzero if this chip can benefit from load scheduling. */
467 int arm_ld_sched
= 0;
469 /* Nonzero if this chip is a StrongARM. */
470 int arm_tune_strongarm
= 0;
472 /* Nonzero if this chip is a Cirrus variant. */
473 int arm_arch_cirrus
= 0;
475 /* Nonzero if this chip supports Intel Wireless MMX technology. */
476 int arm_arch_iwmmxt
= 0;
478 /* Nonzero if this chip is an XScale. */
479 int arm_arch_xscale
= 0;
481 /* Nonzero if tuning for XScale */
482 int arm_tune_xscale
= 0;
484 /* Nonzero if we want to tune for stores that access the write-buffer.
485 This typically means an ARM6 or ARM7 with MMU or MPU. */
486 int arm_tune_wbuf
= 0;
488 /* Nonzero if generating Thumb instructions. */
491 /* Nonzero if we should define __THUMB_INTERWORK__ in the
493 XXX This is a bit of a hack, it's intended to help work around
494 problems in GLD which doesn't understand that armv5t code is
495 interworking clean. */
496 int arm_cpp_interwork
= 0;
498 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
499 must report the mode of the memory reference from PRINT_OPERAND to
500 PRINT_OPERAND_ADDRESS. */
501 enum machine_mode output_memory_reference_mode
;
503 /* The register number to be used for the PIC offset register. */
504 int arm_pic_register
= INVALID_REGNUM
;
506 /* Set to 1 when a return insn is output, this means that the epilogue
508 int return_used_this_function
;
510 /* Set to 1 after arm_reorg has started. Reset to start at the start of
511 the next function. */
512 static int after_arm_reorg
= 0;
514 /* The maximum number of insns to be used when loading a constant. */
515 static int arm_constant_limit
= 3;
517 /* For an explanation of these variables, see final_prescan_insn below. */
519 enum arm_cond_code arm_current_cc
;
521 int arm_target_label
;
523 /* The condition codes of the ARM, and the inverse function. */
524 static const char * const arm_condition_codes
[] =
526 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
527 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
530 #define streq(string1, string2) (strcmp (string1, string2) == 0)
532 /* Initialization code. */
536 const char *const name
;
537 enum processor_type core
;
539 const unsigned long flags
;
540 bool (* rtx_costs
) (rtx
, int, int, int *);
543 /* Not all of these give usefully different compilation alternatives,
544 but there is no simple way of generalizing them. */
545 static const struct processors all_cores
[] =
548 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
549 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
550 #include "arm-cores.def"
552 {NULL
, arm_none
, NULL
, 0, NULL
}
555 static const struct processors all_architectures
[] =
557 /* ARM Architectures */
558 /* We don't specify rtx_costs here as it will be figured out
561 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
562 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
563 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
564 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
565 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
566 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
567 implementations that support it, so we will leave it out for now. */
568 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
569 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
570 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
571 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
572 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
573 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
574 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
575 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
576 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
577 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
578 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
579 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
580 {NULL
, arm_none
, NULL
, 0 , NULL
}
583 struct arm_cpu_select
587 const struct processors
* processors
;
590 /* This is a magic structure. The 'string' field is magically filled in
591 with a pointer to the value specified by the user on the command line
592 assuming that the user has specified such a value. */
594 static struct arm_cpu_select arm_select
[] =
596 /* string name processors */
597 { NULL
, "-mcpu=", all_cores
},
598 { NULL
, "-march=", all_architectures
},
599 { NULL
, "-mtune=", all_cores
}
602 /* Defines representing the indexes into the above table. */
603 #define ARM_OPT_SET_CPU 0
604 #define ARM_OPT_SET_ARCH 1
605 #define ARM_OPT_SET_TUNE 2
607 /* The name of the proprocessor macro to define for this architecture. */
609 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
618 /* Available values for for -mfpu=. */
620 static const struct fpu_desc all_fpus
[] =
622 {"fpa", FPUTYPE_FPA
},
623 {"fpe2", FPUTYPE_FPA_EMU2
},
624 {"fpe3", FPUTYPE_FPA_EMU2
},
625 {"maverick", FPUTYPE_MAVERICK
},
630 /* Floating point models used by the different hardware.
631 See fputype in arm.h. */
633 static const enum fputype fp_model_for_fpu
[] =
635 /* No FP hardware. */
636 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
637 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
638 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
639 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
640 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
641 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
648 enum float_abi_type abi_type
;
652 /* Available values for -mfloat-abi=. */
654 static const struct float_abi all_float_abis
[] =
656 {"soft", ARM_FLOAT_ABI_SOFT
},
657 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
658 {"hard", ARM_FLOAT_ABI_HARD
}
665 enum arm_abi_type abi_type
;
669 /* Available values for -mabi=. */
671 static const struct abi_name arm_all_abis
[] =
673 {"apcs-gnu", ARM_ABI_APCS
},
674 {"atpcs", ARM_ABI_ATPCS
},
675 {"aapcs", ARM_ABI_AAPCS
},
676 {"iwmmxt", ARM_ABI_IWMMXT
}
679 /* Return the number of bits set in VALUE. */
681 bit_count (unsigned long value
)
683 unsigned long count
= 0;
688 value
&= value
- 1; /* Clear the least-significant set bit. */
694 /* Set up library functions unique to ARM. */
697 arm_init_libfuncs (void)
699 /* There are no special library functions unless we are using the
704 /* The functions below are described in Section 4 of the "Run-Time
705 ABI for the ARM architecture", Version 1.0. */
707 /* Double-precision floating-point arithmetic. Table 2. */
708 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
709 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
710 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
711 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
712 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
714 /* Double-precision comparisons. Table 3. */
715 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
716 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
717 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
718 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
719 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
720 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
721 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
723 /* Single-precision floating-point arithmetic. Table 4. */
724 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
725 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
726 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
727 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
728 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
730 /* Single-precision comparisons. Table 5. */
731 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
732 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
733 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
734 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
735 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
736 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
737 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
739 /* Floating-point to integer conversions. Table 6. */
740 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
741 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
742 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
743 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
744 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
745 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
746 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
747 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
749 /* Conversions between floating types. Table 7. */
750 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
751 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
753 /* Integer to floating-point conversions. Table 8. */
754 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
755 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
756 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
757 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
758 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
759 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
760 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
761 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
763 /* Long long. Table 9. */
764 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
765 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
766 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
767 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
768 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
769 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
770 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
771 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
773 /* Integer (32/32->32) division. \S 4.3.1. */
774 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
775 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
777 /* The divmod functions are designed so that they can be used for
778 plain division, even though they return both the quotient and the
779 remainder. The quotient is returned in the usual location (i.e.,
780 r0 for SImode, {r0, r1} for DImode), just as would be expected
781 for an ordinary division routine. Because the AAPCS calling
782 conventions specify that all of { r0, r1, r2, r3 } are
783 callee-saved registers, there is no need to tell the compiler
784 explicitly that those registers are clobbered by these
786 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
787 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
788 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idivmod");
789 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidivmod");
791 /* We don't have mod libcalls. Fortunately gcc knows how to use the
792 divmod libcalls instead. */
793 set_optab_libfunc (smod_optab
, DImode
, NULL
);
794 set_optab_libfunc (umod_optab
, DImode
, NULL
);
795 set_optab_libfunc (smod_optab
, SImode
, NULL
);
796 set_optab_libfunc (umod_optab
, SImode
, NULL
);
799 /* Implement TARGET_HANDLE_OPTION. */
802 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
807 arm_select
[1].string
= arg
;
811 arm_select
[0].string
= arg
;
814 case OPT_mhard_float
:
815 target_float_abi_name
= "hard";
818 case OPT_msoft_float
:
819 target_float_abi_name
= "soft";
823 arm_select
[2].string
= arg
;
831 /* Fix up any incompatible options that the user has specified.
832 This has now turned into a maze. */
834 arm_override_options (void)
837 enum processor_type target_arch_cpu
= arm_none
;
839 /* Set up the flags based on the cpu/architecture selected by the user. */
840 for (i
= ARRAY_SIZE (arm_select
); i
--;)
842 struct arm_cpu_select
* ptr
= arm_select
+ i
;
844 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
846 const struct processors
* sel
;
848 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
849 if (streq (ptr
->string
, sel
->name
))
851 /* Set the architecture define. */
852 if (i
!= ARM_OPT_SET_TUNE
)
853 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
855 /* Determine the processor core for which we should
856 tune code-generation. */
857 if (/* -mcpu= is a sensible default. */
859 /* -mtune= overrides -mcpu= and -march=. */
860 || i
== ARM_OPT_SET_TUNE
)
861 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
863 /* Remember the CPU associated with this architecture.
864 If no other option is used to set the CPU type,
865 we'll use this to guess the most suitable tuning
867 if (i
== ARM_OPT_SET_ARCH
)
868 target_arch_cpu
= sel
->core
;
870 if (i
!= ARM_OPT_SET_TUNE
)
872 /* If we have been given an architecture and a processor
873 make sure that they are compatible. We only generate
874 a warning though, and we prefer the CPU over the
876 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
877 warning (0, "switch -mcpu=%s conflicts with -march= switch",
880 insn_flags
= sel
->flags
;
886 if (sel
->name
== NULL
)
887 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
891 /* Guess the tuning options from the architecture if necessary. */
892 if (arm_tune
== arm_none
)
893 arm_tune
= target_arch_cpu
;
895 /* If the user did not specify a processor, choose one for them. */
898 const struct processors
* sel
;
900 enum processor_type cpu
;
902 cpu
= TARGET_CPU_DEFAULT
;
905 #ifdef SUBTARGET_CPU_DEFAULT
906 /* Use the subtarget default CPU if none was specified by
908 cpu
= SUBTARGET_CPU_DEFAULT
;
910 /* Default to ARM6. */
914 sel
= &all_cores
[cpu
];
916 insn_flags
= sel
->flags
;
918 /* Now check to see if the user has specified some command line
919 switch that require certain abilities from the cpu. */
922 if (TARGET_INTERWORK
|| TARGET_THUMB
)
924 sought
|= (FL_THUMB
| FL_MODE32
);
926 /* There are no ARM processors that support both APCS-26 and
927 interworking. Therefore we force FL_MODE26 to be removed
928 from insn_flags here (if it was set), so that the search
929 below will always be able to find a compatible processor. */
930 insn_flags
&= ~FL_MODE26
;
933 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
935 /* Try to locate a CPU type that supports all of the abilities
936 of the default CPU, plus the extra abilities requested by
938 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
939 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
942 if (sel
->name
== NULL
)
944 unsigned current_bit_count
= 0;
945 const struct processors
* best_fit
= NULL
;
947 /* Ideally we would like to issue an error message here
948 saying that it was not possible to find a CPU compatible
949 with the default CPU, but which also supports the command
950 line options specified by the programmer, and so they
951 ought to use the -mcpu=<name> command line option to
952 override the default CPU type.
954 If we cannot find a cpu that has both the
955 characteristics of the default cpu and the given
956 command line options we scan the array again looking
958 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
959 if ((sel
->flags
& sought
) == sought
)
963 count
= bit_count (sel
->flags
& insn_flags
);
965 if (count
>= current_bit_count
)
968 current_bit_count
= count
;
972 gcc_assert (best_fit
);
976 insn_flags
= sel
->flags
;
978 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
979 if (arm_tune
== arm_none
)
980 arm_tune
= (enum processor_type
) (sel
- all_cores
);
983 /* The processor for which we should tune should now have been
985 gcc_assert (arm_tune
!= arm_none
);
987 tune_flags
= all_cores
[(int)arm_tune
].flags
;
989 targetm
.rtx_costs
= arm_size_rtx_costs
;
991 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
993 /* Make sure that the processor choice does not conflict with any of the
994 other command line choices. */
995 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
997 warning (0, "target CPU does not support interworking" );
998 target_flags
&= ~MASK_INTERWORK
;
1001 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1003 warning (0, "target CPU does not support THUMB instructions");
1004 target_flags
&= ~MASK_THUMB
;
1007 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1009 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1010 target_flags
&= ~MASK_APCS_FRAME
;
1013 /* Callee super interworking implies thumb interworking. Adding
1014 this to the flags here simplifies the logic elsewhere. */
1015 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1016 target_flags
|= MASK_INTERWORK
;
1018 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1019 from here where no function is being compiled currently. */
1020 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1021 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1023 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1024 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1026 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1027 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1029 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1031 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1032 target_flags
|= MASK_APCS_FRAME
;
1035 if (TARGET_POKE_FUNCTION_NAME
)
1036 target_flags
|= MASK_APCS_FRAME
;
1038 if (TARGET_APCS_REENT
&& flag_pic
)
1039 error ("-fpic and -mapcs-reent are incompatible");
1041 if (TARGET_APCS_REENT
)
1042 warning (0, "APCS reentrant code not supported. Ignored");
1044 /* If this target is normally configured to use APCS frames, warn if they
1045 are turned off and debugging is turned on. */
1047 && write_symbols
!= NO_DEBUG
1048 && !TARGET_APCS_FRAME
1049 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1050 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1052 /* If stack checking is disabled, we can use r10 as the PIC register,
1053 which keeps r9 available. */
1055 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1057 if (TARGET_APCS_FLOAT
)
1058 warning (0, "passing floating point arguments in fp regs not yet supported");
1060 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1061 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1062 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1063 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1064 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1065 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1066 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1067 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1068 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1070 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1071 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1072 thumb_code
= (TARGET_ARM
== 0);
1073 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1074 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1075 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1077 /* V5 code we generate is completely interworking capable, so we turn off
1078 TARGET_INTERWORK here to avoid many tests later on. */
1080 /* XXX However, we must pass the right pre-processor defines to CPP
1081 or GLD can get confused. This is a hack. */
1082 if (TARGET_INTERWORK
)
1083 arm_cpp_interwork
= 1;
1086 target_flags
&= ~MASK_INTERWORK
;
1088 if (target_abi_name
)
1090 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1092 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1094 arm_abi
= arm_all_abis
[i
].abi_type
;
1098 if (i
== ARRAY_SIZE (arm_all_abis
))
1099 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1102 arm_abi
= ARM_DEFAULT_ABI
;
1104 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1105 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1107 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1108 error ("iwmmxt abi requires an iwmmxt capable cpu");
1110 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1111 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1113 if (streq (target_fpe_name
, "2"))
1114 target_fpu_name
= "fpe2";
1115 else if (streq (target_fpe_name
, "3"))
1116 target_fpu_name
= "fpe3";
1118 error ("invalid floating point emulation option: -mfpe=%s",
1121 if (target_fpu_name
!= NULL
)
1123 /* The user specified a FPU. */
1124 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1126 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1128 arm_fpu_arch
= all_fpus
[i
].fpu
;
1129 arm_fpu_tune
= arm_fpu_arch
;
1130 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1134 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1135 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1139 #ifdef FPUTYPE_DEFAULT
1140 /* Use the default if it is specified for this platform. */
1141 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1142 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1144 /* Pick one based on CPU type. */
1145 /* ??? Some targets assume FPA is the default.
1146 if ((insn_flags & FL_VFP) != 0)
1147 arm_fpu_arch = FPUTYPE_VFP;
1150 if (arm_arch_cirrus
)
1151 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1153 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1155 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1156 arm_fpu_tune
= FPUTYPE_FPA
;
1158 arm_fpu_tune
= arm_fpu_arch
;
1159 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1160 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1163 if (target_float_abi_name
!= NULL
)
1165 /* The user specified a FP ABI. */
1166 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1168 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1170 arm_float_abi
= all_float_abis
[i
].abi_type
;
1174 if (i
== ARRAY_SIZE (all_float_abis
))
1175 error ("invalid floating point abi: -mfloat-abi=%s",
1176 target_float_abi_name
);
1179 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1181 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1182 sorry ("-mfloat-abi=hard and VFP");
1184 /* If soft-float is specified then don't use FPU. */
1185 if (TARGET_SOFT_FLOAT
)
1186 arm_fpu_arch
= FPUTYPE_NONE
;
1188 /* For arm2/3 there is no need to do any scheduling if there is only
1189 a floating point emulator, or we are doing software floating-point. */
1190 if ((TARGET_SOFT_FLOAT
1191 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1192 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1193 && (tune_flags
& FL_MODE32
) == 0)
1194 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1196 /* Override the default structure alignment for AAPCS ABI. */
1197 if (arm_abi
== ARM_ABI_AAPCS
)
1198 arm_structure_size_boundary
= 8;
1200 if (structure_size_string
!= NULL
)
1202 int size
= strtol (structure_size_string
, NULL
, 0);
1204 if (size
== 8 || size
== 32
1205 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1206 arm_structure_size_boundary
= size
;
1208 warning (0, "structure size boundary can only be set to %s",
1209 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1212 if (arm_pic_register_string
!= NULL
)
1214 int pic_register
= decode_reg_name (arm_pic_register_string
);
1217 warning (0, "-mpic-register= is useless without -fpic");
1219 /* Prevent the user from choosing an obviously stupid PIC register. */
1220 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1221 || pic_register
== HARD_FRAME_POINTER_REGNUM
1222 || pic_register
== STACK_POINTER_REGNUM
1223 || pic_register
>= PC_REGNUM
)
1224 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1226 arm_pic_register
= pic_register
;
1229 if (TARGET_THUMB
&& flag_schedule_insns
)
1231 /* Don't warn since it's on by default in -O2. */
1232 flag_schedule_insns
= 0;
1237 arm_constant_limit
= 1;
1239 /* If optimizing for size, bump the number of instructions that we
1240 are prepared to conditionally execute (even on a StrongARM). */
1241 max_insns_skipped
= 6;
1245 /* For processors with load scheduling, it never costs more than
1246 2 cycles to load a constant, and the load scheduler may well
1247 reduce that to 1. */
1249 arm_constant_limit
= 1;
1251 /* On XScale the longer latency of a load makes it more difficult
1252 to achieve a good schedule, so it's faster to synthesize
1253 constants that can be done in two insns. */
1254 if (arm_tune_xscale
)
1255 arm_constant_limit
= 2;
1257 /* StrongARM has early execution of branches, so a sequence
1258 that is worth skipping is shorter. */
1259 if (arm_tune_strongarm
)
1260 max_insns_skipped
= 3;
1263 /* Register global variables with the garbage collector. */
1264 arm_add_gc_roots ();
1268 arm_add_gc_roots (void)
1270 gcc_obstack_init(&minipool_obstack
);
1271 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1274 /* A table of known ARM exception types.
1275 For use with the interrupt function attribute. */
1279 const char *const arg
;
1280 const unsigned long return_value
;
1284 static const isr_attribute_arg isr_attribute_args
[] =
1286 { "IRQ", ARM_FT_ISR
},
1287 { "irq", ARM_FT_ISR
},
1288 { "FIQ", ARM_FT_FIQ
},
1289 { "fiq", ARM_FT_FIQ
},
1290 { "ABORT", ARM_FT_ISR
},
1291 { "abort", ARM_FT_ISR
},
1292 { "ABORT", ARM_FT_ISR
},
1293 { "abort", ARM_FT_ISR
},
1294 { "UNDEF", ARM_FT_EXCEPTION
},
1295 { "undef", ARM_FT_EXCEPTION
},
1296 { "SWI", ARM_FT_EXCEPTION
},
1297 { "swi", ARM_FT_EXCEPTION
},
1298 { NULL
, ARM_FT_NORMAL
}
1301 /* Returns the (interrupt) function type of the current
1302 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1304 static unsigned long
1305 arm_isr_value (tree argument
)
1307 const isr_attribute_arg
* ptr
;
1310 /* No argument - default to IRQ. */
1311 if (argument
== NULL_TREE
)
1314 /* Get the value of the argument. */
1315 if (TREE_VALUE (argument
) == NULL_TREE
1316 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1317 return ARM_FT_UNKNOWN
;
1319 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1321 /* Check it against the list of known arguments. */
1322 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1323 if (streq (arg
, ptr
->arg
))
1324 return ptr
->return_value
;
1326 /* An unrecognized interrupt type. */
1327 return ARM_FT_UNKNOWN
;
1330 /* Computes the type of the current function. */
1332 static unsigned long
1333 arm_compute_func_type (void)
1335 unsigned long type
= ARM_FT_UNKNOWN
;
1339 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1341 /* Decide if the current function is volatile. Such functions
1342 never return, and many memory cycles can be saved by not storing
1343 register values that will never be needed again. This optimization
1344 was added to speed up context switching in a kernel application. */
1346 && TREE_NOTHROW (current_function_decl
)
1347 && TREE_THIS_VOLATILE (current_function_decl
))
1348 type
|= ARM_FT_VOLATILE
;
1350 if (cfun
->static_chain_decl
!= NULL
)
1351 type
|= ARM_FT_NESTED
;
1353 attr
= DECL_ATTRIBUTES (current_function_decl
);
1355 a
= lookup_attribute ("naked", attr
);
1357 type
|= ARM_FT_NAKED
;
1359 a
= lookup_attribute ("isr", attr
);
1361 a
= lookup_attribute ("interrupt", attr
);
1364 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1366 type
|= arm_isr_value (TREE_VALUE (a
));
1371 /* Returns the type of the current function. */
1374 arm_current_func_type (void)
1376 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1377 cfun
->machine
->func_type
= arm_compute_func_type ();
1379 return cfun
->machine
->func_type
;
1382 /* Return 1 if it is possible to return using a single instruction.
1383 If SIBLING is non-null, this is a test for a return before a sibling
1384 call. SIBLING is the call insn, so we can examine its register usage. */
1387 use_return_insn (int iscond
, rtx sibling
)
1390 unsigned int func_type
;
1391 unsigned long saved_int_regs
;
1392 unsigned HOST_WIDE_INT stack_adjust
;
1393 arm_stack_offsets
*offsets
;
1395 /* Never use a return instruction before reload has run. */
1396 if (!reload_completed
)
1399 func_type
= arm_current_func_type ();
1401 /* Naked functions and volatile functions need special
1403 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1406 /* So do interrupt functions that use the frame pointer. */
1407 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1410 offsets
= arm_get_frame_offsets ();
1411 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1413 /* As do variadic functions. */
1414 if (current_function_pretend_args_size
1415 || cfun
->machine
->uses_anonymous_args
1416 /* Or if the function calls __builtin_eh_return () */
1417 || current_function_calls_eh_return
1418 /* Or if the function calls alloca */
1419 || current_function_calls_alloca
1420 /* Or if there is a stack adjustment. However, if the stack pointer
1421 is saved on the stack, we can use a pre-incrementing stack load. */
1422 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1425 saved_int_regs
= arm_compute_save_reg_mask ();
1427 /* Unfortunately, the insn
1429 ldmib sp, {..., sp, ...}
1431 triggers a bug on most SA-110 based devices, such that the stack
1432 pointer won't be correctly restored if the instruction takes a
1433 page fault. We work around this problem by popping r3 along with
1434 the other registers, since that is never slower than executing
1435 another instruction.
1437 We test for !arm_arch5 here, because code for any architecture
1438 less than this could potentially be run on one of the buggy
1440 if (stack_adjust
== 4 && !arm_arch5
)
1442 /* Validate that r3 is a call-clobbered register (always true in
1443 the default abi) ... */
1444 if (!call_used_regs
[3])
1447 /* ... that it isn't being used for a return value ... */
1448 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1451 /* ... or for a tail-call argument ... */
1454 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1456 if (find_regno_fusage (sibling
, USE
, 3))
1460 /* ... and that there are no call-saved registers in r0-r2
1461 (always true in the default ABI). */
1462 if (saved_int_regs
& 0x7)
1466 /* Can't be done if interworking with Thumb, and any registers have been
1468 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1471 /* On StrongARM, conditional returns are expensive if they aren't
1472 taken and multiple registers have been stacked. */
1473 if (iscond
&& arm_tune_strongarm
)
1475 /* Conditional return when just the LR is stored is a simple
1476 conditional-load instruction, that's not expensive. */
1477 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1480 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1484 /* If there are saved registers but the LR isn't saved, then we need
1485 two instructions for the return. */
1486 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1489 /* Can't be done if any of the FPA regs are pushed,
1490 since this also requires an insn. */
1491 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1492 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1493 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1496 /* Likewise VFP regs. */
1497 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1498 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1499 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1502 if (TARGET_REALLY_IWMMXT
)
1503 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1504 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1510 /* Return TRUE if int I is a valid immediate ARM constant. */
1513 const_ok_for_arm (HOST_WIDE_INT i
)
1517 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1518 be all zero, or all one. */
1519 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1520 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1521 != ((~(unsigned HOST_WIDE_INT
) 0)
1522 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1525 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1527 /* Fast return for 0 and small values. We must do this for zero, since
1528 the code below can't handle that one case. */
1529 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1532 /* Get the number of trailing zeros, rounded down to the nearest even
1534 lowbit
= (ffs ((int) i
) - 1) & ~1;
1536 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1538 else if (lowbit
<= 4
1539 && ((i
& ~0xc000003f) == 0
1540 || (i
& ~0xf000000f) == 0
1541 || (i
& ~0xfc000003) == 0))
1547 /* Return true if I is a valid constant for the operation CODE. */
1549 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1551 if (const_ok_for_arm (i
))
1557 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1559 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1565 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1572 /* Emit a sequence of insns to handle a large constant.
1573 CODE is the code of the operation required, it can be any of SET, PLUS,
1574 IOR, AND, XOR, MINUS;
1575 MODE is the mode in which the operation is being performed;
1576 VAL is the integer to operate on;
1577 SOURCE is the other operand (a register, or a null-pointer for SET);
1578 SUBTARGETS means it is safe to create scratch registers if that will
1579 either produce a simpler sequence, or we will want to cse the values.
1580 Return value is the number of insns emitted. */
1583 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1584 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1588 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1589 cond
= COND_EXEC_TEST (PATTERN (insn
));
1593 if (subtargets
|| code
== SET
1594 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1595 && REGNO (target
) != REGNO (source
)))
1597 /* After arm_reorg has been called, we can't fix up expensive
1598 constants by pushing them into memory so we must synthesize
1599 them in-line, regardless of the cost. This is only likely to
1600 be more costly on chips that have load delay slots and we are
1601 compiling without running the scheduler (so no splitting
1602 occurred before the final instruction emission).
1604 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1606 if (!after_arm_reorg
1608 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1610 > arm_constant_limit
+ (code
!= SET
)))
1614 /* Currently SET is the only monadic value for CODE, all
1615 the rest are diadic. */
1616 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1621 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1623 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1624 /* For MINUS, the value is subtracted from, since we never
1625 have subtraction of a constant. */
1627 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1628 gen_rtx_MINUS (mode
, temp
, source
)));
1630 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1631 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1637 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1642 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1644 HOST_WIDE_INT temp1
;
1652 if (remainder
& (3 << (i
- 2)))
1657 temp1
= remainder
& ((0x0ff << end
)
1658 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1659 remainder
&= ~temp1
;
1664 } while (remainder
);
1668 /* Emit an instruction with the indicated PATTERN. If COND is
1669 non-NULL, conditionalize the execution of the instruction on COND
1673 emit_constant_insn (rtx cond
, rtx pattern
)
1676 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1677 emit_insn (pattern
);
1680 /* As above, but extra parameter GENERATE which, if clear, suppresses
1684 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1685 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1690 int can_negate_initial
= 0;
1693 int num_bits_set
= 0;
1694 int set_sign_bit_copies
= 0;
1695 int clear_sign_bit_copies
= 0;
1696 int clear_zero_bit_copies
= 0;
1697 int set_zero_bit_copies
= 0;
1699 unsigned HOST_WIDE_INT temp1
, temp2
;
1700 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1702 /* Find out which operations are safe for a given CODE. Also do a quick
1703 check for degenerate cases; these can occur when DImode operations
1715 can_negate_initial
= 1;
1719 if (remainder
== 0xffffffff)
1722 emit_constant_insn (cond
,
1723 gen_rtx_SET (VOIDmode
, target
,
1724 GEN_INT (ARM_SIGN_EXTEND (val
))));
1729 if (reload_completed
&& rtx_equal_p (target
, source
))
1732 emit_constant_insn (cond
,
1733 gen_rtx_SET (VOIDmode
, target
, source
));
1742 emit_constant_insn (cond
,
1743 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1746 if (remainder
== 0xffffffff)
1748 if (reload_completed
&& rtx_equal_p (target
, source
))
1751 emit_constant_insn (cond
,
1752 gen_rtx_SET (VOIDmode
, target
, source
));
1761 if (reload_completed
&& rtx_equal_p (target
, source
))
1764 emit_constant_insn (cond
,
1765 gen_rtx_SET (VOIDmode
, target
, source
));
1769 /* We don't know how to handle other cases yet. */
1770 gcc_assert (remainder
== 0xffffffff);
1773 emit_constant_insn (cond
,
1774 gen_rtx_SET (VOIDmode
, target
,
1775 gen_rtx_NOT (mode
, source
)));
1779 /* We treat MINUS as (val - source), since (source - val) is always
1780 passed as (source + (-val)). */
1784 emit_constant_insn (cond
,
1785 gen_rtx_SET (VOIDmode
, target
,
1786 gen_rtx_NEG (mode
, source
)));
1789 if (const_ok_for_arm (val
))
1792 emit_constant_insn (cond
,
1793 gen_rtx_SET (VOIDmode
, target
,
1794 gen_rtx_MINUS (mode
, GEN_INT (val
),
1806 /* If we can do it in one insn get out quickly. */
1807 if (const_ok_for_arm (val
)
1808 || (can_negate_initial
&& const_ok_for_arm (-val
))
1809 || (can_invert
&& const_ok_for_arm (~val
)))
1812 emit_constant_insn (cond
,
1813 gen_rtx_SET (VOIDmode
, target
,
1815 ? gen_rtx_fmt_ee (code
, mode
, source
,
1821 /* Calculate a few attributes that may be useful for specific
1823 for (i
= 31; i
>= 0; i
--)
1825 if ((remainder
& (1 << i
)) == 0)
1826 clear_sign_bit_copies
++;
1831 for (i
= 31; i
>= 0; i
--)
1833 if ((remainder
& (1 << i
)) != 0)
1834 set_sign_bit_copies
++;
1839 for (i
= 0; i
<= 31; i
++)
1841 if ((remainder
& (1 << i
)) == 0)
1842 clear_zero_bit_copies
++;
1847 for (i
= 0; i
<= 31; i
++)
1849 if ((remainder
& (1 << i
)) != 0)
1850 set_zero_bit_copies
++;
1858 /* See if we can do this by sign_extending a constant that is known
1859 to be negative. This is a good, way of doing it, since the shift
1860 may well merge into a subsequent insn. */
1861 if (set_sign_bit_copies
> 1)
1863 if (const_ok_for_arm
1864 (temp1
= ARM_SIGN_EXTEND (remainder
1865 << (set_sign_bit_copies
- 1))))
1869 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1870 emit_constant_insn (cond
,
1871 gen_rtx_SET (VOIDmode
, new_src
,
1873 emit_constant_insn (cond
,
1874 gen_ashrsi3 (target
, new_src
,
1875 GEN_INT (set_sign_bit_copies
- 1)));
1879 /* For an inverted constant, we will need to set the low bits,
1880 these will be shifted out of harm's way. */
1881 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1882 if (const_ok_for_arm (~temp1
))
1886 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1887 emit_constant_insn (cond
,
1888 gen_rtx_SET (VOIDmode
, new_src
,
1890 emit_constant_insn (cond
,
1891 gen_ashrsi3 (target
, new_src
,
1892 GEN_INT (set_sign_bit_copies
- 1)));
1898 /* See if we can calculate the value as the difference between two
1899 valid immediates. */
1900 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1902 int topshift
= clear_sign_bit_copies
& ~1;
1904 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1905 & (0xff000000 >> topshift
));
1907 /* If temp1 is zero, then that means the 9 most significant
1908 bits of remainder were 1 and we've caused it to overflow.
1909 When topshift is 0 we don't need to do anything since we
1910 can borrow from 'bit 32'. */
1911 if (temp1
== 0 && topshift
!= 0)
1912 temp1
= 0x80000000 >> (topshift
- 1);
1914 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1916 if (const_ok_for_arm (temp2
))
1920 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1921 emit_constant_insn (cond
,
1922 gen_rtx_SET (VOIDmode
, new_src
,
1924 emit_constant_insn (cond
,
1925 gen_addsi3 (target
, new_src
,
1933 /* See if we can generate this by setting the bottom (or the top)
1934 16 bits, and then shifting these into the other half of the
1935 word. We only look for the simplest cases, to do more would cost
1936 too much. Be careful, however, not to generate this when the
1937 alternative would take fewer insns. */
1938 if (val
& 0xffff0000)
1940 temp1
= remainder
& 0xffff0000;
1941 temp2
= remainder
& 0x0000ffff;
1943 /* Overlaps outside this range are best done using other methods. */
1944 for (i
= 9; i
< 24; i
++)
1946 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1947 && !const_ok_for_arm (temp2
))
1949 rtx new_src
= (subtargets
1950 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1952 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
1953 source
, subtargets
, generate
);
1961 gen_rtx_ASHIFT (mode
, source
,
1968 /* Don't duplicate cases already considered. */
1969 for (i
= 17; i
< 24; i
++)
1971 if (((temp1
| (temp1
>> i
)) == remainder
)
1972 && !const_ok_for_arm (temp1
))
1974 rtx new_src
= (subtargets
1975 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1977 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
1978 source
, subtargets
, generate
);
1983 gen_rtx_SET (VOIDmode
, target
,
1986 gen_rtx_LSHIFTRT (mode
, source
,
1997 /* If we have IOR or XOR, and the constant can be loaded in a
1998 single instruction, and we can find a temporary to put it in,
1999 then this can be done in two instructions instead of 3-4. */
2001 /* TARGET can't be NULL if SUBTARGETS is 0 */
2002 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2004 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2008 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2010 emit_constant_insn (cond
,
2011 gen_rtx_SET (VOIDmode
, sub
,
2013 emit_constant_insn (cond
,
2014 gen_rtx_SET (VOIDmode
, target
,
2015 gen_rtx_fmt_ee (code
, mode
,
2025 if (set_sign_bit_copies
> 8
2026 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2030 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2031 rtx shift
= GEN_INT (set_sign_bit_copies
);
2035 gen_rtx_SET (VOIDmode
, sub
,
2037 gen_rtx_ASHIFT (mode
,
2042 gen_rtx_SET (VOIDmode
, target
,
2044 gen_rtx_LSHIFTRT (mode
, sub
,
2050 if (set_zero_bit_copies
> 8
2051 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2055 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2056 rtx shift
= GEN_INT (set_zero_bit_copies
);
2060 gen_rtx_SET (VOIDmode
, sub
,
2062 gen_rtx_LSHIFTRT (mode
,
2067 gen_rtx_SET (VOIDmode
, target
,
2069 gen_rtx_ASHIFT (mode
, sub
,
2075 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2079 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2080 emit_constant_insn (cond
,
2081 gen_rtx_SET (VOIDmode
, sub
,
2082 gen_rtx_NOT (mode
, source
)));
2085 sub
= gen_reg_rtx (mode
);
2086 emit_constant_insn (cond
,
2087 gen_rtx_SET (VOIDmode
, sub
,
2088 gen_rtx_AND (mode
, source
,
2090 emit_constant_insn (cond
,
2091 gen_rtx_SET (VOIDmode
, target
,
2092 gen_rtx_NOT (mode
, sub
)));
2099 /* See if two shifts will do 2 or more insn's worth of work. */
2100 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2102 HOST_WIDE_INT shift_mask
= ((0xffffffff
2103 << (32 - clear_sign_bit_copies
))
2106 if ((remainder
| shift_mask
) != 0xffffffff)
2110 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2111 insns
= arm_gen_constant (AND
, mode
, cond
,
2112 remainder
| shift_mask
,
2113 new_src
, source
, subtargets
, 1);
2118 rtx targ
= subtargets
? NULL_RTX
: target
;
2119 insns
= arm_gen_constant (AND
, mode
, cond
,
2120 remainder
| shift_mask
,
2121 targ
, source
, subtargets
, 0);
2127 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2128 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2130 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2131 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2137 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2139 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2141 if ((remainder
| shift_mask
) != 0xffffffff)
2145 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2147 insns
= arm_gen_constant (AND
, mode
, cond
,
2148 remainder
| shift_mask
,
2149 new_src
, source
, subtargets
, 1);
2154 rtx targ
= subtargets
? NULL_RTX
: target
;
2156 insns
= arm_gen_constant (AND
, mode
, cond
,
2157 remainder
| shift_mask
,
2158 targ
, source
, subtargets
, 0);
2164 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2165 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2167 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2168 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2180 for (i
= 0; i
< 32; i
++)
2181 if (remainder
& (1 << i
))
2184 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2185 remainder
= (~remainder
) & 0xffffffff;
2186 else if (code
== PLUS
&& num_bits_set
> 16)
2187 remainder
= (-remainder
) & 0xffffffff;
2194 /* Now try and find a way of doing the job in either two or three
2196 We start by looking for the largest block of zeros that are aligned on
2197 a 2-bit boundary, we then fill up the temps, wrapping around to the
2198 top of the word when we drop off the bottom.
2199 In the worst case this code should produce no more than four insns. */
2202 int best_consecutive_zeros
= 0;
2204 for (i
= 0; i
< 32; i
+= 2)
2206 int consecutive_zeros
= 0;
2208 if (!(remainder
& (3 << i
)))
2210 while ((i
< 32) && !(remainder
& (3 << i
)))
2212 consecutive_zeros
+= 2;
2215 if (consecutive_zeros
> best_consecutive_zeros
)
2217 best_consecutive_zeros
= consecutive_zeros
;
2218 best_start
= i
- consecutive_zeros
;
2224 /* So long as it won't require any more insns to do so, it's
2225 desirable to emit a small constant (in bits 0...9) in the last
2226 insn. This way there is more chance that it can be combined with
2227 a later addressing insn to form a pre-indexed load or store
2228 operation. Consider:
2230 *((volatile int *)0xe0000100) = 1;
2231 *((volatile int *)0xe0000110) = 2;
2233 We want this to wind up as:
2237 str rB, [rA, #0x100]
2239 str rB, [rA, #0x110]
2241 rather than having to synthesize both large constants from scratch.
2243 Therefore, we calculate how many insns would be required to emit
2244 the constant starting from `best_start', and also starting from
2245 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2246 yield a shorter sequence, we may as well use zero. */
2248 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2249 && (count_insns_for_constant (remainder
, 0) <=
2250 count_insns_for_constant (remainder
, best_start
)))
2253 /* Now start emitting the insns. */
2261 if (remainder
& (3 << (i
- 2)))
2266 temp1
= remainder
& ((0x0ff << end
)
2267 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2268 remainder
&= ~temp1
;
2272 rtx new_src
, temp1_rtx
;
2274 if (code
== SET
|| code
== MINUS
)
2276 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2277 if (can_invert
&& code
!= MINUS
)
2282 if (remainder
&& subtargets
)
2283 new_src
= gen_reg_rtx (mode
);
2288 else if (can_negate
)
2292 temp1
= trunc_int_for_mode (temp1
, mode
);
2293 temp1_rtx
= GEN_INT (temp1
);
2297 else if (code
== MINUS
)
2298 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2300 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2302 emit_constant_insn (cond
,
2303 gen_rtx_SET (VOIDmode
, new_src
,
2313 else if (code
== MINUS
)
2327 /* Canonicalize a comparison so that we are more likely to recognize it.
2328 This can be done for a few constant compares, where we can make the
2329 immediate value easier to load. */
2332 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2335 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2336 unsigned HOST_WIDE_INT maxval
;
2337 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2348 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2350 *op1
= GEN_INT (i
+ 1);
2351 return code
== GT
? GE
: LT
;
2358 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2360 *op1
= GEN_INT (i
- 1);
2361 return code
== GE
? GT
: LE
;
2367 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2368 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2370 *op1
= GEN_INT (i
+ 1);
2371 return code
== GTU
? GEU
: LTU
;
2378 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2380 *op1
= GEN_INT (i
- 1);
2381 return code
== GEU
? GTU
: LEU
;
2393 /* Define how to find the value returned by a function. */
2396 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2398 enum machine_mode mode
;
2399 int unsignedp ATTRIBUTE_UNUSED
;
2400 rtx r ATTRIBUTE_UNUSED
;
2402 mode
= TYPE_MODE (type
);
2403 /* Promote integer types. */
2404 if (INTEGRAL_TYPE_P (type
))
2405 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2407 /* Promotes small structs returned in a register to full-word size
2408 for big-endian AAPCS. */
2409 if (arm_return_in_msb (type
))
2411 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2412 if (size
% UNITS_PER_WORD
!= 0)
2414 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2415 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2419 return LIBCALL_VALUE(mode
);
2422 /* Determine the amount of memory needed to store the possible return
2423 registers of an untyped call. */
2425 arm_apply_result_size (void)
2431 if (TARGET_HARD_FLOAT_ABI
)
2435 if (TARGET_MAVERICK
)
2438 if (TARGET_IWMMXT_ABI
)
2445 /* Decide whether a type should be returned in memory (true)
2446 or in a register (false). This is called by the macro
2447 RETURN_IN_MEMORY. */
2449 arm_return_in_memory (tree type
)
2453 if (!AGGREGATE_TYPE_P (type
) &&
2454 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2455 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2456 /* All simple types are returned in registers.
2457 For AAPCS, complex types are treated the same as aggregates. */
2460 size
= int_size_in_bytes (type
);
2462 if (arm_abi
!= ARM_ABI_APCS
)
2464 /* ATPCS and later return aggregate types in memory only if they are
2465 larger than a word (or are variable size). */
2466 return (size
< 0 || size
> UNITS_PER_WORD
);
2469 /* To maximize backwards compatibility with previous versions of gcc,
2470 return vectors up to 4 words in registers. */
2471 if (TREE_CODE (type
) == VECTOR_TYPE
)
2472 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2474 /* For the arm-wince targets we choose to be compatible with Microsoft's
2475 ARM and Thumb compilers, which always return aggregates in memory. */
2477 /* All structures/unions bigger than one word are returned in memory.
2478 Also catch the case where int_size_in_bytes returns -1. In this case
2479 the aggregate is either huge or of variable size, and in either case
2480 we will want to return it via memory and not in a register. */
2481 if (size
< 0 || size
> UNITS_PER_WORD
)
2484 if (TREE_CODE (type
) == RECORD_TYPE
)
2488 /* For a struct the APCS says that we only return in a register
2489 if the type is 'integer like' and every addressable element
2490 has an offset of zero. For practical purposes this means
2491 that the structure can have at most one non bit-field element
2492 and that this element must be the first one in the structure. */
2494 /* Find the first field, ignoring non FIELD_DECL things which will
2495 have been created by C++. */
2496 for (field
= TYPE_FIELDS (type
);
2497 field
&& TREE_CODE (field
) != FIELD_DECL
;
2498 field
= TREE_CHAIN (field
))
2502 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2504 /* Check that the first field is valid for returning in a register. */
2506 /* ... Floats are not allowed */
2507 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2510 /* ... Aggregates that are not themselves valid for returning in
2511 a register are not allowed. */
2512 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2515 /* Now check the remaining fields, if any. Only bitfields are allowed,
2516 since they are not addressable. */
2517 for (field
= TREE_CHAIN (field
);
2519 field
= TREE_CHAIN (field
))
2521 if (TREE_CODE (field
) != FIELD_DECL
)
2524 if (!DECL_BIT_FIELD_TYPE (field
))
2531 if (TREE_CODE (type
) == UNION_TYPE
)
2535 /* Unions can be returned in registers if every element is
2536 integral, or can be returned in an integer register. */
2537 for (field
= TYPE_FIELDS (type
);
2539 field
= TREE_CHAIN (field
))
2541 if (TREE_CODE (field
) != FIELD_DECL
)
2544 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2547 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2553 #endif /* not ARM_WINCE */
2555 /* Return all other types in memory. */
2559 /* Indicate whether or not words of a double are in big-endian order. */
2562 arm_float_words_big_endian (void)
2564 if (TARGET_MAVERICK
)
2567 /* For FPA, float words are always big-endian. For VFP, floats words
2568 follow the memory system mode. */
2576 return (TARGET_BIG_END
? 1 : 0);
2581 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2582 for a call to a function whose data type is FNTYPE.
2583 For a library call, FNTYPE is NULL. */
2585 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2586 rtx libname ATTRIBUTE_UNUSED
,
2587 tree fndecl ATTRIBUTE_UNUSED
)
2589 /* On the ARM, the offset starts at 0. */
2590 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2591 pcum
->iwmmxt_nregs
= 0;
2592 pcum
->can_split
= true;
2594 pcum
->call_cookie
= CALL_NORMAL
;
2596 if (TARGET_LONG_CALLS
)
2597 pcum
->call_cookie
= CALL_LONG
;
2599 /* Check for long call/short call attributes. The attributes
2600 override any command line option. */
2603 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2604 pcum
->call_cookie
= CALL_SHORT
;
2605 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2606 pcum
->call_cookie
= CALL_LONG
;
2609 /* Varargs vectors are treated the same as long long.
2610 named_count avoids having to change the way arm handles 'named' */
2611 pcum
->named_count
= 0;
2614 if (TARGET_REALLY_IWMMXT
&& fntype
)
2618 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2620 fn_arg
= TREE_CHAIN (fn_arg
))
2621 pcum
->named_count
+= 1;
2623 if (! pcum
->named_count
)
2624 pcum
->named_count
= INT_MAX
;
2629 /* Return true if mode/type need doubleword alignment. */
2631 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2633 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2634 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2638 /* Determine where to put an argument to a function.
2639 Value is zero to push the argument on the stack,
2640 or a hard register in which to store the argument.
2642 MODE is the argument's machine mode.
2643 TYPE is the data type of the argument (as a tree).
2644 This is null for libcalls where that information may
2646 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2647 the preceding args and about the function being called.
2648 NAMED is nonzero if this argument is a named parameter
2649 (otherwise it is an extra parameter matching an ellipsis). */
2652 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2653 tree type
, int named
)
2657 /* Varargs vectors are treated the same as long long.
2658 named_count avoids having to change the way arm handles 'named' */
2659 if (TARGET_IWMMXT_ABI
2660 && arm_vector_mode_supported_p (mode
)
2661 && pcum
->named_count
> pcum
->nargs
+ 1)
2663 if (pcum
->iwmmxt_nregs
<= 9)
2664 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2667 pcum
->can_split
= false;
2672 /* Put doubleword aligned quantities in even register pairs. */
2674 && ARM_DOUBLEWORD_ALIGN
2675 && arm_needs_doubleword_align (mode
, type
))
2678 if (mode
== VOIDmode
)
2679 /* Compute operand 2 of the call insn. */
2680 return GEN_INT (pcum
->call_cookie
);
2682 /* Only allow splitting an arg between regs and memory if all preceding
2683 args were allocated to regs. For args passed by reference we only count
2684 the reference pointer. */
2685 if (pcum
->can_split
)
2688 nregs
= ARM_NUM_REGS2 (mode
, type
);
2690 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2693 return gen_rtx_REG (mode
, pcum
->nregs
);
2697 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2698 tree type
, bool named ATTRIBUTE_UNUSED
)
2700 int nregs
= pcum
->nregs
;
2702 if (arm_vector_mode_supported_p (mode
))
2705 if (NUM_ARG_REGS
> nregs
2706 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2708 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2713 /* Variable sized types are passed by reference. This is a GCC
2714 extension to the ARM ABI. */
2717 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2718 enum machine_mode mode ATTRIBUTE_UNUSED
,
2719 tree type
, bool named ATTRIBUTE_UNUSED
)
2721 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2724 /* Encode the current state of the #pragma [no_]long_calls. */
2727 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2728 LONG
, /* #pragma long_calls is in effect. */
2729 SHORT
/* #pragma no_long_calls is in effect. */
2732 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2735 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2737 arm_pragma_long_calls
= LONG
;
2741 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2743 arm_pragma_long_calls
= SHORT
;
2747 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2749 arm_pragma_long_calls
= OFF
;
2752 /* Table of machine attributes. */
2753 const struct attribute_spec arm_attribute_table
[] =
2755 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2756 /* Function calls made to this symbol must be done indirectly, because
2757 it may lie outside of the 26 bit addressing range of a normal function
2759 { "long_call", 0, 0, false, true, true, NULL
},
2760 /* Whereas these functions are always known to reside within the 26 bit
2761 addressing range. */
2762 { "short_call", 0, 0, false, true, true, NULL
},
2763 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2764 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2765 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2766 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2768 /* ARM/PE has three new attributes:
2770 dllexport - for exporting a function/variable that will live in a dll
2771 dllimport - for importing a function/variable from a dll
2773 Microsoft allows multiple declspecs in one __declspec, separating
2774 them with spaces. We do NOT support this. Instead, use __declspec
2777 { "dllimport", 0, 0, true, false, false, NULL
},
2778 { "dllexport", 0, 0, true, false, false, NULL
},
2779 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2780 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2781 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2782 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2783 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2785 { NULL
, 0, 0, false, false, false, NULL
}
2788 /* Handle an attribute requiring a FUNCTION_DECL;
2789 arguments as in struct attribute_spec.handler. */
2791 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2792 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2794 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2796 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2797 IDENTIFIER_POINTER (name
));
2798 *no_add_attrs
= true;
2804 /* Handle an "interrupt" or "isr" attribute;
2805 arguments as in struct attribute_spec.handler. */
2807 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2812 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2814 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2815 IDENTIFIER_POINTER (name
));
2816 *no_add_attrs
= true;
2818 /* FIXME: the argument if any is checked for type attributes;
2819 should it be checked for decl ones? */
2823 if (TREE_CODE (*node
) == FUNCTION_TYPE
2824 || TREE_CODE (*node
) == METHOD_TYPE
)
2826 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2828 warning (OPT_Wattributes
, "%qs attribute ignored",
2829 IDENTIFIER_POINTER (name
));
2830 *no_add_attrs
= true;
2833 else if (TREE_CODE (*node
) == POINTER_TYPE
2834 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2835 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2836 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2838 *node
= build_variant_type_copy (*node
);
2839 TREE_TYPE (*node
) = build_type_attribute_variant
2841 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2842 *no_add_attrs
= true;
2846 /* Possibly pass this attribute on from the type to a decl. */
2847 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2848 | (int) ATTR_FLAG_FUNCTION_NEXT
2849 | (int) ATTR_FLAG_ARRAY_NEXT
))
2851 *no_add_attrs
= true;
2852 return tree_cons (name
, args
, NULL_TREE
);
2856 warning (OPT_Wattributes
, "%qs attribute ignored",
2857 IDENTIFIER_POINTER (name
));
2865 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2866 /* Handle the "notshared" attribute. This attribute is another way of
2867 requesting hidden visibility. ARM's compiler supports
2868 "__declspec(notshared)"; we support the same thing via an
2872 arm_handle_notshared_attribute (tree
*node
,
2873 tree name ATTRIBUTE_UNUSED
,
2874 tree args ATTRIBUTE_UNUSED
,
2875 int flags ATTRIBUTE_UNUSED
,
2878 tree decl
= TYPE_NAME (*node
);
2882 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2883 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2884 *no_add_attrs
= false;
2890 /* Return 0 if the attributes for two types are incompatible, 1 if they
2891 are compatible, and 2 if they are nearly compatible (which causes a
2892 warning to be generated). */
2894 arm_comp_type_attributes (tree type1
, tree type2
)
2898 /* Check for mismatch of non-default calling convention. */
2899 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2902 /* Check for mismatched call attributes. */
2903 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2904 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2905 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2906 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2908 /* Only bother to check if an attribute is defined. */
2909 if (l1
| l2
| s1
| s2
)
2911 /* If one type has an attribute, the other must have the same attribute. */
2912 if ((l1
!= l2
) || (s1
!= s2
))
2915 /* Disallow mixed attributes. */
2916 if ((l1
& s2
) || (l2
& s1
))
2920 /* Check for mismatched ISR attribute. */
2921 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2923 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2924 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2926 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2933 /* Encode long_call or short_call attribute by prefixing
2934 symbol name in DECL with a special character FLAG. */
2936 arm_encode_call_attribute (tree decl
, int flag
)
2938 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2939 int len
= strlen (str
);
2942 /* Do not allow weak functions to be treated as short call. */
2943 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2946 newstr
= alloca (len
+ 2);
2948 strcpy (newstr
+ 1, str
);
2950 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2951 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2954 /* Assigns default attributes to newly defined type. This is used to
2955 set short_call/long_call attributes for function types of
2956 functions defined inside corresponding #pragma scopes. */
2958 arm_set_default_type_attributes (tree type
)
2960 /* Add __attribute__ ((long_call)) to all functions, when
2961 inside #pragma long_calls or __attribute__ ((short_call)),
2962 when inside #pragma no_long_calls. */
2963 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2965 tree type_attr_list
, attr_name
;
2966 type_attr_list
= TYPE_ATTRIBUTES (type
);
2968 if (arm_pragma_long_calls
== LONG
)
2969 attr_name
= get_identifier ("long_call");
2970 else if (arm_pragma_long_calls
== SHORT
)
2971 attr_name
= get_identifier ("short_call");
2975 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2976 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2980 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2981 defined within the current compilation unit. If this cannot be
2982 determined, then 0 is returned. */
2984 current_file_function_operand (rtx sym_ref
)
2986 /* This is a bit of a fib. A function will have a short call flag
2987 applied to its name if it has the short call attribute, or it has
2988 already been defined within the current compilation unit. */
2989 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2992 /* The current function is always defined within the current compilation
2993 unit. If it s a weak definition however, then this may not be the real
2994 definition of the function, and so we have to say no. */
2995 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2996 && !DECL_WEAK (current_function_decl
))
2999 /* We cannot make the determination - default to returning 0. */
3003 /* Return nonzero if a 32 bit "long_call" should be generated for
3004 this call. We generate a long_call if the function:
3006 a. has an __attribute__((long call))
3007 or b. is within the scope of a #pragma long_calls
3008 or c. the -mlong-calls command line switch has been specified
3010 1. -ffunction-sections is in effect
3011 or 2. the current function has __attribute__ ((section))
3012 or 3. the target function has __attribute__ ((section))
3014 However we do not generate a long call if the function:
3016 d. has an __attribute__ ((short_call))
3017 or e. is inside the scope of a #pragma no_long_calls
3018 or f. is defined within the current compilation unit.
3020 This function will be called by C fragments contained in the machine
3021 description file. SYM_REF and CALL_COOKIE correspond to the matched
3022 rtl operands. CALL_SYMBOL is used to distinguish between
3023 two different callers of the function. It is set to 1 in the
3024 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3025 and "call_value" patterns. This is because of the difference in the
3026 SYM_REFs passed by these patterns. */
3028 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3032 if (GET_CODE (sym_ref
) != MEM
)
3035 sym_ref
= XEXP (sym_ref
, 0);
3038 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3041 if (call_cookie
& CALL_SHORT
)
3044 if (TARGET_LONG_CALLS
)
3046 if (flag_function_sections
3047 || DECL_SECTION_NAME (current_function_decl
))
3048 /* c.3 is handled by the definition of the
3049 ARM_DECLARE_FUNCTION_SIZE macro. */
3053 if (current_file_function_operand (sym_ref
))
3056 return (call_cookie
& CALL_LONG
)
3057 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3058 || TARGET_LONG_CALLS
;
3061 /* Return nonzero if it is ok to make a tail-call to DECL. */
3063 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3065 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3067 if (cfun
->machine
->sibcall_blocked
)
3070 /* Never tailcall something for which we have no decl, or if we
3071 are in Thumb mode. */
3072 if (decl
== NULL
|| TARGET_THUMB
)
3075 /* Get the calling method. */
3076 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3077 call_type
= CALL_SHORT
;
3078 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3079 call_type
= CALL_LONG
;
3081 /* Cannot tail-call to long calls, since these are out of range of
3082 a branch instruction. However, if not compiling PIC, we know
3083 we can reach the symbol if it is in this compilation unit. */
3084 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3087 /* If we are interworking and the function is not declared static
3088 then we can't tail-call it unless we know that it exists in this
3089 compilation unit (since it might be a Thumb routine). */
3090 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3093 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3094 if (IS_INTERRUPT (arm_current_func_type ()))
3097 /* Everything else is ok. */
3102 /* Addressing mode support functions. */
3104 /* Return nonzero if X is a legitimate immediate operand when compiling
3107 legitimate_pic_operand_p (rtx x
)
3111 && (GET_CODE (x
) == SYMBOL_REF
3112 || (GET_CODE (x
) == CONST
3113 && GET_CODE (XEXP (x
, 0)) == PLUS
3114 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
3121 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3123 if (GET_CODE (orig
) == SYMBOL_REF
3124 || GET_CODE (orig
) == LABEL_REF
)
3126 #ifndef AOF_ASSEMBLER
3127 rtx pic_ref
, address
;
3134 gcc_assert (!no_new_pseudos
);
3135 reg
= gen_reg_rtx (Pmode
);
3140 #ifdef AOF_ASSEMBLER
3141 /* The AOF assembler can generate relocations for these directly, and
3142 understands that the PIC register has to be added into the offset. */
3143 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3146 address
= gen_reg_rtx (Pmode
);
3151 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3153 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3155 if ((GET_CODE (orig
) == LABEL_REF
3156 || (GET_CODE (orig
) == SYMBOL_REF
&&
3157 SYMBOL_REF_LOCAL_P (orig
)))
3159 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
3162 pic_ref
= gen_const_mem (Pmode
,
3163 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3167 insn
= emit_move_insn (reg
, pic_ref
);
3169 current_function_uses_pic_offset_table
= 1;
3170 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3172 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3176 else if (GET_CODE (orig
) == CONST
)
3180 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3181 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3186 gcc_assert (!no_new_pseudos
);
3187 reg
= gen_reg_rtx (Pmode
);
3190 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3192 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3193 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3194 base
== reg
? 0 : reg
);
3196 if (GET_CODE (offset
) == CONST_INT
)
3198 /* The base register doesn't really matter, we only want to
3199 test the index for the appropriate mode. */
3200 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3202 gcc_assert (!no_new_pseudos
);
3203 offset
= force_reg (Pmode
, offset
);
3206 if (GET_CODE (offset
) == CONST_INT
)
3207 return plus_constant (base
, INTVAL (offset
));
3210 if (GET_MODE_SIZE (mode
) > 4
3211 && (GET_MODE_CLASS (mode
) == MODE_INT
3212 || TARGET_SOFT_FLOAT
))
3214 emit_insn (gen_addsi3 (reg
, base
, offset
));
3218 return gen_rtx_PLUS (Pmode
, base
, offset
);
3225 /* Find a spare low register to use during the prolog of a function. */
3228 thumb_find_work_register (unsigned long pushed_regs_mask
)
3232 /* Check the argument registers first as these are call-used. The
3233 register allocation order means that sometimes r3 might be used
3234 but earlier argument registers might not, so check them all. */
3235 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3236 if (!regs_ever_live
[reg
])
3239 /* Before going on to check the call-saved registers we can try a couple
3240 more ways of deducing that r3 is available. The first is when we are
3241 pushing anonymous arguments onto the stack and we have less than 4
3242 registers worth of fixed arguments(*). In this case r3 will be part of
3243 the variable argument list and so we can be sure that it will be
3244 pushed right at the start of the function. Hence it will be available
3245 for the rest of the prologue.
3246 (*): ie current_function_pretend_args_size is greater than 0. */
3247 if (cfun
->machine
->uses_anonymous_args
3248 && current_function_pretend_args_size
> 0)
3249 return LAST_ARG_REGNUM
;
3251 /* The other case is when we have fixed arguments but less than 4 registers
3252 worth. In this case r3 might be used in the body of the function, but
3253 it is not being used to convey an argument into the function. In theory
3254 we could just check current_function_args_size to see how many bytes are
3255 being passed in argument registers, but it seems that it is unreliable.
3256 Sometimes it will have the value 0 when in fact arguments are being
3257 passed. (See testcase execute/20021111-1.c for an example). So we also
3258 check the args_info.nregs field as well. The problem with this field is
3259 that it makes no allowances for arguments that are passed to the
3260 function but which are not used. Hence we could miss an opportunity
3261 when a function has an unused argument in r3. But it is better to be
3262 safe than to be sorry. */
3263 if (! cfun
->machine
->uses_anonymous_args
3264 && current_function_args_size
>= 0
3265 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3266 && cfun
->args_info
.nregs
< 4)
3267 return LAST_ARG_REGNUM
;
3269 /* Otherwise look for a call-saved register that is going to be pushed. */
3270 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3271 if (pushed_regs_mask
& (1 << reg
))
3274 /* Something went wrong - thumb_compute_save_reg_mask()
3275 should have arranged for a suitable register to be pushed. */
3280 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3284 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3286 #ifndef AOF_ASSEMBLER
3287 rtx l1
, pic_tmp
, pic_tmp2
, pic_rtx
;
3288 rtx global_offset_table
;
3290 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3293 gcc_assert (flag_pic
);
3295 l1
= gen_label_rtx ();
3297 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3298 /* On the ARM the PC register contains 'dot + 8' at the time of the
3299 addition, on the Thumb it is 'dot + 4'. */
3300 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
3302 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3303 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3305 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3307 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3311 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3312 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
3316 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3318 /* We will have pushed the pic register, so we should always be
3319 able to find a work register. */
3320 pic_tmp
= gen_rtx_REG (SImode
,
3321 thumb_find_work_register (saved_regs
));
3322 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3323 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3326 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3327 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
3330 /* Need to emit this whether or not we obey regdecls,
3331 since setjmp/longjmp can cause life info to screw up. */
3332 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3333 #endif /* AOF_ASSEMBLER */
3337 /* Return nonzero if X is valid as an ARM state addressing register. */
3339 arm_address_register_rtx_p (rtx x
, int strict_p
)
3343 if (GET_CODE (x
) != REG
)
3349 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3351 return (regno
<= LAST_ARM_REGNUM
3352 || regno
>= FIRST_PSEUDO_REGISTER
3353 || regno
== FRAME_POINTER_REGNUM
3354 || regno
== ARG_POINTER_REGNUM
);
3357 /* Return nonzero if X is a valid ARM state address operand. */
3359 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3363 enum rtx_code code
= GET_CODE (x
);
3365 if (arm_address_register_rtx_p (x
, strict_p
))
3368 use_ldrd
= (TARGET_LDRD
3370 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3372 if (code
== POST_INC
|| code
== PRE_DEC
3373 || ((code
== PRE_INC
|| code
== POST_DEC
)
3374 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3375 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3377 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3378 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3379 && GET_CODE (XEXP (x
, 1)) == PLUS
3380 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3382 rtx addend
= XEXP (XEXP (x
, 1), 1);
3384 /* Don't allow ldrd post increment by register because it's hard
3385 to fixup invalid register choices. */
3387 && GET_CODE (x
) == POST_MODIFY
3388 && GET_CODE (addend
) == REG
)
3391 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3392 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3395 /* After reload constants split into minipools will have addresses
3396 from a LABEL_REF. */
3397 else if (reload_completed
3398 && (code
== LABEL_REF
3400 && GET_CODE (XEXP (x
, 0)) == PLUS
3401 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3402 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3405 else if (mode
== TImode
)
3408 else if (code
== PLUS
)
3410 rtx xop0
= XEXP (x
, 0);
3411 rtx xop1
= XEXP (x
, 1);
3413 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3414 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3415 || (arm_address_register_rtx_p (xop1
, strict_p
)
3416 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3420 /* Reload currently can't handle MINUS, so disable this for now */
3421 else if (GET_CODE (x
) == MINUS
)
3423 rtx xop0
= XEXP (x
, 0);
3424 rtx xop1
= XEXP (x
, 1);
3426 return (arm_address_register_rtx_p (xop0
, strict_p
)
3427 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3431 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3432 && code
== SYMBOL_REF
3433 && CONSTANT_POOL_ADDRESS_P (x
)
3435 && symbol_mentioned_p (get_pool_constant (x
))))
3441 /* Return nonzero if INDEX is valid for an address index operand in
3444 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3447 HOST_WIDE_INT range
;
3448 enum rtx_code code
= GET_CODE (index
);
3450 /* Standard coprocessor addressing modes. */
3451 if (TARGET_HARD_FLOAT
3452 && (TARGET_FPA
|| TARGET_MAVERICK
)
3453 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3454 || (TARGET_MAVERICK
&& mode
== DImode
)))
3455 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3456 && INTVAL (index
) > -1024
3457 && (INTVAL (index
) & 3) == 0);
3459 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3460 return (code
== CONST_INT
3461 && INTVAL (index
) < 1024
3462 && INTVAL (index
) > -1024
3463 && (INTVAL (index
) & 3) == 0);
3465 if (arm_address_register_rtx_p (index
, strict_p
)
3466 && (GET_MODE_SIZE (mode
) <= 4))
3469 if (mode
== DImode
|| mode
== DFmode
)
3471 if (code
== CONST_INT
)
3473 HOST_WIDE_INT val
= INTVAL (index
);
3476 return val
> -256 && val
< 256;
3478 return val
> -4096 && val
< 4092;
3481 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3484 if (GET_MODE_SIZE (mode
) <= 4
3487 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3491 rtx xiop0
= XEXP (index
, 0);
3492 rtx xiop1
= XEXP (index
, 1);
3494 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3495 && power_of_two_operand (xiop1
, SImode
))
3496 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3497 && power_of_two_operand (xiop0
, SImode
)));
3499 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3500 || code
== ASHIFT
|| code
== ROTATERT
)
3502 rtx op
= XEXP (index
, 1);
3504 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3505 && GET_CODE (op
) == CONST_INT
3507 && INTVAL (op
) <= 31);
3511 /* For ARM v4 we may be doing a sign-extend operation during the
3515 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3521 range
= (mode
== HImode
) ? 4095 : 4096;
3523 return (code
== CONST_INT
3524 && INTVAL (index
) < range
3525 && INTVAL (index
) > -range
);
3528 /* Return nonzero if X is valid as a Thumb state base register. */
3530 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3534 if (GET_CODE (x
) != REG
)
3540 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3542 return (regno
<= LAST_LO_REGNUM
3543 || regno
> LAST_VIRTUAL_REGISTER
3544 || regno
== FRAME_POINTER_REGNUM
3545 || (GET_MODE_SIZE (mode
) >= 4
3546 && (regno
== STACK_POINTER_REGNUM
3547 || regno
>= FIRST_PSEUDO_REGISTER
3548 || x
== hard_frame_pointer_rtx
3549 || x
== arg_pointer_rtx
)));
3552 /* Return nonzero if x is a legitimate index register. This is the case
3553 for any base register that can access a QImode object. */
3555 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3557 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3560 /* Return nonzero if x is a legitimate Thumb-state address.
3562 The AP may be eliminated to either the SP or the FP, so we use the
3563 least common denominator, e.g. SImode, and offsets from 0 to 64.
3565 ??? Verify whether the above is the right approach.
3567 ??? Also, the FP may be eliminated to the SP, so perhaps that
3568 needs special handling also.
3570 ??? Look at how the mips16 port solves this problem. It probably uses
3571 better ways to solve some of these problems.
3573 Although it is not incorrect, we don't accept QImode and HImode
3574 addresses based on the frame pointer or arg pointer until the
3575 reload pass starts. This is so that eliminating such addresses
3576 into stack based ones won't produce impossible code. */
3578 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3580 /* ??? Not clear if this is right. Experiment. */
3581 if (GET_MODE_SIZE (mode
) < 4
3582 && !(reload_in_progress
|| reload_completed
)
3583 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3584 || reg_mentioned_p (arg_pointer_rtx
, x
)
3585 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3586 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3587 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3588 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3591 /* Accept any base register. SP only in SImode or larger. */
3592 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3595 /* This is PC relative data before arm_reorg runs. */
3596 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3597 && GET_CODE (x
) == SYMBOL_REF
3598 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3601 /* This is PC relative data after arm_reorg runs. */
3602 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3603 && (GET_CODE (x
) == LABEL_REF
3604 || (GET_CODE (x
) == CONST
3605 && GET_CODE (XEXP (x
, 0)) == PLUS
3606 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3607 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3610 /* Post-inc indexing only supported for SImode and larger. */
3611 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3612 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3615 else if (GET_CODE (x
) == PLUS
)
3617 /* REG+REG address can be any two index registers. */
3618 /* We disallow FRAME+REG addressing since we know that FRAME
3619 will be replaced with STACK, and SP relative addressing only
3620 permits SP+OFFSET. */
3621 if (GET_MODE_SIZE (mode
) <= 4
3622 && XEXP (x
, 0) != frame_pointer_rtx
3623 && XEXP (x
, 1) != frame_pointer_rtx
3624 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3625 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3628 /* REG+const has 5-7 bit offset for non-SP registers. */
3629 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3630 || XEXP (x
, 0) == arg_pointer_rtx
)
3631 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3632 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3635 /* REG+const has 10 bit offset for SP, but only SImode and
3636 larger is supported. */
3637 /* ??? Should probably check for DI/DFmode overflow here
3638 just like GO_IF_LEGITIMATE_OFFSET does. */
3639 else if (GET_CODE (XEXP (x
, 0)) == REG
3640 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3641 && GET_MODE_SIZE (mode
) >= 4
3642 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3643 && INTVAL (XEXP (x
, 1)) >= 0
3644 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3645 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3648 else if (GET_CODE (XEXP (x
, 0)) == REG
3649 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3650 && GET_MODE_SIZE (mode
) >= 4
3651 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3652 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3656 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3657 && GET_MODE_SIZE (mode
) == 4
3658 && GET_CODE (x
) == SYMBOL_REF
3659 && CONSTANT_POOL_ADDRESS_P (x
)
3661 && symbol_mentioned_p (get_pool_constant (x
))))
3667 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3668 instruction of mode MODE. */
3670 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3672 switch (GET_MODE_SIZE (mode
))
3675 return val
>= 0 && val
< 32;
3678 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3682 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3687 /* Try machine-dependent ways of modifying an illegitimate address
3688 to be legitimate. If we find one, return the new, valid address. */
3690 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3692 if (GET_CODE (x
) == PLUS
)
3694 rtx xop0
= XEXP (x
, 0);
3695 rtx xop1
= XEXP (x
, 1);
3697 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3698 xop0
= force_reg (SImode
, xop0
);
3700 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3701 xop1
= force_reg (SImode
, xop1
);
3703 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3704 && GET_CODE (xop1
) == CONST_INT
)
3706 HOST_WIDE_INT n
, low_n
;
3710 /* VFP addressing modes actually allow greater offsets, but for
3711 now we just stick with the lowest common denominator. */
3713 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3725 low_n
= ((mode
) == TImode
? 0
3726 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3730 base_reg
= gen_reg_rtx (SImode
);
3731 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3732 GEN_INT (n
)), NULL_RTX
);
3733 emit_move_insn (base_reg
, val
);
3734 x
= (low_n
== 0 ? base_reg
3735 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3737 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3738 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3741 /* XXX We don't allow MINUS any more -- see comment in
3742 arm_legitimate_address_p (). */
3743 else if (GET_CODE (x
) == MINUS
)
3745 rtx xop0
= XEXP (x
, 0);
3746 rtx xop1
= XEXP (x
, 1);
3748 if (CONSTANT_P (xop0
))
3749 xop0
= force_reg (SImode
, xop0
);
3751 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3752 xop1
= force_reg (SImode
, xop1
);
3754 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3755 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3758 /* Make sure to take full advantage of the pre-indexed addressing mode
3759 with absolute addresses which often allows for the base register to
3760 be factorized for multiple adjacent memory references, and it might
3761 even allows for the mini pool to be avoided entirely. */
3762 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
3765 HOST_WIDE_INT mask
, base
, index
;
3768 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
3769 use a 8 bit index. So let's use a 12 bit index for SImode only and
3770 hope that arm_gen_constant will enable ldrb to use more bits. */
3771 bits
= (mode
== SImode
) ? 12 : 8;
3772 mask
= (1 << bits
) - 1;
3773 base
= INTVAL (x
) & ~mask
;
3774 index
= INTVAL (x
) & mask
;
3775 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
3777 /* It'll most probably be more efficient to generate the base
3778 with more bits set and use a negative index instead. */
3782 base_reg
= force_reg (SImode
, GEN_INT (base
));
3783 x
= gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (index
));
3788 /* We need to find and carefully transform any SYMBOL and LABEL
3789 references; so go back to the original address expression. */
3790 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3792 if (new_x
!= orig_x
)
3800 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3801 to be legitimate. If we find one, return the new, valid address. */
3803 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3805 if (GET_CODE (x
) == PLUS
3806 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3807 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
3808 || INTVAL (XEXP (x
, 1)) < 0))
3810 rtx xop0
= XEXP (x
, 0);
3811 rtx xop1
= XEXP (x
, 1);
3812 HOST_WIDE_INT offset
= INTVAL (xop1
);
3814 /* Try and fold the offset into a biasing of the base register and
3815 then offsetting that. Don't do this when optimizing for space
3816 since it can cause too many CSEs. */
3817 if (optimize_size
&& offset
>= 0
3818 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
3820 HOST_WIDE_INT delta
;
3823 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
3824 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
3825 delta
= 31 * GET_MODE_SIZE (mode
);
3827 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
3829 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
3831 x
= plus_constant (xop0
, delta
);
3833 else if (offset
< 0 && offset
> -256)
3834 /* Small negative offsets are best done with a subtract before the
3835 dereference, forcing these into a register normally takes two
3837 x
= force_operand (x
, NULL_RTX
);
3840 /* For the remaining cases, force the constant into a register. */
3841 xop1
= force_reg (SImode
, xop1
);
3842 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3845 else if (GET_CODE (x
) == PLUS
3846 && s_register_operand (XEXP (x
, 1), SImode
)
3847 && !s_register_operand (XEXP (x
, 0), SImode
))
3849 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
3851 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
3856 /* We need to find and carefully transform any SYMBOL and LABEL
3857 references; so go back to the original address expression. */
3858 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3860 if (new_x
!= orig_x
)
3868 thumb_legitimize_reload_address(rtx
*x_p
,
3869 enum machine_mode mode
,
3870 int opnum
, int type
,
3871 int ind_levels ATTRIBUTE_UNUSED
)
3875 if (GET_CODE (x
) == PLUS
3876 && GET_MODE_SIZE (mode
) < 4
3877 && REG_P (XEXP (x
, 0))
3878 && XEXP (x
, 0) == stack_pointer_rtx
3879 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3880 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3885 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
3886 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
3890 /* If both registers are hi-regs, then it's better to reload the
3891 entire expression rather than each register individually. That
3892 only requires one reload register rather than two. */
3893 if (GET_CODE (x
) == PLUS
3894 && REG_P (XEXP (x
, 0))
3895 && REG_P (XEXP (x
, 1))
3896 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
3897 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
3902 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
3903 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
3912 #define REG_OR_SUBREG_REG(X) \
3913 (GET_CODE (X) == REG \
3914 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3916 #define REG_OR_SUBREG_RTX(X) \
3917 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3919 #ifndef COSTS_N_INSNS
3920 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3923 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3925 enum machine_mode mode
= GET_MODE (x
);
3938 return COSTS_N_INSNS (1);
3941 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3944 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3951 return COSTS_N_INSNS (2) + cycles
;
3953 return COSTS_N_INSNS (1) + 16;
3956 return (COSTS_N_INSNS (1)
3957 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3958 + GET_CODE (SET_DEST (x
)) == MEM
));
3963 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3965 if (thumb_shiftable_const (INTVAL (x
)))
3966 return COSTS_N_INSNS (2);
3967 return COSTS_N_INSNS (3);
3969 else if ((outer
== PLUS
|| outer
== COMPARE
)
3970 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3972 else if (outer
== AND
3973 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3974 return COSTS_N_INSNS (1);
3975 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3976 || outer
== LSHIFTRT
)
3978 return COSTS_N_INSNS (2);
3984 return COSTS_N_INSNS (3);
4002 /* XXX another guess. */
4003 /* Memory costs quite a lot for the first word, but subsequent words
4004 load at the equivalent of a single insn each. */
4005 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4006 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4011 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4016 /* XXX still guessing. */
4017 switch (GET_MODE (XEXP (x
, 0)))
4020 return (1 + (mode
== DImode
? 4 : 0)
4021 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4024 return (4 + (mode
== DImode
? 4 : 0)
4025 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4028 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4040 /* Worker routine for arm_rtx_costs. */
4042 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4044 enum machine_mode mode
= GET_MODE (x
);
4045 enum rtx_code subcode
;
4051 /* Memory costs quite a lot for the first word, but subsequent words
4052 load at the equivalent of a single insn each. */
4053 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4054 + (GET_CODE (x
) == SYMBOL_REF
4055 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4061 return optimize_size
? COSTS_N_INSNS (2) : 100;
4064 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4071 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4073 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4074 + ((GET_CODE (XEXP (x
, 0)) == REG
4075 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4076 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4078 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4079 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4080 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4082 + ((GET_CODE (XEXP (x
, 1)) == REG
4083 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4084 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4085 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4090 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4091 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4092 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4093 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4096 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4097 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4098 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4099 && arm_const_double_rtx (XEXP (x
, 1))))
4101 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4102 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4103 && arm_const_double_rtx (XEXP (x
, 0))))
4106 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4107 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4108 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4109 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4110 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4111 || subcode
== ROTATE
|| subcode
== ROTATERT
4113 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4114 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4115 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4116 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4117 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4118 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4119 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4124 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4125 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4126 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4127 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4128 && arm_const_double_rtx (XEXP (x
, 1))))
4132 case AND
: case XOR
: case IOR
:
4135 /* Normally the frame registers will be spilt into reg+const during
4136 reload, so it is a bad idea to combine them with other instructions,
4137 since then they might not be moved outside of loops. As a compromise
4138 we allow integration with ops that have a constant as their second
4140 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4141 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4142 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4143 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4144 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4148 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4149 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4150 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4151 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4154 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4155 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4156 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4157 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4158 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4161 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4162 return (1 + extra_cost
4163 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4164 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4165 || subcode
== ROTATE
|| subcode
== ROTATERT
4167 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4168 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4169 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4170 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4171 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4172 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4178 /* This should have been handled by the CPU specific routines. */
4182 if (arm_arch3m
&& mode
== SImode
4183 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4184 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4185 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4186 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4187 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4188 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4193 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4194 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4198 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4200 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4203 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4211 return 4 + (mode
== DImode
? 4 : 0);
4214 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4215 return (4 + (mode
== DImode
? 4 : 0)
4216 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4219 switch (GET_MODE (XEXP (x
, 0)))
4222 return (1 + (mode
== DImode
? 4 : 0)
4223 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4226 return (4 + (mode
== DImode
? 4 : 0)
4227 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4230 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4245 if (const_ok_for_arm (INTVAL (x
)))
4246 return outer
== SET
? 2 : -1;
4247 else if (outer
== AND
4248 && const_ok_for_arm (~INTVAL (x
)))
4250 else if ((outer
== COMPARE
4251 || outer
== PLUS
|| outer
== MINUS
)
4252 && const_ok_for_arm (-INTVAL (x
)))
4263 if (arm_const_double_rtx (x
))
4264 return outer
== SET
? 2 : -1;
4265 else if ((outer
== COMPARE
|| outer
== PLUS
)
4266 && neg_const_double_rtx_ok_for_fpa (x
))
4275 /* RTX costs when optimizing for size. */
4277 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4279 enum machine_mode mode
= GET_MODE (x
);
4283 /* XXX TBD. For now, use the standard costs. */
4284 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4291 /* A memory access costs 1 insn if the mode is small, or the address is
4292 a single register, otherwise it costs one insn per word. */
4293 if (REG_P (XEXP (x
, 0)))
4294 *total
= COSTS_N_INSNS (1);
4296 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4303 /* Needs a libcall, so it costs about this. */
4304 *total
= COSTS_N_INSNS (2);
4308 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4310 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4318 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4320 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4323 else if (mode
== SImode
)
4325 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4326 /* Slightly disparage register shifts, but not by much. */
4327 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4328 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4332 /* Needs a libcall. */
4333 *total
= COSTS_N_INSNS (2);
4337 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4339 *total
= COSTS_N_INSNS (1);
4345 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4346 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4348 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4349 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4350 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4351 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4352 || subcode1
== ASHIFTRT
)
4354 /* It's just the cost of the two operands. */
4359 *total
= COSTS_N_INSNS (1);
4363 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4367 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4369 *total
= COSTS_N_INSNS (1);
4374 case AND
: case XOR
: case IOR
:
4377 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4379 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4380 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4381 || (code
== AND
&& subcode
== NOT
))
4383 /* It's just the cost of the two operands. */
4389 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4393 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4397 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4398 *total
= COSTS_N_INSNS (1);
4401 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4410 if (cc_register (XEXP (x
, 0), VOIDmode
))
4413 *total
= COSTS_N_INSNS (1);
4417 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4418 *total
= COSTS_N_INSNS (1);
4420 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4425 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4427 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4428 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4431 *total
+= COSTS_N_INSNS (1);
4436 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4438 switch (GET_MODE (XEXP (x
, 0)))
4441 *total
+= COSTS_N_INSNS (1);
4445 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4451 *total
+= COSTS_N_INSNS (2);
4456 *total
+= COSTS_N_INSNS (1);
4461 if (const_ok_for_arm (INTVAL (x
)))
4462 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4463 else if (const_ok_for_arm (~INTVAL (x
)))
4464 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4465 else if (const_ok_for_arm (-INTVAL (x
)))
4467 if (outer_code
== COMPARE
|| outer_code
== PLUS
4468 || outer_code
== MINUS
)
4471 *total
= COSTS_N_INSNS (1);
4474 *total
= COSTS_N_INSNS (2);
4480 *total
= COSTS_N_INSNS (2);
4484 *total
= COSTS_N_INSNS (4);
4488 if (mode
!= VOIDmode
)
4489 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4491 *total
= COSTS_N_INSNS (4); /* How knows? */
4496 /* RTX costs for cores with a slow MUL implementation. */
4499 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4501 enum machine_mode mode
= GET_MODE (x
);
4505 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4512 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4519 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4521 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4522 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4523 int cost
, const_ok
= const_ok_for_arm (i
);
4524 int j
, booth_unit_size
;
4526 /* Tune as appropriate. */
4527 cost
= const_ok
? 4 : 8;
4528 booth_unit_size
= 2;
4529 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4531 i
>>= booth_unit_size
;
4539 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4540 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4544 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4550 /* RTX cost for cores with a fast multiply unit (M variants). */
4553 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4555 enum machine_mode mode
= GET_MODE (x
);
4559 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4566 /* There is no point basing this on the tuning, since it is always the
4567 fast variant if it exists at all. */
4569 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4570 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4571 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4578 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4585 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4587 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4588 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4589 int cost
, const_ok
= const_ok_for_arm (i
);
4590 int j
, booth_unit_size
;
4592 /* Tune as appropriate. */
4593 cost
= const_ok
? 4 : 8;
4594 booth_unit_size
= 8;
4595 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4597 i
>>= booth_unit_size
;
4605 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4606 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4610 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4616 /* RTX cost for XScale CPUs. */
4619 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4621 enum machine_mode mode
= GET_MODE (x
);
4625 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4632 /* There is no point basing this on the tuning, since it is always the
4633 fast variant if it exists at all. */
4635 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4636 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4637 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4644 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4651 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4653 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4654 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4655 int cost
, const_ok
= const_ok_for_arm (i
);
4656 unsigned HOST_WIDE_INT masked_const
;
4658 /* The cost will be related to two insns.
4659 First a load of the constant (MOV or LDR), then a multiply. */
4662 cost
+= 1; /* LDR is probably more expensive because
4663 of longer result latency. */
4664 masked_const
= i
& 0xffff8000;
4665 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4667 masked_const
= i
& 0xf8000000;
4668 if (masked_const
== 0 || masked_const
== 0xf8000000)
4677 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4678 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4682 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4683 will stall until the multiplication is complete. */
4684 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4685 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
4687 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4691 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4697 /* RTX costs for 9e (and later) cores. */
4700 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4702 enum machine_mode mode
= GET_MODE (x
);
4711 *total
= COSTS_N_INSNS (3);
4715 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4723 /* There is no point basing this on the tuning, since it is always the
4724 fast variant if it exists at all. */
4726 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4727 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4728 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4735 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4752 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
4753 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
4757 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4761 /* All address computations that can be done are free, but rtx cost returns
4762 the same for practically all of them. So we weight the different types
4763 of address here in the order (most pref first):
4764 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4766 arm_arm_address_cost (rtx x
)
4768 enum rtx_code c
= GET_CODE (x
);
4770 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
4772 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
4775 if (c
== PLUS
|| c
== MINUS
)
4777 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4780 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
4790 arm_thumb_address_cost (rtx x
)
4792 enum rtx_code c
= GET_CODE (x
);
4797 && GET_CODE (XEXP (x
, 0)) == REG
4798 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4805 arm_address_cost (rtx x
)
4807 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
4811 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
4815 /* Some true dependencies can have a higher cost depending
4816 on precisely how certain input operands are used. */
4818 && REG_NOTE_KIND (link
) == 0
4819 && recog_memoized (insn
) >= 0
4820 && recog_memoized (dep
) >= 0)
4822 int shift_opnum
= get_attr_shift (insn
);
4823 enum attr_type attr_type
= get_attr_type (dep
);
4825 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4826 operand for INSN. If we have a shifted input operand and the
4827 instruction we depend on is another ALU instruction, then we may
4828 have to account for an additional stall. */
4829 if (shift_opnum
!= 0
4830 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
4832 rtx shifted_operand
;
4835 /* Get the shifted operand. */
4836 extract_insn (insn
);
4837 shifted_operand
= recog_data
.operand
[shift_opnum
];
4839 /* Iterate over all the operands in DEP. If we write an operand
4840 that overlaps with SHIFTED_OPERAND, then we have increase the
4841 cost of this dependency. */
4843 preprocess_constraints ();
4844 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4846 /* We can ignore strict inputs. */
4847 if (recog_data
.operand_type
[opno
] == OP_IN
)
4850 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
4857 /* XXX This is not strictly true for the FPA. */
4858 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
4859 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4862 /* Call insns don't incur a stall, even if they follow a load. */
4863 if (REG_NOTE_KIND (link
) == 0
4864 && GET_CODE (insn
) == CALL_INSN
)
4867 if ((i_pat
= single_set (insn
)) != NULL
4868 && GET_CODE (SET_SRC (i_pat
)) == MEM
4869 && (d_pat
= single_set (dep
)) != NULL
4870 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
4872 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
4873 /* This is a load after a store, there is no conflict if the load reads
4874 from a cached area. Assume that loads from the stack, and from the
4875 constant pool are cached, and that others will miss. This is a
4878 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
4879 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
4880 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
4881 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
4888 static int fp_consts_inited
= 0;
4890 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4891 static const char * const strings_fp
[8] =
4894 "4", "5", "0.5", "10"
4897 static REAL_VALUE_TYPE values_fp
[8];
4900 init_fp_table (void)
4906 fp_consts_inited
= 1;
4908 fp_consts_inited
= 8;
4910 for (i
= 0; i
< fp_consts_inited
; i
++)
4912 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
4917 /* Return TRUE if rtx X is a valid immediate FP constant. */
4919 arm_const_double_rtx (rtx x
)
4924 if (!fp_consts_inited
)
4927 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4928 if (REAL_VALUE_MINUS_ZERO (r
))
4931 for (i
= 0; i
< fp_consts_inited
; i
++)
4932 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4938 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4940 neg_const_double_rtx_ok_for_fpa (rtx x
)
4945 if (!fp_consts_inited
)
4948 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4949 r
= REAL_VALUE_NEGATE (r
);
4950 if (REAL_VALUE_MINUS_ZERO (r
))
4953 for (i
= 0; i
< 8; i
++)
4954 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4960 /* Predicates for `match_operand' and `match_operator'. */
4962 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4964 cirrus_memory_offset (rtx op
)
4966 /* Reject eliminable registers. */
4967 if (! (reload_in_progress
|| reload_completed
)
4968 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4969 || reg_mentioned_p (arg_pointer_rtx
, op
)
4970 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4971 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4972 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4973 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4976 if (GET_CODE (op
) == MEM
)
4982 /* Match: (mem (reg)). */
4983 if (GET_CODE (ind
) == REG
)
4989 if (GET_CODE (ind
) == PLUS
4990 && GET_CODE (XEXP (ind
, 0)) == REG
4991 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4992 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4999 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5000 WB if true if writeback address modes are allowed. */
5003 arm_coproc_mem_operand (rtx op
, bool wb
)
5007 /* Reject eliminable registers. */
5008 if (! (reload_in_progress
|| reload_completed
)
5009 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5010 || reg_mentioned_p (arg_pointer_rtx
, op
)
5011 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5012 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5013 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5014 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5017 /* Constants are converted into offsets from labels. */
5018 if (GET_CODE (op
) != MEM
)
5023 if (reload_completed
5024 && (GET_CODE (ind
) == LABEL_REF
5025 || (GET_CODE (ind
) == CONST
5026 && GET_CODE (XEXP (ind
, 0)) == PLUS
5027 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5028 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5031 /* Match: (mem (reg)). */
5032 if (GET_CODE (ind
) == REG
)
5033 return arm_address_register_rtx_p (ind
, 0);
5035 /* Autoincremment addressing modes. */
5037 && (GET_CODE (ind
) == PRE_INC
5038 || GET_CODE (ind
) == POST_INC
5039 || GET_CODE (ind
) == PRE_DEC
5040 || GET_CODE (ind
) == POST_DEC
))
5041 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5044 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5045 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5046 && GET_CODE (XEXP (ind
, 1)) == PLUS
5047 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5048 ind
= XEXP (ind
, 1);
5053 if (GET_CODE (ind
) == PLUS
5054 && GET_CODE (XEXP (ind
, 0)) == REG
5055 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5056 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5057 && INTVAL (XEXP (ind
, 1)) > -1024
5058 && INTVAL (XEXP (ind
, 1)) < 1024
5059 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5065 /* Return true if X is a register that will be eliminated later on. */
5067 arm_eliminable_register (rtx x
)
5069 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5070 || REGNO (x
) == ARG_POINTER_REGNUM
5071 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5072 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5075 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5076 VFP registers. Otherwise return NO_REGS. */
5079 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5081 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5084 return GENERAL_REGS
;
5087 /* Values which must be returned in the most-significant end of the return
5091 arm_return_in_msb (tree valtype
)
5093 return (TARGET_AAPCS_BASED
5095 && (AGGREGATE_TYPE_P (valtype
)
5096 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5099 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5100 Use by the Cirrus Maverick code which has to workaround
5101 a hardware bug triggered by such instructions. */
5103 arm_memory_load_p (rtx insn
)
5105 rtx body
, lhs
, rhs
;;
5107 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5110 body
= PATTERN (insn
);
5112 if (GET_CODE (body
) != SET
)
5115 lhs
= XEXP (body
, 0);
5116 rhs
= XEXP (body
, 1);
5118 lhs
= REG_OR_SUBREG_RTX (lhs
);
5120 /* If the destination is not a general purpose
5121 register we do not have to worry. */
5122 if (GET_CODE (lhs
) != REG
5123 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5126 /* As well as loads from memory we also have to react
5127 to loads of invalid constants which will be turned
5128 into loads from the minipool. */
5129 return (GET_CODE (rhs
) == MEM
5130 || GET_CODE (rhs
) == SYMBOL_REF
5131 || note_invalid_constants (insn
, -1, false));
5134 /* Return TRUE if INSN is a Cirrus instruction. */
5136 arm_cirrus_insn_p (rtx insn
)
5138 enum attr_cirrus attr
;
5140 /* get_attr cannot accept USE or CLOBBER. */
5142 || GET_CODE (insn
) != INSN
5143 || GET_CODE (PATTERN (insn
)) == USE
5144 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5147 attr
= get_attr_cirrus (insn
);
5149 return attr
!= CIRRUS_NOT
;
5152 /* Cirrus reorg for invalid instruction combinations. */
5154 cirrus_reorg (rtx first
)
5156 enum attr_cirrus attr
;
5157 rtx body
= PATTERN (first
);
5161 /* Any branch must be followed by 2 non Cirrus instructions. */
5162 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5165 t
= next_nonnote_insn (first
);
5167 if (arm_cirrus_insn_p (t
))
5170 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5174 emit_insn_after (gen_nop (), first
);
5179 /* (float (blah)) is in parallel with a clobber. */
5180 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5181 body
= XVECEXP (body
, 0, 0);
5183 if (GET_CODE (body
) == SET
)
5185 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5187 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5188 be followed by a non Cirrus insn. */
5189 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5191 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5192 emit_insn_after (gen_nop (), first
);
5196 else if (arm_memory_load_p (first
))
5198 unsigned int arm_regno
;
5200 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5201 ldr/cfmv64hr combination where the Rd field is the same
5202 in both instructions must be split with a non Cirrus
5209 /* Get Arm register number for ldr insn. */
5210 if (GET_CODE (lhs
) == REG
)
5211 arm_regno
= REGNO (lhs
);
5214 gcc_assert (GET_CODE (rhs
) == REG
);
5215 arm_regno
= REGNO (rhs
);
5219 first
= next_nonnote_insn (first
);
5221 if (! arm_cirrus_insn_p (first
))
5224 body
= PATTERN (first
);
5226 /* (float (blah)) is in parallel with a clobber. */
5227 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5228 body
= XVECEXP (body
, 0, 0);
5230 if (GET_CODE (body
) == FLOAT
)
5231 body
= XEXP (body
, 0);
5233 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5234 && GET_CODE (XEXP (body
, 1)) == REG
5235 && arm_regno
== REGNO (XEXP (body
, 1)))
5236 emit_insn_after (gen_nop (), first
);
5242 /* get_attr cannot accept USE or CLOBBER. */
5244 || GET_CODE (first
) != INSN
5245 || GET_CODE (PATTERN (first
)) == USE
5246 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5249 attr
= get_attr_cirrus (first
);
5251 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5252 must be followed by a non-coprocessor instruction. */
5253 if (attr
== CIRRUS_COMPARE
)
5257 t
= next_nonnote_insn (first
);
5259 if (arm_cirrus_insn_p (t
))
5262 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5266 emit_insn_after (gen_nop (), first
);
5272 /* Return TRUE if X references a SYMBOL_REF. */
5274 symbol_mentioned_p (rtx x
)
5279 if (GET_CODE (x
) == SYMBOL_REF
)
5282 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5284 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5290 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5291 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5294 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5301 /* Return TRUE if X references a LABEL_REF. */
5303 label_mentioned_p (rtx x
)
5308 if (GET_CODE (x
) == LABEL_REF
)
5311 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5312 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5318 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5319 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5322 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5332 enum rtx_code code
= GET_CODE (x
);
5349 /* Return 1 if memory locations are adjacent. */
5351 adjacent_mem_locations (rtx a
, rtx b
)
5353 /* We don't guarantee to preserve the order of these memory refs. */
5354 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5357 if ((GET_CODE (XEXP (a
, 0)) == REG
5358 || (GET_CODE (XEXP (a
, 0)) == PLUS
5359 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5360 && (GET_CODE (XEXP (b
, 0)) == REG
5361 || (GET_CODE (XEXP (b
, 0)) == PLUS
5362 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5364 HOST_WIDE_INT val0
= 0, val1
= 0;
5368 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5370 reg0
= XEXP (XEXP (a
, 0), 0);
5371 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5376 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5378 reg1
= XEXP (XEXP (b
, 0), 0);
5379 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5384 /* Don't accept any offset that will require multiple
5385 instructions to handle, since this would cause the
5386 arith_adjacentmem pattern to output an overlong sequence. */
5387 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5390 /* Don't allow an eliminable register: register elimination can make
5391 the offset too large. */
5392 if (arm_eliminable_register (reg0
))
5395 val_diff
= val1
- val0
;
5399 /* If the target has load delay slots, then there's no benefit
5400 to using an ldm instruction unless the offset is zero and
5401 we are optimizing for size. */
5402 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5403 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5404 && (val_diff
== 4 || val_diff
== -4));
5407 return ((REGNO (reg0
) == REGNO (reg1
))
5408 && (val_diff
== 4 || val_diff
== -4));
5415 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5416 HOST_WIDE_INT
*load_offset
)
5418 int unsorted_regs
[4];
5419 HOST_WIDE_INT unsorted_offsets
[4];
5424 /* Can only handle 2, 3, or 4 insns at present,
5425 though could be easily extended if required. */
5426 gcc_assert (nops
>= 2 && nops
<= 4);
5428 /* Loop over the operands and check that the memory references are
5429 suitable (i.e. immediate offsets from the same base register). At
5430 the same time, extract the target register, and the memory
5432 for (i
= 0; i
< nops
; i
++)
5437 /* Convert a subreg of a mem into the mem itself. */
5438 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5439 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5441 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5443 /* Don't reorder volatile memory references; it doesn't seem worth
5444 looking for the case where the order is ok anyway. */
5445 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5448 offset
= const0_rtx
;
5450 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5451 || (GET_CODE (reg
) == SUBREG
5452 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5453 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5454 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5456 || (GET_CODE (reg
) == SUBREG
5457 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5458 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5463 base_reg
= REGNO (reg
);
5464 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5465 ? REGNO (operands
[i
])
5466 : REGNO (SUBREG_REG (operands
[i
])));
5471 if (base_reg
!= (int) REGNO (reg
))
5472 /* Not addressed from the same base register. */
5475 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5476 ? REGNO (operands
[i
])
5477 : REGNO (SUBREG_REG (operands
[i
])));
5478 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5482 /* If it isn't an integer register, or if it overwrites the
5483 base register but isn't the last insn in the list, then
5484 we can't do this. */
5485 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5486 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5489 unsorted_offsets
[i
] = INTVAL (offset
);
5492 /* Not a suitable memory address. */
5496 /* All the useful information has now been extracted from the
5497 operands into unsorted_regs and unsorted_offsets; additionally,
5498 order[0] has been set to the lowest numbered register in the
5499 list. Sort the registers into order, and check that the memory
5500 offsets are ascending and adjacent. */
5502 for (i
= 1; i
< nops
; i
++)
5506 order
[i
] = order
[i
- 1];
5507 for (j
= 0; j
< nops
; j
++)
5508 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5509 && (order
[i
] == order
[i
- 1]
5510 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5513 /* Have we found a suitable register? if not, one must be used more
5515 if (order
[i
] == order
[i
- 1])
5518 /* Is the memory address adjacent and ascending? */
5519 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5527 for (i
= 0; i
< nops
; i
++)
5528 regs
[i
] = unsorted_regs
[order
[i
]];
5530 *load_offset
= unsorted_offsets
[order
[0]];
5533 if (unsorted_offsets
[order
[0]] == 0)
5534 return 1; /* ldmia */
5536 if (unsorted_offsets
[order
[0]] == 4)
5537 return 2; /* ldmib */
5539 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5540 return 3; /* ldmda */
5542 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5543 return 4; /* ldmdb */
5545 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5546 if the offset isn't small enough. The reason 2 ldrs are faster
5547 is because these ARMs are able to do more than one cache access
5548 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5549 whilst the ARM8 has a double bandwidth cache. This means that
5550 these cores can do both an instruction fetch and a data fetch in
5551 a single cycle, so the trick of calculating the address into a
5552 scratch register (one of the result regs) and then doing a load
5553 multiple actually becomes slower (and no smaller in code size).
5554 That is the transformation
5556 ldr rd1, [rbase + offset]
5557 ldr rd2, [rbase + offset + 4]
5561 add rd1, rbase, offset
5562 ldmia rd1, {rd1, rd2}
5564 produces worse code -- '3 cycles + any stalls on rd2' instead of
5565 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5566 access per cycle, the first sequence could never complete in less
5567 than 6 cycles, whereas the ldm sequence would only take 5 and
5568 would make better use of sequential accesses if not hitting the
5571 We cheat here and test 'arm_ld_sched' which we currently know to
5572 only be true for the ARM8, ARM9 and StrongARM. If this ever
5573 changes, then the test below needs to be reworked. */
5574 if (nops
== 2 && arm_ld_sched
)
5577 /* Can't do it without setting up the offset, only do this if it takes
5578 no more than one insn. */
5579 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5580 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5584 emit_ldm_seq (rtx
*operands
, int nops
)
5588 HOST_WIDE_INT offset
;
5592 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5595 strcpy (buf
, "ldm%?ia\t");
5599 strcpy (buf
, "ldm%?ib\t");
5603 strcpy (buf
, "ldm%?da\t");
5607 strcpy (buf
, "ldm%?db\t");
5612 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5613 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5616 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5617 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5619 output_asm_insn (buf
, operands
);
5621 strcpy (buf
, "ldm%?ia\t");
5628 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5629 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5631 for (i
= 1; i
< nops
; i
++)
5632 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5633 reg_names
[regs
[i
]]);
5635 strcat (buf
, "}\t%@ phole ldm");
5637 output_asm_insn (buf
, operands
);
5642 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5643 HOST_WIDE_INT
* load_offset
)
5645 int unsorted_regs
[4];
5646 HOST_WIDE_INT unsorted_offsets
[4];
5651 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5652 extended if required. */
5653 gcc_assert (nops
>= 2 && nops
<= 4);
5655 /* Loop over the operands and check that the memory references are
5656 suitable (i.e. immediate offsets from the same base register). At
5657 the same time, extract the target register, and the memory
5659 for (i
= 0; i
< nops
; i
++)
5664 /* Convert a subreg of a mem into the mem itself. */
5665 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5666 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5668 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5670 /* Don't reorder volatile memory references; it doesn't seem worth
5671 looking for the case where the order is ok anyway. */
5672 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5675 offset
= const0_rtx
;
5677 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5678 || (GET_CODE (reg
) == SUBREG
5679 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5680 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5681 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5683 || (GET_CODE (reg
) == SUBREG
5684 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5685 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5690 base_reg
= REGNO (reg
);
5691 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5692 ? REGNO (operands
[i
])
5693 : REGNO (SUBREG_REG (operands
[i
])));
5698 if (base_reg
!= (int) REGNO (reg
))
5699 /* Not addressed from the same base register. */
5702 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5703 ? REGNO (operands
[i
])
5704 : REGNO (SUBREG_REG (operands
[i
])));
5705 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5709 /* If it isn't an integer register, then we can't do this. */
5710 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5713 unsorted_offsets
[i
] = INTVAL (offset
);
5716 /* Not a suitable memory address. */
5720 /* All the useful information has now been extracted from the
5721 operands into unsorted_regs and unsorted_offsets; additionally,
5722 order[0] has been set to the lowest numbered register in the
5723 list. Sort the registers into order, and check that the memory
5724 offsets are ascending and adjacent. */
5726 for (i
= 1; i
< nops
; i
++)
5730 order
[i
] = order
[i
- 1];
5731 for (j
= 0; j
< nops
; j
++)
5732 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5733 && (order
[i
] == order
[i
- 1]
5734 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5737 /* Have we found a suitable register? if not, one must be used more
5739 if (order
[i
] == order
[i
- 1])
5742 /* Is the memory address adjacent and ascending? */
5743 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5751 for (i
= 0; i
< nops
; i
++)
5752 regs
[i
] = unsorted_regs
[order
[i
]];
5754 *load_offset
= unsorted_offsets
[order
[0]];
5757 if (unsorted_offsets
[order
[0]] == 0)
5758 return 1; /* stmia */
5760 if (unsorted_offsets
[order
[0]] == 4)
5761 return 2; /* stmib */
5763 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5764 return 3; /* stmda */
5766 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5767 return 4; /* stmdb */
5773 emit_stm_seq (rtx
*operands
, int nops
)
5777 HOST_WIDE_INT offset
;
5781 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5784 strcpy (buf
, "stm%?ia\t");
5788 strcpy (buf
, "stm%?ib\t");
5792 strcpy (buf
, "stm%?da\t");
5796 strcpy (buf
, "stm%?db\t");
5803 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5804 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5806 for (i
= 1; i
< nops
; i
++)
5807 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5808 reg_names
[regs
[i
]]);
5810 strcat (buf
, "}\t%@ phole stm");
5812 output_asm_insn (buf
, operands
);
5817 /* Routines for use in generating RTL. */
5820 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5821 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
5823 HOST_WIDE_INT offset
= *offsetp
;
5826 int sign
= up
? 1 : -1;
5829 /* XScale has load-store double instructions, but they have stricter
5830 alignment requirements than load-store multiple, so we cannot
5833 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5834 the pipeline until completion.
5842 An ldr instruction takes 1-3 cycles, but does not block the
5851 Best case ldr will always win. However, the more ldr instructions
5852 we issue, the less likely we are to be able to schedule them well.
5853 Using ldr instructions also increases code size.
5855 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5856 for counts of 3 or 4 regs. */
5857 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5863 for (i
= 0; i
< count
; i
++)
5865 addr
= plus_constant (from
, i
* 4 * sign
);
5866 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
5867 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5873 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5883 result
= gen_rtx_PARALLEL (VOIDmode
,
5884 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5887 XVECEXP (result
, 0, 0)
5888 = gen_rtx_SET (GET_MODE (from
), from
,
5889 plus_constant (from
, count
* 4 * sign
));
5894 for (j
= 0; i
< count
; i
++, j
++)
5896 addr
= plus_constant (from
, j
* 4 * sign
);
5897 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
5898 XVECEXP (result
, 0, i
)
5899 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5910 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5911 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
5913 HOST_WIDE_INT offset
= *offsetp
;
5916 int sign
= up
? 1 : -1;
5919 /* See arm_gen_load_multiple for discussion of
5920 the pros/cons of ldm/stm usage for XScale. */
5921 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5927 for (i
= 0; i
< count
; i
++)
5929 addr
= plus_constant (to
, i
* 4 * sign
);
5930 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
5931 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5937 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5947 result
= gen_rtx_PARALLEL (VOIDmode
,
5948 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5951 XVECEXP (result
, 0, 0)
5952 = gen_rtx_SET (GET_MODE (to
), to
,
5953 plus_constant (to
, count
* 4 * sign
));
5958 for (j
= 0; i
< count
; i
++, j
++)
5960 addr
= plus_constant (to
, j
* 4 * sign
);
5961 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
5962 XVECEXP (result
, 0, i
)
5963 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5974 arm_gen_movmemqi (rtx
*operands
)
5976 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5977 HOST_WIDE_INT srcoffset
, dstoffset
;
5979 rtx src
, dst
, srcbase
, dstbase
;
5980 rtx part_bytes_reg
= NULL
;
5983 if (GET_CODE (operands
[2]) != CONST_INT
5984 || GET_CODE (operands
[3]) != CONST_INT
5985 || INTVAL (operands
[2]) > 64
5986 || INTVAL (operands
[3]) & 3)
5989 dstbase
= operands
[0];
5990 srcbase
= operands
[1];
5992 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
5993 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
5995 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5996 out_words_to_go
= INTVAL (operands
[2]) / 4;
5997 last_bytes
= INTVAL (operands
[2]) & 3;
5998 dstoffset
= srcoffset
= 0;
6000 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6001 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6003 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6005 if (in_words_to_go
> 4)
6006 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6007 srcbase
, &srcoffset
));
6009 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6010 FALSE
, srcbase
, &srcoffset
));
6012 if (out_words_to_go
)
6014 if (out_words_to_go
> 4)
6015 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6016 dstbase
, &dstoffset
));
6017 else if (out_words_to_go
!= 1)
6018 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6022 dstbase
, &dstoffset
));
6025 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6026 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6027 if (last_bytes
!= 0)
6029 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6035 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6036 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6039 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6040 if (out_words_to_go
)
6044 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6045 sreg
= copy_to_reg (mem
);
6047 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6048 emit_move_insn (mem
, sreg
);
6051 gcc_assert (!in_words_to_go
); /* Sanity check */
6056 gcc_assert (in_words_to_go
> 0);
6058 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6059 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6062 gcc_assert (!last_bytes
|| part_bytes_reg
);
6064 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6066 rtx tmp
= gen_reg_rtx (SImode
);
6068 /* The bytes we want are in the top end of the word. */
6069 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6070 GEN_INT (8 * (4 - last_bytes
))));
6071 part_bytes_reg
= tmp
;
6075 mem
= adjust_automodify_address (dstbase
, QImode
,
6076 plus_constant (dst
, last_bytes
- 1),
6077 dstoffset
+ last_bytes
- 1);
6078 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6082 tmp
= gen_reg_rtx (SImode
);
6083 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6084 part_bytes_reg
= tmp
;
6093 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6094 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6098 rtx tmp
= gen_reg_rtx (SImode
);
6099 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6100 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6101 part_bytes_reg
= tmp
;
6108 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6109 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6116 /* Generate a memory reference for a half word, such that it will be loaded
6117 into the top 16 bits of the word. We can assume that the address is
6118 known to be alignable and of the form reg, or plus (reg, const). */
6120 /* Select a dominance comparison mode if possible for a test of the general
6121 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6122 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6123 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6124 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6125 In all cases OP will be either EQ or NE, but we don't need to know which
6126 here. If we are unable to support a dominance comparison we return
6127 CC mode. This will then fail to match for the RTL expressions that
6128 generate this call. */
6130 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6132 enum rtx_code cond1
, cond2
;
6135 /* Currently we will probably get the wrong result if the individual
6136 comparisons are not simple. This also ensures that it is safe to
6137 reverse a comparison if necessary. */
6138 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6140 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6144 /* The if_then_else variant of this tests the second condition if the
6145 first passes, but is true if the first fails. Reverse the first
6146 condition to get a true "inclusive-or" expression. */
6147 if (cond_or
== DOM_CC_NX_OR_Y
)
6148 cond1
= reverse_condition (cond1
);
6150 /* If the comparisons are not equal, and one doesn't dominate the other,
6151 then we can't do this. */
6153 && !comparison_dominates_p (cond1
, cond2
)
6154 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6159 enum rtx_code temp
= cond1
;
6167 if (cond_or
== DOM_CC_X_AND_Y
)
6172 case EQ
: return CC_DEQmode
;
6173 case LE
: return CC_DLEmode
;
6174 case LEU
: return CC_DLEUmode
;
6175 case GE
: return CC_DGEmode
;
6176 case GEU
: return CC_DGEUmode
;
6177 default: gcc_unreachable ();
6181 if (cond_or
== DOM_CC_X_AND_Y
)
6197 if (cond_or
== DOM_CC_X_AND_Y
)
6213 if (cond_or
== DOM_CC_X_AND_Y
)
6229 if (cond_or
== DOM_CC_X_AND_Y
)
6244 /* The remaining cases only occur when both comparisons are the
6247 gcc_assert (cond1
== cond2
);
6251 gcc_assert (cond1
== cond2
);
6255 gcc_assert (cond1
== cond2
);
6259 gcc_assert (cond1
== cond2
);
6263 gcc_assert (cond1
== cond2
);
6272 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6274 /* All floating point compares return CCFP if it is an equality
6275 comparison, and CCFPE otherwise. */
6276 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6296 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6305 /* A compare with a shifted operand. Because of canonicalization, the
6306 comparison will have to be swapped when we emit the assembler. */
6307 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6308 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6309 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6310 || GET_CODE (x
) == ROTATERT
))
6313 /* This operation is performed swapped, but since we only rely on the Z
6314 flag we don't need an additional mode. */
6315 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6316 && GET_CODE (x
) == NEG
6317 && (op
== EQ
|| op
== NE
))
6320 /* This is a special case that is used by combine to allow a
6321 comparison of a shifted byte load to be split into a zero-extend
6322 followed by a comparison of the shifted integer (only valid for
6323 equalities and unsigned inequalities). */
6324 if (GET_MODE (x
) == SImode
6325 && GET_CODE (x
) == ASHIFT
6326 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6327 && GET_CODE (XEXP (x
, 0)) == SUBREG
6328 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6329 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6330 && (op
== EQ
|| op
== NE
6331 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6332 && GET_CODE (y
) == CONST_INT
)
6335 /* A construct for a conditional compare, if the false arm contains
6336 0, then both conditions must be true, otherwise either condition
6337 must be true. Not all conditions are possible, so CCmode is
6338 returned if it can't be done. */
6339 if (GET_CODE (x
) == IF_THEN_ELSE
6340 && (XEXP (x
, 2) == const0_rtx
6341 || XEXP (x
, 2) == const1_rtx
)
6342 && COMPARISON_P (XEXP (x
, 0))
6343 && COMPARISON_P (XEXP (x
, 1)))
6344 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6345 INTVAL (XEXP (x
, 2)));
6347 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6348 if (GET_CODE (x
) == AND
6349 && COMPARISON_P (XEXP (x
, 0))
6350 && COMPARISON_P (XEXP (x
, 1)))
6351 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6354 if (GET_CODE (x
) == IOR
6355 && COMPARISON_P (XEXP (x
, 0))
6356 && COMPARISON_P (XEXP (x
, 1)))
6357 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6360 /* An operation (on Thumb) where we want to test for a single bit.
6361 This is done by shifting that bit up into the top bit of a
6362 scratch register; we can then branch on the sign bit. */
6364 && GET_MODE (x
) == SImode
6365 && (op
== EQ
|| op
== NE
)
6366 && (GET_CODE (x
) == ZERO_EXTRACT
))
6369 /* An operation that sets the condition codes as a side-effect, the
6370 V flag is not set correctly, so we can only use comparisons where
6371 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6373 if (GET_MODE (x
) == SImode
6375 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6376 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6377 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6378 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6379 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6380 || GET_CODE (x
) == LSHIFTRT
6381 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6382 || GET_CODE (x
) == ROTATERT
6383 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6386 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6389 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6390 && GET_CODE (x
) == PLUS
6391 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6397 /* X and Y are two things to compare using CODE. Emit the compare insn and
6398 return the rtx for register 0 in the proper mode. FP means this is a
6399 floating point compare: I don't think that it is needed on the arm. */
6401 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6403 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6404 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6406 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6407 gen_rtx_COMPARE (mode
, x
, y
)));
6412 /* Generate a sequence of insns that will generate the correct return
6413 address mask depending on the physical architecture that the program
6416 arm_gen_return_addr_mask (void)
6418 rtx reg
= gen_reg_rtx (Pmode
);
6420 emit_insn (gen_return_addr_mask (reg
));
6425 arm_reload_in_hi (rtx
*operands
)
6427 rtx ref
= operands
[1];
6429 HOST_WIDE_INT offset
= 0;
6431 if (GET_CODE (ref
) == SUBREG
)
6433 offset
= SUBREG_BYTE (ref
);
6434 ref
= SUBREG_REG (ref
);
6437 if (GET_CODE (ref
) == REG
)
6439 /* We have a pseudo which has been spilt onto the stack; there
6440 are two cases here: the first where there is a simple
6441 stack-slot replacement and a second where the stack-slot is
6442 out of range, or is used as a subreg. */
6443 if (reg_equiv_mem
[REGNO (ref
)])
6445 ref
= reg_equiv_mem
[REGNO (ref
)];
6446 base
= find_replacement (&XEXP (ref
, 0));
6449 /* The slot is out of range, or was dressed up in a SUBREG. */
6450 base
= reg_equiv_address
[REGNO (ref
)];
6453 base
= find_replacement (&XEXP (ref
, 0));
6455 /* Handle the case where the address is too complex to be offset by 1. */
6456 if (GET_CODE (base
) == MINUS
6457 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6459 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6461 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6464 else if (GET_CODE (base
) == PLUS
)
6466 /* The addend must be CONST_INT, or we would have dealt with it above. */
6467 HOST_WIDE_INT hi
, lo
;
6469 offset
+= INTVAL (XEXP (base
, 1));
6470 base
= XEXP (base
, 0);
6472 /* Rework the address into a legal sequence of insns. */
6473 /* Valid range for lo is -4095 -> 4095 */
6476 : -((-offset
) & 0xfff));
6478 /* Corner case, if lo is the max offset then we would be out of range
6479 once we have added the additional 1 below, so bump the msb into the
6480 pre-loading insn(s). */
6484 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6485 ^ (HOST_WIDE_INT
) 0x80000000)
6486 - (HOST_WIDE_INT
) 0x80000000);
6488 gcc_assert (hi
+ lo
== offset
);
6492 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6494 /* Get the base address; addsi3 knows how to handle constants
6495 that require more than one insn. */
6496 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6502 /* Operands[2] may overlap operands[0] (though it won't overlap
6503 operands[1]), that's why we asked for a DImode reg -- so we can
6504 use the bit that does not overlap. */
6505 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6506 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6508 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6510 emit_insn (gen_zero_extendqisi2 (scratch
,
6511 gen_rtx_MEM (QImode
,
6512 plus_constant (base
,
6514 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6515 gen_rtx_MEM (QImode
,
6516 plus_constant (base
,
6518 if (!BYTES_BIG_ENDIAN
)
6519 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6520 gen_rtx_IOR (SImode
,
6523 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6527 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6528 gen_rtx_IOR (SImode
,
6529 gen_rtx_ASHIFT (SImode
, scratch
,
6531 gen_rtx_SUBREG (SImode
, operands
[0],
6535 /* Handle storing a half-word to memory during reload by synthesizing as two
6536 byte stores. Take care not to clobber the input values until after we
6537 have moved them somewhere safe. This code assumes that if the DImode
6538 scratch in operands[2] overlaps either the input value or output address
6539 in some way, then that value must die in this insn (we absolutely need
6540 two scratch registers for some corner cases). */
6542 arm_reload_out_hi (rtx
*operands
)
6544 rtx ref
= operands
[0];
6545 rtx outval
= operands
[1];
6547 HOST_WIDE_INT offset
= 0;
6549 if (GET_CODE (ref
) == SUBREG
)
6551 offset
= SUBREG_BYTE (ref
);
6552 ref
= SUBREG_REG (ref
);
6555 if (GET_CODE (ref
) == REG
)
6557 /* We have a pseudo which has been spilt onto the stack; there
6558 are two cases here: the first where there is a simple
6559 stack-slot replacement and a second where the stack-slot is
6560 out of range, or is used as a subreg. */
6561 if (reg_equiv_mem
[REGNO (ref
)])
6563 ref
= reg_equiv_mem
[REGNO (ref
)];
6564 base
= find_replacement (&XEXP (ref
, 0));
6567 /* The slot is out of range, or was dressed up in a SUBREG. */
6568 base
= reg_equiv_address
[REGNO (ref
)];
6571 base
= find_replacement (&XEXP (ref
, 0));
6573 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6575 /* Handle the case where the address is too complex to be offset by 1. */
6576 if (GET_CODE (base
) == MINUS
6577 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6579 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6581 /* Be careful not to destroy OUTVAL. */
6582 if (reg_overlap_mentioned_p (base_plus
, outval
))
6584 /* Updating base_plus might destroy outval, see if we can
6585 swap the scratch and base_plus. */
6586 if (!reg_overlap_mentioned_p (scratch
, outval
))
6589 scratch
= base_plus
;
6594 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6596 /* Be conservative and copy OUTVAL into the scratch now,
6597 this should only be necessary if outval is a subreg
6598 of something larger than a word. */
6599 /* XXX Might this clobber base? I can't see how it can,
6600 since scratch is known to overlap with OUTVAL, and
6601 must be wider than a word. */
6602 emit_insn (gen_movhi (scratch_hi
, outval
));
6603 outval
= scratch_hi
;
6607 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6610 else if (GET_CODE (base
) == PLUS
)
6612 /* The addend must be CONST_INT, or we would have dealt with it above. */
6613 HOST_WIDE_INT hi
, lo
;
6615 offset
+= INTVAL (XEXP (base
, 1));
6616 base
= XEXP (base
, 0);
6618 /* Rework the address into a legal sequence of insns. */
6619 /* Valid range for lo is -4095 -> 4095 */
6622 : -((-offset
) & 0xfff));
6624 /* Corner case, if lo is the max offset then we would be out of range
6625 once we have added the additional 1 below, so bump the msb into the
6626 pre-loading insn(s). */
6630 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6631 ^ (HOST_WIDE_INT
) 0x80000000)
6632 - (HOST_WIDE_INT
) 0x80000000);
6634 gcc_assert (hi
+ lo
== offset
);
6638 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6640 /* Be careful not to destroy OUTVAL. */
6641 if (reg_overlap_mentioned_p (base_plus
, outval
))
6643 /* Updating base_plus might destroy outval, see if we
6644 can swap the scratch and base_plus. */
6645 if (!reg_overlap_mentioned_p (scratch
, outval
))
6648 scratch
= base_plus
;
6653 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6655 /* Be conservative and copy outval into scratch now,
6656 this should only be necessary if outval is a
6657 subreg of something larger than a word. */
6658 /* XXX Might this clobber base? I can't see how it
6659 can, since scratch is known to overlap with
6661 emit_insn (gen_movhi (scratch_hi
, outval
));
6662 outval
= scratch_hi
;
6666 /* Get the base address; addsi3 knows how to handle constants
6667 that require more than one insn. */
6668 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6674 if (BYTES_BIG_ENDIAN
)
6676 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6677 plus_constant (base
, offset
+ 1)),
6678 gen_lowpart (QImode
, outval
)));
6679 emit_insn (gen_lshrsi3 (scratch
,
6680 gen_rtx_SUBREG (SImode
, outval
, 0),
6682 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6683 gen_lowpart (QImode
, scratch
)));
6687 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6688 gen_lowpart (QImode
, outval
)));
6689 emit_insn (gen_lshrsi3 (scratch
,
6690 gen_rtx_SUBREG (SImode
, outval
, 0),
6692 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6693 plus_constant (base
, offset
+ 1)),
6694 gen_lowpart (QImode
, scratch
)));
6698 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
6699 (padded to the size of a word) should be passed in a register. */
6702 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
6704 if (TARGET_AAPCS_BASED
)
6705 return must_pass_in_stack_var_size (mode
, type
);
6707 return must_pass_in_stack_var_size_or_pad (mode
, type
);
6711 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
6712 Return true if an argument passed on the stack should be padded upwards,
6713 i.e. if the least-significant byte has useful data.
6714 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
6715 aggregate types are placed in the lowest memory address. */
6718 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
6720 if (!TARGET_AAPCS_BASED
)
6721 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
6723 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
6730 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
6731 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
6732 byte of the register has useful data, and return the opposite if the
6733 most significant byte does.
6734 For AAPCS, small aggregates and small complex types are always padded
6738 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
6739 tree type
, int first ATTRIBUTE_UNUSED
)
6741 if (TARGET_AAPCS_BASED
6743 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
6744 && int_size_in_bytes (type
) <= 4)
6747 /* Otherwise, use default padding. */
6748 return !BYTES_BIG_ENDIAN
;
6753 /* Print a symbolic form of X to the debug file, F. */
6755 arm_print_value (FILE *f
, rtx x
)
6757 switch (GET_CODE (x
))
6760 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6764 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6772 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6774 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6775 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6783 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6787 fprintf (f
, "`%s'", XSTR (x
, 0));
6791 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6795 arm_print_value (f
, XEXP (x
, 0));
6799 arm_print_value (f
, XEXP (x
, 0));
6801 arm_print_value (f
, XEXP (x
, 1));
6809 fprintf (f
, "????");
6814 /* Routines for manipulation of the constant pool. */
6816 /* Arm instructions cannot load a large constant directly into a
6817 register; they have to come from a pc relative load. The constant
6818 must therefore be placed in the addressable range of the pc
6819 relative load. Depending on the precise pc relative load
6820 instruction the range is somewhere between 256 bytes and 4k. This
6821 means that we often have to dump a constant inside a function, and
6822 generate code to branch around it.
6824 It is important to minimize this, since the branches will slow
6825 things down and make the code larger.
6827 Normally we can hide the table after an existing unconditional
6828 branch so that there is no interruption of the flow, but in the
6829 worst case the code looks like this:
6847 We fix this by performing a scan after scheduling, which notices
6848 which instructions need to have their operands fetched from the
6849 constant table and builds the table.
6851 The algorithm starts by building a table of all the constants that
6852 need fixing up and all the natural barriers in the function (places
6853 where a constant table can be dropped without breaking the flow).
6854 For each fixup we note how far the pc-relative replacement will be
6855 able to reach and the offset of the instruction into the function.
6857 Having built the table we then group the fixes together to form
6858 tables that are as large as possible (subject to addressing
6859 constraints) and emit each table of constants after the last
6860 barrier that is within range of all the instructions in the group.
6861 If a group does not contain a barrier, then we forcibly create one
6862 by inserting a jump instruction into the flow. Once the table has
6863 been inserted, the insns are then modified to reference the
6864 relevant entry in the pool.
6866 Possible enhancements to the algorithm (not implemented) are:
6868 1) For some processors and object formats, there may be benefit in
6869 aligning the pools to the start of cache lines; this alignment
6870 would need to be taken into account when calculating addressability
6873 /* These typedefs are located at the start of this file, so that
6874 they can be used in the prototypes there. This comment is to
6875 remind readers of that fact so that the following structures
6876 can be understood more easily.
6878 typedef struct minipool_node Mnode;
6879 typedef struct minipool_fixup Mfix; */
6881 struct minipool_node
6883 /* Doubly linked chain of entries. */
6886 /* The maximum offset into the code that this entry can be placed. While
6887 pushing fixes for forward references, all entries are sorted in order
6888 of increasing max_address. */
6889 HOST_WIDE_INT max_address
;
6890 /* Similarly for an entry inserted for a backwards ref. */
6891 HOST_WIDE_INT min_address
;
6892 /* The number of fixes referencing this entry. This can become zero
6893 if we "unpush" an entry. In this case we ignore the entry when we
6894 come to emit the code. */
6896 /* The offset from the start of the minipool. */
6897 HOST_WIDE_INT offset
;
6898 /* The value in table. */
6900 /* The mode of value. */
6901 enum machine_mode mode
;
6902 /* The size of the value. With iWMMXt enabled
6903 sizes > 4 also imply an alignment of 8-bytes. */
6907 struct minipool_fixup
6911 HOST_WIDE_INT address
;
6913 enum machine_mode mode
;
6917 HOST_WIDE_INT forwards
;
6918 HOST_WIDE_INT backwards
;
6921 /* Fixes less than a word need padding out to a word boundary. */
6922 #define MINIPOOL_FIX_SIZE(mode) \
6923 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6925 static Mnode
* minipool_vector_head
;
6926 static Mnode
* minipool_vector_tail
;
6927 static rtx minipool_vector_label
;
6929 /* The linked list of all minipool fixes required for this function. */
6930 Mfix
* minipool_fix_head
;
6931 Mfix
* minipool_fix_tail
;
6932 /* The fix entry for the current minipool, once it has been placed. */
6933 Mfix
* minipool_barrier
;
6935 /* Determines if INSN is the start of a jump table. Returns the end
6936 of the TABLE or NULL_RTX. */
6938 is_jump_table (rtx insn
)
6942 if (GET_CODE (insn
) == JUMP_INSN
6943 && JUMP_LABEL (insn
) != NULL
6944 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6945 == next_real_insn (insn
))
6947 && GET_CODE (table
) == JUMP_INSN
6948 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6949 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6955 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6956 #define JUMP_TABLES_IN_TEXT_SECTION 0
6959 static HOST_WIDE_INT
6960 get_jump_table_size (rtx insn
)
6962 /* ADDR_VECs only take room if read-only data does into the text
6964 if (JUMP_TABLES_IN_TEXT_SECTION
6965 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6970 rtx body
= PATTERN (insn
);
6971 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6973 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6979 /* Move a minipool fix MP from its current location to before MAX_MP.
6980 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6981 constraints may need updating. */
6983 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6984 HOST_WIDE_INT max_address
)
6986 /* The code below assumes these are different. */
6987 gcc_assert (mp
!= max_mp
);
6991 if (max_address
< mp
->max_address
)
6992 mp
->max_address
= max_address
;
6996 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6997 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6999 mp
->max_address
= max_address
;
7001 /* Unlink MP from its current position. Since max_mp is non-null,
7002 mp->prev must be non-null. */
7003 mp
->prev
->next
= mp
->next
;
7004 if (mp
->next
!= NULL
)
7005 mp
->next
->prev
= mp
->prev
;
7007 minipool_vector_tail
= mp
->prev
;
7009 /* Re-insert it before MAX_MP. */
7011 mp
->prev
= max_mp
->prev
;
7014 if (mp
->prev
!= NULL
)
7015 mp
->prev
->next
= mp
;
7017 minipool_vector_head
= mp
;
7020 /* Save the new entry. */
7023 /* Scan over the preceding entries and adjust their addresses as
7025 while (mp
->prev
!= NULL
7026 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7028 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7035 /* Add a constant to the minipool for a forward reference. Returns the
7036 node added or NULL if the constant will not fit in this pool. */
7038 add_minipool_forward_ref (Mfix
*fix
)
7040 /* If set, max_mp is the first pool_entry that has a lower
7041 constraint than the one we are trying to add. */
7042 Mnode
* max_mp
= NULL
;
7043 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7046 /* If this fix's address is greater than the address of the first
7047 entry, then we can't put the fix in this pool. We subtract the
7048 size of the current fix to ensure that if the table is fully
7049 packed we still have enough room to insert this value by shuffling
7050 the other fixes forwards. */
7051 if (minipool_vector_head
&&
7052 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7055 /* Scan the pool to see if a constant with the same value has
7056 already been added. While we are doing this, also note the
7057 location where we must insert the constant if it doesn't already
7059 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7061 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7062 && fix
->mode
== mp
->mode
7063 && (GET_CODE (fix
->value
) != CODE_LABEL
7064 || (CODE_LABEL_NUMBER (fix
->value
)
7065 == CODE_LABEL_NUMBER (mp
->value
)))
7066 && rtx_equal_p (fix
->value
, mp
->value
))
7068 /* More than one fix references this entry. */
7070 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7073 /* Note the insertion point if necessary. */
7075 && mp
->max_address
> max_address
)
7078 /* If we are inserting an 8-bytes aligned quantity and
7079 we have not already found an insertion point, then
7080 make sure that all such 8-byte aligned quantities are
7081 placed at the start of the pool. */
7082 if (ARM_DOUBLEWORD_ALIGN
7084 && fix
->fix_size
== 8
7085 && mp
->fix_size
!= 8)
7088 max_address
= mp
->max_address
;
7092 /* The value is not currently in the minipool, so we need to create
7093 a new entry for it. If MAX_MP is NULL, the entry will be put on
7094 the end of the list since the placement is less constrained than
7095 any existing entry. Otherwise, we insert the new fix before
7096 MAX_MP and, if necessary, adjust the constraints on the other
7098 mp
= xmalloc (sizeof (* mp
));
7099 mp
->fix_size
= fix
->fix_size
;
7100 mp
->mode
= fix
->mode
;
7101 mp
->value
= fix
->value
;
7103 /* Not yet required for a backwards ref. */
7104 mp
->min_address
= -65536;
7108 mp
->max_address
= max_address
;
7110 mp
->prev
= minipool_vector_tail
;
7112 if (mp
->prev
== NULL
)
7114 minipool_vector_head
= mp
;
7115 minipool_vector_label
= gen_label_rtx ();
7118 mp
->prev
->next
= mp
;
7120 minipool_vector_tail
= mp
;
7124 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7125 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7127 mp
->max_address
= max_address
;
7130 mp
->prev
= max_mp
->prev
;
7132 if (mp
->prev
!= NULL
)
7133 mp
->prev
->next
= mp
;
7135 minipool_vector_head
= mp
;
7138 /* Save the new entry. */
7141 /* Scan over the preceding entries and adjust their addresses as
7143 while (mp
->prev
!= NULL
7144 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7146 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7154 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7155 HOST_WIDE_INT min_address
)
7157 HOST_WIDE_INT offset
;
7159 /* The code below assumes these are different. */
7160 gcc_assert (mp
!= min_mp
);
7164 if (min_address
> mp
->min_address
)
7165 mp
->min_address
= min_address
;
7169 /* We will adjust this below if it is too loose. */
7170 mp
->min_address
= min_address
;
7172 /* Unlink MP from its current position. Since min_mp is non-null,
7173 mp->next must be non-null. */
7174 mp
->next
->prev
= mp
->prev
;
7175 if (mp
->prev
!= NULL
)
7176 mp
->prev
->next
= mp
->next
;
7178 minipool_vector_head
= mp
->next
;
7180 /* Reinsert it after MIN_MP. */
7182 mp
->next
= min_mp
->next
;
7184 if (mp
->next
!= NULL
)
7185 mp
->next
->prev
= mp
;
7187 minipool_vector_tail
= mp
;
7193 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7195 mp
->offset
= offset
;
7196 if (mp
->refcount
> 0)
7197 offset
+= mp
->fix_size
;
7199 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7200 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7206 /* Add a constant to the minipool for a backward reference. Returns the
7207 node added or NULL if the constant will not fit in this pool.
7209 Note that the code for insertion for a backwards reference can be
7210 somewhat confusing because the calculated offsets for each fix do
7211 not take into account the size of the pool (which is still under
7214 add_minipool_backward_ref (Mfix
*fix
)
7216 /* If set, min_mp is the last pool_entry that has a lower constraint
7217 than the one we are trying to add. */
7218 Mnode
*min_mp
= NULL
;
7219 /* This can be negative, since it is only a constraint. */
7220 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7223 /* If we can't reach the current pool from this insn, or if we can't
7224 insert this entry at the end of the pool without pushing other
7225 fixes out of range, then we don't try. This ensures that we
7226 can't fail later on. */
7227 if (min_address
>= minipool_barrier
->address
7228 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7229 >= minipool_barrier
->address
))
7232 /* Scan the pool to see if a constant with the same value has
7233 already been added. While we are doing this, also note the
7234 location where we must insert the constant if it doesn't already
7236 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7238 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7239 && fix
->mode
== mp
->mode
7240 && (GET_CODE (fix
->value
) != CODE_LABEL
7241 || (CODE_LABEL_NUMBER (fix
->value
)
7242 == CODE_LABEL_NUMBER (mp
->value
)))
7243 && rtx_equal_p (fix
->value
, mp
->value
)
7244 /* Check that there is enough slack to move this entry to the
7245 end of the table (this is conservative). */
7247 > (minipool_barrier
->address
7248 + minipool_vector_tail
->offset
7249 + minipool_vector_tail
->fix_size
)))
7252 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7256 mp
->min_address
+= fix
->fix_size
;
7259 /* Note the insertion point if necessary. */
7260 if (mp
->min_address
< min_address
)
7262 /* For now, we do not allow the insertion of 8-byte alignment
7263 requiring nodes anywhere but at the start of the pool. */
7264 if (ARM_DOUBLEWORD_ALIGN
7265 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7270 else if (mp
->max_address
7271 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7273 /* Inserting before this entry would push the fix beyond
7274 its maximum address (which can happen if we have
7275 re-located a forwards fix); force the new fix to come
7278 min_address
= mp
->min_address
+ fix
->fix_size
;
7280 /* If we are inserting an 8-bytes aligned quantity and
7281 we have not already found an insertion point, then
7282 make sure that all such 8-byte aligned quantities are
7283 placed at the start of the pool. */
7284 else if (ARM_DOUBLEWORD_ALIGN
7286 && fix
->fix_size
== 8
7287 && mp
->fix_size
< 8)
7290 min_address
= mp
->min_address
+ fix
->fix_size
;
7295 /* We need to create a new entry. */
7296 mp
= xmalloc (sizeof (* mp
));
7297 mp
->fix_size
= fix
->fix_size
;
7298 mp
->mode
= fix
->mode
;
7299 mp
->value
= fix
->value
;
7301 mp
->max_address
= minipool_barrier
->address
+ 65536;
7303 mp
->min_address
= min_address
;
7308 mp
->next
= minipool_vector_head
;
7310 if (mp
->next
== NULL
)
7312 minipool_vector_tail
= mp
;
7313 minipool_vector_label
= gen_label_rtx ();
7316 mp
->next
->prev
= mp
;
7318 minipool_vector_head
= mp
;
7322 mp
->next
= min_mp
->next
;
7326 if (mp
->next
!= NULL
)
7327 mp
->next
->prev
= mp
;
7329 minipool_vector_tail
= mp
;
7332 /* Save the new entry. */
7340 /* Scan over the following entries and adjust their offsets. */
7341 while (mp
->next
!= NULL
)
7343 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7344 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7347 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7349 mp
->next
->offset
= mp
->offset
;
7358 assign_minipool_offsets (Mfix
*barrier
)
7360 HOST_WIDE_INT offset
= 0;
7363 minipool_barrier
= barrier
;
7365 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7367 mp
->offset
= offset
;
7369 if (mp
->refcount
> 0)
7370 offset
+= mp
->fix_size
;
7374 /* Output the literal table */
7376 dump_minipool (rtx scan
)
7382 if (ARM_DOUBLEWORD_ALIGN
)
7383 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7384 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7392 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7393 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7395 scan
= emit_label_after (gen_label_rtx (), scan
);
7396 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7397 scan
= emit_label_after (minipool_vector_label
, scan
);
7399 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7401 if (mp
->refcount
> 0)
7406 ";; Offset %u, min %ld, max %ld ",
7407 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7408 (unsigned long) mp
->max_address
);
7409 arm_print_value (dump_file
, mp
->value
);
7410 fputc ('\n', dump_file
);
7413 switch (mp
->fix_size
)
7415 #ifdef HAVE_consttable_1
7417 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7421 #ifdef HAVE_consttable_2
7423 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7427 #ifdef HAVE_consttable_4
7429 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7433 #ifdef HAVE_consttable_8
7435 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7448 minipool_vector_head
= minipool_vector_tail
= NULL
;
7449 scan
= emit_insn_after (gen_consttable_end (), scan
);
7450 scan
= emit_barrier_after (scan
);
7453 /* Return the cost of forcibly inserting a barrier after INSN. */
7455 arm_barrier_cost (rtx insn
)
7457 /* Basing the location of the pool on the loop depth is preferable,
7458 but at the moment, the basic block information seems to be
7459 corrupt by this stage of the compilation. */
7461 rtx next
= next_nonnote_insn (insn
);
7463 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7466 switch (GET_CODE (insn
))
7469 /* It will always be better to place the table before the label, rather
7478 return base_cost
- 10;
7481 return base_cost
+ 10;
7485 /* Find the best place in the insn stream in the range
7486 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7487 Create the barrier by inserting a jump and add a new fix entry for
7490 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7492 HOST_WIDE_INT count
= 0;
7494 rtx from
= fix
->insn
;
7495 rtx selected
= from
;
7497 HOST_WIDE_INT selected_address
;
7499 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7500 rtx label
= gen_label_rtx ();
7502 selected_cost
= arm_barrier_cost (from
);
7503 selected_address
= fix
->address
;
7505 while (from
&& count
< max_count
)
7510 /* This code shouldn't have been called if there was a natural barrier
7512 gcc_assert (GET_CODE (from
) != BARRIER
);
7514 /* Count the length of this insn. */
7515 count
+= get_attr_length (from
);
7517 /* If there is a jump table, add its length. */
7518 tmp
= is_jump_table (from
);
7521 count
+= get_jump_table_size (tmp
);
7523 /* Jump tables aren't in a basic block, so base the cost on
7524 the dispatch insn. If we select this location, we will
7525 still put the pool after the table. */
7526 new_cost
= arm_barrier_cost (from
);
7528 if (count
< max_count
&& new_cost
<= selected_cost
)
7531 selected_cost
= new_cost
;
7532 selected_address
= fix
->address
+ count
;
7535 /* Continue after the dispatch table. */
7536 from
= NEXT_INSN (tmp
);
7540 new_cost
= arm_barrier_cost (from
);
7542 if (count
< max_count
&& new_cost
<= selected_cost
)
7545 selected_cost
= new_cost
;
7546 selected_address
= fix
->address
+ count
;
7549 from
= NEXT_INSN (from
);
7552 /* Create a new JUMP_INSN that branches around a barrier. */
7553 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7554 JUMP_LABEL (from
) = label
;
7555 barrier
= emit_barrier_after (from
);
7556 emit_label_after (label
, barrier
);
7558 /* Create a minipool barrier entry for the new barrier. */
7559 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7560 new_fix
->insn
= barrier
;
7561 new_fix
->address
= selected_address
;
7562 new_fix
->next
= fix
->next
;
7563 fix
->next
= new_fix
;
7568 /* Record that there is a natural barrier in the insn stream at
7571 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7573 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7576 fix
->address
= address
;
7579 if (minipool_fix_head
!= NULL
)
7580 minipool_fix_tail
->next
= fix
;
7582 minipool_fix_head
= fix
;
7584 minipool_fix_tail
= fix
;
7587 /* Record INSN, which will need fixing up to load a value from the
7588 minipool. ADDRESS is the offset of the insn since the start of the
7589 function; LOC is a pointer to the part of the insn which requires
7590 fixing; VALUE is the constant that must be loaded, which is of type
7593 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7594 enum machine_mode mode
, rtx value
)
7596 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7598 #ifdef AOF_ASSEMBLER
7599 /* PIC symbol references need to be converted into offsets into the
7601 /* XXX This shouldn't be done here. */
7602 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7603 value
= aof_pic_entry (value
);
7604 #endif /* AOF_ASSEMBLER */
7607 fix
->address
= address
;
7610 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7612 fix
->forwards
= get_attr_pool_range (insn
);
7613 fix
->backwards
= get_attr_neg_pool_range (insn
);
7614 fix
->minipool
= NULL
;
7616 /* If an insn doesn't have a range defined for it, then it isn't
7617 expecting to be reworked by this code. Better to stop now than
7618 to generate duff assembly code. */
7619 gcc_assert (fix
->forwards
|| fix
->backwards
);
7621 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7622 So there might be an empty word before the start of the pool.
7623 Hence we reduce the forward range by 4 to allow for this
7625 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7631 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7632 GET_MODE_NAME (mode
),
7633 INSN_UID (insn
), (unsigned long) address
,
7634 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7635 arm_print_value (dump_file
, fix
->value
);
7636 fprintf (dump_file
, "\n");
7639 /* Add it to the chain of fixes. */
7642 if (minipool_fix_head
!= NULL
)
7643 minipool_fix_tail
->next
= fix
;
7645 minipool_fix_head
= fix
;
7647 minipool_fix_tail
= fix
;
7650 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7651 Returns the number of insns needed, or 99 if we don't know how to
7654 arm_const_double_inline_cost (rtx val
)
7656 rtx lowpart
, highpart
;
7657 enum machine_mode mode
;
7659 mode
= GET_MODE (val
);
7661 if (mode
== VOIDmode
)
7664 gcc_assert (GET_MODE_SIZE (mode
) == 8);
7666 lowpart
= gen_lowpart (SImode
, val
);
7667 highpart
= gen_highpart_mode (SImode
, mode
, val
);
7669 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
7670 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
7672 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
7673 NULL_RTX
, NULL_RTX
, 0, 0)
7674 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
7675 NULL_RTX
, NULL_RTX
, 0, 0));
7678 /* Return true if it is worthwhile to split a 64-bit constant into two
7679 32-bit operations. This is the case if optimizing for size, or
7680 if we have load delay slots, or if one 32-bit part can be done with
7681 a single data operation. */
7683 arm_const_double_by_parts (rtx val
)
7685 enum machine_mode mode
= GET_MODE (val
);
7688 if (optimize_size
|| arm_ld_sched
)
7691 if (mode
== VOIDmode
)
7694 part
= gen_highpart_mode (SImode
, mode
, val
);
7696 gcc_assert (GET_CODE (part
) == CONST_INT
);
7698 if (const_ok_for_arm (INTVAL (part
))
7699 || const_ok_for_arm (~INTVAL (part
)))
7702 part
= gen_lowpart (SImode
, val
);
7704 gcc_assert (GET_CODE (part
) == CONST_INT
);
7706 if (const_ok_for_arm (INTVAL (part
))
7707 || const_ok_for_arm (~INTVAL (part
)))
7713 /* Scan INSN and note any of its operands that need fixing.
7714 If DO_PUSHES is false we do not actually push any of the fixups
7715 needed. The function returns TRUE if any fixups were needed/pushed.
7716 This is used by arm_memory_load_p() which needs to know about loads
7717 of constants that will be converted into minipool loads. */
7719 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
7721 bool result
= false;
7724 extract_insn (insn
);
7726 if (!constrain_operands (1))
7727 fatal_insn_not_found (insn
);
7729 if (recog_data
.n_alternatives
== 0)
7732 /* Fill in recog_op_alt with information about the constraints of
7734 preprocess_constraints ();
7736 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7738 /* Things we need to fix can only occur in inputs. */
7739 if (recog_data
.operand_type
[opno
] != OP_IN
)
7742 /* If this alternative is a memory reference, then any mention
7743 of constants in this alternative is really to fool reload
7744 into allowing us to accept one there. We need to fix them up
7745 now so that we output the right code. */
7746 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
7748 rtx op
= recog_data
.operand
[opno
];
7750 if (CONSTANT_P (op
))
7753 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
7754 recog_data
.operand_mode
[opno
], op
);
7757 else if (GET_CODE (op
) == MEM
7758 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
7759 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
7763 rtx cop
= avoid_constant_pool_reference (op
);
7765 /* Casting the address of something to a mode narrower
7766 than a word can cause avoid_constant_pool_reference()
7767 to return the pool reference itself. That's no good to
7768 us here. Lets just hope that we can use the
7769 constant pool value directly. */
7771 cop
= get_pool_constant (XEXP (op
, 0));
7773 push_minipool_fix (insn
, address
,
7774 recog_data
.operand_loc
[opno
],
7775 recog_data
.operand_mode
[opno
], cop
);
7786 /* Gcc puts the pool in the wrong place for ARM, since we can only
7787 load addresses a limited distance around the pc. We do some
7788 special munging to move the constant pool values to the correct
7789 point in the code. */
7794 HOST_WIDE_INT address
= 0;
7797 minipool_fix_head
= minipool_fix_tail
= NULL
;
7799 /* The first insn must always be a note, or the code below won't
7800 scan it properly. */
7801 insn
= get_insns ();
7802 gcc_assert (GET_CODE (insn
) == NOTE
);
7804 /* Scan all the insns and record the operands that will need fixing. */
7805 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7807 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7808 && (arm_cirrus_insn_p (insn
)
7809 || GET_CODE (insn
) == JUMP_INSN
7810 || arm_memory_load_p (insn
)))
7811 cirrus_reorg (insn
);
7813 if (GET_CODE (insn
) == BARRIER
)
7814 push_minipool_barrier (insn
, address
);
7815 else if (INSN_P (insn
))
7819 note_invalid_constants (insn
, address
, true);
7820 address
+= get_attr_length (insn
);
7822 /* If the insn is a vector jump, add the size of the table
7823 and skip the table. */
7824 if ((table
= is_jump_table (insn
)) != NULL
)
7826 address
+= get_jump_table_size (table
);
7832 fix
= minipool_fix_head
;
7834 /* Now scan the fixups and perform the required changes. */
7839 Mfix
* last_added_fix
;
7840 Mfix
* last_barrier
= NULL
;
7843 /* Skip any further barriers before the next fix. */
7844 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7847 /* No more fixes. */
7851 last_added_fix
= NULL
;
7853 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7855 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7857 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7860 last_barrier
= ftmp
;
7862 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7865 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7868 /* If we found a barrier, drop back to that; any fixes that we
7869 could have reached but come after the barrier will now go in
7870 the next mini-pool. */
7871 if (last_barrier
!= NULL
)
7873 /* Reduce the refcount for those fixes that won't go into this
7875 for (fdel
= last_barrier
->next
;
7876 fdel
&& fdel
!= ftmp
;
7879 fdel
->minipool
->refcount
--;
7880 fdel
->minipool
= NULL
;
7883 ftmp
= last_barrier
;
7887 /* ftmp is first fix that we can't fit into this pool and
7888 there no natural barriers that we could use. Insert a
7889 new barrier in the code somewhere between the previous
7890 fix and this one, and arrange to jump around it. */
7891 HOST_WIDE_INT max_address
;
7893 /* The last item on the list of fixes must be a barrier, so
7894 we can never run off the end of the list of fixes without
7895 last_barrier being set. */
7898 max_address
= minipool_vector_head
->max_address
;
7899 /* Check that there isn't another fix that is in range that
7900 we couldn't fit into this pool because the pool was
7901 already too large: we need to put the pool before such an
7903 if (ftmp
->address
< max_address
)
7904 max_address
= ftmp
->address
;
7906 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7909 assign_minipool_offsets (last_barrier
);
7913 if (GET_CODE (ftmp
->insn
) != BARRIER
7914 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7921 /* Scan over the fixes we have identified for this pool, fixing them
7922 up and adding the constants to the pool itself. */
7923 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7924 this_fix
= this_fix
->next
)
7925 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7928 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7929 minipool_vector_label
),
7930 this_fix
->minipool
->offset
);
7931 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7934 dump_minipool (last_barrier
->insn
);
7938 /* From now on we must synthesize any constants that we can't handle
7939 directly. This can happen if the RTL gets split during final
7940 instruction generation. */
7941 after_arm_reorg
= 1;
7943 /* Free the minipool memory. */
7944 obstack_free (&minipool_obstack
, minipool_startobj
);
7947 /* Routines to output assembly language. */
7949 /* If the rtx is the correct value then return the string of the number.
7950 In this way we can ensure that valid double constants are generated even
7951 when cross compiling. */
7953 fp_immediate_constant (rtx x
)
7958 if (!fp_consts_inited
)
7961 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7962 for (i
= 0; i
< 8; i
++)
7963 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7964 return strings_fp
[i
];
7969 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7971 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7975 if (!fp_consts_inited
)
7978 for (i
= 0; i
< 8; i
++)
7979 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
7980 return strings_fp
[i
];
7985 /* Output the operands of a LDM/STM instruction to STREAM.
7986 MASK is the ARM register set mask of which only bits 0-15 are important.
7987 REG is the base register, either the frame pointer or the stack pointer,
7988 INSTR is the possibly suffixed load or store instruction. */
7991 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
7995 bool not_first
= FALSE
;
7997 fputc ('\t', stream
);
7998 asm_fprintf (stream
, instr
, reg
);
7999 fputs (", {", stream
);
8001 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8002 if (mask
& (1 << i
))
8005 fprintf (stream
, ", ");
8007 asm_fprintf (stream
, "%r", i
);
8011 fprintf (stream
, "}\n");
8015 /* Output a FLDMX instruction to STREAM.
8016 BASE if the register containing the address.
8017 REG and COUNT specify the register range.
8018 Extra registers may be added to avoid hardware bugs. */
8021 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8025 /* Workaround ARM10 VFPr1 bug. */
8026 if (count
== 2 && !arm_arch6
)
8033 fputc ('\t', stream
);
8034 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8036 for (i
= reg
; i
< reg
+ count
; i
++)
8039 fputs (", ", stream
);
8040 asm_fprintf (stream
, "d%d", i
);
8042 fputs ("}\n", stream
);
8047 /* Output the assembly for a store multiple. */
8050 vfp_output_fstmx (rtx
* operands
)
8057 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8058 p
= strlen (pattern
);
8060 gcc_assert (GET_CODE (operands
[1]) == REG
);
8062 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8063 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8065 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8067 strcpy (&pattern
[p
], "}");
8069 output_asm_insn (pattern
, operands
);
8074 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8075 number of bytes pushed. */
8078 vfp_emit_fstmx (int base_reg
, int count
)
8085 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8086 register pairs are stored by a store multiple insn. We avoid this
8087 by pushing an extra pair. */
8088 if (count
== 2 && !arm_arch6
)
8090 if (base_reg
== LAST_VFP_REGNUM
- 3)
8095 /* ??? The frame layout is implementation defined. We describe
8096 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8097 We really need some way of representing the whole block so that the
8098 unwinder can figure it out at runtime. */
8099 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8100 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8102 reg
= gen_rtx_REG (DFmode
, base_reg
);
8106 = gen_rtx_SET (VOIDmode
,
8107 gen_frame_mem (BLKmode
,
8108 gen_rtx_PRE_DEC (BLKmode
,
8109 stack_pointer_rtx
)),
8110 gen_rtx_UNSPEC (BLKmode
,
8114 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8115 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8116 GEN_INT (-(count
* 8 + 4))));
8117 RTX_FRAME_RELATED_P (tmp
) = 1;
8118 XVECEXP (dwarf
, 0, 0) = tmp
;
8120 tmp
= gen_rtx_SET (VOIDmode
,
8121 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8123 RTX_FRAME_RELATED_P (tmp
) = 1;
8124 XVECEXP (dwarf
, 0, 1) = tmp
;
8126 for (i
= 1; i
< count
; i
++)
8128 reg
= gen_rtx_REG (DFmode
, base_reg
);
8130 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8132 tmp
= gen_rtx_SET (VOIDmode
,
8133 gen_frame_mem (DFmode
,
8134 gen_rtx_PLUS (SImode
,
8138 RTX_FRAME_RELATED_P (tmp
) = 1;
8139 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8142 par
= emit_insn (par
);
8143 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8145 RTX_FRAME_RELATED_P (par
) = 1;
8147 return count
* 8 + 4;
8151 /* Output a 'call' insn. */
8153 output_call (rtx
*operands
)
8155 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8157 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8158 if (REGNO (operands
[0]) == LR_REGNUM
)
8160 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8161 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8164 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8166 if (TARGET_INTERWORK
|| arm_arch4t
)
8167 output_asm_insn ("bx%?\t%0", operands
);
8169 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8174 /* Output a 'call' insn that is a reference in memory. */
8176 output_call_mem (rtx
*operands
)
8178 if (TARGET_INTERWORK
&& !arm_arch5
)
8180 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8181 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8182 output_asm_insn ("bx%?\t%|ip", operands
);
8184 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8186 /* LR is used in the memory address. We load the address in the
8187 first instruction. It's safe to use IP as the target of the
8188 load since the call will kill it anyway. */
8189 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8191 output_asm_insn ("blx%?\t%|ip", operands
);
8194 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8196 output_asm_insn ("bx%?\t%|ip", operands
);
8198 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8203 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8204 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8211 /* Output a move from arm registers to an fpa registers.
8212 OPERANDS[0] is an fpa register.
8213 OPERANDS[1] is the first registers of an arm register pair. */
8215 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8217 int arm_reg0
= REGNO (operands
[1]);
8220 gcc_assert (arm_reg0
!= IP_REGNUM
);
8222 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8223 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8224 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8226 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8227 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8232 /* Output a move from an fpa register to arm registers.
8233 OPERANDS[0] is the first registers of an arm register pair.
8234 OPERANDS[1] is an fpa register. */
8236 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8238 int arm_reg0
= REGNO (operands
[0]);
8241 gcc_assert (arm_reg0
!= IP_REGNUM
);
8243 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8244 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8245 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8247 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8248 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8252 /* Output a move from arm registers to arm registers of a long double
8253 OPERANDS[0] is the destination.
8254 OPERANDS[1] is the source. */
8256 output_mov_long_double_arm_from_arm (rtx
*operands
)
8258 /* We have to be careful here because the two might overlap. */
8259 int dest_start
= REGNO (operands
[0]);
8260 int src_start
= REGNO (operands
[1]);
8264 if (dest_start
< src_start
)
8266 for (i
= 0; i
< 3; i
++)
8268 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8269 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8270 output_asm_insn ("mov%?\t%0, %1", ops
);
8275 for (i
= 2; i
>= 0; i
--)
8277 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8278 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8279 output_asm_insn ("mov%?\t%0, %1", ops
);
8287 /* Output a move from arm registers to an fpa registers.
8288 OPERANDS[0] is an fpa register.
8289 OPERANDS[1] is the first registers of an arm register pair. */
8291 output_mov_double_fpa_from_arm (rtx
*operands
)
8293 int arm_reg0
= REGNO (operands
[1]);
8296 gcc_assert (arm_reg0
!= IP_REGNUM
);
8298 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8299 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8300 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8301 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8305 /* Output a move from an fpa register to arm registers.
8306 OPERANDS[0] is the first registers of an arm register pair.
8307 OPERANDS[1] is an fpa register. */
8309 output_mov_double_arm_from_fpa (rtx
*operands
)
8311 int arm_reg0
= REGNO (operands
[0]);
8314 gcc_assert (arm_reg0
!= IP_REGNUM
);
8316 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8317 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8318 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8319 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8323 /* Output a move between double words.
8324 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8325 or MEM<-REG and all MEMs must be offsettable addresses. */
8327 output_move_double (rtx
*operands
)
8329 enum rtx_code code0
= GET_CODE (operands
[0]);
8330 enum rtx_code code1
= GET_CODE (operands
[1]);
8335 int reg0
= REGNO (operands
[0]);
8337 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8339 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8341 switch (GET_CODE (XEXP (operands
[1], 0)))
8344 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8348 gcc_assert (TARGET_LDRD
);
8349 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8353 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8357 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8361 gcc_assert (TARGET_LDRD
);
8362 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8367 otherops
[0] = operands
[0];
8368 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8369 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8371 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8373 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8375 /* Registers overlap so split out the increment. */
8376 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8377 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8380 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8384 /* We only allow constant increments, so this is safe. */
8385 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8391 output_asm_insn ("adr%?\t%0, %1", operands
);
8392 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8396 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8397 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8399 otherops
[0] = operands
[0];
8400 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8401 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8403 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8405 if (GET_CODE (otherops
[2]) == CONST_INT
)
8407 switch ((int) INTVAL (otherops
[2]))
8410 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8413 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8416 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8421 && (GET_CODE (otherops
[2]) == REG
8422 || (GET_CODE (otherops
[2]) == CONST_INT
8423 && INTVAL (otherops
[2]) > -256
8424 && INTVAL (otherops
[2]) < 256)))
8426 if (reg_overlap_mentioned_p (otherops
[0],
8429 /* Swap base and index registers over to
8430 avoid a conflict. */
8431 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8432 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8435 /* If both registers conflict, it will usually
8436 have been fixed by a splitter. */
8437 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8439 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8440 output_asm_insn ("ldr%?d\t%0, [%1]",
8444 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8448 if (GET_CODE (otherops
[2]) == CONST_INT
)
8450 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8451 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8453 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8456 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8459 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8461 return "ldm%?ia\t%0, %M0";
8465 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8466 /* Take care of overlapping base/data reg. */
8467 if (reg_mentioned_p (operands
[0], operands
[1]))
8469 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8470 output_asm_insn ("ldr%?\t%0, %1", operands
);
8474 output_asm_insn ("ldr%?\t%0, %1", operands
);
8475 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8482 /* Constraints should ensure this. */
8483 gcc_assert (code0
== MEM
&& code1
== REG
);
8484 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8486 switch (GET_CODE (XEXP (operands
[0], 0)))
8489 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8493 gcc_assert (TARGET_LDRD
);
8494 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8498 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8502 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8506 gcc_assert (TARGET_LDRD
);
8507 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8512 otherops
[0] = operands
[1];
8513 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8514 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8516 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8517 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8519 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8523 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8524 if (GET_CODE (otherops
[2]) == CONST_INT
)
8526 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8529 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8533 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8537 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8542 && (GET_CODE (otherops
[2]) == REG
8543 || (GET_CODE (otherops
[2]) == CONST_INT
8544 && INTVAL (otherops
[2]) > -256
8545 && INTVAL (otherops
[2]) < 256)))
8547 otherops
[0] = operands
[1];
8548 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8549 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8555 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8556 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8557 output_asm_insn ("str%?\t%1, %0", operands
);
8558 output_asm_insn ("str%?\t%1, %0", otherops
);
8565 /* Output an ADD r, s, #n where n may be too big for one instruction.
8566 If adding zero to one register, output nothing. */
8568 output_add_immediate (rtx
*operands
)
8570 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8572 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8575 output_multi_immediate (operands
,
8576 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8579 output_multi_immediate (operands
,
8580 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8587 /* Output a multiple immediate operation.
8588 OPERANDS is the vector of operands referred to in the output patterns.
8589 INSTR1 is the output pattern to use for the first constant.
8590 INSTR2 is the output pattern to use for subsequent constants.
8591 IMMED_OP is the index of the constant slot in OPERANDS.
8592 N is the constant value. */
8594 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8595 int immed_op
, HOST_WIDE_INT n
)
8597 #if HOST_BITS_PER_WIDE_INT > 32
8603 /* Quick and easy output. */
8604 operands
[immed_op
] = const0_rtx
;
8605 output_asm_insn (instr1
, operands
);
8610 const char * instr
= instr1
;
8612 /* Note that n is never zero here (which would give no output). */
8613 for (i
= 0; i
< 32; i
+= 2)
8617 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8618 output_asm_insn (instr
, operands
);
8628 /* Return the appropriate ARM instruction for the operation code.
8629 The returned result should not be overwritten. OP is the rtx of the
8630 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8633 arithmetic_instr (rtx op
, int shift_first_arg
)
8635 switch (GET_CODE (op
))
8641 return shift_first_arg
? "rsb" : "sub";
8657 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8658 for the operation code. The returned result should not be overwritten.
8659 OP is the rtx code of the shift.
8660 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8663 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8666 enum rtx_code code
= GET_CODE (op
);
8668 switch (GET_CODE (XEXP (op
, 1)))
8676 *amountp
= INTVAL (XEXP (op
, 1));
8698 gcc_assert (*amountp
!= -1);
8699 *amountp
= 32 - *amountp
;
8708 /* We never have to worry about the amount being other than a
8709 power of 2, since this case can never be reloaded from a reg. */
8710 gcc_assert (*amountp
!= -1);
8711 *amountp
= int_log2 (*amountp
);
8720 /* This is not 100% correct, but follows from the desire to merge
8721 multiplication by a power of 2 with the recognizer for a
8722 shift. >=32 is not a valid shift for "asl", so we must try and
8723 output a shift that produces the correct arithmetical result.
8724 Using lsr #32 is identical except for the fact that the carry bit
8725 is not set correctly if we set the flags; but we never use the
8726 carry bit from such an operation, so we can ignore that. */
8727 if (code
== ROTATERT
)
8728 /* Rotate is just modulo 32. */
8730 else if (*amountp
!= (*amountp
& 31))
8737 /* Shifts of 0 are no-ops. */
8745 /* Obtain the shift from the POWER of two. */
8747 static HOST_WIDE_INT
8748 int_log2 (HOST_WIDE_INT power
)
8750 HOST_WIDE_INT shift
= 0;
8752 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
8754 gcc_assert (shift
<= 31);
8761 /* Output a .ascii pseudo-op, keeping track of lengths. This is
8762 because /bin/as is horribly restrictive. The judgement about
8763 whether or not each character is 'printable' (and can be output as
8764 is) or not (and must be printed with an octal escape) must be made
8765 with reference to the *host* character set -- the situation is
8766 similar to that discussed in the comments above pp_c_char in
8767 c-pretty-print.c. */
8769 #define MAX_ASCII_LEN 51
8772 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
8777 fputs ("\t.ascii\t\"", stream
);
8779 for (i
= 0; i
< len
; i
++)
8783 if (len_so_far
>= MAX_ASCII_LEN
)
8785 fputs ("\"\n\t.ascii\t\"", stream
);
8791 if (c
== '\\' || c
== '\"')
8793 putc ('\\', stream
);
8801 fprintf (stream
, "\\%03o", c
);
8806 fputs ("\"\n", stream
);
8809 /* Compute the register save mask for registers 0 through 12
8810 inclusive. This code is used by arm_compute_save_reg_mask. */
8812 static unsigned long
8813 arm_compute_save_reg0_reg12_mask (void)
8815 unsigned long func_type
= arm_current_func_type ();
8816 unsigned long save_reg_mask
= 0;
8819 if (IS_INTERRUPT (func_type
))
8821 unsigned int max_reg
;
8822 /* Interrupt functions must not corrupt any registers,
8823 even call clobbered ones. If this is a leaf function
8824 we can just examine the registers used by the RTL, but
8825 otherwise we have to assume that whatever function is
8826 called might clobber anything, and so we have to save
8827 all the call-clobbered registers as well. */
8828 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
8829 /* FIQ handlers have registers r8 - r12 banked, so
8830 we only need to check r0 - r7, Normal ISRs only
8831 bank r14 and r15, so we must check up to r12.
8832 r13 is the stack pointer which is always preserved,
8833 so we do not need to consider it here. */
8838 for (reg
= 0; reg
<= max_reg
; reg
++)
8839 if (regs_ever_live
[reg
]
8840 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
8841 save_reg_mask
|= (1 << reg
);
8843 /* Also save the pic base register if necessary. */
8845 && !TARGET_SINGLE_PIC_BASE
8846 && current_function_uses_pic_offset_table
)
8847 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8851 /* In the normal case we only need to save those registers
8852 which are call saved and which are used by this function. */
8853 for (reg
= 0; reg
<= 10; reg
++)
8854 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8855 save_reg_mask
|= (1 << reg
);
8857 /* Handle the frame pointer as a special case. */
8858 if (! TARGET_APCS_FRAME
8859 && ! frame_pointer_needed
8860 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
8861 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
8862 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
8864 /* If we aren't loading the PIC register,
8865 don't stack it even though it may be live. */
8867 && !TARGET_SINGLE_PIC_BASE
8868 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
8869 || current_function_uses_pic_offset_table
))
8870 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8873 /* Save registers so the exception handler can modify them. */
8874 if (current_function_calls_eh_return
)
8880 reg
= EH_RETURN_DATA_REGNO (i
);
8881 if (reg
== INVALID_REGNUM
)
8883 save_reg_mask
|= 1 << reg
;
8887 return save_reg_mask
;
8890 /* Compute a bit mask of which registers need to be
8891 saved on the stack for the current function. */
8893 static unsigned long
8894 arm_compute_save_reg_mask (void)
8896 unsigned int save_reg_mask
= 0;
8897 unsigned long func_type
= arm_current_func_type ();
8899 if (IS_NAKED (func_type
))
8900 /* This should never really happen. */
8903 /* If we are creating a stack frame, then we must save the frame pointer,
8904 IP (which will hold the old stack pointer), LR and the PC. */
8905 if (frame_pointer_needed
)
8907 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
8912 /* Volatile functions do not return, so there
8913 is no need to save any other registers. */
8914 if (IS_VOLATILE (func_type
))
8915 return save_reg_mask
;
8917 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
8919 /* Decide if we need to save the link register.
8920 Interrupt routines have their own banked link register,
8921 so they never need to save it.
8922 Otherwise if we do not use the link register we do not need to save
8923 it. If we are pushing other registers onto the stack however, we
8924 can save an instruction in the epilogue by pushing the link register
8925 now and then popping it back into the PC. This incurs extra memory
8926 accesses though, so we only do it when optimizing for size, and only
8927 if we know that we will not need a fancy return sequence. */
8928 if (regs_ever_live
[LR_REGNUM
]
8931 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8932 && !current_function_calls_eh_return
))
8933 save_reg_mask
|= 1 << LR_REGNUM
;
8935 if (cfun
->machine
->lr_save_eliminated
)
8936 save_reg_mask
&= ~ (1 << LR_REGNUM
);
8938 if (TARGET_REALLY_IWMMXT
8939 && ((bit_count (save_reg_mask
)
8940 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
8944 /* The total number of registers that are going to be pushed
8945 onto the stack is odd. We need to ensure that the stack
8946 is 64-bit aligned before we start to save iWMMXt registers,
8947 and also before we start to create locals. (A local variable
8948 might be a double or long long which we will load/store using
8949 an iWMMXt instruction). Therefore we need to push another
8950 ARM register, so that the stack will be 64-bit aligned. We
8951 try to avoid using the arg registers (r0 -r3) as they might be
8952 used to pass values in a tail call. */
8953 for (reg
= 4; reg
<= 12; reg
++)
8954 if ((save_reg_mask
& (1 << reg
)) == 0)
8958 save_reg_mask
|= (1 << reg
);
8961 cfun
->machine
->sibcall_blocked
= 1;
8962 save_reg_mask
|= (1 << 3);
8966 return save_reg_mask
;
8970 /* Compute a bit mask of which registers need to be
8971 saved on the stack for the current function. */
8972 static unsigned long
8973 thumb_compute_save_reg_mask (void)
8979 for (reg
= 0; reg
< 12; reg
++)
8980 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8984 && !TARGET_SINGLE_PIC_BASE
8985 && current_function_uses_pic_offset_table
)
8986 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8988 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
8989 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
8990 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
8992 /* LR will also be pushed if any lo regs are pushed. */
8993 if (mask
& 0xff || thumb_force_lr_save ())
8994 mask
|= (1 << LR_REGNUM
);
8996 /* Make sure we have a low work register if we need one.
8997 We will need one if we are going to push a high register,
8998 but we are not currently intending to push a low register. */
8999 if ((mask
& 0xff) == 0
9000 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9002 /* Use thumb_find_work_register to choose which register
9003 we will use. If the register is live then we will
9004 have to push it. Use LAST_LO_REGNUM as our fallback
9005 choice for the register to select. */
9006 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9008 if (! call_used_regs
[reg
])
9016 /* Return the number of bytes required to save VFP registers. */
9018 arm_get_vfp_saved_size (void)
9025 /* Space for saved VFP registers. */
9026 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9029 for (regno
= FIRST_VFP_REGNUM
;
9030 regno
< LAST_VFP_REGNUM
;
9033 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9034 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9038 /* Workaround ARM10 VFPr1 bug. */
9039 if (count
== 2 && !arm_arch6
)
9041 saved
+= count
* 8 + 4;
9050 if (count
== 2 && !arm_arch6
)
9052 saved
+= count
* 8 + 4;
9059 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9060 everything bar the final return instruction. */
9062 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9064 char conditional
[10];
9067 unsigned long live_regs_mask
;
9068 unsigned long func_type
;
9069 arm_stack_offsets
*offsets
;
9071 func_type
= arm_current_func_type ();
9073 if (IS_NAKED (func_type
))
9076 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9078 /* If this function was declared non-returning, and we have
9079 found a tail call, then we have to trust that the called
9080 function won't return. */
9085 /* Otherwise, trap an attempted return by aborting. */
9087 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9089 assemble_external_libcall (ops
[1]);
9090 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9096 gcc_assert (!current_function_calls_alloca
|| really_return
);
9098 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9100 return_used_this_function
= 1;
9102 live_regs_mask
= arm_compute_save_reg_mask ();
9106 const char * return_reg
;
9108 /* If we do not have any special requirements for function exit
9109 (e.g. interworking, or ISR) then we can load the return address
9110 directly into the PC. Otherwise we must load it into LR. */
9112 && ! TARGET_INTERWORK
)
9113 return_reg
= reg_names
[PC_REGNUM
];
9115 return_reg
= reg_names
[LR_REGNUM
];
9117 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9119 /* There are three possible reasons for the IP register
9120 being saved. 1) a stack frame was created, in which case
9121 IP contains the old stack pointer, or 2) an ISR routine
9122 corrupted it, or 3) it was saved to align the stack on
9123 iWMMXt. In case 1, restore IP into SP, otherwise just
9125 if (frame_pointer_needed
)
9127 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9128 live_regs_mask
|= (1 << SP_REGNUM
);
9131 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9134 /* On some ARM architectures it is faster to use LDR rather than
9135 LDM to load a single register. On other architectures, the
9136 cost is the same. In 26 bit mode, or for exception handlers,
9137 we have to use LDM to load the PC so that the CPSR is also
9139 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9140 if (live_regs_mask
== (1U << reg
))
9143 if (reg
<= LAST_ARM_REGNUM
9144 && (reg
!= LR_REGNUM
9146 || ! IS_INTERRUPT (func_type
)))
9148 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9149 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9156 /* Generate the load multiple instruction to restore the
9157 registers. Note we can get here, even if
9158 frame_pointer_needed is true, but only if sp already
9159 points to the base of the saved core registers. */
9160 if (live_regs_mask
& (1 << SP_REGNUM
))
9162 unsigned HOST_WIDE_INT stack_adjust
;
9164 offsets
= arm_get_frame_offsets ();
9165 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9166 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9168 if (stack_adjust
&& arm_arch5
)
9169 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9172 /* If we can't use ldmib (SA110 bug),
9173 then try to pop r3 instead. */
9175 live_regs_mask
|= 1 << 3;
9176 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9180 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9182 p
= instr
+ strlen (instr
);
9184 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9185 if (live_regs_mask
& (1 << reg
))
9187 int l
= strlen (reg_names
[reg
]);
9193 memcpy (p
, ", ", 2);
9197 memcpy (p
, "%|", 2);
9198 memcpy (p
+ 2, reg_names
[reg
], l
);
9202 if (live_regs_mask
& (1 << LR_REGNUM
))
9204 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9205 /* If returning from an interrupt, restore the CPSR. */
9206 if (IS_INTERRUPT (func_type
))
9213 output_asm_insn (instr
, & operand
);
9215 /* See if we need to generate an extra instruction to
9216 perform the actual function return. */
9218 && func_type
!= ARM_FT_INTERWORKED
9219 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9221 /* The return has already been handled
9222 by loading the LR into the PC. */
9229 switch ((int) ARM_FUNC_TYPE (func_type
))
9233 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9236 case ARM_FT_INTERWORKED
:
9237 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9240 case ARM_FT_EXCEPTION
:
9241 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9245 /* Use bx if it's available. */
9246 if (arm_arch5
|| arm_arch4t
)
9247 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9249 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9253 output_asm_insn (instr
, & operand
);
9259 /* Write the function name into the code section, directly preceding
9260 the function prologue.
9262 Code will be output similar to this:
9264 .ascii "arm_poke_function_name", 0
9267 .word 0xff000000 + (t1 - t0)
9268 arm_poke_function_name
9270 stmfd sp!, {fp, ip, lr, pc}
9273 When performing a stack backtrace, code can inspect the value
9274 of 'pc' stored at 'fp' + 0. If the trace function then looks
9275 at location pc - 12 and the top 8 bits are set, then we know
9276 that there is a function name embedded immediately preceding this
9277 location and has length ((pc[-3]) & 0xff000000).
9279 We assume that pc is declared as a pointer to an unsigned long.
9281 It is of no benefit to output the function name if we are assembling
9282 a leaf function. These function types will not contain a stack
9283 backtrace structure, therefore it is not possible to determine the
9286 arm_poke_function_name (FILE *stream
, const char *name
)
9288 unsigned long alignlength
;
9289 unsigned long length
;
9292 length
= strlen (name
) + 1;
9293 alignlength
= ROUND_UP_WORD (length
);
9295 ASM_OUTPUT_ASCII (stream
, name
, length
);
9296 ASM_OUTPUT_ALIGN (stream
, 2);
9297 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9298 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9301 /* Place some comments into the assembler stream
9302 describing the current function. */
9304 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9306 unsigned long func_type
;
9310 thumb_output_function_prologue (f
, frame_size
);
9315 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9317 func_type
= arm_current_func_type ();
9319 switch ((int) ARM_FUNC_TYPE (func_type
))
9324 case ARM_FT_INTERWORKED
:
9325 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9328 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9331 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9333 case ARM_FT_EXCEPTION
:
9334 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9338 if (IS_NAKED (func_type
))
9339 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9341 if (IS_VOLATILE (func_type
))
9342 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9344 if (IS_NESTED (func_type
))
9345 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9347 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9348 current_function_args_size
,
9349 current_function_pretend_args_size
, frame_size
);
9351 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9352 frame_pointer_needed
,
9353 cfun
->machine
->uses_anonymous_args
);
9355 if (cfun
->machine
->lr_save_eliminated
)
9356 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9358 if (current_function_calls_eh_return
)
9359 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9361 #ifdef AOF_ASSEMBLER
9363 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9366 return_used_this_function
= 0;
9370 arm_output_epilogue (rtx sibling
)
9373 unsigned long saved_regs_mask
;
9374 unsigned long func_type
;
9375 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9376 frame that is $fp + 4 for a non-variadic function. */
9377 int floats_offset
= 0;
9379 FILE * f
= asm_out_file
;
9380 unsigned int lrm_count
= 0;
9381 int really_return
= (sibling
== NULL
);
9383 arm_stack_offsets
*offsets
;
9385 /* If we have already generated the return instruction
9386 then it is futile to generate anything else. */
9387 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9390 func_type
= arm_current_func_type ();
9392 if (IS_NAKED (func_type
))
9393 /* Naked functions don't have epilogues. */
9396 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9400 /* A volatile function should never return. Call abort. */
9401 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9402 assemble_external_libcall (op
);
9403 output_asm_insn ("bl\t%a0", &op
);
9408 /* If we are throwing an exception, then we really must be doing a
9409 return, so we can't tail-call. */
9410 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9412 offsets
= arm_get_frame_offsets ();
9413 saved_regs_mask
= arm_compute_save_reg_mask ();
9416 lrm_count
= bit_count (saved_regs_mask
);
9418 floats_offset
= offsets
->saved_args
;
9419 /* Compute how far away the floats will be. */
9420 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9421 if (saved_regs_mask
& (1 << reg
))
9424 if (frame_pointer_needed
)
9426 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9427 int vfp_offset
= offsets
->frame
;
9429 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9431 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9432 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9434 floats_offset
+= 12;
9435 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9436 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9441 start_reg
= LAST_FPA_REGNUM
;
9443 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9445 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9447 floats_offset
+= 12;
9449 /* We can't unstack more than four registers at once. */
9450 if (start_reg
- reg
== 3)
9452 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9453 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9454 start_reg
= reg
- 1;
9459 if (reg
!= start_reg
)
9460 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9461 reg
+ 1, start_reg
- reg
,
9462 FP_REGNUM
, floats_offset
- vfp_offset
);
9463 start_reg
= reg
- 1;
9467 /* Just in case the last register checked also needs unstacking. */
9468 if (reg
!= start_reg
)
9469 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9470 reg
+ 1, start_reg
- reg
,
9471 FP_REGNUM
, floats_offset
- vfp_offset
);
9474 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9478 /* The fldmx insn does not have base+offset addressing modes,
9479 so we use IP to hold the address. */
9480 saved_size
= arm_get_vfp_saved_size ();
9484 floats_offset
+= saved_size
;
9485 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9486 FP_REGNUM
, floats_offset
- vfp_offset
);
9488 start_reg
= FIRST_VFP_REGNUM
;
9489 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9491 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9492 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9494 if (start_reg
!= reg
)
9495 arm_output_fldmx (f
, IP_REGNUM
,
9496 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9497 (reg
- start_reg
) / 2);
9498 start_reg
= reg
+ 2;
9501 if (start_reg
!= reg
)
9502 arm_output_fldmx (f
, IP_REGNUM
,
9503 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9504 (reg
- start_reg
) / 2);
9509 /* The frame pointer is guaranteed to be non-double-word aligned.
9510 This is because it is set to (old_stack_pointer - 4) and the
9511 old_stack_pointer was double word aligned. Thus the offset to
9512 the iWMMXt registers to be loaded must also be non-double-word
9513 sized, so that the resultant address *is* double-word aligned.
9514 We can ignore floats_offset since that was already included in
9515 the live_regs_mask. */
9516 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9518 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9519 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9521 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9522 reg
, FP_REGNUM
, lrm_count
* 4);
9527 /* saved_regs_mask should contain the IP, which at the time of stack
9528 frame generation actually contains the old stack pointer. So a
9529 quick way to unwind the stack is just pop the IP register directly
9530 into the stack pointer. */
9531 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9532 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9533 saved_regs_mask
|= (1 << SP_REGNUM
);
9535 /* There are two registers left in saved_regs_mask - LR and PC. We
9536 only need to restore the LR register (the return address), but to
9537 save time we can load it directly into the PC, unless we need a
9538 special function exit sequence, or we are not really returning. */
9540 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9541 && !current_function_calls_eh_return
)
9542 /* Delete the LR from the register mask, so that the LR on
9543 the stack is loaded into the PC in the register mask. */
9544 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9546 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9548 /* We must use SP as the base register, because SP is one of the
9549 registers being restored. If an interrupt or page fault
9550 happens in the ldm instruction, the SP might or might not
9551 have been restored. That would be bad, as then SP will no
9552 longer indicate the safe area of stack, and we can get stack
9553 corruption. Using SP as the base register means that it will
9554 be reset correctly to the original value, should an interrupt
9555 occur. If the stack pointer already points at the right
9556 place, then omit the subtraction. */
9557 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9558 || current_function_calls_alloca
)
9559 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9560 4 * bit_count (saved_regs_mask
));
9561 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9563 if (IS_INTERRUPT (func_type
))
9564 /* Interrupt handlers will have pushed the
9565 IP onto the stack, so restore it now. */
9566 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9570 /* Restore stack pointer if necessary. */
9571 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9573 operands
[0] = operands
[1] = stack_pointer_rtx
;
9574 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9575 output_add_immediate (operands
);
9578 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9580 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9581 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9582 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9587 start_reg
= FIRST_FPA_REGNUM
;
9589 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9591 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9593 if (reg
- start_reg
== 3)
9595 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9596 start_reg
, SP_REGNUM
);
9597 start_reg
= reg
+ 1;
9602 if (reg
!= start_reg
)
9603 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9604 start_reg
, reg
- start_reg
,
9607 start_reg
= reg
+ 1;
9611 /* Just in case the last register checked also needs unstacking. */
9612 if (reg
!= start_reg
)
9613 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9614 start_reg
, reg
- start_reg
, SP_REGNUM
);
9617 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9619 start_reg
= FIRST_VFP_REGNUM
;
9620 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9622 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9623 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9625 if (start_reg
!= reg
)
9626 arm_output_fldmx (f
, SP_REGNUM
,
9627 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9628 (reg
- start_reg
) / 2);
9629 start_reg
= reg
+ 2;
9632 if (start_reg
!= reg
)
9633 arm_output_fldmx (f
, SP_REGNUM
,
9634 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9635 (reg
- start_reg
) / 2);
9638 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9639 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9640 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9642 /* If we can, restore the LR into the PC. */
9643 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9645 && current_function_pretend_args_size
== 0
9646 && saved_regs_mask
& (1 << LR_REGNUM
)
9647 && !current_function_calls_eh_return
)
9649 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9650 saved_regs_mask
|= (1 << PC_REGNUM
);
9653 /* Load the registers off the stack. If we only have one register
9654 to load use the LDR instruction - it is faster. */
9655 if (saved_regs_mask
== (1 << LR_REGNUM
))
9657 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9659 else if (saved_regs_mask
)
9661 if (saved_regs_mask
& (1 << SP_REGNUM
))
9662 /* Note - write back to the stack register is not enabled
9663 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9664 in the list of registers and if we add writeback the
9665 instruction becomes UNPREDICTABLE. */
9666 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9668 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9671 if (current_function_pretend_args_size
)
9673 /* Unwind the pre-pushed regs. */
9674 operands
[0] = operands
[1] = stack_pointer_rtx
;
9675 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9676 output_add_immediate (operands
);
9680 /* We may have already restored PC directly from the stack. */
9681 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
9684 /* Stack adjustment for exception handler. */
9685 if (current_function_calls_eh_return
)
9686 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
9687 ARM_EH_STACKADJ_REGNUM
);
9689 /* Generate the return instruction. */
9690 switch ((int) ARM_FUNC_TYPE (func_type
))
9694 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
9697 case ARM_FT_EXCEPTION
:
9698 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9701 case ARM_FT_INTERWORKED
:
9702 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9706 if (arm_arch5
|| arm_arch4t
)
9707 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9709 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9717 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9718 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
9720 arm_stack_offsets
*offsets
;
9726 /* Emit any call-via-reg trampolines that are needed for v4t support
9727 of call_reg and call_value_reg type insns. */
9728 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
9730 rtx label
= cfun
->machine
->call_via
[regno
];
9734 function_section (current_function_decl
);
9735 targetm
.asm_out
.internal_label (asm_out_file
, "L",
9736 CODE_LABEL_NUMBER (label
));
9737 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
9741 /* ??? Probably not safe to set this here, since it assumes that a
9742 function will be emitted as assembly immediately after we generate
9743 RTL for it. This does not happen for inline functions. */
9744 return_used_this_function
= 0;
9748 /* We need to take into account any stack-frame rounding. */
9749 offsets
= arm_get_frame_offsets ();
9751 gcc_assert (!use_return_insn (FALSE
, NULL
)
9752 || !return_used_this_function
9753 || offsets
->saved_regs
== offsets
->outgoing_args
9754 || frame_pointer_needed
);
9756 /* Reset the ARM-specific per-function variables. */
9757 after_arm_reorg
= 0;
9761 /* Generate and emit an insn that we will recognize as a push_multi.
9762 Unfortunately, since this insn does not reflect very well the actual
9763 semantics of the operation, we need to annotate the insn for the benefit
9764 of DWARF2 frame unwind information. */
9766 emit_multi_reg_push (unsigned long mask
)
9773 int dwarf_par_index
;
9776 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9777 if (mask
& (1 << i
))
9780 gcc_assert (num_regs
&& num_regs
<= 16);
9782 /* We don't record the PC in the dwarf frame information. */
9783 num_dwarf_regs
= num_regs
;
9784 if (mask
& (1 << PC_REGNUM
))
9787 /* For the body of the insn we are going to generate an UNSPEC in
9788 parallel with several USEs. This allows the insn to be recognized
9789 by the push_multi pattern in the arm.md file. The insn looks
9790 something like this:
9793 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9794 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9795 (use (reg:SI 11 fp))
9796 (use (reg:SI 12 ip))
9797 (use (reg:SI 14 lr))
9798 (use (reg:SI 15 pc))
9801 For the frame note however, we try to be more explicit and actually
9802 show each register being stored into the stack frame, plus a (single)
9803 decrement of the stack pointer. We do it this way in order to be
9804 friendly to the stack unwinding code, which only wants to see a single
9805 stack decrement per instruction. The RTL we generate for the note looks
9806 something like this:
9809 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9810 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9811 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9812 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9813 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9816 This sequence is used both by the code to support stack unwinding for
9817 exceptions handlers and the code to generate dwarf2 frame debugging. */
9819 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
9820 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
9821 dwarf_par_index
= 1;
9823 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9825 if (mask
& (1 << i
))
9827 reg
= gen_rtx_REG (SImode
, i
);
9830 = gen_rtx_SET (VOIDmode
,
9831 gen_frame_mem (BLKmode
,
9832 gen_rtx_PRE_DEC (BLKmode
,
9833 stack_pointer_rtx
)),
9834 gen_rtx_UNSPEC (BLKmode
,
9840 tmp
= gen_rtx_SET (VOIDmode
,
9841 gen_frame_mem (SImode
, stack_pointer_rtx
),
9843 RTX_FRAME_RELATED_P (tmp
) = 1;
9844 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
9852 for (j
= 1, i
++; j
< num_regs
; i
++)
9854 if (mask
& (1 << i
))
9856 reg
= gen_rtx_REG (SImode
, i
);
9858 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
9863 = gen_rtx_SET (VOIDmode
,
9864 gen_frame_mem (SImode
,
9865 plus_constant (stack_pointer_rtx
,
9868 RTX_FRAME_RELATED_P (tmp
) = 1;
9869 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
9876 par
= emit_insn (par
);
9878 tmp
= gen_rtx_SET (SImode
,
9880 gen_rtx_PLUS (SImode
,
9882 GEN_INT (-4 * num_regs
)));
9883 RTX_FRAME_RELATED_P (tmp
) = 1;
9884 XVECEXP (dwarf
, 0, 0) = tmp
;
9886 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9891 /* Calculate the size of the return value that is passed in registers. */
9893 arm_size_return_regs (void)
9895 enum machine_mode mode
;
9897 if (current_function_return_rtx
!= 0)
9898 mode
= GET_MODE (current_function_return_rtx
);
9900 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9902 return GET_MODE_SIZE (mode
);
9906 emit_sfm (int base_reg
, int count
)
9913 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
9914 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
9916 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9919 = gen_rtx_SET (VOIDmode
,
9920 gen_frame_mem (BLKmode
,
9921 gen_rtx_PRE_DEC (BLKmode
,
9922 stack_pointer_rtx
)),
9923 gen_rtx_UNSPEC (BLKmode
,
9926 tmp
= gen_rtx_SET (VOIDmode
,
9927 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
9928 RTX_FRAME_RELATED_P (tmp
) = 1;
9929 XVECEXP (dwarf
, 0, 1) = tmp
;
9931 for (i
= 1; i
< count
; i
++)
9933 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9934 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
9936 tmp
= gen_rtx_SET (VOIDmode
,
9937 gen_frame_mem (XFmode
,
9938 plus_constant (stack_pointer_rtx
,
9941 RTX_FRAME_RELATED_P (tmp
) = 1;
9942 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
9945 tmp
= gen_rtx_SET (VOIDmode
,
9947 gen_rtx_PLUS (SImode
,
9949 GEN_INT (-12 * count
)));
9950 RTX_FRAME_RELATED_P (tmp
) = 1;
9951 XVECEXP (dwarf
, 0, 0) = tmp
;
9953 par
= emit_insn (par
);
9954 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9960 /* Return true if the current function needs to save/restore LR. */
9963 thumb_force_lr_save (void)
9965 return !cfun
->machine
->lr_save_eliminated
9966 && (!leaf_function_p ()
9967 || thumb_far_jump_used_p ()
9968 || regs_ever_live
[LR_REGNUM
]);
9972 /* Compute the distance from register FROM to register TO.
9973 These can be the arg pointer (26), the soft frame pointer (25),
9974 the stack pointer (13) or the hard frame pointer (11).
9975 In thumb mode r7 is used as the soft frame pointer, if needed.
9976 Typical stack layout looks like this:
9978 old stack pointer -> | |
9981 | | saved arguments for
9982 | | vararg functions
9985 hard FP & arg pointer -> | | \
9993 soft frame pointer -> | | /
9998 locals base pointer -> | | /
10003 current stack pointer -> | | /
10006 For a given function some or all of these stack components
10007 may not be needed, giving rise to the possibility of
10008 eliminating some of the registers.
10010 The values returned by this function must reflect the behavior
10011 of arm_expand_prologue() and arm_compute_save_reg_mask().
10013 The sign of the number returned reflects the direction of stack
10014 growth, so the values are positive for all eliminations except
10015 from the soft frame pointer to the hard frame pointer.
10017 SFP may point just inside the local variables block to ensure correct
10021 /* Calculate stack offsets. These are used to calculate register elimination
10022 offsets and in prologue/epilogue code. */
10024 static arm_stack_offsets
*
10025 arm_get_frame_offsets (void)
10027 struct arm_stack_offsets
*offsets
;
10028 unsigned long func_type
;
10031 HOST_WIDE_INT frame_size
;
10033 offsets
= &cfun
->machine
->stack_offsets
;
10035 /* We need to know if we are a leaf function. Unfortunately, it
10036 is possible to be called after start_sequence has been called,
10037 which causes get_insns to return the insns for the sequence,
10038 not the function, which will cause leaf_function_p to return
10039 the incorrect result.
10041 to know about leaf functions once reload has completed, and the
10042 frame size cannot be changed after that time, so we can safely
10043 use the cached value. */
10045 if (reload_completed
)
10048 /* Initially this is the size of the local variables. It will translated
10049 into an offset once we have determined the size of preceding data. */
10050 frame_size
= ROUND_UP_WORD (get_frame_size ());
10052 leaf
= leaf_function_p ();
10054 /* Space for variadic functions. */
10055 offsets
->saved_args
= current_function_pretend_args_size
;
10057 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10061 unsigned int regno
;
10063 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10065 /* We know that SP will be doubleword aligned on entry, and we must
10066 preserve that condition at any subroutine call. We also require the
10067 soft frame pointer to be doubleword aligned. */
10069 if (TARGET_REALLY_IWMMXT
)
10071 /* Check for the call-saved iWMMXt registers. */
10072 for (regno
= FIRST_IWMMXT_REGNUM
;
10073 regno
<= LAST_IWMMXT_REGNUM
;
10075 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10079 func_type
= arm_current_func_type ();
10080 if (! IS_VOLATILE (func_type
))
10082 /* Space for saved FPA registers. */
10083 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10084 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10087 /* Space for saved VFP registers. */
10088 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10089 saved
+= arm_get_vfp_saved_size ();
10092 else /* TARGET_THUMB */
10094 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10095 if (TARGET_BACKTRACE
)
10099 /* Saved registers include the stack frame. */
10100 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10101 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10102 /* A leaf function does not need any stack alignment if it has nothing
10104 if (leaf
&& frame_size
== 0)
10106 offsets
->outgoing_args
= offsets
->soft_frame
;
10110 /* Ensure SFP has the correct alignment. */
10111 if (ARM_DOUBLEWORD_ALIGN
10112 && (offsets
->soft_frame
& 7))
10113 offsets
->soft_frame
+= 4;
10115 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10116 offsets
->outgoing_args
= (offsets
->locals_base
10117 + current_function_outgoing_args_size
);
10119 if (ARM_DOUBLEWORD_ALIGN
)
10121 /* Ensure SP remains doubleword aligned. */
10122 if (offsets
->outgoing_args
& 7)
10123 offsets
->outgoing_args
+= 4;
10124 gcc_assert (!(offsets
->outgoing_args
& 7));
10131 /* Calculate the relative offsets for the different stack pointers. Positive
10132 offsets are in the direction of stack growth. */
10135 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10137 arm_stack_offsets
*offsets
;
10139 offsets
= arm_get_frame_offsets ();
10141 /* OK, now we have enough information to compute the distances.
10142 There must be an entry in these switch tables for each pair
10143 of registers in ELIMINABLE_REGS, even if some of the entries
10144 seem to be redundant or useless. */
10147 case ARG_POINTER_REGNUM
:
10150 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10153 case FRAME_POINTER_REGNUM
:
10154 /* This is the reverse of the soft frame pointer
10155 to hard frame pointer elimination below. */
10156 return offsets
->soft_frame
- offsets
->saved_args
;
10158 case ARM_HARD_FRAME_POINTER_REGNUM
:
10159 /* If there is no stack frame then the hard
10160 frame pointer and the arg pointer coincide. */
10161 if (offsets
->frame
== offsets
->saved_regs
)
10163 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10164 return (frame_pointer_needed
10165 && cfun
->static_chain_decl
!= NULL
10166 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10168 case STACK_POINTER_REGNUM
:
10169 /* If nothing has been pushed on the stack at all
10170 then this will return -4. This *is* correct! */
10171 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10174 gcc_unreachable ();
10176 gcc_unreachable ();
10178 case FRAME_POINTER_REGNUM
:
10181 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10184 case ARM_HARD_FRAME_POINTER_REGNUM
:
10185 /* The hard frame pointer points to the top entry in the
10186 stack frame. The soft frame pointer to the bottom entry
10187 in the stack frame. If there is no stack frame at all,
10188 then they are identical. */
10190 return offsets
->frame
- offsets
->soft_frame
;
10192 case STACK_POINTER_REGNUM
:
10193 return offsets
->outgoing_args
- offsets
->soft_frame
;
10196 gcc_unreachable ();
10198 gcc_unreachable ();
10201 /* You cannot eliminate from the stack pointer.
10202 In theory you could eliminate from the hard frame
10203 pointer to the stack pointer, but this will never
10204 happen, since if a stack frame is not needed the
10205 hard frame pointer will never be used. */
10206 gcc_unreachable ();
10211 /* Generate the prologue instructions for entry into an ARM function. */
10213 arm_expand_prologue (void)
10219 unsigned long live_regs_mask
;
10220 unsigned long func_type
;
10222 int saved_pretend_args
= 0;
10223 int saved_regs
= 0;
10224 unsigned HOST_WIDE_INT args_to_push
;
10225 arm_stack_offsets
*offsets
;
10227 func_type
= arm_current_func_type ();
10229 /* Naked functions don't have prologues. */
10230 if (IS_NAKED (func_type
))
10233 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10234 args_to_push
= current_function_pretend_args_size
;
10236 /* Compute which register we will have to save onto the stack. */
10237 live_regs_mask
= arm_compute_save_reg_mask ();
10239 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10241 if (frame_pointer_needed
)
10243 if (IS_INTERRUPT (func_type
))
10245 /* Interrupt functions must not corrupt any registers.
10246 Creating a frame pointer however, corrupts the IP
10247 register, so we must push it first. */
10248 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10250 /* Do not set RTX_FRAME_RELATED_P on this insn.
10251 The dwarf stack unwinding code only wants to see one
10252 stack decrement per function, and this is not it. If
10253 this instruction is labeled as being part of the frame
10254 creation sequence then dwarf2out_frame_debug_expr will
10255 die when it encounters the assignment of IP to FP
10256 later on, since the use of SP here establishes SP as
10257 the CFA register and not IP.
10259 Anyway this instruction is not really part of the stack
10260 frame creation although it is part of the prologue. */
10262 else if (IS_NESTED (func_type
))
10264 /* The Static chain register is the same as the IP register
10265 used as a scratch register during stack frame creation.
10266 To get around this need to find somewhere to store IP
10267 whilst the frame is being created. We try the following
10270 1. The last argument register.
10271 2. A slot on the stack above the frame. (This only
10272 works if the function is not a varargs function).
10273 3. Register r3, after pushing the argument registers
10276 Note - we only need to tell the dwarf2 backend about the SP
10277 adjustment in the second variant; the static chain register
10278 doesn't need to be unwound, as it doesn't contain a value
10279 inherited from the caller. */
10281 if (regs_ever_live
[3] == 0)
10283 insn
= gen_rtx_REG (SImode
, 3);
10284 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10285 insn
= emit_insn (insn
);
10287 else if (args_to_push
== 0)
10290 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10291 insn
= gen_frame_mem (SImode
, insn
);
10292 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10293 insn
= emit_insn (insn
);
10297 /* Just tell the dwarf backend that we adjusted SP. */
10298 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10299 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10300 GEN_INT (-fp_offset
)));
10301 RTX_FRAME_RELATED_P (insn
) = 1;
10302 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10303 dwarf
, REG_NOTES (insn
));
10307 /* Store the args on the stack. */
10308 if (cfun
->machine
->uses_anonymous_args
)
10309 insn
= emit_multi_reg_push
10310 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10313 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10314 GEN_INT (- args_to_push
)));
10316 RTX_FRAME_RELATED_P (insn
) = 1;
10318 saved_pretend_args
= 1;
10319 fp_offset
= args_to_push
;
10322 /* Now reuse r3 to preserve IP. */
10323 insn
= gen_rtx_REG (SImode
, 3);
10324 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10325 (void) emit_insn (insn
);
10331 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10332 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10335 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10337 insn
= emit_insn (insn
);
10338 RTX_FRAME_RELATED_P (insn
) = 1;
10343 /* Push the argument registers, or reserve space for them. */
10344 if (cfun
->machine
->uses_anonymous_args
)
10345 insn
= emit_multi_reg_push
10346 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10349 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10350 GEN_INT (- args_to_push
)));
10351 RTX_FRAME_RELATED_P (insn
) = 1;
10354 /* If this is an interrupt service routine, and the link register
10355 is going to be pushed, and we are not creating a stack frame,
10356 (which would involve an extra push of IP and a pop in the epilogue)
10357 subtracting four from LR now will mean that the function return
10358 can be done with a single instruction. */
10359 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10360 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10361 && ! frame_pointer_needed
)
10362 emit_insn (gen_rtx_SET (SImode
,
10363 gen_rtx_REG (SImode
, LR_REGNUM
),
10364 gen_rtx_PLUS (SImode
,
10365 gen_rtx_REG (SImode
, LR_REGNUM
),
10368 if (live_regs_mask
)
10370 insn
= emit_multi_reg_push (live_regs_mask
);
10371 saved_regs
+= bit_count (live_regs_mask
) * 4;
10372 RTX_FRAME_RELATED_P (insn
) = 1;
10376 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10377 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10379 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10380 insn
= gen_frame_mem (V2SImode
, insn
);
10381 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10382 gen_rtx_REG (V2SImode
, reg
)));
10383 RTX_FRAME_RELATED_P (insn
) = 1;
10387 if (! IS_VOLATILE (func_type
))
10391 /* Save any floating point call-saved registers used by this
10393 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10395 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10396 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10398 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10399 insn
= gen_frame_mem (XFmode
, insn
);
10400 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10401 gen_rtx_REG (XFmode
, reg
)));
10402 RTX_FRAME_RELATED_P (insn
) = 1;
10408 start_reg
= LAST_FPA_REGNUM
;
10410 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10412 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10414 if (start_reg
- reg
== 3)
10416 insn
= emit_sfm (reg
, 4);
10417 RTX_FRAME_RELATED_P (insn
) = 1;
10419 start_reg
= reg
- 1;
10424 if (start_reg
!= reg
)
10426 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10427 RTX_FRAME_RELATED_P (insn
) = 1;
10428 saved_regs
+= (start_reg
- reg
) * 12;
10430 start_reg
= reg
- 1;
10434 if (start_reg
!= reg
)
10436 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10437 saved_regs
+= (start_reg
- reg
) * 12;
10438 RTX_FRAME_RELATED_P (insn
) = 1;
10441 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10443 start_reg
= FIRST_VFP_REGNUM
;
10445 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10447 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10448 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10450 if (start_reg
!= reg
)
10451 saved_regs
+= vfp_emit_fstmx (start_reg
,
10452 (reg
- start_reg
) / 2);
10453 start_reg
= reg
+ 2;
10456 if (start_reg
!= reg
)
10457 saved_regs
+= vfp_emit_fstmx (start_reg
,
10458 (reg
- start_reg
) / 2);
10462 if (frame_pointer_needed
)
10464 /* Create the new frame pointer. */
10465 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10466 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10467 RTX_FRAME_RELATED_P (insn
) = 1;
10469 if (IS_NESTED (func_type
))
10471 /* Recover the static chain register. */
10472 if (regs_ever_live
[3] == 0
10473 || saved_pretend_args
)
10474 insn
= gen_rtx_REG (SImode
, 3);
10475 else /* if (current_function_pretend_args_size == 0) */
10477 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10479 insn
= gen_frame_mem (SImode
, insn
);
10482 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10483 /* Add a USE to stop propagate_one_insn() from barfing. */
10484 emit_insn (gen_prologue_use (ip_rtx
));
10488 offsets
= arm_get_frame_offsets ();
10489 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10491 /* This add can produce multiple insns for a large constant, so we
10492 need to get tricky. */
10493 rtx last
= get_last_insn ();
10495 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10496 - offsets
->outgoing_args
);
10498 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10502 last
= last
? NEXT_INSN (last
) : get_insns ();
10503 RTX_FRAME_RELATED_P (last
) = 1;
10505 while (last
!= insn
);
10507 /* If the frame pointer is needed, emit a special barrier that
10508 will prevent the scheduler from moving stores to the frame
10509 before the stack adjustment. */
10510 if (frame_pointer_needed
)
10511 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10512 hard_frame_pointer_rtx
));
10517 arm_load_pic_register (0UL);
10519 /* If we are profiling, make sure no instructions are scheduled before
10520 the call to mcount. Similarly if the user has requested no
10521 scheduling in the prolog. */
10522 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
10523 emit_insn (gen_blockage ());
10525 /* If the link register is being kept alive, with the return address in it,
10526 then make sure that it does not get reused by the ce2 pass. */
10527 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10529 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10530 cfun
->machine
->lr_save_eliminated
= 1;
10534 /* If CODE is 'd', then the X is a condition operand and the instruction
10535 should only be executed if the condition is true.
10536 if CODE is 'D', then the X is a condition operand and the instruction
10537 should only be executed if the condition is false: however, if the mode
10538 of the comparison is CCFPEmode, then always execute the instruction -- we
10539 do this because in these circumstances !GE does not necessarily imply LT;
10540 in these cases the instruction pattern will take care to make sure that
10541 an instruction containing %d will follow, thereby undoing the effects of
10542 doing this instruction unconditionally.
10543 If CODE is 'N' then X is a floating point operand that must be negated
10545 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10546 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10548 arm_print_operand (FILE *stream
, rtx x
, int code
)
10553 fputs (ASM_COMMENT_START
, stream
);
10557 fputs (user_label_prefix
, stream
);
10561 fputs (REGISTER_PREFIX
, stream
);
10565 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10569 output_operand_lossage ("predicated Thumb instruction");
10572 if (current_insn_predicate
!= NULL
)
10574 output_operand_lossage
10575 ("predicated instruction in conditional sequence");
10579 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10581 else if (current_insn_predicate
)
10583 enum arm_cond_code code
;
10587 output_operand_lossage ("predicated Thumb instruction");
10591 code
= get_arm_condition_code (current_insn_predicate
);
10592 fputs (arm_condition_codes
[code
], stream
);
10599 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10600 r
= REAL_VALUE_NEGATE (r
);
10601 fprintf (stream
, "%s", fp_const_from_val (&r
));
10606 if (GET_CODE (x
) == CONST_INT
)
10609 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10610 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10614 putc ('~', stream
);
10615 output_addr_const (stream
, x
);
10620 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10623 /* Truncate Cirrus shift counts. */
10625 if (GET_CODE (x
) == CONST_INT
)
10627 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10630 arm_print_operand (stream
, x
, 0);
10634 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10640 const char * shift
= shift_op (x
, &val
);
10644 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10646 arm_print_operand (stream
, XEXP (x
, 1), 0);
10648 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10653 /* An explanation of the 'Q', 'R' and 'H' register operands:
10655 In a pair of registers containing a DI or DF value the 'Q'
10656 operand returns the register number of the register containing
10657 the least significant part of the value. The 'R' operand returns
10658 the register number of the register containing the most
10659 significant part of the value.
10661 The 'H' operand returns the higher of the two register numbers.
10662 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10663 same as the 'Q' operand, since the most significant part of the
10664 value is held in the lower number register. The reverse is true
10665 on systems where WORDS_BIG_ENDIAN is false.
10667 The purpose of these operands is to distinguish between cases
10668 where the endian-ness of the values is important (for example
10669 when they are added together), and cases where the endian-ness
10670 is irrelevant, but the order of register operations is important.
10671 For example when loading a value from memory into a register
10672 pair, the endian-ness does not matter. Provided that the value
10673 from the lower memory address is put into the lower numbered
10674 register, and the value from the higher address is put into the
10675 higher numbered register, the load will work regardless of whether
10676 the value being loaded is big-wordian or little-wordian. The
10677 order of the two register loads can matter however, if the address
10678 of the memory location is actually held in one of the registers
10679 being overwritten by the load. */
10681 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10683 output_operand_lossage ("invalid operand for code '%c'", code
);
10687 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
10691 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10693 output_operand_lossage ("invalid operand for code '%c'", code
);
10697 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
10701 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10703 output_operand_lossage ("invalid operand for code '%c'", code
);
10707 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
10711 asm_fprintf (stream
, "%r",
10712 GET_CODE (XEXP (x
, 0)) == REG
10713 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
10717 asm_fprintf (stream
, "{%r-%r}",
10719 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
10723 /* CONST_TRUE_RTX means always -- that's the default. */
10724 if (x
== const_true_rtx
)
10727 if (!COMPARISON_P (x
))
10729 output_operand_lossage ("invalid operand for code '%c'", code
);
10733 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
10738 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
10739 want to do that. */
10740 if (x
== const_true_rtx
)
10742 output_operand_lossage ("instruction never exectued");
10745 if (!COMPARISON_P (x
))
10747 output_operand_lossage ("invalid operand for code '%c'", code
);
10751 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
10752 (get_arm_condition_code (x
))],
10756 /* Cirrus registers can be accessed in a variety of ways:
10757 single floating point (f)
10758 double floating point (d)
10760 64bit integer (dx). */
10761 case 'W': /* Cirrus register in F mode. */
10762 case 'X': /* Cirrus register in D mode. */
10763 case 'Y': /* Cirrus register in FX mode. */
10764 case 'Z': /* Cirrus register in DX mode. */
10765 gcc_assert (GET_CODE (x
) == REG
10766 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
10768 fprintf (stream
, "mv%s%s",
10770 : code
== 'X' ? "d"
10771 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
10775 /* Print cirrus register in the mode specified by the register's mode. */
10778 int mode
= GET_MODE (x
);
10780 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10782 output_operand_lossage ("invalid operand for code '%c'", code
);
10786 fprintf (stream
, "mv%s%s",
10787 mode
== DFmode
? "d"
10788 : mode
== SImode
? "fx"
10789 : mode
== DImode
? "dx"
10790 : "f", reg_names
[REGNO (x
)] + 2);
10796 if (GET_CODE (x
) != REG
10797 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
10798 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
10799 /* Bad value for wCG register number. */
10801 output_operand_lossage ("invalid operand for code '%c'", code
);
10806 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
10809 /* Print an iWMMXt control register name. */
10811 if (GET_CODE (x
) != CONST_INT
10813 || INTVAL (x
) >= 16)
10814 /* Bad value for wC register number. */
10816 output_operand_lossage ("invalid operand for code '%c'", code
);
10822 static const char * wc_reg_names
[16] =
10824 "wCID", "wCon", "wCSSF", "wCASF",
10825 "wC4", "wC5", "wC6", "wC7",
10826 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10827 "wC12", "wC13", "wC14", "wC15"
10830 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
10834 /* Print a VFP double precision register name. */
10837 int mode
= GET_MODE (x
);
10840 if (mode
!= DImode
&& mode
!= DFmode
)
10842 output_operand_lossage ("invalid operand for code '%c'", code
);
10846 if (GET_CODE (x
) != REG
10847 || !IS_VFP_REGNUM (REGNO (x
)))
10849 output_operand_lossage ("invalid operand for code '%c'", code
);
10853 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
10856 output_operand_lossage ("invalid operand for code '%c'", code
);
10860 fprintf (stream
, "d%d", num
>> 1);
10867 output_operand_lossage ("missing operand");
10871 switch (GET_CODE (x
))
10874 asm_fprintf (stream
, "%r", REGNO (x
));
10878 output_memory_reference_mode
= GET_MODE (x
);
10879 output_address (XEXP (x
, 0));
10883 fprintf (stream
, "#%s", fp_immediate_constant (x
));
10887 gcc_assert (GET_CODE (x
) != NEG
);
10888 fputc ('#', stream
);
10889 output_addr_const (stream
, x
);
10895 #ifndef AOF_ASSEMBLER
10896 /* Target hook for assembling integer objects. The ARM version needs to
10897 handle word-sized values specially. */
10899 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10901 if (size
== UNITS_PER_WORD
&& aligned_p
)
10903 fputs ("\t.word\t", asm_out_file
);
10904 output_addr_const (asm_out_file
, x
);
10906 /* Mark symbols as position independent. We only do this in the
10907 .text segment, not in the .data segment. */
10908 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
10909 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
10911 if (GET_CODE (x
) == SYMBOL_REF
10912 && (CONSTANT_POOL_ADDRESS_P (x
)
10913 || SYMBOL_REF_LOCAL_P (x
)))
10914 fputs ("(GOTOFF)", asm_out_file
);
10915 else if (GET_CODE (x
) == LABEL_REF
)
10916 fputs ("(GOTOFF)", asm_out_file
);
10918 fputs ("(GOT)", asm_out_file
);
10920 fputc ('\n', asm_out_file
);
10924 if (arm_vector_mode_supported_p (GET_MODE (x
)))
10928 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
10930 units
= CONST_VECTOR_NUNITS (x
);
10932 switch (GET_MODE (x
))
10934 case V2SImode
: size
= 4; break;
10935 case V4HImode
: size
= 2; break;
10936 case V8QImode
: size
= 1; break;
10938 gcc_unreachable ();
10941 for (i
= 0; i
< units
; i
++)
10945 elt
= CONST_VECTOR_ELT (x
, i
);
10947 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
10953 return default_assemble_integer (x
, size
, aligned_p
);
10957 /* Add a function to the list of static constructors. */
10960 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
10962 if (!TARGET_AAPCS_BASED
)
10964 default_named_section_asm_out_constructor (symbol
, priority
);
10968 /* Put these in the .init_array section, using a special relocation. */
10970 assemble_align (POINTER_SIZE
);
10971 fputs ("\t.word\t", asm_out_file
);
10972 output_addr_const (asm_out_file
, symbol
);
10973 fputs ("(target1)\n", asm_out_file
);
10977 /* A finite state machine takes care of noticing whether or not instructions
10978 can be conditionally executed, and thus decrease execution time and code
10979 size by deleting branch instructions. The fsm is controlled by
10980 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10982 /* The state of the fsm controlling condition codes are:
10983 0: normal, do nothing special
10984 1: make ASM_OUTPUT_OPCODE not output this instruction
10985 2: make ASM_OUTPUT_OPCODE not output this instruction
10986 3: make instructions conditional
10987 4: make instructions conditional
10989 State transitions (state->state by whom under condition):
10990 0 -> 1 final_prescan_insn if the `target' is a label
10991 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10992 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10993 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10994 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10995 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10996 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10997 (the target insn is arm_target_insn).
10999 If the jump clobbers the conditions then we use states 2 and 4.
11001 A similar thing can be done with conditional return insns.
11003 XXX In case the `target' is an unconditional branch, this conditionalising
11004 of the instructions always reduces code size, but not always execution
11005 time. But then, I want to reduce the code size to somewhere near what
11006 /bin/cc produces. */
11008 /* Returns the index of the ARM condition code string in
11009 `arm_condition_codes'. COMPARISON should be an rtx like
11010 `(eq (...) (...))'. */
11011 static enum arm_cond_code
11012 get_arm_condition_code (rtx comparison
)
11014 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11016 enum rtx_code comp_code
= GET_CODE (comparison
);
11018 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11019 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11020 XEXP (comparison
, 1));
11024 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11025 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11026 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11027 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11028 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11029 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11030 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11031 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11032 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11033 case CC_DLTUmode
: code
= ARM_CC
;
11036 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11038 if (comp_code
== EQ
)
11039 return ARM_INVERSE_CONDITION_CODE (code
);
11045 case NE
: return ARM_NE
;
11046 case EQ
: return ARM_EQ
;
11047 case GE
: return ARM_PL
;
11048 case LT
: return ARM_MI
;
11049 default: gcc_unreachable ();
11055 case NE
: return ARM_NE
;
11056 case EQ
: return ARM_EQ
;
11057 default: gcc_unreachable ();
11063 case NE
: return ARM_MI
;
11064 case EQ
: return ARM_PL
;
11065 default: gcc_unreachable ();
11070 /* These encodings assume that AC=1 in the FPA system control
11071 byte. This allows us to handle all cases except UNEQ and
11075 case GE
: return ARM_GE
;
11076 case GT
: return ARM_GT
;
11077 case LE
: return ARM_LS
;
11078 case LT
: return ARM_MI
;
11079 case NE
: return ARM_NE
;
11080 case EQ
: return ARM_EQ
;
11081 case ORDERED
: return ARM_VC
;
11082 case UNORDERED
: return ARM_VS
;
11083 case UNLT
: return ARM_LT
;
11084 case UNLE
: return ARM_LE
;
11085 case UNGT
: return ARM_HI
;
11086 case UNGE
: return ARM_PL
;
11087 /* UNEQ and LTGT do not have a representation. */
11088 case UNEQ
: /* Fall through. */
11089 case LTGT
: /* Fall through. */
11090 default: gcc_unreachable ();
11096 case NE
: return ARM_NE
;
11097 case EQ
: return ARM_EQ
;
11098 case GE
: return ARM_LE
;
11099 case GT
: return ARM_LT
;
11100 case LE
: return ARM_GE
;
11101 case LT
: return ARM_GT
;
11102 case GEU
: return ARM_LS
;
11103 case GTU
: return ARM_CC
;
11104 case LEU
: return ARM_CS
;
11105 case LTU
: return ARM_HI
;
11106 default: gcc_unreachable ();
11112 case LTU
: return ARM_CS
;
11113 case GEU
: return ARM_CC
;
11114 default: gcc_unreachable ();
11120 case NE
: return ARM_NE
;
11121 case EQ
: return ARM_EQ
;
11122 case GE
: return ARM_GE
;
11123 case GT
: return ARM_GT
;
11124 case LE
: return ARM_LE
;
11125 case LT
: return ARM_LT
;
11126 case GEU
: return ARM_CS
;
11127 case GTU
: return ARM_HI
;
11128 case LEU
: return ARM_LS
;
11129 case LTU
: return ARM_CC
;
11130 default: gcc_unreachable ();
11133 default: gcc_unreachable ();
11138 arm_final_prescan_insn (rtx insn
)
11140 /* BODY will hold the body of INSN. */
11141 rtx body
= PATTERN (insn
);
11143 /* This will be 1 if trying to repeat the trick, and things need to be
11144 reversed if it appears to fail. */
11147 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11148 taken are clobbered, even if the rtl suggests otherwise. It also
11149 means that we have to grub around within the jump expression to find
11150 out what the conditions are when the jump isn't taken. */
11151 int jump_clobbers
= 0;
11153 /* If we start with a return insn, we only succeed if we find another one. */
11154 int seeking_return
= 0;
11156 /* START_INSN will hold the insn from where we start looking. This is the
11157 first insn after the following code_label if REVERSE is true. */
11158 rtx start_insn
= insn
;
11160 /* If in state 4, check if the target branch is reached, in order to
11161 change back to state 0. */
11162 if (arm_ccfsm_state
== 4)
11164 if (insn
== arm_target_insn
)
11166 arm_target_insn
= NULL
;
11167 arm_ccfsm_state
= 0;
11172 /* If in state 3, it is possible to repeat the trick, if this insn is an
11173 unconditional branch to a label, and immediately following this branch
11174 is the previous target label which is only used once, and the label this
11175 branch jumps to is not too far off. */
11176 if (arm_ccfsm_state
== 3)
11178 if (simplejump_p (insn
))
11180 start_insn
= next_nonnote_insn (start_insn
);
11181 if (GET_CODE (start_insn
) == BARRIER
)
11183 /* XXX Isn't this always a barrier? */
11184 start_insn
= next_nonnote_insn (start_insn
);
11186 if (GET_CODE (start_insn
) == CODE_LABEL
11187 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11188 && LABEL_NUSES (start_insn
) == 1)
11193 else if (GET_CODE (body
) == RETURN
)
11195 start_insn
= next_nonnote_insn (start_insn
);
11196 if (GET_CODE (start_insn
) == BARRIER
)
11197 start_insn
= next_nonnote_insn (start_insn
);
11198 if (GET_CODE (start_insn
) == CODE_LABEL
11199 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11200 && LABEL_NUSES (start_insn
) == 1)
11203 seeking_return
= 1;
11212 gcc_assert (!arm_ccfsm_state
|| reverse
);
11213 if (GET_CODE (insn
) != JUMP_INSN
)
11216 /* This jump might be paralleled with a clobber of the condition codes
11217 the jump should always come first */
11218 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11219 body
= XVECEXP (body
, 0, 0);
11222 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11223 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11226 int fail
= FALSE
, succeed
= FALSE
;
11227 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11228 int then_not_else
= TRUE
;
11229 rtx this_insn
= start_insn
, label
= 0;
11231 /* If the jump cannot be done with one instruction, we cannot
11232 conditionally execute the instruction in the inverse case. */
11233 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11239 /* Register the insn jumped to. */
11242 if (!seeking_return
)
11243 label
= XEXP (SET_SRC (body
), 0);
11245 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11246 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11247 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11249 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11250 then_not_else
= FALSE
;
11252 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11253 seeking_return
= 1;
11254 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11256 seeking_return
= 1;
11257 then_not_else
= FALSE
;
11260 gcc_unreachable ();
11262 /* See how many insns this branch skips, and what kind of insns. If all
11263 insns are okay, and the label or unconditional branch to the same
11264 label is not too far away, succeed. */
11265 for (insns_skipped
= 0;
11266 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11270 this_insn
= next_nonnote_insn (this_insn
);
11274 switch (GET_CODE (this_insn
))
11277 /* Succeed if it is the target label, otherwise fail since
11278 control falls in from somewhere else. */
11279 if (this_insn
== label
)
11283 arm_ccfsm_state
= 2;
11284 this_insn
= next_nonnote_insn (this_insn
);
11287 arm_ccfsm_state
= 1;
11295 /* Succeed if the following insn is the target label.
11297 If return insns are used then the last insn in a function
11298 will be a barrier. */
11299 this_insn
= next_nonnote_insn (this_insn
);
11300 if (this_insn
&& this_insn
== label
)
11304 arm_ccfsm_state
= 2;
11305 this_insn
= next_nonnote_insn (this_insn
);
11308 arm_ccfsm_state
= 1;
11316 /* The AAPCS says that conditional calls should not be
11317 used since they make interworking inefficient (the
11318 linker can't transform BL<cond> into BLX). That's
11319 only a problem if the machine has BLX. */
11326 /* Succeed if the following insn is the target label, or
11327 if the following two insns are a barrier and the
11329 this_insn
= next_nonnote_insn (this_insn
);
11330 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11331 this_insn
= next_nonnote_insn (this_insn
);
11333 if (this_insn
&& this_insn
== label
11334 && insns_skipped
< max_insns_skipped
)
11338 arm_ccfsm_state
= 2;
11339 this_insn
= next_nonnote_insn (this_insn
);
11342 arm_ccfsm_state
= 1;
11350 /* If this is an unconditional branch to the same label, succeed.
11351 If it is to another label, do nothing. If it is conditional,
11353 /* XXX Probably, the tests for SET and the PC are
11356 scanbody
= PATTERN (this_insn
);
11357 if (GET_CODE (scanbody
) == SET
11358 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11360 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11361 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11363 arm_ccfsm_state
= 2;
11366 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11369 /* Fail if a conditional return is undesirable (e.g. on a
11370 StrongARM), but still allow this if optimizing for size. */
11371 else if (GET_CODE (scanbody
) == RETURN
11372 && !use_return_insn (TRUE
, NULL
)
11375 else if (GET_CODE (scanbody
) == RETURN
11378 arm_ccfsm_state
= 2;
11381 else if (GET_CODE (scanbody
) == PARALLEL
)
11383 switch (get_attr_conds (this_insn
))
11393 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11398 /* Instructions using or affecting the condition codes make it
11400 scanbody
= PATTERN (this_insn
);
11401 if (!(GET_CODE (scanbody
) == SET
11402 || GET_CODE (scanbody
) == PARALLEL
)
11403 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11406 /* A conditional cirrus instruction must be followed by
11407 a non Cirrus instruction. However, since we
11408 conditionalize instructions in this function and by
11409 the time we get here we can't add instructions
11410 (nops), because shorten_branches() has already been
11411 called, we will disable conditionalizing Cirrus
11412 instructions to be safe. */
11413 if (GET_CODE (scanbody
) != USE
11414 && GET_CODE (scanbody
) != CLOBBER
11415 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11425 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11426 arm_target_label
= CODE_LABEL_NUMBER (label
);
11429 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11431 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11433 this_insn
= next_nonnote_insn (this_insn
);
11434 gcc_assert (!this_insn
11435 || (GET_CODE (this_insn
) != BARRIER
11436 && GET_CODE (this_insn
) != CODE_LABEL
));
11440 /* Oh, dear! we ran off the end.. give up. */
11441 recog (PATTERN (insn
), insn
, NULL
);
11442 arm_ccfsm_state
= 0;
11443 arm_target_insn
= NULL
;
11446 arm_target_insn
= this_insn
;
11450 gcc_assert (!reverse
);
11452 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11454 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11455 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11456 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11457 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11461 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11464 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11468 if (reverse
|| then_not_else
)
11469 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11472 /* Restore recog_data (getting the attributes of other insns can
11473 destroy this array, but final.c assumes that it remains intact
11474 across this call; since the insn has been recognized already we
11475 call recog direct). */
11476 recog (PATTERN (insn
), insn
, NULL
);
11480 /* Returns true if REGNO is a valid register
11481 for holding a quantity of type MODE. */
11483 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11485 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11486 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11489 /* For the Thumb we only allow values bigger than SImode in
11490 registers 0 - 6, so that there is always a second low
11491 register available to hold the upper part of the value.
11492 We probably we ought to ensure that the register is the
11493 start of an even numbered register pair. */
11494 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11496 if (IS_CIRRUS_REGNUM (regno
))
11497 /* We have outlawed SI values in Cirrus registers because they
11498 reside in the lower 32 bits, but SF values reside in the
11499 upper 32 bits. This causes gcc all sorts of grief. We can't
11500 even split the registers into pairs because Cirrus SI values
11501 get sign extended to 64bits-- aldyh. */
11502 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11504 if (IS_VFP_REGNUM (regno
))
11506 if (mode
== SFmode
|| mode
== SImode
)
11509 /* DFmode values are only valid in even register pairs. */
11510 if (mode
== DFmode
)
11511 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11515 if (IS_IWMMXT_GR_REGNUM (regno
))
11516 return mode
== SImode
;
11518 if (IS_IWMMXT_REGNUM (regno
))
11519 return VALID_IWMMXT_REG_MODE (mode
);
11521 /* We allow any value to be stored in the general registers.
11522 Restrict doubleword quantities to even register pairs so that we can
11524 if (regno
<= LAST_ARM_REGNUM
)
11525 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11527 if ( regno
== FRAME_POINTER_REGNUM
11528 || regno
== ARG_POINTER_REGNUM
)
11529 /* We only allow integers in the fake hard registers. */
11530 return GET_MODE_CLASS (mode
) == MODE_INT
;
11532 /* The only registers left are the FPA registers
11533 which we only allow to hold FP values. */
11534 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11535 && regno
>= FIRST_FPA_REGNUM
11536 && regno
<= LAST_FPA_REGNUM
;
11540 arm_regno_class (int regno
)
11544 if (regno
== STACK_POINTER_REGNUM
)
11546 if (regno
== CC_REGNUM
)
11553 if ( regno
<= LAST_ARM_REGNUM
11554 || regno
== FRAME_POINTER_REGNUM
11555 || regno
== ARG_POINTER_REGNUM
)
11556 return GENERAL_REGS
;
11558 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11561 if (IS_CIRRUS_REGNUM (regno
))
11562 return CIRRUS_REGS
;
11564 if (IS_VFP_REGNUM (regno
))
11567 if (IS_IWMMXT_REGNUM (regno
))
11568 return IWMMXT_REGS
;
11570 if (IS_IWMMXT_GR_REGNUM (regno
))
11571 return IWMMXT_GR_REGS
;
11576 /* Handle a special case when computing the offset
11577 of an argument from the frame pointer. */
11579 arm_debugger_arg_offset (int value
, rtx addr
)
11583 /* We are only interested if dbxout_parms() failed to compute the offset. */
11587 /* We can only cope with the case where the address is held in a register. */
11588 if (GET_CODE (addr
) != REG
)
11591 /* If we are using the frame pointer to point at the argument, then
11592 an offset of 0 is correct. */
11593 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11596 /* If we are using the stack pointer to point at the
11597 argument, then an offset of 0 is correct. */
11598 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11599 && REGNO (addr
) == SP_REGNUM
)
11602 /* Oh dear. The argument is pointed to by a register rather
11603 than being held in a register, or being stored at a known
11604 offset from the frame pointer. Since GDB only understands
11605 those two kinds of argument we must translate the address
11606 held in the register into an offset from the frame pointer.
11607 We do this by searching through the insns for the function
11608 looking to see where this register gets its value. If the
11609 register is initialized from the frame pointer plus an offset
11610 then we are in luck and we can continue, otherwise we give up.
11612 This code is exercised by producing debugging information
11613 for a function with arguments like this:
11615 double func (double a, double b, int c, double d) {return d;}
11617 Without this code the stab for parameter 'd' will be set to
11618 an offset of 0 from the frame pointer, rather than 8. */
11620 /* The if() statement says:
11622 If the insn is a normal instruction
11623 and if the insn is setting the value in a register
11624 and if the register being set is the register holding the address of the argument
11625 and if the address is computing by an addition
11626 that involves adding to a register
11627 which is the frame pointer
11632 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11634 if ( GET_CODE (insn
) == INSN
11635 && GET_CODE (PATTERN (insn
)) == SET
11636 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11637 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11638 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11639 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11640 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11643 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11652 warning (0, "unable to compute real location of stacked parameter");
11653 value
= 8; /* XXX magic hack */
11659 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11662 if ((MASK) & insn_flags) \
11663 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11664 BUILT_IN_MD, NULL, NULL_TREE); \
11668 struct builtin_description
11670 const unsigned int mask
;
11671 const enum insn_code icode
;
11672 const char * const name
;
11673 const enum arm_builtins code
;
11674 const enum rtx_code comparison
;
11675 const unsigned int flag
;
11678 static const struct builtin_description bdesc_2arg
[] =
11680 #define IWMMXT_BUILTIN(code, string, builtin) \
11681 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11682 ARM_BUILTIN_##builtin, 0, 0 },
11684 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
11685 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
11686 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
11687 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
11688 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
11689 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
11690 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
11691 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
11692 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
11693 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
11694 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
11695 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
11696 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
11697 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
11698 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
11699 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
11700 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
11701 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
11702 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
11703 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
11704 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
11705 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
11706 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
11707 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
11708 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
11709 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
11710 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
11711 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
11712 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
11713 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
11714 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
11715 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
11716 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
11717 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
11718 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
11719 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
11720 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
11721 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
11722 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
11723 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
11724 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
11725 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
11726 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
11727 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
11728 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
11729 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
11730 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
11731 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
11732 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
11733 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
11734 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
11735 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
11736 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
11737 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
11738 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
11739 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
11740 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
11741 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
11743 #define IWMMXT_BUILTIN2(code, builtin) \
11744 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11746 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
11747 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
11748 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
11749 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
11750 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
11751 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
11752 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
11753 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
11754 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
11755 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
11756 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
11757 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
11758 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
11759 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
11760 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
11761 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
11762 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
11763 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
11764 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
11765 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
11766 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
11767 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
11768 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
11769 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
11770 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
11771 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
11772 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
11773 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
11774 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
11775 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
11776 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
11777 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
11780 static const struct builtin_description bdesc_1arg
[] =
11782 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
11783 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
11784 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
11785 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
11786 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
11787 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
11788 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
11789 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
11790 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
11791 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
11792 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
11793 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
11794 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
11795 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
11796 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
11797 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
11798 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
11799 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
11802 /* Set up all the iWMMXt builtins. This is
11803 not called if TARGET_IWMMXT is zero. */
11806 arm_init_iwmmxt_builtins (void)
11808 const struct builtin_description
* d
;
11810 tree endlink
= void_list_node
;
11812 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
11813 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
11814 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
11817 = build_function_type (integer_type_node
,
11818 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
11819 tree v8qi_ftype_v8qi_v8qi_int
11820 = build_function_type (V8QI_type_node
,
11821 tree_cons (NULL_TREE
, V8QI_type_node
,
11822 tree_cons (NULL_TREE
, V8QI_type_node
,
11823 tree_cons (NULL_TREE
,
11826 tree v4hi_ftype_v4hi_int
11827 = build_function_type (V4HI_type_node
,
11828 tree_cons (NULL_TREE
, V4HI_type_node
,
11829 tree_cons (NULL_TREE
, integer_type_node
,
11831 tree v2si_ftype_v2si_int
11832 = build_function_type (V2SI_type_node
,
11833 tree_cons (NULL_TREE
, V2SI_type_node
,
11834 tree_cons (NULL_TREE
, integer_type_node
,
11836 tree v2si_ftype_di_di
11837 = build_function_type (V2SI_type_node
,
11838 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11839 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11841 tree di_ftype_di_int
11842 = build_function_type (long_long_integer_type_node
,
11843 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11844 tree_cons (NULL_TREE
, integer_type_node
,
11846 tree di_ftype_di_int_int
11847 = build_function_type (long_long_integer_type_node
,
11848 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11849 tree_cons (NULL_TREE
, integer_type_node
,
11850 tree_cons (NULL_TREE
,
11853 tree int_ftype_v8qi
11854 = build_function_type (integer_type_node
,
11855 tree_cons (NULL_TREE
, V8QI_type_node
,
11857 tree int_ftype_v4hi
11858 = build_function_type (integer_type_node
,
11859 tree_cons (NULL_TREE
, V4HI_type_node
,
11861 tree int_ftype_v2si
11862 = build_function_type (integer_type_node
,
11863 tree_cons (NULL_TREE
, V2SI_type_node
,
11865 tree int_ftype_v8qi_int
11866 = build_function_type (integer_type_node
,
11867 tree_cons (NULL_TREE
, V8QI_type_node
,
11868 tree_cons (NULL_TREE
, integer_type_node
,
11870 tree int_ftype_v4hi_int
11871 = build_function_type (integer_type_node
,
11872 tree_cons (NULL_TREE
, V4HI_type_node
,
11873 tree_cons (NULL_TREE
, integer_type_node
,
11875 tree int_ftype_v2si_int
11876 = build_function_type (integer_type_node
,
11877 tree_cons (NULL_TREE
, V2SI_type_node
,
11878 tree_cons (NULL_TREE
, integer_type_node
,
11880 tree v8qi_ftype_v8qi_int_int
11881 = build_function_type (V8QI_type_node
,
11882 tree_cons (NULL_TREE
, V8QI_type_node
,
11883 tree_cons (NULL_TREE
, integer_type_node
,
11884 tree_cons (NULL_TREE
,
11887 tree v4hi_ftype_v4hi_int_int
11888 = build_function_type (V4HI_type_node
,
11889 tree_cons (NULL_TREE
, V4HI_type_node
,
11890 tree_cons (NULL_TREE
, integer_type_node
,
11891 tree_cons (NULL_TREE
,
11894 tree v2si_ftype_v2si_int_int
11895 = build_function_type (V2SI_type_node
,
11896 tree_cons (NULL_TREE
, V2SI_type_node
,
11897 tree_cons (NULL_TREE
, integer_type_node
,
11898 tree_cons (NULL_TREE
,
11901 /* Miscellaneous. */
11902 tree v8qi_ftype_v4hi_v4hi
11903 = build_function_type (V8QI_type_node
,
11904 tree_cons (NULL_TREE
, V4HI_type_node
,
11905 tree_cons (NULL_TREE
, V4HI_type_node
,
11907 tree v4hi_ftype_v2si_v2si
11908 = build_function_type (V4HI_type_node
,
11909 tree_cons (NULL_TREE
, V2SI_type_node
,
11910 tree_cons (NULL_TREE
, V2SI_type_node
,
11912 tree v2si_ftype_v4hi_v4hi
11913 = build_function_type (V2SI_type_node
,
11914 tree_cons (NULL_TREE
, V4HI_type_node
,
11915 tree_cons (NULL_TREE
, V4HI_type_node
,
11917 tree v2si_ftype_v8qi_v8qi
11918 = build_function_type (V2SI_type_node
,
11919 tree_cons (NULL_TREE
, V8QI_type_node
,
11920 tree_cons (NULL_TREE
, V8QI_type_node
,
11922 tree v4hi_ftype_v4hi_di
11923 = build_function_type (V4HI_type_node
,
11924 tree_cons (NULL_TREE
, V4HI_type_node
,
11925 tree_cons (NULL_TREE
,
11926 long_long_integer_type_node
,
11928 tree v2si_ftype_v2si_di
11929 = build_function_type (V2SI_type_node
,
11930 tree_cons (NULL_TREE
, V2SI_type_node
,
11931 tree_cons (NULL_TREE
,
11932 long_long_integer_type_node
,
11934 tree void_ftype_int_int
11935 = build_function_type (void_type_node
,
11936 tree_cons (NULL_TREE
, integer_type_node
,
11937 tree_cons (NULL_TREE
, integer_type_node
,
11940 = build_function_type (long_long_unsigned_type_node
, endlink
);
11942 = build_function_type (long_long_integer_type_node
,
11943 tree_cons (NULL_TREE
, V8QI_type_node
,
11946 = build_function_type (long_long_integer_type_node
,
11947 tree_cons (NULL_TREE
, V4HI_type_node
,
11950 = build_function_type (long_long_integer_type_node
,
11951 tree_cons (NULL_TREE
, V2SI_type_node
,
11953 tree v2si_ftype_v4hi
11954 = build_function_type (V2SI_type_node
,
11955 tree_cons (NULL_TREE
, V4HI_type_node
,
11957 tree v4hi_ftype_v8qi
11958 = build_function_type (V4HI_type_node
,
11959 tree_cons (NULL_TREE
, V8QI_type_node
,
11962 tree di_ftype_di_v4hi_v4hi
11963 = build_function_type (long_long_unsigned_type_node
,
11964 tree_cons (NULL_TREE
,
11965 long_long_unsigned_type_node
,
11966 tree_cons (NULL_TREE
, V4HI_type_node
,
11967 tree_cons (NULL_TREE
,
11971 tree di_ftype_v4hi_v4hi
11972 = build_function_type (long_long_unsigned_type_node
,
11973 tree_cons (NULL_TREE
, V4HI_type_node
,
11974 tree_cons (NULL_TREE
, V4HI_type_node
,
11977 /* Normal vector binops. */
11978 tree v8qi_ftype_v8qi_v8qi
11979 = build_function_type (V8QI_type_node
,
11980 tree_cons (NULL_TREE
, V8QI_type_node
,
11981 tree_cons (NULL_TREE
, V8QI_type_node
,
11983 tree v4hi_ftype_v4hi_v4hi
11984 = build_function_type (V4HI_type_node
,
11985 tree_cons (NULL_TREE
, V4HI_type_node
,
11986 tree_cons (NULL_TREE
, V4HI_type_node
,
11988 tree v2si_ftype_v2si_v2si
11989 = build_function_type (V2SI_type_node
,
11990 tree_cons (NULL_TREE
, V2SI_type_node
,
11991 tree_cons (NULL_TREE
, V2SI_type_node
,
11993 tree di_ftype_di_di
11994 = build_function_type (long_long_unsigned_type_node
,
11995 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
11996 tree_cons (NULL_TREE
,
11997 long_long_unsigned_type_node
,
12000 /* Add all builtins that are more or less simple operations on two
12002 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12004 /* Use one of the operands; the target can have a different mode for
12005 mask-generating compares. */
12006 enum machine_mode mode
;
12012 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12017 type
= v8qi_ftype_v8qi_v8qi
;
12020 type
= v4hi_ftype_v4hi_v4hi
;
12023 type
= v2si_ftype_v2si_v2si
;
12026 type
= di_ftype_di_di
;
12030 gcc_unreachable ();
12033 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12036 /* Add the remaining MMX insns with somewhat more complicated types. */
12037 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12038 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12039 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12041 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12042 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12043 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12044 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12045 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12046 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12048 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12049 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12050 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12051 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12052 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12053 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12055 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12056 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12057 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12058 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12059 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12060 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12062 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12063 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12064 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12065 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12066 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12067 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12069 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12071 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12072 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12073 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12074 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12076 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12077 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12078 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12079 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12080 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12081 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12082 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12083 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12084 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12086 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12087 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12088 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12090 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12091 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12092 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12094 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12095 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12096 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12097 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12098 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12099 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12101 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12102 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12103 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12104 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12105 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12106 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12107 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12108 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12109 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12110 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12111 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12112 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12114 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12115 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12116 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12117 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12119 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12120 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12121 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12122 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12123 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12124 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12125 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12129 arm_init_builtins (void)
12131 if (TARGET_REALLY_IWMMXT
)
12132 arm_init_iwmmxt_builtins ();
12135 /* Errors in the source file can cause expand_expr to return const0_rtx
12136 where we expect a vector. To avoid crashing, use one of the vector
12137 clear instructions. */
12140 safe_vector_operand (rtx x
, enum machine_mode mode
)
12142 if (x
!= const0_rtx
)
12144 x
= gen_reg_rtx (mode
);
12146 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12147 : gen_rtx_SUBREG (DImode
, x
, 0)));
12151 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12154 arm_expand_binop_builtin (enum insn_code icode
,
12155 tree arglist
, rtx target
)
12158 tree arg0
= TREE_VALUE (arglist
);
12159 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12160 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12161 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12162 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12163 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12164 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12166 if (VECTOR_MODE_P (mode0
))
12167 op0
= safe_vector_operand (op0
, mode0
);
12168 if (VECTOR_MODE_P (mode1
))
12169 op1
= safe_vector_operand (op1
, mode1
);
12172 || GET_MODE (target
) != tmode
12173 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12174 target
= gen_reg_rtx (tmode
);
12176 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12178 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12179 op0
= copy_to_mode_reg (mode0
, op0
);
12180 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12181 op1
= copy_to_mode_reg (mode1
, op1
);
12183 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12190 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12193 arm_expand_unop_builtin (enum insn_code icode
,
12194 tree arglist
, rtx target
, int do_load
)
12197 tree arg0
= TREE_VALUE (arglist
);
12198 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12199 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12200 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12203 || GET_MODE (target
) != tmode
12204 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12205 target
= gen_reg_rtx (tmode
);
12207 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12210 if (VECTOR_MODE_P (mode0
))
12211 op0
= safe_vector_operand (op0
, mode0
);
12213 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12214 op0
= copy_to_mode_reg (mode0
, op0
);
12217 pat
= GEN_FCN (icode
) (target
, op0
);
12224 /* Expand an expression EXP that calls a built-in function,
12225 with result going to TARGET if that's convenient
12226 (and in mode MODE if that's convenient).
12227 SUBTARGET may be used as the target for computing one of EXP's operands.
12228 IGNORE is nonzero if the value is to be ignored. */
12231 arm_expand_builtin (tree exp
,
12233 rtx subtarget ATTRIBUTE_UNUSED
,
12234 enum machine_mode mode ATTRIBUTE_UNUSED
,
12235 int ignore ATTRIBUTE_UNUSED
)
12237 const struct builtin_description
* d
;
12238 enum insn_code icode
;
12239 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12240 tree arglist
= TREE_OPERAND (exp
, 1);
12248 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12250 enum machine_mode tmode
;
12251 enum machine_mode mode0
;
12252 enum machine_mode mode1
;
12253 enum machine_mode mode2
;
12257 case ARM_BUILTIN_TEXTRMSB
:
12258 case ARM_BUILTIN_TEXTRMUB
:
12259 case ARM_BUILTIN_TEXTRMSH
:
12260 case ARM_BUILTIN_TEXTRMUH
:
12261 case ARM_BUILTIN_TEXTRMSW
:
12262 case ARM_BUILTIN_TEXTRMUW
:
12263 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12264 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12265 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12266 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12267 : CODE_FOR_iwmmxt_textrmw
);
12269 arg0
= TREE_VALUE (arglist
);
12270 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12271 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12272 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12273 tmode
= insn_data
[icode
].operand
[0].mode
;
12274 mode0
= insn_data
[icode
].operand
[1].mode
;
12275 mode1
= insn_data
[icode
].operand
[2].mode
;
12277 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12278 op0
= copy_to_mode_reg (mode0
, op0
);
12279 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12281 /* @@@ better error message */
12282 error ("selector must be an immediate");
12283 return gen_reg_rtx (tmode
);
12286 || GET_MODE (target
) != tmode
12287 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12288 target
= gen_reg_rtx (tmode
);
12289 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12295 case ARM_BUILTIN_TINSRB
:
12296 case ARM_BUILTIN_TINSRH
:
12297 case ARM_BUILTIN_TINSRW
:
12298 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12299 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12300 : CODE_FOR_iwmmxt_tinsrw
);
12301 arg0
= TREE_VALUE (arglist
);
12302 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12303 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12304 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12305 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12306 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12307 tmode
= insn_data
[icode
].operand
[0].mode
;
12308 mode0
= insn_data
[icode
].operand
[1].mode
;
12309 mode1
= insn_data
[icode
].operand
[2].mode
;
12310 mode2
= insn_data
[icode
].operand
[3].mode
;
12312 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12313 op0
= copy_to_mode_reg (mode0
, op0
);
12314 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12315 op1
= copy_to_mode_reg (mode1
, op1
);
12316 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12318 /* @@@ better error message */
12319 error ("selector must be an immediate");
12323 || GET_MODE (target
) != tmode
12324 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12325 target
= gen_reg_rtx (tmode
);
12326 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12332 case ARM_BUILTIN_SETWCX
:
12333 arg0
= TREE_VALUE (arglist
);
12334 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12335 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12336 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12337 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12340 case ARM_BUILTIN_GETWCX
:
12341 arg0
= TREE_VALUE (arglist
);
12342 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12343 target
= gen_reg_rtx (SImode
);
12344 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12347 case ARM_BUILTIN_WSHUFH
:
12348 icode
= CODE_FOR_iwmmxt_wshufh
;
12349 arg0
= TREE_VALUE (arglist
);
12350 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12351 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12352 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12353 tmode
= insn_data
[icode
].operand
[0].mode
;
12354 mode1
= insn_data
[icode
].operand
[1].mode
;
12355 mode2
= insn_data
[icode
].operand
[2].mode
;
12357 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12358 op0
= copy_to_mode_reg (mode1
, op0
);
12359 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12361 /* @@@ better error message */
12362 error ("mask must be an immediate");
12366 || GET_MODE (target
) != tmode
12367 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12368 target
= gen_reg_rtx (tmode
);
12369 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12375 case ARM_BUILTIN_WSADB
:
12376 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12377 case ARM_BUILTIN_WSADH
:
12378 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12379 case ARM_BUILTIN_WSADBZ
:
12380 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12381 case ARM_BUILTIN_WSADHZ
:
12382 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12384 /* Several three-argument builtins. */
12385 case ARM_BUILTIN_WMACS
:
12386 case ARM_BUILTIN_WMACU
:
12387 case ARM_BUILTIN_WALIGN
:
12388 case ARM_BUILTIN_TMIA
:
12389 case ARM_BUILTIN_TMIAPH
:
12390 case ARM_BUILTIN_TMIATT
:
12391 case ARM_BUILTIN_TMIATB
:
12392 case ARM_BUILTIN_TMIABT
:
12393 case ARM_BUILTIN_TMIABB
:
12394 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12395 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12396 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12397 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12398 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12399 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12400 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12401 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12402 : CODE_FOR_iwmmxt_walign
);
12403 arg0
= TREE_VALUE (arglist
);
12404 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12405 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12406 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12407 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12408 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12409 tmode
= insn_data
[icode
].operand
[0].mode
;
12410 mode0
= insn_data
[icode
].operand
[1].mode
;
12411 mode1
= insn_data
[icode
].operand
[2].mode
;
12412 mode2
= insn_data
[icode
].operand
[3].mode
;
12414 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12415 op0
= copy_to_mode_reg (mode0
, op0
);
12416 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12417 op1
= copy_to_mode_reg (mode1
, op1
);
12418 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12419 op2
= copy_to_mode_reg (mode2
, op2
);
12421 || GET_MODE (target
) != tmode
12422 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12423 target
= gen_reg_rtx (tmode
);
12424 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12430 case ARM_BUILTIN_WZERO
:
12431 target
= gen_reg_rtx (DImode
);
12432 emit_insn (gen_iwmmxt_clrdi (target
));
12439 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12440 if (d
->code
== (const enum arm_builtins
) fcode
)
12441 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12443 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12444 if (d
->code
== (const enum arm_builtins
) fcode
)
12445 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12447 /* @@@ Should really do something sensible here. */
12451 /* Return the number (counting from 0) of
12452 the least significant set bit in MASK. */
12455 number_of_first_bit_set (unsigned mask
)
12460 (mask
& (1 << bit
)) == 0;
12467 /* Emit code to push or pop registers to or from the stack. F is the
12468 assembly file. MASK is the registers to push or pop. PUSH is
12469 nonzero if we should push, and zero if we should pop. For debugging
12470 output, if pushing, adjust CFA_OFFSET by the amount of space added
12471 to the stack. REAL_REGS should have the same number of bits set as
12472 MASK, and will be used instead (in the same order) to describe which
12473 registers were saved - this is used to mark the save slots when we
12474 push high registers after moving them to low registers. */
12476 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12477 unsigned long real_regs
)
12480 int lo_mask
= mask
& 0xFF;
12481 int pushed_words
= 0;
12485 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12487 /* Special case. Do not generate a POP PC statement here, do it in
12489 thumb_exit (f
, -1);
12493 if (ARM_EABI_UNWIND_TABLES
&& push
)
12495 fprintf (f
, "\t.save\t{");
12496 for (regno
= 0; regno
< 15; regno
++)
12498 if (real_regs
& (1 << regno
))
12500 if (real_regs
& ((1 << regno
) -1))
12502 asm_fprintf (f
, "%r", regno
);
12505 fprintf (f
, "}\n");
12508 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12510 /* Look at the low registers first. */
12511 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12515 asm_fprintf (f
, "%r", regno
);
12517 if ((lo_mask
& ~1) != 0)
12524 if (push
&& (mask
& (1 << LR_REGNUM
)))
12526 /* Catch pushing the LR. */
12530 asm_fprintf (f
, "%r", LR_REGNUM
);
12534 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12536 /* Catch popping the PC. */
12537 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12538 || current_function_calls_eh_return
)
12540 /* The PC is never poped directly, instead
12541 it is popped into r3 and then BX is used. */
12542 fprintf (f
, "}\n");
12544 thumb_exit (f
, -1);
12553 asm_fprintf (f
, "%r", PC_REGNUM
);
12557 fprintf (f
, "}\n");
12559 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12561 char *l
= dwarf2out_cfi_label ();
12562 int pushed_mask
= real_regs
;
12564 *cfa_offset
+= pushed_words
* 4;
12565 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12568 pushed_mask
= real_regs
;
12569 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12571 if (pushed_mask
& 1)
12572 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12577 /* Generate code to return from a thumb function.
12578 If 'reg_containing_return_addr' is -1, then the return address is
12579 actually on the stack, at the stack pointer. */
12581 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12583 unsigned regs_available_for_popping
;
12584 unsigned regs_to_pop
;
12586 unsigned available
;
12590 int restore_a4
= FALSE
;
12592 /* Compute the registers we need to pop. */
12596 if (reg_containing_return_addr
== -1)
12598 regs_to_pop
|= 1 << LR_REGNUM
;
12602 if (TARGET_BACKTRACE
)
12604 /* Restore the (ARM) frame pointer and stack pointer. */
12605 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12609 /* If there is nothing to pop then just emit the BX instruction and
12611 if (pops_needed
== 0)
12613 if (current_function_calls_eh_return
)
12614 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12616 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12619 /* Otherwise if we are not supporting interworking and we have not created
12620 a backtrace structure and the function was not entered in ARM mode then
12621 just pop the return address straight into the PC. */
12622 else if (!TARGET_INTERWORK
12623 && !TARGET_BACKTRACE
12624 && !is_called_in_ARM_mode (current_function_decl
)
12625 && !current_function_calls_eh_return
)
12627 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12631 /* Find out how many of the (return) argument registers we can corrupt. */
12632 regs_available_for_popping
= 0;
12634 /* If returning via __builtin_eh_return, the bottom three registers
12635 all contain information needed for the return. */
12636 if (current_function_calls_eh_return
)
12640 /* If we can deduce the registers used from the function's
12641 return value. This is more reliable that examining
12642 regs_ever_live[] because that will be set if the register is
12643 ever used in the function, not just if the register is used
12644 to hold a return value. */
12646 if (current_function_return_rtx
!= 0)
12647 mode
= GET_MODE (current_function_return_rtx
);
12649 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12651 size
= GET_MODE_SIZE (mode
);
12655 /* In a void function we can use any argument register.
12656 In a function that returns a structure on the stack
12657 we can use the second and third argument registers. */
12658 if (mode
== VOIDmode
)
12659 regs_available_for_popping
=
12660 (1 << ARG_REGISTER (1))
12661 | (1 << ARG_REGISTER (2))
12662 | (1 << ARG_REGISTER (3));
12664 regs_available_for_popping
=
12665 (1 << ARG_REGISTER (2))
12666 | (1 << ARG_REGISTER (3));
12668 else if (size
<= 4)
12669 regs_available_for_popping
=
12670 (1 << ARG_REGISTER (2))
12671 | (1 << ARG_REGISTER (3));
12672 else if (size
<= 8)
12673 regs_available_for_popping
=
12674 (1 << ARG_REGISTER (3));
12677 /* Match registers to be popped with registers into which we pop them. */
12678 for (available
= regs_available_for_popping
,
12679 required
= regs_to_pop
;
12680 required
!= 0 && available
!= 0;
12681 available
&= ~(available
& - available
),
12682 required
&= ~(required
& - required
))
12685 /* If we have any popping registers left over, remove them. */
12687 regs_available_for_popping
&= ~available
;
12689 /* Otherwise if we need another popping register we can use
12690 the fourth argument register. */
12691 else if (pops_needed
)
12693 /* If we have not found any free argument registers and
12694 reg a4 contains the return address, we must move it. */
12695 if (regs_available_for_popping
== 0
12696 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
12698 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12699 reg_containing_return_addr
= LR_REGNUM
;
12701 else if (size
> 12)
12703 /* Register a4 is being used to hold part of the return value,
12704 but we have dire need of a free, low register. */
12707 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
12710 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
12712 /* The fourth argument register is available. */
12713 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
12719 /* Pop as many registers as we can. */
12720 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12721 regs_available_for_popping
);
12723 /* Process the registers we popped. */
12724 if (reg_containing_return_addr
== -1)
12726 /* The return address was popped into the lowest numbered register. */
12727 regs_to_pop
&= ~(1 << LR_REGNUM
);
12729 reg_containing_return_addr
=
12730 number_of_first_bit_set (regs_available_for_popping
);
12732 /* Remove this register for the mask of available registers, so that
12733 the return address will not be corrupted by further pops. */
12734 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
12737 /* If we popped other registers then handle them here. */
12738 if (regs_available_for_popping
)
12742 /* Work out which register currently contains the frame pointer. */
12743 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12745 /* Move it into the correct place. */
12746 asm_fprintf (f
, "\tmov\t%r, %r\n",
12747 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
12749 /* (Temporarily) remove it from the mask of popped registers. */
12750 regs_available_for_popping
&= ~(1 << frame_pointer
);
12751 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
12753 if (regs_available_for_popping
)
12757 /* We popped the stack pointer as well,
12758 find the register that contains it. */
12759 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12761 /* Move it into the stack register. */
12762 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
12764 /* At this point we have popped all necessary registers, so
12765 do not worry about restoring regs_available_for_popping
12766 to its correct value:
12768 assert (pops_needed == 0)
12769 assert (regs_available_for_popping == (1 << frame_pointer))
12770 assert (regs_to_pop == (1 << STACK_POINTER)) */
12774 /* Since we have just move the popped value into the frame
12775 pointer, the popping register is available for reuse, and
12776 we know that we still have the stack pointer left to pop. */
12777 regs_available_for_popping
|= (1 << frame_pointer
);
12781 /* If we still have registers left on the stack, but we no longer have
12782 any registers into which we can pop them, then we must move the return
12783 address into the link register and make available the register that
12785 if (regs_available_for_popping
== 0 && pops_needed
> 0)
12787 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
12789 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
12790 reg_containing_return_addr
);
12792 reg_containing_return_addr
= LR_REGNUM
;
12795 /* If we have registers left on the stack then pop some more.
12796 We know that at most we will want to pop FP and SP. */
12797 if (pops_needed
> 0)
12802 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12803 regs_available_for_popping
);
12805 /* We have popped either FP or SP.
12806 Move whichever one it is into the correct register. */
12807 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12808 move_to
= number_of_first_bit_set (regs_to_pop
);
12810 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
12812 regs_to_pop
&= ~(1 << move_to
);
12817 /* If we still have not popped everything then we must have only
12818 had one register available to us and we are now popping the SP. */
12819 if (pops_needed
> 0)
12823 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12824 regs_available_for_popping
);
12826 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12828 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
12830 assert (regs_to_pop == (1 << STACK_POINTER))
12831 assert (pops_needed == 1)
12835 /* If necessary restore the a4 register. */
12838 if (reg_containing_return_addr
!= LR_REGNUM
)
12840 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12841 reg_containing_return_addr
= LR_REGNUM
;
12844 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12847 if (current_function_calls_eh_return
)
12848 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12850 /* Return to caller. */
12851 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12856 thumb_final_prescan_insn (rtx insn
)
12858 if (flag_print_asm_name
)
12859 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
12860 INSN_ADDRESSES (INSN_UID (insn
)));
12864 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
12866 unsigned HOST_WIDE_INT mask
= 0xff;
12869 if (val
== 0) /* XXX */
12872 for (i
= 0; i
< 25; i
++)
12873 if ((val
& (mask
<< i
)) == val
)
12879 /* Returns nonzero if the current function contains,
12880 or might contain a far jump. */
12882 thumb_far_jump_used_p (void)
12886 /* This test is only important for leaf functions. */
12887 /* assert (!leaf_function_p ()); */
12889 /* If we have already decided that far jumps may be used,
12890 do not bother checking again, and always return true even if
12891 it turns out that they are not being used. Once we have made
12892 the decision that far jumps are present (and that hence the link
12893 register will be pushed onto the stack) we cannot go back on it. */
12894 if (cfun
->machine
->far_jump_used
)
12897 /* If this function is not being called from the prologue/epilogue
12898 generation code then it must be being called from the
12899 INITIAL_ELIMINATION_OFFSET macro. */
12900 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
12902 /* In this case we know that we are being asked about the elimination
12903 of the arg pointer register. If that register is not being used,
12904 then there are no arguments on the stack, and we do not have to
12905 worry that a far jump might force the prologue to push the link
12906 register, changing the stack offsets. In this case we can just
12907 return false, since the presence of far jumps in the function will
12908 not affect stack offsets.
12910 If the arg pointer is live (or if it was live, but has now been
12911 eliminated and so set to dead) then we do have to test to see if
12912 the function might contain a far jump. This test can lead to some
12913 false negatives, since before reload is completed, then length of
12914 branch instructions is not known, so gcc defaults to returning their
12915 longest length, which in turn sets the far jump attribute to true.
12917 A false negative will not result in bad code being generated, but it
12918 will result in a needless push and pop of the link register. We
12919 hope that this does not occur too often.
12921 If we need doubleword stack alignment this could affect the other
12922 elimination offsets so we can't risk getting it wrong. */
12923 if (regs_ever_live
[ARG_POINTER_REGNUM
])
12924 cfun
->machine
->arg_pointer_live
= 1;
12925 else if (!cfun
->machine
->arg_pointer_live
)
12929 /* Check to see if the function contains a branch
12930 insn with the far jump attribute set. */
12931 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12933 if (GET_CODE (insn
) == JUMP_INSN
12934 /* Ignore tablejump patterns. */
12935 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
12936 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
12937 && get_attr_far_jump (insn
) == FAR_JUMP_YES
12940 /* Record the fact that we have decided that
12941 the function does use far jumps. */
12942 cfun
->machine
->far_jump_used
= 1;
12950 /* Return nonzero if FUNC must be entered in ARM mode. */
12952 is_called_in_ARM_mode (tree func
)
12954 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
12956 /* Ignore the problem about functions whose address is taken. */
12957 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
12961 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
12967 /* The bits which aren't usefully expanded as rtl. */
12969 thumb_unexpanded_epilogue (void)
12972 unsigned long live_regs_mask
= 0;
12973 int high_regs_pushed
= 0;
12974 int had_to_push_lr
;
12977 if (return_used_this_function
)
12980 if (IS_NAKED (arm_current_func_type ()))
12983 live_regs_mask
= thumb_compute_save_reg_mask ();
12984 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
12986 /* If we can deduce the registers used from the function's return value.
12987 This is more reliable that examining regs_ever_live[] because that
12988 will be set if the register is ever used in the function, not just if
12989 the register is used to hold a return value. */
12990 size
= arm_size_return_regs ();
12992 /* The prolog may have pushed some high registers to use as
12993 work registers. e.g. the testsuite file:
12994 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12995 compiles to produce:
12996 push {r4, r5, r6, r7, lr}
13000 as part of the prolog. We have to undo that pushing here. */
13002 if (high_regs_pushed
)
13004 unsigned long mask
= live_regs_mask
& 0xff;
13007 /* The available low registers depend on the size of the value we are
13015 /* Oh dear! We have no low registers into which we can pop
13018 ("no low registers available for popping high registers");
13020 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13021 if (live_regs_mask
& (1 << next_hi_reg
))
13024 while (high_regs_pushed
)
13026 /* Find lo register(s) into which the high register(s) can
13028 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13030 if (mask
& (1 << regno
))
13031 high_regs_pushed
--;
13032 if (high_regs_pushed
== 0)
13036 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13038 /* Pop the values into the low register(s). */
13039 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13041 /* Move the value(s) into the high registers. */
13042 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13044 if (mask
& (1 << regno
))
13046 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13049 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13050 if (live_regs_mask
& (1 << next_hi_reg
))
13055 live_regs_mask
&= ~0x0f00;
13058 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13059 live_regs_mask
&= 0xff;
13061 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13063 /* Pop the return address into the PC. */
13064 if (had_to_push_lr
)
13065 live_regs_mask
|= 1 << PC_REGNUM
;
13067 /* Either no argument registers were pushed or a backtrace
13068 structure was created which includes an adjusted stack
13069 pointer, so just pop everything. */
13070 if (live_regs_mask
)
13071 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13074 /* We have either just popped the return address into the
13075 PC or it is was kept in LR for the entire function. */
13076 if (!had_to_push_lr
)
13077 thumb_exit (asm_out_file
, LR_REGNUM
);
13081 /* Pop everything but the return address. */
13082 if (live_regs_mask
)
13083 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13086 if (had_to_push_lr
)
13090 /* We have no free low regs, so save one. */
13091 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13095 /* Get the return address into a temporary register. */
13096 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13097 1 << LAST_ARG_REGNUM
);
13101 /* Move the return address to lr. */
13102 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13104 /* Restore the low register. */
13105 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13110 regno
= LAST_ARG_REGNUM
;
13115 /* Remove the argument registers that were pushed onto the stack. */
13116 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13117 SP_REGNUM
, SP_REGNUM
,
13118 current_function_pretend_args_size
);
13120 thumb_exit (asm_out_file
, regno
);
13126 /* Functions to save and restore machine-specific function data. */
13127 static struct machine_function
*
13128 arm_init_machine_status (void)
13130 struct machine_function
*machine
;
13131 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13133 #if ARM_FT_UNKNOWN != 0
13134 machine
->func_type
= ARM_FT_UNKNOWN
;
13139 /* Return an RTX indicating where the return address to the
13140 calling function can be found. */
13142 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13147 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13150 /* Do anything needed before RTL is emitted for each function. */
13152 arm_init_expanders (void)
13154 /* Arrange to initialize and mark the machine per-function status. */
13155 init_machine_status
= arm_init_machine_status
;
13157 /* This is to stop the combine pass optimizing away the alignment
13158 adjustment of va_arg. */
13159 /* ??? It is claimed that this should not be necessary. */
13161 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13165 /* Like arm_compute_initial_elimination offset. Simpler because there
13166 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13167 to point at the base of the local variables after static stack
13168 space for a function has been allocated. */
13171 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13173 arm_stack_offsets
*offsets
;
13175 offsets
= arm_get_frame_offsets ();
13179 case ARG_POINTER_REGNUM
:
13182 case STACK_POINTER_REGNUM
:
13183 return offsets
->outgoing_args
- offsets
->saved_args
;
13185 case FRAME_POINTER_REGNUM
:
13186 return offsets
->soft_frame
- offsets
->saved_args
;
13188 case ARM_HARD_FRAME_POINTER_REGNUM
:
13189 return offsets
->saved_regs
- offsets
->saved_args
;
13191 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13192 return offsets
->locals_base
- offsets
->saved_args
;
13195 gcc_unreachable ();
13199 case FRAME_POINTER_REGNUM
:
13202 case STACK_POINTER_REGNUM
:
13203 return offsets
->outgoing_args
- offsets
->soft_frame
;
13205 case ARM_HARD_FRAME_POINTER_REGNUM
:
13206 return offsets
->saved_regs
- offsets
->soft_frame
;
13208 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13209 return offsets
->locals_base
- offsets
->soft_frame
;
13212 gcc_unreachable ();
13217 gcc_unreachable ();
13222 /* Generate the rest of a function's prologue. */
13224 thumb_expand_prologue (void)
13228 HOST_WIDE_INT amount
;
13229 arm_stack_offsets
*offsets
;
13230 unsigned long func_type
;
13232 unsigned long live_regs_mask
;
13234 func_type
= arm_current_func_type ();
13236 /* Naked functions don't have prologues. */
13237 if (IS_NAKED (func_type
))
13240 if (IS_INTERRUPT (func_type
))
13242 error ("interrupt Service Routines cannot be coded in Thumb mode");
13246 live_regs_mask
= thumb_compute_save_reg_mask ();
13247 /* Load the pic register before setting the frame pointer,
13248 so we can use r7 as a temporary work register. */
13250 arm_load_pic_register (live_regs_mask
);
13252 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13253 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13254 stack_pointer_rtx
);
13256 offsets
= arm_get_frame_offsets ();
13257 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13262 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13263 GEN_INT (- amount
)));
13264 RTX_FRAME_RELATED_P (insn
) = 1;
13270 /* The stack decrement is too big for an immediate value in a single
13271 insn. In theory we could issue multiple subtracts, but after
13272 three of them it becomes more space efficient to place the full
13273 value in the constant pool and load into a register. (Also the
13274 ARM debugger really likes to see only one stack decrement per
13275 function). So instead we look for a scratch register into which
13276 we can load the decrement, and then we subtract this from the
13277 stack pointer. Unfortunately on the thumb the only available
13278 scratch registers are the argument registers, and we cannot use
13279 these as they may hold arguments to the function. Instead we
13280 attempt to locate a call preserved register which is used by this
13281 function. If we can find one, then we know that it will have
13282 been pushed at the start of the prologue and so we can corrupt
13284 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13285 if (live_regs_mask
& (1 << regno
)
13286 && !(frame_pointer_needed
13287 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13290 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13292 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13294 /* Choose an arbitrary, non-argument low register. */
13295 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13297 /* Save it by copying it into a high, scratch register. */
13298 emit_insn (gen_movsi (spare
, reg
));
13299 /* Add a USE to stop propagate_one_insn() from barfing. */
13300 emit_insn (gen_prologue_use (spare
));
13302 /* Decrement the stack. */
13303 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13304 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13305 stack_pointer_rtx
, reg
));
13306 RTX_FRAME_RELATED_P (insn
) = 1;
13307 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13308 plus_constant (stack_pointer_rtx
,
13310 RTX_FRAME_RELATED_P (dwarf
) = 1;
13312 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13315 /* Restore the low register's original value. */
13316 emit_insn (gen_movsi (reg
, spare
));
13318 /* Emit a USE of the restored scratch register, so that flow
13319 analysis will not consider the restore redundant. The
13320 register won't be used again in this function and isn't
13321 restored by the epilogue. */
13322 emit_insn (gen_prologue_use (reg
));
13326 reg
= gen_rtx_REG (SImode
, regno
);
13328 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13330 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13331 stack_pointer_rtx
, reg
));
13332 RTX_FRAME_RELATED_P (insn
) = 1;
13333 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13334 plus_constant (stack_pointer_rtx
,
13336 RTX_FRAME_RELATED_P (dwarf
) = 1;
13338 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13344 if (frame_pointer_needed
)
13346 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13349 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13350 stack_pointer_rtx
, GEN_INT (amount
)));
13353 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13354 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13355 hard_frame_pointer_rtx
,
13356 stack_pointer_rtx
));
13357 dwarf
= gen_rtx_SET (SImode
, hard_frame_pointer_rtx
,
13358 plus_constant (stack_pointer_rtx
, amount
));
13359 RTX_FRAME_RELATED_P (dwarf
) = 1;
13360 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13364 RTX_FRAME_RELATED_P (insn
) = 1;
13367 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13368 emit_insn (gen_blockage ());
13370 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13371 if (live_regs_mask
& 0xff)
13372 cfun
->machine
->lr_save_eliminated
= 0;
13374 /* If the link register is being kept alive, with the return address in it,
13375 then make sure that it does not get reused by the ce2 pass. */
13376 if (cfun
->machine
->lr_save_eliminated
)
13377 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13382 thumb_expand_epilogue (void)
13384 HOST_WIDE_INT amount
;
13385 arm_stack_offsets
*offsets
;
13388 /* Naked functions don't have prologues. */
13389 if (IS_NAKED (arm_current_func_type ()))
13392 offsets
= arm_get_frame_offsets ();
13393 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13395 if (frame_pointer_needed
)
13397 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13398 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13404 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13405 GEN_INT (amount
)));
13408 /* r3 is always free in the epilogue. */
13409 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13411 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13412 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13416 /* Emit a USE (stack_pointer_rtx), so that
13417 the stack adjustment will not be deleted. */
13418 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13420 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13421 emit_insn (gen_blockage ());
13423 /* Emit a clobber for each insn that will be restored in the epilogue,
13424 so that flow2 will get register lifetimes correct. */
13425 for (regno
= 0; regno
< 13; regno
++)
13426 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13427 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13429 if (! regs_ever_live
[LR_REGNUM
])
13430 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13434 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13436 unsigned long live_regs_mask
= 0;
13437 unsigned long l_mask
;
13438 unsigned high_regs_pushed
= 0;
13439 int cfa_offset
= 0;
13442 if (IS_NAKED (arm_current_func_type ()))
13445 if (is_called_in_ARM_mode (current_function_decl
))
13449 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13450 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13452 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13454 /* Generate code sequence to switch us into Thumb mode. */
13455 /* The .code 32 directive has already been emitted by
13456 ASM_DECLARE_FUNCTION_NAME. */
13457 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13458 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13460 /* Generate a label, so that the debugger will notice the
13461 change in instruction sets. This label is also used by
13462 the assembler to bypass the ARM code when this function
13463 is called from a Thumb encoded function elsewhere in the
13464 same file. Hence the definition of STUB_NAME here must
13465 agree with the definition in gas/config/tc-arm.c. */
13467 #define STUB_NAME ".real_start_of"
13469 fprintf (f
, "\t.code\t16\n");
13471 if (arm_dllexport_name_p (name
))
13472 name
= arm_strip_name_encoding (name
);
13474 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13475 fprintf (f
, "\t.thumb_func\n");
13476 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13479 if (current_function_pretend_args_size
)
13481 /* Output unwind directive for the stack adjustment. */
13482 if (ARM_EABI_UNWIND_TABLES
)
13483 fprintf (f
, "\t.pad #%d\n",
13484 current_function_pretend_args_size
);
13486 if (cfun
->machine
->uses_anonymous_args
)
13490 fprintf (f
, "\tpush\t{");
13492 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13494 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13495 regno
<= LAST_ARG_REGNUM
;
13497 asm_fprintf (f
, "%r%s", regno
,
13498 regno
== LAST_ARG_REGNUM
? "" : ", ");
13500 fprintf (f
, "}\n");
13503 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13504 SP_REGNUM
, SP_REGNUM
,
13505 current_function_pretend_args_size
);
13507 /* We don't need to record the stores for unwinding (would it
13508 help the debugger any if we did?), but record the change in
13509 the stack pointer. */
13510 if (dwarf2out_do_frame ())
13512 char *l
= dwarf2out_cfi_label ();
13514 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13515 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13519 /* Get the registers we are going to push. */
13520 live_regs_mask
= thumb_compute_save_reg_mask ();
13521 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13522 l_mask
= live_regs_mask
& 0x40ff;
13523 /* Then count how many other high registers will need to be pushed. */
13524 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13526 if (TARGET_BACKTRACE
)
13529 unsigned work_register
;
13531 /* We have been asked to create a stack backtrace structure.
13532 The code looks like this:
13536 0 sub SP, #16 Reserve space for 4 registers.
13537 2 push {R7} Push low registers.
13538 4 add R7, SP, #20 Get the stack pointer before the push.
13539 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13540 8 mov R7, PC Get hold of the start of this code plus 12.
13541 10 str R7, [SP, #16] Store it.
13542 12 mov R7, FP Get hold of the current frame pointer.
13543 14 str R7, [SP, #4] Store it.
13544 16 mov R7, LR Get hold of the current return address.
13545 18 str R7, [SP, #12] Store it.
13546 20 add R7, SP, #16 Point at the start of the backtrace structure.
13547 22 mov FP, R7 Put this value into the frame pointer. */
13549 work_register
= thumb_find_work_register (live_regs_mask
);
13551 if (ARM_EABI_UNWIND_TABLES
)
13552 asm_fprintf (f
, "\t.pad #16\n");
13555 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13556 SP_REGNUM
, SP_REGNUM
);
13558 if (dwarf2out_do_frame ())
13560 char *l
= dwarf2out_cfi_label ();
13562 cfa_offset
= cfa_offset
+ 16;
13563 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13568 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13569 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13574 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13575 offset
+ 16 + current_function_pretend_args_size
);
13577 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13580 /* Make sure that the instruction fetching the PC is in the right place
13581 to calculate "start of backtrace creation code + 12". */
13584 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13585 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13587 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13588 ARM_HARD_FRAME_POINTER_REGNUM
);
13589 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13594 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13595 ARM_HARD_FRAME_POINTER_REGNUM
);
13596 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13598 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13599 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13603 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13604 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13606 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13608 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13609 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13611 /* Optimization: If we are not pushing any low registers but we are going
13612 to push some high registers then delay our first push. This will just
13613 be a push of LR and we can combine it with the push of the first high
13615 else if ((l_mask
& 0xff) != 0
13616 || (high_regs_pushed
== 0 && l_mask
))
13617 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13619 if (high_regs_pushed
)
13621 unsigned pushable_regs
;
13622 unsigned next_hi_reg
;
13624 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13625 if (live_regs_mask
& (1 << next_hi_reg
))
13628 pushable_regs
= l_mask
& 0xff;
13630 if (pushable_regs
== 0)
13631 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13633 while (high_regs_pushed
> 0)
13635 unsigned long real_regs_mask
= 0;
13637 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13639 if (pushable_regs
& (1 << regno
))
13641 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13643 high_regs_pushed
--;
13644 real_regs_mask
|= (1 << next_hi_reg
);
13646 if (high_regs_pushed
)
13648 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13650 if (live_regs_mask
& (1 << next_hi_reg
))
13655 pushable_regs
&= ~((1 << regno
) - 1);
13661 /* If we had to find a work register and we have not yet
13662 saved the LR then add it to the list of regs to push. */
13663 if (l_mask
== (1 << LR_REGNUM
))
13665 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
13667 real_regs_mask
| (1 << LR_REGNUM
));
13671 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
13676 /* Handle the case of a double word load into a low register from
13677 a computed memory address. The computed address may involve a
13678 register which is overwritten by the load. */
13680 thumb_load_double_from_address (rtx
*operands
)
13688 gcc_assert (GET_CODE (operands
[0]) == REG
);
13689 gcc_assert (GET_CODE (operands
[1]) == MEM
);
13691 /* Get the memory address. */
13692 addr
= XEXP (operands
[1], 0);
13694 /* Work out how the memory address is computed. */
13695 switch (GET_CODE (addr
))
13698 operands
[2] = adjust_address (operands
[1], SImode
, 4);
13700 if (REGNO (operands
[0]) == REGNO (addr
))
13702 output_asm_insn ("ldr\t%H0, %2", operands
);
13703 output_asm_insn ("ldr\t%0, %1", operands
);
13707 output_asm_insn ("ldr\t%0, %1", operands
);
13708 output_asm_insn ("ldr\t%H0, %2", operands
);
13713 /* Compute <address> + 4 for the high order load. */
13714 operands
[2] = adjust_address (operands
[1], SImode
, 4);
13716 output_asm_insn ("ldr\t%0, %1", operands
);
13717 output_asm_insn ("ldr\t%H0, %2", operands
);
13721 arg1
= XEXP (addr
, 0);
13722 arg2
= XEXP (addr
, 1);
13724 if (CONSTANT_P (arg1
))
13725 base
= arg2
, offset
= arg1
;
13727 base
= arg1
, offset
= arg2
;
13729 gcc_assert (GET_CODE (base
) == REG
);
13731 /* Catch the case of <address> = <reg> + <reg> */
13732 if (GET_CODE (offset
) == REG
)
13734 int reg_offset
= REGNO (offset
);
13735 int reg_base
= REGNO (base
);
13736 int reg_dest
= REGNO (operands
[0]);
13738 /* Add the base and offset registers together into the
13739 higher destination register. */
13740 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
13741 reg_dest
+ 1, reg_base
, reg_offset
);
13743 /* Load the lower destination register from the address in
13744 the higher destination register. */
13745 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
13746 reg_dest
, reg_dest
+ 1);
13748 /* Load the higher destination register from its own address
13750 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
13751 reg_dest
+ 1, reg_dest
+ 1);
13755 /* Compute <address> + 4 for the high order load. */
13756 operands
[2] = adjust_address (operands
[1], SImode
, 4);
13759 /* If the computed address is held in the low order register
13760 then load the high order register first, otherwise always
13761 load the low order register first. */
13762 if (REGNO (operands
[0]) == REGNO (base
))
13764 output_asm_insn ("ldr\t%H0, %2", operands
);
13765 output_asm_insn ("ldr\t%0, %1", operands
);
13769 output_asm_insn ("ldr\t%0, %1", operands
);
13770 output_asm_insn ("ldr\t%H0, %2", operands
);
13776 /* With no registers to worry about we can just load the value
13778 operands
[2] = adjust_address (operands
[1], SImode
, 4);
13780 output_asm_insn ("ldr\t%H0, %2", operands
);
13781 output_asm_insn ("ldr\t%0, %1", operands
);
13785 gcc_unreachable ();
13792 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
13799 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13802 operands
[4] = operands
[5];
13805 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
13806 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
13810 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13813 operands
[4] = operands
[5];
13816 if (REGNO (operands
[5]) > REGNO (operands
[6]))
13819 operands
[5] = operands
[6];
13822 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13825 operands
[4] = operands
[5];
13829 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
13830 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
13834 gcc_unreachable ();
13840 /* Output a call-via instruction for thumb state. */
13842 thumb_call_via_reg (rtx reg
)
13844 int regno
= REGNO (reg
);
13847 gcc_assert (regno
< LR_REGNUM
);
13849 /* If we are in the normal text section we can use a single instance
13850 per compilation unit. If we are doing function sections, then we need
13851 an entry per section, since we can't rely on reachability. */
13852 if (in_text_section ())
13854 thumb_call_reg_needed
= 1;
13856 if (thumb_call_via_label
[regno
] == NULL
)
13857 thumb_call_via_label
[regno
] = gen_label_rtx ();
13858 labelp
= thumb_call_via_label
+ regno
;
13862 if (cfun
->machine
->call_via
[regno
] == NULL
)
13863 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
13864 labelp
= cfun
->machine
->call_via
+ regno
;
13867 output_asm_insn ("bl\t%a0", labelp
);
13871 /* Routines for generating rtl. */
13873 thumb_expand_movmemqi (rtx
*operands
)
13875 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
13876 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
13877 HOST_WIDE_INT len
= INTVAL (operands
[2]);
13878 HOST_WIDE_INT offset
= 0;
13882 emit_insn (gen_movmem12b (out
, in
, out
, in
));
13888 emit_insn (gen_movmem8b (out
, in
, out
, in
));
13894 rtx reg
= gen_reg_rtx (SImode
);
13895 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
13896 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
13903 rtx reg
= gen_reg_rtx (HImode
);
13904 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
13905 plus_constant (in
, offset
))));
13906 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
13914 rtx reg
= gen_reg_rtx (QImode
);
13915 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
13916 plus_constant (in
, offset
))));
13917 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
13923 thumb_reload_out_hi (rtx
*operands
)
13925 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
13928 /* Handle reading a half-word from memory during reload. */
13930 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
13932 gcc_unreachable ();
13935 /* Return the length of a function name prefix
13936 that starts with the character 'c'. */
13938 arm_get_strip_length (int c
)
13942 ARM_NAME_ENCODING_LENGTHS
13947 /* Return a pointer to a function's name with any
13948 and all prefix encodings stripped from it. */
13950 arm_strip_name_encoding (const char *name
)
13954 while ((skip
= arm_get_strip_length (* name
)))
13960 /* If there is a '*' anywhere in the name's prefix, then
13961 emit the stripped name verbatim, otherwise prepend an
13962 underscore if leading underscores are being used. */
13964 arm_asm_output_labelref (FILE *stream
, const char *name
)
13969 while ((skip
= arm_get_strip_length (* name
)))
13971 verbatim
|= (*name
== '*');
13976 fputs (name
, stream
);
13978 asm_fprintf (stream
, "%U%s", name
);
13982 arm_file_end (void)
13986 if (! thumb_call_reg_needed
)
13990 asm_fprintf (asm_out_file
, "\t.code 16\n");
13991 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
13993 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
13995 rtx label
= thumb_call_via_label
[regno
];
13999 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14000 CODE_LABEL_NUMBER (label
));
14001 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14008 #ifdef AOF_ASSEMBLER
14009 /* Special functions only needed when producing AOF syntax assembler. */
14013 struct pic_chain
* next
;
14014 const char * symname
;
14017 static struct pic_chain
* aof_pic_chain
= NULL
;
14020 aof_pic_entry (rtx x
)
14022 struct pic_chain
** chainp
;
14025 if (aof_pic_label
== NULL_RTX
)
14027 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14030 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14031 offset
+= 4, chainp
= &(*chainp
)->next
)
14032 if ((*chainp
)->symname
== XSTR (x
, 0))
14033 return plus_constant (aof_pic_label
, offset
);
14035 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14036 (*chainp
)->next
= NULL
;
14037 (*chainp
)->symname
= XSTR (x
, 0);
14038 return plus_constant (aof_pic_label
, offset
);
14042 aof_dump_pic_table (FILE *f
)
14044 struct pic_chain
* chain
;
14046 if (aof_pic_chain
== NULL
)
14049 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14050 PIC_OFFSET_TABLE_REGNUM
,
14051 PIC_OFFSET_TABLE_REGNUM
);
14052 fputs ("|x$adcons|\n", f
);
14054 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14056 fputs ("\tDCD\t", f
);
14057 assemble_name (f
, chain
->symname
);
14062 int arm_text_section_count
= 1;
14065 aof_text_section (void )
14067 static char buf
[100];
14068 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14069 arm_text_section_count
++);
14071 strcat (buf
, ", PIC, REENTRANT");
14075 static int arm_data_section_count
= 1;
14078 aof_data_section (void)
14080 static char buf
[100];
14081 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14085 /* The AOF assembler is religiously strict about declarations of
14086 imported and exported symbols, so that it is impossible to declare
14087 a function as imported near the beginning of the file, and then to
14088 export it later on. It is, however, possible to delay the decision
14089 until all the functions in the file have been compiled. To get
14090 around this, we maintain a list of the imports and exports, and
14091 delete from it any that are subsequently defined. At the end of
14092 compilation we spit the remainder of the list out before the END
14097 struct import
* next
;
14101 static struct import
* imports_list
= NULL
;
14104 aof_add_import (const char *name
)
14106 struct import
* new;
14108 for (new = imports_list
; new; new = new->next
)
14109 if (new->name
== name
)
14112 new = (struct import
*) xmalloc (sizeof (struct import
));
14113 new->next
= imports_list
;
14114 imports_list
= new;
14119 aof_delete_import (const char *name
)
14121 struct import
** old
;
14123 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14125 if ((*old
)->name
== name
)
14127 *old
= (*old
)->next
;
14133 int arm_main_function
= 0;
14136 aof_dump_imports (FILE *f
)
14138 /* The AOF assembler needs this to cause the startup code to be extracted
14139 from the library. Brining in __main causes the whole thing to work
14141 if (arm_main_function
)
14144 fputs ("\tIMPORT __main\n", f
);
14145 fputs ("\tDCD __main\n", f
);
14148 /* Now dump the remaining imports. */
14149 while (imports_list
)
14151 fprintf (f
, "\tIMPORT\t");
14152 assemble_name (f
, imports_list
->name
);
14154 imports_list
= imports_list
->next
;
14159 aof_globalize_label (FILE *stream
, const char *name
)
14161 default_globalize_label (stream
, name
);
14162 if (! strcmp (name
, "main"))
14163 arm_main_function
= 1;
14167 aof_file_start (void)
14169 fputs ("__r0\tRN\t0\n", asm_out_file
);
14170 fputs ("__a1\tRN\t0\n", asm_out_file
);
14171 fputs ("__a2\tRN\t1\n", asm_out_file
);
14172 fputs ("__a3\tRN\t2\n", asm_out_file
);
14173 fputs ("__a4\tRN\t3\n", asm_out_file
);
14174 fputs ("__v1\tRN\t4\n", asm_out_file
);
14175 fputs ("__v2\tRN\t5\n", asm_out_file
);
14176 fputs ("__v3\tRN\t6\n", asm_out_file
);
14177 fputs ("__v4\tRN\t7\n", asm_out_file
);
14178 fputs ("__v5\tRN\t8\n", asm_out_file
);
14179 fputs ("__v6\tRN\t9\n", asm_out_file
);
14180 fputs ("__sl\tRN\t10\n", asm_out_file
);
14181 fputs ("__fp\tRN\t11\n", asm_out_file
);
14182 fputs ("__ip\tRN\t12\n", asm_out_file
);
14183 fputs ("__sp\tRN\t13\n", asm_out_file
);
14184 fputs ("__lr\tRN\t14\n", asm_out_file
);
14185 fputs ("__pc\tRN\t15\n", asm_out_file
);
14186 fputs ("__f0\tFN\t0\n", asm_out_file
);
14187 fputs ("__f1\tFN\t1\n", asm_out_file
);
14188 fputs ("__f2\tFN\t2\n", asm_out_file
);
14189 fputs ("__f3\tFN\t3\n", asm_out_file
);
14190 fputs ("__f4\tFN\t4\n", asm_out_file
);
14191 fputs ("__f5\tFN\t5\n", asm_out_file
);
14192 fputs ("__f6\tFN\t6\n", asm_out_file
);
14193 fputs ("__f7\tFN\t7\n", asm_out_file
);
14198 aof_file_end (void)
14201 aof_dump_pic_table (asm_out_file
);
14203 aof_dump_imports (asm_out_file
);
14204 fputs ("\tEND\n", asm_out_file
);
14206 #endif /* AOF_ASSEMBLER */
14209 /* Symbols in the text segment can be accessed without indirecting via the
14210 constant pool; it may take an extra binary operation, but this is still
14211 faster than indirecting via memory. Don't do this when not optimizing,
14212 since we won't be calculating al of the offsets necessary to do this
14216 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14218 /* This doesn't work with AOF syntax, since the string table may be in
14219 a different AREA. */
14220 #ifndef AOF_ASSEMBLER
14221 if (optimize
> 0 && TREE_CONSTANT (decl
))
14222 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14225 /* If we are referencing a function that is weak then encode a long call
14226 flag in the function name, otherwise if the function is static or
14227 or known to be defined in this file then encode a short call flag. */
14228 if (first
&& DECL_P (decl
))
14230 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14231 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14232 else if (! TREE_PUBLIC (decl
))
14233 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14236 #endif /* !ARM_PE */
14239 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14241 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14242 && !strcmp (prefix
, "L"))
14244 arm_ccfsm_state
= 0;
14245 arm_target_insn
= NULL
;
14247 default_internal_label (stream
, prefix
, labelno
);
14250 /* Output code to add DELTA to the first argument, and then jump
14251 to FUNCTION. Used for C++ multiple inheritance. */
14253 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14254 HOST_WIDE_INT delta
,
14255 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14258 static int thunk_label
= 0;
14260 int mi_delta
= delta
;
14261 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14263 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14266 mi_delta
= - mi_delta
;
14269 int labelno
= thunk_label
++;
14270 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14271 fputs ("\tldr\tr12, ", file
);
14272 assemble_name (file
, label
);
14273 fputc ('\n', file
);
14275 while (mi_delta
!= 0)
14277 if ((mi_delta
& (3 << shift
)) == 0)
14281 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14282 mi_op
, this_regno
, this_regno
,
14283 mi_delta
& (0xff << shift
));
14284 mi_delta
&= ~(0xff << shift
);
14290 fprintf (file
, "\tbx\tr12\n");
14291 ASM_OUTPUT_ALIGN (file
, 2);
14292 assemble_name (file
, label
);
14293 fputs (":\n", file
);
14294 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14298 fputs ("\tb\t", file
);
14299 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14300 if (NEED_PLT_RELOC
)
14301 fputs ("(PLT)", file
);
14302 fputc ('\n', file
);
14307 arm_emit_vector_const (FILE *file
, rtx x
)
14310 const char * pattern
;
14312 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14314 switch (GET_MODE (x
))
14316 case V2SImode
: pattern
= "%08x"; break;
14317 case V4HImode
: pattern
= "%04x"; break;
14318 case V8QImode
: pattern
= "%02x"; break;
14319 default: gcc_unreachable ();
14322 fprintf (file
, "0x");
14323 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14327 element
= CONST_VECTOR_ELT (x
, i
);
14328 fprintf (file
, pattern
, INTVAL (element
));
14335 arm_output_load_gr (rtx
*operands
)
14342 if (GET_CODE (operands
[1]) != MEM
14343 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14344 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14345 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14346 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14347 return "wldrw%?\t%0, %1";
14349 /* Fix up an out-of-range load of a GR register. */
14350 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14351 wcgr
= operands
[0];
14353 output_asm_insn ("ldr%?\t%0, %1", operands
);
14355 operands
[0] = wcgr
;
14357 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14358 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14364 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14365 int incoming ATTRIBUTE_UNUSED
)
14368 /* FIXME: The ARM backend has special code to handle structure
14369 returns, and will reserve its own hidden first argument. So
14370 if this macro is enabled a *second* hidden argument will be
14371 reserved, which will break binary compatibility with old
14372 toolchains and also thunk handling. One day this should be
14376 /* Register in which address to store a structure value
14377 is passed to a function. */
14378 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14382 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14384 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14385 named arg and all anonymous args onto the stack.
14386 XXX I know the prologue shouldn't be pushing registers, but it is faster
14390 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14391 enum machine_mode mode ATTRIBUTE_UNUSED
,
14392 tree type ATTRIBUTE_UNUSED
,
14394 int second_time ATTRIBUTE_UNUSED
)
14396 cfun
->machine
->uses_anonymous_args
= 1;
14397 if (cum
->nregs
< NUM_ARG_REGS
)
14398 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14401 /* Return nonzero if the CONSUMER instruction (a store) does not need
14402 PRODUCER's value to calculate the address. */
14405 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14407 rtx value
= PATTERN (producer
);
14408 rtx addr
= PATTERN (consumer
);
14410 if (GET_CODE (value
) == COND_EXEC
)
14411 value
= COND_EXEC_CODE (value
);
14412 if (GET_CODE (value
) == PARALLEL
)
14413 value
= XVECEXP (value
, 0, 0);
14414 value
= XEXP (value
, 0);
14415 if (GET_CODE (addr
) == COND_EXEC
)
14416 addr
= COND_EXEC_CODE (addr
);
14417 if (GET_CODE (addr
) == PARALLEL
)
14418 addr
= XVECEXP (addr
, 0, 0);
14419 addr
= XEXP (addr
, 0);
14421 return !reg_overlap_mentioned_p (value
, addr
);
14424 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14425 have an early register shift value or amount dependency on the
14426 result of PRODUCER. */
14429 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14431 rtx value
= PATTERN (producer
);
14432 rtx op
= PATTERN (consumer
);
14435 if (GET_CODE (value
) == COND_EXEC
)
14436 value
= COND_EXEC_CODE (value
);
14437 if (GET_CODE (value
) == PARALLEL
)
14438 value
= XVECEXP (value
, 0, 0);
14439 value
= XEXP (value
, 0);
14440 if (GET_CODE (op
) == COND_EXEC
)
14441 op
= COND_EXEC_CODE (op
);
14442 if (GET_CODE (op
) == PARALLEL
)
14443 op
= XVECEXP (op
, 0, 0);
14446 early_op
= XEXP (op
, 0);
14447 /* This is either an actual independent shift, or a shift applied to
14448 the first operand of another operation. We want the whole shift
14450 if (GET_CODE (early_op
) == REG
)
14453 return !reg_overlap_mentioned_p (value
, early_op
);
14456 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14457 have an early register shift value dependency on the result of
14461 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14463 rtx value
= PATTERN (producer
);
14464 rtx op
= PATTERN (consumer
);
14467 if (GET_CODE (value
) == COND_EXEC
)
14468 value
= COND_EXEC_CODE (value
);
14469 if (GET_CODE (value
) == PARALLEL
)
14470 value
= XVECEXP (value
, 0, 0);
14471 value
= XEXP (value
, 0);
14472 if (GET_CODE (op
) == COND_EXEC
)
14473 op
= COND_EXEC_CODE (op
);
14474 if (GET_CODE (op
) == PARALLEL
)
14475 op
= XVECEXP (op
, 0, 0);
14478 early_op
= XEXP (op
, 0);
14480 /* This is either an actual independent shift, or a shift applied to
14481 the first operand of another operation. We want the value being
14482 shifted, in either case. */
14483 if (GET_CODE (early_op
) != REG
)
14484 early_op
= XEXP (early_op
, 0);
14486 return !reg_overlap_mentioned_p (value
, early_op
);
14489 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14490 have an early register mult dependency on the result of
14494 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14496 rtx value
= PATTERN (producer
);
14497 rtx op
= PATTERN (consumer
);
14499 if (GET_CODE (value
) == COND_EXEC
)
14500 value
= COND_EXEC_CODE (value
);
14501 if (GET_CODE (value
) == PARALLEL
)
14502 value
= XVECEXP (value
, 0, 0);
14503 value
= XEXP (value
, 0);
14504 if (GET_CODE (op
) == COND_EXEC
)
14505 op
= COND_EXEC_CODE (op
);
14506 if (GET_CODE (op
) == PARALLEL
)
14507 op
= XVECEXP (op
, 0, 0);
14510 return (GET_CODE (op
) == PLUS
14511 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14515 /* We can't rely on the caller doing the proper promotion when
14516 using APCS or ATPCS. */
14519 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14521 return !TARGET_AAPCS_BASED
;
14525 /* AAPCS based ABIs use short enums by default. */
14528 arm_default_short_enums (void)
14530 return TARGET_AAPCS_BASED
;
14534 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14537 arm_align_anon_bitfield (void)
14539 return TARGET_AAPCS_BASED
;
14543 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14546 arm_cxx_guard_type (void)
14548 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14552 /* The EABI says test the least significant bit of a guard variable. */
14555 arm_cxx_guard_mask_bit (void)
14557 return TARGET_AAPCS_BASED
;
14561 /* The EABI specifies that all array cookies are 8 bytes long. */
14564 arm_get_cookie_size (tree type
)
14568 if (!TARGET_AAPCS_BASED
)
14569 return default_cxx_get_cookie_size (type
);
14571 size
= build_int_cst (sizetype
, 8);
14576 /* The EABI says that array cookies should also contain the element size. */
14579 arm_cookie_has_size (void)
14581 return TARGET_AAPCS_BASED
;
14585 /* The EABI says constructors and destructors should return a pointer to
14586 the object constructed/destroyed. */
14589 arm_cxx_cdtor_returns_this (void)
14591 return TARGET_AAPCS_BASED
;
14594 /* The EABI says that an inline function may never be the key
14598 arm_cxx_key_method_may_be_inline (void)
14600 return !TARGET_AAPCS_BASED
;
14604 arm_cxx_determine_class_data_visibility (tree decl
)
14606 if (!TARGET_AAPCS_BASED
)
14609 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14610 is exported. However, on systems without dynamic vague linkage,
14611 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14612 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
14613 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
14615 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
14616 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
14620 arm_cxx_class_data_always_comdat (void)
14622 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14623 vague linkage if the class has no key function. */
14624 return !TARGET_AAPCS_BASED
;
14628 /* The EABI says __aeabi_atexit should be used to register static
14632 arm_cxx_use_aeabi_atexit (void)
14634 return TARGET_AAPCS_BASED
;
14639 arm_set_return_address (rtx source
, rtx scratch
)
14641 arm_stack_offsets
*offsets
;
14642 HOST_WIDE_INT delta
;
14644 unsigned long saved_regs
;
14646 saved_regs
= arm_compute_save_reg_mask ();
14648 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14649 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14652 if (frame_pointer_needed
)
14653 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
14656 /* LR will be the first saved register. */
14657 offsets
= arm_get_frame_offsets ();
14658 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
14663 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
14664 GEN_INT (delta
& ~4095)));
14669 addr
= stack_pointer_rtx
;
14671 addr
= plus_constant (addr
, delta
);
14673 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
14679 thumb_set_return_address (rtx source
, rtx scratch
)
14681 arm_stack_offsets
*offsets
;
14682 HOST_WIDE_INT delta
;
14685 unsigned long mask
;
14687 emit_insn (gen_rtx_USE (VOIDmode
, source
));
14689 mask
= thumb_compute_save_reg_mask ();
14690 if (mask
& (1 << LR_REGNUM
))
14692 offsets
= arm_get_frame_offsets ();
14694 /* Find the saved regs. */
14695 if (frame_pointer_needed
)
14697 delta
= offsets
->soft_frame
- offsets
->saved_args
;
14698 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
14702 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
14705 /* Allow for the stack frame. */
14706 if (TARGET_BACKTRACE
)
14708 /* The link register is always the first saved register. */
14711 /* Construct the address. */
14712 addr
= gen_rtx_REG (SImode
, reg
);
14713 if ((reg
!= SP_REGNUM
&& delta
>= 128)
14716 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
14717 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
14721 addr
= plus_constant (addr
, delta
);
14723 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
14726 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14729 /* Implements target hook vector_mode_supported_p. */
14731 arm_vector_mode_supported_p (enum machine_mode mode
)
14733 if ((mode
== V2SImode
)
14734 || (mode
== V4HImode
)
14735 || (mode
== V8QImode
))
14741 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
14742 ARM insns and therefore guarantee that the shift count is modulo 256.
14743 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
14744 guarantee no particular behavior for out-of-range counts. */
14746 static unsigned HOST_WIDE_INT
14747 arm_shift_truncation_mask (enum machine_mode mode
)
14749 return mode
== SImode
? 255 : 0;
14753 /* Map internal gcc register numbers to DWARF2 register numbers. */
14756 arm_dbx_register_number (unsigned int regno
)
14761 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
14762 compatibility. The EABI defines them as registers 96-103. */
14763 if (IS_FPA_REGNUM (regno
))
14764 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
14766 if (IS_VFP_REGNUM (regno
))
14767 return 64 + regno
- FIRST_VFP_REGNUM
;
14769 if (IS_IWMMXT_GR_REGNUM (regno
))
14770 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
14772 if (IS_IWMMXT_REGNUM (regno
))
14773 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
14775 gcc_unreachable ();
14779 #ifdef TARGET_UNWIND_INFO
14780 /* Emit unwind directives for a store-multiple instruction. This should
14781 only ever be generated by the function prologue code, so we expect it
14782 to have a particular form. */
14785 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
14788 HOST_WIDE_INT offset
;
14789 HOST_WIDE_INT nregs
;
14795 /* First insn will adjust the stack pointer. */
14796 e
= XVECEXP (p
, 0, 0);
14797 if (GET_CODE (e
) != SET
14798 || GET_CODE (XEXP (e
, 0)) != REG
14799 || REGNO (XEXP (e
, 0)) != SP_REGNUM
14800 || GET_CODE (XEXP (e
, 1)) != PLUS
)
14803 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
14804 nregs
= XVECLEN (p
, 0) - 1;
14806 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
14809 /* The function prologue may also push pc, but not annotate it as it is
14810 never restored. We turn this into a stack pointer adjustment. */
14811 if (nregs
* 4 == offset
- 4)
14813 fprintf (asm_out_file
, "\t.pad #4\n");
14818 else if (IS_VFP_REGNUM (reg
))
14820 /* FPA register saves use an additional word. */
14824 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
14826 /* FPA registers are done differently. */
14827 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
14831 /* Unknown register type. */
14834 /* If the stack increment doesn't match the size of the saved registers,
14835 something has gone horribly wrong. */
14836 if (offset
!= nregs
* reg_size
)
14839 fprintf (asm_out_file
, "\t.save {");
14843 /* The remaining insns will describe the stores. */
14844 for (i
= 1; i
<= nregs
; i
++)
14846 /* Expect (set (mem <addr>) (reg)).
14847 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
14848 e
= XVECEXP (p
, 0, i
);
14849 if (GET_CODE (e
) != SET
14850 || GET_CODE (XEXP (e
, 0)) != MEM
14851 || GET_CODE (XEXP (e
, 1)) != REG
)
14854 reg
= REGNO (XEXP (e
, 1));
14859 fprintf (asm_out_file
, ", ");
14860 /* We can't use %r for vfp because we need to use the
14861 double precision register names. */
14862 if (IS_VFP_REGNUM (reg
))
14863 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
14865 asm_fprintf (asm_out_file
, "%r", reg
);
14867 #ifdef ENABLE_CHECKING
14868 /* Check that the addresses are consecutive. */
14869 e
= XEXP (XEXP (e
, 0), 0);
14870 if (GET_CODE (e
) == PLUS
)
14872 offset
+= reg_size
;
14873 if (GET_CODE (XEXP (e
, 0)) != REG
14874 || REGNO (XEXP (e
, 0)) != SP_REGNUM
14875 || GET_CODE (XEXP (e
, 1)) != CONST_INT
14876 || offset
!= INTVAL (XEXP (e
, 1)))
14880 || GET_CODE (e
) != REG
14881 || REGNO (e
) != SP_REGNUM
)
14885 fprintf (asm_out_file
, "}\n");
14888 /* Emit unwind directives for a SET. */
14891 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
14898 switch (GET_CODE (e0
))
14901 /* Pushing a single register. */
14902 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
14903 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
14904 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
14907 asm_fprintf (asm_out_file
, "\t.save ");
14908 if (IS_VFP_REGNUM (REGNO (e1
)))
14909 asm_fprintf(asm_out_file
, "{d%d}\n",
14910 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
14912 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
14916 if (REGNO (e0
) == SP_REGNUM
)
14918 /* A stack increment. */
14919 if (GET_CODE (e1
) != PLUS
14920 || GET_CODE (XEXP (e1
, 0)) != REG
14921 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
14922 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
14925 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
14926 -INTVAL (XEXP (e1
, 1)));
14928 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
14930 HOST_WIDE_INT offset
;
14933 if (GET_CODE (e1
) == PLUS
)
14935 if (GET_CODE (XEXP (e1
, 0)) != REG
14936 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
14938 reg
= REGNO (XEXP (e1
, 0));
14939 offset
= INTVAL (XEXP (e1
, 1));
14940 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
14941 HARD_FRAME_POINTER_REGNUM
, reg
,
14942 INTVAL (XEXP (e1
, 1)));
14944 else if (GET_CODE (e1
) == REG
)
14947 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
14948 HARD_FRAME_POINTER_REGNUM
, reg
);
14953 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
14955 /* Move from sp to reg. */
14956 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
14968 /* Emit unwind directives for the given insn. */
14971 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
14975 if (!ARM_EABI_UNWIND_TABLES
)
14978 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
14981 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
14983 pat
= XEXP (pat
, 0);
14985 pat
= PATTERN (insn
);
14987 switch (GET_CODE (pat
))
14990 arm_unwind_emit_set (asm_out_file
, pat
);
14994 /* Store multiple. */
14995 arm_unwind_emit_stm (asm_out_file
, pat
);
15004 /* Output a reference from a function exception table to the type_info
15005 object X. The EABI specifies that the symbol should be relocated by
15006 an R_ARM_TARGET2 relocation. */
15009 arm_output_ttype (rtx x
)
15011 fputs ("\t.word\t", asm_out_file
);
15012 output_addr_const (asm_out_file
, x
);
15013 /* Use special relocations for symbol references. */
15014 if (GET_CODE (x
) != CONST_INT
)
15015 fputs ("(TARGET2)", asm_out_file
);
15016 fputc ('\n', asm_out_file
);
15020 #endif /* TARGET_UNWIND_INFO */
15023 /* Output unwind directives for the start/end of a function. */
15026 arm_output_fn_unwind (FILE * f
, bool prologue
)
15028 if (!ARM_EABI_UNWIND_TABLES
)
15032 fputs ("\t.fnstart\n", f
);
15034 fputs ("\t.fnend\n", f
);