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[official-gcc.git] / gcc / config / arm / arm.h
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1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The architecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 extern GTY(()) rtx arm_compare_op0;
123 extern GTY(()) rtx arm_compare_op1;
124 /* The label of the current constant pool. */
125 extern rtx pool_vector_label;
126 /* Set to 1 when a return insn is output, this means that the epilogue
127 is not needed. */
128 extern int return_used_this_function;
129 /* Used to produce AOF syntax assembler. */
130 extern GTY(()) rtx aof_pic_label;
131 \f
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
135 #endif
136
137
138 #undef CPP_SPEC
139 #define CPP_SPEC "%(subtarget_cpp_spec) \
140 %{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142 %{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
144
145 #ifndef CC1_SPEC
146 #define CC1_SPEC ""
147 #endif
148
149 /* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
152
153 Each subgrouping contains a string constant, that defines the
154 specification name, and a string constant that used by the GCC driver
155 program.
156
157 Do not define this macro if it does not need to do anything. */
158 #define EXTRA_SPECS \
159 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
160 SUBTARGET_EXTRA_SPECS
161
162 #ifndef SUBTARGET_EXTRA_SPECS
163 #define SUBTARGET_EXTRA_SPECS
164 #endif
165
166 #ifndef SUBTARGET_CPP_SPEC
167 #define SUBTARGET_CPP_SPEC ""
168 #endif
169 \f
170 /* Run-time Target Specification. */
171 #ifndef TARGET_VERSION
172 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
173 #endif
174
175 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
176 /* Use hardware floating point instructions. */
177 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point calling convention. */
179 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
180 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
183 #define TARGET_IWMMXT (arm_arch_iwmmxt)
184 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
185 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
186 #define TARGET_ARM (! TARGET_THUMB)
187 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
188 #define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
190 : TARGET_TPCS_FRAME)
191 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
192 #define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
194
195 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
196 then TARGET_AAPCS_BASED must be true -- but the converse does not
197 hold. TARGET_BPABI implies the use of the BPABI runtime library,
198 etc., in addition to just the AAPCS calling conventions. */
199 #ifndef TARGET_BPABI
200 #define TARGET_BPABI false
201 #endif
202
203 /* Support for a compile-time default CPU, et cetera. The rules are:
204 --with-arch is ignored if -march or -mcpu are specified.
205 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
206 by --with-arch.
207 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
208 by -march).
209 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
210 specified.
211 --with-fpu is ignored if -mfpu is specified.
212 --with-abi is ignored is -mabi is specified. */
213 #define OPTION_DEFAULT_SPECS \
214 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
215 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
216 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
217 {"float", \
218 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
219 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
220 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
221
222 /* Which floating point model to use. */
223 enum arm_fp_model
224 {
225 ARM_FP_MODEL_UNKNOWN,
226 /* FPA model (Hardware or software). */
227 ARM_FP_MODEL_FPA,
228 /* Cirrus Maverick floating point model. */
229 ARM_FP_MODEL_MAVERICK,
230 /* VFP floating point model. */
231 ARM_FP_MODEL_VFP
232 };
233
234 extern enum arm_fp_model arm_fp_model;
235
236 /* Which floating point hardware is available. Also update
237 fp_model_for_fpu in arm.c when adding entries to this list. */
238 enum fputype
239 {
240 /* No FP hardware. */
241 FPUTYPE_NONE,
242 /* Full FPA support. */
243 FPUTYPE_FPA,
244 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
245 FPUTYPE_FPA_EMU2,
246 /* Emulated FPA hardware, Issue 3 emulator. */
247 FPUTYPE_FPA_EMU3,
248 /* Cirrus Maverick floating point co-processor. */
249 FPUTYPE_MAVERICK,
250 /* VFP. */
251 FPUTYPE_VFP
252 };
253
254 /* Recast the floating point class to be the floating point attribute. */
255 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
256
257 /* What type of floating point to tune for */
258 extern enum fputype arm_fpu_tune;
259
260 /* What type of floating point instructions are available */
261 extern enum fputype arm_fpu_arch;
262
263 enum float_abi_type
264 {
265 ARM_FLOAT_ABI_SOFT,
266 ARM_FLOAT_ABI_SOFTFP,
267 ARM_FLOAT_ABI_HARD
268 };
269
270 extern enum float_abi_type arm_float_abi;
271
272 #ifndef TARGET_DEFAULT_FLOAT_ABI
273 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
274 #endif
275
276 /* Which ABI to use. */
277 enum arm_abi_type
278 {
279 ARM_ABI_APCS,
280 ARM_ABI_ATPCS,
281 ARM_ABI_AAPCS,
282 ARM_ABI_IWMMXT,
283 ARM_ABI_AAPCS_LINUX
284 };
285
286 extern enum arm_abi_type arm_abi;
287
288 #ifndef ARM_DEFAULT_ABI
289 #define ARM_DEFAULT_ABI ARM_ABI_APCS
290 #endif
291
292 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
293 extern int arm_arch3m;
294
295 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
296 extern int arm_arch4;
297
298 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
299 extern int arm_arch4t;
300
301 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
302 extern int arm_arch5;
303
304 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
305 extern int arm_arch5e;
306
307 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
308 extern int arm_arch6;
309
310 /* Nonzero if this chip can benefit from load scheduling. */
311 extern int arm_ld_sched;
312
313 /* Nonzero if generating thumb code. */
314 extern int thumb_code;
315
316 /* Nonzero if this chip is a StrongARM. */
317 extern int arm_tune_strongarm;
318
319 /* Nonzero if this chip is a Cirrus variant. */
320 extern int arm_arch_cirrus;
321
322 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
323 extern int arm_arch_iwmmxt;
324
325 /* Nonzero if this chip is an XScale. */
326 extern int arm_arch_xscale;
327
328 /* Nonzero if tuning for XScale. */
329 extern int arm_tune_xscale;
330
331 /* Nonzero if tuning for stores via the write buffer. */
332 extern int arm_tune_wbuf;
333
334 /* Nonzero if we should define __THUMB_INTERWORK__ in the
335 preprocessor.
336 XXX This is a bit of a hack, it's intended to help work around
337 problems in GLD which doesn't understand that armv5t code is
338 interworking clean. */
339 extern int arm_cpp_interwork;
340
341 #ifndef TARGET_DEFAULT
342 #define TARGET_DEFAULT (MASK_APCS_FRAME)
343 #endif
344
345 /* The frame pointer register used in gcc has nothing to do with debugging;
346 that is controlled by the APCS-FRAME option. */
347 #define CAN_DEBUG_WITHOUT_FP
348
349 #define OVERRIDE_OPTIONS arm_override_options ()
350
351 /* Nonzero if PIC code requires explicit qualifiers to generate
352 PLT and GOT relocs rather than the assembler doing so implicitly.
353 Subtargets can override these if required. */
354 #ifndef NEED_GOT_RELOC
355 #define NEED_GOT_RELOC 0
356 #endif
357 #ifndef NEED_PLT_RELOC
358 #define NEED_PLT_RELOC 0
359 #endif
360
361 /* Nonzero if we need to refer to the GOT with a PC-relative
362 offset. In other words, generate
363
364 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
365
366 rather than
367
368 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
369
370 The default is true, which matches NetBSD. Subtargets can
371 override this if required. */
372 #ifndef GOT_PCREL
373 #define GOT_PCREL 1
374 #endif
375 \f
376 /* Target machine storage Layout. */
377
378
379 /* Define this macro if it is advisable to hold scalars in registers
380 in a wider mode than that declared by the program. In such cases,
381 the value is constrained to be within the bounds of the declared
382 type, but kept valid in the wider mode. The signedness of the
383 extension may differ from that of the type. */
384
385 /* It is far faster to zero extend chars than to sign extend them */
386
387 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
388 if (GET_MODE_CLASS (MODE) == MODE_INT \
389 && GET_MODE_SIZE (MODE) < 4) \
390 { \
391 if (MODE == QImode) \
392 UNSIGNEDP = 1; \
393 else if (MODE == HImode) \
394 UNSIGNEDP = 1; \
395 (MODE) = SImode; \
396 }
397
398 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
399 if ((GET_MODE_CLASS (MODE) == MODE_INT \
400 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
401 && GET_MODE_SIZE (MODE) < 4) \
402 (MODE) = SImode; \
403
404 /* Define this if most significant bit is lowest numbered
405 in instructions that operate on numbered bit-fields. */
406 #define BITS_BIG_ENDIAN 0
407
408 /* Define this if most significant byte of a word is the lowest numbered.
409 Most ARM processors are run in little endian mode, so that is the default.
410 If you want to have it run-time selectable, change the definition in a
411 cover file to be TARGET_BIG_ENDIAN. */
412 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
413
414 /* Define this if most significant word of a multiword number is the lowest
415 numbered.
416 This is always false, even when in big-endian mode. */
417 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
418
419 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
420 on processor pre-defineds when compiling libgcc2.c. */
421 #if defined(__ARMEB__) && !defined(__ARMWEL__)
422 #define LIBGCC2_WORDS_BIG_ENDIAN 1
423 #else
424 #define LIBGCC2_WORDS_BIG_ENDIAN 0
425 #endif
426
427 /* Define this if most significant word of doubles is the lowest numbered.
428 The rules are different based on whether or not we use FPA-format,
429 VFP-format or some other floating point co-processor's format doubles. */
430 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
431
432 #define UNITS_PER_WORD 4
433
434 /* True if natural alignment is used for doubleword types. */
435 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
436
437 #define DOUBLEWORD_ALIGNMENT 64
438
439 #define PARM_BOUNDARY 32
440
441 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
442
443 #define PREFERRED_STACK_BOUNDARY \
444 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
445
446 #define FUNCTION_BOUNDARY 32
447
448 /* The lowest bit is used to indicate Thumb-mode functions, so the
449 vbit must go into the delta field of pointers to member
450 functions. */
451 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
452
453 #define EMPTY_FIELD_BOUNDARY 32
454
455 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
456
457 /* XXX Blah -- this macro is used directly by libobjc. Since it
458 supports no vector modes, cut out the complexity and fall back
459 on BIGGEST_FIELD_ALIGNMENT. */
460 #ifdef IN_TARGET_LIBS
461 #define BIGGEST_FIELD_ALIGNMENT 64
462 #endif
463
464 /* Make strings word-aligned so strcpy from constants will be faster. */
465 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
466
467 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
468 ((TREE_CODE (EXP) == STRING_CST \
469 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
470 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
471
472 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
473 value set in previous versions of this toolchain was 8, which produces more
474 compact structures. The command line option -mstructure_size_boundary=<n>
475 can be used to change this value. For compatibility with the ARM SDK
476 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
477 0020D) page 2-20 says "Structures are aligned on word boundaries".
478 The AAPCS specifies a value of 8. */
479 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
480 extern int arm_structure_size_boundary;
481
482 /* This is the value used to initialize arm_structure_size_boundary. If a
483 particular arm target wants to change the default value it should change
484 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
485 for an example of this. */
486 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
487 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
488 #endif
489
490 /* Nonzero if move instructions will actually fail to work
491 when given unaligned data. */
492 #define STRICT_ALIGNMENT 1
493
494 /* wchar_t is unsigned under the AAPCS. */
495 #ifndef WCHAR_TYPE
496 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
497
498 #define WCHAR_TYPE_SIZE BITS_PER_WORD
499 #endif
500
501 #ifndef SIZE_TYPE
502 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
503 #endif
504
505 #ifndef PTRDIFF_TYPE
506 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
507 #endif
508
509 /* AAPCS requires that structure alignment is affected by bitfields. */
510 #ifndef PCC_BITFIELD_TYPE_MATTERS
511 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
512 #endif
513
514 \f
515 /* Standard register usage. */
516
517 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
518 (S - saved over call).
519
520 r0 * argument word/integer result
521 r1-r3 argument word
522
523 r4-r8 S register variable
524 r9 S (rfp) register variable (real frame pointer)
525
526 r10 F S (sl) stack limit (used by -mapcs-stack-check)
527 r11 F S (fp) argument pointer
528 r12 (ip) temp workspace
529 r13 F S (sp) lower end of current stack frame
530 r14 (lr) link address/workspace
531 r15 F (pc) program counter
532
533 f0 floating point result
534 f1-f3 floating point scratch
535
536 f4-f7 S floating point variable
537
538 cc This is NOT a real register, but is used internally
539 to represent things that use or set the condition
540 codes.
541 sfp This isn't either. It is used during rtl generation
542 since the offset between the frame pointer and the
543 auto's isn't known until after register allocation.
544 afp Nor this, we only need this because of non-local
545 goto. Without it fp appears to be used and the
546 elimination code won't get rid of sfp. It tracks
547 fp exactly at all times.
548
549 *: See CONDITIONAL_REGISTER_USAGE */
550
551 /*
552 mvf0 Cirrus floating point result
553 mvf1-mvf3 Cirrus floating point scratch
554 mvf4-mvf15 S Cirrus floating point variable. */
555
556 /* s0-s15 VFP scratch (aka d0-d7).
557 s16-s31 S VFP variable (aka d8-d15).
558 vfpcc Not a real register. Represents the VFP condition
559 code flags. */
560
561 /* The stack backtrace structure is as follows:
562 fp points to here: | save code pointer | [fp]
563 | return link value | [fp, #-4]
564 | return sp value | [fp, #-8]
565 | return fp value | [fp, #-12]
566 [| saved r10 value |]
567 [| saved r9 value |]
568 [| saved r8 value |]
569 [| saved r7 value |]
570 [| saved r6 value |]
571 [| saved r5 value |]
572 [| saved r4 value |]
573 [| saved r3 value |]
574 [| saved r2 value |]
575 [| saved r1 value |]
576 [| saved r0 value |]
577 [| saved f7 value |] three words
578 [| saved f6 value |] three words
579 [| saved f5 value |] three words
580 [| saved f4 value |] three words
581 r0-r3 are not normally saved in a C function. */
582
583 /* 1 for registers that have pervasive standard uses
584 and are not available for the register allocator. */
585 #define FIXED_REGISTERS \
586 { \
587 0,0,0,0,0,0,0,0, \
588 0,0,0,0,0,1,0,1, \
589 0,0,0,0,0,0,0,0, \
590 1,1,1, \
591 1,1,1,1,1,1,1,1, \
592 1,1,1,1,1,1,1,1, \
593 1,1,1,1,1,1,1,1, \
594 1,1,1,1,1,1,1,1, \
595 1,1,1,1, \
596 1,1,1,1,1,1,1,1, \
597 1,1,1,1,1,1,1,1, \
598 1,1,1,1,1,1,1,1, \
599 1,1,1,1,1,1,1,1, \
600 1 \
601 }
602
603 /* 1 for registers not available across function calls.
604 These must include the FIXED_REGISTERS and also any
605 registers that can be used without being saved.
606 The latter must include the registers where values are returned
607 and the register where structure-value addresses are passed.
608 Aside from that, you can include as many other registers as you like.
609 The CC is not preserved over function calls on the ARM 6, so it is
610 easier to assume this for all. SFP is preserved, since FP is. */
611 #define CALL_USED_REGISTERS \
612 { \
613 1,1,1,1,0,0,0,0, \
614 0,0,0,0,1,1,1,1, \
615 1,1,1,1,0,0,0,0, \
616 1,1,1, \
617 1,1,1,1,1,1,1,1, \
618 1,1,1,1,1,1,1,1, \
619 1,1,1,1,1,1,1,1, \
620 1,1,1,1,1,1,1,1, \
621 1,1,1,1, \
622 1,1,1,1,1,1,1,1, \
623 1,1,1,1,1,1,1,1, \
624 1,1,1,1,1,1,1,1, \
625 1,1,1,1,1,1,1,1, \
626 1 \
627 }
628
629 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
630 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
631 #endif
632
633 #define CONDITIONAL_REGISTER_USAGE \
634 { \
635 int regno; \
636 \
637 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
638 { \
639 for (regno = FIRST_FPA_REGNUM; \
640 regno <= LAST_FPA_REGNUM; ++regno) \
641 fixed_regs[regno] = call_used_regs[regno] = 1; \
642 } \
643 \
644 if (TARGET_THUMB && optimize_size) \
645 { \
646 /* When optimizing for size, it's better not to use \
647 the HI regs, because of the overhead of stacking \
648 them. */ \
649 for (regno = FIRST_HI_REGNUM; \
650 regno <= LAST_HI_REGNUM; ++regno) \
651 fixed_regs[regno] = call_used_regs[regno] = 1; \
652 } \
653 \
654 /* The link register can be clobbered by any branch insn, \
655 but we have no way to track that at present, so mark \
656 it as unavailable. */ \
657 if (TARGET_THUMB) \
658 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
659 \
660 if (TARGET_ARM && TARGET_HARD_FLOAT) \
661 { \
662 if (TARGET_MAVERICK) \
663 { \
664 for (regno = FIRST_FPA_REGNUM; \
665 regno <= LAST_FPA_REGNUM; ++ regno) \
666 fixed_regs[regno] = call_used_regs[regno] = 1; \
667 for (regno = FIRST_CIRRUS_FP_REGNUM; \
668 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
669 { \
670 fixed_regs[regno] = 0; \
671 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
672 } \
673 } \
674 if (TARGET_VFP) \
675 { \
676 for (regno = FIRST_VFP_REGNUM; \
677 regno <= LAST_VFP_REGNUM; ++ regno) \
678 { \
679 fixed_regs[regno] = 0; \
680 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
681 } \
682 } \
683 } \
684 \
685 if (TARGET_REALLY_IWMMXT) \
686 { \
687 regno = FIRST_IWMMXT_GR_REGNUM; \
688 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
689 and wCG1 as call-preserved registers. The 2002/11/21 \
690 revision changed this so that all wCG registers are \
691 scratch registers. */ \
692 for (regno = FIRST_IWMMXT_GR_REGNUM; \
693 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
694 fixed_regs[regno] = 0; \
695 /* The XScale ABI has wR0 - wR9 as scratch registers, \
696 the rest as call-preserved registers. */ \
697 for (regno = FIRST_IWMMXT_REGNUM; \
698 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
699 { \
700 fixed_regs[regno] = 0; \
701 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
702 } \
703 } \
704 \
705 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
706 { \
707 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
708 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
709 } \
710 else if (TARGET_APCS_STACK) \
711 { \
712 fixed_regs[10] = 1; \
713 call_used_regs[10] = 1; \
714 } \
715 /* -mcaller-super-interworking reserves r11 for calls to \
716 _interwork_r11_call_via_rN(). Making the register global \
717 is an easy way of ensuring that it remains valid for all \
718 calls. */ \
719 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
720 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
721 { \
722 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
723 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
724 if (TARGET_CALLER_INTERWORKING) \
725 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
726 } \
727 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
728 }
729
730 /* These are a couple of extensions to the formats accepted
731 by asm_fprintf:
732 %@ prints out ASM_COMMENT_START
733 %r prints out REGISTER_PREFIX reg_names[arg] */
734 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
735 case '@': \
736 fputs (ASM_COMMENT_START, FILE); \
737 break; \
738 \
739 case 'r': \
740 fputs (REGISTER_PREFIX, FILE); \
741 fputs (reg_names [va_arg (ARGS, int)], FILE); \
742 break;
743
744 /* Round X up to the nearest word. */
745 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
746
747 /* Convert fron bytes to ints. */
748 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
749
750 /* The number of (integer) registers required to hold a quantity of type MODE.
751 Also used for VFP registers. */
752 #define ARM_NUM_REGS(MODE) \
753 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
754
755 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
756 #define ARM_NUM_REGS2(MODE, TYPE) \
757 ARM_NUM_INTS ((MODE) == BLKmode ? \
758 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
759
760 /* The number of (integer) argument register available. */
761 #define NUM_ARG_REGS 4
762
763 /* Return the register number of the N'th (integer) argument. */
764 #define ARG_REGISTER(N) (N - 1)
765
766 /* Specify the registers used for certain standard purposes.
767 The values of these macros are register numbers. */
768
769 /* The number of the last argument register. */
770 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
771
772 /* The numbers of the Thumb register ranges. */
773 #define FIRST_LO_REGNUM 0
774 #define LAST_LO_REGNUM 7
775 #define FIRST_HI_REGNUM 8
776 #define LAST_HI_REGNUM 11
777
778 #ifndef TARGET_UNWIND_INFO
779 /* We use sjlj exceptions for backwards compatibility. */
780 #define MUST_USE_SJLJ_EXCEPTIONS 1
781 #endif
782
783 /* We can generate DWARF2 Unwind info, even though we don't use it. */
784 #define DWARF2_UNWIND_INFO 1
785
786 /* Use r0 and r1 to pass exception handling information. */
787 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
788
789 /* The register that holds the return address in exception handlers. */
790 #define ARM_EH_STACKADJ_REGNUM 2
791 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
792
793 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
794 as an invisible last argument (possible since varargs don't exist in
795 Pascal), so the following is not true. */
796 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
797
798 /* Define this to be where the real frame pointer is if it is not possible to
799 work out the offset between the frame pointer and the automatic variables
800 until after register allocation has taken place. FRAME_POINTER_REGNUM
801 should point to a special register that we will make sure is eliminated.
802
803 For the Thumb we have another problem. The TPCS defines the frame pointer
804 as r11, and GCC believes that it is always possible to use the frame pointer
805 as base register for addressing purposes. (See comments in
806 find_reloads_address()). But - the Thumb does not allow high registers,
807 including r11, to be used as base address registers. Hence our problem.
808
809 The solution used here, and in the old thumb port is to use r7 instead of
810 r11 as the hard frame pointer and to have special code to generate
811 backtrace structures on the stack (if required to do so via a command line
812 option) using r11. This is the only 'user visible' use of r11 as a frame
813 pointer. */
814 #define ARM_HARD_FRAME_POINTER_REGNUM 11
815 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
816
817 #define HARD_FRAME_POINTER_REGNUM \
818 (TARGET_ARM \
819 ? ARM_HARD_FRAME_POINTER_REGNUM \
820 : THUMB_HARD_FRAME_POINTER_REGNUM)
821
822 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
823
824 /* Register to use for pushing function arguments. */
825 #define STACK_POINTER_REGNUM SP_REGNUM
826
827 /* ARM floating pointer registers. */
828 #define FIRST_FPA_REGNUM 16
829 #define LAST_FPA_REGNUM 23
830 #define IS_FPA_REGNUM(REGNUM) \
831 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
832
833 #define FIRST_IWMMXT_GR_REGNUM 43
834 #define LAST_IWMMXT_GR_REGNUM 46
835 #define FIRST_IWMMXT_REGNUM 47
836 #define LAST_IWMMXT_REGNUM 62
837 #define IS_IWMMXT_REGNUM(REGNUM) \
838 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
839 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
840 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
841
842 /* Base register for access to local variables of the function. */
843 #define FRAME_POINTER_REGNUM 25
844
845 /* Base register for access to arguments of the function. */
846 #define ARG_POINTER_REGNUM 26
847
848 #define FIRST_CIRRUS_FP_REGNUM 27
849 #define LAST_CIRRUS_FP_REGNUM 42
850 #define IS_CIRRUS_REGNUM(REGNUM) \
851 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
852
853 #define FIRST_VFP_REGNUM 63
854 #define LAST_VFP_REGNUM 94
855 #define IS_VFP_REGNUM(REGNUM) \
856 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
857
858 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
859 /* + 16 Cirrus registers take us up to 43. */
860 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
861 /* VFP adds 32 + 1 more. */
862 #define FIRST_PSEUDO_REGISTER 96
863
864 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
865
866 /* Value should be nonzero if functions must have frame pointers.
867 Zero means the frame pointer need not be set up (and parms may be accessed
868 via the stack pointer) in functions that seem suitable.
869 If we have to have a frame pointer we might as well make use of it.
870 APCS says that the frame pointer does not need to be pushed in leaf
871 functions, or simple tail call functions. */
872
873 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
874 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
875 #endif
876
877 #define FRAME_POINTER_REQUIRED \
878 (current_function_has_nonlocal_label \
879 || SUBTARGET_FRAME_POINTER_REQUIRED \
880 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
881
882 /* Return number of consecutive hard regs needed starting at reg REGNO
883 to hold something of mode MODE.
884 This is ordinarily the length in words of a value of mode MODE
885 but can be less for certain modes in special long registers.
886
887 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
888 mode. */
889 #define HARD_REGNO_NREGS(REGNO, MODE) \
890 ((TARGET_ARM \
891 && REGNO >= FIRST_FPA_REGNUM \
892 && REGNO != FRAME_POINTER_REGNUM \
893 && REGNO != ARG_POINTER_REGNUM) \
894 && !IS_VFP_REGNUM (REGNO) \
895 ? 1 : ARM_NUM_REGS (MODE))
896
897 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
898 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
899 arm_hard_regno_mode_ok ((REGNO), (MODE))
900
901 /* Value is 1 if it is a good idea to tie two pseudo registers
902 when one has mode MODE1 and one has mode MODE2.
903 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
904 for any hard reg, then this must be 0 for correct output. */
905 #define MODES_TIEABLE_P(MODE1, MODE2) \
906 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
907
908 #define VALID_IWMMXT_REG_MODE(MODE) \
909 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
910
911 /* The order in which register should be allocated. It is good to use ip
912 since no saving is required (though calls clobber it) and it never contains
913 function parameters. It is quite good to use lr since other calls may
914 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
915 least likely to contain a function parameter; in addition results are
916 returned in r0. */
917
918 #define REG_ALLOC_ORDER \
919 { \
920 3, 2, 1, 0, 12, 14, 4, 5, \
921 6, 7, 8, 10, 9, 11, 13, 15, \
922 16, 17, 18, 19, 20, 21, 22, 23, \
923 27, 28, 29, 30, 31, 32, 33, 34, \
924 35, 36, 37, 38, 39, 40, 41, 42, \
925 43, 44, 45, 46, 47, 48, 49, 50, \
926 51, 52, 53, 54, 55, 56, 57, 58, \
927 59, 60, 61, 62, \
928 24, 25, 26, \
929 78, 77, 76, 75, 74, 73, 72, 71, \
930 70, 69, 68, 67, 66, 65, 64, 63, \
931 79, 80, 81, 82, 83, 84, 85, 86, \
932 87, 88, 89, 90, 91, 92, 93, 94, \
933 95 \
934 }
935
936 /* Interrupt functions can only use registers that have already been
937 saved by the prologue, even if they would normally be
938 call-clobbered. */
939 #define HARD_REGNO_RENAME_OK(SRC, DST) \
940 (! IS_INTERRUPT (cfun->machine->func_type) || \
941 regs_ever_live[DST])
942 \f
943 /* Register and constant classes. */
944
945 /* Register classes: used to be simple, just all ARM regs or all FPA regs
946 Now that the Thumb is involved it has become more complicated. */
947 enum reg_class
948 {
949 NO_REGS,
950 FPA_REGS,
951 CIRRUS_REGS,
952 VFP_REGS,
953 IWMMXT_GR_REGS,
954 IWMMXT_REGS,
955 LO_REGS,
956 STACK_REG,
957 BASE_REGS,
958 HI_REGS,
959 CC_REG,
960 VFPCC_REG,
961 GENERAL_REGS,
962 ALL_REGS,
963 LIM_REG_CLASSES
964 };
965
966 #define N_REG_CLASSES (int) LIM_REG_CLASSES
967
968 /* Give names of register classes as strings for dump file. */
969 #define REG_CLASS_NAMES \
970 { \
971 "NO_REGS", \
972 "FPA_REGS", \
973 "CIRRUS_REGS", \
974 "VFP_REGS", \
975 "IWMMXT_GR_REGS", \
976 "IWMMXT_REGS", \
977 "LO_REGS", \
978 "STACK_REG", \
979 "BASE_REGS", \
980 "HI_REGS", \
981 "CC_REG", \
982 "VFPCC_REG", \
983 "GENERAL_REGS", \
984 "ALL_REGS", \
985 }
986
987 /* Define which registers fit in which classes.
988 This is an initializer for a vector of HARD_REG_SET
989 of length N_REG_CLASSES. */
990 #define REG_CLASS_CONTENTS \
991 { \
992 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
993 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
994 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
995 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
996 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
997 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
998 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
999 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1000 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1001 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1002 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1003 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1004 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1005 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1006 }
1007
1008 /* The same information, inverted:
1009 Return the class number of the smallest class containing
1010 reg number REGNO. This could be a conditional expression
1011 or could index an array. */
1012 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1013
1014 /* FPA registers can't do subreg as all values are reformatted to internal
1015 precision. VFP registers may only be accessed in the mode they
1016 were set. */
1017 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1018 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1019 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1020 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1021 : 0)
1022
1023 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1024 using r0-r4 for function arguments, r7 for the stack frame and don't
1025 have enough left over to do doubleword arithmetic. */
1026 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1027 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1028 || (CLASS) == CC_REG)
1029
1030 /* The class value for index registers, and the one for base regs. */
1031 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1032 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1033
1034 /* For the Thumb the high registers cannot be used as base registers
1035 when addressing quantities in QI or HI mode; if we don't know the
1036 mode, then we must be conservative. */
1037 #define MODE_BASE_REG_CLASS(MODE) \
1038 (TARGET_ARM ? GENERAL_REGS : \
1039 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1040
1041 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1042 instead of BASE_REGS. */
1043 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1044
1045 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1046 registers explicitly used in the rtl to be used as spill registers
1047 but prevents the compiler from extending the lifetime of these
1048 registers. */
1049 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1050
1051 /* Get reg_class from a letter such as appears in the machine description.
1052 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1053 ARM, but several more letters for the Thumb. */
1054 #define REG_CLASS_FROM_LETTER(C) \
1055 ( (C) == 'f' ? FPA_REGS \
1056 : (C) == 'v' ? CIRRUS_REGS \
1057 : (C) == 'w' ? VFP_REGS \
1058 : (C) == 'y' ? IWMMXT_REGS \
1059 : (C) == 'z' ? IWMMXT_GR_REGS \
1060 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1061 : TARGET_ARM ? NO_REGS \
1062 : (C) == 'h' ? HI_REGS \
1063 : (C) == 'b' ? BASE_REGS \
1064 : (C) == 'k' ? STACK_REG \
1065 : (C) == 'c' ? CC_REG \
1066 : NO_REGS)
1067
1068 /* The letters I, J, K, L and M in a register constraint string
1069 can be used to stand for particular ranges of immediate operands.
1070 This macro defines what the ranges are.
1071 C is the letter, and VALUE is a constant value.
1072 Return 1 if VALUE is in the range specified by C.
1073 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1074 J: valid indexing constants.
1075 K: ~value ok in rhs argument of data operand.
1076 L: -value ok in rhs argument of data operand.
1077 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1078 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1079 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1080 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1081 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1082 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1083 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1084 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1085 : 0)
1086
1087 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1088 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1089 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1090 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1091 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1092 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1093 && ((VAL) & 3) == 0) : \
1094 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1095 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1096 : 0)
1097
1098 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1099 (TARGET_ARM ? \
1100 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1101
1102 /* Constant letter 'G' for the FP immediate constants.
1103 'H' means the same constant negated. */
1104 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1105 ((C) == 'G' ? arm_const_double_rtx (X) : \
1106 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1107
1108 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1109 (TARGET_ARM ? \
1110 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1111
1112 /* For the ARM, `Q' means that this is a memory operand that is just
1113 an offset from a register.
1114 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1115 address. This means that the symbol is in the text segment and can be
1116 accessed without using a load.
1117 'D' Prefixes a number of const_double operands where:
1118 'Da' is a constant that takes two ARM insns to load.
1119 'Db' takes three ARM insns.
1120 'Dc' takes four ARM insns, if we allow that in this compilation.
1121 'U' Prefixes an extended memory constraint where:
1122 'Uv' is an address valid for VFP load/store insns.
1123 'Uy' is an address valid for iwmmxt load/store insns.
1124 'Uq' is an address valid for ldrsb. */
1125
1126 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1127 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1128 || GET_CODE (OP) == CONST_INT \
1129 || GET_CODE (OP) == CONST_VECTOR) \
1130 && (((STR)[1] == 'a' \
1131 && arm_const_double_inline_cost (OP) == 2) \
1132 || ((STR)[1] == 'b' \
1133 && arm_const_double_inline_cost (OP) == 3) \
1134 || ((STR)[1] == 'c' \
1135 && arm_const_double_inline_cost (OP) == 4 \
1136 && !(optimize_size || arm_ld_sched)))) : \
1137 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1138 && GET_CODE (XEXP (OP, 0)) == REG) : \
1139 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1140 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1141 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1142 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1143 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1144 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1145 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1146 ((C) == 'U' && (STR)[1] == 'q') \
1147 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1148 : 0)
1149
1150 #define CONSTRAINT_LEN(C,STR) \
1151 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1152
1153 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1154 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1155 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1156
1157 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1158 (TARGET_ARM \
1159 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1160 : EXTRA_CONSTRAINT_THUMB (X, C))
1161
1162 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1163
1164 /* Given an rtx X being reloaded into a reg required to be
1165 in class CLASS, return the class of reg to actually use.
1166 In general this is just CLASS, but for the Thumb we prefer
1167 a LO_REGS class or a subset. */
1168 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1169 (TARGET_ARM ? (CLASS) : \
1170 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1171
1172 /* Must leave BASE_REGS reloads alone */
1173 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1174 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1175 ? ((true_regnum (X) == -1 ? LO_REGS \
1176 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1177 : NO_REGS)) \
1178 : NO_REGS)
1179
1180 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1181 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1182 ? ((true_regnum (X) == -1 ? LO_REGS \
1183 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1184 : NO_REGS)) \
1185 : NO_REGS)
1186
1187 /* Return the register class of a scratch register needed to copy IN into
1188 or out of a register in CLASS in MODE. If it can be done directly,
1189 NO_REGS is returned. */
1190 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1191 /* Restrict which direct reloads are allowed for VFP regs. */ \
1192 ((TARGET_VFP && TARGET_HARD_FLOAT \
1193 && (CLASS) == VFP_REGS) \
1194 ? vfp_secondary_reload_class (MODE, X) \
1195 : TARGET_ARM \
1196 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1197 ? GENERAL_REGS : NO_REGS) \
1198 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1199
1200 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1201 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1202 /* Restrict which direct reloads are allowed for VFP regs. */ \
1203 ((TARGET_VFP && TARGET_HARD_FLOAT \
1204 && (CLASS) == VFP_REGS) \
1205 ? vfp_secondary_reload_class (MODE, X) : \
1206 /* Cannot load constants into Cirrus registers. */ \
1207 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1208 && (CLASS) == CIRRUS_REGS \
1209 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1210 ? GENERAL_REGS : \
1211 (TARGET_ARM ? \
1212 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1213 && CONSTANT_P (X)) \
1214 ? GENERAL_REGS : \
1215 (((MODE) == HImode && ! arm_arch4 \
1216 && (GET_CODE (X) == MEM \
1217 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1218 && true_regnum (X) == -1))) \
1219 ? GENERAL_REGS : NO_REGS) \
1220 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1221
1222 /* Try a machine-dependent way of reloading an illegitimate address
1223 operand. If we find one, push the reload and jump to WIN. This
1224 macro is used in only one place: `find_reloads_address' in reload.c.
1225
1226 For the ARM, we wish to handle large displacements off a base
1227 register by splitting the addend across a MOV and the mem insn.
1228 This can cut the number of reloads needed. */
1229 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1230 do \
1231 { \
1232 if (GET_CODE (X) == PLUS \
1233 && GET_CODE (XEXP (X, 0)) == REG \
1234 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1235 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1236 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1237 { \
1238 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1239 HOST_WIDE_INT low, high; \
1240 \
1241 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1242 low = ((val & 0xf) ^ 0x8) - 0x8; \
1243 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1244 /* Need to be careful, -256 is not a valid offset. */ \
1245 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1246 else if (MODE == SImode \
1247 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1248 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1249 /* Need to be careful, -4096 is not a valid offset. */ \
1250 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1251 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1252 /* Need to be careful, -256 is not a valid offset. */ \
1253 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1254 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1255 && TARGET_HARD_FLOAT && TARGET_FPA) \
1256 /* Need to be careful, -1024 is not a valid offset. */ \
1257 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1258 else \
1259 break; \
1260 \
1261 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1262 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1263 - (unsigned HOST_WIDE_INT) 0x80000000); \
1264 /* Check for overflow or zero */ \
1265 if (low == 0 || high == 0 || (high + low != val)) \
1266 break; \
1267 \
1268 /* Reload the high part into a base reg; leave the low part \
1269 in the mem. */ \
1270 X = gen_rtx_PLUS (GET_MODE (X), \
1271 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1272 GEN_INT (high)), \
1273 GEN_INT (low)); \
1274 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1275 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1276 VOIDmode, 0, 0, OPNUM, TYPE); \
1277 goto WIN; \
1278 } \
1279 } \
1280 while (0)
1281
1282 /* XXX If an HImode FP+large_offset address is converted to an HImode
1283 SP+large_offset address, then reload won't know how to fix it. It sees
1284 only that SP isn't valid for HImode, and so reloads the SP into an index
1285 register, but the resulting address is still invalid because the offset
1286 is too big. We fix it here instead by reloading the entire address. */
1287 /* We could probably achieve better results by defining PROMOTE_MODE to help
1288 cope with the variances between the Thumb's signed and unsigned byte and
1289 halfword load instructions. */
1290 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1291 do { \
1292 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1293 if (new_x) \
1294 { \
1295 X = new_x; \
1296 goto WIN; \
1297 } \
1298 } while (0)
1299
1300 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1301 if (TARGET_ARM) \
1302 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1303 else \
1304 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1305
1306 /* Return the maximum number of consecutive registers
1307 needed to represent mode MODE in a register of class CLASS.
1308 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1309 #define CLASS_MAX_NREGS(CLASS, MODE) \
1310 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1311
1312 /* If defined, gives a class of registers that cannot be used as the
1313 operand of a SUBREG that changes the mode of the object illegally. */
1314
1315 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1316 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1317 (TARGET_ARM ? \
1318 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1319 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1320 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1321 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1322 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1323 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1324 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1325 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1326 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1327 2) \
1328 : \
1329 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1330 \f
1331 /* Stack layout; function entry, exit and calling. */
1332
1333 /* Define this if pushing a word on the stack
1334 makes the stack pointer a smaller address. */
1335 #define STACK_GROWS_DOWNWARD 1
1336
1337 /* Define this to nonzero if the nominal address of the stack frame
1338 is at the high-address end of the local variables;
1339 that is, each additional local variable allocated
1340 goes at a more negative offset in the frame. */
1341 #define FRAME_GROWS_DOWNWARD 1
1342
1343 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1344 When present, it is one word in size, and sits at the top of the frame,
1345 between the soft frame pointer and either r7 or r11.
1346
1347 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1348 and only then if some outgoing arguments are passed on the stack. It would
1349 be tempting to also check whether the stack arguments are passed by indirect
1350 calls, but there seems to be no reason in principle why a post-reload pass
1351 couldn't convert a direct call into an indirect one. */
1352 #define CALLER_INTERWORKING_SLOT_SIZE \
1353 (TARGET_CALLER_INTERWORKING \
1354 && current_function_outgoing_args_size != 0 \
1355 ? UNITS_PER_WORD : 0)
1356
1357 /* Offset within stack frame to start allocating local variables at.
1358 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1359 first local allocated. Otherwise, it is the offset to the BEGINNING
1360 of the first local allocated. */
1361 #define STARTING_FRAME_OFFSET 0
1362
1363 /* If we generate an insn to push BYTES bytes,
1364 this says how many the stack pointer really advances by. */
1365 /* The push insns do not do this rounding implicitly.
1366 So don't define this. */
1367 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1368
1369 /* Define this if the maximum size of all the outgoing args is to be
1370 accumulated and pushed during the prologue. The amount can be
1371 found in the variable current_function_outgoing_args_size. */
1372 #define ACCUMULATE_OUTGOING_ARGS 1
1373
1374 /* Offset of first parameter from the argument pointer register value. */
1375 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1376
1377 /* Value is the number of byte of arguments automatically
1378 popped when returning from a subroutine call.
1379 FUNDECL is the declaration node of the function (as a tree),
1380 FUNTYPE is the data type of the function (as a tree),
1381 or for a library call it is an identifier node for the subroutine name.
1382 SIZE is the number of bytes of arguments passed on the stack.
1383
1384 On the ARM, the caller does not pop any of its arguments that were passed
1385 on the stack. */
1386 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1387
1388 /* Define how to find the value returned by a library function
1389 assuming the value has mode MODE. */
1390 #define LIBCALL_VALUE(MODE) \
1391 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1392 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1393 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1394 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1395 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1396 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1397 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1398 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1399 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1400
1401 /* Define how to find the value returned by a function.
1402 VALTYPE is the data type of the value (as a tree).
1403 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1404 otherwise, FUNC is 0. */
1405 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1406 arm_function_value (VALTYPE, FUNC);
1407
1408 /* 1 if N is a possible register number for a function value.
1409 On the ARM, only r0 and f0 can return results. */
1410 /* On a Cirrus chip, mvf0 can return results. */
1411 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1412 ((REGNO) == ARG_REGISTER (1) \
1413 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1414 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1415 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1416 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1417 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1418
1419 /* Amount of memory needed for an untyped call to save all possible return
1420 registers. */
1421 #define APPLY_RESULT_SIZE arm_apply_result_size()
1422
1423 /* How large values are returned */
1424 /* A C expression which can inhibit the returning of certain function values
1425 in registers, based on the type of value. */
1426 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1427
1428 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1429 values must be in memory. On the ARM, they need only do so if larger
1430 than a word, or if they contain elements offset from zero in the struct. */
1431 #define DEFAULT_PCC_STRUCT_RETURN 0
1432
1433 /* Flags for the call/call_value rtl operations set up by function_arg. */
1434 #define CALL_NORMAL 0x00000000 /* No special processing. */
1435 #define CALL_LONG 0x00000001 /* Always call indirect. */
1436 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1437
1438 /* These bits describe the different types of function supported
1439 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1440 normal function and an interworked function, for example. Knowing the
1441 type of a function is important for determining its prologue and
1442 epilogue sequences.
1443 Note value 7 is currently unassigned. Also note that the interrupt
1444 function types all have bit 2 set, so that they can be tested for easily.
1445 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1446 machine_function structure is initialized (to zero) func_type will
1447 default to unknown. This will force the first use of arm_current_func_type
1448 to call arm_compute_func_type. */
1449 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1450 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1451 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1452 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1453 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1454 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1455
1456 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1457
1458 /* In addition functions can have several type modifiers,
1459 outlined by these bit masks: */
1460 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1461 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1462 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1463 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1464
1465 /* Some macros to test these flags. */
1466 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1467 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1468 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1469 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1470 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1471
1472
1473 /* Structure used to hold the function stack frame layout. Offsets are
1474 relative to the stack pointer on function entry. Positive offsets are
1475 in the direction of stack growth.
1476 Only soft_frame is used in thumb mode. */
1477
1478 typedef struct arm_stack_offsets GTY(())
1479 {
1480 int saved_args; /* ARG_POINTER_REGNUM. */
1481 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1482 int saved_regs;
1483 int soft_frame; /* FRAME_POINTER_REGNUM. */
1484 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1485 int outgoing_args; /* STACK_POINTER_REGNUM. */
1486 }
1487 arm_stack_offsets;
1488
1489 /* A C structure for machine-specific, per-function data.
1490 This is added to the cfun structure. */
1491 typedef struct machine_function GTY(())
1492 {
1493 /* Additional stack adjustment in __builtin_eh_throw. */
1494 rtx eh_epilogue_sp_ofs;
1495 /* Records if LR has to be saved for far jumps. */
1496 int far_jump_used;
1497 /* Records if ARG_POINTER was ever live. */
1498 int arg_pointer_live;
1499 /* Records if the save of LR has been eliminated. */
1500 int lr_save_eliminated;
1501 /* The size of the stack frame. Only valid after reload. */
1502 arm_stack_offsets stack_offsets;
1503 /* Records the type of the current function. */
1504 unsigned long func_type;
1505 /* Record if the function has a variable argument list. */
1506 int uses_anonymous_args;
1507 /* Records if sibcalls are blocked because an argument
1508 register is needed to preserve stack alignment. */
1509 int sibcall_blocked;
1510 /* Labels for per-function Thumb call-via stubs. One per potential calling
1511 register. We can never call via LR or PC. We can call via SP if a
1512 trampoline happens to be on the top of the stack. */
1513 rtx call_via[14];
1514 }
1515 machine_function;
1516
1517 /* As in the machine_function, a global set of call-via labels, for code
1518 that is in text_section(). */
1519 extern GTY(()) rtx thumb_call_via_label[14];
1520
1521 /* A C type for declaring a variable that is used as the first argument of
1522 `FUNCTION_ARG' and other related values. For some target machines, the
1523 type `int' suffices and can hold the number of bytes of argument so far. */
1524 typedef struct
1525 {
1526 /* This is the number of registers of arguments scanned so far. */
1527 int nregs;
1528 /* This is the number of iWMMXt register arguments scanned so far. */
1529 int iwmmxt_nregs;
1530 int named_count;
1531 int nargs;
1532 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1533 int call_cookie;
1534 int can_split;
1535 } CUMULATIVE_ARGS;
1536
1537 /* Define where to put the arguments to a function.
1538 Value is zero to push the argument on the stack,
1539 or a hard register in which to store the argument.
1540
1541 MODE is the argument's machine mode.
1542 TYPE is the data type of the argument (as a tree).
1543 This is null for libcalls where that information may
1544 not be available.
1545 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1546 the preceding args and about the function being called.
1547 NAMED is nonzero if this argument is a named parameter
1548 (otherwise it is an extra parameter matching an ellipsis).
1549
1550 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1551 other arguments are passed on the stack. If (NAMED == 0) (which happens
1552 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1553 defined), say it is passed in the stack (function_prologue will
1554 indeed make it pass in the stack if necessary). */
1555 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1556 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1557
1558 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1559 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1560
1561 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1562 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1563
1564 /* For AAPCS, padding should never be below the argument. For other ABIs,
1565 * mimic the default. */
1566 #define PAD_VARARGS_DOWN \
1567 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1568
1569 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1570 for a call to a function whose data type is FNTYPE.
1571 For a library call, FNTYPE is 0.
1572 On the ARM, the offset starts at 0. */
1573 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1574 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1575
1576 /* Update the data in CUM to advance over an argument
1577 of mode MODE and data type TYPE.
1578 (TYPE is null for libcalls where that information may not be available.) */
1579 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1580 (CUM).nargs += 1; \
1581 if (arm_vector_mode_supported_p (MODE) \
1582 && (CUM).named_count > (CUM).nargs) \
1583 (CUM).iwmmxt_nregs += 1; \
1584 else \
1585 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1586
1587 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1588 argument with the specified mode and type. If it is not defined,
1589 `PARM_BOUNDARY' is used for all arguments. */
1590 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1591 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1592 ? DOUBLEWORD_ALIGNMENT \
1593 : PARM_BOUNDARY )
1594
1595 /* 1 if N is a possible register number for function argument passing.
1596 On the ARM, r0-r3 are used to pass args. */
1597 #define FUNCTION_ARG_REGNO_P(REGNO) \
1598 (IN_RANGE ((REGNO), 0, 3) \
1599 || (TARGET_IWMMXT_ABI \
1600 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1601
1602 \f
1603 /* If your target environment doesn't prefix user functions with an
1604 underscore, you may wish to re-define this to prevent any conflicts.
1605 e.g. AOF may prefix mcount with an underscore. */
1606 #ifndef ARM_MCOUNT_NAME
1607 #define ARM_MCOUNT_NAME "*mcount"
1608 #endif
1609
1610 /* Call the function profiler with a given profile label. The Acorn
1611 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1612 On the ARM the full profile code will look like:
1613 .data
1614 LP1
1615 .word 0
1616 .text
1617 mov ip, lr
1618 bl mcount
1619 .word LP1
1620
1621 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1622 will output the .text section.
1623
1624 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1625 ``prof'' doesn't seem to mind about this!
1626
1627 Note - this version of the code is designed to work in both ARM and
1628 Thumb modes. */
1629 #ifndef ARM_FUNCTION_PROFILER
1630 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1631 { \
1632 char temp[20]; \
1633 rtx sym; \
1634 \
1635 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1636 IP_REGNUM, LR_REGNUM); \
1637 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1638 fputc ('\n', STREAM); \
1639 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1640 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1641 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1642 }
1643 #endif
1644
1645 #ifdef THUMB_FUNCTION_PROFILER
1646 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1647 if (TARGET_ARM) \
1648 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1649 else \
1650 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1651 #else
1652 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1653 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1654 #endif
1655
1656 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1657 the stack pointer does not matter. The value is tested only in
1658 functions that have frame pointers.
1659 No definition is equivalent to always zero.
1660
1661 On the ARM, the function epilogue recovers the stack pointer from the
1662 frame. */
1663 #define EXIT_IGNORE_STACK 1
1664
1665 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1666
1667 /* Determine if the epilogue should be output as RTL.
1668 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1669 #define USE_RETURN_INSN(ISCOND) \
1670 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1671
1672 /* Definitions for register eliminations.
1673
1674 This is an array of structures. Each structure initializes one pair
1675 of eliminable registers. The "from" register number is given first,
1676 followed by "to". Eliminations of the same "from" register are listed
1677 in order of preference.
1678
1679 We have two registers that can be eliminated on the ARM. First, the
1680 arg pointer register can often be eliminated in favor of the stack
1681 pointer register. Secondly, the pseudo frame pointer register can always
1682 be eliminated; it is replaced with either the stack or the real frame
1683 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1684 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1685
1686 #define ELIMINABLE_REGS \
1687 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1688 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1689 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1690 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1691 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1692 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1693 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1694
1695 /* Given FROM and TO register numbers, say whether this elimination is
1696 allowed. Frame pointer elimination is automatically handled.
1697
1698 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1699 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1700 pointer, we must eliminate FRAME_POINTER_REGNUM into
1701 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1702 ARG_POINTER_REGNUM. */
1703 #define CAN_ELIMINATE(FROM, TO) \
1704 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1705 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1706 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1707 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1708 1)
1709
1710 /* Define the offset between two registers, one to be eliminated, and the
1711 other its replacement, at the start of a routine. */
1712 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1713 if (TARGET_ARM) \
1714 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1715 else \
1716 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1717
1718 /* Special case handling of the location of arguments passed on the stack. */
1719 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1720
1721 /* Initialize data used by insn expanders. This is called from insn_emit,
1722 once for every function before code is generated. */
1723 #define INIT_EXPANDERS arm_init_expanders ()
1724
1725 /* Output assembler code for a block containing the constant parts
1726 of a trampoline, leaving space for the variable parts.
1727
1728 On the ARM, (if r8 is the static chain regnum, and remembering that
1729 referencing pc adds an offset of 8) the trampoline looks like:
1730 ldr r8, [pc, #0]
1731 ldr pc, [pc]
1732 .word static chain value
1733 .word function's address
1734 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1735 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1736 { \
1737 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1738 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1739 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1740 PC_REGNUM, PC_REGNUM); \
1741 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1742 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1743 }
1744
1745 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1746 Why - because it is easier. This code will always be branched to via
1747 a BX instruction and since the compiler magically generates the address
1748 of the function the linker has no opportunity to ensure that the
1749 bottom bit is set. Thus the processor will be in ARM mode when it
1750 reaches this code. So we duplicate the ARM trampoline code and add
1751 a switch into Thumb mode as well. */
1752 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1753 { \
1754 fprintf (FILE, "\t.code 32\n"); \
1755 fprintf (FILE, ".Ltrampoline_start:\n"); \
1756 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1757 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1758 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1759 IP_REGNUM, PC_REGNUM); \
1760 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1761 IP_REGNUM, IP_REGNUM); \
1762 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1763 fprintf (FILE, "\t.word\t0\n"); \
1764 fprintf (FILE, "\t.word\t0\n"); \
1765 fprintf (FILE, "\t.code 16\n"); \
1766 }
1767
1768 #define TRAMPOLINE_TEMPLATE(FILE) \
1769 if (TARGET_ARM) \
1770 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1771 else \
1772 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1773
1774 /* Length in units of the trampoline for entering a nested function. */
1775 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1776
1777 /* Alignment required for a trampoline in bits. */
1778 #define TRAMPOLINE_ALIGNMENT 32
1779
1780
1781 /* Emit RTL insns to initialize the variable parts of a trampoline.
1782 FNADDR is an RTX for the address of the function's pure code.
1783 CXT is an RTX for the static chain value for the function. */
1784 #ifndef INITIALIZE_TRAMPOLINE
1785 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1786 { \
1787 emit_move_insn (gen_rtx_MEM (SImode, \
1788 plus_constant (TRAMP, \
1789 TARGET_ARM ? 8 : 16)), \
1790 CXT); \
1791 emit_move_insn (gen_rtx_MEM (SImode, \
1792 plus_constant (TRAMP, \
1793 TARGET_ARM ? 12 : 20)), \
1794 FNADDR); \
1795 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1796 0, VOIDmode, 2, TRAMP, Pmode, \
1797 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1798 }
1799 #endif
1800
1801 \f
1802 /* Addressing modes, and classification of registers for them. */
1803 #define HAVE_POST_INCREMENT 1
1804 #define HAVE_PRE_INCREMENT TARGET_ARM
1805 #define HAVE_POST_DECREMENT TARGET_ARM
1806 #define HAVE_PRE_DECREMENT TARGET_ARM
1807 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1808 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1809 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1810 #define HAVE_POST_MODIFY_REG TARGET_ARM
1811
1812 /* Macros to check register numbers against specific register classes. */
1813
1814 /* These assume that REGNO is a hard or pseudo reg number.
1815 They give nonzero only if REGNO is a hard reg of the suitable class
1816 or a pseudo reg currently allocated to a suitable hard reg.
1817 Since they use reg_renumber, they are safe only once reg_renumber
1818 has been allocated, which happens in local-alloc.c. */
1819 #define TEST_REGNO(R, TEST, VALUE) \
1820 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1821
1822 /* On the ARM, don't allow the pc to be used. */
1823 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1824 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1825 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1826 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1827
1828 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1829 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1830 || (GET_MODE_SIZE (MODE) >= 4 \
1831 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1832
1833 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1834 (TARGET_THUMB \
1835 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1836 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1837
1838 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1839 For Thumb, we can not use SP + reg, so reject SP. */
1840 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1841 REGNO_OK_FOR_INDEX_P (X)
1842
1843 /* For ARM code, we don't care about the mode, but for Thumb, the index
1844 must be suitable for use in a QImode load. */
1845 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1846 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1847
1848 /* Maximum number of registers that can appear in a valid memory address.
1849 Shifts in addresses can't be by a register. */
1850 #define MAX_REGS_PER_ADDRESS 2
1851
1852 /* Recognize any constant value that is a valid address. */
1853 /* XXX We can address any constant, eventually... */
1854
1855 #ifdef AOF_ASSEMBLER
1856
1857 #define CONSTANT_ADDRESS_P(X) \
1858 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1859
1860 #else
1861
1862 #define CONSTANT_ADDRESS_P(X) \
1863 (GET_CODE (X) == SYMBOL_REF \
1864 && (CONSTANT_POOL_ADDRESS_P (X) \
1865 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1866
1867 #endif /* AOF_ASSEMBLER */
1868
1869 /* Nonzero if the constant value X is a legitimate general operand.
1870 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1871
1872 On the ARM, allow any integer (invalid ones are removed later by insn
1873 patterns), nice doubles and symbol_refs which refer to the function's
1874 constant pool XXX.
1875
1876 When generating pic allow anything. */
1877 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1878
1879 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1880 ( GET_CODE (X) == CONST_INT \
1881 || GET_CODE (X) == CONST_DOUBLE \
1882 || CONSTANT_ADDRESS_P (X) \
1883 || flag_pic)
1884
1885 #define LEGITIMATE_CONSTANT_P(X) \
1886 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1887
1888 /* Special characters prefixed to function names
1889 in order to encode attribute like information.
1890 Note, '@' and '*' have already been taken. */
1891 #define SHORT_CALL_FLAG_CHAR '^'
1892 #define LONG_CALL_FLAG_CHAR '#'
1893
1894 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1895 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1896
1897 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1898 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1899
1900 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1901 #define SUBTARGET_NAME_ENCODING_LENGTHS
1902 #endif
1903
1904 /* This is a C fragment for the inside of a switch statement.
1905 Each case label should return the number of characters to
1906 be stripped from the start of a function's name, if that
1907 name starts with the indicated character. */
1908 #define ARM_NAME_ENCODING_LENGTHS \
1909 case SHORT_CALL_FLAG_CHAR: return 1; \
1910 case LONG_CALL_FLAG_CHAR: return 1; \
1911 case '*': return 1; \
1912 SUBTARGET_NAME_ENCODING_LENGTHS
1913
1914 /* This is how to output a reference to a user-level label named NAME.
1915 `assemble_name' uses this. */
1916 #undef ASM_OUTPUT_LABELREF
1917 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1918 arm_asm_output_labelref (FILE, NAME)
1919
1920 /* The EABI specifies that constructors should go in .init_array.
1921 Other targets use .ctors for compatibility. */
1922 #ifndef ARM_EABI_CTORS_SECTION_OP
1923 #define ARM_EABI_CTORS_SECTION_OP \
1924 "\t.section\t.init_array,\"aw\",%init_array"
1925 #endif
1926 #ifndef ARM_EABI_DTORS_SECTION_OP
1927 #define ARM_EABI_DTORS_SECTION_OP \
1928 "\t.section\t.fini_array,\"aw\",%fini_array"
1929 #endif
1930 #define ARM_CTORS_SECTION_OP \
1931 "\t.section\t.ctors,\"aw\",%progbits"
1932 #define ARM_DTORS_SECTION_OP \
1933 "\t.section\t.dtors,\"aw\",%progbits"
1934
1935 /* Define CTORS_SECTION_ASM_OP. */
1936 #undef CTORS_SECTION_ASM_OP
1937 #undef DTORS_SECTION_ASM_OP
1938 #ifndef IN_LIBGCC2
1939 # define CTORS_SECTION_ASM_OP \
1940 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1941 # define DTORS_SECTION_ASM_OP \
1942 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1943 #else /* !defined (IN_LIBGCC2) */
1944 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1945 so we cannot use the definition above. */
1946 # ifdef __ARM_EABI__
1947 /* The .ctors section is not part of the EABI, so we do not define
1948 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1949 from trying to use it. We do define it when doing normal
1950 compilation, as .init_array can be used instead of .ctors. */
1951 /* There is no need to emit begin or end markers when using
1952 init_array; the dynamic linker will compute the size of the
1953 array itself based on special symbols created by the static
1954 linker. However, we do need to arrange to set up
1955 exception-handling here. */
1956 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1957 # define CTOR_LIST_END /* empty */
1958 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1959 # define DTOR_LIST_END /* empty */
1960 # else /* !defined (__ARM_EABI__) */
1961 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1962 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1963 # endif /* !defined (__ARM_EABI__) */
1964 #endif /* !defined (IN_LIBCC2) */
1965
1966 /* True if the operating system can merge entities with vague linkage
1967 (e.g., symbols in COMDAT group) during dynamic linking. */
1968 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1969 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1970 #endif
1971
1972 /* Set the short-call flag for any function compiled in the current
1973 compilation unit. We skip this for functions with the section
1974 attribute when long-calls are in effect as this tells the compiler
1975 that the section might be placed a long way from the caller.
1976 See arm_is_longcall_p() for more information. */
1977 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1978 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1979 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1980
1981 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1982
1983 #ifdef TARGET_UNWIND_INFO
1984 #define ARM_EABI_UNWIND_TABLES \
1985 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1986 #else
1987 #define ARM_EABI_UNWIND_TABLES 0
1988 #endif
1989
1990 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1991 and check its validity for a certain class.
1992 We have two alternate definitions for each of them.
1993 The usual definition accepts all pseudo regs; the other rejects
1994 them unless they have been allocated suitable hard regs.
1995 The symbol REG_OK_STRICT causes the latter definition to be used. */
1996 #ifndef REG_OK_STRICT
1997
1998 #define ARM_REG_OK_FOR_BASE_P(X) \
1999 (REGNO (X) <= LAST_ARM_REGNUM \
2000 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2001 || REGNO (X) == FRAME_POINTER_REGNUM \
2002 || REGNO (X) == ARG_POINTER_REGNUM)
2003
2004 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2005 (REGNO (X) <= LAST_LO_REGNUM \
2006 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2007 || (GET_MODE_SIZE (MODE) >= 4 \
2008 && (REGNO (X) == STACK_POINTER_REGNUM \
2009 || (X) == hard_frame_pointer_rtx \
2010 || (X) == arg_pointer_rtx)))
2011
2012 #define REG_STRICT_P 0
2013
2014 #else /* REG_OK_STRICT */
2015
2016 #define ARM_REG_OK_FOR_BASE_P(X) \
2017 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2018
2019 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2020 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2021
2022 #define REG_STRICT_P 1
2023
2024 #endif /* REG_OK_STRICT */
2025
2026 /* Now define some helpers in terms of the above. */
2027
2028 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2029 (TARGET_THUMB \
2030 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2031 : ARM_REG_OK_FOR_BASE_P (X))
2032
2033 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2034
2035 /* For Thumb, a valid index register is anything that can be used in
2036 a byte load instruction. */
2037 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2038
2039 /* Nonzero if X is a hard reg that can be used as an index
2040 or if it is a pseudo reg. On the Thumb, the stack pointer
2041 is not suitable. */
2042 #define REG_OK_FOR_INDEX_P(X) \
2043 (TARGET_THUMB \
2044 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2045 : ARM_REG_OK_FOR_INDEX_P (X))
2046
2047 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2048 For Thumb, we can not use SP + reg, so reject SP. */
2049 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2050 REG_OK_FOR_INDEX_P (X)
2051 \f
2052 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2053 that is a valid memory address for an instruction.
2054 The MODE argument is the machine mode for the MEM expression
2055 that wants to use this address. */
2056
2057 #define ARM_BASE_REGISTER_RTX_P(X) \
2058 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2059
2060 #define ARM_INDEX_REGISTER_RTX_P(X) \
2061 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2062
2063 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2064 { \
2065 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2066 goto WIN; \
2067 }
2068
2069 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2070 { \
2071 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2072 goto WIN; \
2073 }
2074
2075 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2076 if (TARGET_ARM) \
2077 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2078 else /* if (TARGET_THUMB) */ \
2079 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2080
2081 \f
2082 /* Try machine-dependent ways of modifying an illegitimate address
2083 to be legitimate. If we find one, return the new, valid address. */
2084 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2085 do { \
2086 X = arm_legitimize_address (X, OLDX, MODE); \
2087 } while (0)
2088
2089 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2090 do { \
2091 X = thumb_legitimize_address (X, OLDX, MODE); \
2092 } while (0)
2093
2094 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2095 do { \
2096 if (TARGET_ARM) \
2097 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2098 else \
2099 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2100 \
2101 if (memory_address_p (MODE, X)) \
2102 goto WIN; \
2103 } while (0)
2104
2105 /* Go to LABEL if ADDR (a legitimate address expression)
2106 has an effect that depends on the machine mode it is used for. */
2107 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2108 { \
2109 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2110 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2111 goto LABEL; \
2112 }
2113
2114 /* Nothing helpful to do for the Thumb */
2115 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2116 if (TARGET_ARM) \
2117 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2118 \f
2119
2120 /* Specify the machine mode that this machine uses
2121 for the index in the tablejump instruction. */
2122 #define CASE_VECTOR_MODE Pmode
2123
2124 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2125 unsigned is probably best, but may break some code. */
2126 #ifndef DEFAULT_SIGNED_CHAR
2127 #define DEFAULT_SIGNED_CHAR 0
2128 #endif
2129
2130 /* Max number of bytes we can move from memory to memory
2131 in one reasonably fast instruction. */
2132 #define MOVE_MAX 4
2133
2134 #undef MOVE_RATIO
2135 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2136
2137 /* Define if operations between registers always perform the operation
2138 on the full register even if a narrower mode is specified. */
2139 #define WORD_REGISTER_OPERATIONS
2140
2141 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2142 will either zero-extend or sign-extend. The value of this macro should
2143 be the code that says which one of the two operations is implicitly
2144 done, UNKNOWN if none. */
2145 #define LOAD_EXTEND_OP(MODE) \
2146 (TARGET_THUMB ? ZERO_EXTEND : \
2147 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2148 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2149
2150 /* Nonzero if access to memory by bytes is slow and undesirable. */
2151 #define SLOW_BYTE_ACCESS 0
2152
2153 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2154
2155 /* Immediate shift counts are truncated by the output routines (or was it
2156 the assembler?). Shift counts in a register are truncated by ARM. Note
2157 that the native compiler puts too large (> 32) immediate shift counts
2158 into a register and shifts by the register, letting the ARM decide what
2159 to do instead of doing that itself. */
2160 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2161 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2162 On the arm, Y in a register is used modulo 256 for the shift. Only for
2163 rotates is modulo 32 used. */
2164 /* #define SHIFT_COUNT_TRUNCATED 1 */
2165
2166 /* All integers have the same format so truncation is easy. */
2167 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2168
2169 /* Calling from registers is a massive pain. */
2170 #define NO_FUNCTION_CSE 1
2171
2172 /* The machine modes of pointers and functions */
2173 #define Pmode SImode
2174 #define FUNCTION_MODE Pmode
2175
2176 #define ARM_FRAME_RTX(X) \
2177 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2178 || (X) == arg_pointer_rtx)
2179
2180 /* Moves to and from memory are quite expensive */
2181 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2182 (TARGET_ARM ? 10 : \
2183 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2184 * (CLASS == LO_REGS ? 1 : 2)))
2185
2186 /* Try to generate sequences that don't involve branches, we can then use
2187 conditional instructions */
2188 #define BRANCH_COST \
2189 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2190 \f
2191 /* Position Independent Code. */
2192 /* We decide which register to use based on the compilation options and
2193 the assembler in use; this is more general than the APCS restriction of
2194 using sb (r9) all the time. */
2195 extern int arm_pic_register;
2196
2197 /* The register number of the register used to address a table of static
2198 data addresses in memory. */
2199 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2200
2201 /* We can't directly access anything that contains a symbol,
2202 nor can we indirect via the constant pool. */
2203 #define LEGITIMATE_PIC_OPERAND_P(X) \
2204 (!(symbol_mentioned_p (X) \
2205 || label_mentioned_p (X) \
2206 || (GET_CODE (X) == SYMBOL_REF \
2207 && CONSTANT_POOL_ADDRESS_P (X) \
2208 && (symbol_mentioned_p (get_pool_constant (X)) \
2209 || label_mentioned_p (get_pool_constant (X))))))
2210
2211 /* We need to know when we are making a constant pool; this determines
2212 whether data needs to be in the GOT or can be referenced via a GOT
2213 offset. */
2214 extern int making_const_table;
2215 \f
2216 /* Handle pragmas for compatibility with Intel's compilers. */
2217 #define REGISTER_TARGET_PRAGMAS() do { \
2218 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2219 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2220 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2221 } while (0)
2222
2223 /* Condition code information. */
2224 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2225 return the mode to be used for the comparison. */
2226
2227 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2228
2229 #define REVERSIBLE_CC_MODE(MODE) 1
2230
2231 #define REVERSE_CONDITION(CODE,MODE) \
2232 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2233 ? reverse_condition_maybe_unordered (code) \
2234 : reverse_condition (code))
2235
2236 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2237 do \
2238 { \
2239 if (GET_CODE (OP1) == CONST_INT \
2240 && ! (const_ok_for_arm (INTVAL (OP1)) \
2241 || (const_ok_for_arm (- INTVAL (OP1))))) \
2242 { \
2243 rtx const_op = OP1; \
2244 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2245 &const_op); \
2246 OP1 = const_op; \
2247 } \
2248 } \
2249 while (0)
2250
2251 /* The arm5 clz instruction returns 32. */
2252 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2253 \f
2254 #undef ASM_APP_OFF
2255 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2256
2257 /* Output a push or a pop instruction (only used when profiling). */
2258 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2259 do \
2260 { \
2261 if (TARGET_ARM) \
2262 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2263 STACK_POINTER_REGNUM, REGNO); \
2264 else \
2265 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2266 } while (0)
2267
2268
2269 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2270 do \
2271 { \
2272 if (TARGET_ARM) \
2273 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2274 STACK_POINTER_REGNUM, REGNO); \
2275 else \
2276 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2277 } while (0)
2278
2279 /* This is how to output a label which precedes a jumptable. Since
2280 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2281 #undef ASM_OUTPUT_CASE_LABEL
2282 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2283 do \
2284 { \
2285 if (TARGET_THUMB) \
2286 ASM_OUTPUT_ALIGN (FILE, 2); \
2287 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2288 } \
2289 while (0)
2290
2291 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2292 do \
2293 { \
2294 if (TARGET_THUMB) \
2295 { \
2296 if (is_called_in_ARM_mode (DECL) \
2297 || current_function_is_thunk) \
2298 fprintf (STREAM, "\t.code 32\n") ; \
2299 else \
2300 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2301 } \
2302 if (TARGET_POKE_FUNCTION_NAME) \
2303 arm_poke_function_name (STREAM, (char *) NAME); \
2304 } \
2305 while (0)
2306
2307 /* For aliases of functions we use .thumb_set instead. */
2308 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2309 do \
2310 { \
2311 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2312 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2313 \
2314 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2315 { \
2316 fprintf (FILE, "\t.thumb_set "); \
2317 assemble_name (FILE, LABEL1); \
2318 fprintf (FILE, ","); \
2319 assemble_name (FILE, LABEL2); \
2320 fprintf (FILE, "\n"); \
2321 } \
2322 else \
2323 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2324 } \
2325 while (0)
2326
2327 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2328 /* To support -falign-* switches we need to use .p2align so
2329 that alignment directives in code sections will be padded
2330 with no-op instructions, rather than zeroes. */
2331 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2332 if ((LOG) != 0) \
2333 { \
2334 if ((MAX_SKIP) == 0) \
2335 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2336 else \
2337 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2338 (int) (LOG), (int) (MAX_SKIP)); \
2339 }
2340 #endif
2341 \f
2342 /* Only perform branch elimination (by making instructions conditional) if
2343 we're optimizing. Otherwise it's of no use anyway. */
2344 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2345 if (TARGET_ARM && optimize) \
2346 arm_final_prescan_insn (INSN); \
2347 else if (TARGET_THUMB) \
2348 thumb_final_prescan_insn (INSN)
2349
2350 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2351 (CODE == '@' || CODE == '|' \
2352 || (TARGET_ARM && (CODE == '?')) \
2353 || (TARGET_THUMB && (CODE == '_')))
2354
2355 /* Output an operand of an instruction. */
2356 #define PRINT_OPERAND(STREAM, X, CODE) \
2357 arm_print_operand (STREAM, X, CODE)
2358
2359 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2360 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2361 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2362 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2363 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2364 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2365 : 0))))
2366
2367 /* Output the address of an operand. */
2368 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2369 { \
2370 int is_minus = GET_CODE (X) == MINUS; \
2371 \
2372 if (GET_CODE (X) == REG) \
2373 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2374 else if (GET_CODE (X) == PLUS || is_minus) \
2375 { \
2376 rtx base = XEXP (X, 0); \
2377 rtx index = XEXP (X, 1); \
2378 HOST_WIDE_INT offset = 0; \
2379 if (GET_CODE (base) != REG) \
2380 { \
2381 /* Ensure that BASE is a register. */ \
2382 /* (one of them must be). */ \
2383 rtx temp = base; \
2384 base = index; \
2385 index = temp; \
2386 } \
2387 switch (GET_CODE (index)) \
2388 { \
2389 case CONST_INT: \
2390 offset = INTVAL (index); \
2391 if (is_minus) \
2392 offset = -offset; \
2393 asm_fprintf (STREAM, "[%r, #%wd]", \
2394 REGNO (base), offset); \
2395 break; \
2396 \
2397 case REG: \
2398 asm_fprintf (STREAM, "[%r, %s%r]", \
2399 REGNO (base), is_minus ? "-" : "", \
2400 REGNO (index)); \
2401 break; \
2402 \
2403 case MULT: \
2404 case ASHIFTRT: \
2405 case LSHIFTRT: \
2406 case ASHIFT: \
2407 case ROTATERT: \
2408 { \
2409 asm_fprintf (STREAM, "[%r, %s%r", \
2410 REGNO (base), is_minus ? "-" : "", \
2411 REGNO (XEXP (index, 0))); \
2412 arm_print_operand (STREAM, index, 'S'); \
2413 fputs ("]", STREAM); \
2414 break; \
2415 } \
2416 \
2417 default: \
2418 gcc_unreachable (); \
2419 } \
2420 } \
2421 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2422 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2423 { \
2424 extern enum machine_mode output_memory_reference_mode; \
2425 \
2426 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2427 \
2428 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2429 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2430 REGNO (XEXP (X, 0)), \
2431 GET_CODE (X) == PRE_DEC ? "-" : "", \
2432 GET_MODE_SIZE (output_memory_reference_mode)); \
2433 else \
2434 asm_fprintf (STREAM, "[%r], #%s%d", \
2435 REGNO (XEXP (X, 0)), \
2436 GET_CODE (X) == POST_DEC ? "-" : "", \
2437 GET_MODE_SIZE (output_memory_reference_mode)); \
2438 } \
2439 else if (GET_CODE (X) == PRE_MODIFY) \
2440 { \
2441 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2442 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2443 asm_fprintf (STREAM, "#%wd]!", \
2444 INTVAL (XEXP (XEXP (X, 1), 1))); \
2445 else \
2446 asm_fprintf (STREAM, "%r]!", \
2447 REGNO (XEXP (XEXP (X, 1), 1))); \
2448 } \
2449 else if (GET_CODE (X) == POST_MODIFY) \
2450 { \
2451 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2452 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2453 asm_fprintf (STREAM, "#%wd", \
2454 INTVAL (XEXP (XEXP (X, 1), 1))); \
2455 else \
2456 asm_fprintf (STREAM, "%r", \
2457 REGNO (XEXP (XEXP (X, 1), 1))); \
2458 } \
2459 else output_addr_const (STREAM, X); \
2460 }
2461
2462 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2463 { \
2464 if (GET_CODE (X) == REG) \
2465 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2466 else if (GET_CODE (X) == POST_INC) \
2467 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2468 else if (GET_CODE (X) == PLUS) \
2469 { \
2470 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2471 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2472 asm_fprintf (STREAM, "[%r, #%wd]", \
2473 REGNO (XEXP (X, 0)), \
2474 INTVAL (XEXP (X, 1))); \
2475 else \
2476 asm_fprintf (STREAM, "[%r, %r]", \
2477 REGNO (XEXP (X, 0)), \
2478 REGNO (XEXP (X, 1))); \
2479 } \
2480 else \
2481 output_addr_const (STREAM, X); \
2482 }
2483
2484 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2485 if (TARGET_ARM) \
2486 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2487 else \
2488 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2489
2490 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2491 if (GET_CODE (X) != CONST_VECTOR \
2492 || ! arm_emit_vector_const (FILE, X)) \
2493 goto FAIL;
2494
2495 /* A C expression whose value is RTL representing the value of the return
2496 address for the frame COUNT steps up from the current frame. */
2497
2498 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2499 arm_return_addr (COUNT, FRAME)
2500
2501 /* Mask of the bits in the PC that contain the real return address
2502 when running in 26-bit mode. */
2503 #define RETURN_ADDR_MASK26 (0x03fffffc)
2504
2505 /* Pick up the return address upon entry to a procedure. Used for
2506 dwarf2 unwind information. This also enables the table driven
2507 mechanism. */
2508 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2509 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2510
2511 /* Used to mask out junk bits from the return address, such as
2512 processor state, interrupt status, condition codes and the like. */
2513 #define MASK_RETURN_ADDR \
2514 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2515 in 26 bit mode, the condition codes must be masked out of the \
2516 return address. This does not apply to ARM6 and later processors \
2517 when running in 32 bit mode. */ \
2518 ((arm_arch4 || TARGET_THUMB) \
2519 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2520 : arm_gen_return_addr_mask ())
2521
2522 \f
2523 enum arm_builtins
2524 {
2525 ARM_BUILTIN_GETWCX,
2526 ARM_BUILTIN_SETWCX,
2527
2528 ARM_BUILTIN_WZERO,
2529
2530 ARM_BUILTIN_WAVG2BR,
2531 ARM_BUILTIN_WAVG2HR,
2532 ARM_BUILTIN_WAVG2B,
2533 ARM_BUILTIN_WAVG2H,
2534
2535 ARM_BUILTIN_WACCB,
2536 ARM_BUILTIN_WACCH,
2537 ARM_BUILTIN_WACCW,
2538
2539 ARM_BUILTIN_WMACS,
2540 ARM_BUILTIN_WMACSZ,
2541 ARM_BUILTIN_WMACU,
2542 ARM_BUILTIN_WMACUZ,
2543
2544 ARM_BUILTIN_WSADB,
2545 ARM_BUILTIN_WSADBZ,
2546 ARM_BUILTIN_WSADH,
2547 ARM_BUILTIN_WSADHZ,
2548
2549 ARM_BUILTIN_WALIGN,
2550
2551 ARM_BUILTIN_TMIA,
2552 ARM_BUILTIN_TMIAPH,
2553 ARM_BUILTIN_TMIABB,
2554 ARM_BUILTIN_TMIABT,
2555 ARM_BUILTIN_TMIATB,
2556 ARM_BUILTIN_TMIATT,
2557
2558 ARM_BUILTIN_TMOVMSKB,
2559 ARM_BUILTIN_TMOVMSKH,
2560 ARM_BUILTIN_TMOVMSKW,
2561
2562 ARM_BUILTIN_TBCSTB,
2563 ARM_BUILTIN_TBCSTH,
2564 ARM_BUILTIN_TBCSTW,
2565
2566 ARM_BUILTIN_WMADDS,
2567 ARM_BUILTIN_WMADDU,
2568
2569 ARM_BUILTIN_WPACKHSS,
2570 ARM_BUILTIN_WPACKWSS,
2571 ARM_BUILTIN_WPACKDSS,
2572 ARM_BUILTIN_WPACKHUS,
2573 ARM_BUILTIN_WPACKWUS,
2574 ARM_BUILTIN_WPACKDUS,
2575
2576 ARM_BUILTIN_WADDB,
2577 ARM_BUILTIN_WADDH,
2578 ARM_BUILTIN_WADDW,
2579 ARM_BUILTIN_WADDSSB,
2580 ARM_BUILTIN_WADDSSH,
2581 ARM_BUILTIN_WADDSSW,
2582 ARM_BUILTIN_WADDUSB,
2583 ARM_BUILTIN_WADDUSH,
2584 ARM_BUILTIN_WADDUSW,
2585 ARM_BUILTIN_WSUBB,
2586 ARM_BUILTIN_WSUBH,
2587 ARM_BUILTIN_WSUBW,
2588 ARM_BUILTIN_WSUBSSB,
2589 ARM_BUILTIN_WSUBSSH,
2590 ARM_BUILTIN_WSUBSSW,
2591 ARM_BUILTIN_WSUBUSB,
2592 ARM_BUILTIN_WSUBUSH,
2593 ARM_BUILTIN_WSUBUSW,
2594
2595 ARM_BUILTIN_WAND,
2596 ARM_BUILTIN_WANDN,
2597 ARM_BUILTIN_WOR,
2598 ARM_BUILTIN_WXOR,
2599
2600 ARM_BUILTIN_WCMPEQB,
2601 ARM_BUILTIN_WCMPEQH,
2602 ARM_BUILTIN_WCMPEQW,
2603 ARM_BUILTIN_WCMPGTUB,
2604 ARM_BUILTIN_WCMPGTUH,
2605 ARM_BUILTIN_WCMPGTUW,
2606 ARM_BUILTIN_WCMPGTSB,
2607 ARM_BUILTIN_WCMPGTSH,
2608 ARM_BUILTIN_WCMPGTSW,
2609
2610 ARM_BUILTIN_TEXTRMSB,
2611 ARM_BUILTIN_TEXTRMSH,
2612 ARM_BUILTIN_TEXTRMSW,
2613 ARM_BUILTIN_TEXTRMUB,
2614 ARM_BUILTIN_TEXTRMUH,
2615 ARM_BUILTIN_TEXTRMUW,
2616 ARM_BUILTIN_TINSRB,
2617 ARM_BUILTIN_TINSRH,
2618 ARM_BUILTIN_TINSRW,
2619
2620 ARM_BUILTIN_WMAXSW,
2621 ARM_BUILTIN_WMAXSH,
2622 ARM_BUILTIN_WMAXSB,
2623 ARM_BUILTIN_WMAXUW,
2624 ARM_BUILTIN_WMAXUH,
2625 ARM_BUILTIN_WMAXUB,
2626 ARM_BUILTIN_WMINSW,
2627 ARM_BUILTIN_WMINSH,
2628 ARM_BUILTIN_WMINSB,
2629 ARM_BUILTIN_WMINUW,
2630 ARM_BUILTIN_WMINUH,
2631 ARM_BUILTIN_WMINUB,
2632
2633 ARM_BUILTIN_WMULUM,
2634 ARM_BUILTIN_WMULSM,
2635 ARM_BUILTIN_WMULUL,
2636
2637 ARM_BUILTIN_PSADBH,
2638 ARM_BUILTIN_WSHUFH,
2639
2640 ARM_BUILTIN_WSLLH,
2641 ARM_BUILTIN_WSLLW,
2642 ARM_BUILTIN_WSLLD,
2643 ARM_BUILTIN_WSRAH,
2644 ARM_BUILTIN_WSRAW,
2645 ARM_BUILTIN_WSRAD,
2646 ARM_BUILTIN_WSRLH,
2647 ARM_BUILTIN_WSRLW,
2648 ARM_BUILTIN_WSRLD,
2649 ARM_BUILTIN_WRORH,
2650 ARM_BUILTIN_WRORW,
2651 ARM_BUILTIN_WRORD,
2652 ARM_BUILTIN_WSLLHI,
2653 ARM_BUILTIN_WSLLWI,
2654 ARM_BUILTIN_WSLLDI,
2655 ARM_BUILTIN_WSRAHI,
2656 ARM_BUILTIN_WSRAWI,
2657 ARM_BUILTIN_WSRADI,
2658 ARM_BUILTIN_WSRLHI,
2659 ARM_BUILTIN_WSRLWI,
2660 ARM_BUILTIN_WSRLDI,
2661 ARM_BUILTIN_WRORHI,
2662 ARM_BUILTIN_WRORWI,
2663 ARM_BUILTIN_WRORDI,
2664
2665 ARM_BUILTIN_WUNPCKIHB,
2666 ARM_BUILTIN_WUNPCKIHH,
2667 ARM_BUILTIN_WUNPCKIHW,
2668 ARM_BUILTIN_WUNPCKILB,
2669 ARM_BUILTIN_WUNPCKILH,
2670 ARM_BUILTIN_WUNPCKILW,
2671
2672 ARM_BUILTIN_WUNPCKEHSB,
2673 ARM_BUILTIN_WUNPCKEHSH,
2674 ARM_BUILTIN_WUNPCKEHSW,
2675 ARM_BUILTIN_WUNPCKEHUB,
2676 ARM_BUILTIN_WUNPCKEHUH,
2677 ARM_BUILTIN_WUNPCKEHUW,
2678 ARM_BUILTIN_WUNPCKELSB,
2679 ARM_BUILTIN_WUNPCKELSH,
2680 ARM_BUILTIN_WUNPCKELSW,
2681 ARM_BUILTIN_WUNPCKELUB,
2682 ARM_BUILTIN_WUNPCKELUH,
2683 ARM_BUILTIN_WUNPCKELUW,
2684
2685 ARM_BUILTIN_MAX
2686 };
2687 #endif /* ! GCC_ARM_H */
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