1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx
, int);
152 static void arm_encode_section_info (tree
, rtx
, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx
arm_struct_value_rtx (tree
, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
168 enum machine_mode
, tree
, bool);
169 static bool arm_promote_prototypes (tree
);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree
);
173 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx
);
176 static bool arm_output_ttype (rtx
);
179 static tree
arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree
arm_get_cookie_size (tree
);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree
);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
191 static bool arm_cannot_copy_insn_p (rtx
);
192 static bool arm_tls_symbol_p (rtx x
);
195 /* Initialize the GCC target structure. */
196 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
197 #undef TARGET_MERGE_DECL_ATTRIBUTES
198 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
201 #undef TARGET_ATTRIBUTE_TABLE
202 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
204 #undef TARGET_ASM_FILE_END
205 #define TARGET_ASM_FILE_END arm_file_end
208 #undef TARGET_ASM_BYTE_OP
209 #define TARGET_ASM_BYTE_OP "\tDCB\t"
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
214 #undef TARGET_ASM_GLOBALIZE_LABEL
215 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
216 #undef TARGET_ASM_FILE_START
217 #define TARGET_ASM_FILE_START aof_file_start
218 #undef TARGET_ASM_FILE_END
219 #define TARGET_ASM_FILE_END aof_file_end
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP NULL
223 #undef TARGET_ASM_INTEGER
224 #define TARGET_ASM_INTEGER arm_assemble_integer
227 #undef TARGET_ASM_FUNCTION_PROLOGUE
228 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
230 #undef TARGET_ASM_FUNCTION_EPILOGUE
231 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
233 #undef TARGET_DEFAULT_TARGET_FLAGS
234 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
235 #undef TARGET_HANDLE_OPTION
236 #define TARGET_HANDLE_OPTION arm_handle_option
238 #undef TARGET_COMP_TYPE_ATTRIBUTES
239 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
241 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
242 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
244 #undef TARGET_SCHED_ADJUST_COST
245 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
247 #undef TARGET_ENCODE_SECTION_INFO
249 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
251 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
254 #undef TARGET_STRIP_NAME_ENCODING
255 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
257 #undef TARGET_ASM_INTERNAL_LABEL
258 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
260 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
261 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
263 #undef TARGET_ASM_OUTPUT_MI_THUNK
264 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
265 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
266 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
268 /* This will be overridden in arm_override_options. */
269 #undef TARGET_RTX_COSTS
270 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
271 #undef TARGET_ADDRESS_COST
272 #define TARGET_ADDRESS_COST arm_address_cost
274 #undef TARGET_SHIFT_TRUNCATION_MASK
275 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
276 #undef TARGET_VECTOR_MODE_SUPPORTED_P
277 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
279 #undef TARGET_MACHINE_DEPENDENT_REORG
280 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
282 #undef TARGET_INIT_BUILTINS
283 #define TARGET_INIT_BUILTINS arm_init_builtins
284 #undef TARGET_EXPAND_BUILTIN
285 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
287 #undef TARGET_INIT_LIBFUNCS
288 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
290 #undef TARGET_PROMOTE_FUNCTION_ARGS
291 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
292 #undef TARGET_PROMOTE_FUNCTION_RETURN
293 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
294 #undef TARGET_PROMOTE_PROTOTYPES
295 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
296 #undef TARGET_PASS_BY_REFERENCE
297 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
298 #undef TARGET_ARG_PARTIAL_BYTES
299 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
301 #undef TARGET_STRUCT_VALUE_RTX
302 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
304 #undef TARGET_SETUP_INCOMING_VARARGS
305 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
307 #undef TARGET_DEFAULT_SHORT_ENUMS
308 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
310 #undef TARGET_ALIGN_ANON_BITFIELD
311 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
313 #undef TARGET_CXX_GUARD_TYPE
314 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
316 #undef TARGET_CXX_GUARD_MASK_BIT
317 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
319 #undef TARGET_CXX_GET_COOKIE_SIZE
320 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
322 #undef TARGET_CXX_COOKIE_HAS_SIZE
323 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
325 #undef TARGET_CXX_CDTOR_RETURNS_THIS
326 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
328 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
329 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
331 #undef TARGET_CXX_USE_AEABI_ATEXIT
332 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
334 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
335 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
336 arm_cxx_determine_class_data_visibility
338 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
339 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
341 #undef TARGET_RETURN_IN_MSB
342 #define TARGET_RETURN_IN_MSB arm_return_in_msb
344 #undef TARGET_MUST_PASS_IN_STACK
345 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
347 #ifdef TARGET_UNWIND_INFO
348 #undef TARGET_UNWIND_EMIT
349 #define TARGET_UNWIND_EMIT arm_unwind_emit
351 /* EABI unwinding tables use a different format for the typeinfo tables. */
352 #undef TARGET_ASM_TTYPE
353 #define TARGET_ASM_TTYPE arm_output_ttype
355 #undef TARGET_ARM_EABI_UNWINDER
356 #define TARGET_ARM_EABI_UNWINDER true
357 #endif /* TARGET_UNWIND_INFO */
359 #undef TARGET_CANNOT_COPY_INSN_P
360 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
363 #undef TARGET_HAVE_TLS
364 #define TARGET_HAVE_TLS true
367 #undef TARGET_CANNOT_FORCE_CONST_MEM
368 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
370 struct gcc_target targetm
= TARGET_INITIALIZER
;
372 /* Obstack for minipool constant handling. */
373 static struct obstack minipool_obstack
;
374 static char * minipool_startobj
;
376 /* The maximum number of insns skipped which
377 will be conditionalised if possible. */
378 static int max_insns_skipped
= 5;
380 extern FILE * asm_out_file
;
382 /* True if we are currently building a constant table. */
383 int making_const_table
;
385 /* Define the information needed to generate branch insns. This is
386 stored from the compare operation. */
387 rtx arm_compare_op0
, arm_compare_op1
;
389 /* The processor for which instructions should be scheduled. */
390 enum processor_type arm_tune
= arm_none
;
392 /* Which floating point model to use. */
393 enum arm_fp_model arm_fp_model
;
395 /* Which floating point hardware is available. */
396 enum fputype arm_fpu_arch
;
398 /* Which floating point hardware to schedule for. */
399 enum fputype arm_fpu_tune
;
401 /* Whether to use floating point hardware. */
402 enum float_abi_type arm_float_abi
;
404 /* Which ABI to use. */
405 enum arm_abi_type arm_abi
;
407 /* Which thread pointer model to use. */
408 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
410 /* Used to parse -mstructure_size_boundary command line option. */
411 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
413 /* Used for Thumb call_via trampolines. */
414 rtx thumb_call_via_label
[14];
415 static int thumb_call_reg_needed
;
417 /* Bit values used to identify processor capabilities. */
418 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
419 #define FL_ARCH3M (1 << 1) /* Extended multiply */
420 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
421 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
422 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
423 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
424 #define FL_THUMB (1 << 6) /* Thumb aware */
425 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
426 #define FL_STRONG (1 << 8) /* StrongARM */
427 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
428 #define FL_XSCALE (1 << 10) /* XScale */
429 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
430 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
431 media instructions. */
432 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
433 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
434 Note: ARM6 & 7 derivatives only. */
435 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
437 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
439 #define FL_FOR_ARCH2 0
440 #define FL_FOR_ARCH3 FL_MODE32
441 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
442 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
443 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
444 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
445 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
446 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
447 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
448 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
449 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
450 #define FL_FOR_ARCH6J FL_FOR_ARCH6
451 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
452 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
453 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
455 /* The bits in this mask specify which
456 instructions we are allowed to generate. */
457 static unsigned long insn_flags
= 0;
459 /* The bits in this mask specify which instruction scheduling options should
461 static unsigned long tune_flags
= 0;
463 /* The following are used in the arm.md file as equivalents to bits
464 in the above two flag variables. */
466 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
469 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
472 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
475 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
478 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
481 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
484 /* Nonzero if this chip supports the ARM 6K extensions. */
487 /* Nonzero if this chip can benefit from load scheduling. */
488 int arm_ld_sched
= 0;
490 /* Nonzero if this chip is a StrongARM. */
491 int arm_tune_strongarm
= 0;
493 /* Nonzero if this chip is a Cirrus variant. */
494 int arm_arch_cirrus
= 0;
496 /* Nonzero if this chip supports Intel Wireless MMX technology. */
497 int arm_arch_iwmmxt
= 0;
499 /* Nonzero if this chip is an XScale. */
500 int arm_arch_xscale
= 0;
502 /* Nonzero if tuning for XScale */
503 int arm_tune_xscale
= 0;
505 /* Nonzero if we want to tune for stores that access the write-buffer.
506 This typically means an ARM6 or ARM7 with MMU or MPU. */
507 int arm_tune_wbuf
= 0;
509 /* Nonzero if generating Thumb instructions. */
512 /* Nonzero if we should define __THUMB_INTERWORK__ in the
514 XXX This is a bit of a hack, it's intended to help work around
515 problems in GLD which doesn't understand that armv5t code is
516 interworking clean. */
517 int arm_cpp_interwork
= 0;
519 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
520 must report the mode of the memory reference from PRINT_OPERAND to
521 PRINT_OPERAND_ADDRESS. */
522 enum machine_mode output_memory_reference_mode
;
524 /* The register number to be used for the PIC offset register. */
525 int arm_pic_register
= INVALID_REGNUM
;
527 /* Set to 1 when a return insn is output, this means that the epilogue
529 int return_used_this_function
;
531 /* Set to 1 after arm_reorg has started. Reset to start at the start of
532 the next function. */
533 static int after_arm_reorg
= 0;
535 /* The maximum number of insns to be used when loading a constant. */
536 static int arm_constant_limit
= 3;
538 /* For an explanation of these variables, see final_prescan_insn below. */
540 enum arm_cond_code arm_current_cc
;
542 int arm_target_label
;
544 /* The condition codes of the ARM, and the inverse function. */
545 static const char * const arm_condition_codes
[] =
547 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
548 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
551 #define streq(string1, string2) (strcmp (string1, string2) == 0)
553 /* Initialization code. */
557 const char *const name
;
558 enum processor_type core
;
560 const unsigned long flags
;
561 bool (* rtx_costs
) (rtx
, int, int, int *);
564 /* Not all of these give usefully different compilation alternatives,
565 but there is no simple way of generalizing them. */
566 static const struct processors all_cores
[] =
569 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
570 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
571 #include "arm-cores.def"
573 {NULL
, arm_none
, NULL
, 0, NULL
}
576 static const struct processors all_architectures
[] =
578 /* ARM Architectures */
579 /* We don't specify rtx_costs here as it will be figured out
582 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
583 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
584 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
585 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
586 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
587 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
588 implementations that support it, so we will leave it out for now. */
589 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
590 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
591 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
592 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
593 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
594 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
595 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
596 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
597 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
598 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
599 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
600 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
601 {NULL
, arm_none
, NULL
, 0 , NULL
}
604 struct arm_cpu_select
608 const struct processors
* processors
;
611 /* This is a magic structure. The 'string' field is magically filled in
612 with a pointer to the value specified by the user on the command line
613 assuming that the user has specified such a value. */
615 static struct arm_cpu_select arm_select
[] =
617 /* string name processors */
618 { NULL
, "-mcpu=", all_cores
},
619 { NULL
, "-march=", all_architectures
},
620 { NULL
, "-mtune=", all_cores
}
623 /* Defines representing the indexes into the above table. */
624 #define ARM_OPT_SET_CPU 0
625 #define ARM_OPT_SET_ARCH 1
626 #define ARM_OPT_SET_TUNE 2
628 /* The name of the proprocessor macro to define for this architecture. */
630 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
639 /* Available values for for -mfpu=. */
641 static const struct fpu_desc all_fpus
[] =
643 {"fpa", FPUTYPE_FPA
},
644 {"fpe2", FPUTYPE_FPA_EMU2
},
645 {"fpe3", FPUTYPE_FPA_EMU2
},
646 {"maverick", FPUTYPE_MAVERICK
},
651 /* Floating point models used by the different hardware.
652 See fputype in arm.h. */
654 static const enum fputype fp_model_for_fpu
[] =
656 /* No FP hardware. */
657 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
658 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
659 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
660 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
661 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
662 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
669 enum float_abi_type abi_type
;
673 /* Available values for -mfloat-abi=. */
675 static const struct float_abi all_float_abis
[] =
677 {"soft", ARM_FLOAT_ABI_SOFT
},
678 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
679 {"hard", ARM_FLOAT_ABI_HARD
}
686 enum arm_abi_type abi_type
;
690 /* Available values for -mabi=. */
692 static const struct abi_name arm_all_abis
[] =
694 {"apcs-gnu", ARM_ABI_APCS
},
695 {"atpcs", ARM_ABI_ATPCS
},
696 {"aapcs", ARM_ABI_AAPCS
},
697 {"iwmmxt", ARM_ABI_IWMMXT
},
698 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
701 /* Supported TLS relocations. */
711 /* Return the number of bits set in VALUE. */
713 bit_count (unsigned long value
)
715 unsigned long count
= 0;
720 value
&= value
- 1; /* Clear the least-significant set bit. */
726 /* Set up library functions unique to ARM. */
729 arm_init_libfuncs (void)
731 /* There are no special library functions unless we are using the
736 /* The functions below are described in Section 4 of the "Run-Time
737 ABI for the ARM architecture", Version 1.0. */
739 /* Double-precision floating-point arithmetic. Table 2. */
740 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
741 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
742 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
743 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
744 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
746 /* Double-precision comparisons. Table 3. */
747 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
748 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
749 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
750 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
751 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
752 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
753 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
755 /* Single-precision floating-point arithmetic. Table 4. */
756 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
757 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
758 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
759 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
760 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
762 /* Single-precision comparisons. Table 5. */
763 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
764 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
765 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
766 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
767 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
768 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
769 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
771 /* Floating-point to integer conversions. Table 6. */
772 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
773 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
774 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
775 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
776 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
777 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
778 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
779 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
781 /* Conversions between floating types. Table 7. */
782 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
783 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
785 /* Integer to floating-point conversions. Table 8. */
786 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
787 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
788 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
789 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
790 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
791 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
792 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
793 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
795 /* Long long. Table 9. */
796 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
797 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
798 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
799 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
800 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
801 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
802 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
803 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
805 /* Integer (32/32->32) division. \S 4.3.1. */
806 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
807 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
809 /* The divmod functions are designed so that they can be used for
810 plain division, even though they return both the quotient and the
811 remainder. The quotient is returned in the usual location (i.e.,
812 r0 for SImode, {r0, r1} for DImode), just as would be expected
813 for an ordinary division routine. Because the AAPCS calling
814 conventions specify that all of { r0, r1, r2, r3 } are
815 callee-saved registers, there is no need to tell the compiler
816 explicitly that those registers are clobbered by these
818 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
819 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
821 /* For SImode division the ABI provides div-without-mod routines,
823 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
824 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
826 /* We don't have mod libcalls. Fortunately gcc knows how to use the
827 divmod libcalls instead. */
828 set_optab_libfunc (smod_optab
, DImode
, NULL
);
829 set_optab_libfunc (umod_optab
, DImode
, NULL
);
830 set_optab_libfunc (smod_optab
, SImode
, NULL
);
831 set_optab_libfunc (umod_optab
, SImode
, NULL
);
834 /* Implement TARGET_HANDLE_OPTION. */
837 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
842 arm_select
[1].string
= arg
;
846 arm_select
[0].string
= arg
;
849 case OPT_mhard_float
:
850 target_float_abi_name
= "hard";
853 case OPT_msoft_float
:
854 target_float_abi_name
= "soft";
858 arm_select
[2].string
= arg
;
866 /* Fix up any incompatible options that the user has specified.
867 This has now turned into a maze. */
869 arm_override_options (void)
872 enum processor_type target_arch_cpu
= arm_none
;
874 /* Set up the flags based on the cpu/architecture selected by the user. */
875 for (i
= ARRAY_SIZE (arm_select
); i
--;)
877 struct arm_cpu_select
* ptr
= arm_select
+ i
;
879 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
881 const struct processors
* sel
;
883 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
884 if (streq (ptr
->string
, sel
->name
))
886 /* Set the architecture define. */
887 if (i
!= ARM_OPT_SET_TUNE
)
888 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
890 /* Determine the processor core for which we should
891 tune code-generation. */
892 if (/* -mcpu= is a sensible default. */
894 /* -mtune= overrides -mcpu= and -march=. */
895 || i
== ARM_OPT_SET_TUNE
)
896 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
898 /* Remember the CPU associated with this architecture.
899 If no other option is used to set the CPU type,
900 we'll use this to guess the most suitable tuning
902 if (i
== ARM_OPT_SET_ARCH
)
903 target_arch_cpu
= sel
->core
;
905 if (i
!= ARM_OPT_SET_TUNE
)
907 /* If we have been given an architecture and a processor
908 make sure that they are compatible. We only generate
909 a warning though, and we prefer the CPU over the
911 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
912 warning (0, "switch -mcpu=%s conflicts with -march= switch",
915 insn_flags
= sel
->flags
;
921 if (sel
->name
== NULL
)
922 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
926 /* Guess the tuning options from the architecture if necessary. */
927 if (arm_tune
== arm_none
)
928 arm_tune
= target_arch_cpu
;
930 /* If the user did not specify a processor, choose one for them. */
933 const struct processors
* sel
;
935 enum processor_type cpu
;
937 cpu
= TARGET_CPU_DEFAULT
;
940 #ifdef SUBTARGET_CPU_DEFAULT
941 /* Use the subtarget default CPU if none was specified by
943 cpu
= SUBTARGET_CPU_DEFAULT
;
945 /* Default to ARM6. */
949 sel
= &all_cores
[cpu
];
951 insn_flags
= sel
->flags
;
953 /* Now check to see if the user has specified some command line
954 switch that require certain abilities from the cpu. */
957 if (TARGET_INTERWORK
|| TARGET_THUMB
)
959 sought
|= (FL_THUMB
| FL_MODE32
);
961 /* There are no ARM processors that support both APCS-26 and
962 interworking. Therefore we force FL_MODE26 to be removed
963 from insn_flags here (if it was set), so that the search
964 below will always be able to find a compatible processor. */
965 insn_flags
&= ~FL_MODE26
;
968 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
970 /* Try to locate a CPU type that supports all of the abilities
971 of the default CPU, plus the extra abilities requested by
973 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
974 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
977 if (sel
->name
== NULL
)
979 unsigned current_bit_count
= 0;
980 const struct processors
* best_fit
= NULL
;
982 /* Ideally we would like to issue an error message here
983 saying that it was not possible to find a CPU compatible
984 with the default CPU, but which also supports the command
985 line options specified by the programmer, and so they
986 ought to use the -mcpu=<name> command line option to
987 override the default CPU type.
989 If we cannot find a cpu that has both the
990 characteristics of the default cpu and the given
991 command line options we scan the array again looking
993 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
994 if ((sel
->flags
& sought
) == sought
)
998 count
= bit_count (sel
->flags
& insn_flags
);
1000 if (count
>= current_bit_count
)
1003 current_bit_count
= count
;
1007 gcc_assert (best_fit
);
1011 insn_flags
= sel
->flags
;
1013 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1014 if (arm_tune
== arm_none
)
1015 arm_tune
= (enum processor_type
) (sel
- all_cores
);
1018 /* The processor for which we should tune should now have been
1020 gcc_assert (arm_tune
!= arm_none
);
1022 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1024 targetm
.rtx_costs
= arm_size_rtx_costs
;
1026 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1028 /* Make sure that the processor choice does not conflict with any of the
1029 other command line choices. */
1030 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1032 warning (0, "target CPU does not support interworking" );
1033 target_flags
&= ~MASK_INTERWORK
;
1036 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1038 warning (0, "target CPU does not support THUMB instructions");
1039 target_flags
&= ~MASK_THUMB
;
1042 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1044 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1045 target_flags
&= ~MASK_APCS_FRAME
;
1048 /* Callee super interworking implies thumb interworking. Adding
1049 this to the flags here simplifies the logic elsewhere. */
1050 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1051 target_flags
|= MASK_INTERWORK
;
1053 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1054 from here where no function is being compiled currently. */
1055 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1056 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1058 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1059 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1061 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1062 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1064 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1066 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1067 target_flags
|= MASK_APCS_FRAME
;
1070 if (TARGET_POKE_FUNCTION_NAME
)
1071 target_flags
|= MASK_APCS_FRAME
;
1073 if (TARGET_APCS_REENT
&& flag_pic
)
1074 error ("-fpic and -mapcs-reent are incompatible");
1076 if (TARGET_APCS_REENT
)
1077 warning (0, "APCS reentrant code not supported. Ignored");
1079 /* If this target is normally configured to use APCS frames, warn if they
1080 are turned off and debugging is turned on. */
1082 && write_symbols
!= NO_DEBUG
1083 && !TARGET_APCS_FRAME
1084 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1085 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1087 /* If stack checking is disabled, we can use r10 as the PIC register,
1088 which keeps r9 available. */
1090 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1092 if (TARGET_APCS_FLOAT
)
1093 warning (0, "passing floating point arguments in fp regs not yet supported");
1095 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1096 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1097 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1098 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1099 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1100 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1101 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1102 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1103 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1104 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1106 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1107 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1108 thumb_code
= (TARGET_ARM
== 0);
1109 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1110 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1111 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1113 /* V5 code we generate is completely interworking capable, so we turn off
1114 TARGET_INTERWORK here to avoid many tests later on. */
1116 /* XXX However, we must pass the right pre-processor defines to CPP
1117 or GLD can get confused. This is a hack. */
1118 if (TARGET_INTERWORK
)
1119 arm_cpp_interwork
= 1;
1122 target_flags
&= ~MASK_INTERWORK
;
1124 if (target_abi_name
)
1126 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1128 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1130 arm_abi
= arm_all_abis
[i
].abi_type
;
1134 if (i
== ARRAY_SIZE (arm_all_abis
))
1135 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1138 arm_abi
= ARM_DEFAULT_ABI
;
1140 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1141 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1143 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1144 error ("iwmmxt abi requires an iwmmxt capable cpu");
1146 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1147 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1149 if (streq (target_fpe_name
, "2"))
1150 target_fpu_name
= "fpe2";
1151 else if (streq (target_fpe_name
, "3"))
1152 target_fpu_name
= "fpe3";
1154 error ("invalid floating point emulation option: -mfpe=%s",
1157 if (target_fpu_name
!= NULL
)
1159 /* The user specified a FPU. */
1160 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1162 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1164 arm_fpu_arch
= all_fpus
[i
].fpu
;
1165 arm_fpu_tune
= arm_fpu_arch
;
1166 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1170 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1171 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1175 #ifdef FPUTYPE_DEFAULT
1176 /* Use the default if it is specified for this platform. */
1177 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1178 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1180 /* Pick one based on CPU type. */
1181 /* ??? Some targets assume FPA is the default.
1182 if ((insn_flags & FL_VFP) != 0)
1183 arm_fpu_arch = FPUTYPE_VFP;
1186 if (arm_arch_cirrus
)
1187 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1189 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1191 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1192 arm_fpu_tune
= FPUTYPE_FPA
;
1194 arm_fpu_tune
= arm_fpu_arch
;
1195 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1196 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1199 if (target_float_abi_name
!= NULL
)
1201 /* The user specified a FP ABI. */
1202 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1204 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1206 arm_float_abi
= all_float_abis
[i
].abi_type
;
1210 if (i
== ARRAY_SIZE (all_float_abis
))
1211 error ("invalid floating point abi: -mfloat-abi=%s",
1212 target_float_abi_name
);
1215 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1217 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1218 sorry ("-mfloat-abi=hard and VFP");
1220 /* If soft-float is specified then don't use FPU. */
1221 if (TARGET_SOFT_FLOAT
)
1222 arm_fpu_arch
= FPUTYPE_NONE
;
1224 /* For arm2/3 there is no need to do any scheduling if there is only
1225 a floating point emulator, or we are doing software floating-point. */
1226 if ((TARGET_SOFT_FLOAT
1227 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1228 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1229 && (tune_flags
& FL_MODE32
) == 0)
1230 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1232 if (target_thread_switch
)
1234 if (strcmp (target_thread_switch
, "soft") == 0)
1235 target_thread_pointer
= TP_SOFT
;
1236 else if (strcmp (target_thread_switch
, "auto") == 0)
1237 target_thread_pointer
= TP_AUTO
;
1238 else if (strcmp (target_thread_switch
, "cp15") == 0)
1239 target_thread_pointer
= TP_CP15
;
1241 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1244 /* Use the cp15 method if it is available. */
1245 if (target_thread_pointer
== TP_AUTO
)
1247 if (arm_arch6k
&& !TARGET_THUMB
)
1248 target_thread_pointer
= TP_CP15
;
1250 target_thread_pointer
= TP_SOFT
;
1253 if (TARGET_HARD_TP
&& TARGET_THUMB
)
1254 error ("can not use -mtp=cp15 with -mthumb");
1256 /* Override the default structure alignment for AAPCS ABI. */
1257 if (TARGET_AAPCS_BASED
)
1258 arm_structure_size_boundary
= 8;
1260 if (structure_size_string
!= NULL
)
1262 int size
= strtol (structure_size_string
, NULL
, 0);
1264 if (size
== 8 || size
== 32
1265 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1266 arm_structure_size_boundary
= size
;
1268 warning (0, "structure size boundary can only be set to %s",
1269 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1272 if (arm_pic_register_string
!= NULL
)
1274 int pic_register
= decode_reg_name (arm_pic_register_string
);
1277 warning (0, "-mpic-register= is useless without -fpic");
1279 /* Prevent the user from choosing an obviously stupid PIC register. */
1280 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1281 || pic_register
== HARD_FRAME_POINTER_REGNUM
1282 || pic_register
== STACK_POINTER_REGNUM
1283 || pic_register
>= PC_REGNUM
)
1284 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1286 arm_pic_register
= pic_register
;
1289 if (TARGET_THUMB
&& flag_schedule_insns
)
1291 /* Don't warn since it's on by default in -O2. */
1292 flag_schedule_insns
= 0;
1297 arm_constant_limit
= 1;
1299 /* If optimizing for size, bump the number of instructions that we
1300 are prepared to conditionally execute (even on a StrongARM). */
1301 max_insns_skipped
= 6;
1305 /* For processors with load scheduling, it never costs more than
1306 2 cycles to load a constant, and the load scheduler may well
1307 reduce that to 1. */
1309 arm_constant_limit
= 1;
1311 /* On XScale the longer latency of a load makes it more difficult
1312 to achieve a good schedule, so it's faster to synthesize
1313 constants that can be done in two insns. */
1314 if (arm_tune_xscale
)
1315 arm_constant_limit
= 2;
1317 /* StrongARM has early execution of branches, so a sequence
1318 that is worth skipping is shorter. */
1319 if (arm_tune_strongarm
)
1320 max_insns_skipped
= 3;
1323 /* Register global variables with the garbage collector. */
1324 arm_add_gc_roots ();
1328 arm_add_gc_roots (void)
1330 gcc_obstack_init(&minipool_obstack
);
1331 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1334 /* A table of known ARM exception types.
1335 For use with the interrupt function attribute. */
1339 const char *const arg
;
1340 const unsigned long return_value
;
1344 static const isr_attribute_arg isr_attribute_args
[] =
1346 { "IRQ", ARM_FT_ISR
},
1347 { "irq", ARM_FT_ISR
},
1348 { "FIQ", ARM_FT_FIQ
},
1349 { "fiq", ARM_FT_FIQ
},
1350 { "ABORT", ARM_FT_ISR
},
1351 { "abort", ARM_FT_ISR
},
1352 { "ABORT", ARM_FT_ISR
},
1353 { "abort", ARM_FT_ISR
},
1354 { "UNDEF", ARM_FT_EXCEPTION
},
1355 { "undef", ARM_FT_EXCEPTION
},
1356 { "SWI", ARM_FT_EXCEPTION
},
1357 { "swi", ARM_FT_EXCEPTION
},
1358 { NULL
, ARM_FT_NORMAL
}
1361 /* Returns the (interrupt) function type of the current
1362 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1364 static unsigned long
1365 arm_isr_value (tree argument
)
1367 const isr_attribute_arg
* ptr
;
1370 /* No argument - default to IRQ. */
1371 if (argument
== NULL_TREE
)
1374 /* Get the value of the argument. */
1375 if (TREE_VALUE (argument
) == NULL_TREE
1376 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1377 return ARM_FT_UNKNOWN
;
1379 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1381 /* Check it against the list of known arguments. */
1382 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1383 if (streq (arg
, ptr
->arg
))
1384 return ptr
->return_value
;
1386 /* An unrecognized interrupt type. */
1387 return ARM_FT_UNKNOWN
;
1390 /* Computes the type of the current function. */
1392 static unsigned long
1393 arm_compute_func_type (void)
1395 unsigned long type
= ARM_FT_UNKNOWN
;
1399 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1401 /* Decide if the current function is volatile. Such functions
1402 never return, and many memory cycles can be saved by not storing
1403 register values that will never be needed again. This optimization
1404 was added to speed up context switching in a kernel application. */
1406 && TREE_NOTHROW (current_function_decl
)
1407 && TREE_THIS_VOLATILE (current_function_decl
))
1408 type
|= ARM_FT_VOLATILE
;
1410 if (cfun
->static_chain_decl
!= NULL
)
1411 type
|= ARM_FT_NESTED
;
1413 attr
= DECL_ATTRIBUTES (current_function_decl
);
1415 a
= lookup_attribute ("naked", attr
);
1417 type
|= ARM_FT_NAKED
;
1419 a
= lookup_attribute ("isr", attr
);
1421 a
= lookup_attribute ("interrupt", attr
);
1424 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1426 type
|= arm_isr_value (TREE_VALUE (a
));
1431 /* Returns the type of the current function. */
1434 arm_current_func_type (void)
1436 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1437 cfun
->machine
->func_type
= arm_compute_func_type ();
1439 return cfun
->machine
->func_type
;
1442 /* Return 1 if it is possible to return using a single instruction.
1443 If SIBLING is non-null, this is a test for a return before a sibling
1444 call. SIBLING is the call insn, so we can examine its register usage. */
1447 use_return_insn (int iscond
, rtx sibling
)
1450 unsigned int func_type
;
1451 unsigned long saved_int_regs
;
1452 unsigned HOST_WIDE_INT stack_adjust
;
1453 arm_stack_offsets
*offsets
;
1455 /* Never use a return instruction before reload has run. */
1456 if (!reload_completed
)
1459 func_type
= arm_current_func_type ();
1461 /* Naked functions and volatile functions need special
1463 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1466 /* So do interrupt functions that use the frame pointer. */
1467 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1470 offsets
= arm_get_frame_offsets ();
1471 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1473 /* As do variadic functions. */
1474 if (current_function_pretend_args_size
1475 || cfun
->machine
->uses_anonymous_args
1476 /* Or if the function calls __builtin_eh_return () */
1477 || current_function_calls_eh_return
1478 /* Or if the function calls alloca */
1479 || current_function_calls_alloca
1480 /* Or if there is a stack adjustment. However, if the stack pointer
1481 is saved on the stack, we can use a pre-incrementing stack load. */
1482 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1485 saved_int_regs
= arm_compute_save_reg_mask ();
1487 /* Unfortunately, the insn
1489 ldmib sp, {..., sp, ...}
1491 triggers a bug on most SA-110 based devices, such that the stack
1492 pointer won't be correctly restored if the instruction takes a
1493 page fault. We work around this problem by popping r3 along with
1494 the other registers, since that is never slower than executing
1495 another instruction.
1497 We test for !arm_arch5 here, because code for any architecture
1498 less than this could potentially be run on one of the buggy
1500 if (stack_adjust
== 4 && !arm_arch5
)
1502 /* Validate that r3 is a call-clobbered register (always true in
1503 the default abi) ... */
1504 if (!call_used_regs
[3])
1507 /* ... that it isn't being used for a return value ... */
1508 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1511 /* ... or for a tail-call argument ... */
1514 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1516 if (find_regno_fusage (sibling
, USE
, 3))
1520 /* ... and that there are no call-saved registers in r0-r2
1521 (always true in the default ABI). */
1522 if (saved_int_regs
& 0x7)
1526 /* Can't be done if interworking with Thumb, and any registers have been
1528 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1531 /* On StrongARM, conditional returns are expensive if they aren't
1532 taken and multiple registers have been stacked. */
1533 if (iscond
&& arm_tune_strongarm
)
1535 /* Conditional return when just the LR is stored is a simple
1536 conditional-load instruction, that's not expensive. */
1537 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1540 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1544 /* If there are saved registers but the LR isn't saved, then we need
1545 two instructions for the return. */
1546 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1549 /* Can't be done if any of the FPA regs are pushed,
1550 since this also requires an insn. */
1551 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1552 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1553 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1556 /* Likewise VFP regs. */
1557 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1558 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1559 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1562 if (TARGET_REALLY_IWMMXT
)
1563 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1564 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1570 /* Return TRUE if int I is a valid immediate ARM constant. */
1573 const_ok_for_arm (HOST_WIDE_INT i
)
1577 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1578 be all zero, or all one. */
1579 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1580 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1581 != ((~(unsigned HOST_WIDE_INT
) 0)
1582 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1585 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1587 /* Fast return for 0 and small values. We must do this for zero, since
1588 the code below can't handle that one case. */
1589 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1592 /* Get the number of trailing zeros, rounded down to the nearest even
1594 lowbit
= (ffs ((int) i
) - 1) & ~1;
1596 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1598 else if (lowbit
<= 4
1599 && ((i
& ~0xc000003f) == 0
1600 || (i
& ~0xf000000f) == 0
1601 || (i
& ~0xfc000003) == 0))
1607 /* Return true if I is a valid constant for the operation CODE. */
1609 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1611 if (const_ok_for_arm (i
))
1617 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1619 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1625 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1632 /* Emit a sequence of insns to handle a large constant.
1633 CODE is the code of the operation required, it can be any of SET, PLUS,
1634 IOR, AND, XOR, MINUS;
1635 MODE is the mode in which the operation is being performed;
1636 VAL is the integer to operate on;
1637 SOURCE is the other operand (a register, or a null-pointer for SET);
1638 SUBTARGETS means it is safe to create scratch registers if that will
1639 either produce a simpler sequence, or we will want to cse the values.
1640 Return value is the number of insns emitted. */
1643 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1644 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1648 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1649 cond
= COND_EXEC_TEST (PATTERN (insn
));
1653 if (subtargets
|| code
== SET
1654 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1655 && REGNO (target
) != REGNO (source
)))
1657 /* After arm_reorg has been called, we can't fix up expensive
1658 constants by pushing them into memory so we must synthesize
1659 them in-line, regardless of the cost. This is only likely to
1660 be more costly on chips that have load delay slots and we are
1661 compiling without running the scheduler (so no splitting
1662 occurred before the final instruction emission).
1664 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1666 if (!after_arm_reorg
1668 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1670 > arm_constant_limit
+ (code
!= SET
)))
1674 /* Currently SET is the only monadic value for CODE, all
1675 the rest are diadic. */
1676 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1681 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1683 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1684 /* For MINUS, the value is subtracted from, since we never
1685 have subtraction of a constant. */
1687 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1688 gen_rtx_MINUS (mode
, temp
, source
)));
1690 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1691 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1697 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1702 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1704 HOST_WIDE_INT temp1
;
1712 if (remainder
& (3 << (i
- 2)))
1717 temp1
= remainder
& ((0x0ff << end
)
1718 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1719 remainder
&= ~temp1
;
1724 } while (remainder
);
1728 /* Emit an instruction with the indicated PATTERN. If COND is
1729 non-NULL, conditionalize the execution of the instruction on COND
1733 emit_constant_insn (rtx cond
, rtx pattern
)
1736 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1737 emit_insn (pattern
);
1740 /* As above, but extra parameter GENERATE which, if clear, suppresses
1744 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1745 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1750 int can_negate_initial
= 0;
1753 int num_bits_set
= 0;
1754 int set_sign_bit_copies
= 0;
1755 int clear_sign_bit_copies
= 0;
1756 int clear_zero_bit_copies
= 0;
1757 int set_zero_bit_copies
= 0;
1759 unsigned HOST_WIDE_INT temp1
, temp2
;
1760 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1762 /* Find out which operations are safe for a given CODE. Also do a quick
1763 check for degenerate cases; these can occur when DImode operations
1775 can_negate_initial
= 1;
1779 if (remainder
== 0xffffffff)
1782 emit_constant_insn (cond
,
1783 gen_rtx_SET (VOIDmode
, target
,
1784 GEN_INT (ARM_SIGN_EXTEND (val
))));
1789 if (reload_completed
&& rtx_equal_p (target
, source
))
1792 emit_constant_insn (cond
,
1793 gen_rtx_SET (VOIDmode
, target
, source
));
1802 emit_constant_insn (cond
,
1803 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1806 if (remainder
== 0xffffffff)
1808 if (reload_completed
&& rtx_equal_p (target
, source
))
1811 emit_constant_insn (cond
,
1812 gen_rtx_SET (VOIDmode
, target
, source
));
1821 if (reload_completed
&& rtx_equal_p (target
, source
))
1824 emit_constant_insn (cond
,
1825 gen_rtx_SET (VOIDmode
, target
, source
));
1829 /* We don't know how to handle other cases yet. */
1830 gcc_assert (remainder
== 0xffffffff);
1833 emit_constant_insn (cond
,
1834 gen_rtx_SET (VOIDmode
, target
,
1835 gen_rtx_NOT (mode
, source
)));
1839 /* We treat MINUS as (val - source), since (source - val) is always
1840 passed as (source + (-val)). */
1844 emit_constant_insn (cond
,
1845 gen_rtx_SET (VOIDmode
, target
,
1846 gen_rtx_NEG (mode
, source
)));
1849 if (const_ok_for_arm (val
))
1852 emit_constant_insn (cond
,
1853 gen_rtx_SET (VOIDmode
, target
,
1854 gen_rtx_MINUS (mode
, GEN_INT (val
),
1866 /* If we can do it in one insn get out quickly. */
1867 if (const_ok_for_arm (val
)
1868 || (can_negate_initial
&& const_ok_for_arm (-val
))
1869 || (can_invert
&& const_ok_for_arm (~val
)))
1872 emit_constant_insn (cond
,
1873 gen_rtx_SET (VOIDmode
, target
,
1875 ? gen_rtx_fmt_ee (code
, mode
, source
,
1881 /* Calculate a few attributes that may be useful for specific
1883 for (i
= 31; i
>= 0; i
--)
1885 if ((remainder
& (1 << i
)) == 0)
1886 clear_sign_bit_copies
++;
1891 for (i
= 31; i
>= 0; i
--)
1893 if ((remainder
& (1 << i
)) != 0)
1894 set_sign_bit_copies
++;
1899 for (i
= 0; i
<= 31; i
++)
1901 if ((remainder
& (1 << i
)) == 0)
1902 clear_zero_bit_copies
++;
1907 for (i
= 0; i
<= 31; i
++)
1909 if ((remainder
& (1 << i
)) != 0)
1910 set_zero_bit_copies
++;
1918 /* See if we can do this by sign_extending a constant that is known
1919 to be negative. This is a good, way of doing it, since the shift
1920 may well merge into a subsequent insn. */
1921 if (set_sign_bit_copies
> 1)
1923 if (const_ok_for_arm
1924 (temp1
= ARM_SIGN_EXTEND (remainder
1925 << (set_sign_bit_copies
- 1))))
1929 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1930 emit_constant_insn (cond
,
1931 gen_rtx_SET (VOIDmode
, new_src
,
1933 emit_constant_insn (cond
,
1934 gen_ashrsi3 (target
, new_src
,
1935 GEN_INT (set_sign_bit_copies
- 1)));
1939 /* For an inverted constant, we will need to set the low bits,
1940 these will be shifted out of harm's way. */
1941 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1942 if (const_ok_for_arm (~temp1
))
1946 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1947 emit_constant_insn (cond
,
1948 gen_rtx_SET (VOIDmode
, new_src
,
1950 emit_constant_insn (cond
,
1951 gen_ashrsi3 (target
, new_src
,
1952 GEN_INT (set_sign_bit_copies
- 1)));
1958 /* See if we can calculate the value as the difference between two
1959 valid immediates. */
1960 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1962 int topshift
= clear_sign_bit_copies
& ~1;
1964 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1965 & (0xff000000 >> topshift
));
1967 /* If temp1 is zero, then that means the 9 most significant
1968 bits of remainder were 1 and we've caused it to overflow.
1969 When topshift is 0 we don't need to do anything since we
1970 can borrow from 'bit 32'. */
1971 if (temp1
== 0 && topshift
!= 0)
1972 temp1
= 0x80000000 >> (topshift
- 1);
1974 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1976 if (const_ok_for_arm (temp2
))
1980 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1981 emit_constant_insn (cond
,
1982 gen_rtx_SET (VOIDmode
, new_src
,
1984 emit_constant_insn (cond
,
1985 gen_addsi3 (target
, new_src
,
1993 /* See if we can generate this by setting the bottom (or the top)
1994 16 bits, and then shifting these into the other half of the
1995 word. We only look for the simplest cases, to do more would cost
1996 too much. Be careful, however, not to generate this when the
1997 alternative would take fewer insns. */
1998 if (val
& 0xffff0000)
2000 temp1
= remainder
& 0xffff0000;
2001 temp2
= remainder
& 0x0000ffff;
2003 /* Overlaps outside this range are best done using other methods. */
2004 for (i
= 9; i
< 24; i
++)
2006 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2007 && !const_ok_for_arm (temp2
))
2009 rtx new_src
= (subtargets
2010 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2012 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2013 source
, subtargets
, generate
);
2021 gen_rtx_ASHIFT (mode
, source
,
2028 /* Don't duplicate cases already considered. */
2029 for (i
= 17; i
< 24; i
++)
2031 if (((temp1
| (temp1
>> i
)) == remainder
)
2032 && !const_ok_for_arm (temp1
))
2034 rtx new_src
= (subtargets
2035 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2037 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2038 source
, subtargets
, generate
);
2043 gen_rtx_SET (VOIDmode
, target
,
2046 gen_rtx_LSHIFTRT (mode
, source
,
2057 /* If we have IOR or XOR, and the constant can be loaded in a
2058 single instruction, and we can find a temporary to put it in,
2059 then this can be done in two instructions instead of 3-4. */
2061 /* TARGET can't be NULL if SUBTARGETS is 0 */
2062 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2064 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2068 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2070 emit_constant_insn (cond
,
2071 gen_rtx_SET (VOIDmode
, sub
,
2073 emit_constant_insn (cond
,
2074 gen_rtx_SET (VOIDmode
, target
,
2075 gen_rtx_fmt_ee (code
, mode
,
2085 if (set_sign_bit_copies
> 8
2086 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2090 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2091 rtx shift
= GEN_INT (set_sign_bit_copies
);
2095 gen_rtx_SET (VOIDmode
, sub
,
2097 gen_rtx_ASHIFT (mode
,
2102 gen_rtx_SET (VOIDmode
, target
,
2104 gen_rtx_LSHIFTRT (mode
, sub
,
2110 if (set_zero_bit_copies
> 8
2111 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2115 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2116 rtx shift
= GEN_INT (set_zero_bit_copies
);
2120 gen_rtx_SET (VOIDmode
, sub
,
2122 gen_rtx_LSHIFTRT (mode
,
2127 gen_rtx_SET (VOIDmode
, target
,
2129 gen_rtx_ASHIFT (mode
, sub
,
2135 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2139 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2140 emit_constant_insn (cond
,
2141 gen_rtx_SET (VOIDmode
, sub
,
2142 gen_rtx_NOT (mode
, source
)));
2145 sub
= gen_reg_rtx (mode
);
2146 emit_constant_insn (cond
,
2147 gen_rtx_SET (VOIDmode
, sub
,
2148 gen_rtx_AND (mode
, source
,
2150 emit_constant_insn (cond
,
2151 gen_rtx_SET (VOIDmode
, target
,
2152 gen_rtx_NOT (mode
, sub
)));
2159 /* See if two shifts will do 2 or more insn's worth of work. */
2160 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2162 HOST_WIDE_INT shift_mask
= ((0xffffffff
2163 << (32 - clear_sign_bit_copies
))
2166 if ((remainder
| shift_mask
) != 0xffffffff)
2170 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2171 insns
= arm_gen_constant (AND
, mode
, cond
,
2172 remainder
| shift_mask
,
2173 new_src
, source
, subtargets
, 1);
2178 rtx targ
= subtargets
? NULL_RTX
: target
;
2179 insns
= arm_gen_constant (AND
, mode
, cond
,
2180 remainder
| shift_mask
,
2181 targ
, source
, subtargets
, 0);
2187 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2188 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2190 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2191 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2197 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2199 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2201 if ((remainder
| shift_mask
) != 0xffffffff)
2205 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2207 insns
= arm_gen_constant (AND
, mode
, cond
,
2208 remainder
| shift_mask
,
2209 new_src
, source
, subtargets
, 1);
2214 rtx targ
= subtargets
? NULL_RTX
: target
;
2216 insns
= arm_gen_constant (AND
, mode
, cond
,
2217 remainder
| shift_mask
,
2218 targ
, source
, subtargets
, 0);
2224 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2225 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2227 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2228 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2240 for (i
= 0; i
< 32; i
++)
2241 if (remainder
& (1 << i
))
2244 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2245 remainder
= (~remainder
) & 0xffffffff;
2246 else if (code
== PLUS
&& num_bits_set
> 16)
2247 remainder
= (-remainder
) & 0xffffffff;
2254 /* Now try and find a way of doing the job in either two or three
2256 We start by looking for the largest block of zeros that are aligned on
2257 a 2-bit boundary, we then fill up the temps, wrapping around to the
2258 top of the word when we drop off the bottom.
2259 In the worst case this code should produce no more than four insns. */
2262 int best_consecutive_zeros
= 0;
2264 for (i
= 0; i
< 32; i
+= 2)
2266 int consecutive_zeros
= 0;
2268 if (!(remainder
& (3 << i
)))
2270 while ((i
< 32) && !(remainder
& (3 << i
)))
2272 consecutive_zeros
+= 2;
2275 if (consecutive_zeros
> best_consecutive_zeros
)
2277 best_consecutive_zeros
= consecutive_zeros
;
2278 best_start
= i
- consecutive_zeros
;
2284 /* So long as it won't require any more insns to do so, it's
2285 desirable to emit a small constant (in bits 0...9) in the last
2286 insn. This way there is more chance that it can be combined with
2287 a later addressing insn to form a pre-indexed load or store
2288 operation. Consider:
2290 *((volatile int *)0xe0000100) = 1;
2291 *((volatile int *)0xe0000110) = 2;
2293 We want this to wind up as:
2297 str rB, [rA, #0x100]
2299 str rB, [rA, #0x110]
2301 rather than having to synthesize both large constants from scratch.
2303 Therefore, we calculate how many insns would be required to emit
2304 the constant starting from `best_start', and also starting from
2305 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2306 yield a shorter sequence, we may as well use zero. */
2308 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2309 && (count_insns_for_constant (remainder
, 0) <=
2310 count_insns_for_constant (remainder
, best_start
)))
2313 /* Now start emitting the insns. */
2321 if (remainder
& (3 << (i
- 2)))
2326 temp1
= remainder
& ((0x0ff << end
)
2327 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2328 remainder
&= ~temp1
;
2332 rtx new_src
, temp1_rtx
;
2334 if (code
== SET
|| code
== MINUS
)
2336 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2337 if (can_invert
&& code
!= MINUS
)
2342 if (remainder
&& subtargets
)
2343 new_src
= gen_reg_rtx (mode
);
2348 else if (can_negate
)
2352 temp1
= trunc_int_for_mode (temp1
, mode
);
2353 temp1_rtx
= GEN_INT (temp1
);
2357 else if (code
== MINUS
)
2358 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2360 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2362 emit_constant_insn (cond
,
2363 gen_rtx_SET (VOIDmode
, new_src
,
2373 else if (code
== MINUS
)
2387 /* Canonicalize a comparison so that we are more likely to recognize it.
2388 This can be done for a few constant compares, where we can make the
2389 immediate value easier to load. */
2392 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2395 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2396 unsigned HOST_WIDE_INT maxval
;
2397 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2408 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2410 *op1
= GEN_INT (i
+ 1);
2411 return code
== GT
? GE
: LT
;
2418 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2420 *op1
= GEN_INT (i
- 1);
2421 return code
== GE
? GT
: LE
;
2427 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2428 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2430 *op1
= GEN_INT (i
+ 1);
2431 return code
== GTU
? GEU
: LTU
;
2438 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2440 *op1
= GEN_INT (i
- 1);
2441 return code
== GEU
? GTU
: LEU
;
2453 /* Define how to find the value returned by a function. */
2456 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2458 enum machine_mode mode
;
2459 int unsignedp ATTRIBUTE_UNUSED
;
2460 rtx r ATTRIBUTE_UNUSED
;
2462 mode
= TYPE_MODE (type
);
2463 /* Promote integer types. */
2464 if (INTEGRAL_TYPE_P (type
))
2465 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2467 /* Promotes small structs returned in a register to full-word size
2468 for big-endian AAPCS. */
2469 if (arm_return_in_msb (type
))
2471 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2472 if (size
% UNITS_PER_WORD
!= 0)
2474 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2475 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2479 return LIBCALL_VALUE(mode
);
2482 /* Determine the amount of memory needed to store the possible return
2483 registers of an untyped call. */
2485 arm_apply_result_size (void)
2491 if (TARGET_HARD_FLOAT_ABI
)
2495 if (TARGET_MAVERICK
)
2498 if (TARGET_IWMMXT_ABI
)
2505 /* Decide whether a type should be returned in memory (true)
2506 or in a register (false). This is called by the macro
2507 RETURN_IN_MEMORY. */
2509 arm_return_in_memory (tree type
)
2513 if (!AGGREGATE_TYPE_P (type
) &&
2514 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2515 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2516 /* All simple types are returned in registers.
2517 For AAPCS, complex types are treated the same as aggregates. */
2520 size
= int_size_in_bytes (type
);
2522 if (arm_abi
!= ARM_ABI_APCS
)
2524 /* ATPCS and later return aggregate types in memory only if they are
2525 larger than a word (or are variable size). */
2526 return (size
< 0 || size
> UNITS_PER_WORD
);
2529 /* To maximize backwards compatibility with previous versions of gcc,
2530 return vectors up to 4 words in registers. */
2531 if (TREE_CODE (type
) == VECTOR_TYPE
)
2532 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2534 /* For the arm-wince targets we choose to be compatible with Microsoft's
2535 ARM and Thumb compilers, which always return aggregates in memory. */
2537 /* All structures/unions bigger than one word are returned in memory.
2538 Also catch the case where int_size_in_bytes returns -1. In this case
2539 the aggregate is either huge or of variable size, and in either case
2540 we will want to return it via memory and not in a register. */
2541 if (size
< 0 || size
> UNITS_PER_WORD
)
2544 if (TREE_CODE (type
) == RECORD_TYPE
)
2548 /* For a struct the APCS says that we only return in a register
2549 if the type is 'integer like' and every addressable element
2550 has an offset of zero. For practical purposes this means
2551 that the structure can have at most one non bit-field element
2552 and that this element must be the first one in the structure. */
2554 /* Find the first field, ignoring non FIELD_DECL things which will
2555 have been created by C++. */
2556 for (field
= TYPE_FIELDS (type
);
2557 field
&& TREE_CODE (field
) != FIELD_DECL
;
2558 field
= TREE_CHAIN (field
))
2562 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2564 /* Check that the first field is valid for returning in a register. */
2566 /* ... Floats are not allowed */
2567 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2570 /* ... Aggregates that are not themselves valid for returning in
2571 a register are not allowed. */
2572 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2575 /* Now check the remaining fields, if any. Only bitfields are allowed,
2576 since they are not addressable. */
2577 for (field
= TREE_CHAIN (field
);
2579 field
= TREE_CHAIN (field
))
2581 if (TREE_CODE (field
) != FIELD_DECL
)
2584 if (!DECL_BIT_FIELD_TYPE (field
))
2591 if (TREE_CODE (type
) == UNION_TYPE
)
2595 /* Unions can be returned in registers if every element is
2596 integral, or can be returned in an integer register. */
2597 for (field
= TYPE_FIELDS (type
);
2599 field
= TREE_CHAIN (field
))
2601 if (TREE_CODE (field
) != FIELD_DECL
)
2604 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2607 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2613 #endif /* not ARM_WINCE */
2615 /* Return all other types in memory. */
2619 /* Indicate whether or not words of a double are in big-endian order. */
2622 arm_float_words_big_endian (void)
2624 if (TARGET_MAVERICK
)
2627 /* For FPA, float words are always big-endian. For VFP, floats words
2628 follow the memory system mode. */
2636 return (TARGET_BIG_END
? 1 : 0);
2641 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2642 for a call to a function whose data type is FNTYPE.
2643 For a library call, FNTYPE is NULL. */
2645 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2646 rtx libname ATTRIBUTE_UNUSED
,
2647 tree fndecl ATTRIBUTE_UNUSED
)
2649 /* On the ARM, the offset starts at 0. */
2650 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2651 pcum
->iwmmxt_nregs
= 0;
2652 pcum
->can_split
= true;
2654 pcum
->call_cookie
= CALL_NORMAL
;
2656 if (TARGET_LONG_CALLS
)
2657 pcum
->call_cookie
= CALL_LONG
;
2659 /* Check for long call/short call attributes. The attributes
2660 override any command line option. */
2663 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2664 pcum
->call_cookie
= CALL_SHORT
;
2665 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2666 pcum
->call_cookie
= CALL_LONG
;
2669 /* Varargs vectors are treated the same as long long.
2670 named_count avoids having to change the way arm handles 'named' */
2671 pcum
->named_count
= 0;
2674 if (TARGET_REALLY_IWMMXT
&& fntype
)
2678 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2680 fn_arg
= TREE_CHAIN (fn_arg
))
2681 pcum
->named_count
+= 1;
2683 if (! pcum
->named_count
)
2684 pcum
->named_count
= INT_MAX
;
2689 /* Return true if mode/type need doubleword alignment. */
2691 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2693 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2694 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2698 /* Determine where to put an argument to a function.
2699 Value is zero to push the argument on the stack,
2700 or a hard register in which to store the argument.
2702 MODE is the argument's machine mode.
2703 TYPE is the data type of the argument (as a tree).
2704 This is null for libcalls where that information may
2706 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2707 the preceding args and about the function being called.
2708 NAMED is nonzero if this argument is a named parameter
2709 (otherwise it is an extra parameter matching an ellipsis). */
2712 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2713 tree type
, int named
)
2717 /* Varargs vectors are treated the same as long long.
2718 named_count avoids having to change the way arm handles 'named' */
2719 if (TARGET_IWMMXT_ABI
2720 && arm_vector_mode_supported_p (mode
)
2721 && pcum
->named_count
> pcum
->nargs
+ 1)
2723 if (pcum
->iwmmxt_nregs
<= 9)
2724 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2727 pcum
->can_split
= false;
2732 /* Put doubleword aligned quantities in even register pairs. */
2734 && ARM_DOUBLEWORD_ALIGN
2735 && arm_needs_doubleword_align (mode
, type
))
2738 if (mode
== VOIDmode
)
2739 /* Compute operand 2 of the call insn. */
2740 return GEN_INT (pcum
->call_cookie
);
2742 /* Only allow splitting an arg between regs and memory if all preceding
2743 args were allocated to regs. For args passed by reference we only count
2744 the reference pointer. */
2745 if (pcum
->can_split
)
2748 nregs
= ARM_NUM_REGS2 (mode
, type
);
2750 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2753 return gen_rtx_REG (mode
, pcum
->nregs
);
2757 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2758 tree type
, bool named ATTRIBUTE_UNUSED
)
2760 int nregs
= pcum
->nregs
;
2762 if (arm_vector_mode_supported_p (mode
))
2765 if (NUM_ARG_REGS
> nregs
2766 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2768 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2773 /* Variable sized types are passed by reference. This is a GCC
2774 extension to the ARM ABI. */
2777 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2778 enum machine_mode mode ATTRIBUTE_UNUSED
,
2779 tree type
, bool named ATTRIBUTE_UNUSED
)
2781 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2784 /* Encode the current state of the #pragma [no_]long_calls. */
2787 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2788 LONG
, /* #pragma long_calls is in effect. */
2789 SHORT
/* #pragma no_long_calls is in effect. */
2792 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2795 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2797 arm_pragma_long_calls
= LONG
;
2801 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2803 arm_pragma_long_calls
= SHORT
;
2807 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2809 arm_pragma_long_calls
= OFF
;
2812 /* Table of machine attributes. */
2813 const struct attribute_spec arm_attribute_table
[] =
2815 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2816 /* Function calls made to this symbol must be done indirectly, because
2817 it may lie outside of the 26 bit addressing range of a normal function
2819 { "long_call", 0, 0, false, true, true, NULL
},
2820 /* Whereas these functions are always known to reside within the 26 bit
2821 addressing range. */
2822 { "short_call", 0, 0, false, true, true, NULL
},
2823 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2824 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2825 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2826 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2828 /* ARM/PE has three new attributes:
2830 dllexport - for exporting a function/variable that will live in a dll
2831 dllimport - for importing a function/variable from a dll
2833 Microsoft allows multiple declspecs in one __declspec, separating
2834 them with spaces. We do NOT support this. Instead, use __declspec
2837 { "dllimport", 0, 0, true, false, false, NULL
},
2838 { "dllexport", 0, 0, true, false, false, NULL
},
2839 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2840 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2841 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2842 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2843 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2845 { NULL
, 0, 0, false, false, false, NULL
}
2848 /* Handle an attribute requiring a FUNCTION_DECL;
2849 arguments as in struct attribute_spec.handler. */
2851 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2852 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2854 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2856 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2857 IDENTIFIER_POINTER (name
));
2858 *no_add_attrs
= true;
2864 /* Handle an "interrupt" or "isr" attribute;
2865 arguments as in struct attribute_spec.handler. */
2867 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2872 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2874 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2875 IDENTIFIER_POINTER (name
));
2876 *no_add_attrs
= true;
2878 /* FIXME: the argument if any is checked for type attributes;
2879 should it be checked for decl ones? */
2883 if (TREE_CODE (*node
) == FUNCTION_TYPE
2884 || TREE_CODE (*node
) == METHOD_TYPE
)
2886 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2888 warning (OPT_Wattributes
, "%qs attribute ignored",
2889 IDENTIFIER_POINTER (name
));
2890 *no_add_attrs
= true;
2893 else if (TREE_CODE (*node
) == POINTER_TYPE
2894 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2895 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2896 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2898 *node
= build_variant_type_copy (*node
);
2899 TREE_TYPE (*node
) = build_type_attribute_variant
2901 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2902 *no_add_attrs
= true;
2906 /* Possibly pass this attribute on from the type to a decl. */
2907 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2908 | (int) ATTR_FLAG_FUNCTION_NEXT
2909 | (int) ATTR_FLAG_ARRAY_NEXT
))
2911 *no_add_attrs
= true;
2912 return tree_cons (name
, args
, NULL_TREE
);
2916 warning (OPT_Wattributes
, "%qs attribute ignored",
2917 IDENTIFIER_POINTER (name
));
2925 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2926 /* Handle the "notshared" attribute. This attribute is another way of
2927 requesting hidden visibility. ARM's compiler supports
2928 "__declspec(notshared)"; we support the same thing via an
2932 arm_handle_notshared_attribute (tree
*node
,
2933 tree name ATTRIBUTE_UNUSED
,
2934 tree args ATTRIBUTE_UNUSED
,
2935 int flags ATTRIBUTE_UNUSED
,
2938 tree decl
= TYPE_NAME (*node
);
2942 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2943 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2944 *no_add_attrs
= false;
2950 /* Return 0 if the attributes for two types are incompatible, 1 if they
2951 are compatible, and 2 if they are nearly compatible (which causes a
2952 warning to be generated). */
2954 arm_comp_type_attributes (tree type1
, tree type2
)
2958 /* Check for mismatch of non-default calling convention. */
2959 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2962 /* Check for mismatched call attributes. */
2963 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2964 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2965 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2966 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2968 /* Only bother to check if an attribute is defined. */
2969 if (l1
| l2
| s1
| s2
)
2971 /* If one type has an attribute, the other must have the same attribute. */
2972 if ((l1
!= l2
) || (s1
!= s2
))
2975 /* Disallow mixed attributes. */
2976 if ((l1
& s2
) || (l2
& s1
))
2980 /* Check for mismatched ISR attribute. */
2981 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2983 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2984 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2986 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2993 /* Encode long_call or short_call attribute by prefixing
2994 symbol name in DECL with a special character FLAG. */
2996 arm_encode_call_attribute (tree decl
, int flag
)
2998 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2999 int len
= strlen (str
);
3002 /* Do not allow weak functions to be treated as short call. */
3003 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3006 newstr
= alloca (len
+ 2);
3008 strcpy (newstr
+ 1, str
);
3010 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3011 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3014 /* Assigns default attributes to newly defined type. This is used to
3015 set short_call/long_call attributes for function types of
3016 functions defined inside corresponding #pragma scopes. */
3018 arm_set_default_type_attributes (tree type
)
3020 /* Add __attribute__ ((long_call)) to all functions, when
3021 inside #pragma long_calls or __attribute__ ((short_call)),
3022 when inside #pragma no_long_calls. */
3023 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3025 tree type_attr_list
, attr_name
;
3026 type_attr_list
= TYPE_ATTRIBUTES (type
);
3028 if (arm_pragma_long_calls
== LONG
)
3029 attr_name
= get_identifier ("long_call");
3030 else if (arm_pragma_long_calls
== SHORT
)
3031 attr_name
= get_identifier ("short_call");
3035 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3036 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3040 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3041 defined within the current compilation unit. If this cannot be
3042 determined, then 0 is returned. */
3044 current_file_function_operand (rtx sym_ref
)
3046 /* This is a bit of a fib. A function will have a short call flag
3047 applied to its name if it has the short call attribute, or it has
3048 already been defined within the current compilation unit. */
3049 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3052 /* The current function is always defined within the current compilation
3053 unit. If it s a weak definition however, then this may not be the real
3054 definition of the function, and so we have to say no. */
3055 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3056 && !DECL_WEAK (current_function_decl
))
3059 /* We cannot make the determination - default to returning 0. */
3063 /* Return nonzero if a 32 bit "long_call" should be generated for
3064 this call. We generate a long_call if the function:
3066 a. has an __attribute__((long call))
3067 or b. is within the scope of a #pragma long_calls
3068 or c. the -mlong-calls command line switch has been specified
3070 1. -ffunction-sections is in effect
3071 or 2. the current function has __attribute__ ((section))
3072 or 3. the target function has __attribute__ ((section))
3074 However we do not generate a long call if the function:
3076 d. has an __attribute__ ((short_call))
3077 or e. is inside the scope of a #pragma no_long_calls
3078 or f. is defined within the current compilation unit.
3080 This function will be called by C fragments contained in the machine
3081 description file. SYM_REF and CALL_COOKIE correspond to the matched
3082 rtl operands. CALL_SYMBOL is used to distinguish between
3083 two different callers of the function. It is set to 1 in the
3084 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3085 and "call_value" patterns. This is because of the difference in the
3086 SYM_REFs passed by these patterns. */
3088 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3092 if (GET_CODE (sym_ref
) != MEM
)
3095 sym_ref
= XEXP (sym_ref
, 0);
3098 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3101 if (call_cookie
& CALL_SHORT
)
3104 if (TARGET_LONG_CALLS
)
3106 if (flag_function_sections
3107 || DECL_SECTION_NAME (current_function_decl
))
3108 /* c.3 is handled by the definition of the
3109 ARM_DECLARE_FUNCTION_SIZE macro. */
3113 if (current_file_function_operand (sym_ref
))
3116 return (call_cookie
& CALL_LONG
)
3117 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3118 || TARGET_LONG_CALLS
;
3121 /* Return nonzero if it is ok to make a tail-call to DECL. */
3123 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3125 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3127 if (cfun
->machine
->sibcall_blocked
)
3130 /* Never tailcall something for which we have no decl, or if we
3131 are in Thumb mode. */
3132 if (decl
== NULL
|| TARGET_THUMB
)
3135 /* Get the calling method. */
3136 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3137 call_type
= CALL_SHORT
;
3138 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3139 call_type
= CALL_LONG
;
3141 /* Cannot tail-call to long calls, since these are out of range of
3142 a branch instruction. However, if not compiling PIC, we know
3143 we can reach the symbol if it is in this compilation unit. */
3144 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3147 /* If we are interworking and the function is not declared static
3148 then we can't tail-call it unless we know that it exists in this
3149 compilation unit (since it might be a Thumb routine). */
3150 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3153 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3154 if (IS_INTERRUPT (arm_current_func_type ()))
3157 /* Everything else is ok. */
3162 /* Addressing mode support functions. */
3164 /* Return nonzero if X is a legitimate immediate operand when compiling
3167 legitimate_pic_operand_p (rtx x
)
3171 && (GET_CODE (x
) == SYMBOL_REF
3172 || (GET_CODE (x
) == CONST
3173 && GET_CODE (XEXP (x
, 0)) == PLUS
3174 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
3181 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3183 if (GET_CODE (orig
) == SYMBOL_REF
3184 || GET_CODE (orig
) == LABEL_REF
)
3186 #ifndef AOF_ASSEMBLER
3187 rtx pic_ref
, address
;
3194 gcc_assert (!no_new_pseudos
);
3195 reg
= gen_reg_rtx (Pmode
);
3200 #ifdef AOF_ASSEMBLER
3201 /* The AOF assembler can generate relocations for these directly, and
3202 understands that the PIC register has to be added into the offset. */
3203 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3206 address
= gen_reg_rtx (Pmode
);
3211 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3213 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3215 if ((GET_CODE (orig
) == LABEL_REF
3216 || (GET_CODE (orig
) == SYMBOL_REF
&&
3217 SYMBOL_REF_LOCAL_P (orig
)))
3219 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
3222 pic_ref
= gen_const_mem (Pmode
,
3223 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3227 insn
= emit_move_insn (reg
, pic_ref
);
3229 current_function_uses_pic_offset_table
= 1;
3230 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3232 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3236 else if (GET_CODE (orig
) == CONST
)
3240 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3241 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3244 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3245 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3250 gcc_assert (!no_new_pseudos
);
3251 reg
= gen_reg_rtx (Pmode
);
3254 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3256 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3257 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3258 base
== reg
? 0 : reg
);
3260 if (GET_CODE (offset
) == CONST_INT
)
3262 /* The base register doesn't really matter, we only want to
3263 test the index for the appropriate mode. */
3264 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3266 gcc_assert (!no_new_pseudos
);
3267 offset
= force_reg (Pmode
, offset
);
3270 if (GET_CODE (offset
) == CONST_INT
)
3271 return plus_constant (base
, INTVAL (offset
));
3274 if (GET_MODE_SIZE (mode
) > 4
3275 && (GET_MODE_CLASS (mode
) == MODE_INT
3276 || TARGET_SOFT_FLOAT
))
3278 emit_insn (gen_addsi3 (reg
, base
, offset
));
3282 return gen_rtx_PLUS (Pmode
, base
, offset
);
3289 /* Find a spare low register to use during the prolog of a function. */
3292 thumb_find_work_register (unsigned long pushed_regs_mask
)
3296 /* Check the argument registers first as these are call-used. The
3297 register allocation order means that sometimes r3 might be used
3298 but earlier argument registers might not, so check them all. */
3299 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3300 if (!regs_ever_live
[reg
])
3303 /* Before going on to check the call-saved registers we can try a couple
3304 more ways of deducing that r3 is available. The first is when we are
3305 pushing anonymous arguments onto the stack and we have less than 4
3306 registers worth of fixed arguments(*). In this case r3 will be part of
3307 the variable argument list and so we can be sure that it will be
3308 pushed right at the start of the function. Hence it will be available
3309 for the rest of the prologue.
3310 (*): ie current_function_pretend_args_size is greater than 0. */
3311 if (cfun
->machine
->uses_anonymous_args
3312 && current_function_pretend_args_size
> 0)
3313 return LAST_ARG_REGNUM
;
3315 /* The other case is when we have fixed arguments but less than 4 registers
3316 worth. In this case r3 might be used in the body of the function, but
3317 it is not being used to convey an argument into the function. In theory
3318 we could just check current_function_args_size to see how many bytes are
3319 being passed in argument registers, but it seems that it is unreliable.
3320 Sometimes it will have the value 0 when in fact arguments are being
3321 passed. (See testcase execute/20021111-1.c for an example). So we also
3322 check the args_info.nregs field as well. The problem with this field is
3323 that it makes no allowances for arguments that are passed to the
3324 function but which are not used. Hence we could miss an opportunity
3325 when a function has an unused argument in r3. But it is better to be
3326 safe than to be sorry. */
3327 if (! cfun
->machine
->uses_anonymous_args
3328 && current_function_args_size
>= 0
3329 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3330 && cfun
->args_info
.nregs
< 4)
3331 return LAST_ARG_REGNUM
;
3333 /* Otherwise look for a call-saved register that is going to be pushed. */
3334 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3335 if (pushed_regs_mask
& (1 << reg
))
3338 /* Something went wrong - thumb_compute_save_reg_mask()
3339 should have arranged for a suitable register to be pushed. */
3344 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3348 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3350 #ifndef AOF_ASSEMBLER
3351 rtx l1
, pic_tmp
, pic_tmp2
, pic_rtx
;
3352 rtx global_offset_table
;
3354 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3357 gcc_assert (flag_pic
);
3359 l1
= gen_label_rtx ();
3361 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3362 /* On the ARM the PC register contains 'dot + 8' at the time of the
3363 addition, on the Thumb it is 'dot + 4'. */
3364 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
3366 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3367 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3369 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3371 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3375 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3376 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
3380 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3382 /* We will have pushed the pic register, so we should always be
3383 able to find a work register. */
3384 pic_tmp
= gen_rtx_REG (SImode
,
3385 thumb_find_work_register (saved_regs
));
3386 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3387 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3390 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3391 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
3394 /* Need to emit this whether or not we obey regdecls,
3395 since setjmp/longjmp can cause life info to screw up. */
3396 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3397 #endif /* AOF_ASSEMBLER */
3401 /* Return nonzero if X is valid as an ARM state addressing register. */
3403 arm_address_register_rtx_p (rtx x
, int strict_p
)
3407 if (GET_CODE (x
) != REG
)
3413 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3415 return (regno
<= LAST_ARM_REGNUM
3416 || regno
>= FIRST_PSEUDO_REGISTER
3417 || regno
== FRAME_POINTER_REGNUM
3418 || regno
== ARG_POINTER_REGNUM
);
3421 /* Return TRUE if this rtx is the difference of a symbol and a label,
3422 and will reduce to a PC-relative relocation in the object file.
3423 Expressions like this can be left alone when generating PIC, rather
3424 than forced through the GOT. */
3426 pcrel_constant_p (rtx x
)
3428 if (GET_CODE (x
) == MINUS
)
3429 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3434 /* Return nonzero if X is a valid ARM state address operand. */
3436 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3440 enum rtx_code code
= GET_CODE (x
);
3442 if (arm_address_register_rtx_p (x
, strict_p
))
3445 use_ldrd
= (TARGET_LDRD
3447 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3449 if (code
== POST_INC
|| code
== PRE_DEC
3450 || ((code
== PRE_INC
|| code
== POST_DEC
)
3451 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3452 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3454 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3455 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3456 && GET_CODE (XEXP (x
, 1)) == PLUS
3457 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3459 rtx addend
= XEXP (XEXP (x
, 1), 1);
3461 /* Don't allow ldrd post increment by register because it's hard
3462 to fixup invalid register choices. */
3464 && GET_CODE (x
) == POST_MODIFY
3465 && GET_CODE (addend
) == REG
)
3468 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3469 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3472 /* After reload constants split into minipools will have addresses
3473 from a LABEL_REF. */
3474 else if (reload_completed
3475 && (code
== LABEL_REF
3477 && GET_CODE (XEXP (x
, 0)) == PLUS
3478 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3479 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3482 else if (mode
== TImode
)
3485 else if (code
== PLUS
)
3487 rtx xop0
= XEXP (x
, 0);
3488 rtx xop1
= XEXP (x
, 1);
3490 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3491 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3492 || (arm_address_register_rtx_p (xop1
, strict_p
)
3493 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3497 /* Reload currently can't handle MINUS, so disable this for now */
3498 else if (GET_CODE (x
) == MINUS
)
3500 rtx xop0
= XEXP (x
, 0);
3501 rtx xop1
= XEXP (x
, 1);
3503 return (arm_address_register_rtx_p (xop0
, strict_p
)
3504 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3508 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3509 && code
== SYMBOL_REF
3510 && CONSTANT_POOL_ADDRESS_P (x
)
3512 && symbol_mentioned_p (get_pool_constant (x
))
3513 && ! pcrel_constant_p (get_pool_constant (x
))))
3519 /* Return nonzero if INDEX is valid for an address index operand in
3522 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3525 HOST_WIDE_INT range
;
3526 enum rtx_code code
= GET_CODE (index
);
3528 /* Standard coprocessor addressing modes. */
3529 if (TARGET_HARD_FLOAT
3530 && (TARGET_FPA
|| TARGET_MAVERICK
)
3531 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3532 || (TARGET_MAVERICK
&& mode
== DImode
)))
3533 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3534 && INTVAL (index
) > -1024
3535 && (INTVAL (index
) & 3) == 0);
3537 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3538 return (code
== CONST_INT
3539 && INTVAL (index
) < 1024
3540 && INTVAL (index
) > -1024
3541 && (INTVAL (index
) & 3) == 0);
3543 if (arm_address_register_rtx_p (index
, strict_p
)
3544 && (GET_MODE_SIZE (mode
) <= 4))
3547 if (mode
== DImode
|| mode
== DFmode
)
3549 if (code
== CONST_INT
)
3551 HOST_WIDE_INT val
= INTVAL (index
);
3554 return val
> -256 && val
< 256;
3556 return val
> -4096 && val
< 4092;
3559 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3562 if (GET_MODE_SIZE (mode
) <= 4
3565 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3569 rtx xiop0
= XEXP (index
, 0);
3570 rtx xiop1
= XEXP (index
, 1);
3572 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3573 && power_of_two_operand (xiop1
, SImode
))
3574 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3575 && power_of_two_operand (xiop0
, SImode
)));
3577 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3578 || code
== ASHIFT
|| code
== ROTATERT
)
3580 rtx op
= XEXP (index
, 1);
3582 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3583 && GET_CODE (op
) == CONST_INT
3585 && INTVAL (op
) <= 31);
3589 /* For ARM v4 we may be doing a sign-extend operation during the
3593 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3599 range
= (mode
== HImode
) ? 4095 : 4096;
3601 return (code
== CONST_INT
3602 && INTVAL (index
) < range
3603 && INTVAL (index
) > -range
);
3606 /* Return nonzero if X is valid as a Thumb state base register. */
3608 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3612 if (GET_CODE (x
) != REG
)
3618 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3620 return (regno
<= LAST_LO_REGNUM
3621 || regno
> LAST_VIRTUAL_REGISTER
3622 || regno
== FRAME_POINTER_REGNUM
3623 || (GET_MODE_SIZE (mode
) >= 4
3624 && (regno
== STACK_POINTER_REGNUM
3625 || regno
>= FIRST_PSEUDO_REGISTER
3626 || x
== hard_frame_pointer_rtx
3627 || x
== arg_pointer_rtx
)));
3630 /* Return nonzero if x is a legitimate index register. This is the case
3631 for any base register that can access a QImode object. */
3633 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3635 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3638 /* Return nonzero if x is a legitimate Thumb-state address.
3640 The AP may be eliminated to either the SP or the FP, so we use the
3641 least common denominator, e.g. SImode, and offsets from 0 to 64.
3643 ??? Verify whether the above is the right approach.
3645 ??? Also, the FP may be eliminated to the SP, so perhaps that
3646 needs special handling also.
3648 ??? Look at how the mips16 port solves this problem. It probably uses
3649 better ways to solve some of these problems.
3651 Although it is not incorrect, we don't accept QImode and HImode
3652 addresses based on the frame pointer or arg pointer until the
3653 reload pass starts. This is so that eliminating such addresses
3654 into stack based ones won't produce impossible code. */
3656 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3658 /* ??? Not clear if this is right. Experiment. */
3659 if (GET_MODE_SIZE (mode
) < 4
3660 && !(reload_in_progress
|| reload_completed
)
3661 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3662 || reg_mentioned_p (arg_pointer_rtx
, x
)
3663 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3664 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3665 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3666 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3669 /* Accept any base register. SP only in SImode or larger. */
3670 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3673 /* This is PC relative data before arm_reorg runs. */
3674 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3675 && GET_CODE (x
) == SYMBOL_REF
3676 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3679 /* This is PC relative data after arm_reorg runs. */
3680 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3681 && (GET_CODE (x
) == LABEL_REF
3682 || (GET_CODE (x
) == CONST
3683 && GET_CODE (XEXP (x
, 0)) == PLUS
3684 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3685 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3688 /* Post-inc indexing only supported for SImode and larger. */
3689 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3690 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3693 else if (GET_CODE (x
) == PLUS
)
3695 /* REG+REG address can be any two index registers. */
3696 /* We disallow FRAME+REG addressing since we know that FRAME
3697 will be replaced with STACK, and SP relative addressing only
3698 permits SP+OFFSET. */
3699 if (GET_MODE_SIZE (mode
) <= 4
3700 && XEXP (x
, 0) != frame_pointer_rtx
3701 && XEXP (x
, 1) != frame_pointer_rtx
3702 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3703 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3706 /* REG+const has 5-7 bit offset for non-SP registers. */
3707 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3708 || XEXP (x
, 0) == arg_pointer_rtx
)
3709 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3710 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3713 /* REG+const has 10 bit offset for SP, but only SImode and
3714 larger is supported. */
3715 /* ??? Should probably check for DI/DFmode overflow here
3716 just like GO_IF_LEGITIMATE_OFFSET does. */
3717 else if (GET_CODE (XEXP (x
, 0)) == REG
3718 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3719 && GET_MODE_SIZE (mode
) >= 4
3720 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3721 && INTVAL (XEXP (x
, 1)) >= 0
3722 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3723 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3726 else if (GET_CODE (XEXP (x
, 0)) == REG
3727 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3728 && GET_MODE_SIZE (mode
) >= 4
3729 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3730 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3734 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3735 && GET_MODE_SIZE (mode
) == 4
3736 && GET_CODE (x
) == SYMBOL_REF
3737 && CONSTANT_POOL_ADDRESS_P (x
)
3739 && symbol_mentioned_p (get_pool_constant (x
))
3740 && ! pcrel_constant_p (get_pool_constant (x
))))
3746 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3747 instruction of mode MODE. */
3749 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3751 switch (GET_MODE_SIZE (mode
))
3754 return val
>= 0 && val
< 32;
3757 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3761 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3766 /* Build the SYMBOL_REF for __tls_get_addr. */
3768 static GTY(()) rtx tls_get_addr_libfunc
;
3771 get_tls_get_addr (void)
3773 if (!tls_get_addr_libfunc
)
3774 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
3775 return tls_get_addr_libfunc
;
3779 arm_load_tp (rtx target
)
3782 target
= gen_reg_rtx (SImode
);
3786 /* Can return in any reg. */
3787 emit_insn (gen_load_tp_hard (target
));
3791 /* Always returned in r0. Immediately copy the result into a pseudo,
3792 otherwise other uses of r0 (e.g. setting up function arguments) may
3793 clobber the value. */
3797 emit_insn (gen_load_tp_soft ());
3799 tmp
= gen_rtx_REG (SImode
, 0);
3800 emit_move_insn (target
, tmp
);
3806 load_tls_operand (rtx x
, rtx reg
)
3810 if (reg
== NULL_RTX
)
3811 reg
= gen_reg_rtx (SImode
);
3813 tmp
= gen_rtx_CONST (SImode
, x
);
3815 emit_move_insn (reg
, tmp
);
3821 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
3823 rtx insns
, label
, sum
;
3827 label
= gen_label_rtx ();
3828 sum
= gen_rtx_UNSPEC (Pmode
,
3829 gen_rtvec (4, x
, GEN_INT (reloc
),
3830 gen_rtx_LABEL_REF (Pmode
, label
),
3831 GEN_INT (TARGET_ARM
? 8 : 4)),
3833 reg
= load_tls_operand (sum
, reg
);
3836 emit_insn (gen_pic_add_dot_plus_eight (reg
, label
));
3838 emit_insn (gen_pic_add_dot_plus_four (reg
, label
));
3840 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
3841 Pmode
, 1, reg
, Pmode
);
3843 insns
= get_insns ();
3850 legitimize_tls_address (rtx x
, rtx reg
)
3852 rtx dest
, tp
, label
, sum
, insns
, ret
, eqv
, addend
;
3853 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
3857 case TLS_MODEL_GLOBAL_DYNAMIC
:
3858 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
3859 dest
= gen_reg_rtx (Pmode
);
3860 emit_libcall_block (insns
, dest
, ret
, x
);
3863 case TLS_MODEL_LOCAL_DYNAMIC
:
3864 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
3866 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3867 share the LDM result with other LD model accesses. */
3868 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
3870 dest
= gen_reg_rtx (Pmode
);
3871 emit_libcall_block (insns
, dest
, ret
, x
);
3873 /* Load the addend. */
3874 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
3876 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
3877 return gen_rtx_PLUS (Pmode
, dest
, addend
);
3879 case TLS_MODEL_INITIAL_EXEC
:
3880 label
= gen_label_rtx ();
3881 sum
= gen_rtx_UNSPEC (Pmode
,
3882 gen_rtvec (4, x
, GEN_INT (TLS_IE32
),
3883 gen_rtx_LABEL_REF (Pmode
, label
),
3884 GEN_INT (TARGET_ARM
? 8 : 4)),
3886 reg
= load_tls_operand (sum
, reg
);
3889 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, label
));
3892 emit_insn (gen_pic_add_dot_plus_four (reg
, label
));
3893 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
3896 tp
= arm_load_tp (NULL_RTX
);
3898 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3900 case TLS_MODEL_LOCAL_EXEC
:
3901 tp
= arm_load_tp (NULL_RTX
);
3903 reg
= gen_rtx_UNSPEC (Pmode
,
3904 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
3906 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
3908 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3915 /* Try machine-dependent ways of modifying an illegitimate address
3916 to be legitimate. If we find one, return the new, valid address. */
3918 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3920 if (arm_tls_symbol_p (x
))
3921 return legitimize_tls_address (x
, NULL_RTX
);
3923 if (GET_CODE (x
) == PLUS
)
3925 rtx xop0
= XEXP (x
, 0);
3926 rtx xop1
= XEXP (x
, 1);
3928 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3929 xop0
= force_reg (SImode
, xop0
);
3931 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3932 xop1
= force_reg (SImode
, xop1
);
3934 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3935 && GET_CODE (xop1
) == CONST_INT
)
3937 HOST_WIDE_INT n
, low_n
;
3941 /* VFP addressing modes actually allow greater offsets, but for
3942 now we just stick with the lowest common denominator. */
3944 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3956 low_n
= ((mode
) == TImode
? 0
3957 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3961 base_reg
= gen_reg_rtx (SImode
);
3962 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3963 GEN_INT (n
)), NULL_RTX
);
3964 emit_move_insn (base_reg
, val
);
3965 x
= (low_n
== 0 ? base_reg
3966 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3968 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3969 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3972 /* XXX We don't allow MINUS any more -- see comment in
3973 arm_legitimate_address_p (). */
3974 else if (GET_CODE (x
) == MINUS
)
3976 rtx xop0
= XEXP (x
, 0);
3977 rtx xop1
= XEXP (x
, 1);
3979 if (CONSTANT_P (xop0
))
3980 xop0
= force_reg (SImode
, xop0
);
3982 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3983 xop1
= force_reg (SImode
, xop1
);
3985 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3986 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3989 /* Make sure to take full advantage of the pre-indexed addressing mode
3990 with absolute addresses which often allows for the base register to
3991 be factorized for multiple adjacent memory references, and it might
3992 even allows for the mini pool to be avoided entirely. */
3993 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
3996 HOST_WIDE_INT mask
, base
, index
;
3999 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4000 use a 8 bit index. So let's use a 12 bit index for SImode only and
4001 hope that arm_gen_constant will enable ldrb to use more bits. */
4002 bits
= (mode
== SImode
) ? 12 : 8;
4003 mask
= (1 << bits
) - 1;
4004 base
= INTVAL (x
) & ~mask
;
4005 index
= INTVAL (x
) & mask
;
4006 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4008 /* It'll most probably be more efficient to generate the base
4009 with more bits set and use a negative index instead. */
4013 base_reg
= force_reg (SImode
, GEN_INT (base
));
4014 x
= gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (index
));
4019 /* We need to find and carefully transform any SYMBOL and LABEL
4020 references; so go back to the original address expression. */
4021 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4023 if (new_x
!= orig_x
)
4031 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4032 to be legitimate. If we find one, return the new, valid address. */
4034 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4036 if (arm_tls_symbol_p (x
))
4037 return legitimize_tls_address (x
, NULL_RTX
);
4039 if (GET_CODE (x
) == PLUS
4040 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4041 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4042 || INTVAL (XEXP (x
, 1)) < 0))
4044 rtx xop0
= XEXP (x
, 0);
4045 rtx xop1
= XEXP (x
, 1);
4046 HOST_WIDE_INT offset
= INTVAL (xop1
);
4048 /* Try and fold the offset into a biasing of the base register and
4049 then offsetting that. Don't do this when optimizing for space
4050 since it can cause too many CSEs. */
4051 if (optimize_size
&& offset
>= 0
4052 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4054 HOST_WIDE_INT delta
;
4057 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4058 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4059 delta
= 31 * GET_MODE_SIZE (mode
);
4061 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4063 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4065 x
= plus_constant (xop0
, delta
);
4067 else if (offset
< 0 && offset
> -256)
4068 /* Small negative offsets are best done with a subtract before the
4069 dereference, forcing these into a register normally takes two
4071 x
= force_operand (x
, NULL_RTX
);
4074 /* For the remaining cases, force the constant into a register. */
4075 xop1
= force_reg (SImode
, xop1
);
4076 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4079 else if (GET_CODE (x
) == PLUS
4080 && s_register_operand (XEXP (x
, 1), SImode
)
4081 && !s_register_operand (XEXP (x
, 0), SImode
))
4083 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4085 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4090 /* We need to find and carefully transform any SYMBOL and LABEL
4091 references; so go back to the original address expression. */
4092 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4094 if (new_x
!= orig_x
)
4102 thumb_legitimize_reload_address (rtx
*x_p
,
4103 enum machine_mode mode
,
4104 int opnum
, int type
,
4105 int ind_levels ATTRIBUTE_UNUSED
)
4109 if (GET_CODE (x
) == PLUS
4110 && GET_MODE_SIZE (mode
) < 4
4111 && REG_P (XEXP (x
, 0))
4112 && XEXP (x
, 0) == stack_pointer_rtx
4113 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4114 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4119 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4120 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4124 /* If both registers are hi-regs, then it's better to reload the
4125 entire expression rather than each register individually. That
4126 only requires one reload register rather than two. */
4127 if (GET_CODE (x
) == PLUS
4128 && REG_P (XEXP (x
, 0))
4129 && REG_P (XEXP (x
, 1))
4130 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4131 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4136 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4137 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4144 /* Test for various thread-local symbols. */
4146 /* Return TRUE if X is a thread-local symbol. */
4149 arm_tls_symbol_p (rtx x
)
4151 if (! TARGET_HAVE_TLS
)
4154 if (GET_CODE (x
) != SYMBOL_REF
)
4157 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4160 /* Helper for arm_tls_referenced_p. */
4163 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4165 if (GET_CODE (*x
) == SYMBOL_REF
)
4166 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4168 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4169 TLS offsets, not real symbol references. */
4170 if (GET_CODE (*x
) == UNSPEC
4171 && XINT (*x
, 1) == UNSPEC_TLS
)
4177 /* Return TRUE if X contains any TLS symbol references. */
4180 arm_tls_referenced_p (rtx x
)
4182 if (! TARGET_HAVE_TLS
)
4185 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4188 #define REG_OR_SUBREG_REG(X) \
4189 (GET_CODE (X) == REG \
4190 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4192 #define REG_OR_SUBREG_RTX(X) \
4193 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4195 #ifndef COSTS_N_INSNS
4196 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4199 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4201 enum machine_mode mode
= GET_MODE (x
);
4214 return COSTS_N_INSNS (1);
4217 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4220 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4227 return COSTS_N_INSNS (2) + cycles
;
4229 return COSTS_N_INSNS (1) + 16;
4232 return (COSTS_N_INSNS (1)
4233 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4234 + GET_CODE (SET_DEST (x
)) == MEM
));
4239 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4241 if (thumb_shiftable_const (INTVAL (x
)))
4242 return COSTS_N_INSNS (2);
4243 return COSTS_N_INSNS (3);
4245 else if ((outer
== PLUS
|| outer
== COMPARE
)
4246 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4248 else if (outer
== AND
4249 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4250 return COSTS_N_INSNS (1);
4251 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4252 || outer
== LSHIFTRT
)
4254 return COSTS_N_INSNS (2);
4260 return COSTS_N_INSNS (3);
4278 /* XXX another guess. */
4279 /* Memory costs quite a lot for the first word, but subsequent words
4280 load at the equivalent of a single insn each. */
4281 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4282 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4287 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4292 /* XXX still guessing. */
4293 switch (GET_MODE (XEXP (x
, 0)))
4296 return (1 + (mode
== DImode
? 4 : 0)
4297 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4300 return (4 + (mode
== DImode
? 4 : 0)
4301 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4304 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4316 /* Worker routine for arm_rtx_costs. */
4318 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4320 enum machine_mode mode
= GET_MODE (x
);
4321 enum rtx_code subcode
;
4327 /* Memory costs quite a lot for the first word, but subsequent words
4328 load at the equivalent of a single insn each. */
4329 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4330 + (GET_CODE (x
) == SYMBOL_REF
4331 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4337 return optimize_size
? COSTS_N_INSNS (2) : 100;
4340 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4347 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4349 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4350 + ((GET_CODE (XEXP (x
, 0)) == REG
4351 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4352 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4354 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4355 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4356 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4358 + ((GET_CODE (XEXP (x
, 1)) == REG
4359 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4360 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4361 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4366 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4367 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4368 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4369 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4372 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4373 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4374 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4375 && arm_const_double_rtx (XEXP (x
, 1))))
4377 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4378 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4379 && arm_const_double_rtx (XEXP (x
, 0))))
4382 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4383 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4384 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4385 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4386 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4387 || subcode
== ROTATE
|| subcode
== ROTATERT
4389 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4390 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4391 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4392 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4393 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4394 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4395 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4400 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4401 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4402 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4403 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4404 && arm_const_double_rtx (XEXP (x
, 1))))
4408 case AND
: case XOR
: case IOR
:
4411 /* Normally the frame registers will be spilt into reg+const during
4412 reload, so it is a bad idea to combine them with other instructions,
4413 since then they might not be moved outside of loops. As a compromise
4414 we allow integration with ops that have a constant as their second
4416 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4417 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4418 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4419 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4420 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4424 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4425 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4426 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4427 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4430 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4431 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4432 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4433 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4434 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4437 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4438 return (1 + extra_cost
4439 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4440 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4441 || subcode
== ROTATE
|| subcode
== ROTATERT
4443 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4444 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4445 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4446 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4447 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4448 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4454 /* This should have been handled by the CPU specific routines. */
4458 if (arm_arch3m
&& mode
== SImode
4459 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4460 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4461 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4462 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4463 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4464 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4469 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4470 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4474 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4476 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4479 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4487 return 4 + (mode
== DImode
? 4 : 0);
4490 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4491 return (4 + (mode
== DImode
? 4 : 0)
4492 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4495 switch (GET_MODE (XEXP (x
, 0)))
4498 return (1 + (mode
== DImode
? 4 : 0)
4499 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4502 return (4 + (mode
== DImode
? 4 : 0)
4503 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4506 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4521 if (const_ok_for_arm (INTVAL (x
)))
4522 return outer
== SET
? 2 : -1;
4523 else if (outer
== AND
4524 && const_ok_for_arm (~INTVAL (x
)))
4526 else if ((outer
== COMPARE
4527 || outer
== PLUS
|| outer
== MINUS
)
4528 && const_ok_for_arm (-INTVAL (x
)))
4539 if (arm_const_double_rtx (x
))
4540 return outer
== SET
? 2 : -1;
4541 else if ((outer
== COMPARE
|| outer
== PLUS
)
4542 && neg_const_double_rtx_ok_for_fpa (x
))
4551 /* RTX costs when optimizing for size. */
4553 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4555 enum machine_mode mode
= GET_MODE (x
);
4559 /* XXX TBD. For now, use the standard costs. */
4560 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4567 /* A memory access costs 1 insn if the mode is small, or the address is
4568 a single register, otherwise it costs one insn per word. */
4569 if (REG_P (XEXP (x
, 0)))
4570 *total
= COSTS_N_INSNS (1);
4572 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4579 /* Needs a libcall, so it costs about this. */
4580 *total
= COSTS_N_INSNS (2);
4584 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4586 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4594 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4596 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4599 else if (mode
== SImode
)
4601 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4602 /* Slightly disparage register shifts, but not by much. */
4603 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4604 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4608 /* Needs a libcall. */
4609 *total
= COSTS_N_INSNS (2);
4613 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4615 *total
= COSTS_N_INSNS (1);
4621 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4622 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4624 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4625 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4626 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4627 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4628 || subcode1
== ASHIFTRT
)
4630 /* It's just the cost of the two operands. */
4635 *total
= COSTS_N_INSNS (1);
4639 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4643 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4645 *total
= COSTS_N_INSNS (1);
4650 case AND
: case XOR
: case IOR
:
4653 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4655 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4656 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4657 || (code
== AND
&& subcode
== NOT
))
4659 /* It's just the cost of the two operands. */
4665 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4669 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4673 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4674 *total
= COSTS_N_INSNS (1);
4677 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4686 if (cc_register (XEXP (x
, 0), VOIDmode
))
4689 *total
= COSTS_N_INSNS (1);
4693 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4694 *total
= COSTS_N_INSNS (1);
4696 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4701 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4703 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4704 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4707 *total
+= COSTS_N_INSNS (1);
4712 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4714 switch (GET_MODE (XEXP (x
, 0)))
4717 *total
+= COSTS_N_INSNS (1);
4721 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4727 *total
+= COSTS_N_INSNS (2);
4732 *total
+= COSTS_N_INSNS (1);
4737 if (const_ok_for_arm (INTVAL (x
)))
4738 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4739 else if (const_ok_for_arm (~INTVAL (x
)))
4740 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4741 else if (const_ok_for_arm (-INTVAL (x
)))
4743 if (outer_code
== COMPARE
|| outer_code
== PLUS
4744 || outer_code
== MINUS
)
4747 *total
= COSTS_N_INSNS (1);
4750 *total
= COSTS_N_INSNS (2);
4756 *total
= COSTS_N_INSNS (2);
4760 *total
= COSTS_N_INSNS (4);
4764 if (mode
!= VOIDmode
)
4765 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4767 *total
= COSTS_N_INSNS (4); /* How knows? */
4772 /* RTX costs for cores with a slow MUL implementation. */
4775 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4777 enum machine_mode mode
= GET_MODE (x
);
4781 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4788 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4795 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4797 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4798 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4799 int cost
, const_ok
= const_ok_for_arm (i
);
4800 int j
, booth_unit_size
;
4802 /* Tune as appropriate. */
4803 cost
= const_ok
? 4 : 8;
4804 booth_unit_size
= 2;
4805 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4807 i
>>= booth_unit_size
;
4815 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4816 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4820 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4826 /* RTX cost for cores with a fast multiply unit (M variants). */
4829 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4831 enum machine_mode mode
= GET_MODE (x
);
4835 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4842 /* There is no point basing this on the tuning, since it is always the
4843 fast variant if it exists at all. */
4845 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4846 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4847 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4854 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4861 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4863 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4864 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4865 int cost
, const_ok
= const_ok_for_arm (i
);
4866 int j
, booth_unit_size
;
4868 /* Tune as appropriate. */
4869 cost
= const_ok
? 4 : 8;
4870 booth_unit_size
= 8;
4871 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4873 i
>>= booth_unit_size
;
4881 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4882 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4886 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4892 /* RTX cost for XScale CPUs. */
4895 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4897 enum machine_mode mode
= GET_MODE (x
);
4901 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4908 /* There is no point basing this on the tuning, since it is always the
4909 fast variant if it exists at all. */
4911 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4912 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4913 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4920 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4927 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4929 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4930 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4931 int cost
, const_ok
= const_ok_for_arm (i
);
4932 unsigned HOST_WIDE_INT masked_const
;
4934 /* The cost will be related to two insns.
4935 First a load of the constant (MOV or LDR), then a multiply. */
4938 cost
+= 1; /* LDR is probably more expensive because
4939 of longer result latency. */
4940 masked_const
= i
& 0xffff8000;
4941 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4943 masked_const
= i
& 0xf8000000;
4944 if (masked_const
== 0 || masked_const
== 0xf8000000)
4953 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4954 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4958 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4959 will stall until the multiplication is complete. */
4960 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4961 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
4963 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4967 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4973 /* RTX costs for 9e (and later) cores. */
4976 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4978 enum machine_mode mode
= GET_MODE (x
);
4987 *total
= COSTS_N_INSNS (3);
4991 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4999 /* There is no point basing this on the tuning, since it is always the
5000 fast variant if it exists at all. */
5002 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5003 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5004 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5011 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5028 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5029 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5033 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5037 /* All address computations that can be done are free, but rtx cost returns
5038 the same for practically all of them. So we weight the different types
5039 of address here in the order (most pref first):
5040 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5042 arm_arm_address_cost (rtx x
)
5044 enum rtx_code c
= GET_CODE (x
);
5046 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5048 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5051 if (c
== PLUS
|| c
== MINUS
)
5053 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5056 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5066 arm_thumb_address_cost (rtx x
)
5068 enum rtx_code c
= GET_CODE (x
);
5073 && GET_CODE (XEXP (x
, 0)) == REG
5074 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5081 arm_address_cost (rtx x
)
5083 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5087 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5091 /* Some true dependencies can have a higher cost depending
5092 on precisely how certain input operands are used. */
5094 && REG_NOTE_KIND (link
) == 0
5095 && recog_memoized (insn
) >= 0
5096 && recog_memoized (dep
) >= 0)
5098 int shift_opnum
= get_attr_shift (insn
);
5099 enum attr_type attr_type
= get_attr_type (dep
);
5101 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5102 operand for INSN. If we have a shifted input operand and the
5103 instruction we depend on is another ALU instruction, then we may
5104 have to account for an additional stall. */
5105 if (shift_opnum
!= 0
5106 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5108 rtx shifted_operand
;
5111 /* Get the shifted operand. */
5112 extract_insn (insn
);
5113 shifted_operand
= recog_data
.operand
[shift_opnum
];
5115 /* Iterate over all the operands in DEP. If we write an operand
5116 that overlaps with SHIFTED_OPERAND, then we have increase the
5117 cost of this dependency. */
5119 preprocess_constraints ();
5120 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5122 /* We can ignore strict inputs. */
5123 if (recog_data
.operand_type
[opno
] == OP_IN
)
5126 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5133 /* XXX This is not strictly true for the FPA. */
5134 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5135 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5138 /* Call insns don't incur a stall, even if they follow a load. */
5139 if (REG_NOTE_KIND (link
) == 0
5140 && GET_CODE (insn
) == CALL_INSN
)
5143 if ((i_pat
= single_set (insn
)) != NULL
5144 && GET_CODE (SET_SRC (i_pat
)) == MEM
5145 && (d_pat
= single_set (dep
)) != NULL
5146 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5148 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5149 /* This is a load after a store, there is no conflict if the load reads
5150 from a cached area. Assume that loads from the stack, and from the
5151 constant pool are cached, and that others will miss. This is a
5154 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5155 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5156 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5157 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5164 static int fp_consts_inited
= 0;
5166 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5167 static const char * const strings_fp
[8] =
5170 "4", "5", "0.5", "10"
5173 static REAL_VALUE_TYPE values_fp
[8];
5176 init_fp_table (void)
5182 fp_consts_inited
= 1;
5184 fp_consts_inited
= 8;
5186 for (i
= 0; i
< fp_consts_inited
; i
++)
5188 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5193 /* Return TRUE if rtx X is a valid immediate FP constant. */
5195 arm_const_double_rtx (rtx x
)
5200 if (!fp_consts_inited
)
5203 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5204 if (REAL_VALUE_MINUS_ZERO (r
))
5207 for (i
= 0; i
< fp_consts_inited
; i
++)
5208 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5214 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5216 neg_const_double_rtx_ok_for_fpa (rtx x
)
5221 if (!fp_consts_inited
)
5224 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5225 r
= REAL_VALUE_NEGATE (r
);
5226 if (REAL_VALUE_MINUS_ZERO (r
))
5229 for (i
= 0; i
< 8; i
++)
5230 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5236 /* Predicates for `match_operand' and `match_operator'. */
5238 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5240 cirrus_memory_offset (rtx op
)
5242 /* Reject eliminable registers. */
5243 if (! (reload_in_progress
|| reload_completed
)
5244 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5245 || reg_mentioned_p (arg_pointer_rtx
, op
)
5246 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5247 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5248 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5249 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5252 if (GET_CODE (op
) == MEM
)
5258 /* Match: (mem (reg)). */
5259 if (GET_CODE (ind
) == REG
)
5265 if (GET_CODE (ind
) == PLUS
5266 && GET_CODE (XEXP (ind
, 0)) == REG
5267 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5268 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5275 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5276 WB if true if writeback address modes are allowed. */
5279 arm_coproc_mem_operand (rtx op
, bool wb
)
5283 /* Reject eliminable registers. */
5284 if (! (reload_in_progress
|| reload_completed
)
5285 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5286 || reg_mentioned_p (arg_pointer_rtx
, op
)
5287 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5288 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5289 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5290 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5293 /* Constants are converted into offsets from labels. */
5294 if (GET_CODE (op
) != MEM
)
5299 if (reload_completed
5300 && (GET_CODE (ind
) == LABEL_REF
5301 || (GET_CODE (ind
) == CONST
5302 && GET_CODE (XEXP (ind
, 0)) == PLUS
5303 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5304 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5307 /* Match: (mem (reg)). */
5308 if (GET_CODE (ind
) == REG
)
5309 return arm_address_register_rtx_p (ind
, 0);
5311 /* Autoincremment addressing modes. */
5313 && (GET_CODE (ind
) == PRE_INC
5314 || GET_CODE (ind
) == POST_INC
5315 || GET_CODE (ind
) == PRE_DEC
5316 || GET_CODE (ind
) == POST_DEC
))
5317 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5320 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5321 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5322 && GET_CODE (XEXP (ind
, 1)) == PLUS
5323 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5324 ind
= XEXP (ind
, 1);
5329 if (GET_CODE (ind
) == PLUS
5330 && GET_CODE (XEXP (ind
, 0)) == REG
5331 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5332 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5333 && INTVAL (XEXP (ind
, 1)) > -1024
5334 && INTVAL (XEXP (ind
, 1)) < 1024
5335 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5341 /* Return true if X is a register that will be eliminated later on. */
5343 arm_eliminable_register (rtx x
)
5345 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5346 || REGNO (x
) == ARG_POINTER_REGNUM
5347 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5348 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5351 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5352 VFP registers. Otherwise return NO_REGS. */
5355 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5357 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5360 return GENERAL_REGS
;
5363 /* Values which must be returned in the most-significant end of the return
5367 arm_return_in_msb (tree valtype
)
5369 return (TARGET_AAPCS_BASED
5371 && (AGGREGATE_TYPE_P (valtype
)
5372 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5375 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5376 Use by the Cirrus Maverick code which has to workaround
5377 a hardware bug triggered by such instructions. */
5379 arm_memory_load_p (rtx insn
)
5381 rtx body
, lhs
, rhs
;;
5383 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5386 body
= PATTERN (insn
);
5388 if (GET_CODE (body
) != SET
)
5391 lhs
= XEXP (body
, 0);
5392 rhs
= XEXP (body
, 1);
5394 lhs
= REG_OR_SUBREG_RTX (lhs
);
5396 /* If the destination is not a general purpose
5397 register we do not have to worry. */
5398 if (GET_CODE (lhs
) != REG
5399 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5402 /* As well as loads from memory we also have to react
5403 to loads of invalid constants which will be turned
5404 into loads from the minipool. */
5405 return (GET_CODE (rhs
) == MEM
5406 || GET_CODE (rhs
) == SYMBOL_REF
5407 || note_invalid_constants (insn
, -1, false));
5410 /* Return TRUE if INSN is a Cirrus instruction. */
5412 arm_cirrus_insn_p (rtx insn
)
5414 enum attr_cirrus attr
;
5416 /* get_attr cannot accept USE or CLOBBER. */
5418 || GET_CODE (insn
) != INSN
5419 || GET_CODE (PATTERN (insn
)) == USE
5420 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5423 attr
= get_attr_cirrus (insn
);
5425 return attr
!= CIRRUS_NOT
;
5428 /* Cirrus reorg for invalid instruction combinations. */
5430 cirrus_reorg (rtx first
)
5432 enum attr_cirrus attr
;
5433 rtx body
= PATTERN (first
);
5437 /* Any branch must be followed by 2 non Cirrus instructions. */
5438 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5441 t
= next_nonnote_insn (first
);
5443 if (arm_cirrus_insn_p (t
))
5446 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5450 emit_insn_after (gen_nop (), first
);
5455 /* (float (blah)) is in parallel with a clobber. */
5456 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5457 body
= XVECEXP (body
, 0, 0);
5459 if (GET_CODE (body
) == SET
)
5461 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5463 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5464 be followed by a non Cirrus insn. */
5465 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5467 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5468 emit_insn_after (gen_nop (), first
);
5472 else if (arm_memory_load_p (first
))
5474 unsigned int arm_regno
;
5476 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5477 ldr/cfmv64hr combination where the Rd field is the same
5478 in both instructions must be split with a non Cirrus
5485 /* Get Arm register number for ldr insn. */
5486 if (GET_CODE (lhs
) == REG
)
5487 arm_regno
= REGNO (lhs
);
5490 gcc_assert (GET_CODE (rhs
) == REG
);
5491 arm_regno
= REGNO (rhs
);
5495 first
= next_nonnote_insn (first
);
5497 if (! arm_cirrus_insn_p (first
))
5500 body
= PATTERN (first
);
5502 /* (float (blah)) is in parallel with a clobber. */
5503 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5504 body
= XVECEXP (body
, 0, 0);
5506 if (GET_CODE (body
) == FLOAT
)
5507 body
= XEXP (body
, 0);
5509 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5510 && GET_CODE (XEXP (body
, 1)) == REG
5511 && arm_regno
== REGNO (XEXP (body
, 1)))
5512 emit_insn_after (gen_nop (), first
);
5518 /* get_attr cannot accept USE or CLOBBER. */
5520 || GET_CODE (first
) != INSN
5521 || GET_CODE (PATTERN (first
)) == USE
5522 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5525 attr
= get_attr_cirrus (first
);
5527 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5528 must be followed by a non-coprocessor instruction. */
5529 if (attr
== CIRRUS_COMPARE
)
5533 t
= next_nonnote_insn (first
);
5535 if (arm_cirrus_insn_p (t
))
5538 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5542 emit_insn_after (gen_nop (), first
);
5548 /* Return TRUE if X references a SYMBOL_REF. */
5550 symbol_mentioned_p (rtx x
)
5555 if (GET_CODE (x
) == SYMBOL_REF
)
5558 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5559 are constant offsets, not symbols. */
5560 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5563 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5565 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5571 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5572 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5575 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5582 /* Return TRUE if X references a LABEL_REF. */
5584 label_mentioned_p (rtx x
)
5589 if (GET_CODE (x
) == LABEL_REF
)
5592 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5593 instruction, but they are constant offsets, not symbols. */
5594 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5597 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5598 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5604 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5605 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5608 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5616 tls_mentioned_p (rtx x
)
5618 switch (GET_CODE (x
))
5621 return tls_mentioned_p (XEXP (x
, 0));
5624 if (XINT (x
, 1) == UNSPEC_TLS
)
5632 /* Must not copy a SET whose source operand is PC-relative. */
5635 arm_cannot_copy_insn_p (rtx insn
)
5637 rtx pat
= PATTERN (insn
);
5639 if (GET_CODE (pat
) == PARALLEL
5640 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
5642 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
5644 if (GET_CODE (rhs
) == UNSPEC
5645 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
5648 if (GET_CODE (rhs
) == MEM
5649 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
5650 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
5660 enum rtx_code code
= GET_CODE (x
);
5677 /* Return 1 if memory locations are adjacent. */
5679 adjacent_mem_locations (rtx a
, rtx b
)
5681 /* We don't guarantee to preserve the order of these memory refs. */
5682 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5685 if ((GET_CODE (XEXP (a
, 0)) == REG
5686 || (GET_CODE (XEXP (a
, 0)) == PLUS
5687 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5688 && (GET_CODE (XEXP (b
, 0)) == REG
5689 || (GET_CODE (XEXP (b
, 0)) == PLUS
5690 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5692 HOST_WIDE_INT val0
= 0, val1
= 0;
5696 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5698 reg0
= XEXP (XEXP (a
, 0), 0);
5699 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5704 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5706 reg1
= XEXP (XEXP (b
, 0), 0);
5707 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5712 /* Don't accept any offset that will require multiple
5713 instructions to handle, since this would cause the
5714 arith_adjacentmem pattern to output an overlong sequence. */
5715 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5718 /* Don't allow an eliminable register: register elimination can make
5719 the offset too large. */
5720 if (arm_eliminable_register (reg0
))
5723 val_diff
= val1
- val0
;
5727 /* If the target has load delay slots, then there's no benefit
5728 to using an ldm instruction unless the offset is zero and
5729 we are optimizing for size. */
5730 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5731 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5732 && (val_diff
== 4 || val_diff
== -4));
5735 return ((REGNO (reg0
) == REGNO (reg1
))
5736 && (val_diff
== 4 || val_diff
== -4));
5743 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5744 HOST_WIDE_INT
*load_offset
)
5746 int unsorted_regs
[4];
5747 HOST_WIDE_INT unsorted_offsets
[4];
5752 /* Can only handle 2, 3, or 4 insns at present,
5753 though could be easily extended if required. */
5754 gcc_assert (nops
>= 2 && nops
<= 4);
5756 /* Loop over the operands and check that the memory references are
5757 suitable (i.e. immediate offsets from the same base register). At
5758 the same time, extract the target register, and the memory
5760 for (i
= 0; i
< nops
; i
++)
5765 /* Convert a subreg of a mem into the mem itself. */
5766 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5767 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5769 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5771 /* Don't reorder volatile memory references; it doesn't seem worth
5772 looking for the case where the order is ok anyway. */
5773 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5776 offset
= const0_rtx
;
5778 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5779 || (GET_CODE (reg
) == SUBREG
5780 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5781 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5782 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5784 || (GET_CODE (reg
) == SUBREG
5785 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5786 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5791 base_reg
= REGNO (reg
);
5792 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5793 ? REGNO (operands
[i
])
5794 : REGNO (SUBREG_REG (operands
[i
])));
5799 if (base_reg
!= (int) REGNO (reg
))
5800 /* Not addressed from the same base register. */
5803 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5804 ? REGNO (operands
[i
])
5805 : REGNO (SUBREG_REG (operands
[i
])));
5806 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5810 /* If it isn't an integer register, or if it overwrites the
5811 base register but isn't the last insn in the list, then
5812 we can't do this. */
5813 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5814 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5817 unsorted_offsets
[i
] = INTVAL (offset
);
5820 /* Not a suitable memory address. */
5824 /* All the useful information has now been extracted from the
5825 operands into unsorted_regs and unsorted_offsets; additionally,
5826 order[0] has been set to the lowest numbered register in the
5827 list. Sort the registers into order, and check that the memory
5828 offsets are ascending and adjacent. */
5830 for (i
= 1; i
< nops
; i
++)
5834 order
[i
] = order
[i
- 1];
5835 for (j
= 0; j
< nops
; j
++)
5836 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5837 && (order
[i
] == order
[i
- 1]
5838 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5841 /* Have we found a suitable register? if not, one must be used more
5843 if (order
[i
] == order
[i
- 1])
5846 /* Is the memory address adjacent and ascending? */
5847 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5855 for (i
= 0; i
< nops
; i
++)
5856 regs
[i
] = unsorted_regs
[order
[i
]];
5858 *load_offset
= unsorted_offsets
[order
[0]];
5861 if (unsorted_offsets
[order
[0]] == 0)
5862 return 1; /* ldmia */
5864 if (unsorted_offsets
[order
[0]] == 4)
5865 return 2; /* ldmib */
5867 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5868 return 3; /* ldmda */
5870 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5871 return 4; /* ldmdb */
5873 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5874 if the offset isn't small enough. The reason 2 ldrs are faster
5875 is because these ARMs are able to do more than one cache access
5876 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5877 whilst the ARM8 has a double bandwidth cache. This means that
5878 these cores can do both an instruction fetch and a data fetch in
5879 a single cycle, so the trick of calculating the address into a
5880 scratch register (one of the result regs) and then doing a load
5881 multiple actually becomes slower (and no smaller in code size).
5882 That is the transformation
5884 ldr rd1, [rbase + offset]
5885 ldr rd2, [rbase + offset + 4]
5889 add rd1, rbase, offset
5890 ldmia rd1, {rd1, rd2}
5892 produces worse code -- '3 cycles + any stalls on rd2' instead of
5893 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5894 access per cycle, the first sequence could never complete in less
5895 than 6 cycles, whereas the ldm sequence would only take 5 and
5896 would make better use of sequential accesses if not hitting the
5899 We cheat here and test 'arm_ld_sched' which we currently know to
5900 only be true for the ARM8, ARM9 and StrongARM. If this ever
5901 changes, then the test below needs to be reworked. */
5902 if (nops
== 2 && arm_ld_sched
)
5905 /* Can't do it without setting up the offset, only do this if it takes
5906 no more than one insn. */
5907 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5908 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5912 emit_ldm_seq (rtx
*operands
, int nops
)
5916 HOST_WIDE_INT offset
;
5920 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5923 strcpy (buf
, "ldm%?ia\t");
5927 strcpy (buf
, "ldm%?ib\t");
5931 strcpy (buf
, "ldm%?da\t");
5935 strcpy (buf
, "ldm%?db\t");
5940 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5941 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5944 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5945 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5947 output_asm_insn (buf
, operands
);
5949 strcpy (buf
, "ldm%?ia\t");
5956 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5957 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5959 for (i
= 1; i
< nops
; i
++)
5960 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5961 reg_names
[regs
[i
]]);
5963 strcat (buf
, "}\t%@ phole ldm");
5965 output_asm_insn (buf
, operands
);
5970 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5971 HOST_WIDE_INT
* load_offset
)
5973 int unsorted_regs
[4];
5974 HOST_WIDE_INT unsorted_offsets
[4];
5979 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5980 extended if required. */
5981 gcc_assert (nops
>= 2 && nops
<= 4);
5983 /* Loop over the operands and check that the memory references are
5984 suitable (i.e. immediate offsets from the same base register). At
5985 the same time, extract the target register, and the memory
5987 for (i
= 0; i
< nops
; i
++)
5992 /* Convert a subreg of a mem into the mem itself. */
5993 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5994 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5996 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5998 /* Don't reorder volatile memory references; it doesn't seem worth
5999 looking for the case where the order is ok anyway. */
6000 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6003 offset
= const0_rtx
;
6005 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6006 || (GET_CODE (reg
) == SUBREG
6007 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6008 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6009 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6011 || (GET_CODE (reg
) == SUBREG
6012 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6013 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6018 base_reg
= REGNO (reg
);
6019 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6020 ? REGNO (operands
[i
])
6021 : REGNO (SUBREG_REG (operands
[i
])));
6026 if (base_reg
!= (int) REGNO (reg
))
6027 /* Not addressed from the same base register. */
6030 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6031 ? REGNO (operands
[i
])
6032 : REGNO (SUBREG_REG (operands
[i
])));
6033 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6037 /* If it isn't an integer register, then we can't do this. */
6038 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6041 unsorted_offsets
[i
] = INTVAL (offset
);
6044 /* Not a suitable memory address. */
6048 /* All the useful information has now been extracted from the
6049 operands into unsorted_regs and unsorted_offsets; additionally,
6050 order[0] has been set to the lowest numbered register in the
6051 list. Sort the registers into order, and check that the memory
6052 offsets are ascending and adjacent. */
6054 for (i
= 1; i
< nops
; i
++)
6058 order
[i
] = order
[i
- 1];
6059 for (j
= 0; j
< nops
; j
++)
6060 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6061 && (order
[i
] == order
[i
- 1]
6062 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6065 /* Have we found a suitable register? if not, one must be used more
6067 if (order
[i
] == order
[i
- 1])
6070 /* Is the memory address adjacent and ascending? */
6071 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6079 for (i
= 0; i
< nops
; i
++)
6080 regs
[i
] = unsorted_regs
[order
[i
]];
6082 *load_offset
= unsorted_offsets
[order
[0]];
6085 if (unsorted_offsets
[order
[0]] == 0)
6086 return 1; /* stmia */
6088 if (unsorted_offsets
[order
[0]] == 4)
6089 return 2; /* stmib */
6091 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6092 return 3; /* stmda */
6094 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6095 return 4; /* stmdb */
6101 emit_stm_seq (rtx
*operands
, int nops
)
6105 HOST_WIDE_INT offset
;
6109 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6112 strcpy (buf
, "stm%?ia\t");
6116 strcpy (buf
, "stm%?ib\t");
6120 strcpy (buf
, "stm%?da\t");
6124 strcpy (buf
, "stm%?db\t");
6131 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6132 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6134 for (i
= 1; i
< nops
; i
++)
6135 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6136 reg_names
[regs
[i
]]);
6138 strcat (buf
, "}\t%@ phole stm");
6140 output_asm_insn (buf
, operands
);
6144 /* Routines for use in generating RTL. */
6147 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6148 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6150 HOST_WIDE_INT offset
= *offsetp
;
6153 int sign
= up
? 1 : -1;
6156 /* XScale has load-store double instructions, but they have stricter
6157 alignment requirements than load-store multiple, so we cannot
6160 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6161 the pipeline until completion.
6169 An ldr instruction takes 1-3 cycles, but does not block the
6178 Best case ldr will always win. However, the more ldr instructions
6179 we issue, the less likely we are to be able to schedule them well.
6180 Using ldr instructions also increases code size.
6182 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6183 for counts of 3 or 4 regs. */
6184 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6190 for (i
= 0; i
< count
; i
++)
6192 addr
= plus_constant (from
, i
* 4 * sign
);
6193 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6194 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6200 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6210 result
= gen_rtx_PARALLEL (VOIDmode
,
6211 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6214 XVECEXP (result
, 0, 0)
6215 = gen_rtx_SET (GET_MODE (from
), from
,
6216 plus_constant (from
, count
* 4 * sign
));
6221 for (j
= 0; i
< count
; i
++, j
++)
6223 addr
= plus_constant (from
, j
* 4 * sign
);
6224 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6225 XVECEXP (result
, 0, i
)
6226 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6237 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6238 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6240 HOST_WIDE_INT offset
= *offsetp
;
6243 int sign
= up
? 1 : -1;
6246 /* See arm_gen_load_multiple for discussion of
6247 the pros/cons of ldm/stm usage for XScale. */
6248 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6254 for (i
= 0; i
< count
; i
++)
6256 addr
= plus_constant (to
, i
* 4 * sign
);
6257 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6258 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6264 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6274 result
= gen_rtx_PARALLEL (VOIDmode
,
6275 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6278 XVECEXP (result
, 0, 0)
6279 = gen_rtx_SET (GET_MODE (to
), to
,
6280 plus_constant (to
, count
* 4 * sign
));
6285 for (j
= 0; i
< count
; i
++, j
++)
6287 addr
= plus_constant (to
, j
* 4 * sign
);
6288 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6289 XVECEXP (result
, 0, i
)
6290 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6301 arm_gen_movmemqi (rtx
*operands
)
6303 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6304 HOST_WIDE_INT srcoffset
, dstoffset
;
6306 rtx src
, dst
, srcbase
, dstbase
;
6307 rtx part_bytes_reg
= NULL
;
6310 if (GET_CODE (operands
[2]) != CONST_INT
6311 || GET_CODE (operands
[3]) != CONST_INT
6312 || INTVAL (operands
[2]) > 64
6313 || INTVAL (operands
[3]) & 3)
6316 dstbase
= operands
[0];
6317 srcbase
= operands
[1];
6319 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6320 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6322 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6323 out_words_to_go
= INTVAL (operands
[2]) / 4;
6324 last_bytes
= INTVAL (operands
[2]) & 3;
6325 dstoffset
= srcoffset
= 0;
6327 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6328 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6330 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6332 if (in_words_to_go
> 4)
6333 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6334 srcbase
, &srcoffset
));
6336 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6337 FALSE
, srcbase
, &srcoffset
));
6339 if (out_words_to_go
)
6341 if (out_words_to_go
> 4)
6342 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6343 dstbase
, &dstoffset
));
6344 else if (out_words_to_go
!= 1)
6345 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6349 dstbase
, &dstoffset
));
6352 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6353 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6354 if (last_bytes
!= 0)
6356 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6362 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6363 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6366 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6367 if (out_words_to_go
)
6371 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6372 sreg
= copy_to_reg (mem
);
6374 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6375 emit_move_insn (mem
, sreg
);
6378 gcc_assert (!in_words_to_go
); /* Sanity check */
6383 gcc_assert (in_words_to_go
> 0);
6385 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6386 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6389 gcc_assert (!last_bytes
|| part_bytes_reg
);
6391 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6393 rtx tmp
= gen_reg_rtx (SImode
);
6395 /* The bytes we want are in the top end of the word. */
6396 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6397 GEN_INT (8 * (4 - last_bytes
))));
6398 part_bytes_reg
= tmp
;
6402 mem
= adjust_automodify_address (dstbase
, QImode
,
6403 plus_constant (dst
, last_bytes
- 1),
6404 dstoffset
+ last_bytes
- 1);
6405 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6409 tmp
= gen_reg_rtx (SImode
);
6410 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6411 part_bytes_reg
= tmp
;
6420 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6421 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6425 rtx tmp
= gen_reg_rtx (SImode
);
6426 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6427 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6428 part_bytes_reg
= tmp
;
6435 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6436 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6443 /* Select a dominance comparison mode if possible for a test of the general
6444 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6445 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6446 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6447 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6448 In all cases OP will be either EQ or NE, but we don't need to know which
6449 here. If we are unable to support a dominance comparison we return
6450 CC mode. This will then fail to match for the RTL expressions that
6451 generate this call. */
6453 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6455 enum rtx_code cond1
, cond2
;
6458 /* Currently we will probably get the wrong result if the individual
6459 comparisons are not simple. This also ensures that it is safe to
6460 reverse a comparison if necessary. */
6461 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6463 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6467 /* The if_then_else variant of this tests the second condition if the
6468 first passes, but is true if the first fails. Reverse the first
6469 condition to get a true "inclusive-or" expression. */
6470 if (cond_or
== DOM_CC_NX_OR_Y
)
6471 cond1
= reverse_condition (cond1
);
6473 /* If the comparisons are not equal, and one doesn't dominate the other,
6474 then we can't do this. */
6476 && !comparison_dominates_p (cond1
, cond2
)
6477 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6482 enum rtx_code temp
= cond1
;
6490 if (cond_or
== DOM_CC_X_AND_Y
)
6495 case EQ
: return CC_DEQmode
;
6496 case LE
: return CC_DLEmode
;
6497 case LEU
: return CC_DLEUmode
;
6498 case GE
: return CC_DGEmode
;
6499 case GEU
: return CC_DGEUmode
;
6500 default: gcc_unreachable ();
6504 if (cond_or
== DOM_CC_X_AND_Y
)
6520 if (cond_or
== DOM_CC_X_AND_Y
)
6536 if (cond_or
== DOM_CC_X_AND_Y
)
6552 if (cond_or
== DOM_CC_X_AND_Y
)
6567 /* The remaining cases only occur when both comparisons are the
6570 gcc_assert (cond1
== cond2
);
6574 gcc_assert (cond1
== cond2
);
6578 gcc_assert (cond1
== cond2
);
6582 gcc_assert (cond1
== cond2
);
6586 gcc_assert (cond1
== cond2
);
6595 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6597 /* All floating point compares return CCFP if it is an equality
6598 comparison, and CCFPE otherwise. */
6599 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6619 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6628 /* A compare with a shifted operand. Because of canonicalization, the
6629 comparison will have to be swapped when we emit the assembler. */
6630 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6631 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6632 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6633 || GET_CODE (x
) == ROTATERT
))
6636 /* This operation is performed swapped, but since we only rely on the Z
6637 flag we don't need an additional mode. */
6638 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6639 && GET_CODE (x
) == NEG
6640 && (op
== EQ
|| op
== NE
))
6643 /* This is a special case that is used by combine to allow a
6644 comparison of a shifted byte load to be split into a zero-extend
6645 followed by a comparison of the shifted integer (only valid for
6646 equalities and unsigned inequalities). */
6647 if (GET_MODE (x
) == SImode
6648 && GET_CODE (x
) == ASHIFT
6649 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6650 && GET_CODE (XEXP (x
, 0)) == SUBREG
6651 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6652 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6653 && (op
== EQ
|| op
== NE
6654 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6655 && GET_CODE (y
) == CONST_INT
)
6658 /* A construct for a conditional compare, if the false arm contains
6659 0, then both conditions must be true, otherwise either condition
6660 must be true. Not all conditions are possible, so CCmode is
6661 returned if it can't be done. */
6662 if (GET_CODE (x
) == IF_THEN_ELSE
6663 && (XEXP (x
, 2) == const0_rtx
6664 || XEXP (x
, 2) == const1_rtx
)
6665 && COMPARISON_P (XEXP (x
, 0))
6666 && COMPARISON_P (XEXP (x
, 1)))
6667 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6668 INTVAL (XEXP (x
, 2)));
6670 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6671 if (GET_CODE (x
) == AND
6672 && COMPARISON_P (XEXP (x
, 0))
6673 && COMPARISON_P (XEXP (x
, 1)))
6674 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6677 if (GET_CODE (x
) == IOR
6678 && COMPARISON_P (XEXP (x
, 0))
6679 && COMPARISON_P (XEXP (x
, 1)))
6680 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6683 /* An operation (on Thumb) where we want to test for a single bit.
6684 This is done by shifting that bit up into the top bit of a
6685 scratch register; we can then branch on the sign bit. */
6687 && GET_MODE (x
) == SImode
6688 && (op
== EQ
|| op
== NE
)
6689 && (GET_CODE (x
) == ZERO_EXTRACT
))
6692 /* An operation that sets the condition codes as a side-effect, the
6693 V flag is not set correctly, so we can only use comparisons where
6694 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6696 if (GET_MODE (x
) == SImode
6698 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6699 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6700 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6701 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6702 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6703 || GET_CODE (x
) == LSHIFTRT
6704 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6705 || GET_CODE (x
) == ROTATERT
6706 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6709 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6712 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6713 && GET_CODE (x
) == PLUS
6714 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6720 /* X and Y are two things to compare using CODE. Emit the compare insn and
6721 return the rtx for register 0 in the proper mode. FP means this is a
6722 floating point compare: I don't think that it is needed on the arm. */
6724 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6726 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6727 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6729 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6730 gen_rtx_COMPARE (mode
, x
, y
)));
6735 /* Generate a sequence of insns that will generate the correct return
6736 address mask depending on the physical architecture that the program
6739 arm_gen_return_addr_mask (void)
6741 rtx reg
= gen_reg_rtx (Pmode
);
6743 emit_insn (gen_return_addr_mask (reg
));
6748 arm_reload_in_hi (rtx
*operands
)
6750 rtx ref
= operands
[1];
6752 HOST_WIDE_INT offset
= 0;
6754 if (GET_CODE (ref
) == SUBREG
)
6756 offset
= SUBREG_BYTE (ref
);
6757 ref
= SUBREG_REG (ref
);
6760 if (GET_CODE (ref
) == REG
)
6762 /* We have a pseudo which has been spilt onto the stack; there
6763 are two cases here: the first where there is a simple
6764 stack-slot replacement and a second where the stack-slot is
6765 out of range, or is used as a subreg. */
6766 if (reg_equiv_mem
[REGNO (ref
)])
6768 ref
= reg_equiv_mem
[REGNO (ref
)];
6769 base
= find_replacement (&XEXP (ref
, 0));
6772 /* The slot is out of range, or was dressed up in a SUBREG. */
6773 base
= reg_equiv_address
[REGNO (ref
)];
6776 base
= find_replacement (&XEXP (ref
, 0));
6778 /* Handle the case where the address is too complex to be offset by 1. */
6779 if (GET_CODE (base
) == MINUS
6780 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6782 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6784 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6787 else if (GET_CODE (base
) == PLUS
)
6789 /* The addend must be CONST_INT, or we would have dealt with it above. */
6790 HOST_WIDE_INT hi
, lo
;
6792 offset
+= INTVAL (XEXP (base
, 1));
6793 base
= XEXP (base
, 0);
6795 /* Rework the address into a legal sequence of insns. */
6796 /* Valid range for lo is -4095 -> 4095 */
6799 : -((-offset
) & 0xfff));
6801 /* Corner case, if lo is the max offset then we would be out of range
6802 once we have added the additional 1 below, so bump the msb into the
6803 pre-loading insn(s). */
6807 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6808 ^ (HOST_WIDE_INT
) 0x80000000)
6809 - (HOST_WIDE_INT
) 0x80000000);
6811 gcc_assert (hi
+ lo
== offset
);
6815 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6817 /* Get the base address; addsi3 knows how to handle constants
6818 that require more than one insn. */
6819 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6825 /* Operands[2] may overlap operands[0] (though it won't overlap
6826 operands[1]), that's why we asked for a DImode reg -- so we can
6827 use the bit that does not overlap. */
6828 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6829 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6831 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6833 emit_insn (gen_zero_extendqisi2 (scratch
,
6834 gen_rtx_MEM (QImode
,
6835 plus_constant (base
,
6837 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6838 gen_rtx_MEM (QImode
,
6839 plus_constant (base
,
6841 if (!BYTES_BIG_ENDIAN
)
6842 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6843 gen_rtx_IOR (SImode
,
6846 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6850 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6851 gen_rtx_IOR (SImode
,
6852 gen_rtx_ASHIFT (SImode
, scratch
,
6854 gen_rtx_SUBREG (SImode
, operands
[0],
6858 /* Handle storing a half-word to memory during reload by synthesizing as two
6859 byte stores. Take care not to clobber the input values until after we
6860 have moved them somewhere safe. This code assumes that if the DImode
6861 scratch in operands[2] overlaps either the input value or output address
6862 in some way, then that value must die in this insn (we absolutely need
6863 two scratch registers for some corner cases). */
6865 arm_reload_out_hi (rtx
*operands
)
6867 rtx ref
= operands
[0];
6868 rtx outval
= operands
[1];
6870 HOST_WIDE_INT offset
= 0;
6872 if (GET_CODE (ref
) == SUBREG
)
6874 offset
= SUBREG_BYTE (ref
);
6875 ref
= SUBREG_REG (ref
);
6878 if (GET_CODE (ref
) == REG
)
6880 /* We have a pseudo which has been spilt onto the stack; there
6881 are two cases here: the first where there is a simple
6882 stack-slot replacement and a second where the stack-slot is
6883 out of range, or is used as a subreg. */
6884 if (reg_equiv_mem
[REGNO (ref
)])
6886 ref
= reg_equiv_mem
[REGNO (ref
)];
6887 base
= find_replacement (&XEXP (ref
, 0));
6890 /* The slot is out of range, or was dressed up in a SUBREG. */
6891 base
= reg_equiv_address
[REGNO (ref
)];
6894 base
= find_replacement (&XEXP (ref
, 0));
6896 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6898 /* Handle the case where the address is too complex to be offset by 1. */
6899 if (GET_CODE (base
) == MINUS
6900 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6902 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6904 /* Be careful not to destroy OUTVAL. */
6905 if (reg_overlap_mentioned_p (base_plus
, outval
))
6907 /* Updating base_plus might destroy outval, see if we can
6908 swap the scratch and base_plus. */
6909 if (!reg_overlap_mentioned_p (scratch
, outval
))
6912 scratch
= base_plus
;
6917 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6919 /* Be conservative and copy OUTVAL into the scratch now,
6920 this should only be necessary if outval is a subreg
6921 of something larger than a word. */
6922 /* XXX Might this clobber base? I can't see how it can,
6923 since scratch is known to overlap with OUTVAL, and
6924 must be wider than a word. */
6925 emit_insn (gen_movhi (scratch_hi
, outval
));
6926 outval
= scratch_hi
;
6930 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6933 else if (GET_CODE (base
) == PLUS
)
6935 /* The addend must be CONST_INT, or we would have dealt with it above. */
6936 HOST_WIDE_INT hi
, lo
;
6938 offset
+= INTVAL (XEXP (base
, 1));
6939 base
= XEXP (base
, 0);
6941 /* Rework the address into a legal sequence of insns. */
6942 /* Valid range for lo is -4095 -> 4095 */
6945 : -((-offset
) & 0xfff));
6947 /* Corner case, if lo is the max offset then we would be out of range
6948 once we have added the additional 1 below, so bump the msb into the
6949 pre-loading insn(s). */
6953 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6954 ^ (HOST_WIDE_INT
) 0x80000000)
6955 - (HOST_WIDE_INT
) 0x80000000);
6957 gcc_assert (hi
+ lo
== offset
);
6961 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6963 /* Be careful not to destroy OUTVAL. */
6964 if (reg_overlap_mentioned_p (base_plus
, outval
))
6966 /* Updating base_plus might destroy outval, see if we
6967 can swap the scratch and base_plus. */
6968 if (!reg_overlap_mentioned_p (scratch
, outval
))
6971 scratch
= base_plus
;
6976 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6978 /* Be conservative and copy outval into scratch now,
6979 this should only be necessary if outval is a
6980 subreg of something larger than a word. */
6981 /* XXX Might this clobber base? I can't see how it
6982 can, since scratch is known to overlap with
6984 emit_insn (gen_movhi (scratch_hi
, outval
));
6985 outval
= scratch_hi
;
6989 /* Get the base address; addsi3 knows how to handle constants
6990 that require more than one insn. */
6991 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6997 if (BYTES_BIG_ENDIAN
)
6999 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7000 plus_constant (base
, offset
+ 1)),
7001 gen_lowpart (QImode
, outval
)));
7002 emit_insn (gen_lshrsi3 (scratch
,
7003 gen_rtx_SUBREG (SImode
, outval
, 0),
7005 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7006 gen_lowpart (QImode
, scratch
)));
7010 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7011 gen_lowpart (QImode
, outval
)));
7012 emit_insn (gen_lshrsi3 (scratch
,
7013 gen_rtx_SUBREG (SImode
, outval
, 0),
7015 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7016 plus_constant (base
, offset
+ 1)),
7017 gen_lowpart (QImode
, scratch
)));
7021 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7022 (padded to the size of a word) should be passed in a register. */
7025 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7027 if (TARGET_AAPCS_BASED
)
7028 return must_pass_in_stack_var_size (mode
, type
);
7030 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7034 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7035 Return true if an argument passed on the stack should be padded upwards,
7036 i.e. if the least-significant byte has useful data.
7037 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7038 aggregate types are placed in the lowest memory address. */
7041 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7043 if (!TARGET_AAPCS_BASED
)
7044 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7046 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7053 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7054 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7055 byte of the register has useful data, and return the opposite if the
7056 most significant byte does.
7057 For AAPCS, small aggregates and small complex types are always padded
7061 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7062 tree type
, int first ATTRIBUTE_UNUSED
)
7064 if (TARGET_AAPCS_BASED
7066 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7067 && int_size_in_bytes (type
) <= 4)
7070 /* Otherwise, use default padding. */
7071 return !BYTES_BIG_ENDIAN
;
7075 /* Print a symbolic form of X to the debug file, F. */
7077 arm_print_value (FILE *f
, rtx x
)
7079 switch (GET_CODE (x
))
7082 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7086 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7094 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7096 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7097 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7105 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7109 fprintf (f
, "`%s'", XSTR (x
, 0));
7113 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7117 arm_print_value (f
, XEXP (x
, 0));
7121 arm_print_value (f
, XEXP (x
, 0));
7123 arm_print_value (f
, XEXP (x
, 1));
7131 fprintf (f
, "????");
7136 /* Routines for manipulation of the constant pool. */
7138 /* Arm instructions cannot load a large constant directly into a
7139 register; they have to come from a pc relative load. The constant
7140 must therefore be placed in the addressable range of the pc
7141 relative load. Depending on the precise pc relative load
7142 instruction the range is somewhere between 256 bytes and 4k. This
7143 means that we often have to dump a constant inside a function, and
7144 generate code to branch around it.
7146 It is important to minimize this, since the branches will slow
7147 things down and make the code larger.
7149 Normally we can hide the table after an existing unconditional
7150 branch so that there is no interruption of the flow, but in the
7151 worst case the code looks like this:
7169 We fix this by performing a scan after scheduling, which notices
7170 which instructions need to have their operands fetched from the
7171 constant table and builds the table.
7173 The algorithm starts by building a table of all the constants that
7174 need fixing up and all the natural barriers in the function (places
7175 where a constant table can be dropped without breaking the flow).
7176 For each fixup we note how far the pc-relative replacement will be
7177 able to reach and the offset of the instruction into the function.
7179 Having built the table we then group the fixes together to form
7180 tables that are as large as possible (subject to addressing
7181 constraints) and emit each table of constants after the last
7182 barrier that is within range of all the instructions in the group.
7183 If a group does not contain a barrier, then we forcibly create one
7184 by inserting a jump instruction into the flow. Once the table has
7185 been inserted, the insns are then modified to reference the
7186 relevant entry in the pool.
7188 Possible enhancements to the algorithm (not implemented) are:
7190 1) For some processors and object formats, there may be benefit in
7191 aligning the pools to the start of cache lines; this alignment
7192 would need to be taken into account when calculating addressability
7195 /* These typedefs are located at the start of this file, so that
7196 they can be used in the prototypes there. This comment is to
7197 remind readers of that fact so that the following structures
7198 can be understood more easily.
7200 typedef struct minipool_node Mnode;
7201 typedef struct minipool_fixup Mfix; */
7203 struct minipool_node
7205 /* Doubly linked chain of entries. */
7208 /* The maximum offset into the code that this entry can be placed. While
7209 pushing fixes for forward references, all entries are sorted in order
7210 of increasing max_address. */
7211 HOST_WIDE_INT max_address
;
7212 /* Similarly for an entry inserted for a backwards ref. */
7213 HOST_WIDE_INT min_address
;
7214 /* The number of fixes referencing this entry. This can become zero
7215 if we "unpush" an entry. In this case we ignore the entry when we
7216 come to emit the code. */
7218 /* The offset from the start of the minipool. */
7219 HOST_WIDE_INT offset
;
7220 /* The value in table. */
7222 /* The mode of value. */
7223 enum machine_mode mode
;
7224 /* The size of the value. With iWMMXt enabled
7225 sizes > 4 also imply an alignment of 8-bytes. */
7229 struct minipool_fixup
7233 HOST_WIDE_INT address
;
7235 enum machine_mode mode
;
7239 HOST_WIDE_INT forwards
;
7240 HOST_WIDE_INT backwards
;
7243 /* Fixes less than a word need padding out to a word boundary. */
7244 #define MINIPOOL_FIX_SIZE(mode) \
7245 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7247 static Mnode
* minipool_vector_head
;
7248 static Mnode
* minipool_vector_tail
;
7249 static rtx minipool_vector_label
;
7251 /* The linked list of all minipool fixes required for this function. */
7252 Mfix
* minipool_fix_head
;
7253 Mfix
* minipool_fix_tail
;
7254 /* The fix entry for the current minipool, once it has been placed. */
7255 Mfix
* minipool_barrier
;
7257 /* Determines if INSN is the start of a jump table. Returns the end
7258 of the TABLE or NULL_RTX. */
7260 is_jump_table (rtx insn
)
7264 if (GET_CODE (insn
) == JUMP_INSN
7265 && JUMP_LABEL (insn
) != NULL
7266 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7267 == next_real_insn (insn
))
7269 && GET_CODE (table
) == JUMP_INSN
7270 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7271 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7277 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7278 #define JUMP_TABLES_IN_TEXT_SECTION 0
7281 static HOST_WIDE_INT
7282 get_jump_table_size (rtx insn
)
7284 /* ADDR_VECs only take room if read-only data does into the text
7286 if (JUMP_TABLES_IN_TEXT_SECTION
7287 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
7292 rtx body
= PATTERN (insn
);
7293 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7295 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7301 /* Move a minipool fix MP from its current location to before MAX_MP.
7302 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7303 constraints may need updating. */
7305 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7306 HOST_WIDE_INT max_address
)
7308 /* The code below assumes these are different. */
7309 gcc_assert (mp
!= max_mp
);
7313 if (max_address
< mp
->max_address
)
7314 mp
->max_address
= max_address
;
7318 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7319 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7321 mp
->max_address
= max_address
;
7323 /* Unlink MP from its current position. Since max_mp is non-null,
7324 mp->prev must be non-null. */
7325 mp
->prev
->next
= mp
->next
;
7326 if (mp
->next
!= NULL
)
7327 mp
->next
->prev
= mp
->prev
;
7329 minipool_vector_tail
= mp
->prev
;
7331 /* Re-insert it before MAX_MP. */
7333 mp
->prev
= max_mp
->prev
;
7336 if (mp
->prev
!= NULL
)
7337 mp
->prev
->next
= mp
;
7339 minipool_vector_head
= mp
;
7342 /* Save the new entry. */
7345 /* Scan over the preceding entries and adjust their addresses as
7347 while (mp
->prev
!= NULL
7348 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7350 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7357 /* Add a constant to the minipool for a forward reference. Returns the
7358 node added or NULL if the constant will not fit in this pool. */
7360 add_minipool_forward_ref (Mfix
*fix
)
7362 /* If set, max_mp is the first pool_entry that has a lower
7363 constraint than the one we are trying to add. */
7364 Mnode
* max_mp
= NULL
;
7365 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7368 /* If this fix's address is greater than the address of the first
7369 entry, then we can't put the fix in this pool. We subtract the
7370 size of the current fix to ensure that if the table is fully
7371 packed we still have enough room to insert this value by shuffling
7372 the other fixes forwards. */
7373 if (minipool_vector_head
&&
7374 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7377 /* Scan the pool to see if a constant with the same value has
7378 already been added. While we are doing this, also note the
7379 location where we must insert the constant if it doesn't already
7381 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7383 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7384 && fix
->mode
== mp
->mode
7385 && (GET_CODE (fix
->value
) != CODE_LABEL
7386 || (CODE_LABEL_NUMBER (fix
->value
)
7387 == CODE_LABEL_NUMBER (mp
->value
)))
7388 && rtx_equal_p (fix
->value
, mp
->value
))
7390 /* More than one fix references this entry. */
7392 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7395 /* Note the insertion point if necessary. */
7397 && mp
->max_address
> max_address
)
7400 /* If we are inserting an 8-bytes aligned quantity and
7401 we have not already found an insertion point, then
7402 make sure that all such 8-byte aligned quantities are
7403 placed at the start of the pool. */
7404 if (ARM_DOUBLEWORD_ALIGN
7406 && fix
->fix_size
== 8
7407 && mp
->fix_size
!= 8)
7410 max_address
= mp
->max_address
;
7414 /* The value is not currently in the minipool, so we need to create
7415 a new entry for it. If MAX_MP is NULL, the entry will be put on
7416 the end of the list since the placement is less constrained than
7417 any existing entry. Otherwise, we insert the new fix before
7418 MAX_MP and, if necessary, adjust the constraints on the other
7420 mp
= xmalloc (sizeof (* mp
));
7421 mp
->fix_size
= fix
->fix_size
;
7422 mp
->mode
= fix
->mode
;
7423 mp
->value
= fix
->value
;
7425 /* Not yet required for a backwards ref. */
7426 mp
->min_address
= -65536;
7430 mp
->max_address
= max_address
;
7432 mp
->prev
= minipool_vector_tail
;
7434 if (mp
->prev
== NULL
)
7436 minipool_vector_head
= mp
;
7437 minipool_vector_label
= gen_label_rtx ();
7440 mp
->prev
->next
= mp
;
7442 minipool_vector_tail
= mp
;
7446 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7447 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7449 mp
->max_address
= max_address
;
7452 mp
->prev
= max_mp
->prev
;
7454 if (mp
->prev
!= NULL
)
7455 mp
->prev
->next
= mp
;
7457 minipool_vector_head
= mp
;
7460 /* Save the new entry. */
7463 /* Scan over the preceding entries and adjust their addresses as
7465 while (mp
->prev
!= NULL
7466 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7468 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7476 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7477 HOST_WIDE_INT min_address
)
7479 HOST_WIDE_INT offset
;
7481 /* The code below assumes these are different. */
7482 gcc_assert (mp
!= min_mp
);
7486 if (min_address
> mp
->min_address
)
7487 mp
->min_address
= min_address
;
7491 /* We will adjust this below if it is too loose. */
7492 mp
->min_address
= min_address
;
7494 /* Unlink MP from its current position. Since min_mp is non-null,
7495 mp->next must be non-null. */
7496 mp
->next
->prev
= mp
->prev
;
7497 if (mp
->prev
!= NULL
)
7498 mp
->prev
->next
= mp
->next
;
7500 minipool_vector_head
= mp
->next
;
7502 /* Reinsert it after MIN_MP. */
7504 mp
->next
= min_mp
->next
;
7506 if (mp
->next
!= NULL
)
7507 mp
->next
->prev
= mp
;
7509 minipool_vector_tail
= mp
;
7515 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7517 mp
->offset
= offset
;
7518 if (mp
->refcount
> 0)
7519 offset
+= mp
->fix_size
;
7521 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7522 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7528 /* Add a constant to the minipool for a backward reference. Returns the
7529 node added or NULL if the constant will not fit in this pool.
7531 Note that the code for insertion for a backwards reference can be
7532 somewhat confusing because the calculated offsets for each fix do
7533 not take into account the size of the pool (which is still under
7536 add_minipool_backward_ref (Mfix
*fix
)
7538 /* If set, min_mp is the last pool_entry that has a lower constraint
7539 than the one we are trying to add. */
7540 Mnode
*min_mp
= NULL
;
7541 /* This can be negative, since it is only a constraint. */
7542 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7545 /* If we can't reach the current pool from this insn, or if we can't
7546 insert this entry at the end of the pool without pushing other
7547 fixes out of range, then we don't try. This ensures that we
7548 can't fail later on. */
7549 if (min_address
>= minipool_barrier
->address
7550 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7551 >= minipool_barrier
->address
))
7554 /* Scan the pool to see if a constant with the same value has
7555 already been added. While we are doing this, also note the
7556 location where we must insert the constant if it doesn't already
7558 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7560 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7561 && fix
->mode
== mp
->mode
7562 && (GET_CODE (fix
->value
) != CODE_LABEL
7563 || (CODE_LABEL_NUMBER (fix
->value
)
7564 == CODE_LABEL_NUMBER (mp
->value
)))
7565 && rtx_equal_p (fix
->value
, mp
->value
)
7566 /* Check that there is enough slack to move this entry to the
7567 end of the table (this is conservative). */
7569 > (minipool_barrier
->address
7570 + minipool_vector_tail
->offset
7571 + minipool_vector_tail
->fix_size
)))
7574 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7578 mp
->min_address
+= fix
->fix_size
;
7581 /* Note the insertion point if necessary. */
7582 if (mp
->min_address
< min_address
)
7584 /* For now, we do not allow the insertion of 8-byte alignment
7585 requiring nodes anywhere but at the start of the pool. */
7586 if (ARM_DOUBLEWORD_ALIGN
7587 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7592 else if (mp
->max_address
7593 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7595 /* Inserting before this entry would push the fix beyond
7596 its maximum address (which can happen if we have
7597 re-located a forwards fix); force the new fix to come
7600 min_address
= mp
->min_address
+ fix
->fix_size
;
7602 /* If we are inserting an 8-bytes aligned quantity and
7603 we have not already found an insertion point, then
7604 make sure that all such 8-byte aligned quantities are
7605 placed at the start of the pool. */
7606 else if (ARM_DOUBLEWORD_ALIGN
7608 && fix
->fix_size
== 8
7609 && mp
->fix_size
< 8)
7612 min_address
= mp
->min_address
+ fix
->fix_size
;
7617 /* We need to create a new entry. */
7618 mp
= xmalloc (sizeof (* mp
));
7619 mp
->fix_size
= fix
->fix_size
;
7620 mp
->mode
= fix
->mode
;
7621 mp
->value
= fix
->value
;
7623 mp
->max_address
= minipool_barrier
->address
+ 65536;
7625 mp
->min_address
= min_address
;
7630 mp
->next
= minipool_vector_head
;
7632 if (mp
->next
== NULL
)
7634 minipool_vector_tail
= mp
;
7635 minipool_vector_label
= gen_label_rtx ();
7638 mp
->next
->prev
= mp
;
7640 minipool_vector_head
= mp
;
7644 mp
->next
= min_mp
->next
;
7648 if (mp
->next
!= NULL
)
7649 mp
->next
->prev
= mp
;
7651 minipool_vector_tail
= mp
;
7654 /* Save the new entry. */
7662 /* Scan over the following entries and adjust their offsets. */
7663 while (mp
->next
!= NULL
)
7665 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7666 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7669 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7671 mp
->next
->offset
= mp
->offset
;
7680 assign_minipool_offsets (Mfix
*barrier
)
7682 HOST_WIDE_INT offset
= 0;
7685 minipool_barrier
= barrier
;
7687 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7689 mp
->offset
= offset
;
7691 if (mp
->refcount
> 0)
7692 offset
+= mp
->fix_size
;
7696 /* Output the literal table */
7698 dump_minipool (rtx scan
)
7704 if (ARM_DOUBLEWORD_ALIGN
)
7705 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7706 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7714 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7715 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7717 scan
= emit_label_after (gen_label_rtx (), scan
);
7718 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7719 scan
= emit_label_after (minipool_vector_label
, scan
);
7721 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7723 if (mp
->refcount
> 0)
7728 ";; Offset %u, min %ld, max %ld ",
7729 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7730 (unsigned long) mp
->max_address
);
7731 arm_print_value (dump_file
, mp
->value
);
7732 fputc ('\n', dump_file
);
7735 switch (mp
->fix_size
)
7737 #ifdef HAVE_consttable_1
7739 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7743 #ifdef HAVE_consttable_2
7745 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7749 #ifdef HAVE_consttable_4
7751 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7755 #ifdef HAVE_consttable_8
7757 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7770 minipool_vector_head
= minipool_vector_tail
= NULL
;
7771 scan
= emit_insn_after (gen_consttable_end (), scan
);
7772 scan
= emit_barrier_after (scan
);
7775 /* Return the cost of forcibly inserting a barrier after INSN. */
7777 arm_barrier_cost (rtx insn
)
7779 /* Basing the location of the pool on the loop depth is preferable,
7780 but at the moment, the basic block information seems to be
7781 corrupt by this stage of the compilation. */
7783 rtx next
= next_nonnote_insn (insn
);
7785 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7788 switch (GET_CODE (insn
))
7791 /* It will always be better to place the table before the label, rather
7800 return base_cost
- 10;
7803 return base_cost
+ 10;
7807 /* Find the best place in the insn stream in the range
7808 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7809 Create the barrier by inserting a jump and add a new fix entry for
7812 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7814 HOST_WIDE_INT count
= 0;
7816 rtx from
= fix
->insn
;
7817 rtx selected
= from
;
7819 HOST_WIDE_INT selected_address
;
7821 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7822 rtx label
= gen_label_rtx ();
7824 selected_cost
= arm_barrier_cost (from
);
7825 selected_address
= fix
->address
;
7827 while (from
&& count
< max_count
)
7832 /* This code shouldn't have been called if there was a natural barrier
7834 gcc_assert (GET_CODE (from
) != BARRIER
);
7836 /* Count the length of this insn. */
7837 count
+= get_attr_length (from
);
7839 /* If there is a jump table, add its length. */
7840 tmp
= is_jump_table (from
);
7843 count
+= get_jump_table_size (tmp
);
7845 /* Jump tables aren't in a basic block, so base the cost on
7846 the dispatch insn. If we select this location, we will
7847 still put the pool after the table. */
7848 new_cost
= arm_barrier_cost (from
);
7850 if (count
< max_count
&& new_cost
<= selected_cost
)
7853 selected_cost
= new_cost
;
7854 selected_address
= fix
->address
+ count
;
7857 /* Continue after the dispatch table. */
7858 from
= NEXT_INSN (tmp
);
7862 new_cost
= arm_barrier_cost (from
);
7864 if (count
< max_count
&& new_cost
<= selected_cost
)
7867 selected_cost
= new_cost
;
7868 selected_address
= fix
->address
+ count
;
7871 from
= NEXT_INSN (from
);
7874 /* Create a new JUMP_INSN that branches around a barrier. */
7875 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7876 JUMP_LABEL (from
) = label
;
7877 barrier
= emit_barrier_after (from
);
7878 emit_label_after (label
, barrier
);
7880 /* Create a minipool barrier entry for the new barrier. */
7881 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7882 new_fix
->insn
= barrier
;
7883 new_fix
->address
= selected_address
;
7884 new_fix
->next
= fix
->next
;
7885 fix
->next
= new_fix
;
7890 /* Record that there is a natural barrier in the insn stream at
7893 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7895 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7898 fix
->address
= address
;
7901 if (minipool_fix_head
!= NULL
)
7902 minipool_fix_tail
->next
= fix
;
7904 minipool_fix_head
= fix
;
7906 minipool_fix_tail
= fix
;
7909 /* Record INSN, which will need fixing up to load a value from the
7910 minipool. ADDRESS is the offset of the insn since the start of the
7911 function; LOC is a pointer to the part of the insn which requires
7912 fixing; VALUE is the constant that must be loaded, which is of type
7915 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7916 enum machine_mode mode
, rtx value
)
7918 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7920 #ifdef AOF_ASSEMBLER
7921 /* PIC symbol references need to be converted into offsets into the
7923 /* XXX This shouldn't be done here. */
7924 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7925 value
= aof_pic_entry (value
);
7926 #endif /* AOF_ASSEMBLER */
7929 fix
->address
= address
;
7932 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7934 fix
->forwards
= get_attr_pool_range (insn
);
7935 fix
->backwards
= get_attr_neg_pool_range (insn
);
7936 fix
->minipool
= NULL
;
7938 /* If an insn doesn't have a range defined for it, then it isn't
7939 expecting to be reworked by this code. Better to stop now than
7940 to generate duff assembly code. */
7941 gcc_assert (fix
->forwards
|| fix
->backwards
);
7943 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7944 So there might be an empty word before the start of the pool.
7945 Hence we reduce the forward range by 4 to allow for this
7947 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7953 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7954 GET_MODE_NAME (mode
),
7955 INSN_UID (insn
), (unsigned long) address
,
7956 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7957 arm_print_value (dump_file
, fix
->value
);
7958 fprintf (dump_file
, "\n");
7961 /* Add it to the chain of fixes. */
7964 if (minipool_fix_head
!= NULL
)
7965 minipool_fix_tail
->next
= fix
;
7967 minipool_fix_head
= fix
;
7969 minipool_fix_tail
= fix
;
7972 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7973 Returns the number of insns needed, or 99 if we don't know how to
7976 arm_const_double_inline_cost (rtx val
)
7978 rtx lowpart
, highpart
;
7979 enum machine_mode mode
;
7981 mode
= GET_MODE (val
);
7983 if (mode
== VOIDmode
)
7986 gcc_assert (GET_MODE_SIZE (mode
) == 8);
7988 lowpart
= gen_lowpart (SImode
, val
);
7989 highpart
= gen_highpart_mode (SImode
, mode
, val
);
7991 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
7992 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
7994 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
7995 NULL_RTX
, NULL_RTX
, 0, 0)
7996 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
7997 NULL_RTX
, NULL_RTX
, 0, 0));
8000 /* Return true if it is worthwhile to split a 64-bit constant into two
8001 32-bit operations. This is the case if optimizing for size, or
8002 if we have load delay slots, or if one 32-bit part can be done with
8003 a single data operation. */
8005 arm_const_double_by_parts (rtx val
)
8007 enum machine_mode mode
= GET_MODE (val
);
8010 if (optimize_size
|| arm_ld_sched
)
8013 if (mode
== VOIDmode
)
8016 part
= gen_highpart_mode (SImode
, mode
, val
);
8018 gcc_assert (GET_CODE (part
) == CONST_INT
);
8020 if (const_ok_for_arm (INTVAL (part
))
8021 || const_ok_for_arm (~INTVAL (part
)))
8024 part
= gen_lowpart (SImode
, val
);
8026 gcc_assert (GET_CODE (part
) == CONST_INT
);
8028 if (const_ok_for_arm (INTVAL (part
))
8029 || const_ok_for_arm (~INTVAL (part
)))
8035 /* Scan INSN and note any of its operands that need fixing.
8036 If DO_PUSHES is false we do not actually push any of the fixups
8037 needed. The function returns TRUE if any fixups were needed/pushed.
8038 This is used by arm_memory_load_p() which needs to know about loads
8039 of constants that will be converted into minipool loads. */
8041 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8043 bool result
= false;
8046 extract_insn (insn
);
8048 if (!constrain_operands (1))
8049 fatal_insn_not_found (insn
);
8051 if (recog_data
.n_alternatives
== 0)
8054 /* Fill in recog_op_alt with information about the constraints of
8056 preprocess_constraints ();
8058 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8060 /* Things we need to fix can only occur in inputs. */
8061 if (recog_data
.operand_type
[opno
] != OP_IN
)
8064 /* If this alternative is a memory reference, then any mention
8065 of constants in this alternative is really to fool reload
8066 into allowing us to accept one there. We need to fix them up
8067 now so that we output the right code. */
8068 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8070 rtx op
= recog_data
.operand
[opno
];
8072 if (CONSTANT_P (op
))
8075 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8076 recog_data
.operand_mode
[opno
], op
);
8079 else if (GET_CODE (op
) == MEM
8080 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8081 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8085 rtx cop
= avoid_constant_pool_reference (op
);
8087 /* Casting the address of something to a mode narrower
8088 than a word can cause avoid_constant_pool_reference()
8089 to return the pool reference itself. That's no good to
8090 us here. Lets just hope that we can use the
8091 constant pool value directly. */
8093 cop
= get_pool_constant (XEXP (op
, 0));
8095 push_minipool_fix (insn
, address
,
8096 recog_data
.operand_loc
[opno
],
8097 recog_data
.operand_mode
[opno
], cop
);
8108 /* Gcc puts the pool in the wrong place for ARM, since we can only
8109 load addresses a limited distance around the pc. We do some
8110 special munging to move the constant pool values to the correct
8111 point in the code. */
8116 HOST_WIDE_INT address
= 0;
8119 minipool_fix_head
= minipool_fix_tail
= NULL
;
8121 /* The first insn must always be a note, or the code below won't
8122 scan it properly. */
8123 insn
= get_insns ();
8124 gcc_assert (GET_CODE (insn
) == NOTE
);
8126 /* Scan all the insns and record the operands that will need fixing. */
8127 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8129 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8130 && (arm_cirrus_insn_p (insn
)
8131 || GET_CODE (insn
) == JUMP_INSN
8132 || arm_memory_load_p (insn
)))
8133 cirrus_reorg (insn
);
8135 if (GET_CODE (insn
) == BARRIER
)
8136 push_minipool_barrier (insn
, address
);
8137 else if (INSN_P (insn
))
8141 note_invalid_constants (insn
, address
, true);
8142 address
+= get_attr_length (insn
);
8144 /* If the insn is a vector jump, add the size of the table
8145 and skip the table. */
8146 if ((table
= is_jump_table (insn
)) != NULL
)
8148 address
+= get_jump_table_size (table
);
8154 fix
= minipool_fix_head
;
8156 /* Now scan the fixups and perform the required changes. */
8161 Mfix
* last_added_fix
;
8162 Mfix
* last_barrier
= NULL
;
8165 /* Skip any further barriers before the next fix. */
8166 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8169 /* No more fixes. */
8173 last_added_fix
= NULL
;
8175 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8177 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8179 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8182 last_barrier
= ftmp
;
8184 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8187 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8190 /* If we found a barrier, drop back to that; any fixes that we
8191 could have reached but come after the barrier will now go in
8192 the next mini-pool. */
8193 if (last_barrier
!= NULL
)
8195 /* Reduce the refcount for those fixes that won't go into this
8197 for (fdel
= last_barrier
->next
;
8198 fdel
&& fdel
!= ftmp
;
8201 fdel
->minipool
->refcount
--;
8202 fdel
->minipool
= NULL
;
8205 ftmp
= last_barrier
;
8209 /* ftmp is first fix that we can't fit into this pool and
8210 there no natural barriers that we could use. Insert a
8211 new barrier in the code somewhere between the previous
8212 fix and this one, and arrange to jump around it. */
8213 HOST_WIDE_INT max_address
;
8215 /* The last item on the list of fixes must be a barrier, so
8216 we can never run off the end of the list of fixes without
8217 last_barrier being set. */
8220 max_address
= minipool_vector_head
->max_address
;
8221 /* Check that there isn't another fix that is in range that
8222 we couldn't fit into this pool because the pool was
8223 already too large: we need to put the pool before such an
8225 if (ftmp
->address
< max_address
)
8226 max_address
= ftmp
->address
;
8228 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8231 assign_minipool_offsets (last_barrier
);
8235 if (GET_CODE (ftmp
->insn
) != BARRIER
8236 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8243 /* Scan over the fixes we have identified for this pool, fixing them
8244 up and adding the constants to the pool itself. */
8245 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8246 this_fix
= this_fix
->next
)
8247 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8250 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8251 minipool_vector_label
),
8252 this_fix
->minipool
->offset
);
8253 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8256 dump_minipool (last_barrier
->insn
);
8260 /* From now on we must synthesize any constants that we can't handle
8261 directly. This can happen if the RTL gets split during final
8262 instruction generation. */
8263 after_arm_reorg
= 1;
8265 /* Free the minipool memory. */
8266 obstack_free (&minipool_obstack
, minipool_startobj
);
8269 /* Routines to output assembly language. */
8271 /* If the rtx is the correct value then return the string of the number.
8272 In this way we can ensure that valid double constants are generated even
8273 when cross compiling. */
8275 fp_immediate_constant (rtx x
)
8280 if (!fp_consts_inited
)
8283 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8284 for (i
= 0; i
< 8; i
++)
8285 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8286 return strings_fp
[i
];
8291 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8293 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8297 if (!fp_consts_inited
)
8300 for (i
= 0; i
< 8; i
++)
8301 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8302 return strings_fp
[i
];
8307 /* Output the operands of a LDM/STM instruction to STREAM.
8308 MASK is the ARM register set mask of which only bits 0-15 are important.
8309 REG is the base register, either the frame pointer or the stack pointer,
8310 INSTR is the possibly suffixed load or store instruction. */
8313 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8317 bool not_first
= FALSE
;
8319 fputc ('\t', stream
);
8320 asm_fprintf (stream
, instr
, reg
);
8321 fputs (", {", stream
);
8323 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8324 if (mask
& (1 << i
))
8327 fprintf (stream
, ", ");
8329 asm_fprintf (stream
, "%r", i
);
8333 fprintf (stream
, "}\n");
8337 /* Output a FLDMX instruction to STREAM.
8338 BASE if the register containing the address.
8339 REG and COUNT specify the register range.
8340 Extra registers may be added to avoid hardware bugs. */
8343 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8347 /* Workaround ARM10 VFPr1 bug. */
8348 if (count
== 2 && !arm_arch6
)
8355 fputc ('\t', stream
);
8356 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8358 for (i
= reg
; i
< reg
+ count
; i
++)
8361 fputs (", ", stream
);
8362 asm_fprintf (stream
, "d%d", i
);
8364 fputs ("}\n", stream
);
8369 /* Output the assembly for a store multiple. */
8372 vfp_output_fstmx (rtx
* operands
)
8379 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8380 p
= strlen (pattern
);
8382 gcc_assert (GET_CODE (operands
[1]) == REG
);
8384 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8385 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8387 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8389 strcpy (&pattern
[p
], "}");
8391 output_asm_insn (pattern
, operands
);
8396 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8397 number of bytes pushed. */
8400 vfp_emit_fstmx (int base_reg
, int count
)
8407 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8408 register pairs are stored by a store multiple insn. We avoid this
8409 by pushing an extra pair. */
8410 if (count
== 2 && !arm_arch6
)
8412 if (base_reg
== LAST_VFP_REGNUM
- 3)
8417 /* ??? The frame layout is implementation defined. We describe
8418 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8419 We really need some way of representing the whole block so that the
8420 unwinder can figure it out at runtime. */
8421 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8422 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8424 reg
= gen_rtx_REG (DFmode
, base_reg
);
8428 = gen_rtx_SET (VOIDmode
,
8429 gen_frame_mem (BLKmode
,
8430 gen_rtx_PRE_DEC (BLKmode
,
8431 stack_pointer_rtx
)),
8432 gen_rtx_UNSPEC (BLKmode
,
8436 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8437 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8438 GEN_INT (-(count
* 8 + 4))));
8439 RTX_FRAME_RELATED_P (tmp
) = 1;
8440 XVECEXP (dwarf
, 0, 0) = tmp
;
8442 tmp
= gen_rtx_SET (VOIDmode
,
8443 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8445 RTX_FRAME_RELATED_P (tmp
) = 1;
8446 XVECEXP (dwarf
, 0, 1) = tmp
;
8448 for (i
= 1; i
< count
; i
++)
8450 reg
= gen_rtx_REG (DFmode
, base_reg
);
8452 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8454 tmp
= gen_rtx_SET (VOIDmode
,
8455 gen_frame_mem (DFmode
,
8456 gen_rtx_PLUS (SImode
,
8460 RTX_FRAME_RELATED_P (tmp
) = 1;
8461 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8464 par
= emit_insn (par
);
8465 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8467 RTX_FRAME_RELATED_P (par
) = 1;
8469 return count
* 8 + 4;
8473 /* Output a 'call' insn. */
8475 output_call (rtx
*operands
)
8477 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8479 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8480 if (REGNO (operands
[0]) == LR_REGNUM
)
8482 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8483 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8486 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8488 if (TARGET_INTERWORK
|| arm_arch4t
)
8489 output_asm_insn ("bx%?\t%0", operands
);
8491 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8496 /* Output a 'call' insn that is a reference in memory. */
8498 output_call_mem (rtx
*operands
)
8500 if (TARGET_INTERWORK
&& !arm_arch5
)
8502 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8503 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8504 output_asm_insn ("bx%?\t%|ip", operands
);
8506 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8508 /* LR is used in the memory address. We load the address in the
8509 first instruction. It's safe to use IP as the target of the
8510 load since the call will kill it anyway. */
8511 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8513 output_asm_insn ("blx%?\t%|ip", operands
);
8516 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8518 output_asm_insn ("bx%?\t%|ip", operands
);
8520 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8525 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8526 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8533 /* Output a move from arm registers to an fpa registers.
8534 OPERANDS[0] is an fpa register.
8535 OPERANDS[1] is the first registers of an arm register pair. */
8537 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8539 int arm_reg0
= REGNO (operands
[1]);
8542 gcc_assert (arm_reg0
!= IP_REGNUM
);
8544 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8545 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8546 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8548 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8549 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8554 /* Output a move from an fpa register to arm registers.
8555 OPERANDS[0] is the first registers of an arm register pair.
8556 OPERANDS[1] is an fpa register. */
8558 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8560 int arm_reg0
= REGNO (operands
[0]);
8563 gcc_assert (arm_reg0
!= IP_REGNUM
);
8565 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8566 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8567 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8569 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8570 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8574 /* Output a move from arm registers to arm registers of a long double
8575 OPERANDS[0] is the destination.
8576 OPERANDS[1] is the source. */
8578 output_mov_long_double_arm_from_arm (rtx
*operands
)
8580 /* We have to be careful here because the two might overlap. */
8581 int dest_start
= REGNO (operands
[0]);
8582 int src_start
= REGNO (operands
[1]);
8586 if (dest_start
< src_start
)
8588 for (i
= 0; i
< 3; i
++)
8590 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8591 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8592 output_asm_insn ("mov%?\t%0, %1", ops
);
8597 for (i
= 2; i
>= 0; i
--)
8599 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8600 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8601 output_asm_insn ("mov%?\t%0, %1", ops
);
8609 /* Output a move from arm registers to an fpa registers.
8610 OPERANDS[0] is an fpa register.
8611 OPERANDS[1] is the first registers of an arm register pair. */
8613 output_mov_double_fpa_from_arm (rtx
*operands
)
8615 int arm_reg0
= REGNO (operands
[1]);
8618 gcc_assert (arm_reg0
!= IP_REGNUM
);
8620 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8621 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8622 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8623 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8627 /* Output a move from an fpa register to arm registers.
8628 OPERANDS[0] is the first registers of an arm register pair.
8629 OPERANDS[1] is an fpa register. */
8631 output_mov_double_arm_from_fpa (rtx
*operands
)
8633 int arm_reg0
= REGNO (operands
[0]);
8636 gcc_assert (arm_reg0
!= IP_REGNUM
);
8638 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8639 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8640 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8641 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8645 /* Output a move between double words.
8646 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8647 or MEM<-REG and all MEMs must be offsettable addresses. */
8649 output_move_double (rtx
*operands
)
8651 enum rtx_code code0
= GET_CODE (operands
[0]);
8652 enum rtx_code code1
= GET_CODE (operands
[1]);
8657 int reg0
= REGNO (operands
[0]);
8659 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8661 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8663 switch (GET_CODE (XEXP (operands
[1], 0)))
8666 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8670 gcc_assert (TARGET_LDRD
);
8671 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8675 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8679 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8683 gcc_assert (TARGET_LDRD
);
8684 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8689 otherops
[0] = operands
[0];
8690 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8691 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8693 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8695 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8697 /* Registers overlap so split out the increment. */
8698 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8699 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8702 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8706 /* We only allow constant increments, so this is safe. */
8707 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8713 output_asm_insn ("adr%?\t%0, %1", operands
);
8714 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8718 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8719 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8721 otherops
[0] = operands
[0];
8722 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8723 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8725 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8727 if (GET_CODE (otherops
[2]) == CONST_INT
)
8729 switch ((int) INTVAL (otherops
[2]))
8732 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8735 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8738 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8743 && (GET_CODE (otherops
[2]) == REG
8744 || (GET_CODE (otherops
[2]) == CONST_INT
8745 && INTVAL (otherops
[2]) > -256
8746 && INTVAL (otherops
[2]) < 256)))
8748 if (reg_overlap_mentioned_p (otherops
[0],
8751 /* Swap base and index registers over to
8752 avoid a conflict. */
8753 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8754 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8756 /* If both registers conflict, it will usually
8757 have been fixed by a splitter. */
8758 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8760 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8761 output_asm_insn ("ldr%?d\t%0, [%1]",
8765 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8769 if (GET_CODE (otherops
[2]) == CONST_INT
)
8771 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8772 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8774 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8777 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8780 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8782 return "ldm%?ia\t%0, %M0";
8786 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8787 /* Take care of overlapping base/data reg. */
8788 if (reg_mentioned_p (operands
[0], operands
[1]))
8790 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8791 output_asm_insn ("ldr%?\t%0, %1", operands
);
8795 output_asm_insn ("ldr%?\t%0, %1", operands
);
8796 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8803 /* Constraints should ensure this. */
8804 gcc_assert (code0
== MEM
&& code1
== REG
);
8805 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8807 switch (GET_CODE (XEXP (operands
[0], 0)))
8810 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8814 gcc_assert (TARGET_LDRD
);
8815 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8819 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8823 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8827 gcc_assert (TARGET_LDRD
);
8828 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8833 otherops
[0] = operands
[1];
8834 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8835 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8837 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8838 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8840 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8844 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8845 if (GET_CODE (otherops
[2]) == CONST_INT
)
8847 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8850 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8854 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8858 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8863 && (GET_CODE (otherops
[2]) == REG
8864 || (GET_CODE (otherops
[2]) == CONST_INT
8865 && INTVAL (otherops
[2]) > -256
8866 && INTVAL (otherops
[2]) < 256)))
8868 otherops
[0] = operands
[1];
8869 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8870 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8876 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8877 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8878 output_asm_insn ("str%?\t%1, %0", operands
);
8879 output_asm_insn ("str%?\t%1, %0", otherops
);
8886 /* Output an ADD r, s, #n where n may be too big for one instruction.
8887 If adding zero to one register, output nothing. */
8889 output_add_immediate (rtx
*operands
)
8891 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8893 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8896 output_multi_immediate (operands
,
8897 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8900 output_multi_immediate (operands
,
8901 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8908 /* Output a multiple immediate operation.
8909 OPERANDS is the vector of operands referred to in the output patterns.
8910 INSTR1 is the output pattern to use for the first constant.
8911 INSTR2 is the output pattern to use for subsequent constants.
8912 IMMED_OP is the index of the constant slot in OPERANDS.
8913 N is the constant value. */
8915 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8916 int immed_op
, HOST_WIDE_INT n
)
8918 #if HOST_BITS_PER_WIDE_INT > 32
8924 /* Quick and easy output. */
8925 operands
[immed_op
] = const0_rtx
;
8926 output_asm_insn (instr1
, operands
);
8931 const char * instr
= instr1
;
8933 /* Note that n is never zero here (which would give no output). */
8934 for (i
= 0; i
< 32; i
+= 2)
8938 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8939 output_asm_insn (instr
, operands
);
8949 /* Return the appropriate ARM instruction for the operation code.
8950 The returned result should not be overwritten. OP is the rtx of the
8951 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8954 arithmetic_instr (rtx op
, int shift_first_arg
)
8956 switch (GET_CODE (op
))
8962 return shift_first_arg
? "rsb" : "sub";
8978 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8979 for the operation code. The returned result should not be overwritten.
8980 OP is the rtx code of the shift.
8981 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8984 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8987 enum rtx_code code
= GET_CODE (op
);
8989 switch (GET_CODE (XEXP (op
, 1)))
8997 *amountp
= INTVAL (XEXP (op
, 1));
9019 gcc_assert (*amountp
!= -1);
9020 *amountp
= 32 - *amountp
;
9029 /* We never have to worry about the amount being other than a
9030 power of 2, since this case can never be reloaded from a reg. */
9031 gcc_assert (*amountp
!= -1);
9032 *amountp
= int_log2 (*amountp
);
9041 /* This is not 100% correct, but follows from the desire to merge
9042 multiplication by a power of 2 with the recognizer for a
9043 shift. >=32 is not a valid shift for "asl", so we must try and
9044 output a shift that produces the correct arithmetical result.
9045 Using lsr #32 is identical except for the fact that the carry bit
9046 is not set correctly if we set the flags; but we never use the
9047 carry bit from such an operation, so we can ignore that. */
9048 if (code
== ROTATERT
)
9049 /* Rotate is just modulo 32. */
9051 else if (*amountp
!= (*amountp
& 31))
9058 /* Shifts of 0 are no-ops. */
9066 /* Obtain the shift from the POWER of two. */
9068 static HOST_WIDE_INT
9069 int_log2 (HOST_WIDE_INT power
)
9071 HOST_WIDE_INT shift
= 0;
9073 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9075 gcc_assert (shift
<= 31);
9082 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9083 because /bin/as is horribly restrictive. The judgement about
9084 whether or not each character is 'printable' (and can be output as
9085 is) or not (and must be printed with an octal escape) must be made
9086 with reference to the *host* character set -- the situation is
9087 similar to that discussed in the comments above pp_c_char in
9088 c-pretty-print.c. */
9090 #define MAX_ASCII_LEN 51
9093 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9098 fputs ("\t.ascii\t\"", stream
);
9100 for (i
= 0; i
< len
; i
++)
9104 if (len_so_far
>= MAX_ASCII_LEN
)
9106 fputs ("\"\n\t.ascii\t\"", stream
);
9112 if (c
== '\\' || c
== '\"')
9114 putc ('\\', stream
);
9122 fprintf (stream
, "\\%03o", c
);
9127 fputs ("\"\n", stream
);
9130 /* Compute the register save mask for registers 0 through 12
9131 inclusive. This code is used by arm_compute_save_reg_mask. */
9133 static unsigned long
9134 arm_compute_save_reg0_reg12_mask (void)
9136 unsigned long func_type
= arm_current_func_type ();
9137 unsigned long save_reg_mask
= 0;
9140 if (IS_INTERRUPT (func_type
))
9142 unsigned int max_reg
;
9143 /* Interrupt functions must not corrupt any registers,
9144 even call clobbered ones. If this is a leaf function
9145 we can just examine the registers used by the RTL, but
9146 otherwise we have to assume that whatever function is
9147 called might clobber anything, and so we have to save
9148 all the call-clobbered registers as well. */
9149 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9150 /* FIQ handlers have registers r8 - r12 banked, so
9151 we only need to check r0 - r7, Normal ISRs only
9152 bank r14 and r15, so we must check up to r12.
9153 r13 is the stack pointer which is always preserved,
9154 so we do not need to consider it here. */
9159 for (reg
= 0; reg
<= max_reg
; reg
++)
9160 if (regs_ever_live
[reg
]
9161 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9162 save_reg_mask
|= (1 << reg
);
9164 /* Also save the pic base register if necessary. */
9166 && !TARGET_SINGLE_PIC_BASE
9167 && current_function_uses_pic_offset_table
)
9168 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9172 /* In the normal case we only need to save those registers
9173 which are call saved and which are used by this function. */
9174 for (reg
= 0; reg
<= 10; reg
++)
9175 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9176 save_reg_mask
|= (1 << reg
);
9178 /* Handle the frame pointer as a special case. */
9179 if (! TARGET_APCS_FRAME
9180 && ! frame_pointer_needed
9181 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9182 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9183 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9185 /* If we aren't loading the PIC register,
9186 don't stack it even though it may be live. */
9188 && !TARGET_SINGLE_PIC_BASE
9189 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9190 || current_function_uses_pic_offset_table
))
9191 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9194 /* Save registers so the exception handler can modify them. */
9195 if (current_function_calls_eh_return
)
9201 reg
= EH_RETURN_DATA_REGNO (i
);
9202 if (reg
== INVALID_REGNUM
)
9204 save_reg_mask
|= 1 << reg
;
9208 return save_reg_mask
;
9211 /* Compute a bit mask of which registers need to be
9212 saved on the stack for the current function. */
9214 static unsigned long
9215 arm_compute_save_reg_mask (void)
9217 unsigned int save_reg_mask
= 0;
9218 unsigned long func_type
= arm_current_func_type ();
9220 if (IS_NAKED (func_type
))
9221 /* This should never really happen. */
9224 /* If we are creating a stack frame, then we must save the frame pointer,
9225 IP (which will hold the old stack pointer), LR and the PC. */
9226 if (frame_pointer_needed
)
9228 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9233 /* Volatile functions do not return, so there
9234 is no need to save any other registers. */
9235 if (IS_VOLATILE (func_type
))
9236 return save_reg_mask
;
9238 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9240 /* Decide if we need to save the link register.
9241 Interrupt routines have their own banked link register,
9242 so they never need to save it.
9243 Otherwise if we do not use the link register we do not need to save
9244 it. If we are pushing other registers onto the stack however, we
9245 can save an instruction in the epilogue by pushing the link register
9246 now and then popping it back into the PC. This incurs extra memory
9247 accesses though, so we only do it when optimizing for size, and only
9248 if we know that we will not need a fancy return sequence. */
9249 if (regs_ever_live
[LR_REGNUM
]
9252 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9253 && !current_function_calls_eh_return
))
9254 save_reg_mask
|= 1 << LR_REGNUM
;
9256 if (cfun
->machine
->lr_save_eliminated
)
9257 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9259 if (TARGET_REALLY_IWMMXT
9260 && ((bit_count (save_reg_mask
)
9261 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9265 /* The total number of registers that are going to be pushed
9266 onto the stack is odd. We need to ensure that the stack
9267 is 64-bit aligned before we start to save iWMMXt registers,
9268 and also before we start to create locals. (A local variable
9269 might be a double or long long which we will load/store using
9270 an iWMMXt instruction). Therefore we need to push another
9271 ARM register, so that the stack will be 64-bit aligned. We
9272 try to avoid using the arg registers (r0 -r3) as they might be
9273 used to pass values in a tail call. */
9274 for (reg
= 4; reg
<= 12; reg
++)
9275 if ((save_reg_mask
& (1 << reg
)) == 0)
9279 save_reg_mask
|= (1 << reg
);
9282 cfun
->machine
->sibcall_blocked
= 1;
9283 save_reg_mask
|= (1 << 3);
9287 return save_reg_mask
;
9291 /* Compute a bit mask of which registers need to be
9292 saved on the stack for the current function. */
9293 static unsigned long
9294 thumb_compute_save_reg_mask (void)
9300 for (reg
= 0; reg
< 12; reg
++)
9301 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9305 && !TARGET_SINGLE_PIC_BASE
9306 && current_function_uses_pic_offset_table
)
9307 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9309 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9310 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9311 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9313 /* LR will also be pushed if any lo regs are pushed. */
9314 if (mask
& 0xff || thumb_force_lr_save ())
9315 mask
|= (1 << LR_REGNUM
);
9317 /* Make sure we have a low work register if we need one.
9318 We will need one if we are going to push a high register,
9319 but we are not currently intending to push a low register. */
9320 if ((mask
& 0xff) == 0
9321 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9323 /* Use thumb_find_work_register to choose which register
9324 we will use. If the register is live then we will
9325 have to push it. Use LAST_LO_REGNUM as our fallback
9326 choice for the register to select. */
9327 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9329 if (! call_used_regs
[reg
])
9337 /* Return the number of bytes required to save VFP registers. */
9339 arm_get_vfp_saved_size (void)
9346 /* Space for saved VFP registers. */
9347 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9350 for (regno
= FIRST_VFP_REGNUM
;
9351 regno
< LAST_VFP_REGNUM
;
9354 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9355 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9359 /* Workaround ARM10 VFPr1 bug. */
9360 if (count
== 2 && !arm_arch6
)
9362 saved
+= count
* 8 + 4;
9371 if (count
== 2 && !arm_arch6
)
9373 saved
+= count
* 8 + 4;
9380 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9381 everything bar the final return instruction. */
9383 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9385 char conditional
[10];
9388 unsigned long live_regs_mask
;
9389 unsigned long func_type
;
9390 arm_stack_offsets
*offsets
;
9392 func_type
= arm_current_func_type ();
9394 if (IS_NAKED (func_type
))
9397 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9399 /* If this function was declared non-returning, and we have
9400 found a tail call, then we have to trust that the called
9401 function won't return. */
9406 /* Otherwise, trap an attempted return by aborting. */
9408 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9410 assemble_external_libcall (ops
[1]);
9411 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9417 gcc_assert (!current_function_calls_alloca
|| really_return
);
9419 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9421 return_used_this_function
= 1;
9423 live_regs_mask
= arm_compute_save_reg_mask ();
9427 const char * return_reg
;
9429 /* If we do not have any special requirements for function exit
9430 (e.g. interworking, or ISR) then we can load the return address
9431 directly into the PC. Otherwise we must load it into LR. */
9433 && ! TARGET_INTERWORK
)
9434 return_reg
= reg_names
[PC_REGNUM
];
9436 return_reg
= reg_names
[LR_REGNUM
];
9438 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9440 /* There are three possible reasons for the IP register
9441 being saved. 1) a stack frame was created, in which case
9442 IP contains the old stack pointer, or 2) an ISR routine
9443 corrupted it, or 3) it was saved to align the stack on
9444 iWMMXt. In case 1, restore IP into SP, otherwise just
9446 if (frame_pointer_needed
)
9448 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9449 live_regs_mask
|= (1 << SP_REGNUM
);
9452 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9455 /* On some ARM architectures it is faster to use LDR rather than
9456 LDM to load a single register. On other architectures, the
9457 cost is the same. In 26 bit mode, or for exception handlers,
9458 we have to use LDM to load the PC so that the CPSR is also
9460 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9461 if (live_regs_mask
== (1U << reg
))
9464 if (reg
<= LAST_ARM_REGNUM
9465 && (reg
!= LR_REGNUM
9467 || ! IS_INTERRUPT (func_type
)))
9469 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9470 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9477 /* Generate the load multiple instruction to restore the
9478 registers. Note we can get here, even if
9479 frame_pointer_needed is true, but only if sp already
9480 points to the base of the saved core registers. */
9481 if (live_regs_mask
& (1 << SP_REGNUM
))
9483 unsigned HOST_WIDE_INT stack_adjust
;
9485 offsets
= arm_get_frame_offsets ();
9486 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9487 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9489 if (stack_adjust
&& arm_arch5
)
9490 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9493 /* If we can't use ldmib (SA110 bug),
9494 then try to pop r3 instead. */
9496 live_regs_mask
|= 1 << 3;
9497 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9501 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9503 p
= instr
+ strlen (instr
);
9505 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9506 if (live_regs_mask
& (1 << reg
))
9508 int l
= strlen (reg_names
[reg
]);
9514 memcpy (p
, ", ", 2);
9518 memcpy (p
, "%|", 2);
9519 memcpy (p
+ 2, reg_names
[reg
], l
);
9523 if (live_regs_mask
& (1 << LR_REGNUM
))
9525 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9526 /* If returning from an interrupt, restore the CPSR. */
9527 if (IS_INTERRUPT (func_type
))
9534 output_asm_insn (instr
, & operand
);
9536 /* See if we need to generate an extra instruction to
9537 perform the actual function return. */
9539 && func_type
!= ARM_FT_INTERWORKED
9540 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9542 /* The return has already been handled
9543 by loading the LR into the PC. */
9550 switch ((int) ARM_FUNC_TYPE (func_type
))
9554 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9557 case ARM_FT_INTERWORKED
:
9558 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9561 case ARM_FT_EXCEPTION
:
9562 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9566 /* Use bx if it's available. */
9567 if (arm_arch5
|| arm_arch4t
)
9568 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9570 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9574 output_asm_insn (instr
, & operand
);
9580 /* Write the function name into the code section, directly preceding
9581 the function prologue.
9583 Code will be output similar to this:
9585 .ascii "arm_poke_function_name", 0
9588 .word 0xff000000 + (t1 - t0)
9589 arm_poke_function_name
9591 stmfd sp!, {fp, ip, lr, pc}
9594 When performing a stack backtrace, code can inspect the value
9595 of 'pc' stored at 'fp' + 0. If the trace function then looks
9596 at location pc - 12 and the top 8 bits are set, then we know
9597 that there is a function name embedded immediately preceding this
9598 location and has length ((pc[-3]) & 0xff000000).
9600 We assume that pc is declared as a pointer to an unsigned long.
9602 It is of no benefit to output the function name if we are assembling
9603 a leaf function. These function types will not contain a stack
9604 backtrace structure, therefore it is not possible to determine the
9607 arm_poke_function_name (FILE *stream
, const char *name
)
9609 unsigned long alignlength
;
9610 unsigned long length
;
9613 length
= strlen (name
) + 1;
9614 alignlength
= ROUND_UP_WORD (length
);
9616 ASM_OUTPUT_ASCII (stream
, name
, length
);
9617 ASM_OUTPUT_ALIGN (stream
, 2);
9618 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9619 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9622 /* Place some comments into the assembler stream
9623 describing the current function. */
9625 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9627 unsigned long func_type
;
9631 thumb_output_function_prologue (f
, frame_size
);
9636 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9638 func_type
= arm_current_func_type ();
9640 switch ((int) ARM_FUNC_TYPE (func_type
))
9645 case ARM_FT_INTERWORKED
:
9646 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9649 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9652 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9654 case ARM_FT_EXCEPTION
:
9655 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9659 if (IS_NAKED (func_type
))
9660 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9662 if (IS_VOLATILE (func_type
))
9663 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9665 if (IS_NESTED (func_type
))
9666 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9668 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9669 current_function_args_size
,
9670 current_function_pretend_args_size
, frame_size
);
9672 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9673 frame_pointer_needed
,
9674 cfun
->machine
->uses_anonymous_args
);
9676 if (cfun
->machine
->lr_save_eliminated
)
9677 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9679 if (current_function_calls_eh_return
)
9680 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9682 #ifdef AOF_ASSEMBLER
9684 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9687 return_used_this_function
= 0;
9691 arm_output_epilogue (rtx sibling
)
9694 unsigned long saved_regs_mask
;
9695 unsigned long func_type
;
9696 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9697 frame that is $fp + 4 for a non-variadic function. */
9698 int floats_offset
= 0;
9700 FILE * f
= asm_out_file
;
9701 unsigned int lrm_count
= 0;
9702 int really_return
= (sibling
== NULL
);
9704 arm_stack_offsets
*offsets
;
9706 /* If we have already generated the return instruction
9707 then it is futile to generate anything else. */
9708 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9711 func_type
= arm_current_func_type ();
9713 if (IS_NAKED (func_type
))
9714 /* Naked functions don't have epilogues. */
9717 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9721 /* A volatile function should never return. Call abort. */
9722 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9723 assemble_external_libcall (op
);
9724 output_asm_insn ("bl\t%a0", &op
);
9729 /* If we are throwing an exception, then we really must be doing a
9730 return, so we can't tail-call. */
9731 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9733 offsets
= arm_get_frame_offsets ();
9734 saved_regs_mask
= arm_compute_save_reg_mask ();
9737 lrm_count
= bit_count (saved_regs_mask
);
9739 floats_offset
= offsets
->saved_args
;
9740 /* Compute how far away the floats will be. */
9741 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9742 if (saved_regs_mask
& (1 << reg
))
9745 if (frame_pointer_needed
)
9747 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9748 int vfp_offset
= offsets
->frame
;
9750 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9752 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9753 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9755 floats_offset
+= 12;
9756 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9757 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9762 start_reg
= LAST_FPA_REGNUM
;
9764 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9766 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9768 floats_offset
+= 12;
9770 /* We can't unstack more than four registers at once. */
9771 if (start_reg
- reg
== 3)
9773 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9774 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9775 start_reg
= reg
- 1;
9780 if (reg
!= start_reg
)
9781 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9782 reg
+ 1, start_reg
- reg
,
9783 FP_REGNUM
, floats_offset
- vfp_offset
);
9784 start_reg
= reg
- 1;
9788 /* Just in case the last register checked also needs unstacking. */
9789 if (reg
!= start_reg
)
9790 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9791 reg
+ 1, start_reg
- reg
,
9792 FP_REGNUM
, floats_offset
- vfp_offset
);
9795 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9799 /* The fldmx insn does not have base+offset addressing modes,
9800 so we use IP to hold the address. */
9801 saved_size
= arm_get_vfp_saved_size ();
9805 floats_offset
+= saved_size
;
9806 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9807 FP_REGNUM
, floats_offset
- vfp_offset
);
9809 start_reg
= FIRST_VFP_REGNUM
;
9810 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9812 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9813 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9815 if (start_reg
!= reg
)
9816 arm_output_fldmx (f
, IP_REGNUM
,
9817 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9818 (reg
- start_reg
) / 2);
9819 start_reg
= reg
+ 2;
9822 if (start_reg
!= reg
)
9823 arm_output_fldmx (f
, IP_REGNUM
,
9824 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9825 (reg
- start_reg
) / 2);
9830 /* The frame pointer is guaranteed to be non-double-word aligned.
9831 This is because it is set to (old_stack_pointer - 4) and the
9832 old_stack_pointer was double word aligned. Thus the offset to
9833 the iWMMXt registers to be loaded must also be non-double-word
9834 sized, so that the resultant address *is* double-word aligned.
9835 We can ignore floats_offset since that was already included in
9836 the live_regs_mask. */
9837 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9839 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9840 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9842 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9843 reg
, FP_REGNUM
, lrm_count
* 4);
9848 /* saved_regs_mask should contain the IP, which at the time of stack
9849 frame generation actually contains the old stack pointer. So a
9850 quick way to unwind the stack is just pop the IP register directly
9851 into the stack pointer. */
9852 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9853 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9854 saved_regs_mask
|= (1 << SP_REGNUM
);
9856 /* There are two registers left in saved_regs_mask - LR and PC. We
9857 only need to restore the LR register (the return address), but to
9858 save time we can load it directly into the PC, unless we need a
9859 special function exit sequence, or we are not really returning. */
9861 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9862 && !current_function_calls_eh_return
)
9863 /* Delete the LR from the register mask, so that the LR on
9864 the stack is loaded into the PC in the register mask. */
9865 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9867 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9869 /* We must use SP as the base register, because SP is one of the
9870 registers being restored. If an interrupt or page fault
9871 happens in the ldm instruction, the SP might or might not
9872 have been restored. That would be bad, as then SP will no
9873 longer indicate the safe area of stack, and we can get stack
9874 corruption. Using SP as the base register means that it will
9875 be reset correctly to the original value, should an interrupt
9876 occur. If the stack pointer already points at the right
9877 place, then omit the subtraction. */
9878 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9879 || current_function_calls_alloca
)
9880 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9881 4 * bit_count (saved_regs_mask
));
9882 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9884 if (IS_INTERRUPT (func_type
))
9885 /* Interrupt handlers will have pushed the
9886 IP onto the stack, so restore it now. */
9887 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9891 /* Restore stack pointer if necessary. */
9892 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9894 operands
[0] = operands
[1] = stack_pointer_rtx
;
9895 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9896 output_add_immediate (operands
);
9899 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9901 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9902 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9903 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9908 start_reg
= FIRST_FPA_REGNUM
;
9910 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9912 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9914 if (reg
- start_reg
== 3)
9916 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9917 start_reg
, SP_REGNUM
);
9918 start_reg
= reg
+ 1;
9923 if (reg
!= start_reg
)
9924 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9925 start_reg
, reg
- start_reg
,
9928 start_reg
= reg
+ 1;
9932 /* Just in case the last register checked also needs unstacking. */
9933 if (reg
!= start_reg
)
9934 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9935 start_reg
, reg
- start_reg
, SP_REGNUM
);
9938 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9940 start_reg
= FIRST_VFP_REGNUM
;
9941 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9943 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9944 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9946 if (start_reg
!= reg
)
9947 arm_output_fldmx (f
, SP_REGNUM
,
9948 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9949 (reg
- start_reg
) / 2);
9950 start_reg
= reg
+ 2;
9953 if (start_reg
!= reg
)
9954 arm_output_fldmx (f
, SP_REGNUM
,
9955 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9956 (reg
- start_reg
) / 2);
9959 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9960 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9961 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9963 /* If we can, restore the LR into the PC. */
9964 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9966 && current_function_pretend_args_size
== 0
9967 && saved_regs_mask
& (1 << LR_REGNUM
)
9968 && !current_function_calls_eh_return
)
9970 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9971 saved_regs_mask
|= (1 << PC_REGNUM
);
9974 /* Load the registers off the stack. If we only have one register
9975 to load use the LDR instruction - it is faster. */
9976 if (saved_regs_mask
== (1 << LR_REGNUM
))
9978 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9980 else if (saved_regs_mask
)
9982 if (saved_regs_mask
& (1 << SP_REGNUM
))
9983 /* Note - write back to the stack register is not enabled
9984 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9985 in the list of registers and if we add writeback the
9986 instruction becomes UNPREDICTABLE. */
9987 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9989 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9992 if (current_function_pretend_args_size
)
9994 /* Unwind the pre-pushed regs. */
9995 operands
[0] = operands
[1] = stack_pointer_rtx
;
9996 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9997 output_add_immediate (operands
);
10001 /* We may have already restored PC directly from the stack. */
10002 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10005 /* Stack adjustment for exception handler. */
10006 if (current_function_calls_eh_return
)
10007 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10008 ARM_EH_STACKADJ_REGNUM
);
10010 /* Generate the return instruction. */
10011 switch ((int) ARM_FUNC_TYPE (func_type
))
10015 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10018 case ARM_FT_EXCEPTION
:
10019 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10022 case ARM_FT_INTERWORKED
:
10023 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10027 if (arm_arch5
|| arm_arch4t
)
10028 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10030 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10038 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10039 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10041 arm_stack_offsets
*offsets
;
10047 /* Emit any call-via-reg trampolines that are needed for v4t support
10048 of call_reg and call_value_reg type insns. */
10049 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10051 rtx label
= cfun
->machine
->call_via
[regno
];
10055 function_section (current_function_decl
);
10056 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10057 CODE_LABEL_NUMBER (label
));
10058 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10062 /* ??? Probably not safe to set this here, since it assumes that a
10063 function will be emitted as assembly immediately after we generate
10064 RTL for it. This does not happen for inline functions. */
10065 return_used_this_function
= 0;
10069 /* We need to take into account any stack-frame rounding. */
10070 offsets
= arm_get_frame_offsets ();
10072 gcc_assert (!use_return_insn (FALSE
, NULL
)
10073 || !return_used_this_function
10074 || offsets
->saved_regs
== offsets
->outgoing_args
10075 || frame_pointer_needed
);
10077 /* Reset the ARM-specific per-function variables. */
10078 after_arm_reorg
= 0;
10082 /* Generate and emit an insn that we will recognize as a push_multi.
10083 Unfortunately, since this insn does not reflect very well the actual
10084 semantics of the operation, we need to annotate the insn for the benefit
10085 of DWARF2 frame unwind information. */
10087 emit_multi_reg_push (unsigned long mask
)
10090 int num_dwarf_regs
;
10094 int dwarf_par_index
;
10097 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10098 if (mask
& (1 << i
))
10101 gcc_assert (num_regs
&& num_regs
<= 16);
10103 /* We don't record the PC in the dwarf frame information. */
10104 num_dwarf_regs
= num_regs
;
10105 if (mask
& (1 << PC_REGNUM
))
10108 /* For the body of the insn we are going to generate an UNSPEC in
10109 parallel with several USEs. This allows the insn to be recognized
10110 by the push_multi pattern in the arm.md file. The insn looks
10111 something like this:
10114 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10115 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10116 (use (reg:SI 11 fp))
10117 (use (reg:SI 12 ip))
10118 (use (reg:SI 14 lr))
10119 (use (reg:SI 15 pc))
10122 For the frame note however, we try to be more explicit and actually
10123 show each register being stored into the stack frame, plus a (single)
10124 decrement of the stack pointer. We do it this way in order to be
10125 friendly to the stack unwinding code, which only wants to see a single
10126 stack decrement per instruction. The RTL we generate for the note looks
10127 something like this:
10130 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10131 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10132 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10133 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10134 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10137 This sequence is used both by the code to support stack unwinding for
10138 exceptions handlers and the code to generate dwarf2 frame debugging. */
10140 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10141 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10142 dwarf_par_index
= 1;
10144 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10146 if (mask
& (1 << i
))
10148 reg
= gen_rtx_REG (SImode
, i
);
10150 XVECEXP (par
, 0, 0)
10151 = gen_rtx_SET (VOIDmode
,
10152 gen_frame_mem (BLKmode
,
10153 gen_rtx_PRE_DEC (BLKmode
,
10154 stack_pointer_rtx
)),
10155 gen_rtx_UNSPEC (BLKmode
,
10156 gen_rtvec (1, reg
),
10157 UNSPEC_PUSH_MULT
));
10159 if (i
!= PC_REGNUM
)
10161 tmp
= gen_rtx_SET (VOIDmode
,
10162 gen_frame_mem (SImode
, stack_pointer_rtx
),
10164 RTX_FRAME_RELATED_P (tmp
) = 1;
10165 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10173 for (j
= 1, i
++; j
< num_regs
; i
++)
10175 if (mask
& (1 << i
))
10177 reg
= gen_rtx_REG (SImode
, i
);
10179 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10181 if (i
!= PC_REGNUM
)
10184 = gen_rtx_SET (VOIDmode
,
10185 gen_frame_mem (SImode
,
10186 plus_constant (stack_pointer_rtx
,
10189 RTX_FRAME_RELATED_P (tmp
) = 1;
10190 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10197 par
= emit_insn (par
);
10199 tmp
= gen_rtx_SET (SImode
,
10201 gen_rtx_PLUS (SImode
,
10203 GEN_INT (-4 * num_regs
)));
10204 RTX_FRAME_RELATED_P (tmp
) = 1;
10205 XVECEXP (dwarf
, 0, 0) = tmp
;
10207 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10212 /* Calculate the size of the return value that is passed in registers. */
10214 arm_size_return_regs (void)
10216 enum machine_mode mode
;
10218 if (current_function_return_rtx
!= 0)
10219 mode
= GET_MODE (current_function_return_rtx
);
10221 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10223 return GET_MODE_SIZE (mode
);
10227 emit_sfm (int base_reg
, int count
)
10234 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10235 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10237 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10239 XVECEXP (par
, 0, 0)
10240 = gen_rtx_SET (VOIDmode
,
10241 gen_frame_mem (BLKmode
,
10242 gen_rtx_PRE_DEC (BLKmode
,
10243 stack_pointer_rtx
)),
10244 gen_rtx_UNSPEC (BLKmode
,
10245 gen_rtvec (1, reg
),
10246 UNSPEC_PUSH_MULT
));
10247 tmp
= gen_rtx_SET (VOIDmode
,
10248 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10249 RTX_FRAME_RELATED_P (tmp
) = 1;
10250 XVECEXP (dwarf
, 0, 1) = tmp
;
10252 for (i
= 1; i
< count
; i
++)
10254 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10255 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10257 tmp
= gen_rtx_SET (VOIDmode
,
10258 gen_frame_mem (XFmode
,
10259 plus_constant (stack_pointer_rtx
,
10262 RTX_FRAME_RELATED_P (tmp
) = 1;
10263 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10266 tmp
= gen_rtx_SET (VOIDmode
,
10268 gen_rtx_PLUS (SImode
,
10270 GEN_INT (-12 * count
)));
10271 RTX_FRAME_RELATED_P (tmp
) = 1;
10272 XVECEXP (dwarf
, 0, 0) = tmp
;
10274 par
= emit_insn (par
);
10275 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10281 /* Return true if the current function needs to save/restore LR. */
10284 thumb_force_lr_save (void)
10286 return !cfun
->machine
->lr_save_eliminated
10287 && (!leaf_function_p ()
10288 || thumb_far_jump_used_p ()
10289 || regs_ever_live
[LR_REGNUM
]);
10293 /* Compute the distance from register FROM to register TO.
10294 These can be the arg pointer (26), the soft frame pointer (25),
10295 the stack pointer (13) or the hard frame pointer (11).
10296 In thumb mode r7 is used as the soft frame pointer, if needed.
10297 Typical stack layout looks like this:
10299 old stack pointer -> | |
10302 | | saved arguments for
10303 | | vararg functions
10306 hard FP & arg pointer -> | | \
10314 soft frame pointer -> | | /
10319 locals base pointer -> | | /
10324 current stack pointer -> | | /
10327 For a given function some or all of these stack components
10328 may not be needed, giving rise to the possibility of
10329 eliminating some of the registers.
10331 The values returned by this function must reflect the behavior
10332 of arm_expand_prologue() and arm_compute_save_reg_mask().
10334 The sign of the number returned reflects the direction of stack
10335 growth, so the values are positive for all eliminations except
10336 from the soft frame pointer to the hard frame pointer.
10338 SFP may point just inside the local variables block to ensure correct
10342 /* Calculate stack offsets. These are used to calculate register elimination
10343 offsets and in prologue/epilogue code. */
10345 static arm_stack_offsets
*
10346 arm_get_frame_offsets (void)
10348 struct arm_stack_offsets
*offsets
;
10349 unsigned long func_type
;
10352 HOST_WIDE_INT frame_size
;
10354 offsets
= &cfun
->machine
->stack_offsets
;
10356 /* We need to know if we are a leaf function. Unfortunately, it
10357 is possible to be called after start_sequence has been called,
10358 which causes get_insns to return the insns for the sequence,
10359 not the function, which will cause leaf_function_p to return
10360 the incorrect result.
10362 to know about leaf functions once reload has completed, and the
10363 frame size cannot be changed after that time, so we can safely
10364 use the cached value. */
10366 if (reload_completed
)
10369 /* Initially this is the size of the local variables. It will translated
10370 into an offset once we have determined the size of preceding data. */
10371 frame_size
= ROUND_UP_WORD (get_frame_size ());
10373 leaf
= leaf_function_p ();
10375 /* Space for variadic functions. */
10376 offsets
->saved_args
= current_function_pretend_args_size
;
10378 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10382 unsigned int regno
;
10384 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10386 /* We know that SP will be doubleword aligned on entry, and we must
10387 preserve that condition at any subroutine call. We also require the
10388 soft frame pointer to be doubleword aligned. */
10390 if (TARGET_REALLY_IWMMXT
)
10392 /* Check for the call-saved iWMMXt registers. */
10393 for (regno
= FIRST_IWMMXT_REGNUM
;
10394 regno
<= LAST_IWMMXT_REGNUM
;
10396 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10400 func_type
= arm_current_func_type ();
10401 if (! IS_VOLATILE (func_type
))
10403 /* Space for saved FPA registers. */
10404 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10405 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10408 /* Space for saved VFP registers. */
10409 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10410 saved
+= arm_get_vfp_saved_size ();
10413 else /* TARGET_THUMB */
10415 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10416 if (TARGET_BACKTRACE
)
10420 /* Saved registers include the stack frame. */
10421 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10422 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10423 /* A leaf function does not need any stack alignment if it has nothing
10425 if (leaf
&& frame_size
== 0)
10427 offsets
->outgoing_args
= offsets
->soft_frame
;
10431 /* Ensure SFP has the correct alignment. */
10432 if (ARM_DOUBLEWORD_ALIGN
10433 && (offsets
->soft_frame
& 7))
10434 offsets
->soft_frame
+= 4;
10436 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10437 offsets
->outgoing_args
= (offsets
->locals_base
10438 + current_function_outgoing_args_size
);
10440 if (ARM_DOUBLEWORD_ALIGN
)
10442 /* Ensure SP remains doubleword aligned. */
10443 if (offsets
->outgoing_args
& 7)
10444 offsets
->outgoing_args
+= 4;
10445 gcc_assert (!(offsets
->outgoing_args
& 7));
10452 /* Calculate the relative offsets for the different stack pointers. Positive
10453 offsets are in the direction of stack growth. */
10456 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10458 arm_stack_offsets
*offsets
;
10460 offsets
= arm_get_frame_offsets ();
10462 /* OK, now we have enough information to compute the distances.
10463 There must be an entry in these switch tables for each pair
10464 of registers in ELIMINABLE_REGS, even if some of the entries
10465 seem to be redundant or useless. */
10468 case ARG_POINTER_REGNUM
:
10471 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10474 case FRAME_POINTER_REGNUM
:
10475 /* This is the reverse of the soft frame pointer
10476 to hard frame pointer elimination below. */
10477 return offsets
->soft_frame
- offsets
->saved_args
;
10479 case ARM_HARD_FRAME_POINTER_REGNUM
:
10480 /* If there is no stack frame then the hard
10481 frame pointer and the arg pointer coincide. */
10482 if (offsets
->frame
== offsets
->saved_regs
)
10484 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10485 return (frame_pointer_needed
10486 && cfun
->static_chain_decl
!= NULL
10487 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10489 case STACK_POINTER_REGNUM
:
10490 /* If nothing has been pushed on the stack at all
10491 then this will return -4. This *is* correct! */
10492 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10495 gcc_unreachable ();
10497 gcc_unreachable ();
10499 case FRAME_POINTER_REGNUM
:
10502 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10505 case ARM_HARD_FRAME_POINTER_REGNUM
:
10506 /* The hard frame pointer points to the top entry in the
10507 stack frame. The soft frame pointer to the bottom entry
10508 in the stack frame. If there is no stack frame at all,
10509 then they are identical. */
10511 return offsets
->frame
- offsets
->soft_frame
;
10513 case STACK_POINTER_REGNUM
:
10514 return offsets
->outgoing_args
- offsets
->soft_frame
;
10517 gcc_unreachable ();
10519 gcc_unreachable ();
10522 /* You cannot eliminate from the stack pointer.
10523 In theory you could eliminate from the hard frame
10524 pointer to the stack pointer, but this will never
10525 happen, since if a stack frame is not needed the
10526 hard frame pointer will never be used. */
10527 gcc_unreachable ();
10532 /* Generate the prologue instructions for entry into an ARM function. */
10534 arm_expand_prologue (void)
10540 unsigned long live_regs_mask
;
10541 unsigned long func_type
;
10543 int saved_pretend_args
= 0;
10544 int saved_regs
= 0;
10545 unsigned HOST_WIDE_INT args_to_push
;
10546 arm_stack_offsets
*offsets
;
10548 func_type
= arm_current_func_type ();
10550 /* Naked functions don't have prologues. */
10551 if (IS_NAKED (func_type
))
10554 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10555 args_to_push
= current_function_pretend_args_size
;
10557 /* Compute which register we will have to save onto the stack. */
10558 live_regs_mask
= arm_compute_save_reg_mask ();
10560 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10562 if (frame_pointer_needed
)
10564 if (IS_INTERRUPT (func_type
))
10566 /* Interrupt functions must not corrupt any registers.
10567 Creating a frame pointer however, corrupts the IP
10568 register, so we must push it first. */
10569 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10571 /* Do not set RTX_FRAME_RELATED_P on this insn.
10572 The dwarf stack unwinding code only wants to see one
10573 stack decrement per function, and this is not it. If
10574 this instruction is labeled as being part of the frame
10575 creation sequence then dwarf2out_frame_debug_expr will
10576 die when it encounters the assignment of IP to FP
10577 later on, since the use of SP here establishes SP as
10578 the CFA register and not IP.
10580 Anyway this instruction is not really part of the stack
10581 frame creation although it is part of the prologue. */
10583 else if (IS_NESTED (func_type
))
10585 /* The Static chain register is the same as the IP register
10586 used as a scratch register during stack frame creation.
10587 To get around this need to find somewhere to store IP
10588 whilst the frame is being created. We try the following
10591 1. The last argument register.
10592 2. A slot on the stack above the frame. (This only
10593 works if the function is not a varargs function).
10594 3. Register r3, after pushing the argument registers
10597 Note - we only need to tell the dwarf2 backend about the SP
10598 adjustment in the second variant; the static chain register
10599 doesn't need to be unwound, as it doesn't contain a value
10600 inherited from the caller. */
10602 if (regs_ever_live
[3] == 0)
10604 insn
= gen_rtx_REG (SImode
, 3);
10605 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10606 insn
= emit_insn (insn
);
10608 else if (args_to_push
== 0)
10611 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10612 insn
= gen_frame_mem (SImode
, insn
);
10613 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10614 insn
= emit_insn (insn
);
10618 /* Just tell the dwarf backend that we adjusted SP. */
10619 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10620 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10621 GEN_INT (-fp_offset
)));
10622 RTX_FRAME_RELATED_P (insn
) = 1;
10623 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10624 dwarf
, REG_NOTES (insn
));
10628 /* Store the args on the stack. */
10629 if (cfun
->machine
->uses_anonymous_args
)
10630 insn
= emit_multi_reg_push
10631 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10634 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10635 GEN_INT (- args_to_push
)));
10637 RTX_FRAME_RELATED_P (insn
) = 1;
10639 saved_pretend_args
= 1;
10640 fp_offset
= args_to_push
;
10643 /* Now reuse r3 to preserve IP. */
10644 insn
= gen_rtx_REG (SImode
, 3);
10645 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10646 (void) emit_insn (insn
);
10652 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10653 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10656 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10658 insn
= emit_insn (insn
);
10659 RTX_FRAME_RELATED_P (insn
) = 1;
10664 /* Push the argument registers, or reserve space for them. */
10665 if (cfun
->machine
->uses_anonymous_args
)
10666 insn
= emit_multi_reg_push
10667 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10670 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10671 GEN_INT (- args_to_push
)));
10672 RTX_FRAME_RELATED_P (insn
) = 1;
10675 /* If this is an interrupt service routine, and the link register
10676 is going to be pushed, and we are not creating a stack frame,
10677 (which would involve an extra push of IP and a pop in the epilogue)
10678 subtracting four from LR now will mean that the function return
10679 can be done with a single instruction. */
10680 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10681 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10682 && ! frame_pointer_needed
)
10683 emit_insn (gen_rtx_SET (SImode
,
10684 gen_rtx_REG (SImode
, LR_REGNUM
),
10685 gen_rtx_PLUS (SImode
,
10686 gen_rtx_REG (SImode
, LR_REGNUM
),
10689 if (live_regs_mask
)
10691 insn
= emit_multi_reg_push (live_regs_mask
);
10692 saved_regs
+= bit_count (live_regs_mask
) * 4;
10693 RTX_FRAME_RELATED_P (insn
) = 1;
10697 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10698 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10700 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10701 insn
= gen_frame_mem (V2SImode
, insn
);
10702 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10703 gen_rtx_REG (V2SImode
, reg
)));
10704 RTX_FRAME_RELATED_P (insn
) = 1;
10708 if (! IS_VOLATILE (func_type
))
10712 /* Save any floating point call-saved registers used by this
10714 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10716 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10717 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10719 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10720 insn
= gen_frame_mem (XFmode
, insn
);
10721 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10722 gen_rtx_REG (XFmode
, reg
)));
10723 RTX_FRAME_RELATED_P (insn
) = 1;
10729 start_reg
= LAST_FPA_REGNUM
;
10731 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10733 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10735 if (start_reg
- reg
== 3)
10737 insn
= emit_sfm (reg
, 4);
10738 RTX_FRAME_RELATED_P (insn
) = 1;
10740 start_reg
= reg
- 1;
10745 if (start_reg
!= reg
)
10747 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10748 RTX_FRAME_RELATED_P (insn
) = 1;
10749 saved_regs
+= (start_reg
- reg
) * 12;
10751 start_reg
= reg
- 1;
10755 if (start_reg
!= reg
)
10757 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10758 saved_regs
+= (start_reg
- reg
) * 12;
10759 RTX_FRAME_RELATED_P (insn
) = 1;
10762 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10764 start_reg
= FIRST_VFP_REGNUM
;
10766 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10768 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10769 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10771 if (start_reg
!= reg
)
10772 saved_regs
+= vfp_emit_fstmx (start_reg
,
10773 (reg
- start_reg
) / 2);
10774 start_reg
= reg
+ 2;
10777 if (start_reg
!= reg
)
10778 saved_regs
+= vfp_emit_fstmx (start_reg
,
10779 (reg
- start_reg
) / 2);
10783 if (frame_pointer_needed
)
10785 /* Create the new frame pointer. */
10786 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10787 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10788 RTX_FRAME_RELATED_P (insn
) = 1;
10790 if (IS_NESTED (func_type
))
10792 /* Recover the static chain register. */
10793 if (regs_ever_live
[3] == 0
10794 || saved_pretend_args
)
10795 insn
= gen_rtx_REG (SImode
, 3);
10796 else /* if (current_function_pretend_args_size == 0) */
10798 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10800 insn
= gen_frame_mem (SImode
, insn
);
10803 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10804 /* Add a USE to stop propagate_one_insn() from barfing. */
10805 emit_insn (gen_prologue_use (ip_rtx
));
10809 offsets
= arm_get_frame_offsets ();
10810 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10812 /* This add can produce multiple insns for a large constant, so we
10813 need to get tricky. */
10814 rtx last
= get_last_insn ();
10816 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10817 - offsets
->outgoing_args
);
10819 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10823 last
= last
? NEXT_INSN (last
) : get_insns ();
10824 RTX_FRAME_RELATED_P (last
) = 1;
10826 while (last
!= insn
);
10828 /* If the frame pointer is needed, emit a special barrier that
10829 will prevent the scheduler from moving stores to the frame
10830 before the stack adjustment. */
10831 if (frame_pointer_needed
)
10832 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10833 hard_frame_pointer_rtx
));
10838 arm_load_pic_register (0UL);
10840 /* If we are profiling, make sure no instructions are scheduled before
10841 the call to mcount. Similarly if the user has requested no
10842 scheduling in the prolog. */
10843 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
10844 emit_insn (gen_blockage ());
10846 /* If the link register is being kept alive, with the return address in it,
10847 then make sure that it does not get reused by the ce2 pass. */
10848 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10850 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10851 cfun
->machine
->lr_save_eliminated
= 1;
10855 /* If CODE is 'd', then the X is a condition operand and the instruction
10856 should only be executed if the condition is true.
10857 if CODE is 'D', then the X is a condition operand and the instruction
10858 should only be executed if the condition is false: however, if the mode
10859 of the comparison is CCFPEmode, then always execute the instruction -- we
10860 do this because in these circumstances !GE does not necessarily imply LT;
10861 in these cases the instruction pattern will take care to make sure that
10862 an instruction containing %d will follow, thereby undoing the effects of
10863 doing this instruction unconditionally.
10864 If CODE is 'N' then X is a floating point operand that must be negated
10866 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10867 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10869 arm_print_operand (FILE *stream
, rtx x
, int code
)
10874 fputs (ASM_COMMENT_START
, stream
);
10878 fputs (user_label_prefix
, stream
);
10882 fputs (REGISTER_PREFIX
, stream
);
10886 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10890 output_operand_lossage ("predicated Thumb instruction");
10893 if (current_insn_predicate
!= NULL
)
10895 output_operand_lossage
10896 ("predicated instruction in conditional sequence");
10900 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10902 else if (current_insn_predicate
)
10904 enum arm_cond_code code
;
10908 output_operand_lossage ("predicated Thumb instruction");
10912 code
= get_arm_condition_code (current_insn_predicate
);
10913 fputs (arm_condition_codes
[code
], stream
);
10920 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10921 r
= REAL_VALUE_NEGATE (r
);
10922 fprintf (stream
, "%s", fp_const_from_val (&r
));
10927 if (GET_CODE (x
) == CONST_INT
)
10930 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10931 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10935 putc ('~', stream
);
10936 output_addr_const (stream
, x
);
10941 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10944 /* Truncate Cirrus shift counts. */
10946 if (GET_CODE (x
) == CONST_INT
)
10948 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10951 arm_print_operand (stream
, x
, 0);
10955 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10961 const char * shift
= shift_op (x
, &val
);
10965 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10967 arm_print_operand (stream
, XEXP (x
, 1), 0);
10969 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10974 /* An explanation of the 'Q', 'R' and 'H' register operands:
10976 In a pair of registers containing a DI or DF value the 'Q'
10977 operand returns the register number of the register containing
10978 the least significant part of the value. The 'R' operand returns
10979 the register number of the register containing the most
10980 significant part of the value.
10982 The 'H' operand returns the higher of the two register numbers.
10983 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10984 same as the 'Q' operand, since the most significant part of the
10985 value is held in the lower number register. The reverse is true
10986 on systems where WORDS_BIG_ENDIAN is false.
10988 The purpose of these operands is to distinguish between cases
10989 where the endian-ness of the values is important (for example
10990 when they are added together), and cases where the endian-ness
10991 is irrelevant, but the order of register operations is important.
10992 For example when loading a value from memory into a register
10993 pair, the endian-ness does not matter. Provided that the value
10994 from the lower memory address is put into the lower numbered
10995 register, and the value from the higher address is put into the
10996 higher numbered register, the load will work regardless of whether
10997 the value being loaded is big-wordian or little-wordian. The
10998 order of the two register loads can matter however, if the address
10999 of the memory location is actually held in one of the registers
11000 being overwritten by the load. */
11002 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11004 output_operand_lossage ("invalid operand for code '%c'", code
);
11008 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11012 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11014 output_operand_lossage ("invalid operand for code '%c'", code
);
11018 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11022 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11024 output_operand_lossage ("invalid operand for code '%c'", code
);
11028 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11032 asm_fprintf (stream
, "%r",
11033 GET_CODE (XEXP (x
, 0)) == REG
11034 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11038 asm_fprintf (stream
, "{%r-%r}",
11040 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11044 /* CONST_TRUE_RTX means always -- that's the default. */
11045 if (x
== const_true_rtx
)
11048 if (!COMPARISON_P (x
))
11050 output_operand_lossage ("invalid operand for code '%c'", code
);
11054 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11059 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11060 want to do that. */
11061 if (x
== const_true_rtx
)
11063 output_operand_lossage ("instruction never exectued");
11066 if (!COMPARISON_P (x
))
11068 output_operand_lossage ("invalid operand for code '%c'", code
);
11072 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11073 (get_arm_condition_code (x
))],
11077 /* Cirrus registers can be accessed in a variety of ways:
11078 single floating point (f)
11079 double floating point (d)
11081 64bit integer (dx). */
11082 case 'W': /* Cirrus register in F mode. */
11083 case 'X': /* Cirrus register in D mode. */
11084 case 'Y': /* Cirrus register in FX mode. */
11085 case 'Z': /* Cirrus register in DX mode. */
11086 gcc_assert (GET_CODE (x
) == REG
11087 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11089 fprintf (stream
, "mv%s%s",
11091 : code
== 'X' ? "d"
11092 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11096 /* Print cirrus register in the mode specified by the register's mode. */
11099 int mode
= GET_MODE (x
);
11101 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11103 output_operand_lossage ("invalid operand for code '%c'", code
);
11107 fprintf (stream
, "mv%s%s",
11108 mode
== DFmode
? "d"
11109 : mode
== SImode
? "fx"
11110 : mode
== DImode
? "dx"
11111 : "f", reg_names
[REGNO (x
)] + 2);
11117 if (GET_CODE (x
) != REG
11118 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11119 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11120 /* Bad value for wCG register number. */
11122 output_operand_lossage ("invalid operand for code '%c'", code
);
11127 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11130 /* Print an iWMMXt control register name. */
11132 if (GET_CODE (x
) != CONST_INT
11134 || INTVAL (x
) >= 16)
11135 /* Bad value for wC register number. */
11137 output_operand_lossage ("invalid operand for code '%c'", code
);
11143 static const char * wc_reg_names
[16] =
11145 "wCID", "wCon", "wCSSF", "wCASF",
11146 "wC4", "wC5", "wC6", "wC7",
11147 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11148 "wC12", "wC13", "wC14", "wC15"
11151 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11155 /* Print a VFP double precision register name. */
11158 int mode
= GET_MODE (x
);
11161 if (mode
!= DImode
&& mode
!= DFmode
)
11163 output_operand_lossage ("invalid operand for code '%c'", code
);
11167 if (GET_CODE (x
) != REG
11168 || !IS_VFP_REGNUM (REGNO (x
)))
11170 output_operand_lossage ("invalid operand for code '%c'", code
);
11174 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11177 output_operand_lossage ("invalid operand for code '%c'", code
);
11181 fprintf (stream
, "d%d", num
>> 1);
11188 output_operand_lossage ("missing operand");
11192 switch (GET_CODE (x
))
11195 asm_fprintf (stream
, "%r", REGNO (x
));
11199 output_memory_reference_mode
= GET_MODE (x
);
11200 output_address (XEXP (x
, 0));
11204 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11208 gcc_assert (GET_CODE (x
) != NEG
);
11209 fputc ('#', stream
);
11210 output_addr_const (stream
, x
);
11216 #ifndef AOF_ASSEMBLER
11217 /* Target hook for assembling integer objects. The ARM version needs to
11218 handle word-sized values specially. */
11220 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11222 if (size
== UNITS_PER_WORD
&& aligned_p
)
11224 fputs ("\t.word\t", asm_out_file
);
11225 output_addr_const (asm_out_file
, x
);
11227 /* Mark symbols as position independent. We only do this in the
11228 .text segment, not in the .data segment. */
11229 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11230 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11232 if (GET_CODE (x
) == SYMBOL_REF
11233 && (CONSTANT_POOL_ADDRESS_P (x
)
11234 || SYMBOL_REF_LOCAL_P (x
)))
11235 fputs ("(GOTOFF)", asm_out_file
);
11236 else if (GET_CODE (x
) == LABEL_REF
)
11237 fputs ("(GOTOFF)", asm_out_file
);
11239 fputs ("(GOT)", asm_out_file
);
11241 fputc ('\n', asm_out_file
);
11245 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11249 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11251 units
= CONST_VECTOR_NUNITS (x
);
11253 switch (GET_MODE (x
))
11255 case V2SImode
: size
= 4; break;
11256 case V4HImode
: size
= 2; break;
11257 case V8QImode
: size
= 1; break;
11259 gcc_unreachable ();
11262 for (i
= 0; i
< units
; i
++)
11266 elt
= CONST_VECTOR_ELT (x
, i
);
11268 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11274 return default_assemble_integer (x
, size
, aligned_p
);
11278 /* Add a function to the list of static constructors. */
11281 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
11283 if (!TARGET_AAPCS_BASED
)
11285 default_named_section_asm_out_constructor (symbol
, priority
);
11289 /* Put these in the .init_array section, using a special relocation. */
11291 assemble_align (POINTER_SIZE
);
11292 fputs ("\t.word\t", asm_out_file
);
11293 output_addr_const (asm_out_file
, symbol
);
11294 fputs ("(target1)\n", asm_out_file
);
11298 /* A finite state machine takes care of noticing whether or not instructions
11299 can be conditionally executed, and thus decrease execution time and code
11300 size by deleting branch instructions. The fsm is controlled by
11301 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11303 /* The state of the fsm controlling condition codes are:
11304 0: normal, do nothing special
11305 1: make ASM_OUTPUT_OPCODE not output this instruction
11306 2: make ASM_OUTPUT_OPCODE not output this instruction
11307 3: make instructions conditional
11308 4: make instructions conditional
11310 State transitions (state->state by whom under condition):
11311 0 -> 1 final_prescan_insn if the `target' is a label
11312 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11313 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11314 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11315 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11316 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11317 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11318 (the target insn is arm_target_insn).
11320 If the jump clobbers the conditions then we use states 2 and 4.
11322 A similar thing can be done with conditional return insns.
11324 XXX In case the `target' is an unconditional branch, this conditionalising
11325 of the instructions always reduces code size, but not always execution
11326 time. But then, I want to reduce the code size to somewhere near what
11327 /bin/cc produces. */
11329 /* Returns the index of the ARM condition code string in
11330 `arm_condition_codes'. COMPARISON should be an rtx like
11331 `(eq (...) (...))'. */
11332 static enum arm_cond_code
11333 get_arm_condition_code (rtx comparison
)
11335 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11337 enum rtx_code comp_code
= GET_CODE (comparison
);
11339 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11340 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11341 XEXP (comparison
, 1));
11345 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11346 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11347 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11348 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11349 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11350 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11351 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11352 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11353 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11354 case CC_DLTUmode
: code
= ARM_CC
;
11357 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11359 if (comp_code
== EQ
)
11360 return ARM_INVERSE_CONDITION_CODE (code
);
11366 case NE
: return ARM_NE
;
11367 case EQ
: return ARM_EQ
;
11368 case GE
: return ARM_PL
;
11369 case LT
: return ARM_MI
;
11370 default: gcc_unreachable ();
11376 case NE
: return ARM_NE
;
11377 case EQ
: return ARM_EQ
;
11378 default: gcc_unreachable ();
11384 case NE
: return ARM_MI
;
11385 case EQ
: return ARM_PL
;
11386 default: gcc_unreachable ();
11391 /* These encodings assume that AC=1 in the FPA system control
11392 byte. This allows us to handle all cases except UNEQ and
11396 case GE
: return ARM_GE
;
11397 case GT
: return ARM_GT
;
11398 case LE
: return ARM_LS
;
11399 case LT
: return ARM_MI
;
11400 case NE
: return ARM_NE
;
11401 case EQ
: return ARM_EQ
;
11402 case ORDERED
: return ARM_VC
;
11403 case UNORDERED
: return ARM_VS
;
11404 case UNLT
: return ARM_LT
;
11405 case UNLE
: return ARM_LE
;
11406 case UNGT
: return ARM_HI
;
11407 case UNGE
: return ARM_PL
;
11408 /* UNEQ and LTGT do not have a representation. */
11409 case UNEQ
: /* Fall through. */
11410 case LTGT
: /* Fall through. */
11411 default: gcc_unreachable ();
11417 case NE
: return ARM_NE
;
11418 case EQ
: return ARM_EQ
;
11419 case GE
: return ARM_LE
;
11420 case GT
: return ARM_LT
;
11421 case LE
: return ARM_GE
;
11422 case LT
: return ARM_GT
;
11423 case GEU
: return ARM_LS
;
11424 case GTU
: return ARM_CC
;
11425 case LEU
: return ARM_CS
;
11426 case LTU
: return ARM_HI
;
11427 default: gcc_unreachable ();
11433 case LTU
: return ARM_CS
;
11434 case GEU
: return ARM_CC
;
11435 default: gcc_unreachable ();
11441 case NE
: return ARM_NE
;
11442 case EQ
: return ARM_EQ
;
11443 case GE
: return ARM_GE
;
11444 case GT
: return ARM_GT
;
11445 case LE
: return ARM_LE
;
11446 case LT
: return ARM_LT
;
11447 case GEU
: return ARM_CS
;
11448 case GTU
: return ARM_HI
;
11449 case LEU
: return ARM_LS
;
11450 case LTU
: return ARM_CC
;
11451 default: gcc_unreachable ();
11454 default: gcc_unreachable ();
11459 arm_final_prescan_insn (rtx insn
)
11461 /* BODY will hold the body of INSN. */
11462 rtx body
= PATTERN (insn
);
11464 /* This will be 1 if trying to repeat the trick, and things need to be
11465 reversed if it appears to fail. */
11468 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11469 taken are clobbered, even if the rtl suggests otherwise. It also
11470 means that we have to grub around within the jump expression to find
11471 out what the conditions are when the jump isn't taken. */
11472 int jump_clobbers
= 0;
11474 /* If we start with a return insn, we only succeed if we find another one. */
11475 int seeking_return
= 0;
11477 /* START_INSN will hold the insn from where we start looking. This is the
11478 first insn after the following code_label if REVERSE is true. */
11479 rtx start_insn
= insn
;
11481 /* If in state 4, check if the target branch is reached, in order to
11482 change back to state 0. */
11483 if (arm_ccfsm_state
== 4)
11485 if (insn
== arm_target_insn
)
11487 arm_target_insn
= NULL
;
11488 arm_ccfsm_state
= 0;
11493 /* If in state 3, it is possible to repeat the trick, if this insn is an
11494 unconditional branch to a label, and immediately following this branch
11495 is the previous target label which is only used once, and the label this
11496 branch jumps to is not too far off. */
11497 if (arm_ccfsm_state
== 3)
11499 if (simplejump_p (insn
))
11501 start_insn
= next_nonnote_insn (start_insn
);
11502 if (GET_CODE (start_insn
) == BARRIER
)
11504 /* XXX Isn't this always a barrier? */
11505 start_insn
= next_nonnote_insn (start_insn
);
11507 if (GET_CODE (start_insn
) == CODE_LABEL
11508 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11509 && LABEL_NUSES (start_insn
) == 1)
11514 else if (GET_CODE (body
) == RETURN
)
11516 start_insn
= next_nonnote_insn (start_insn
);
11517 if (GET_CODE (start_insn
) == BARRIER
)
11518 start_insn
= next_nonnote_insn (start_insn
);
11519 if (GET_CODE (start_insn
) == CODE_LABEL
11520 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11521 && LABEL_NUSES (start_insn
) == 1)
11524 seeking_return
= 1;
11533 gcc_assert (!arm_ccfsm_state
|| reverse
);
11534 if (GET_CODE (insn
) != JUMP_INSN
)
11537 /* This jump might be paralleled with a clobber of the condition codes
11538 the jump should always come first */
11539 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11540 body
= XVECEXP (body
, 0, 0);
11543 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11544 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11547 int fail
= FALSE
, succeed
= FALSE
;
11548 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11549 int then_not_else
= TRUE
;
11550 rtx this_insn
= start_insn
, label
= 0;
11552 /* If the jump cannot be done with one instruction, we cannot
11553 conditionally execute the instruction in the inverse case. */
11554 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11560 /* Register the insn jumped to. */
11563 if (!seeking_return
)
11564 label
= XEXP (SET_SRC (body
), 0);
11566 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11567 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11568 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11570 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11571 then_not_else
= FALSE
;
11573 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11574 seeking_return
= 1;
11575 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11577 seeking_return
= 1;
11578 then_not_else
= FALSE
;
11581 gcc_unreachable ();
11583 /* See how many insns this branch skips, and what kind of insns. If all
11584 insns are okay, and the label or unconditional branch to the same
11585 label is not too far away, succeed. */
11586 for (insns_skipped
= 0;
11587 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11591 this_insn
= next_nonnote_insn (this_insn
);
11595 switch (GET_CODE (this_insn
))
11598 /* Succeed if it is the target label, otherwise fail since
11599 control falls in from somewhere else. */
11600 if (this_insn
== label
)
11604 arm_ccfsm_state
= 2;
11605 this_insn
= next_nonnote_insn (this_insn
);
11608 arm_ccfsm_state
= 1;
11616 /* Succeed if the following insn is the target label.
11618 If return insns are used then the last insn in a function
11619 will be a barrier. */
11620 this_insn
= next_nonnote_insn (this_insn
);
11621 if (this_insn
&& this_insn
== label
)
11625 arm_ccfsm_state
= 2;
11626 this_insn
= next_nonnote_insn (this_insn
);
11629 arm_ccfsm_state
= 1;
11637 /* The AAPCS says that conditional calls should not be
11638 used since they make interworking inefficient (the
11639 linker can't transform BL<cond> into BLX). That's
11640 only a problem if the machine has BLX. */
11647 /* Succeed if the following insn is the target label, or
11648 if the following two insns are a barrier and the
11650 this_insn
= next_nonnote_insn (this_insn
);
11651 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11652 this_insn
= next_nonnote_insn (this_insn
);
11654 if (this_insn
&& this_insn
== label
11655 && insns_skipped
< max_insns_skipped
)
11659 arm_ccfsm_state
= 2;
11660 this_insn
= next_nonnote_insn (this_insn
);
11663 arm_ccfsm_state
= 1;
11671 /* If this is an unconditional branch to the same label, succeed.
11672 If it is to another label, do nothing. If it is conditional,
11674 /* XXX Probably, the tests for SET and the PC are
11677 scanbody
= PATTERN (this_insn
);
11678 if (GET_CODE (scanbody
) == SET
11679 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11681 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11682 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11684 arm_ccfsm_state
= 2;
11687 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11690 /* Fail if a conditional return is undesirable (e.g. on a
11691 StrongARM), but still allow this if optimizing for size. */
11692 else if (GET_CODE (scanbody
) == RETURN
11693 && !use_return_insn (TRUE
, NULL
)
11696 else if (GET_CODE (scanbody
) == RETURN
11699 arm_ccfsm_state
= 2;
11702 else if (GET_CODE (scanbody
) == PARALLEL
)
11704 switch (get_attr_conds (this_insn
))
11714 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11719 /* Instructions using or affecting the condition codes make it
11721 scanbody
= PATTERN (this_insn
);
11722 if (!(GET_CODE (scanbody
) == SET
11723 || GET_CODE (scanbody
) == PARALLEL
)
11724 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11727 /* A conditional cirrus instruction must be followed by
11728 a non Cirrus instruction. However, since we
11729 conditionalize instructions in this function and by
11730 the time we get here we can't add instructions
11731 (nops), because shorten_branches() has already been
11732 called, we will disable conditionalizing Cirrus
11733 instructions to be safe. */
11734 if (GET_CODE (scanbody
) != USE
11735 && GET_CODE (scanbody
) != CLOBBER
11736 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11746 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11747 arm_target_label
= CODE_LABEL_NUMBER (label
);
11750 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11752 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11754 this_insn
= next_nonnote_insn (this_insn
);
11755 gcc_assert (!this_insn
11756 || (GET_CODE (this_insn
) != BARRIER
11757 && GET_CODE (this_insn
) != CODE_LABEL
));
11761 /* Oh, dear! we ran off the end.. give up. */
11762 recog (PATTERN (insn
), insn
, NULL
);
11763 arm_ccfsm_state
= 0;
11764 arm_target_insn
= NULL
;
11767 arm_target_insn
= this_insn
;
11771 gcc_assert (!reverse
);
11773 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11775 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11776 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11777 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11778 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11782 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11785 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11789 if (reverse
|| then_not_else
)
11790 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11793 /* Restore recog_data (getting the attributes of other insns can
11794 destroy this array, but final.c assumes that it remains intact
11795 across this call; since the insn has been recognized already we
11796 call recog direct). */
11797 recog (PATTERN (insn
), insn
, NULL
);
11801 /* Returns true if REGNO is a valid register
11802 for holding a quantity of type MODE. */
11804 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11806 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11807 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11810 /* For the Thumb we only allow values bigger than SImode in
11811 registers 0 - 6, so that there is always a second low
11812 register available to hold the upper part of the value.
11813 We probably we ought to ensure that the register is the
11814 start of an even numbered register pair. */
11815 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11817 if (IS_CIRRUS_REGNUM (regno
))
11818 /* We have outlawed SI values in Cirrus registers because they
11819 reside in the lower 32 bits, but SF values reside in the
11820 upper 32 bits. This causes gcc all sorts of grief. We can't
11821 even split the registers into pairs because Cirrus SI values
11822 get sign extended to 64bits-- aldyh. */
11823 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11825 if (IS_VFP_REGNUM (regno
))
11827 if (mode
== SFmode
|| mode
== SImode
)
11830 /* DFmode values are only valid in even register pairs. */
11831 if (mode
== DFmode
)
11832 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11836 if (IS_IWMMXT_GR_REGNUM (regno
))
11837 return mode
== SImode
;
11839 if (IS_IWMMXT_REGNUM (regno
))
11840 return VALID_IWMMXT_REG_MODE (mode
);
11842 /* We allow any value to be stored in the general registers.
11843 Restrict doubleword quantities to even register pairs so that we can
11845 if (regno
<= LAST_ARM_REGNUM
)
11846 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11848 if ( regno
== FRAME_POINTER_REGNUM
11849 || regno
== ARG_POINTER_REGNUM
)
11850 /* We only allow integers in the fake hard registers. */
11851 return GET_MODE_CLASS (mode
) == MODE_INT
;
11853 /* The only registers left are the FPA registers
11854 which we only allow to hold FP values. */
11855 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11856 && regno
>= FIRST_FPA_REGNUM
11857 && regno
<= LAST_FPA_REGNUM
;
11861 arm_regno_class (int regno
)
11865 if (regno
== STACK_POINTER_REGNUM
)
11867 if (regno
== CC_REGNUM
)
11874 if ( regno
<= LAST_ARM_REGNUM
11875 || regno
== FRAME_POINTER_REGNUM
11876 || regno
== ARG_POINTER_REGNUM
)
11877 return GENERAL_REGS
;
11879 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11882 if (IS_CIRRUS_REGNUM (regno
))
11883 return CIRRUS_REGS
;
11885 if (IS_VFP_REGNUM (regno
))
11888 if (IS_IWMMXT_REGNUM (regno
))
11889 return IWMMXT_REGS
;
11891 if (IS_IWMMXT_GR_REGNUM (regno
))
11892 return IWMMXT_GR_REGS
;
11897 /* Handle a special case when computing the offset
11898 of an argument from the frame pointer. */
11900 arm_debugger_arg_offset (int value
, rtx addr
)
11904 /* We are only interested if dbxout_parms() failed to compute the offset. */
11908 /* We can only cope with the case where the address is held in a register. */
11909 if (GET_CODE (addr
) != REG
)
11912 /* If we are using the frame pointer to point at the argument, then
11913 an offset of 0 is correct. */
11914 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11917 /* If we are using the stack pointer to point at the
11918 argument, then an offset of 0 is correct. */
11919 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11920 && REGNO (addr
) == SP_REGNUM
)
11923 /* Oh dear. The argument is pointed to by a register rather
11924 than being held in a register, or being stored at a known
11925 offset from the frame pointer. Since GDB only understands
11926 those two kinds of argument we must translate the address
11927 held in the register into an offset from the frame pointer.
11928 We do this by searching through the insns for the function
11929 looking to see where this register gets its value. If the
11930 register is initialized from the frame pointer plus an offset
11931 then we are in luck and we can continue, otherwise we give up.
11933 This code is exercised by producing debugging information
11934 for a function with arguments like this:
11936 double func (double a, double b, int c, double d) {return d;}
11938 Without this code the stab for parameter 'd' will be set to
11939 an offset of 0 from the frame pointer, rather than 8. */
11941 /* The if() statement says:
11943 If the insn is a normal instruction
11944 and if the insn is setting the value in a register
11945 and if the register being set is the register holding the address of the argument
11946 and if the address is computing by an addition
11947 that involves adding to a register
11948 which is the frame pointer
11953 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11955 if ( GET_CODE (insn
) == INSN
11956 && GET_CODE (PATTERN (insn
)) == SET
11957 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11958 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11959 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11960 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11961 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11964 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11973 warning (0, "unable to compute real location of stacked parameter");
11974 value
= 8; /* XXX magic hack */
11980 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11983 if ((MASK) & insn_flags) \
11984 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11985 BUILT_IN_MD, NULL, NULL_TREE); \
11989 struct builtin_description
11991 const unsigned int mask
;
11992 const enum insn_code icode
;
11993 const char * const name
;
11994 const enum arm_builtins code
;
11995 const enum rtx_code comparison
;
11996 const unsigned int flag
;
11999 static const struct builtin_description bdesc_2arg
[] =
12001 #define IWMMXT_BUILTIN(code, string, builtin) \
12002 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12003 ARM_BUILTIN_##builtin, 0, 0 },
12005 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12006 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12007 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12008 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12009 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12010 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12011 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12012 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12013 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12014 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12015 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12016 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12017 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12018 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12019 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12020 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12021 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12022 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12023 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12024 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12025 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12026 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12027 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12028 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12029 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12030 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12031 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12032 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12033 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12034 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12035 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12036 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12037 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12038 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12039 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12040 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12041 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12042 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12043 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12044 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12045 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12046 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12047 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12048 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12049 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12050 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12051 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12052 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12053 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12054 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12055 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12056 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12057 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12058 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12059 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12060 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12061 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12062 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12064 #define IWMMXT_BUILTIN2(code, builtin) \
12065 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12067 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12068 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12069 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12070 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12071 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12072 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12073 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12074 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12075 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12076 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12077 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12078 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12079 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12080 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12081 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12082 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12083 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12084 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12085 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12086 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12087 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12088 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12089 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12090 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12091 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12092 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12093 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12094 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12095 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12096 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12097 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12098 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12101 static const struct builtin_description bdesc_1arg
[] =
12103 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12104 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12105 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12106 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12107 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12108 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12109 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12110 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12111 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12112 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12113 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12114 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12115 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12116 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12117 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12118 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12119 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12120 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12123 /* Set up all the iWMMXt builtins. This is
12124 not called if TARGET_IWMMXT is zero. */
12127 arm_init_iwmmxt_builtins (void)
12129 const struct builtin_description
* d
;
12131 tree endlink
= void_list_node
;
12133 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12134 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12135 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12138 = build_function_type (integer_type_node
,
12139 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12140 tree v8qi_ftype_v8qi_v8qi_int
12141 = build_function_type (V8QI_type_node
,
12142 tree_cons (NULL_TREE
, V8QI_type_node
,
12143 tree_cons (NULL_TREE
, V8QI_type_node
,
12144 tree_cons (NULL_TREE
,
12147 tree v4hi_ftype_v4hi_int
12148 = build_function_type (V4HI_type_node
,
12149 tree_cons (NULL_TREE
, V4HI_type_node
,
12150 tree_cons (NULL_TREE
, integer_type_node
,
12152 tree v2si_ftype_v2si_int
12153 = build_function_type (V2SI_type_node
,
12154 tree_cons (NULL_TREE
, V2SI_type_node
,
12155 tree_cons (NULL_TREE
, integer_type_node
,
12157 tree v2si_ftype_di_di
12158 = build_function_type (V2SI_type_node
,
12159 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12160 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12162 tree di_ftype_di_int
12163 = build_function_type (long_long_integer_type_node
,
12164 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12165 tree_cons (NULL_TREE
, integer_type_node
,
12167 tree di_ftype_di_int_int
12168 = build_function_type (long_long_integer_type_node
,
12169 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12170 tree_cons (NULL_TREE
, integer_type_node
,
12171 tree_cons (NULL_TREE
,
12174 tree int_ftype_v8qi
12175 = build_function_type (integer_type_node
,
12176 tree_cons (NULL_TREE
, V8QI_type_node
,
12178 tree int_ftype_v4hi
12179 = build_function_type (integer_type_node
,
12180 tree_cons (NULL_TREE
, V4HI_type_node
,
12182 tree int_ftype_v2si
12183 = build_function_type (integer_type_node
,
12184 tree_cons (NULL_TREE
, V2SI_type_node
,
12186 tree int_ftype_v8qi_int
12187 = build_function_type (integer_type_node
,
12188 tree_cons (NULL_TREE
, V8QI_type_node
,
12189 tree_cons (NULL_TREE
, integer_type_node
,
12191 tree int_ftype_v4hi_int
12192 = build_function_type (integer_type_node
,
12193 tree_cons (NULL_TREE
, V4HI_type_node
,
12194 tree_cons (NULL_TREE
, integer_type_node
,
12196 tree int_ftype_v2si_int
12197 = build_function_type (integer_type_node
,
12198 tree_cons (NULL_TREE
, V2SI_type_node
,
12199 tree_cons (NULL_TREE
, integer_type_node
,
12201 tree v8qi_ftype_v8qi_int_int
12202 = build_function_type (V8QI_type_node
,
12203 tree_cons (NULL_TREE
, V8QI_type_node
,
12204 tree_cons (NULL_TREE
, integer_type_node
,
12205 tree_cons (NULL_TREE
,
12208 tree v4hi_ftype_v4hi_int_int
12209 = build_function_type (V4HI_type_node
,
12210 tree_cons (NULL_TREE
, V4HI_type_node
,
12211 tree_cons (NULL_TREE
, integer_type_node
,
12212 tree_cons (NULL_TREE
,
12215 tree v2si_ftype_v2si_int_int
12216 = build_function_type (V2SI_type_node
,
12217 tree_cons (NULL_TREE
, V2SI_type_node
,
12218 tree_cons (NULL_TREE
, integer_type_node
,
12219 tree_cons (NULL_TREE
,
12222 /* Miscellaneous. */
12223 tree v8qi_ftype_v4hi_v4hi
12224 = build_function_type (V8QI_type_node
,
12225 tree_cons (NULL_TREE
, V4HI_type_node
,
12226 tree_cons (NULL_TREE
, V4HI_type_node
,
12228 tree v4hi_ftype_v2si_v2si
12229 = build_function_type (V4HI_type_node
,
12230 tree_cons (NULL_TREE
, V2SI_type_node
,
12231 tree_cons (NULL_TREE
, V2SI_type_node
,
12233 tree v2si_ftype_v4hi_v4hi
12234 = build_function_type (V2SI_type_node
,
12235 tree_cons (NULL_TREE
, V4HI_type_node
,
12236 tree_cons (NULL_TREE
, V4HI_type_node
,
12238 tree v2si_ftype_v8qi_v8qi
12239 = build_function_type (V2SI_type_node
,
12240 tree_cons (NULL_TREE
, V8QI_type_node
,
12241 tree_cons (NULL_TREE
, V8QI_type_node
,
12243 tree v4hi_ftype_v4hi_di
12244 = build_function_type (V4HI_type_node
,
12245 tree_cons (NULL_TREE
, V4HI_type_node
,
12246 tree_cons (NULL_TREE
,
12247 long_long_integer_type_node
,
12249 tree v2si_ftype_v2si_di
12250 = build_function_type (V2SI_type_node
,
12251 tree_cons (NULL_TREE
, V2SI_type_node
,
12252 tree_cons (NULL_TREE
,
12253 long_long_integer_type_node
,
12255 tree void_ftype_int_int
12256 = build_function_type (void_type_node
,
12257 tree_cons (NULL_TREE
, integer_type_node
,
12258 tree_cons (NULL_TREE
, integer_type_node
,
12261 = build_function_type (long_long_unsigned_type_node
, endlink
);
12263 = build_function_type (long_long_integer_type_node
,
12264 tree_cons (NULL_TREE
, V8QI_type_node
,
12267 = build_function_type (long_long_integer_type_node
,
12268 tree_cons (NULL_TREE
, V4HI_type_node
,
12271 = build_function_type (long_long_integer_type_node
,
12272 tree_cons (NULL_TREE
, V2SI_type_node
,
12274 tree v2si_ftype_v4hi
12275 = build_function_type (V2SI_type_node
,
12276 tree_cons (NULL_TREE
, V4HI_type_node
,
12278 tree v4hi_ftype_v8qi
12279 = build_function_type (V4HI_type_node
,
12280 tree_cons (NULL_TREE
, V8QI_type_node
,
12283 tree di_ftype_di_v4hi_v4hi
12284 = build_function_type (long_long_unsigned_type_node
,
12285 tree_cons (NULL_TREE
,
12286 long_long_unsigned_type_node
,
12287 tree_cons (NULL_TREE
, V4HI_type_node
,
12288 tree_cons (NULL_TREE
,
12292 tree di_ftype_v4hi_v4hi
12293 = build_function_type (long_long_unsigned_type_node
,
12294 tree_cons (NULL_TREE
, V4HI_type_node
,
12295 tree_cons (NULL_TREE
, V4HI_type_node
,
12298 /* Normal vector binops. */
12299 tree v8qi_ftype_v8qi_v8qi
12300 = build_function_type (V8QI_type_node
,
12301 tree_cons (NULL_TREE
, V8QI_type_node
,
12302 tree_cons (NULL_TREE
, V8QI_type_node
,
12304 tree v4hi_ftype_v4hi_v4hi
12305 = build_function_type (V4HI_type_node
,
12306 tree_cons (NULL_TREE
, V4HI_type_node
,
12307 tree_cons (NULL_TREE
, V4HI_type_node
,
12309 tree v2si_ftype_v2si_v2si
12310 = build_function_type (V2SI_type_node
,
12311 tree_cons (NULL_TREE
, V2SI_type_node
,
12312 tree_cons (NULL_TREE
, V2SI_type_node
,
12314 tree di_ftype_di_di
12315 = build_function_type (long_long_unsigned_type_node
,
12316 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12317 tree_cons (NULL_TREE
,
12318 long_long_unsigned_type_node
,
12321 /* Add all builtins that are more or less simple operations on two
12323 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12325 /* Use one of the operands; the target can have a different mode for
12326 mask-generating compares. */
12327 enum machine_mode mode
;
12333 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12338 type
= v8qi_ftype_v8qi_v8qi
;
12341 type
= v4hi_ftype_v4hi_v4hi
;
12344 type
= v2si_ftype_v2si_v2si
;
12347 type
= di_ftype_di_di
;
12351 gcc_unreachable ();
12354 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12357 /* Add the remaining MMX insns with somewhat more complicated types. */
12358 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12359 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12360 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12362 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12363 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12364 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12365 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12366 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12367 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12369 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12370 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12371 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12372 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12373 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12374 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12376 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12377 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12378 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12379 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12380 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12381 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12383 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12384 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12385 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12386 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12387 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12388 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12390 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12392 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12393 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12394 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12395 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12397 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12398 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12399 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12400 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12401 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12402 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12403 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12404 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12405 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12407 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12408 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12409 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12411 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12412 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12413 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12415 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12416 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12417 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12418 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12419 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12420 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12422 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12423 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12424 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12425 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12426 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12427 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12428 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12429 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12430 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12431 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12432 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12433 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12435 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12436 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12437 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12438 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12440 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12441 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12442 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12443 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12444 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12445 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12446 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12450 arm_init_tls_builtins (void)
12453 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
12454 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
12456 ftype
= build_function_type (ptr_type_node
, void_list_node
);
12457 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
12458 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
12459 NULL
, const_nothrow
);
12463 arm_init_builtins (void)
12465 arm_init_tls_builtins ();
12467 if (TARGET_REALLY_IWMMXT
)
12468 arm_init_iwmmxt_builtins ();
12471 /* Errors in the source file can cause expand_expr to return const0_rtx
12472 where we expect a vector. To avoid crashing, use one of the vector
12473 clear instructions. */
12476 safe_vector_operand (rtx x
, enum machine_mode mode
)
12478 if (x
!= const0_rtx
)
12480 x
= gen_reg_rtx (mode
);
12482 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12483 : gen_rtx_SUBREG (DImode
, x
, 0)));
12487 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12490 arm_expand_binop_builtin (enum insn_code icode
,
12491 tree arglist
, rtx target
)
12494 tree arg0
= TREE_VALUE (arglist
);
12495 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12496 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12497 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12498 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12499 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12500 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12502 if (VECTOR_MODE_P (mode0
))
12503 op0
= safe_vector_operand (op0
, mode0
);
12504 if (VECTOR_MODE_P (mode1
))
12505 op1
= safe_vector_operand (op1
, mode1
);
12508 || GET_MODE (target
) != tmode
12509 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12510 target
= gen_reg_rtx (tmode
);
12512 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12514 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12515 op0
= copy_to_mode_reg (mode0
, op0
);
12516 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12517 op1
= copy_to_mode_reg (mode1
, op1
);
12519 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12526 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12529 arm_expand_unop_builtin (enum insn_code icode
,
12530 tree arglist
, rtx target
, int do_load
)
12533 tree arg0
= TREE_VALUE (arglist
);
12534 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12535 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12536 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12539 || GET_MODE (target
) != tmode
12540 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12541 target
= gen_reg_rtx (tmode
);
12543 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12546 if (VECTOR_MODE_P (mode0
))
12547 op0
= safe_vector_operand (op0
, mode0
);
12549 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12550 op0
= copy_to_mode_reg (mode0
, op0
);
12553 pat
= GEN_FCN (icode
) (target
, op0
);
12560 /* Expand an expression EXP that calls a built-in function,
12561 with result going to TARGET if that's convenient
12562 (and in mode MODE if that's convenient).
12563 SUBTARGET may be used as the target for computing one of EXP's operands.
12564 IGNORE is nonzero if the value is to be ignored. */
12567 arm_expand_builtin (tree exp
,
12569 rtx subtarget ATTRIBUTE_UNUSED
,
12570 enum machine_mode mode ATTRIBUTE_UNUSED
,
12571 int ignore ATTRIBUTE_UNUSED
)
12573 const struct builtin_description
* d
;
12574 enum insn_code icode
;
12575 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12576 tree arglist
= TREE_OPERAND (exp
, 1);
12584 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12586 enum machine_mode tmode
;
12587 enum machine_mode mode0
;
12588 enum machine_mode mode1
;
12589 enum machine_mode mode2
;
12593 case ARM_BUILTIN_TEXTRMSB
:
12594 case ARM_BUILTIN_TEXTRMUB
:
12595 case ARM_BUILTIN_TEXTRMSH
:
12596 case ARM_BUILTIN_TEXTRMUH
:
12597 case ARM_BUILTIN_TEXTRMSW
:
12598 case ARM_BUILTIN_TEXTRMUW
:
12599 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12600 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12601 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12602 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12603 : CODE_FOR_iwmmxt_textrmw
);
12605 arg0
= TREE_VALUE (arglist
);
12606 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12607 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12608 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12609 tmode
= insn_data
[icode
].operand
[0].mode
;
12610 mode0
= insn_data
[icode
].operand
[1].mode
;
12611 mode1
= insn_data
[icode
].operand
[2].mode
;
12613 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12614 op0
= copy_to_mode_reg (mode0
, op0
);
12615 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12617 /* @@@ better error message */
12618 error ("selector must be an immediate");
12619 return gen_reg_rtx (tmode
);
12622 || GET_MODE (target
) != tmode
12623 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12624 target
= gen_reg_rtx (tmode
);
12625 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12631 case ARM_BUILTIN_TINSRB
:
12632 case ARM_BUILTIN_TINSRH
:
12633 case ARM_BUILTIN_TINSRW
:
12634 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12635 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12636 : CODE_FOR_iwmmxt_tinsrw
);
12637 arg0
= TREE_VALUE (arglist
);
12638 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12639 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12640 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12641 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12642 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12643 tmode
= insn_data
[icode
].operand
[0].mode
;
12644 mode0
= insn_data
[icode
].operand
[1].mode
;
12645 mode1
= insn_data
[icode
].operand
[2].mode
;
12646 mode2
= insn_data
[icode
].operand
[3].mode
;
12648 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12649 op0
= copy_to_mode_reg (mode0
, op0
);
12650 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12651 op1
= copy_to_mode_reg (mode1
, op1
);
12652 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12654 /* @@@ better error message */
12655 error ("selector must be an immediate");
12659 || GET_MODE (target
) != tmode
12660 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12661 target
= gen_reg_rtx (tmode
);
12662 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12668 case ARM_BUILTIN_SETWCX
:
12669 arg0
= TREE_VALUE (arglist
);
12670 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12671 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12672 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12673 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12676 case ARM_BUILTIN_GETWCX
:
12677 arg0
= TREE_VALUE (arglist
);
12678 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12679 target
= gen_reg_rtx (SImode
);
12680 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12683 case ARM_BUILTIN_WSHUFH
:
12684 icode
= CODE_FOR_iwmmxt_wshufh
;
12685 arg0
= TREE_VALUE (arglist
);
12686 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12687 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12688 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12689 tmode
= insn_data
[icode
].operand
[0].mode
;
12690 mode1
= insn_data
[icode
].operand
[1].mode
;
12691 mode2
= insn_data
[icode
].operand
[2].mode
;
12693 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12694 op0
= copy_to_mode_reg (mode1
, op0
);
12695 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12697 /* @@@ better error message */
12698 error ("mask must be an immediate");
12702 || GET_MODE (target
) != tmode
12703 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12704 target
= gen_reg_rtx (tmode
);
12705 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12711 case ARM_BUILTIN_WSADB
:
12712 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12713 case ARM_BUILTIN_WSADH
:
12714 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12715 case ARM_BUILTIN_WSADBZ
:
12716 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12717 case ARM_BUILTIN_WSADHZ
:
12718 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12720 /* Several three-argument builtins. */
12721 case ARM_BUILTIN_WMACS
:
12722 case ARM_BUILTIN_WMACU
:
12723 case ARM_BUILTIN_WALIGN
:
12724 case ARM_BUILTIN_TMIA
:
12725 case ARM_BUILTIN_TMIAPH
:
12726 case ARM_BUILTIN_TMIATT
:
12727 case ARM_BUILTIN_TMIATB
:
12728 case ARM_BUILTIN_TMIABT
:
12729 case ARM_BUILTIN_TMIABB
:
12730 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12731 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12732 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12733 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12734 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12735 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12736 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12737 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12738 : CODE_FOR_iwmmxt_walign
);
12739 arg0
= TREE_VALUE (arglist
);
12740 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12741 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12742 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12743 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12744 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12745 tmode
= insn_data
[icode
].operand
[0].mode
;
12746 mode0
= insn_data
[icode
].operand
[1].mode
;
12747 mode1
= insn_data
[icode
].operand
[2].mode
;
12748 mode2
= insn_data
[icode
].operand
[3].mode
;
12750 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12751 op0
= copy_to_mode_reg (mode0
, op0
);
12752 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12753 op1
= copy_to_mode_reg (mode1
, op1
);
12754 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12755 op2
= copy_to_mode_reg (mode2
, op2
);
12757 || GET_MODE (target
) != tmode
12758 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12759 target
= gen_reg_rtx (tmode
);
12760 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12766 case ARM_BUILTIN_WZERO
:
12767 target
= gen_reg_rtx (DImode
);
12768 emit_insn (gen_iwmmxt_clrdi (target
));
12771 case ARM_BUILTIN_THREAD_POINTER
:
12772 return arm_load_tp (target
);
12778 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12779 if (d
->code
== (const enum arm_builtins
) fcode
)
12780 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12782 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12783 if (d
->code
== (const enum arm_builtins
) fcode
)
12784 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12786 /* @@@ Should really do something sensible here. */
12790 /* Return the number (counting from 0) of
12791 the least significant set bit in MASK. */
12794 number_of_first_bit_set (unsigned mask
)
12799 (mask
& (1 << bit
)) == 0;
12806 /* Emit code to push or pop registers to or from the stack. F is the
12807 assembly file. MASK is the registers to push or pop. PUSH is
12808 nonzero if we should push, and zero if we should pop. For debugging
12809 output, if pushing, adjust CFA_OFFSET by the amount of space added
12810 to the stack. REAL_REGS should have the same number of bits set as
12811 MASK, and will be used instead (in the same order) to describe which
12812 registers were saved - this is used to mark the save slots when we
12813 push high registers after moving them to low registers. */
12815 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12816 unsigned long real_regs
)
12819 int lo_mask
= mask
& 0xFF;
12820 int pushed_words
= 0;
12824 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12826 /* Special case. Do not generate a POP PC statement here, do it in
12828 thumb_exit (f
, -1);
12832 if (ARM_EABI_UNWIND_TABLES
&& push
)
12834 fprintf (f
, "\t.save\t{");
12835 for (regno
= 0; regno
< 15; regno
++)
12837 if (real_regs
& (1 << regno
))
12839 if (real_regs
& ((1 << regno
) -1))
12841 asm_fprintf (f
, "%r", regno
);
12844 fprintf (f
, "}\n");
12847 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12849 /* Look at the low registers first. */
12850 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12854 asm_fprintf (f
, "%r", regno
);
12856 if ((lo_mask
& ~1) != 0)
12863 if (push
&& (mask
& (1 << LR_REGNUM
)))
12865 /* Catch pushing the LR. */
12869 asm_fprintf (f
, "%r", LR_REGNUM
);
12873 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12875 /* Catch popping the PC. */
12876 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12877 || current_function_calls_eh_return
)
12879 /* The PC is never poped directly, instead
12880 it is popped into r3 and then BX is used. */
12881 fprintf (f
, "}\n");
12883 thumb_exit (f
, -1);
12892 asm_fprintf (f
, "%r", PC_REGNUM
);
12896 fprintf (f
, "}\n");
12898 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12900 char *l
= dwarf2out_cfi_label ();
12901 int pushed_mask
= real_regs
;
12903 *cfa_offset
+= pushed_words
* 4;
12904 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12907 pushed_mask
= real_regs
;
12908 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12910 if (pushed_mask
& 1)
12911 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12916 /* Generate code to return from a thumb function.
12917 If 'reg_containing_return_addr' is -1, then the return address is
12918 actually on the stack, at the stack pointer. */
12920 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12922 unsigned regs_available_for_popping
;
12923 unsigned regs_to_pop
;
12925 unsigned available
;
12929 int restore_a4
= FALSE
;
12931 /* Compute the registers we need to pop. */
12935 if (reg_containing_return_addr
== -1)
12937 regs_to_pop
|= 1 << LR_REGNUM
;
12941 if (TARGET_BACKTRACE
)
12943 /* Restore the (ARM) frame pointer and stack pointer. */
12944 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12948 /* If there is nothing to pop then just emit the BX instruction and
12950 if (pops_needed
== 0)
12952 if (current_function_calls_eh_return
)
12953 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12955 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12958 /* Otherwise if we are not supporting interworking and we have not created
12959 a backtrace structure and the function was not entered in ARM mode then
12960 just pop the return address straight into the PC. */
12961 else if (!TARGET_INTERWORK
12962 && !TARGET_BACKTRACE
12963 && !is_called_in_ARM_mode (current_function_decl
)
12964 && !current_function_calls_eh_return
)
12966 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12970 /* Find out how many of the (return) argument registers we can corrupt. */
12971 regs_available_for_popping
= 0;
12973 /* If returning via __builtin_eh_return, the bottom three registers
12974 all contain information needed for the return. */
12975 if (current_function_calls_eh_return
)
12979 /* If we can deduce the registers used from the function's
12980 return value. This is more reliable that examining
12981 regs_ever_live[] because that will be set if the register is
12982 ever used in the function, not just if the register is used
12983 to hold a return value. */
12985 if (current_function_return_rtx
!= 0)
12986 mode
= GET_MODE (current_function_return_rtx
);
12988 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12990 size
= GET_MODE_SIZE (mode
);
12994 /* In a void function we can use any argument register.
12995 In a function that returns a structure on the stack
12996 we can use the second and third argument registers. */
12997 if (mode
== VOIDmode
)
12998 regs_available_for_popping
=
12999 (1 << ARG_REGISTER (1))
13000 | (1 << ARG_REGISTER (2))
13001 | (1 << ARG_REGISTER (3));
13003 regs_available_for_popping
=
13004 (1 << ARG_REGISTER (2))
13005 | (1 << ARG_REGISTER (3));
13007 else if (size
<= 4)
13008 regs_available_for_popping
=
13009 (1 << ARG_REGISTER (2))
13010 | (1 << ARG_REGISTER (3));
13011 else if (size
<= 8)
13012 regs_available_for_popping
=
13013 (1 << ARG_REGISTER (3));
13016 /* Match registers to be popped with registers into which we pop them. */
13017 for (available
= regs_available_for_popping
,
13018 required
= regs_to_pop
;
13019 required
!= 0 && available
!= 0;
13020 available
&= ~(available
& - available
),
13021 required
&= ~(required
& - required
))
13024 /* If we have any popping registers left over, remove them. */
13026 regs_available_for_popping
&= ~available
;
13028 /* Otherwise if we need another popping register we can use
13029 the fourth argument register. */
13030 else if (pops_needed
)
13032 /* If we have not found any free argument registers and
13033 reg a4 contains the return address, we must move it. */
13034 if (regs_available_for_popping
== 0
13035 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13037 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13038 reg_containing_return_addr
= LR_REGNUM
;
13040 else if (size
> 12)
13042 /* Register a4 is being used to hold part of the return value,
13043 but we have dire need of a free, low register. */
13046 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13049 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13051 /* The fourth argument register is available. */
13052 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13058 /* Pop as many registers as we can. */
13059 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13060 regs_available_for_popping
);
13062 /* Process the registers we popped. */
13063 if (reg_containing_return_addr
== -1)
13065 /* The return address was popped into the lowest numbered register. */
13066 regs_to_pop
&= ~(1 << LR_REGNUM
);
13068 reg_containing_return_addr
=
13069 number_of_first_bit_set (regs_available_for_popping
);
13071 /* Remove this register for the mask of available registers, so that
13072 the return address will not be corrupted by further pops. */
13073 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13076 /* If we popped other registers then handle them here. */
13077 if (regs_available_for_popping
)
13081 /* Work out which register currently contains the frame pointer. */
13082 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13084 /* Move it into the correct place. */
13085 asm_fprintf (f
, "\tmov\t%r, %r\n",
13086 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13088 /* (Temporarily) remove it from the mask of popped registers. */
13089 regs_available_for_popping
&= ~(1 << frame_pointer
);
13090 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13092 if (regs_available_for_popping
)
13096 /* We popped the stack pointer as well,
13097 find the register that contains it. */
13098 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13100 /* Move it into the stack register. */
13101 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13103 /* At this point we have popped all necessary registers, so
13104 do not worry about restoring regs_available_for_popping
13105 to its correct value:
13107 assert (pops_needed == 0)
13108 assert (regs_available_for_popping == (1 << frame_pointer))
13109 assert (regs_to_pop == (1 << STACK_POINTER)) */
13113 /* Since we have just move the popped value into the frame
13114 pointer, the popping register is available for reuse, and
13115 we know that we still have the stack pointer left to pop. */
13116 regs_available_for_popping
|= (1 << frame_pointer
);
13120 /* If we still have registers left on the stack, but we no longer have
13121 any registers into which we can pop them, then we must move the return
13122 address into the link register and make available the register that
13124 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13126 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13128 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13129 reg_containing_return_addr
);
13131 reg_containing_return_addr
= LR_REGNUM
;
13134 /* If we have registers left on the stack then pop some more.
13135 We know that at most we will want to pop FP and SP. */
13136 if (pops_needed
> 0)
13141 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13142 regs_available_for_popping
);
13144 /* We have popped either FP or SP.
13145 Move whichever one it is into the correct register. */
13146 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13147 move_to
= number_of_first_bit_set (regs_to_pop
);
13149 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13151 regs_to_pop
&= ~(1 << move_to
);
13156 /* If we still have not popped everything then we must have only
13157 had one register available to us and we are now popping the SP. */
13158 if (pops_needed
> 0)
13162 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13163 regs_available_for_popping
);
13165 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13167 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13169 assert (regs_to_pop == (1 << STACK_POINTER))
13170 assert (pops_needed == 1)
13174 /* If necessary restore the a4 register. */
13177 if (reg_containing_return_addr
!= LR_REGNUM
)
13179 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13180 reg_containing_return_addr
= LR_REGNUM
;
13183 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13186 if (current_function_calls_eh_return
)
13187 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13189 /* Return to caller. */
13190 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13195 thumb_final_prescan_insn (rtx insn
)
13197 if (flag_print_asm_name
)
13198 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
13199 INSN_ADDRESSES (INSN_UID (insn
)));
13203 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
13205 unsigned HOST_WIDE_INT mask
= 0xff;
13208 if (val
== 0) /* XXX */
13211 for (i
= 0; i
< 25; i
++)
13212 if ((val
& (mask
<< i
)) == val
)
13218 /* Returns nonzero if the current function contains,
13219 or might contain a far jump. */
13221 thumb_far_jump_used_p (void)
13225 /* This test is only important for leaf functions. */
13226 /* assert (!leaf_function_p ()); */
13228 /* If we have already decided that far jumps may be used,
13229 do not bother checking again, and always return true even if
13230 it turns out that they are not being used. Once we have made
13231 the decision that far jumps are present (and that hence the link
13232 register will be pushed onto the stack) we cannot go back on it. */
13233 if (cfun
->machine
->far_jump_used
)
13236 /* If this function is not being called from the prologue/epilogue
13237 generation code then it must be being called from the
13238 INITIAL_ELIMINATION_OFFSET macro. */
13239 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13241 /* In this case we know that we are being asked about the elimination
13242 of the arg pointer register. If that register is not being used,
13243 then there are no arguments on the stack, and we do not have to
13244 worry that a far jump might force the prologue to push the link
13245 register, changing the stack offsets. In this case we can just
13246 return false, since the presence of far jumps in the function will
13247 not affect stack offsets.
13249 If the arg pointer is live (or if it was live, but has now been
13250 eliminated and so set to dead) then we do have to test to see if
13251 the function might contain a far jump. This test can lead to some
13252 false negatives, since before reload is completed, then length of
13253 branch instructions is not known, so gcc defaults to returning their
13254 longest length, which in turn sets the far jump attribute to true.
13256 A false negative will not result in bad code being generated, but it
13257 will result in a needless push and pop of the link register. We
13258 hope that this does not occur too often.
13260 If we need doubleword stack alignment this could affect the other
13261 elimination offsets so we can't risk getting it wrong. */
13262 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13263 cfun
->machine
->arg_pointer_live
= 1;
13264 else if (!cfun
->machine
->arg_pointer_live
)
13268 /* Check to see if the function contains a branch
13269 insn with the far jump attribute set. */
13270 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13272 if (GET_CODE (insn
) == JUMP_INSN
13273 /* Ignore tablejump patterns. */
13274 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13275 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13276 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13279 /* Record the fact that we have decided that
13280 the function does use far jumps. */
13281 cfun
->machine
->far_jump_used
= 1;
13289 /* Return nonzero if FUNC must be entered in ARM mode. */
13291 is_called_in_ARM_mode (tree func
)
13293 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
13295 /* Ignore the problem about functions whose address is taken. */
13296 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13300 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13306 /* The bits which aren't usefully expanded as rtl. */
13308 thumb_unexpanded_epilogue (void)
13311 unsigned long live_regs_mask
= 0;
13312 int high_regs_pushed
= 0;
13313 int had_to_push_lr
;
13316 if (return_used_this_function
)
13319 if (IS_NAKED (arm_current_func_type ()))
13322 live_regs_mask
= thumb_compute_save_reg_mask ();
13323 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13325 /* If we can deduce the registers used from the function's return value.
13326 This is more reliable that examining regs_ever_live[] because that
13327 will be set if the register is ever used in the function, not just if
13328 the register is used to hold a return value. */
13329 size
= arm_size_return_regs ();
13331 /* The prolog may have pushed some high registers to use as
13332 work registers. e.g. the testsuite file:
13333 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13334 compiles to produce:
13335 push {r4, r5, r6, r7, lr}
13339 as part of the prolog. We have to undo that pushing here. */
13341 if (high_regs_pushed
)
13343 unsigned long mask
= live_regs_mask
& 0xff;
13346 /* The available low registers depend on the size of the value we are
13354 /* Oh dear! We have no low registers into which we can pop
13357 ("no low registers available for popping high registers");
13359 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13360 if (live_regs_mask
& (1 << next_hi_reg
))
13363 while (high_regs_pushed
)
13365 /* Find lo register(s) into which the high register(s) can
13367 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13369 if (mask
& (1 << regno
))
13370 high_regs_pushed
--;
13371 if (high_regs_pushed
== 0)
13375 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13377 /* Pop the values into the low register(s). */
13378 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13380 /* Move the value(s) into the high registers. */
13381 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13383 if (mask
& (1 << regno
))
13385 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13388 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13389 if (live_regs_mask
& (1 << next_hi_reg
))
13394 live_regs_mask
&= ~0x0f00;
13397 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13398 live_regs_mask
&= 0xff;
13400 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13402 /* Pop the return address into the PC. */
13403 if (had_to_push_lr
)
13404 live_regs_mask
|= 1 << PC_REGNUM
;
13406 /* Either no argument registers were pushed or a backtrace
13407 structure was created which includes an adjusted stack
13408 pointer, so just pop everything. */
13409 if (live_regs_mask
)
13410 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13413 /* We have either just popped the return address into the
13414 PC or it is was kept in LR for the entire function. */
13415 if (!had_to_push_lr
)
13416 thumb_exit (asm_out_file
, LR_REGNUM
);
13420 /* Pop everything but the return address. */
13421 if (live_regs_mask
)
13422 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13425 if (had_to_push_lr
)
13429 /* We have no free low regs, so save one. */
13430 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13434 /* Get the return address into a temporary register. */
13435 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13436 1 << LAST_ARG_REGNUM
);
13440 /* Move the return address to lr. */
13441 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13443 /* Restore the low register. */
13444 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13449 regno
= LAST_ARG_REGNUM
;
13454 /* Remove the argument registers that were pushed onto the stack. */
13455 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13456 SP_REGNUM
, SP_REGNUM
,
13457 current_function_pretend_args_size
);
13459 thumb_exit (asm_out_file
, regno
);
13465 /* Functions to save and restore machine-specific function data. */
13466 static struct machine_function
*
13467 arm_init_machine_status (void)
13469 struct machine_function
*machine
;
13470 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13472 #if ARM_FT_UNKNOWN != 0
13473 machine
->func_type
= ARM_FT_UNKNOWN
;
13478 /* Return an RTX indicating where the return address to the
13479 calling function can be found. */
13481 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13486 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13489 /* Do anything needed before RTL is emitted for each function. */
13491 arm_init_expanders (void)
13493 /* Arrange to initialize and mark the machine per-function status. */
13494 init_machine_status
= arm_init_machine_status
;
13496 /* This is to stop the combine pass optimizing away the alignment
13497 adjustment of va_arg. */
13498 /* ??? It is claimed that this should not be necessary. */
13500 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13504 /* Like arm_compute_initial_elimination offset. Simpler because there
13505 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13506 to point at the base of the local variables after static stack
13507 space for a function has been allocated. */
13510 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13512 arm_stack_offsets
*offsets
;
13514 offsets
= arm_get_frame_offsets ();
13518 case ARG_POINTER_REGNUM
:
13521 case STACK_POINTER_REGNUM
:
13522 return offsets
->outgoing_args
- offsets
->saved_args
;
13524 case FRAME_POINTER_REGNUM
:
13525 return offsets
->soft_frame
- offsets
->saved_args
;
13527 case ARM_HARD_FRAME_POINTER_REGNUM
:
13528 return offsets
->saved_regs
- offsets
->saved_args
;
13530 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13531 return offsets
->locals_base
- offsets
->saved_args
;
13534 gcc_unreachable ();
13538 case FRAME_POINTER_REGNUM
:
13541 case STACK_POINTER_REGNUM
:
13542 return offsets
->outgoing_args
- offsets
->soft_frame
;
13544 case ARM_HARD_FRAME_POINTER_REGNUM
:
13545 return offsets
->saved_regs
- offsets
->soft_frame
;
13547 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13548 return offsets
->locals_base
- offsets
->soft_frame
;
13551 gcc_unreachable ();
13556 gcc_unreachable ();
13561 /* Generate the rest of a function's prologue. */
13563 thumb_expand_prologue (void)
13567 HOST_WIDE_INT amount
;
13568 arm_stack_offsets
*offsets
;
13569 unsigned long func_type
;
13571 unsigned long live_regs_mask
;
13573 func_type
= arm_current_func_type ();
13575 /* Naked functions don't have prologues. */
13576 if (IS_NAKED (func_type
))
13579 if (IS_INTERRUPT (func_type
))
13581 error ("interrupt Service Routines cannot be coded in Thumb mode");
13585 live_regs_mask
= thumb_compute_save_reg_mask ();
13586 /* Load the pic register before setting the frame pointer,
13587 so we can use r7 as a temporary work register. */
13589 arm_load_pic_register (live_regs_mask
);
13591 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13592 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13593 stack_pointer_rtx
);
13595 offsets
= arm_get_frame_offsets ();
13596 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13601 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13602 GEN_INT (- amount
)));
13603 RTX_FRAME_RELATED_P (insn
) = 1;
13609 /* The stack decrement is too big for an immediate value in a single
13610 insn. In theory we could issue multiple subtracts, but after
13611 three of them it becomes more space efficient to place the full
13612 value in the constant pool and load into a register. (Also the
13613 ARM debugger really likes to see only one stack decrement per
13614 function). So instead we look for a scratch register into which
13615 we can load the decrement, and then we subtract this from the
13616 stack pointer. Unfortunately on the thumb the only available
13617 scratch registers are the argument registers, and we cannot use
13618 these as they may hold arguments to the function. Instead we
13619 attempt to locate a call preserved register which is used by this
13620 function. If we can find one, then we know that it will have
13621 been pushed at the start of the prologue and so we can corrupt
13623 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13624 if (live_regs_mask
& (1 << regno
)
13625 && !(frame_pointer_needed
13626 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13629 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13631 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13633 /* Choose an arbitrary, non-argument low register. */
13634 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13636 /* Save it by copying it into a high, scratch register. */
13637 emit_insn (gen_movsi (spare
, reg
));
13638 /* Add a USE to stop propagate_one_insn() from barfing. */
13639 emit_insn (gen_prologue_use (spare
));
13641 /* Decrement the stack. */
13642 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13643 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13644 stack_pointer_rtx
, reg
));
13645 RTX_FRAME_RELATED_P (insn
) = 1;
13646 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13647 plus_constant (stack_pointer_rtx
,
13649 RTX_FRAME_RELATED_P (dwarf
) = 1;
13651 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13654 /* Restore the low register's original value. */
13655 emit_insn (gen_movsi (reg
, spare
));
13657 /* Emit a USE of the restored scratch register, so that flow
13658 analysis will not consider the restore redundant. The
13659 register won't be used again in this function and isn't
13660 restored by the epilogue. */
13661 emit_insn (gen_prologue_use (reg
));
13665 reg
= gen_rtx_REG (SImode
, regno
);
13667 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13669 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13670 stack_pointer_rtx
, reg
));
13671 RTX_FRAME_RELATED_P (insn
) = 1;
13672 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13673 plus_constant (stack_pointer_rtx
,
13675 RTX_FRAME_RELATED_P (dwarf
) = 1;
13677 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13683 if (frame_pointer_needed
)
13685 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13688 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13689 stack_pointer_rtx
, GEN_INT (amount
)));
13692 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13693 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13694 hard_frame_pointer_rtx
,
13695 stack_pointer_rtx
));
13696 dwarf
= gen_rtx_SET (SImode
, hard_frame_pointer_rtx
,
13697 plus_constant (stack_pointer_rtx
, amount
));
13698 RTX_FRAME_RELATED_P (dwarf
) = 1;
13699 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13703 RTX_FRAME_RELATED_P (insn
) = 1;
13706 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13707 emit_insn (gen_blockage ());
13709 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13710 if (live_regs_mask
& 0xff)
13711 cfun
->machine
->lr_save_eliminated
= 0;
13713 /* If the link register is being kept alive, with the return address in it,
13714 then make sure that it does not get reused by the ce2 pass. */
13715 if (cfun
->machine
->lr_save_eliminated
)
13716 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13721 thumb_expand_epilogue (void)
13723 HOST_WIDE_INT amount
;
13724 arm_stack_offsets
*offsets
;
13727 /* Naked functions don't have prologues. */
13728 if (IS_NAKED (arm_current_func_type ()))
13731 offsets
= arm_get_frame_offsets ();
13732 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13734 if (frame_pointer_needed
)
13736 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13737 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13743 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13744 GEN_INT (amount
)));
13747 /* r3 is always free in the epilogue. */
13748 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13750 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13751 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13755 /* Emit a USE (stack_pointer_rtx), so that
13756 the stack adjustment will not be deleted. */
13757 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13759 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13760 emit_insn (gen_blockage ());
13762 /* Emit a clobber for each insn that will be restored in the epilogue,
13763 so that flow2 will get register lifetimes correct. */
13764 for (regno
= 0; regno
< 13; regno
++)
13765 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13766 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13768 if (! regs_ever_live
[LR_REGNUM
])
13769 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13773 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13775 unsigned long live_regs_mask
= 0;
13776 unsigned long l_mask
;
13777 unsigned high_regs_pushed
= 0;
13778 int cfa_offset
= 0;
13781 if (IS_NAKED (arm_current_func_type ()))
13784 if (is_called_in_ARM_mode (current_function_decl
))
13788 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13789 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13791 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13793 /* Generate code sequence to switch us into Thumb mode. */
13794 /* The .code 32 directive has already been emitted by
13795 ASM_DECLARE_FUNCTION_NAME. */
13796 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13797 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13799 /* Generate a label, so that the debugger will notice the
13800 change in instruction sets. This label is also used by
13801 the assembler to bypass the ARM code when this function
13802 is called from a Thumb encoded function elsewhere in the
13803 same file. Hence the definition of STUB_NAME here must
13804 agree with the definition in gas/config/tc-arm.c. */
13806 #define STUB_NAME ".real_start_of"
13808 fprintf (f
, "\t.code\t16\n");
13810 if (arm_dllexport_name_p (name
))
13811 name
= arm_strip_name_encoding (name
);
13813 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13814 fprintf (f
, "\t.thumb_func\n");
13815 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13818 if (current_function_pretend_args_size
)
13820 /* Output unwind directive for the stack adjustment. */
13821 if (ARM_EABI_UNWIND_TABLES
)
13822 fprintf (f
, "\t.pad #%d\n",
13823 current_function_pretend_args_size
);
13825 if (cfun
->machine
->uses_anonymous_args
)
13829 fprintf (f
, "\tpush\t{");
13831 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13833 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13834 regno
<= LAST_ARG_REGNUM
;
13836 asm_fprintf (f
, "%r%s", regno
,
13837 regno
== LAST_ARG_REGNUM
? "" : ", ");
13839 fprintf (f
, "}\n");
13842 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13843 SP_REGNUM
, SP_REGNUM
,
13844 current_function_pretend_args_size
);
13846 /* We don't need to record the stores for unwinding (would it
13847 help the debugger any if we did?), but record the change in
13848 the stack pointer. */
13849 if (dwarf2out_do_frame ())
13851 char *l
= dwarf2out_cfi_label ();
13853 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13854 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13858 /* Get the registers we are going to push. */
13859 live_regs_mask
= thumb_compute_save_reg_mask ();
13860 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13861 l_mask
= live_regs_mask
& 0x40ff;
13862 /* Then count how many other high registers will need to be pushed. */
13863 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13865 if (TARGET_BACKTRACE
)
13868 unsigned work_register
;
13870 /* We have been asked to create a stack backtrace structure.
13871 The code looks like this:
13875 0 sub SP, #16 Reserve space for 4 registers.
13876 2 push {R7} Push low registers.
13877 4 add R7, SP, #20 Get the stack pointer before the push.
13878 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13879 8 mov R7, PC Get hold of the start of this code plus 12.
13880 10 str R7, [SP, #16] Store it.
13881 12 mov R7, FP Get hold of the current frame pointer.
13882 14 str R7, [SP, #4] Store it.
13883 16 mov R7, LR Get hold of the current return address.
13884 18 str R7, [SP, #12] Store it.
13885 20 add R7, SP, #16 Point at the start of the backtrace structure.
13886 22 mov FP, R7 Put this value into the frame pointer. */
13888 work_register
= thumb_find_work_register (live_regs_mask
);
13890 if (ARM_EABI_UNWIND_TABLES
)
13891 asm_fprintf (f
, "\t.pad #16\n");
13894 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13895 SP_REGNUM
, SP_REGNUM
);
13897 if (dwarf2out_do_frame ())
13899 char *l
= dwarf2out_cfi_label ();
13901 cfa_offset
= cfa_offset
+ 16;
13902 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13907 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13908 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13913 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13914 offset
+ 16 + current_function_pretend_args_size
);
13916 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13919 /* Make sure that the instruction fetching the PC is in the right place
13920 to calculate "start of backtrace creation code + 12". */
13923 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13924 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13926 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13927 ARM_HARD_FRAME_POINTER_REGNUM
);
13928 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13933 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13934 ARM_HARD_FRAME_POINTER_REGNUM
);
13935 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13937 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13938 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13942 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13943 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13945 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13947 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13948 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13950 /* Optimization: If we are not pushing any low registers but we are going
13951 to push some high registers then delay our first push. This will just
13952 be a push of LR and we can combine it with the push of the first high
13954 else if ((l_mask
& 0xff) != 0
13955 || (high_regs_pushed
== 0 && l_mask
))
13956 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13958 if (high_regs_pushed
)
13960 unsigned pushable_regs
;
13961 unsigned next_hi_reg
;
13963 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13964 if (live_regs_mask
& (1 << next_hi_reg
))
13967 pushable_regs
= l_mask
& 0xff;
13969 if (pushable_regs
== 0)
13970 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13972 while (high_regs_pushed
> 0)
13974 unsigned long real_regs_mask
= 0;
13976 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13978 if (pushable_regs
& (1 << regno
))
13980 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13982 high_regs_pushed
--;
13983 real_regs_mask
|= (1 << next_hi_reg
);
13985 if (high_regs_pushed
)
13987 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13989 if (live_regs_mask
& (1 << next_hi_reg
))
13994 pushable_regs
&= ~((1 << regno
) - 1);
14000 /* If we had to find a work register and we have not yet
14001 saved the LR then add it to the list of regs to push. */
14002 if (l_mask
== (1 << LR_REGNUM
))
14004 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14006 real_regs_mask
| (1 << LR_REGNUM
));
14010 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14015 /* Handle the case of a double word load into a low register from
14016 a computed memory address. The computed address may involve a
14017 register which is overwritten by the load. */
14019 thumb_load_double_from_address (rtx
*operands
)
14027 gcc_assert (GET_CODE (operands
[0]) == REG
);
14028 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14030 /* Get the memory address. */
14031 addr
= XEXP (operands
[1], 0);
14033 /* Work out how the memory address is computed. */
14034 switch (GET_CODE (addr
))
14037 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14039 if (REGNO (operands
[0]) == REGNO (addr
))
14041 output_asm_insn ("ldr\t%H0, %2", operands
);
14042 output_asm_insn ("ldr\t%0, %1", operands
);
14046 output_asm_insn ("ldr\t%0, %1", operands
);
14047 output_asm_insn ("ldr\t%H0, %2", operands
);
14052 /* Compute <address> + 4 for the high order load. */
14053 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14055 output_asm_insn ("ldr\t%0, %1", operands
);
14056 output_asm_insn ("ldr\t%H0, %2", operands
);
14060 arg1
= XEXP (addr
, 0);
14061 arg2
= XEXP (addr
, 1);
14063 if (CONSTANT_P (arg1
))
14064 base
= arg2
, offset
= arg1
;
14066 base
= arg1
, offset
= arg2
;
14068 gcc_assert (GET_CODE (base
) == REG
);
14070 /* Catch the case of <address> = <reg> + <reg> */
14071 if (GET_CODE (offset
) == REG
)
14073 int reg_offset
= REGNO (offset
);
14074 int reg_base
= REGNO (base
);
14075 int reg_dest
= REGNO (operands
[0]);
14077 /* Add the base and offset registers together into the
14078 higher destination register. */
14079 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14080 reg_dest
+ 1, reg_base
, reg_offset
);
14082 /* Load the lower destination register from the address in
14083 the higher destination register. */
14084 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14085 reg_dest
, reg_dest
+ 1);
14087 /* Load the higher destination register from its own address
14089 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14090 reg_dest
+ 1, reg_dest
+ 1);
14094 /* Compute <address> + 4 for the high order load. */
14095 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14097 /* If the computed address is held in the low order register
14098 then load the high order register first, otherwise always
14099 load the low order register first. */
14100 if (REGNO (operands
[0]) == REGNO (base
))
14102 output_asm_insn ("ldr\t%H0, %2", operands
);
14103 output_asm_insn ("ldr\t%0, %1", operands
);
14107 output_asm_insn ("ldr\t%0, %1", operands
);
14108 output_asm_insn ("ldr\t%H0, %2", operands
);
14114 /* With no registers to worry about we can just load the value
14116 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14118 output_asm_insn ("ldr\t%H0, %2", operands
);
14119 output_asm_insn ("ldr\t%0, %1", operands
);
14123 gcc_unreachable ();
14130 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14137 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14140 operands
[4] = operands
[5];
14143 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14144 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14148 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14151 operands
[4] = operands
[5];
14154 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14157 operands
[5] = operands
[6];
14160 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14163 operands
[4] = operands
[5];
14167 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14168 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14172 gcc_unreachable ();
14178 /* Output a call-via instruction for thumb state. */
14180 thumb_call_via_reg (rtx reg
)
14182 int regno
= REGNO (reg
);
14185 gcc_assert (regno
< LR_REGNUM
);
14187 /* If we are in the normal text section we can use a single instance
14188 per compilation unit. If we are doing function sections, then we need
14189 an entry per section, since we can't rely on reachability. */
14190 if (in_text_section ())
14192 thumb_call_reg_needed
= 1;
14194 if (thumb_call_via_label
[regno
] == NULL
)
14195 thumb_call_via_label
[regno
] = gen_label_rtx ();
14196 labelp
= thumb_call_via_label
+ regno
;
14200 if (cfun
->machine
->call_via
[regno
] == NULL
)
14201 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
14202 labelp
= cfun
->machine
->call_via
+ regno
;
14205 output_asm_insn ("bl\t%a0", labelp
);
14209 /* Routines for generating rtl. */
14211 thumb_expand_movmemqi (rtx
*operands
)
14213 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
14214 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
14215 HOST_WIDE_INT len
= INTVAL (operands
[2]);
14216 HOST_WIDE_INT offset
= 0;
14220 emit_insn (gen_movmem12b (out
, in
, out
, in
));
14226 emit_insn (gen_movmem8b (out
, in
, out
, in
));
14232 rtx reg
= gen_reg_rtx (SImode
);
14233 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
14234 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
14241 rtx reg
= gen_reg_rtx (HImode
);
14242 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
14243 plus_constant (in
, offset
))));
14244 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
14252 rtx reg
= gen_reg_rtx (QImode
);
14253 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
14254 plus_constant (in
, offset
))));
14255 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
14261 thumb_reload_out_hi (rtx
*operands
)
14263 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14266 /* Handle reading a half-word from memory during reload. */
14268 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14270 gcc_unreachable ();
14273 /* Return the length of a function name prefix
14274 that starts with the character 'c'. */
14276 arm_get_strip_length (int c
)
14280 ARM_NAME_ENCODING_LENGTHS
14285 /* Return a pointer to a function's name with any
14286 and all prefix encodings stripped from it. */
14288 arm_strip_name_encoding (const char *name
)
14292 while ((skip
= arm_get_strip_length (* name
)))
14298 /* If there is a '*' anywhere in the name's prefix, then
14299 emit the stripped name verbatim, otherwise prepend an
14300 underscore if leading underscores are being used. */
14302 arm_asm_output_labelref (FILE *stream
, const char *name
)
14307 while ((skip
= arm_get_strip_length (* name
)))
14309 verbatim
|= (*name
== '*');
14314 fputs (name
, stream
);
14316 asm_fprintf (stream
, "%U%s", name
);
14320 arm_file_end (void)
14324 if (! thumb_call_reg_needed
)
14328 asm_fprintf (asm_out_file
, "\t.code 16\n");
14329 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
14331 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14333 rtx label
= thumb_call_via_label
[regno
];
14337 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14338 CODE_LABEL_NUMBER (label
));
14339 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14346 #ifdef AOF_ASSEMBLER
14347 /* Special functions only needed when producing AOF syntax assembler. */
14351 struct pic_chain
* next
;
14352 const char * symname
;
14355 static struct pic_chain
* aof_pic_chain
= NULL
;
14358 aof_pic_entry (rtx x
)
14360 struct pic_chain
** chainp
;
14363 if (aof_pic_label
== NULL_RTX
)
14365 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14368 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14369 offset
+= 4, chainp
= &(*chainp
)->next
)
14370 if ((*chainp
)->symname
== XSTR (x
, 0))
14371 return plus_constant (aof_pic_label
, offset
);
14373 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14374 (*chainp
)->next
= NULL
;
14375 (*chainp
)->symname
= XSTR (x
, 0);
14376 return plus_constant (aof_pic_label
, offset
);
14380 aof_dump_pic_table (FILE *f
)
14382 struct pic_chain
* chain
;
14384 if (aof_pic_chain
== NULL
)
14387 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14388 PIC_OFFSET_TABLE_REGNUM
,
14389 PIC_OFFSET_TABLE_REGNUM
);
14390 fputs ("|x$adcons|\n", f
);
14392 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14394 fputs ("\tDCD\t", f
);
14395 assemble_name (f
, chain
->symname
);
14400 int arm_text_section_count
= 1;
14403 aof_text_section (void )
14405 static char buf
[100];
14406 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14407 arm_text_section_count
++);
14409 strcat (buf
, ", PIC, REENTRANT");
14413 static int arm_data_section_count
= 1;
14416 aof_data_section (void)
14418 static char buf
[100];
14419 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14423 /* The AOF assembler is religiously strict about declarations of
14424 imported and exported symbols, so that it is impossible to declare
14425 a function as imported near the beginning of the file, and then to
14426 export it later on. It is, however, possible to delay the decision
14427 until all the functions in the file have been compiled. To get
14428 around this, we maintain a list of the imports and exports, and
14429 delete from it any that are subsequently defined. At the end of
14430 compilation we spit the remainder of the list out before the END
14435 struct import
* next
;
14439 static struct import
* imports_list
= NULL
;
14442 aof_add_import (const char *name
)
14444 struct import
* new;
14446 for (new = imports_list
; new; new = new->next
)
14447 if (new->name
== name
)
14450 new = (struct import
*) xmalloc (sizeof (struct import
));
14451 new->next
= imports_list
;
14452 imports_list
= new;
14457 aof_delete_import (const char *name
)
14459 struct import
** old
;
14461 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14463 if ((*old
)->name
== name
)
14465 *old
= (*old
)->next
;
14471 int arm_main_function
= 0;
14474 aof_dump_imports (FILE *f
)
14476 /* The AOF assembler needs this to cause the startup code to be extracted
14477 from the library. Brining in __main causes the whole thing to work
14479 if (arm_main_function
)
14482 fputs ("\tIMPORT __main\n", f
);
14483 fputs ("\tDCD __main\n", f
);
14486 /* Now dump the remaining imports. */
14487 while (imports_list
)
14489 fprintf (f
, "\tIMPORT\t");
14490 assemble_name (f
, imports_list
->name
);
14492 imports_list
= imports_list
->next
;
14497 aof_globalize_label (FILE *stream
, const char *name
)
14499 default_globalize_label (stream
, name
);
14500 if (! strcmp (name
, "main"))
14501 arm_main_function
= 1;
14505 aof_file_start (void)
14507 fputs ("__r0\tRN\t0\n", asm_out_file
);
14508 fputs ("__a1\tRN\t0\n", asm_out_file
);
14509 fputs ("__a2\tRN\t1\n", asm_out_file
);
14510 fputs ("__a3\tRN\t2\n", asm_out_file
);
14511 fputs ("__a4\tRN\t3\n", asm_out_file
);
14512 fputs ("__v1\tRN\t4\n", asm_out_file
);
14513 fputs ("__v2\tRN\t5\n", asm_out_file
);
14514 fputs ("__v3\tRN\t6\n", asm_out_file
);
14515 fputs ("__v4\tRN\t7\n", asm_out_file
);
14516 fputs ("__v5\tRN\t8\n", asm_out_file
);
14517 fputs ("__v6\tRN\t9\n", asm_out_file
);
14518 fputs ("__sl\tRN\t10\n", asm_out_file
);
14519 fputs ("__fp\tRN\t11\n", asm_out_file
);
14520 fputs ("__ip\tRN\t12\n", asm_out_file
);
14521 fputs ("__sp\tRN\t13\n", asm_out_file
);
14522 fputs ("__lr\tRN\t14\n", asm_out_file
);
14523 fputs ("__pc\tRN\t15\n", asm_out_file
);
14524 fputs ("__f0\tFN\t0\n", asm_out_file
);
14525 fputs ("__f1\tFN\t1\n", asm_out_file
);
14526 fputs ("__f2\tFN\t2\n", asm_out_file
);
14527 fputs ("__f3\tFN\t3\n", asm_out_file
);
14528 fputs ("__f4\tFN\t4\n", asm_out_file
);
14529 fputs ("__f5\tFN\t5\n", asm_out_file
);
14530 fputs ("__f6\tFN\t6\n", asm_out_file
);
14531 fputs ("__f7\tFN\t7\n", asm_out_file
);
14536 aof_file_end (void)
14539 aof_dump_pic_table (asm_out_file
);
14541 aof_dump_imports (asm_out_file
);
14542 fputs ("\tEND\n", asm_out_file
);
14544 #endif /* AOF_ASSEMBLER */
14547 /* Symbols in the text segment can be accessed without indirecting via the
14548 constant pool; it may take an extra binary operation, but this is still
14549 faster than indirecting via memory. Don't do this when not optimizing,
14550 since we won't be calculating al of the offsets necessary to do this
14554 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14556 /* This doesn't work with AOF syntax, since the string table may be in
14557 a different AREA. */
14558 #ifndef AOF_ASSEMBLER
14559 if (optimize
> 0 && TREE_CONSTANT (decl
))
14560 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14563 /* If we are referencing a function that is weak then encode a long call
14564 flag in the function name, otherwise if the function is static or
14565 or known to be defined in this file then encode a short call flag. */
14566 if (first
&& DECL_P (decl
))
14568 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14569 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14570 else if (! TREE_PUBLIC (decl
))
14571 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14574 default_encode_section_info (decl
, rtl
, first
);
14576 #endif /* !ARM_PE */
14579 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14581 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14582 && !strcmp (prefix
, "L"))
14584 arm_ccfsm_state
= 0;
14585 arm_target_insn
= NULL
;
14587 default_internal_label (stream
, prefix
, labelno
);
14590 /* Output code to add DELTA to the first argument, and then jump
14591 to FUNCTION. Used for C++ multiple inheritance. */
14593 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14594 HOST_WIDE_INT delta
,
14595 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14598 static int thunk_label
= 0;
14600 int mi_delta
= delta
;
14601 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14603 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14606 mi_delta
= - mi_delta
;
14609 int labelno
= thunk_label
++;
14610 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14611 fputs ("\tldr\tr12, ", file
);
14612 assemble_name (file
, label
);
14613 fputc ('\n', file
);
14615 while (mi_delta
!= 0)
14617 if ((mi_delta
& (3 << shift
)) == 0)
14621 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14622 mi_op
, this_regno
, this_regno
,
14623 mi_delta
& (0xff << shift
));
14624 mi_delta
&= ~(0xff << shift
);
14630 fprintf (file
, "\tbx\tr12\n");
14631 ASM_OUTPUT_ALIGN (file
, 2);
14632 assemble_name (file
, label
);
14633 fputs (":\n", file
);
14634 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14638 fputs ("\tb\t", file
);
14639 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14640 if (NEED_PLT_RELOC
)
14641 fputs ("(PLT)", file
);
14642 fputc ('\n', file
);
14647 arm_emit_vector_const (FILE *file
, rtx x
)
14650 const char * pattern
;
14652 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14654 switch (GET_MODE (x
))
14656 case V2SImode
: pattern
= "%08x"; break;
14657 case V4HImode
: pattern
= "%04x"; break;
14658 case V8QImode
: pattern
= "%02x"; break;
14659 default: gcc_unreachable ();
14662 fprintf (file
, "0x");
14663 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14667 element
= CONST_VECTOR_ELT (x
, i
);
14668 fprintf (file
, pattern
, INTVAL (element
));
14675 arm_output_load_gr (rtx
*operands
)
14682 if (GET_CODE (operands
[1]) != MEM
14683 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14684 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14685 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14686 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14687 return "wldrw%?\t%0, %1";
14689 /* Fix up an out-of-range load of a GR register. */
14690 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14691 wcgr
= operands
[0];
14693 output_asm_insn ("ldr%?\t%0, %1", operands
);
14695 operands
[0] = wcgr
;
14697 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14698 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14704 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14705 int incoming ATTRIBUTE_UNUSED
)
14708 /* FIXME: The ARM backend has special code to handle structure
14709 returns, and will reserve its own hidden first argument. So
14710 if this macro is enabled a *second* hidden argument will be
14711 reserved, which will break binary compatibility with old
14712 toolchains and also thunk handling. One day this should be
14716 /* Register in which address to store a structure value
14717 is passed to a function. */
14718 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14722 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14724 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14725 named arg and all anonymous args onto the stack.
14726 XXX I know the prologue shouldn't be pushing registers, but it is faster
14730 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14731 enum machine_mode mode ATTRIBUTE_UNUSED
,
14732 tree type ATTRIBUTE_UNUSED
,
14734 int second_time ATTRIBUTE_UNUSED
)
14736 cfun
->machine
->uses_anonymous_args
= 1;
14737 if (cum
->nregs
< NUM_ARG_REGS
)
14738 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14741 /* Return nonzero if the CONSUMER instruction (a store) does not need
14742 PRODUCER's value to calculate the address. */
14745 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14747 rtx value
= PATTERN (producer
);
14748 rtx addr
= PATTERN (consumer
);
14750 if (GET_CODE (value
) == COND_EXEC
)
14751 value
= COND_EXEC_CODE (value
);
14752 if (GET_CODE (value
) == PARALLEL
)
14753 value
= XVECEXP (value
, 0, 0);
14754 value
= XEXP (value
, 0);
14755 if (GET_CODE (addr
) == COND_EXEC
)
14756 addr
= COND_EXEC_CODE (addr
);
14757 if (GET_CODE (addr
) == PARALLEL
)
14758 addr
= XVECEXP (addr
, 0, 0);
14759 addr
= XEXP (addr
, 0);
14761 return !reg_overlap_mentioned_p (value
, addr
);
14764 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14765 have an early register shift value or amount dependency on the
14766 result of PRODUCER. */
14769 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14771 rtx value
= PATTERN (producer
);
14772 rtx op
= PATTERN (consumer
);
14775 if (GET_CODE (value
) == COND_EXEC
)
14776 value
= COND_EXEC_CODE (value
);
14777 if (GET_CODE (value
) == PARALLEL
)
14778 value
= XVECEXP (value
, 0, 0);
14779 value
= XEXP (value
, 0);
14780 if (GET_CODE (op
) == COND_EXEC
)
14781 op
= COND_EXEC_CODE (op
);
14782 if (GET_CODE (op
) == PARALLEL
)
14783 op
= XVECEXP (op
, 0, 0);
14786 early_op
= XEXP (op
, 0);
14787 /* This is either an actual independent shift, or a shift applied to
14788 the first operand of another operation. We want the whole shift
14790 if (GET_CODE (early_op
) == REG
)
14793 return !reg_overlap_mentioned_p (value
, early_op
);
14796 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14797 have an early register shift value dependency on the result of
14801 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14803 rtx value
= PATTERN (producer
);
14804 rtx op
= PATTERN (consumer
);
14807 if (GET_CODE (value
) == COND_EXEC
)
14808 value
= COND_EXEC_CODE (value
);
14809 if (GET_CODE (value
) == PARALLEL
)
14810 value
= XVECEXP (value
, 0, 0);
14811 value
= XEXP (value
, 0);
14812 if (GET_CODE (op
) == COND_EXEC
)
14813 op
= COND_EXEC_CODE (op
);
14814 if (GET_CODE (op
) == PARALLEL
)
14815 op
= XVECEXP (op
, 0, 0);
14818 early_op
= XEXP (op
, 0);
14820 /* This is either an actual independent shift, or a shift applied to
14821 the first operand of another operation. We want the value being
14822 shifted, in either case. */
14823 if (GET_CODE (early_op
) != REG
)
14824 early_op
= XEXP (early_op
, 0);
14826 return !reg_overlap_mentioned_p (value
, early_op
);
14829 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14830 have an early register mult dependency on the result of
14834 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14836 rtx value
= PATTERN (producer
);
14837 rtx op
= PATTERN (consumer
);
14839 if (GET_CODE (value
) == COND_EXEC
)
14840 value
= COND_EXEC_CODE (value
);
14841 if (GET_CODE (value
) == PARALLEL
)
14842 value
= XVECEXP (value
, 0, 0);
14843 value
= XEXP (value
, 0);
14844 if (GET_CODE (op
) == COND_EXEC
)
14845 op
= COND_EXEC_CODE (op
);
14846 if (GET_CODE (op
) == PARALLEL
)
14847 op
= XVECEXP (op
, 0, 0);
14850 return (GET_CODE (op
) == PLUS
14851 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14855 /* We can't rely on the caller doing the proper promotion when
14856 using APCS or ATPCS. */
14859 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14861 return !TARGET_AAPCS_BASED
;
14865 /* AAPCS based ABIs use short enums by default. */
14868 arm_default_short_enums (void)
14870 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
14874 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14877 arm_align_anon_bitfield (void)
14879 return TARGET_AAPCS_BASED
;
14883 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14886 arm_cxx_guard_type (void)
14888 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14892 /* The EABI says test the least significant bit of a guard variable. */
14895 arm_cxx_guard_mask_bit (void)
14897 return TARGET_AAPCS_BASED
;
14901 /* The EABI specifies that all array cookies are 8 bytes long. */
14904 arm_get_cookie_size (tree type
)
14908 if (!TARGET_AAPCS_BASED
)
14909 return default_cxx_get_cookie_size (type
);
14911 size
= build_int_cst (sizetype
, 8);
14916 /* The EABI says that array cookies should also contain the element size. */
14919 arm_cookie_has_size (void)
14921 return TARGET_AAPCS_BASED
;
14925 /* The EABI says constructors and destructors should return a pointer to
14926 the object constructed/destroyed. */
14929 arm_cxx_cdtor_returns_this (void)
14931 return TARGET_AAPCS_BASED
;
14934 /* The EABI says that an inline function may never be the key
14938 arm_cxx_key_method_may_be_inline (void)
14940 return !TARGET_AAPCS_BASED
;
14944 arm_cxx_determine_class_data_visibility (tree decl
)
14946 if (!TARGET_AAPCS_BASED
)
14949 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14950 is exported. However, on systems without dynamic vague linkage,
14951 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14952 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
14953 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
14955 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
14956 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
14960 arm_cxx_class_data_always_comdat (void)
14962 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14963 vague linkage if the class has no key function. */
14964 return !TARGET_AAPCS_BASED
;
14968 /* The EABI says __aeabi_atexit should be used to register static
14972 arm_cxx_use_aeabi_atexit (void)
14974 return TARGET_AAPCS_BASED
;
14979 arm_set_return_address (rtx source
, rtx scratch
)
14981 arm_stack_offsets
*offsets
;
14982 HOST_WIDE_INT delta
;
14984 unsigned long saved_regs
;
14986 saved_regs
= arm_compute_save_reg_mask ();
14988 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14989 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14992 if (frame_pointer_needed
)
14993 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
14996 /* LR will be the first saved register. */
14997 offsets
= arm_get_frame_offsets ();
14998 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15003 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15004 GEN_INT (delta
& ~4095)));
15009 addr
= stack_pointer_rtx
;
15011 addr
= plus_constant (addr
, delta
);
15013 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15019 thumb_set_return_address (rtx source
, rtx scratch
)
15021 arm_stack_offsets
*offsets
;
15022 HOST_WIDE_INT delta
;
15025 unsigned long mask
;
15027 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15029 mask
= thumb_compute_save_reg_mask ();
15030 if (mask
& (1 << LR_REGNUM
))
15032 offsets
= arm_get_frame_offsets ();
15034 /* Find the saved regs. */
15035 if (frame_pointer_needed
)
15037 delta
= offsets
->soft_frame
- offsets
->saved_args
;
15038 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
15042 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
15045 /* Allow for the stack frame. */
15046 if (TARGET_BACKTRACE
)
15048 /* The link register is always the first saved register. */
15051 /* Construct the address. */
15052 addr
= gen_rtx_REG (SImode
, reg
);
15053 if ((reg
!= SP_REGNUM
&& delta
>= 128)
15056 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
15057 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
15061 addr
= plus_constant (addr
, delta
);
15063 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15066 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15069 /* Implements target hook vector_mode_supported_p. */
15071 arm_vector_mode_supported_p (enum machine_mode mode
)
15073 if ((mode
== V2SImode
)
15074 || (mode
== V4HImode
)
15075 || (mode
== V8QImode
))
15081 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15082 ARM insns and therefore guarantee that the shift count is modulo 256.
15083 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15084 guarantee no particular behavior for out-of-range counts. */
15086 static unsigned HOST_WIDE_INT
15087 arm_shift_truncation_mask (enum machine_mode mode
)
15089 return mode
== SImode
? 255 : 0;
15093 /* Map internal gcc register numbers to DWARF2 register numbers. */
15096 arm_dbx_register_number (unsigned int regno
)
15101 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15102 compatibility. The EABI defines them as registers 96-103. */
15103 if (IS_FPA_REGNUM (regno
))
15104 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
15106 if (IS_VFP_REGNUM (regno
))
15107 return 64 + regno
- FIRST_VFP_REGNUM
;
15109 if (IS_IWMMXT_GR_REGNUM (regno
))
15110 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
15112 if (IS_IWMMXT_REGNUM (regno
))
15113 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
15115 gcc_unreachable ();
15119 #ifdef TARGET_UNWIND_INFO
15120 /* Emit unwind directives for a store-multiple instruction. This should
15121 only ever be generated by the function prologue code, so we expect it
15122 to have a particular form. */
15125 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
15128 HOST_WIDE_INT offset
;
15129 HOST_WIDE_INT nregs
;
15135 /* First insn will adjust the stack pointer. */
15136 e
= XVECEXP (p
, 0, 0);
15137 if (GET_CODE (e
) != SET
15138 || GET_CODE (XEXP (e
, 0)) != REG
15139 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15140 || GET_CODE (XEXP (e
, 1)) != PLUS
)
15143 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
15144 nregs
= XVECLEN (p
, 0) - 1;
15146 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
15149 /* The function prologue may also push pc, but not annotate it as it is
15150 never restored. We turn this into a stack pointer adjustment. */
15151 if (nregs
* 4 == offset
- 4)
15153 fprintf (asm_out_file
, "\t.pad #4\n");
15158 else if (IS_VFP_REGNUM (reg
))
15160 /* FPA register saves use an additional word. */
15164 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
15166 /* FPA registers are done differently. */
15167 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
15171 /* Unknown register type. */
15174 /* If the stack increment doesn't match the size of the saved registers,
15175 something has gone horribly wrong. */
15176 if (offset
!= nregs
* reg_size
)
15179 fprintf (asm_out_file
, "\t.save {");
15183 /* The remaining insns will describe the stores. */
15184 for (i
= 1; i
<= nregs
; i
++)
15186 /* Expect (set (mem <addr>) (reg)).
15187 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15188 e
= XVECEXP (p
, 0, i
);
15189 if (GET_CODE (e
) != SET
15190 || GET_CODE (XEXP (e
, 0)) != MEM
15191 || GET_CODE (XEXP (e
, 1)) != REG
)
15194 reg
= REGNO (XEXP (e
, 1));
15199 fprintf (asm_out_file
, ", ");
15200 /* We can't use %r for vfp because we need to use the
15201 double precision register names. */
15202 if (IS_VFP_REGNUM (reg
))
15203 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
15205 asm_fprintf (asm_out_file
, "%r", reg
);
15207 #ifdef ENABLE_CHECKING
15208 /* Check that the addresses are consecutive. */
15209 e
= XEXP (XEXP (e
, 0), 0);
15210 if (GET_CODE (e
) == PLUS
)
15212 offset
+= reg_size
;
15213 if (GET_CODE (XEXP (e
, 0)) != REG
15214 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15215 || GET_CODE (XEXP (e
, 1)) != CONST_INT
15216 || offset
!= INTVAL (XEXP (e
, 1)))
15220 || GET_CODE (e
) != REG
15221 || REGNO (e
) != SP_REGNUM
)
15225 fprintf (asm_out_file
, "}\n");
15228 /* Emit unwind directives for a SET. */
15231 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
15238 switch (GET_CODE (e0
))
15241 /* Pushing a single register. */
15242 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
15243 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
15244 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
15247 asm_fprintf (asm_out_file
, "\t.save ");
15248 if (IS_VFP_REGNUM (REGNO (e1
)))
15249 asm_fprintf(asm_out_file
, "{d%d}\n",
15250 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
15252 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
15256 if (REGNO (e0
) == SP_REGNUM
)
15258 /* A stack increment. */
15259 if (GET_CODE (e1
) != PLUS
15260 || GET_CODE (XEXP (e1
, 0)) != REG
15261 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
15262 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15265 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
15266 -INTVAL (XEXP (e1
, 1)));
15268 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
15270 HOST_WIDE_INT offset
;
15273 if (GET_CODE (e1
) == PLUS
)
15275 if (GET_CODE (XEXP (e1
, 0)) != REG
15276 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15278 reg
= REGNO (XEXP (e1
, 0));
15279 offset
= INTVAL (XEXP (e1
, 1));
15280 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
15281 HARD_FRAME_POINTER_REGNUM
, reg
,
15282 INTVAL (XEXP (e1
, 1)));
15284 else if (GET_CODE (e1
) == REG
)
15287 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
15288 HARD_FRAME_POINTER_REGNUM
, reg
);
15293 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
15295 /* Move from sp to reg. */
15296 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
15308 /* Emit unwind directives for the given insn. */
15311 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
15315 if (!ARM_EABI_UNWIND_TABLES
)
15318 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
15321 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
15323 pat
= XEXP (pat
, 0);
15325 pat
= PATTERN (insn
);
15327 switch (GET_CODE (pat
))
15330 arm_unwind_emit_set (asm_out_file
, pat
);
15334 /* Store multiple. */
15335 arm_unwind_emit_stm (asm_out_file
, pat
);
15344 /* Output a reference from a function exception table to the type_info
15345 object X. The EABI specifies that the symbol should be relocated by
15346 an R_ARM_TARGET2 relocation. */
15349 arm_output_ttype (rtx x
)
15351 fputs ("\t.word\t", asm_out_file
);
15352 output_addr_const (asm_out_file
, x
);
15353 /* Use special relocations for symbol references. */
15354 if (GET_CODE (x
) != CONST_INT
)
15355 fputs ("(TARGET2)", asm_out_file
);
15356 fputc ('\n', asm_out_file
);
15360 #endif /* TARGET_UNWIND_INFO */
15363 /* Output unwind directives for the start/end of a function. */
15366 arm_output_fn_unwind (FILE * f
, bool prologue
)
15368 if (!ARM_EABI_UNWIND_TABLES
)
15372 fputs ("\t.fnstart\n", f
);
15374 fputs ("\t.fnend\n", f
);
15378 arm_emit_tls_decoration (FILE *fp
, rtx x
)
15380 enum tls_reloc reloc
;
15383 val
= XVECEXP (x
, 0, 0);
15384 reloc
= INTVAL (XVECEXP (x
, 0, 1));
15386 output_addr_const (fp
, val
);
15391 fputs ("(tlsgd)", fp
);
15394 fputs ("(tlsldm)", fp
);
15397 fputs ("(tlsldo)", fp
);
15400 fputs ("(gottpoff)", fp
);
15403 fputs ("(tpoff)", fp
);
15406 gcc_unreachable ();
15414 fputs (" + (. - ", fp
);
15415 output_addr_const (fp
, XVECEXP (x
, 0, 2));
15417 output_addr_const (fp
, XVECEXP (x
, 0, 3));
15428 arm_output_addr_const_extra (FILE *fp
, rtx x
)
15430 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
15431 return arm_emit_tls_decoration (fp
, x
);
15432 else if (GET_CODE (x
) == CONST_VECTOR
)
15433 return arm_emit_vector_const (fp
, x
);
15438 #include "gt-arm.h"