1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx
, int);
152 static void arm_encode_section_info (tree
, rtx
, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx
arm_struct_value_rtx (tree
, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
168 enum machine_mode
, tree
, bool);
169 static bool arm_promote_prototypes (tree
);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree
);
173 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx
);
176 static bool arm_output_ttype (rtx
);
179 static tree
arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree
arm_get_cookie_size (tree
);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree
);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
191 static bool arm_cannot_copy_insn_p (rtx
);
192 static bool arm_tls_symbol_p (rtx x
);
195 /* Initialize the GCC target structure. */
196 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
197 #undef TARGET_MERGE_DECL_ATTRIBUTES
198 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
201 #undef TARGET_ATTRIBUTE_TABLE
202 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
204 #undef TARGET_ASM_FILE_END
205 #define TARGET_ASM_FILE_END arm_file_end
208 #undef TARGET_ASM_BYTE_OP
209 #define TARGET_ASM_BYTE_OP "\tDCB\t"
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
214 #undef TARGET_ASM_GLOBALIZE_LABEL
215 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
216 #undef TARGET_ASM_FILE_START
217 #define TARGET_ASM_FILE_START aof_file_start
218 #undef TARGET_ASM_FILE_END
219 #define TARGET_ASM_FILE_END aof_file_end
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP NULL
223 #undef TARGET_ASM_INTEGER
224 #define TARGET_ASM_INTEGER arm_assemble_integer
227 #undef TARGET_ASM_FUNCTION_PROLOGUE
228 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
230 #undef TARGET_ASM_FUNCTION_EPILOGUE
231 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
233 #undef TARGET_DEFAULT_TARGET_FLAGS
234 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
235 #undef TARGET_HANDLE_OPTION
236 #define TARGET_HANDLE_OPTION arm_handle_option
238 #undef TARGET_COMP_TYPE_ATTRIBUTES
239 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
241 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
242 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
244 #undef TARGET_SCHED_ADJUST_COST
245 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
247 #undef TARGET_ENCODE_SECTION_INFO
249 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
251 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
254 #undef TARGET_STRIP_NAME_ENCODING
255 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
257 #undef TARGET_ASM_INTERNAL_LABEL
258 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
260 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
261 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
263 #undef TARGET_ASM_OUTPUT_MI_THUNK
264 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
265 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
266 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
268 /* This will be overridden in arm_override_options. */
269 #undef TARGET_RTX_COSTS
270 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
271 #undef TARGET_ADDRESS_COST
272 #define TARGET_ADDRESS_COST arm_address_cost
274 #undef TARGET_SHIFT_TRUNCATION_MASK
275 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
276 #undef TARGET_VECTOR_MODE_SUPPORTED_P
277 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
279 #undef TARGET_MACHINE_DEPENDENT_REORG
280 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
282 #undef TARGET_INIT_BUILTINS
283 #define TARGET_INIT_BUILTINS arm_init_builtins
284 #undef TARGET_EXPAND_BUILTIN
285 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
287 #undef TARGET_INIT_LIBFUNCS
288 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
290 #undef TARGET_PROMOTE_FUNCTION_ARGS
291 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
292 #undef TARGET_PROMOTE_FUNCTION_RETURN
293 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
294 #undef TARGET_PROMOTE_PROTOTYPES
295 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
296 #undef TARGET_PASS_BY_REFERENCE
297 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
298 #undef TARGET_ARG_PARTIAL_BYTES
299 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
301 #undef TARGET_STRUCT_VALUE_RTX
302 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
304 #undef TARGET_SETUP_INCOMING_VARARGS
305 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
307 #undef TARGET_DEFAULT_SHORT_ENUMS
308 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
310 #undef TARGET_ALIGN_ANON_BITFIELD
311 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
313 #undef TARGET_CXX_GUARD_TYPE
314 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
316 #undef TARGET_CXX_GUARD_MASK_BIT
317 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
319 #undef TARGET_CXX_GET_COOKIE_SIZE
320 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
322 #undef TARGET_CXX_COOKIE_HAS_SIZE
323 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
325 #undef TARGET_CXX_CDTOR_RETURNS_THIS
326 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
328 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
329 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
331 #undef TARGET_CXX_USE_AEABI_ATEXIT
332 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
334 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
335 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
336 arm_cxx_determine_class_data_visibility
338 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
339 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
341 #undef TARGET_RETURN_IN_MSB
342 #define TARGET_RETURN_IN_MSB arm_return_in_msb
344 #undef TARGET_MUST_PASS_IN_STACK
345 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
347 #ifdef TARGET_UNWIND_INFO
348 #undef TARGET_UNWIND_EMIT
349 #define TARGET_UNWIND_EMIT arm_unwind_emit
351 /* EABI unwinding tables use a different format for the typeinfo tables. */
352 #undef TARGET_ASM_TTYPE
353 #define TARGET_ASM_TTYPE arm_output_ttype
355 #undef TARGET_ARM_EABI_UNWINDER
356 #define TARGET_ARM_EABI_UNWINDER true
357 #endif /* TARGET_UNWIND_INFO */
359 #undef TARGET_CANNOT_COPY_INSN_P
360 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
363 #undef TARGET_HAVE_TLS
364 #define TARGET_HAVE_TLS true
367 #undef TARGET_CANNOT_FORCE_CONST_MEM
368 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
370 struct gcc_target targetm
= TARGET_INITIALIZER
;
372 /* Obstack for minipool constant handling. */
373 static struct obstack minipool_obstack
;
374 static char * minipool_startobj
;
376 /* The maximum number of insns skipped which
377 will be conditionalised if possible. */
378 static int max_insns_skipped
= 5;
380 extern FILE * asm_out_file
;
382 /* True if we are currently building a constant table. */
383 int making_const_table
;
385 /* Define the information needed to generate branch insns. This is
386 stored from the compare operation. */
387 rtx arm_compare_op0
, arm_compare_op1
;
389 /* The processor for which instructions should be scheduled. */
390 enum processor_type arm_tune
= arm_none
;
392 /* Which floating point model to use. */
393 enum arm_fp_model arm_fp_model
;
395 /* Which floating point hardware is available. */
396 enum fputype arm_fpu_arch
;
398 /* Which floating point hardware to schedule for. */
399 enum fputype arm_fpu_tune
;
401 /* Whether to use floating point hardware. */
402 enum float_abi_type arm_float_abi
;
404 /* Which ABI to use. */
405 enum arm_abi_type arm_abi
;
407 /* Which thread pointer model to use. */
408 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
410 /* Used to parse -mstructure_size_boundary command line option. */
411 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
413 /* Used for Thumb call_via trampolines. */
414 rtx thumb_call_via_label
[14];
415 static int thumb_call_reg_needed
;
417 /* Bit values used to identify processor capabilities. */
418 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
419 #define FL_ARCH3M (1 << 1) /* Extended multiply */
420 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
421 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
422 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
423 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
424 #define FL_THUMB (1 << 6) /* Thumb aware */
425 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
426 #define FL_STRONG (1 << 8) /* StrongARM */
427 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
428 #define FL_XSCALE (1 << 10) /* XScale */
429 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
430 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
431 media instructions. */
432 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
433 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
434 Note: ARM6 & 7 derivatives only. */
435 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
437 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
439 #define FL_FOR_ARCH2 0
440 #define FL_FOR_ARCH3 FL_MODE32
441 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
442 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
443 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
444 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
445 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
446 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
447 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
448 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
449 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
450 #define FL_FOR_ARCH6J FL_FOR_ARCH6
451 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
452 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
453 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
455 /* The bits in this mask specify which
456 instructions we are allowed to generate. */
457 static unsigned long insn_flags
= 0;
459 /* The bits in this mask specify which instruction scheduling options should
461 static unsigned long tune_flags
= 0;
463 /* The following are used in the arm.md file as equivalents to bits
464 in the above two flag variables. */
466 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
469 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
472 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
475 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
478 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
481 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
484 /* Nonzero if this chip supports the ARM 6K extensions. */
487 /* Nonzero if this chip can benefit from load scheduling. */
488 int arm_ld_sched
= 0;
490 /* Nonzero if this chip is a StrongARM. */
491 int arm_tune_strongarm
= 0;
493 /* Nonzero if this chip is a Cirrus variant. */
494 int arm_arch_cirrus
= 0;
496 /* Nonzero if this chip supports Intel Wireless MMX technology. */
497 int arm_arch_iwmmxt
= 0;
499 /* Nonzero if this chip is an XScale. */
500 int arm_arch_xscale
= 0;
502 /* Nonzero if tuning for XScale */
503 int arm_tune_xscale
= 0;
505 /* Nonzero if we want to tune for stores that access the write-buffer.
506 This typically means an ARM6 or ARM7 with MMU or MPU. */
507 int arm_tune_wbuf
= 0;
509 /* Nonzero if generating Thumb instructions. */
512 /* Nonzero if we should define __THUMB_INTERWORK__ in the
514 XXX This is a bit of a hack, it's intended to help work around
515 problems in GLD which doesn't understand that armv5t code is
516 interworking clean. */
517 int arm_cpp_interwork
= 0;
519 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
520 must report the mode of the memory reference from PRINT_OPERAND to
521 PRINT_OPERAND_ADDRESS. */
522 enum machine_mode output_memory_reference_mode
;
524 /* The register number to be used for the PIC offset register. */
525 int arm_pic_register
= INVALID_REGNUM
;
527 /* Set to 1 when a return insn is output, this means that the epilogue
529 int return_used_this_function
;
531 /* Set to 1 after arm_reorg has started. Reset to start at the start of
532 the next function. */
533 static int after_arm_reorg
= 0;
535 /* The maximum number of insns to be used when loading a constant. */
536 static int arm_constant_limit
= 3;
538 /* For an explanation of these variables, see final_prescan_insn below. */
540 enum arm_cond_code arm_current_cc
;
542 int arm_target_label
;
544 /* The condition codes of the ARM, and the inverse function. */
545 static const char * const arm_condition_codes
[] =
547 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
548 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
551 #define streq(string1, string2) (strcmp (string1, string2) == 0)
553 /* Initialization code. */
557 const char *const name
;
558 enum processor_type core
;
560 const unsigned long flags
;
561 bool (* rtx_costs
) (rtx
, int, int, int *);
564 /* Not all of these give usefully different compilation alternatives,
565 but there is no simple way of generalizing them. */
566 static const struct processors all_cores
[] =
569 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
570 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
571 #include "arm-cores.def"
573 {NULL
, arm_none
, NULL
, 0, NULL
}
576 static const struct processors all_architectures
[] =
578 /* ARM Architectures */
579 /* We don't specify rtx_costs here as it will be figured out
582 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
583 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
584 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
585 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
586 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
587 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
588 implementations that support it, so we will leave it out for now. */
589 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
590 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
591 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
592 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
593 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
594 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
595 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
596 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
597 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
598 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
599 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
600 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
601 {NULL
, arm_none
, NULL
, 0 , NULL
}
604 struct arm_cpu_select
608 const struct processors
* processors
;
611 /* This is a magic structure. The 'string' field is magically filled in
612 with a pointer to the value specified by the user on the command line
613 assuming that the user has specified such a value. */
615 static struct arm_cpu_select arm_select
[] =
617 /* string name processors */
618 { NULL
, "-mcpu=", all_cores
},
619 { NULL
, "-march=", all_architectures
},
620 { NULL
, "-mtune=", all_cores
}
623 /* Defines representing the indexes into the above table. */
624 #define ARM_OPT_SET_CPU 0
625 #define ARM_OPT_SET_ARCH 1
626 #define ARM_OPT_SET_TUNE 2
628 /* The name of the proprocessor macro to define for this architecture. */
630 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
639 /* Available values for for -mfpu=. */
641 static const struct fpu_desc all_fpus
[] =
643 {"fpa", FPUTYPE_FPA
},
644 {"fpe2", FPUTYPE_FPA_EMU2
},
645 {"fpe3", FPUTYPE_FPA_EMU2
},
646 {"maverick", FPUTYPE_MAVERICK
},
651 /* Floating point models used by the different hardware.
652 See fputype in arm.h. */
654 static const enum fputype fp_model_for_fpu
[] =
656 /* No FP hardware. */
657 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
658 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
659 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
660 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
661 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
662 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
669 enum float_abi_type abi_type
;
673 /* Available values for -mfloat-abi=. */
675 static const struct float_abi all_float_abis
[] =
677 {"soft", ARM_FLOAT_ABI_SOFT
},
678 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
679 {"hard", ARM_FLOAT_ABI_HARD
}
686 enum arm_abi_type abi_type
;
690 /* Available values for -mabi=. */
692 static const struct abi_name arm_all_abis
[] =
694 {"apcs-gnu", ARM_ABI_APCS
},
695 {"atpcs", ARM_ABI_ATPCS
},
696 {"aapcs", ARM_ABI_AAPCS
},
697 {"iwmmxt", ARM_ABI_IWMMXT
},
698 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
701 /* Supported TLS relocations. */
711 /* Return the number of bits set in VALUE. */
713 bit_count (unsigned long value
)
715 unsigned long count
= 0;
720 value
&= value
- 1; /* Clear the least-significant set bit. */
726 /* Set up library functions unique to ARM. */
729 arm_init_libfuncs (void)
731 /* There are no special library functions unless we are using the
736 /* The functions below are described in Section 4 of the "Run-Time
737 ABI for the ARM architecture", Version 1.0. */
739 /* Double-precision floating-point arithmetic. Table 2. */
740 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
741 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
742 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
743 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
744 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
746 /* Double-precision comparisons. Table 3. */
747 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
748 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
749 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
750 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
751 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
752 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
753 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
755 /* Single-precision floating-point arithmetic. Table 4. */
756 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
757 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
758 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
759 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
760 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
762 /* Single-precision comparisons. Table 5. */
763 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
764 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
765 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
766 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
767 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
768 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
769 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
771 /* Floating-point to integer conversions. Table 6. */
772 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
773 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
774 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
775 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
776 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
777 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
778 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
779 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
781 /* Conversions between floating types. Table 7. */
782 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
783 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
785 /* Integer to floating-point conversions. Table 8. */
786 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
787 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
788 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
789 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
790 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
791 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
792 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
793 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
795 /* Long long. Table 9. */
796 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
797 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
798 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
799 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
800 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
801 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
802 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
803 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
805 /* Integer (32/32->32) division. \S 4.3.1. */
806 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
807 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
809 /* The divmod functions are designed so that they can be used for
810 plain division, even though they return both the quotient and the
811 remainder. The quotient is returned in the usual location (i.e.,
812 r0 for SImode, {r0, r1} for DImode), just as would be expected
813 for an ordinary division routine. Because the AAPCS calling
814 conventions specify that all of { r0, r1, r2, r3 } are
815 callee-saved registers, there is no need to tell the compiler
816 explicitly that those registers are clobbered by these
818 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
819 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
821 /* For SImode division the ABI provides div-without-mod routines,
823 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
824 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
826 /* We don't have mod libcalls. Fortunately gcc knows how to use the
827 divmod libcalls instead. */
828 set_optab_libfunc (smod_optab
, DImode
, NULL
);
829 set_optab_libfunc (umod_optab
, DImode
, NULL
);
830 set_optab_libfunc (smod_optab
, SImode
, NULL
);
831 set_optab_libfunc (umod_optab
, SImode
, NULL
);
834 /* Implement TARGET_HANDLE_OPTION. */
837 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
842 arm_select
[1].string
= arg
;
846 arm_select
[0].string
= arg
;
849 case OPT_mhard_float
:
850 target_float_abi_name
= "hard";
853 case OPT_msoft_float
:
854 target_float_abi_name
= "soft";
858 arm_select
[2].string
= arg
;
866 /* Fix up any incompatible options that the user has specified.
867 This has now turned into a maze. */
869 arm_override_options (void)
872 enum processor_type target_arch_cpu
= arm_none
;
874 /* Set up the flags based on the cpu/architecture selected by the user. */
875 for (i
= ARRAY_SIZE (arm_select
); i
--;)
877 struct arm_cpu_select
* ptr
= arm_select
+ i
;
879 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
881 const struct processors
* sel
;
883 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
884 if (streq (ptr
->string
, sel
->name
))
886 /* Set the architecture define. */
887 if (i
!= ARM_OPT_SET_TUNE
)
888 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
890 /* Determine the processor core for which we should
891 tune code-generation. */
892 if (/* -mcpu= is a sensible default. */
894 /* -mtune= overrides -mcpu= and -march=. */
895 || i
== ARM_OPT_SET_TUNE
)
896 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
898 /* Remember the CPU associated with this architecture.
899 If no other option is used to set the CPU type,
900 we'll use this to guess the most suitable tuning
902 if (i
== ARM_OPT_SET_ARCH
)
903 target_arch_cpu
= sel
->core
;
905 if (i
!= ARM_OPT_SET_TUNE
)
907 /* If we have been given an architecture and a processor
908 make sure that they are compatible. We only generate
909 a warning though, and we prefer the CPU over the
911 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
912 warning (0, "switch -mcpu=%s conflicts with -march= switch",
915 insn_flags
= sel
->flags
;
921 if (sel
->name
== NULL
)
922 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
926 /* Guess the tuning options from the architecture if necessary. */
927 if (arm_tune
== arm_none
)
928 arm_tune
= target_arch_cpu
;
930 /* If the user did not specify a processor, choose one for them. */
933 const struct processors
* sel
;
935 enum processor_type cpu
;
937 cpu
= TARGET_CPU_DEFAULT
;
940 #ifdef SUBTARGET_CPU_DEFAULT
941 /* Use the subtarget default CPU if none was specified by
943 cpu
= SUBTARGET_CPU_DEFAULT
;
945 /* Default to ARM6. */
949 sel
= &all_cores
[cpu
];
951 insn_flags
= sel
->flags
;
953 /* Now check to see if the user has specified some command line
954 switch that require certain abilities from the cpu. */
957 if (TARGET_INTERWORK
|| TARGET_THUMB
)
959 sought
|= (FL_THUMB
| FL_MODE32
);
961 /* There are no ARM processors that support both APCS-26 and
962 interworking. Therefore we force FL_MODE26 to be removed
963 from insn_flags here (if it was set), so that the search
964 below will always be able to find a compatible processor. */
965 insn_flags
&= ~FL_MODE26
;
968 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
970 /* Try to locate a CPU type that supports all of the abilities
971 of the default CPU, plus the extra abilities requested by
973 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
974 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
977 if (sel
->name
== NULL
)
979 unsigned current_bit_count
= 0;
980 const struct processors
* best_fit
= NULL
;
982 /* Ideally we would like to issue an error message here
983 saying that it was not possible to find a CPU compatible
984 with the default CPU, but which also supports the command
985 line options specified by the programmer, and so they
986 ought to use the -mcpu=<name> command line option to
987 override the default CPU type.
989 If we cannot find a cpu that has both the
990 characteristics of the default cpu and the given
991 command line options we scan the array again looking
993 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
994 if ((sel
->flags
& sought
) == sought
)
998 count
= bit_count (sel
->flags
& insn_flags
);
1000 if (count
>= current_bit_count
)
1003 current_bit_count
= count
;
1007 gcc_assert (best_fit
);
1011 insn_flags
= sel
->flags
;
1013 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1014 if (arm_tune
== arm_none
)
1015 arm_tune
= (enum processor_type
) (sel
- all_cores
);
1018 /* The processor for which we should tune should now have been
1020 gcc_assert (arm_tune
!= arm_none
);
1022 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1024 targetm
.rtx_costs
= arm_size_rtx_costs
;
1026 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1028 /* Make sure that the processor choice does not conflict with any of the
1029 other command line choices. */
1030 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1032 warning (0, "target CPU does not support interworking" );
1033 target_flags
&= ~MASK_INTERWORK
;
1036 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1038 warning (0, "target CPU does not support THUMB instructions");
1039 target_flags
&= ~MASK_THUMB
;
1042 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1044 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1045 target_flags
&= ~MASK_APCS_FRAME
;
1048 /* Callee super interworking implies thumb interworking. Adding
1049 this to the flags here simplifies the logic elsewhere. */
1050 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1051 target_flags
|= MASK_INTERWORK
;
1053 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1054 from here where no function is being compiled currently. */
1055 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1056 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1058 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1059 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1061 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1062 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1064 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1066 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1067 target_flags
|= MASK_APCS_FRAME
;
1070 if (TARGET_POKE_FUNCTION_NAME
)
1071 target_flags
|= MASK_APCS_FRAME
;
1073 if (TARGET_APCS_REENT
&& flag_pic
)
1074 error ("-fpic and -mapcs-reent are incompatible");
1076 if (TARGET_APCS_REENT
)
1077 warning (0, "APCS reentrant code not supported. Ignored");
1079 /* If this target is normally configured to use APCS frames, warn if they
1080 are turned off and debugging is turned on. */
1082 && write_symbols
!= NO_DEBUG
1083 && !TARGET_APCS_FRAME
1084 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1085 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1087 /* If stack checking is disabled, we can use r10 as the PIC register,
1088 which keeps r9 available. */
1090 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1092 if (TARGET_APCS_FLOAT
)
1093 warning (0, "passing floating point arguments in fp regs not yet supported");
1095 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1096 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1097 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1098 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1099 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1100 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1101 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1102 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1103 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1104 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1106 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1107 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1108 thumb_code
= (TARGET_ARM
== 0);
1109 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1110 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1111 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1113 /* V5 code we generate is completely interworking capable, so we turn off
1114 TARGET_INTERWORK here to avoid many tests later on. */
1116 /* XXX However, we must pass the right pre-processor defines to CPP
1117 or GLD can get confused. This is a hack. */
1118 if (TARGET_INTERWORK
)
1119 arm_cpp_interwork
= 1;
1122 target_flags
&= ~MASK_INTERWORK
;
1124 if (target_abi_name
)
1126 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1128 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1130 arm_abi
= arm_all_abis
[i
].abi_type
;
1134 if (i
== ARRAY_SIZE (arm_all_abis
))
1135 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1138 arm_abi
= ARM_DEFAULT_ABI
;
1140 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1141 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1143 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1144 error ("iwmmxt abi requires an iwmmxt capable cpu");
1146 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1147 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1149 if (streq (target_fpe_name
, "2"))
1150 target_fpu_name
= "fpe2";
1151 else if (streq (target_fpe_name
, "3"))
1152 target_fpu_name
= "fpe3";
1154 error ("invalid floating point emulation option: -mfpe=%s",
1157 if (target_fpu_name
!= NULL
)
1159 /* The user specified a FPU. */
1160 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1162 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1164 arm_fpu_arch
= all_fpus
[i
].fpu
;
1165 arm_fpu_tune
= arm_fpu_arch
;
1166 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1170 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1171 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1175 #ifdef FPUTYPE_DEFAULT
1176 /* Use the default if it is specified for this platform. */
1177 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1178 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1180 /* Pick one based on CPU type. */
1181 /* ??? Some targets assume FPA is the default.
1182 if ((insn_flags & FL_VFP) != 0)
1183 arm_fpu_arch = FPUTYPE_VFP;
1186 if (arm_arch_cirrus
)
1187 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1189 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1191 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1192 arm_fpu_tune
= FPUTYPE_FPA
;
1194 arm_fpu_tune
= arm_fpu_arch
;
1195 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1196 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1199 if (target_float_abi_name
!= NULL
)
1201 /* The user specified a FP ABI. */
1202 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1204 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1206 arm_float_abi
= all_float_abis
[i
].abi_type
;
1210 if (i
== ARRAY_SIZE (all_float_abis
))
1211 error ("invalid floating point abi: -mfloat-abi=%s",
1212 target_float_abi_name
);
1215 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1217 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1218 sorry ("-mfloat-abi=hard and VFP");
1220 /* If soft-float is specified then don't use FPU. */
1221 if (TARGET_SOFT_FLOAT
)
1222 arm_fpu_arch
= FPUTYPE_NONE
;
1224 /* For arm2/3 there is no need to do any scheduling if there is only
1225 a floating point emulator, or we are doing software floating-point. */
1226 if ((TARGET_SOFT_FLOAT
1227 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1228 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1229 && (tune_flags
& FL_MODE32
) == 0)
1230 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1232 if (target_thread_switch
)
1234 if (strcmp (target_thread_switch
, "soft") == 0)
1235 target_thread_pointer
= TP_SOFT
;
1236 else if (strcmp (target_thread_switch
, "auto") == 0)
1237 target_thread_pointer
= TP_AUTO
;
1238 else if (strcmp (target_thread_switch
, "cp15") == 0)
1239 target_thread_pointer
= TP_CP15
;
1241 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1244 /* Use the cp15 method if it is available. */
1245 if (target_thread_pointer
== TP_AUTO
)
1247 if (arm_arch6k
&& !TARGET_THUMB
)
1248 target_thread_pointer
= TP_CP15
;
1250 target_thread_pointer
= TP_SOFT
;
1253 if (TARGET_HARD_TP
&& TARGET_THUMB
)
1254 error ("can not use -mtp=cp15 with -mthumb");
1256 /* Override the default structure alignment for AAPCS ABI. */
1257 if (TARGET_AAPCS_BASED
)
1258 arm_structure_size_boundary
= 8;
1260 if (structure_size_string
!= NULL
)
1262 int size
= strtol (structure_size_string
, NULL
, 0);
1264 if (size
== 8 || size
== 32
1265 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1266 arm_structure_size_boundary
= size
;
1268 warning (0, "structure size boundary can only be set to %s",
1269 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1272 if (arm_pic_register_string
!= NULL
)
1274 int pic_register
= decode_reg_name (arm_pic_register_string
);
1277 warning (0, "-mpic-register= is useless without -fpic");
1279 /* Prevent the user from choosing an obviously stupid PIC register. */
1280 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1281 || pic_register
== HARD_FRAME_POINTER_REGNUM
1282 || pic_register
== STACK_POINTER_REGNUM
1283 || pic_register
>= PC_REGNUM
)
1284 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1286 arm_pic_register
= pic_register
;
1289 if (TARGET_THUMB
&& flag_schedule_insns
)
1291 /* Don't warn since it's on by default in -O2. */
1292 flag_schedule_insns
= 0;
1297 arm_constant_limit
= 1;
1299 /* If optimizing for size, bump the number of instructions that we
1300 are prepared to conditionally execute (even on a StrongARM). */
1301 max_insns_skipped
= 6;
1305 /* For processors with load scheduling, it never costs more than
1306 2 cycles to load a constant, and the load scheduler may well
1307 reduce that to 1. */
1309 arm_constant_limit
= 1;
1311 /* On XScale the longer latency of a load makes it more difficult
1312 to achieve a good schedule, so it's faster to synthesize
1313 constants that can be done in two insns. */
1314 if (arm_tune_xscale
)
1315 arm_constant_limit
= 2;
1317 /* StrongARM has early execution of branches, so a sequence
1318 that is worth skipping is shorter. */
1319 if (arm_tune_strongarm
)
1320 max_insns_skipped
= 3;
1323 /* Register global variables with the garbage collector. */
1324 arm_add_gc_roots ();
1328 arm_add_gc_roots (void)
1330 gcc_obstack_init(&minipool_obstack
);
1331 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1334 /* A table of known ARM exception types.
1335 For use with the interrupt function attribute. */
1339 const char *const arg
;
1340 const unsigned long return_value
;
1344 static const isr_attribute_arg isr_attribute_args
[] =
1346 { "IRQ", ARM_FT_ISR
},
1347 { "irq", ARM_FT_ISR
},
1348 { "FIQ", ARM_FT_FIQ
},
1349 { "fiq", ARM_FT_FIQ
},
1350 { "ABORT", ARM_FT_ISR
},
1351 { "abort", ARM_FT_ISR
},
1352 { "ABORT", ARM_FT_ISR
},
1353 { "abort", ARM_FT_ISR
},
1354 { "UNDEF", ARM_FT_EXCEPTION
},
1355 { "undef", ARM_FT_EXCEPTION
},
1356 { "SWI", ARM_FT_EXCEPTION
},
1357 { "swi", ARM_FT_EXCEPTION
},
1358 { NULL
, ARM_FT_NORMAL
}
1361 /* Returns the (interrupt) function type of the current
1362 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1364 static unsigned long
1365 arm_isr_value (tree argument
)
1367 const isr_attribute_arg
* ptr
;
1370 /* No argument - default to IRQ. */
1371 if (argument
== NULL_TREE
)
1374 /* Get the value of the argument. */
1375 if (TREE_VALUE (argument
) == NULL_TREE
1376 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1377 return ARM_FT_UNKNOWN
;
1379 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1381 /* Check it against the list of known arguments. */
1382 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1383 if (streq (arg
, ptr
->arg
))
1384 return ptr
->return_value
;
1386 /* An unrecognized interrupt type. */
1387 return ARM_FT_UNKNOWN
;
1390 /* Computes the type of the current function. */
1392 static unsigned long
1393 arm_compute_func_type (void)
1395 unsigned long type
= ARM_FT_UNKNOWN
;
1399 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1401 /* Decide if the current function is volatile. Such functions
1402 never return, and many memory cycles can be saved by not storing
1403 register values that will never be needed again. This optimization
1404 was added to speed up context switching in a kernel application. */
1406 && TREE_NOTHROW (current_function_decl
)
1407 && TREE_THIS_VOLATILE (current_function_decl
))
1408 type
|= ARM_FT_VOLATILE
;
1410 if (cfun
->static_chain_decl
!= NULL
)
1411 type
|= ARM_FT_NESTED
;
1413 attr
= DECL_ATTRIBUTES (current_function_decl
);
1415 a
= lookup_attribute ("naked", attr
);
1417 type
|= ARM_FT_NAKED
;
1419 a
= lookup_attribute ("isr", attr
);
1421 a
= lookup_attribute ("interrupt", attr
);
1424 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1426 type
|= arm_isr_value (TREE_VALUE (a
));
1431 /* Returns the type of the current function. */
1434 arm_current_func_type (void)
1436 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1437 cfun
->machine
->func_type
= arm_compute_func_type ();
1439 return cfun
->machine
->func_type
;
1442 /* Return 1 if it is possible to return using a single instruction.
1443 If SIBLING is non-null, this is a test for a return before a sibling
1444 call. SIBLING is the call insn, so we can examine its register usage. */
1447 use_return_insn (int iscond
, rtx sibling
)
1450 unsigned int func_type
;
1451 unsigned long saved_int_regs
;
1452 unsigned HOST_WIDE_INT stack_adjust
;
1453 arm_stack_offsets
*offsets
;
1455 /* Never use a return instruction before reload has run. */
1456 if (!reload_completed
)
1459 func_type
= arm_current_func_type ();
1461 /* Naked functions and volatile functions need special
1463 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1466 /* So do interrupt functions that use the frame pointer. */
1467 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1470 offsets
= arm_get_frame_offsets ();
1471 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1473 /* As do variadic functions. */
1474 if (current_function_pretend_args_size
1475 || cfun
->machine
->uses_anonymous_args
1476 /* Or if the function calls __builtin_eh_return () */
1477 || current_function_calls_eh_return
1478 /* Or if the function calls alloca */
1479 || current_function_calls_alloca
1480 /* Or if there is a stack adjustment. However, if the stack pointer
1481 is saved on the stack, we can use a pre-incrementing stack load. */
1482 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1485 saved_int_regs
= arm_compute_save_reg_mask ();
1487 /* Unfortunately, the insn
1489 ldmib sp, {..., sp, ...}
1491 triggers a bug on most SA-110 based devices, such that the stack
1492 pointer won't be correctly restored if the instruction takes a
1493 page fault. We work around this problem by popping r3 along with
1494 the other registers, since that is never slower than executing
1495 another instruction.
1497 We test for !arm_arch5 here, because code for any architecture
1498 less than this could potentially be run on one of the buggy
1500 if (stack_adjust
== 4 && !arm_arch5
)
1502 /* Validate that r3 is a call-clobbered register (always true in
1503 the default abi) ... */
1504 if (!call_used_regs
[3])
1507 /* ... that it isn't being used for a return value ... */
1508 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1511 /* ... or for a tail-call argument ... */
1514 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1516 if (find_regno_fusage (sibling
, USE
, 3))
1520 /* ... and that there are no call-saved registers in r0-r2
1521 (always true in the default ABI). */
1522 if (saved_int_regs
& 0x7)
1526 /* Can't be done if interworking with Thumb, and any registers have been
1528 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1531 /* On StrongARM, conditional returns are expensive if they aren't
1532 taken and multiple registers have been stacked. */
1533 if (iscond
&& arm_tune_strongarm
)
1535 /* Conditional return when just the LR is stored is a simple
1536 conditional-load instruction, that's not expensive. */
1537 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1540 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1544 /* If there are saved registers but the LR isn't saved, then we need
1545 two instructions for the return. */
1546 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1549 /* Can't be done if any of the FPA regs are pushed,
1550 since this also requires an insn. */
1551 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1552 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1553 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1556 /* Likewise VFP regs. */
1557 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1558 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1559 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1562 if (TARGET_REALLY_IWMMXT
)
1563 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1564 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1570 /* Return TRUE if int I is a valid immediate ARM constant. */
1573 const_ok_for_arm (HOST_WIDE_INT i
)
1577 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1578 be all zero, or all one. */
1579 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1580 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1581 != ((~(unsigned HOST_WIDE_INT
) 0)
1582 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1585 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1587 /* Fast return for 0 and small values. We must do this for zero, since
1588 the code below can't handle that one case. */
1589 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1592 /* Get the number of trailing zeros, rounded down to the nearest even
1594 lowbit
= (ffs ((int) i
) - 1) & ~1;
1596 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1598 else if (lowbit
<= 4
1599 && ((i
& ~0xc000003f) == 0
1600 || (i
& ~0xf000000f) == 0
1601 || (i
& ~0xfc000003) == 0))
1607 /* Return true if I is a valid constant for the operation CODE. */
1609 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1611 if (const_ok_for_arm (i
))
1617 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1619 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1625 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1632 /* Emit a sequence of insns to handle a large constant.
1633 CODE is the code of the operation required, it can be any of SET, PLUS,
1634 IOR, AND, XOR, MINUS;
1635 MODE is the mode in which the operation is being performed;
1636 VAL is the integer to operate on;
1637 SOURCE is the other operand (a register, or a null-pointer for SET);
1638 SUBTARGETS means it is safe to create scratch registers if that will
1639 either produce a simpler sequence, or we will want to cse the values.
1640 Return value is the number of insns emitted. */
1643 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1644 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1648 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1649 cond
= COND_EXEC_TEST (PATTERN (insn
));
1653 if (subtargets
|| code
== SET
1654 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1655 && REGNO (target
) != REGNO (source
)))
1657 /* After arm_reorg has been called, we can't fix up expensive
1658 constants by pushing them into memory so we must synthesize
1659 them in-line, regardless of the cost. This is only likely to
1660 be more costly on chips that have load delay slots and we are
1661 compiling without running the scheduler (so no splitting
1662 occurred before the final instruction emission).
1664 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1666 if (!after_arm_reorg
1668 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1670 > arm_constant_limit
+ (code
!= SET
)))
1674 /* Currently SET is the only monadic value for CODE, all
1675 the rest are diadic. */
1676 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1681 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1683 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1684 /* For MINUS, the value is subtracted from, since we never
1685 have subtraction of a constant. */
1687 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1688 gen_rtx_MINUS (mode
, temp
, source
)));
1690 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1691 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1697 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1702 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1704 HOST_WIDE_INT temp1
;
1712 if (remainder
& (3 << (i
- 2)))
1717 temp1
= remainder
& ((0x0ff << end
)
1718 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1719 remainder
&= ~temp1
;
1724 } while (remainder
);
1728 /* Emit an instruction with the indicated PATTERN. If COND is
1729 non-NULL, conditionalize the execution of the instruction on COND
1733 emit_constant_insn (rtx cond
, rtx pattern
)
1736 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1737 emit_insn (pattern
);
1740 /* As above, but extra parameter GENERATE which, if clear, suppresses
1744 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1745 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1750 int can_negate_initial
= 0;
1753 int num_bits_set
= 0;
1754 int set_sign_bit_copies
= 0;
1755 int clear_sign_bit_copies
= 0;
1756 int clear_zero_bit_copies
= 0;
1757 int set_zero_bit_copies
= 0;
1759 unsigned HOST_WIDE_INT temp1
, temp2
;
1760 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1762 /* Find out which operations are safe for a given CODE. Also do a quick
1763 check for degenerate cases; these can occur when DImode operations
1775 can_negate_initial
= 1;
1779 if (remainder
== 0xffffffff)
1782 emit_constant_insn (cond
,
1783 gen_rtx_SET (VOIDmode
, target
,
1784 GEN_INT (ARM_SIGN_EXTEND (val
))));
1789 if (reload_completed
&& rtx_equal_p (target
, source
))
1792 emit_constant_insn (cond
,
1793 gen_rtx_SET (VOIDmode
, target
, source
));
1802 emit_constant_insn (cond
,
1803 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1806 if (remainder
== 0xffffffff)
1808 if (reload_completed
&& rtx_equal_p (target
, source
))
1811 emit_constant_insn (cond
,
1812 gen_rtx_SET (VOIDmode
, target
, source
));
1821 if (reload_completed
&& rtx_equal_p (target
, source
))
1824 emit_constant_insn (cond
,
1825 gen_rtx_SET (VOIDmode
, target
, source
));
1829 /* We don't know how to handle other cases yet. */
1830 gcc_assert (remainder
== 0xffffffff);
1833 emit_constant_insn (cond
,
1834 gen_rtx_SET (VOIDmode
, target
,
1835 gen_rtx_NOT (mode
, source
)));
1839 /* We treat MINUS as (val - source), since (source - val) is always
1840 passed as (source + (-val)). */
1844 emit_constant_insn (cond
,
1845 gen_rtx_SET (VOIDmode
, target
,
1846 gen_rtx_NEG (mode
, source
)));
1849 if (const_ok_for_arm (val
))
1852 emit_constant_insn (cond
,
1853 gen_rtx_SET (VOIDmode
, target
,
1854 gen_rtx_MINUS (mode
, GEN_INT (val
),
1866 /* If we can do it in one insn get out quickly. */
1867 if (const_ok_for_arm (val
)
1868 || (can_negate_initial
&& const_ok_for_arm (-val
))
1869 || (can_invert
&& const_ok_for_arm (~val
)))
1872 emit_constant_insn (cond
,
1873 gen_rtx_SET (VOIDmode
, target
,
1875 ? gen_rtx_fmt_ee (code
, mode
, source
,
1881 /* Calculate a few attributes that may be useful for specific
1883 for (i
= 31; i
>= 0; i
--)
1885 if ((remainder
& (1 << i
)) == 0)
1886 clear_sign_bit_copies
++;
1891 for (i
= 31; i
>= 0; i
--)
1893 if ((remainder
& (1 << i
)) != 0)
1894 set_sign_bit_copies
++;
1899 for (i
= 0; i
<= 31; i
++)
1901 if ((remainder
& (1 << i
)) == 0)
1902 clear_zero_bit_copies
++;
1907 for (i
= 0; i
<= 31; i
++)
1909 if ((remainder
& (1 << i
)) != 0)
1910 set_zero_bit_copies
++;
1918 /* See if we can do this by sign_extending a constant that is known
1919 to be negative. This is a good, way of doing it, since the shift
1920 may well merge into a subsequent insn. */
1921 if (set_sign_bit_copies
> 1)
1923 if (const_ok_for_arm
1924 (temp1
= ARM_SIGN_EXTEND (remainder
1925 << (set_sign_bit_copies
- 1))))
1929 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1930 emit_constant_insn (cond
,
1931 gen_rtx_SET (VOIDmode
, new_src
,
1933 emit_constant_insn (cond
,
1934 gen_ashrsi3 (target
, new_src
,
1935 GEN_INT (set_sign_bit_copies
- 1)));
1939 /* For an inverted constant, we will need to set the low bits,
1940 these will be shifted out of harm's way. */
1941 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1942 if (const_ok_for_arm (~temp1
))
1946 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1947 emit_constant_insn (cond
,
1948 gen_rtx_SET (VOIDmode
, new_src
,
1950 emit_constant_insn (cond
,
1951 gen_ashrsi3 (target
, new_src
,
1952 GEN_INT (set_sign_bit_copies
- 1)));
1958 /* See if we can calculate the value as the difference between two
1959 valid immediates. */
1960 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1962 int topshift
= clear_sign_bit_copies
& ~1;
1964 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1965 & (0xff000000 >> topshift
));
1967 /* If temp1 is zero, then that means the 9 most significant
1968 bits of remainder were 1 and we've caused it to overflow.
1969 When topshift is 0 we don't need to do anything since we
1970 can borrow from 'bit 32'. */
1971 if (temp1
== 0 && topshift
!= 0)
1972 temp1
= 0x80000000 >> (topshift
- 1);
1974 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1976 if (const_ok_for_arm (temp2
))
1980 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1981 emit_constant_insn (cond
,
1982 gen_rtx_SET (VOIDmode
, new_src
,
1984 emit_constant_insn (cond
,
1985 gen_addsi3 (target
, new_src
,
1993 /* See if we can generate this by setting the bottom (or the top)
1994 16 bits, and then shifting these into the other half of the
1995 word. We only look for the simplest cases, to do more would cost
1996 too much. Be careful, however, not to generate this when the
1997 alternative would take fewer insns. */
1998 if (val
& 0xffff0000)
2000 temp1
= remainder
& 0xffff0000;
2001 temp2
= remainder
& 0x0000ffff;
2003 /* Overlaps outside this range are best done using other methods. */
2004 for (i
= 9; i
< 24; i
++)
2006 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2007 && !const_ok_for_arm (temp2
))
2009 rtx new_src
= (subtargets
2010 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2012 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2013 source
, subtargets
, generate
);
2021 gen_rtx_ASHIFT (mode
, source
,
2028 /* Don't duplicate cases already considered. */
2029 for (i
= 17; i
< 24; i
++)
2031 if (((temp1
| (temp1
>> i
)) == remainder
)
2032 && !const_ok_for_arm (temp1
))
2034 rtx new_src
= (subtargets
2035 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2037 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2038 source
, subtargets
, generate
);
2043 gen_rtx_SET (VOIDmode
, target
,
2046 gen_rtx_LSHIFTRT (mode
, source
,
2057 /* If we have IOR or XOR, and the constant can be loaded in a
2058 single instruction, and we can find a temporary to put it in,
2059 then this can be done in two instructions instead of 3-4. */
2061 /* TARGET can't be NULL if SUBTARGETS is 0 */
2062 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2064 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2068 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2070 emit_constant_insn (cond
,
2071 gen_rtx_SET (VOIDmode
, sub
,
2073 emit_constant_insn (cond
,
2074 gen_rtx_SET (VOIDmode
, target
,
2075 gen_rtx_fmt_ee (code
, mode
,
2085 if (set_sign_bit_copies
> 8
2086 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2090 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2091 rtx shift
= GEN_INT (set_sign_bit_copies
);
2095 gen_rtx_SET (VOIDmode
, sub
,
2097 gen_rtx_ASHIFT (mode
,
2102 gen_rtx_SET (VOIDmode
, target
,
2104 gen_rtx_LSHIFTRT (mode
, sub
,
2110 if (set_zero_bit_copies
> 8
2111 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2115 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2116 rtx shift
= GEN_INT (set_zero_bit_copies
);
2120 gen_rtx_SET (VOIDmode
, sub
,
2122 gen_rtx_LSHIFTRT (mode
,
2127 gen_rtx_SET (VOIDmode
, target
,
2129 gen_rtx_ASHIFT (mode
, sub
,
2135 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2139 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2140 emit_constant_insn (cond
,
2141 gen_rtx_SET (VOIDmode
, sub
,
2142 gen_rtx_NOT (mode
, source
)));
2145 sub
= gen_reg_rtx (mode
);
2146 emit_constant_insn (cond
,
2147 gen_rtx_SET (VOIDmode
, sub
,
2148 gen_rtx_AND (mode
, source
,
2150 emit_constant_insn (cond
,
2151 gen_rtx_SET (VOIDmode
, target
,
2152 gen_rtx_NOT (mode
, sub
)));
2159 /* See if two shifts will do 2 or more insn's worth of work. */
2160 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2162 HOST_WIDE_INT shift_mask
= ((0xffffffff
2163 << (32 - clear_sign_bit_copies
))
2166 if ((remainder
| shift_mask
) != 0xffffffff)
2170 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2171 insns
= arm_gen_constant (AND
, mode
, cond
,
2172 remainder
| shift_mask
,
2173 new_src
, source
, subtargets
, 1);
2178 rtx targ
= subtargets
? NULL_RTX
: target
;
2179 insns
= arm_gen_constant (AND
, mode
, cond
,
2180 remainder
| shift_mask
,
2181 targ
, source
, subtargets
, 0);
2187 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2188 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2190 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2191 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2197 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2199 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2201 if ((remainder
| shift_mask
) != 0xffffffff)
2205 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2207 insns
= arm_gen_constant (AND
, mode
, cond
,
2208 remainder
| shift_mask
,
2209 new_src
, source
, subtargets
, 1);
2214 rtx targ
= subtargets
? NULL_RTX
: target
;
2216 insns
= arm_gen_constant (AND
, mode
, cond
,
2217 remainder
| shift_mask
,
2218 targ
, source
, subtargets
, 0);
2224 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2225 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2227 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2228 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2240 for (i
= 0; i
< 32; i
++)
2241 if (remainder
& (1 << i
))
2244 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2245 remainder
= (~remainder
) & 0xffffffff;
2246 else if (code
== PLUS
&& num_bits_set
> 16)
2247 remainder
= (-remainder
) & 0xffffffff;
2254 /* Now try and find a way of doing the job in either two or three
2256 We start by looking for the largest block of zeros that are aligned on
2257 a 2-bit boundary, we then fill up the temps, wrapping around to the
2258 top of the word when we drop off the bottom.
2259 In the worst case this code should produce no more than four insns. */
2262 int best_consecutive_zeros
= 0;
2264 for (i
= 0; i
< 32; i
+= 2)
2266 int consecutive_zeros
= 0;
2268 if (!(remainder
& (3 << i
)))
2270 while ((i
< 32) && !(remainder
& (3 << i
)))
2272 consecutive_zeros
+= 2;
2275 if (consecutive_zeros
> best_consecutive_zeros
)
2277 best_consecutive_zeros
= consecutive_zeros
;
2278 best_start
= i
- consecutive_zeros
;
2284 /* So long as it won't require any more insns to do so, it's
2285 desirable to emit a small constant (in bits 0...9) in the last
2286 insn. This way there is more chance that it can be combined with
2287 a later addressing insn to form a pre-indexed load or store
2288 operation. Consider:
2290 *((volatile int *)0xe0000100) = 1;
2291 *((volatile int *)0xe0000110) = 2;
2293 We want this to wind up as:
2297 str rB, [rA, #0x100]
2299 str rB, [rA, #0x110]
2301 rather than having to synthesize both large constants from scratch.
2303 Therefore, we calculate how many insns would be required to emit
2304 the constant starting from `best_start', and also starting from
2305 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2306 yield a shorter sequence, we may as well use zero. */
2308 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2309 && (count_insns_for_constant (remainder
, 0) <=
2310 count_insns_for_constant (remainder
, best_start
)))
2313 /* Now start emitting the insns. */
2321 if (remainder
& (3 << (i
- 2)))
2326 temp1
= remainder
& ((0x0ff << end
)
2327 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2328 remainder
&= ~temp1
;
2332 rtx new_src
, temp1_rtx
;
2334 if (code
== SET
|| code
== MINUS
)
2336 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2337 if (can_invert
&& code
!= MINUS
)
2342 if (remainder
&& subtargets
)
2343 new_src
= gen_reg_rtx (mode
);
2348 else if (can_negate
)
2352 temp1
= trunc_int_for_mode (temp1
, mode
);
2353 temp1_rtx
= GEN_INT (temp1
);
2357 else if (code
== MINUS
)
2358 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2360 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2362 emit_constant_insn (cond
,
2363 gen_rtx_SET (VOIDmode
, new_src
,
2373 else if (code
== MINUS
)
2387 /* Canonicalize a comparison so that we are more likely to recognize it.
2388 This can be done for a few constant compares, where we can make the
2389 immediate value easier to load. */
2392 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2395 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2396 unsigned HOST_WIDE_INT maxval
;
2397 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2408 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2410 *op1
= GEN_INT (i
+ 1);
2411 return code
== GT
? GE
: LT
;
2418 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2420 *op1
= GEN_INT (i
- 1);
2421 return code
== GE
? GT
: LE
;
2427 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2428 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2430 *op1
= GEN_INT (i
+ 1);
2431 return code
== GTU
? GEU
: LTU
;
2438 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2440 *op1
= GEN_INT (i
- 1);
2441 return code
== GEU
? GTU
: LEU
;
2453 /* Define how to find the value returned by a function. */
2456 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2458 enum machine_mode mode
;
2459 int unsignedp ATTRIBUTE_UNUSED
;
2460 rtx r ATTRIBUTE_UNUSED
;
2462 mode
= TYPE_MODE (type
);
2463 /* Promote integer types. */
2464 if (INTEGRAL_TYPE_P (type
))
2465 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2467 /* Promotes small structs returned in a register to full-word size
2468 for big-endian AAPCS. */
2469 if (arm_return_in_msb (type
))
2471 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2472 if (size
% UNITS_PER_WORD
!= 0)
2474 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2475 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2479 return LIBCALL_VALUE(mode
);
2482 /* Determine the amount of memory needed to store the possible return
2483 registers of an untyped call. */
2485 arm_apply_result_size (void)
2491 if (TARGET_HARD_FLOAT_ABI
)
2495 if (TARGET_MAVERICK
)
2498 if (TARGET_IWMMXT_ABI
)
2505 /* Decide whether a type should be returned in memory (true)
2506 or in a register (false). This is called by the macro
2507 RETURN_IN_MEMORY. */
2509 arm_return_in_memory (tree type
)
2513 if (!AGGREGATE_TYPE_P (type
) &&
2514 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2515 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2516 /* All simple types are returned in registers.
2517 For AAPCS, complex types are treated the same as aggregates. */
2520 size
= int_size_in_bytes (type
);
2522 if (arm_abi
!= ARM_ABI_APCS
)
2524 /* ATPCS and later return aggregate types in memory only if they are
2525 larger than a word (or are variable size). */
2526 return (size
< 0 || size
> UNITS_PER_WORD
);
2529 /* To maximize backwards compatibility with previous versions of gcc,
2530 return vectors up to 4 words in registers. */
2531 if (TREE_CODE (type
) == VECTOR_TYPE
)
2532 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2534 /* For the arm-wince targets we choose to be compatible with Microsoft's
2535 ARM and Thumb compilers, which always return aggregates in memory. */
2537 /* All structures/unions bigger than one word are returned in memory.
2538 Also catch the case where int_size_in_bytes returns -1. In this case
2539 the aggregate is either huge or of variable size, and in either case
2540 we will want to return it via memory and not in a register. */
2541 if (size
< 0 || size
> UNITS_PER_WORD
)
2544 if (TREE_CODE (type
) == RECORD_TYPE
)
2548 /* For a struct the APCS says that we only return in a register
2549 if the type is 'integer like' and every addressable element
2550 has an offset of zero. For practical purposes this means
2551 that the structure can have at most one non bit-field element
2552 and that this element must be the first one in the structure. */
2554 /* Find the first field, ignoring non FIELD_DECL things which will
2555 have been created by C++. */
2556 for (field
= TYPE_FIELDS (type
);
2557 field
&& TREE_CODE (field
) != FIELD_DECL
;
2558 field
= TREE_CHAIN (field
))
2562 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2564 /* Check that the first field is valid for returning in a register. */
2566 /* ... Floats are not allowed */
2567 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2570 /* ... Aggregates that are not themselves valid for returning in
2571 a register are not allowed. */
2572 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2575 /* Now check the remaining fields, if any. Only bitfields are allowed,
2576 since they are not addressable. */
2577 for (field
= TREE_CHAIN (field
);
2579 field
= TREE_CHAIN (field
))
2581 if (TREE_CODE (field
) != FIELD_DECL
)
2584 if (!DECL_BIT_FIELD_TYPE (field
))
2591 if (TREE_CODE (type
) == UNION_TYPE
)
2595 /* Unions can be returned in registers if every element is
2596 integral, or can be returned in an integer register. */
2597 for (field
= TYPE_FIELDS (type
);
2599 field
= TREE_CHAIN (field
))
2601 if (TREE_CODE (field
) != FIELD_DECL
)
2604 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2607 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2613 #endif /* not ARM_WINCE */
2615 /* Return all other types in memory. */
2619 /* Indicate whether or not words of a double are in big-endian order. */
2622 arm_float_words_big_endian (void)
2624 if (TARGET_MAVERICK
)
2627 /* For FPA, float words are always big-endian. For VFP, floats words
2628 follow the memory system mode. */
2636 return (TARGET_BIG_END
? 1 : 0);
2641 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2642 for a call to a function whose data type is FNTYPE.
2643 For a library call, FNTYPE is NULL. */
2645 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2646 rtx libname ATTRIBUTE_UNUSED
,
2647 tree fndecl ATTRIBUTE_UNUSED
)
2649 /* On the ARM, the offset starts at 0. */
2650 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2651 pcum
->iwmmxt_nregs
= 0;
2652 pcum
->can_split
= true;
2654 pcum
->call_cookie
= CALL_NORMAL
;
2656 if (TARGET_LONG_CALLS
)
2657 pcum
->call_cookie
= CALL_LONG
;
2659 /* Check for long call/short call attributes. The attributes
2660 override any command line option. */
2663 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2664 pcum
->call_cookie
= CALL_SHORT
;
2665 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2666 pcum
->call_cookie
= CALL_LONG
;
2669 /* Varargs vectors are treated the same as long long.
2670 named_count avoids having to change the way arm handles 'named' */
2671 pcum
->named_count
= 0;
2674 if (TARGET_REALLY_IWMMXT
&& fntype
)
2678 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2680 fn_arg
= TREE_CHAIN (fn_arg
))
2681 pcum
->named_count
+= 1;
2683 if (! pcum
->named_count
)
2684 pcum
->named_count
= INT_MAX
;
2689 /* Return true if mode/type need doubleword alignment. */
2691 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2693 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2694 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2698 /* Determine where to put an argument to a function.
2699 Value is zero to push the argument on the stack,
2700 or a hard register in which to store the argument.
2702 MODE is the argument's machine mode.
2703 TYPE is the data type of the argument (as a tree).
2704 This is null for libcalls where that information may
2706 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2707 the preceding args and about the function being called.
2708 NAMED is nonzero if this argument is a named parameter
2709 (otherwise it is an extra parameter matching an ellipsis). */
2712 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2713 tree type
, int named
)
2717 /* Varargs vectors are treated the same as long long.
2718 named_count avoids having to change the way arm handles 'named' */
2719 if (TARGET_IWMMXT_ABI
2720 && arm_vector_mode_supported_p (mode
)
2721 && pcum
->named_count
> pcum
->nargs
+ 1)
2723 if (pcum
->iwmmxt_nregs
<= 9)
2724 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2727 pcum
->can_split
= false;
2732 /* Put doubleword aligned quantities in even register pairs. */
2734 && ARM_DOUBLEWORD_ALIGN
2735 && arm_needs_doubleword_align (mode
, type
))
2738 if (mode
== VOIDmode
)
2739 /* Compute operand 2 of the call insn. */
2740 return GEN_INT (pcum
->call_cookie
);
2742 /* Only allow splitting an arg between regs and memory if all preceding
2743 args were allocated to regs. For args passed by reference we only count
2744 the reference pointer. */
2745 if (pcum
->can_split
)
2748 nregs
= ARM_NUM_REGS2 (mode
, type
);
2750 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2753 return gen_rtx_REG (mode
, pcum
->nregs
);
2757 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2758 tree type
, bool named ATTRIBUTE_UNUSED
)
2760 int nregs
= pcum
->nregs
;
2762 if (arm_vector_mode_supported_p (mode
))
2765 if (NUM_ARG_REGS
> nregs
2766 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2768 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2773 /* Variable sized types are passed by reference. This is a GCC
2774 extension to the ARM ABI. */
2777 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2778 enum machine_mode mode ATTRIBUTE_UNUSED
,
2779 tree type
, bool named ATTRIBUTE_UNUSED
)
2781 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2784 /* Encode the current state of the #pragma [no_]long_calls. */
2787 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2788 LONG
, /* #pragma long_calls is in effect. */
2789 SHORT
/* #pragma no_long_calls is in effect. */
2792 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2795 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2797 arm_pragma_long_calls
= LONG
;
2801 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2803 arm_pragma_long_calls
= SHORT
;
2807 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2809 arm_pragma_long_calls
= OFF
;
2812 /* Table of machine attributes. */
2813 const struct attribute_spec arm_attribute_table
[] =
2815 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2816 /* Function calls made to this symbol must be done indirectly, because
2817 it may lie outside of the 26 bit addressing range of a normal function
2819 { "long_call", 0, 0, false, true, true, NULL
},
2820 /* Whereas these functions are always known to reside within the 26 bit
2821 addressing range. */
2822 { "short_call", 0, 0, false, true, true, NULL
},
2823 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2824 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2825 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2826 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2828 /* ARM/PE has three new attributes:
2830 dllexport - for exporting a function/variable that will live in a dll
2831 dllimport - for importing a function/variable from a dll
2833 Microsoft allows multiple declspecs in one __declspec, separating
2834 them with spaces. We do NOT support this. Instead, use __declspec
2837 { "dllimport", 0, 0, true, false, false, NULL
},
2838 { "dllexport", 0, 0, true, false, false, NULL
},
2839 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2840 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2841 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2842 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2843 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2845 { NULL
, 0, 0, false, false, false, NULL
}
2848 /* Handle an attribute requiring a FUNCTION_DECL;
2849 arguments as in struct attribute_spec.handler. */
2851 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2852 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2854 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2856 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2857 IDENTIFIER_POINTER (name
));
2858 *no_add_attrs
= true;
2864 /* Handle an "interrupt" or "isr" attribute;
2865 arguments as in struct attribute_spec.handler. */
2867 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2872 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2874 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2875 IDENTIFIER_POINTER (name
));
2876 *no_add_attrs
= true;
2878 /* FIXME: the argument if any is checked for type attributes;
2879 should it be checked for decl ones? */
2883 if (TREE_CODE (*node
) == FUNCTION_TYPE
2884 || TREE_CODE (*node
) == METHOD_TYPE
)
2886 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2888 warning (OPT_Wattributes
, "%qs attribute ignored",
2889 IDENTIFIER_POINTER (name
));
2890 *no_add_attrs
= true;
2893 else if (TREE_CODE (*node
) == POINTER_TYPE
2894 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2895 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2896 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2898 *node
= build_variant_type_copy (*node
);
2899 TREE_TYPE (*node
) = build_type_attribute_variant
2901 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2902 *no_add_attrs
= true;
2906 /* Possibly pass this attribute on from the type to a decl. */
2907 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2908 | (int) ATTR_FLAG_FUNCTION_NEXT
2909 | (int) ATTR_FLAG_ARRAY_NEXT
))
2911 *no_add_attrs
= true;
2912 return tree_cons (name
, args
, NULL_TREE
);
2916 warning (OPT_Wattributes
, "%qs attribute ignored",
2917 IDENTIFIER_POINTER (name
));
2925 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2926 /* Handle the "notshared" attribute. This attribute is another way of
2927 requesting hidden visibility. ARM's compiler supports
2928 "__declspec(notshared)"; we support the same thing via an
2932 arm_handle_notshared_attribute (tree
*node
,
2933 tree name ATTRIBUTE_UNUSED
,
2934 tree args ATTRIBUTE_UNUSED
,
2935 int flags ATTRIBUTE_UNUSED
,
2938 tree decl
= TYPE_NAME (*node
);
2942 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2943 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2944 *no_add_attrs
= false;
2950 /* Return 0 if the attributes for two types are incompatible, 1 if they
2951 are compatible, and 2 if they are nearly compatible (which causes a
2952 warning to be generated). */
2954 arm_comp_type_attributes (tree type1
, tree type2
)
2958 /* Check for mismatch of non-default calling convention. */
2959 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2962 /* Check for mismatched call attributes. */
2963 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2964 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2965 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2966 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2968 /* Only bother to check if an attribute is defined. */
2969 if (l1
| l2
| s1
| s2
)
2971 /* If one type has an attribute, the other must have the same attribute. */
2972 if ((l1
!= l2
) || (s1
!= s2
))
2975 /* Disallow mixed attributes. */
2976 if ((l1
& s2
) || (l2
& s1
))
2980 /* Check for mismatched ISR attribute. */
2981 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2983 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2984 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2986 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2993 /* Encode long_call or short_call attribute by prefixing
2994 symbol name in DECL with a special character FLAG. */
2996 arm_encode_call_attribute (tree decl
, int flag
)
2998 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2999 int len
= strlen (str
);
3002 /* Do not allow weak functions to be treated as short call. */
3003 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3006 newstr
= alloca (len
+ 2);
3008 strcpy (newstr
+ 1, str
);
3010 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3011 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3014 /* Assigns default attributes to newly defined type. This is used to
3015 set short_call/long_call attributes for function types of
3016 functions defined inside corresponding #pragma scopes. */
3018 arm_set_default_type_attributes (tree type
)
3020 /* Add __attribute__ ((long_call)) to all functions, when
3021 inside #pragma long_calls or __attribute__ ((short_call)),
3022 when inside #pragma no_long_calls. */
3023 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3025 tree type_attr_list
, attr_name
;
3026 type_attr_list
= TYPE_ATTRIBUTES (type
);
3028 if (arm_pragma_long_calls
== LONG
)
3029 attr_name
= get_identifier ("long_call");
3030 else if (arm_pragma_long_calls
== SHORT
)
3031 attr_name
= get_identifier ("short_call");
3035 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3036 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3040 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3041 defined within the current compilation unit. If this cannot be
3042 determined, then 0 is returned. */
3044 current_file_function_operand (rtx sym_ref
)
3046 /* This is a bit of a fib. A function will have a short call flag
3047 applied to its name if it has the short call attribute, or it has
3048 already been defined within the current compilation unit. */
3049 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3052 /* The current function is always defined within the current compilation
3053 unit. If it s a weak definition however, then this may not be the real
3054 definition of the function, and so we have to say no. */
3055 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3056 && !DECL_WEAK (current_function_decl
))
3059 /* We cannot make the determination - default to returning 0. */
3063 /* Return nonzero if a 32 bit "long_call" should be generated for
3064 this call. We generate a long_call if the function:
3066 a. has an __attribute__((long call))
3067 or b. is within the scope of a #pragma long_calls
3068 or c. the -mlong-calls command line switch has been specified
3070 1. -ffunction-sections is in effect
3071 or 2. the current function has __attribute__ ((section))
3072 or 3. the target function has __attribute__ ((section))
3074 However we do not generate a long call if the function:
3076 d. has an __attribute__ ((short_call))
3077 or e. is inside the scope of a #pragma no_long_calls
3078 or f. is defined within the current compilation unit.
3080 This function will be called by C fragments contained in the machine
3081 description file. SYM_REF and CALL_COOKIE correspond to the matched
3082 rtl operands. CALL_SYMBOL is used to distinguish between
3083 two different callers of the function. It is set to 1 in the
3084 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3085 and "call_value" patterns. This is because of the difference in the
3086 SYM_REFs passed by these patterns. */
3088 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3092 if (GET_CODE (sym_ref
) != MEM
)
3095 sym_ref
= XEXP (sym_ref
, 0);
3098 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3101 if (call_cookie
& CALL_SHORT
)
3104 if (TARGET_LONG_CALLS
)
3106 if (flag_function_sections
3107 || DECL_SECTION_NAME (current_function_decl
))
3108 /* c.3 is handled by the definition of the
3109 ARM_DECLARE_FUNCTION_SIZE macro. */
3113 if (current_file_function_operand (sym_ref
))
3116 return (call_cookie
& CALL_LONG
)
3117 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3118 || TARGET_LONG_CALLS
;
3121 /* Return nonzero if it is ok to make a tail-call to DECL. */
3123 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3125 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3127 if (cfun
->machine
->sibcall_blocked
)
3130 /* Never tailcall something for which we have no decl, or if we
3131 are in Thumb mode. */
3132 if (decl
== NULL
|| TARGET_THUMB
)
3135 /* Get the calling method. */
3136 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3137 call_type
= CALL_SHORT
;
3138 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3139 call_type
= CALL_LONG
;
3141 /* Cannot tail-call to long calls, since these are out of range of
3142 a branch instruction. However, if not compiling PIC, we know
3143 we can reach the symbol if it is in this compilation unit. */
3144 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3147 /* If we are interworking and the function is not declared static
3148 then we can't tail-call it unless we know that it exists in this
3149 compilation unit (since it might be a Thumb routine). */
3150 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3153 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3154 if (IS_INTERRUPT (arm_current_func_type ()))
3157 /* Everything else is ok. */
3162 /* Addressing mode support functions. */
3164 /* Return nonzero if X is a legitimate immediate operand when compiling
3167 legitimate_pic_operand_p (rtx x
)
3171 && (GET_CODE (x
) == SYMBOL_REF
3172 || (GET_CODE (x
) == CONST
3173 && GET_CODE (XEXP (x
, 0)) == PLUS
3174 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
3181 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3183 if (GET_CODE (orig
) == SYMBOL_REF
3184 || GET_CODE (orig
) == LABEL_REF
)
3186 #ifndef AOF_ASSEMBLER
3187 rtx pic_ref
, address
;
3194 gcc_assert (!no_new_pseudos
);
3195 reg
= gen_reg_rtx (Pmode
);
3200 #ifdef AOF_ASSEMBLER
3201 /* The AOF assembler can generate relocations for these directly, and
3202 understands that the PIC register has to be added into the offset. */
3203 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3206 address
= gen_reg_rtx (Pmode
);
3211 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3213 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3215 if ((GET_CODE (orig
) == LABEL_REF
3216 || (GET_CODE (orig
) == SYMBOL_REF
&&
3217 SYMBOL_REF_LOCAL_P (orig
)))
3219 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
3222 pic_ref
= gen_const_mem (Pmode
,
3223 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3227 insn
= emit_move_insn (reg
, pic_ref
);
3229 current_function_uses_pic_offset_table
= 1;
3230 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3232 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3236 else if (GET_CODE (orig
) == CONST
)
3240 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3241 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3244 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3245 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3250 gcc_assert (!no_new_pseudos
);
3251 reg
= gen_reg_rtx (Pmode
);
3254 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3256 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3257 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3258 base
== reg
? 0 : reg
);
3260 if (GET_CODE (offset
) == CONST_INT
)
3262 /* The base register doesn't really matter, we only want to
3263 test the index for the appropriate mode. */
3264 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3266 gcc_assert (!no_new_pseudos
);
3267 offset
= force_reg (Pmode
, offset
);
3270 if (GET_CODE (offset
) == CONST_INT
)
3271 return plus_constant (base
, INTVAL (offset
));
3274 if (GET_MODE_SIZE (mode
) > 4
3275 && (GET_MODE_CLASS (mode
) == MODE_INT
3276 || TARGET_SOFT_FLOAT
))
3278 emit_insn (gen_addsi3 (reg
, base
, offset
));
3282 return gen_rtx_PLUS (Pmode
, base
, offset
);
3289 /* Find a spare low register to use during the prolog of a function. */
3292 thumb_find_work_register (unsigned long pushed_regs_mask
)
3296 /* Check the argument registers first as these are call-used. The
3297 register allocation order means that sometimes r3 might be used
3298 but earlier argument registers might not, so check them all. */
3299 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3300 if (!regs_ever_live
[reg
])
3303 /* Before going on to check the call-saved registers we can try a couple
3304 more ways of deducing that r3 is available. The first is when we are
3305 pushing anonymous arguments onto the stack and we have less than 4
3306 registers worth of fixed arguments(*). In this case r3 will be part of
3307 the variable argument list and so we can be sure that it will be
3308 pushed right at the start of the function. Hence it will be available
3309 for the rest of the prologue.
3310 (*): ie current_function_pretend_args_size is greater than 0. */
3311 if (cfun
->machine
->uses_anonymous_args
3312 && current_function_pretend_args_size
> 0)
3313 return LAST_ARG_REGNUM
;
3315 /* The other case is when we have fixed arguments but less than 4 registers
3316 worth. In this case r3 might be used in the body of the function, but
3317 it is not being used to convey an argument into the function. In theory
3318 we could just check current_function_args_size to see how many bytes are
3319 being passed in argument registers, but it seems that it is unreliable.
3320 Sometimes it will have the value 0 when in fact arguments are being
3321 passed. (See testcase execute/20021111-1.c for an example). So we also
3322 check the args_info.nregs field as well. The problem with this field is
3323 that it makes no allowances for arguments that are passed to the
3324 function but which are not used. Hence we could miss an opportunity
3325 when a function has an unused argument in r3. But it is better to be
3326 safe than to be sorry. */
3327 if (! cfun
->machine
->uses_anonymous_args
3328 && current_function_args_size
>= 0
3329 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3330 && cfun
->args_info
.nregs
< 4)
3331 return LAST_ARG_REGNUM
;
3333 /* Otherwise look for a call-saved register that is going to be pushed. */
3334 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3335 if (pushed_regs_mask
& (1 << reg
))
3338 /* Something went wrong - thumb_compute_save_reg_mask()
3339 should have arranged for a suitable register to be pushed. */
3343 static GTY(()) int pic_labelno
;
3345 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3349 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3351 #ifndef AOF_ASSEMBLER
3352 rtx l1
, labelno
, pic_tmp
, pic_tmp2
, pic_rtx
;
3353 rtx global_offset_table
;
3355 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3358 gcc_assert (flag_pic
);
3360 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3361 in the code stream. */
3363 labelno
= GEN_INT (pic_labelno
++);
3364 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3365 l1
= gen_rtx_CONST (VOIDmode
, l1
);
3367 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3368 /* On the ARM the PC register contains 'dot + 8' at the time of the
3369 addition, on the Thumb it is 'dot + 4'. */
3370 pic_tmp
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
3372 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3373 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3375 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3377 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3381 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3382 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
,
3383 pic_offset_table_rtx
, labelno
));
3387 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3389 /* We will have pushed the pic register, so we should always be
3390 able to find a work register. */
3391 pic_tmp
= gen_rtx_REG (SImode
,
3392 thumb_find_work_register (saved_regs
));
3393 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3394 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3397 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3398 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
,
3399 pic_offset_table_rtx
, labelno
));
3402 /* Need to emit this whether or not we obey regdecls,
3403 since setjmp/longjmp can cause life info to screw up. */
3404 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3405 #endif /* AOF_ASSEMBLER */
3409 /* Return nonzero if X is valid as an ARM state addressing register. */
3411 arm_address_register_rtx_p (rtx x
, int strict_p
)
3415 if (GET_CODE (x
) != REG
)
3421 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3423 return (regno
<= LAST_ARM_REGNUM
3424 || regno
>= FIRST_PSEUDO_REGISTER
3425 || regno
== FRAME_POINTER_REGNUM
3426 || regno
== ARG_POINTER_REGNUM
);
3429 /* Return TRUE if this rtx is the difference of a symbol and a label,
3430 and will reduce to a PC-relative relocation in the object file.
3431 Expressions like this can be left alone when generating PIC, rather
3432 than forced through the GOT. */
3434 pcrel_constant_p (rtx x
)
3436 if (GET_CODE (x
) == MINUS
)
3437 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3442 /* Return nonzero if X is a valid ARM state address operand. */
3444 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3448 enum rtx_code code
= GET_CODE (x
);
3450 if (arm_address_register_rtx_p (x
, strict_p
))
3453 use_ldrd
= (TARGET_LDRD
3455 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3457 if (code
== POST_INC
|| code
== PRE_DEC
3458 || ((code
== PRE_INC
|| code
== POST_DEC
)
3459 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3460 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3462 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3463 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3464 && GET_CODE (XEXP (x
, 1)) == PLUS
3465 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3467 rtx addend
= XEXP (XEXP (x
, 1), 1);
3469 /* Don't allow ldrd post increment by register because it's hard
3470 to fixup invalid register choices. */
3472 && GET_CODE (x
) == POST_MODIFY
3473 && GET_CODE (addend
) == REG
)
3476 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3477 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3480 /* After reload constants split into minipools will have addresses
3481 from a LABEL_REF. */
3482 else if (reload_completed
3483 && (code
== LABEL_REF
3485 && GET_CODE (XEXP (x
, 0)) == PLUS
3486 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3487 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3490 else if (mode
== TImode
)
3493 else if (code
== PLUS
)
3495 rtx xop0
= XEXP (x
, 0);
3496 rtx xop1
= XEXP (x
, 1);
3498 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3499 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3500 || (arm_address_register_rtx_p (xop1
, strict_p
)
3501 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3505 /* Reload currently can't handle MINUS, so disable this for now */
3506 else if (GET_CODE (x
) == MINUS
)
3508 rtx xop0
= XEXP (x
, 0);
3509 rtx xop1
= XEXP (x
, 1);
3511 return (arm_address_register_rtx_p (xop0
, strict_p
)
3512 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3516 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3517 && code
== SYMBOL_REF
3518 && CONSTANT_POOL_ADDRESS_P (x
)
3520 && symbol_mentioned_p (get_pool_constant (x
))
3521 && ! pcrel_constant_p (get_pool_constant (x
))))
3527 /* Return nonzero if INDEX is valid for an address index operand in
3530 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3533 HOST_WIDE_INT range
;
3534 enum rtx_code code
= GET_CODE (index
);
3536 /* Standard coprocessor addressing modes. */
3537 if (TARGET_HARD_FLOAT
3538 && (TARGET_FPA
|| TARGET_MAVERICK
)
3539 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3540 || (TARGET_MAVERICK
&& mode
== DImode
)))
3541 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3542 && INTVAL (index
) > -1024
3543 && (INTVAL (index
) & 3) == 0);
3545 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3546 return (code
== CONST_INT
3547 && INTVAL (index
) < 1024
3548 && INTVAL (index
) > -1024
3549 && (INTVAL (index
) & 3) == 0);
3551 if (arm_address_register_rtx_p (index
, strict_p
)
3552 && (GET_MODE_SIZE (mode
) <= 4))
3555 if (mode
== DImode
|| mode
== DFmode
)
3557 if (code
== CONST_INT
)
3559 HOST_WIDE_INT val
= INTVAL (index
);
3562 return val
> -256 && val
< 256;
3564 return val
> -4096 && val
< 4092;
3567 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3570 if (GET_MODE_SIZE (mode
) <= 4
3573 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3577 rtx xiop0
= XEXP (index
, 0);
3578 rtx xiop1
= XEXP (index
, 1);
3580 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3581 && power_of_two_operand (xiop1
, SImode
))
3582 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3583 && power_of_two_operand (xiop0
, SImode
)));
3585 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3586 || code
== ASHIFT
|| code
== ROTATERT
)
3588 rtx op
= XEXP (index
, 1);
3590 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3591 && GET_CODE (op
) == CONST_INT
3593 && INTVAL (op
) <= 31);
3597 /* For ARM v4 we may be doing a sign-extend operation during the
3601 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3607 range
= (mode
== HImode
) ? 4095 : 4096;
3609 return (code
== CONST_INT
3610 && INTVAL (index
) < range
3611 && INTVAL (index
) > -range
);
3614 /* Return nonzero if X is valid as a Thumb state base register. */
3616 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3620 if (GET_CODE (x
) != REG
)
3626 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3628 return (regno
<= LAST_LO_REGNUM
3629 || regno
> LAST_VIRTUAL_REGISTER
3630 || regno
== FRAME_POINTER_REGNUM
3631 || (GET_MODE_SIZE (mode
) >= 4
3632 && (regno
== STACK_POINTER_REGNUM
3633 || regno
>= FIRST_PSEUDO_REGISTER
3634 || x
== hard_frame_pointer_rtx
3635 || x
== arg_pointer_rtx
)));
3638 /* Return nonzero if x is a legitimate index register. This is the case
3639 for any base register that can access a QImode object. */
3641 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3643 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3646 /* Return nonzero if x is a legitimate Thumb-state address.
3648 The AP may be eliminated to either the SP or the FP, so we use the
3649 least common denominator, e.g. SImode, and offsets from 0 to 64.
3651 ??? Verify whether the above is the right approach.
3653 ??? Also, the FP may be eliminated to the SP, so perhaps that
3654 needs special handling also.
3656 ??? Look at how the mips16 port solves this problem. It probably uses
3657 better ways to solve some of these problems.
3659 Although it is not incorrect, we don't accept QImode and HImode
3660 addresses based on the frame pointer or arg pointer until the
3661 reload pass starts. This is so that eliminating such addresses
3662 into stack based ones won't produce impossible code. */
3664 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3666 /* ??? Not clear if this is right. Experiment. */
3667 if (GET_MODE_SIZE (mode
) < 4
3668 && !(reload_in_progress
|| reload_completed
)
3669 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3670 || reg_mentioned_p (arg_pointer_rtx
, x
)
3671 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3672 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3673 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3674 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3677 /* Accept any base register. SP only in SImode or larger. */
3678 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3681 /* This is PC relative data before arm_reorg runs. */
3682 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3683 && GET_CODE (x
) == SYMBOL_REF
3684 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3687 /* This is PC relative data after arm_reorg runs. */
3688 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3689 && (GET_CODE (x
) == LABEL_REF
3690 || (GET_CODE (x
) == CONST
3691 && GET_CODE (XEXP (x
, 0)) == PLUS
3692 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3693 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3696 /* Post-inc indexing only supported for SImode and larger. */
3697 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3698 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3701 else if (GET_CODE (x
) == PLUS
)
3703 /* REG+REG address can be any two index registers. */
3704 /* We disallow FRAME+REG addressing since we know that FRAME
3705 will be replaced with STACK, and SP relative addressing only
3706 permits SP+OFFSET. */
3707 if (GET_MODE_SIZE (mode
) <= 4
3708 && XEXP (x
, 0) != frame_pointer_rtx
3709 && XEXP (x
, 1) != frame_pointer_rtx
3710 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3711 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3714 /* REG+const has 5-7 bit offset for non-SP registers. */
3715 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3716 || XEXP (x
, 0) == arg_pointer_rtx
)
3717 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3718 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3721 /* REG+const has 10 bit offset for SP, but only SImode and
3722 larger is supported. */
3723 /* ??? Should probably check for DI/DFmode overflow here
3724 just like GO_IF_LEGITIMATE_OFFSET does. */
3725 else if (GET_CODE (XEXP (x
, 0)) == REG
3726 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3727 && GET_MODE_SIZE (mode
) >= 4
3728 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3729 && INTVAL (XEXP (x
, 1)) >= 0
3730 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3731 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3734 else if (GET_CODE (XEXP (x
, 0)) == REG
3735 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3736 && GET_MODE_SIZE (mode
) >= 4
3737 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3738 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3742 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3743 && GET_MODE_SIZE (mode
) == 4
3744 && GET_CODE (x
) == SYMBOL_REF
3745 && CONSTANT_POOL_ADDRESS_P (x
)
3747 && symbol_mentioned_p (get_pool_constant (x
))
3748 && ! pcrel_constant_p (get_pool_constant (x
))))
3754 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3755 instruction of mode MODE. */
3757 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3759 switch (GET_MODE_SIZE (mode
))
3762 return val
>= 0 && val
< 32;
3765 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3769 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3774 /* Build the SYMBOL_REF for __tls_get_addr. */
3776 static GTY(()) rtx tls_get_addr_libfunc
;
3779 get_tls_get_addr (void)
3781 if (!tls_get_addr_libfunc
)
3782 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
3783 return tls_get_addr_libfunc
;
3787 arm_load_tp (rtx target
)
3790 target
= gen_reg_rtx (SImode
);
3794 /* Can return in any reg. */
3795 emit_insn (gen_load_tp_hard (target
));
3799 /* Always returned in r0. Immediately copy the result into a pseudo,
3800 otherwise other uses of r0 (e.g. setting up function arguments) may
3801 clobber the value. */
3805 emit_insn (gen_load_tp_soft ());
3807 tmp
= gen_rtx_REG (SImode
, 0);
3808 emit_move_insn (target
, tmp
);
3814 load_tls_operand (rtx x
, rtx reg
)
3818 if (reg
== NULL_RTX
)
3819 reg
= gen_reg_rtx (SImode
);
3821 tmp
= gen_rtx_CONST (SImode
, x
);
3823 emit_move_insn (reg
, tmp
);
3829 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
3831 rtx insns
, label
, labelno
, sum
;
3835 labelno
= GEN_INT (pic_labelno
++);
3836 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3837 label
= gen_rtx_CONST (VOIDmode
, label
);
3839 sum
= gen_rtx_UNSPEC (Pmode
,
3840 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
3841 GEN_INT (TARGET_ARM
? 8 : 4)),
3843 reg
= load_tls_operand (sum
, reg
);
3846 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
3848 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3850 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
3851 Pmode
, 1, reg
, Pmode
);
3853 insns
= get_insns ();
3860 legitimize_tls_address (rtx x
, rtx reg
)
3862 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
3863 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
3867 case TLS_MODEL_GLOBAL_DYNAMIC
:
3868 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
3869 dest
= gen_reg_rtx (Pmode
);
3870 emit_libcall_block (insns
, dest
, ret
, x
);
3873 case TLS_MODEL_LOCAL_DYNAMIC
:
3874 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
3876 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3877 share the LDM result with other LD model accesses. */
3878 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
3880 dest
= gen_reg_rtx (Pmode
);
3881 emit_libcall_block (insns
, dest
, ret
, eqv
);
3883 /* Load the addend. */
3884 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
3886 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
3887 return gen_rtx_PLUS (Pmode
, dest
, addend
);
3889 case TLS_MODEL_INITIAL_EXEC
:
3890 labelno
= GEN_INT (pic_labelno
++);
3891 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3892 label
= gen_rtx_CONST (VOIDmode
, label
);
3893 sum
= gen_rtx_UNSPEC (Pmode
,
3894 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
3895 GEN_INT (TARGET_ARM
? 8 : 4)),
3897 reg
= load_tls_operand (sum
, reg
);
3900 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
3903 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3904 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
3907 tp
= arm_load_tp (NULL_RTX
);
3909 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3911 case TLS_MODEL_LOCAL_EXEC
:
3912 tp
= arm_load_tp (NULL_RTX
);
3914 reg
= gen_rtx_UNSPEC (Pmode
,
3915 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
3917 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
3919 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3926 /* Try machine-dependent ways of modifying an illegitimate address
3927 to be legitimate. If we find one, return the new, valid address. */
3929 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3931 if (arm_tls_symbol_p (x
))
3932 return legitimize_tls_address (x
, NULL_RTX
);
3934 if (GET_CODE (x
) == PLUS
)
3936 rtx xop0
= XEXP (x
, 0);
3937 rtx xop1
= XEXP (x
, 1);
3939 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3940 xop0
= force_reg (SImode
, xop0
);
3942 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3943 xop1
= force_reg (SImode
, xop1
);
3945 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3946 && GET_CODE (xop1
) == CONST_INT
)
3948 HOST_WIDE_INT n
, low_n
;
3952 /* VFP addressing modes actually allow greater offsets, but for
3953 now we just stick with the lowest common denominator. */
3955 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3967 low_n
= ((mode
) == TImode
? 0
3968 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3972 base_reg
= gen_reg_rtx (SImode
);
3973 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3974 GEN_INT (n
)), NULL_RTX
);
3975 emit_move_insn (base_reg
, val
);
3976 x
= (low_n
== 0 ? base_reg
3977 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3979 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3980 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3983 /* XXX We don't allow MINUS any more -- see comment in
3984 arm_legitimate_address_p (). */
3985 else if (GET_CODE (x
) == MINUS
)
3987 rtx xop0
= XEXP (x
, 0);
3988 rtx xop1
= XEXP (x
, 1);
3990 if (CONSTANT_P (xop0
))
3991 xop0
= force_reg (SImode
, xop0
);
3993 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3994 xop1
= force_reg (SImode
, xop1
);
3996 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3997 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
4000 /* Make sure to take full advantage of the pre-indexed addressing mode
4001 with absolute addresses which often allows for the base register to
4002 be factorized for multiple adjacent memory references, and it might
4003 even allows for the mini pool to be avoided entirely. */
4004 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
4007 HOST_WIDE_INT mask
, base
, index
;
4010 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4011 use a 8 bit index. So let's use a 12 bit index for SImode only and
4012 hope that arm_gen_constant will enable ldrb to use more bits. */
4013 bits
= (mode
== SImode
) ? 12 : 8;
4014 mask
= (1 << bits
) - 1;
4015 base
= INTVAL (x
) & ~mask
;
4016 index
= INTVAL (x
) & mask
;
4017 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4019 /* It'll most probably be more efficient to generate the base
4020 with more bits set and use a negative index instead. */
4024 base_reg
= force_reg (SImode
, GEN_INT (base
));
4025 x
= gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (index
));
4030 /* We need to find and carefully transform any SYMBOL and LABEL
4031 references; so go back to the original address expression. */
4032 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4034 if (new_x
!= orig_x
)
4042 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4043 to be legitimate. If we find one, return the new, valid address. */
4045 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4047 if (arm_tls_symbol_p (x
))
4048 return legitimize_tls_address (x
, NULL_RTX
);
4050 if (GET_CODE (x
) == PLUS
4051 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4052 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4053 || INTVAL (XEXP (x
, 1)) < 0))
4055 rtx xop0
= XEXP (x
, 0);
4056 rtx xop1
= XEXP (x
, 1);
4057 HOST_WIDE_INT offset
= INTVAL (xop1
);
4059 /* Try and fold the offset into a biasing of the base register and
4060 then offsetting that. Don't do this when optimizing for space
4061 since it can cause too many CSEs. */
4062 if (optimize_size
&& offset
>= 0
4063 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4065 HOST_WIDE_INT delta
;
4068 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4069 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4070 delta
= 31 * GET_MODE_SIZE (mode
);
4072 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4074 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4076 x
= plus_constant (xop0
, delta
);
4078 else if (offset
< 0 && offset
> -256)
4079 /* Small negative offsets are best done with a subtract before the
4080 dereference, forcing these into a register normally takes two
4082 x
= force_operand (x
, NULL_RTX
);
4085 /* For the remaining cases, force the constant into a register. */
4086 xop1
= force_reg (SImode
, xop1
);
4087 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4090 else if (GET_CODE (x
) == PLUS
4091 && s_register_operand (XEXP (x
, 1), SImode
)
4092 && !s_register_operand (XEXP (x
, 0), SImode
))
4094 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4096 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4101 /* We need to find and carefully transform any SYMBOL and LABEL
4102 references; so go back to the original address expression. */
4103 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4105 if (new_x
!= orig_x
)
4113 thumb_legitimize_reload_address (rtx
*x_p
,
4114 enum machine_mode mode
,
4115 int opnum
, int type
,
4116 int ind_levels ATTRIBUTE_UNUSED
)
4120 if (GET_CODE (x
) == PLUS
4121 && GET_MODE_SIZE (mode
) < 4
4122 && REG_P (XEXP (x
, 0))
4123 && XEXP (x
, 0) == stack_pointer_rtx
4124 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4125 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4130 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4131 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4135 /* If both registers are hi-regs, then it's better to reload the
4136 entire expression rather than each register individually. That
4137 only requires one reload register rather than two. */
4138 if (GET_CODE (x
) == PLUS
4139 && REG_P (XEXP (x
, 0))
4140 && REG_P (XEXP (x
, 1))
4141 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4142 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4147 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4148 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4155 /* Test for various thread-local symbols. */
4157 /* Return TRUE if X is a thread-local symbol. */
4160 arm_tls_symbol_p (rtx x
)
4162 if (! TARGET_HAVE_TLS
)
4165 if (GET_CODE (x
) != SYMBOL_REF
)
4168 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4171 /* Helper for arm_tls_referenced_p. */
4174 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4176 if (GET_CODE (*x
) == SYMBOL_REF
)
4177 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4179 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4180 TLS offsets, not real symbol references. */
4181 if (GET_CODE (*x
) == UNSPEC
4182 && XINT (*x
, 1) == UNSPEC_TLS
)
4188 /* Return TRUE if X contains any TLS symbol references. */
4191 arm_tls_referenced_p (rtx x
)
4193 if (! TARGET_HAVE_TLS
)
4196 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4199 #define REG_OR_SUBREG_REG(X) \
4200 (GET_CODE (X) == REG \
4201 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4203 #define REG_OR_SUBREG_RTX(X) \
4204 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4206 #ifndef COSTS_N_INSNS
4207 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4210 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4212 enum machine_mode mode
= GET_MODE (x
);
4225 return COSTS_N_INSNS (1);
4228 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4231 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4238 return COSTS_N_INSNS (2) + cycles
;
4240 return COSTS_N_INSNS (1) + 16;
4243 return (COSTS_N_INSNS (1)
4244 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4245 + GET_CODE (SET_DEST (x
)) == MEM
));
4250 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4252 if (thumb_shiftable_const (INTVAL (x
)))
4253 return COSTS_N_INSNS (2);
4254 return COSTS_N_INSNS (3);
4256 else if ((outer
== PLUS
|| outer
== COMPARE
)
4257 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4259 else if (outer
== AND
4260 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4261 return COSTS_N_INSNS (1);
4262 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4263 || outer
== LSHIFTRT
)
4265 return COSTS_N_INSNS (2);
4271 return COSTS_N_INSNS (3);
4289 /* XXX another guess. */
4290 /* Memory costs quite a lot for the first word, but subsequent words
4291 load at the equivalent of a single insn each. */
4292 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4293 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4298 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4303 /* XXX still guessing. */
4304 switch (GET_MODE (XEXP (x
, 0)))
4307 return (1 + (mode
== DImode
? 4 : 0)
4308 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4311 return (4 + (mode
== DImode
? 4 : 0)
4312 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4315 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4327 /* Worker routine for arm_rtx_costs. */
4329 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4331 enum machine_mode mode
= GET_MODE (x
);
4332 enum rtx_code subcode
;
4338 /* Memory costs quite a lot for the first word, but subsequent words
4339 load at the equivalent of a single insn each. */
4340 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4341 + (GET_CODE (x
) == SYMBOL_REF
4342 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4348 return optimize_size
? COSTS_N_INSNS (2) : 100;
4351 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4358 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4360 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4361 + ((GET_CODE (XEXP (x
, 0)) == REG
4362 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4363 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4365 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4366 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4367 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4369 + ((GET_CODE (XEXP (x
, 1)) == REG
4370 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4371 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4372 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4377 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4378 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4379 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4380 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4383 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4384 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4385 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4386 && arm_const_double_rtx (XEXP (x
, 1))))
4388 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4389 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4390 && arm_const_double_rtx (XEXP (x
, 0))))
4393 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4394 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4395 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4396 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4397 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4398 || subcode
== ROTATE
|| subcode
== ROTATERT
4400 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4401 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4402 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4403 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4404 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4405 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4406 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4411 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4412 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4413 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4414 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4415 && arm_const_double_rtx (XEXP (x
, 1))))
4419 case AND
: case XOR
: case IOR
:
4422 /* Normally the frame registers will be spilt into reg+const during
4423 reload, so it is a bad idea to combine them with other instructions,
4424 since then they might not be moved outside of loops. As a compromise
4425 we allow integration with ops that have a constant as their second
4427 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4428 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4429 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4430 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4431 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4435 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4436 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4437 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4438 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4441 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4442 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4443 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4444 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4445 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4448 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4449 return (1 + extra_cost
4450 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4451 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4452 || subcode
== ROTATE
|| subcode
== ROTATERT
4454 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4455 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4456 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4457 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4458 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4459 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4465 /* This should have been handled by the CPU specific routines. */
4469 if (arm_arch3m
&& mode
== SImode
4470 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4471 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4472 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4473 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4474 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4475 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4480 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4481 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4485 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4487 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4490 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4498 return 4 + (mode
== DImode
? 4 : 0);
4501 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4502 return (4 + (mode
== DImode
? 4 : 0)
4503 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4506 switch (GET_MODE (XEXP (x
, 0)))
4509 return (1 + (mode
== DImode
? 4 : 0)
4510 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4513 return (4 + (mode
== DImode
? 4 : 0)
4514 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4517 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4532 if (const_ok_for_arm (INTVAL (x
)))
4533 return outer
== SET
? 2 : -1;
4534 else if (outer
== AND
4535 && const_ok_for_arm (~INTVAL (x
)))
4537 else if ((outer
== COMPARE
4538 || outer
== PLUS
|| outer
== MINUS
)
4539 && const_ok_for_arm (-INTVAL (x
)))
4550 if (arm_const_double_rtx (x
))
4551 return outer
== SET
? 2 : -1;
4552 else if ((outer
== COMPARE
|| outer
== PLUS
)
4553 && neg_const_double_rtx_ok_for_fpa (x
))
4562 /* RTX costs when optimizing for size. */
4564 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4566 enum machine_mode mode
= GET_MODE (x
);
4570 /* XXX TBD. For now, use the standard costs. */
4571 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4578 /* A memory access costs 1 insn if the mode is small, or the address is
4579 a single register, otherwise it costs one insn per word. */
4580 if (REG_P (XEXP (x
, 0)))
4581 *total
= COSTS_N_INSNS (1);
4583 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4590 /* Needs a libcall, so it costs about this. */
4591 *total
= COSTS_N_INSNS (2);
4595 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4597 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4605 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4607 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4610 else if (mode
== SImode
)
4612 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4613 /* Slightly disparage register shifts, but not by much. */
4614 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4615 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4619 /* Needs a libcall. */
4620 *total
= COSTS_N_INSNS (2);
4624 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4626 *total
= COSTS_N_INSNS (1);
4632 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4633 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4635 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4636 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4637 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4638 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4639 || subcode1
== ASHIFTRT
)
4641 /* It's just the cost of the two operands. */
4646 *total
= COSTS_N_INSNS (1);
4650 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4654 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4656 *total
= COSTS_N_INSNS (1);
4661 case AND
: case XOR
: case IOR
:
4664 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4666 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4667 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4668 || (code
== AND
&& subcode
== NOT
))
4670 /* It's just the cost of the two operands. */
4676 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4680 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4684 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4685 *total
= COSTS_N_INSNS (1);
4688 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4697 if (cc_register (XEXP (x
, 0), VOIDmode
))
4700 *total
= COSTS_N_INSNS (1);
4704 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4705 *total
= COSTS_N_INSNS (1);
4707 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4712 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4714 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4715 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4718 *total
+= COSTS_N_INSNS (1);
4723 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4725 switch (GET_MODE (XEXP (x
, 0)))
4728 *total
+= COSTS_N_INSNS (1);
4732 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4738 *total
+= COSTS_N_INSNS (2);
4743 *total
+= COSTS_N_INSNS (1);
4748 if (const_ok_for_arm (INTVAL (x
)))
4749 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4750 else if (const_ok_for_arm (~INTVAL (x
)))
4751 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4752 else if (const_ok_for_arm (-INTVAL (x
)))
4754 if (outer_code
== COMPARE
|| outer_code
== PLUS
4755 || outer_code
== MINUS
)
4758 *total
= COSTS_N_INSNS (1);
4761 *total
= COSTS_N_INSNS (2);
4767 *total
= COSTS_N_INSNS (2);
4771 *total
= COSTS_N_INSNS (4);
4775 if (mode
!= VOIDmode
)
4776 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4778 *total
= COSTS_N_INSNS (4); /* How knows? */
4783 /* RTX costs for cores with a slow MUL implementation. */
4786 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4788 enum machine_mode mode
= GET_MODE (x
);
4792 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4799 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4806 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4808 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4809 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4810 int cost
, const_ok
= const_ok_for_arm (i
);
4811 int j
, booth_unit_size
;
4813 /* Tune as appropriate. */
4814 cost
= const_ok
? 4 : 8;
4815 booth_unit_size
= 2;
4816 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4818 i
>>= booth_unit_size
;
4826 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4827 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4831 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4837 /* RTX cost for cores with a fast multiply unit (M variants). */
4840 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4842 enum machine_mode mode
= GET_MODE (x
);
4846 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4853 /* There is no point basing this on the tuning, since it is always the
4854 fast variant if it exists at all. */
4856 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4857 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4858 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4865 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4872 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4874 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4875 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4876 int cost
, const_ok
= const_ok_for_arm (i
);
4877 int j
, booth_unit_size
;
4879 /* Tune as appropriate. */
4880 cost
= const_ok
? 4 : 8;
4881 booth_unit_size
= 8;
4882 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4884 i
>>= booth_unit_size
;
4892 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4893 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4897 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4903 /* RTX cost for XScale CPUs. */
4906 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4908 enum machine_mode mode
= GET_MODE (x
);
4912 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4919 /* There is no point basing this on the tuning, since it is always the
4920 fast variant if it exists at all. */
4922 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4923 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4924 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4931 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4938 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4940 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4941 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4942 int cost
, const_ok
= const_ok_for_arm (i
);
4943 unsigned HOST_WIDE_INT masked_const
;
4945 /* The cost will be related to two insns.
4946 First a load of the constant (MOV or LDR), then a multiply. */
4949 cost
+= 1; /* LDR is probably more expensive because
4950 of longer result latency. */
4951 masked_const
= i
& 0xffff8000;
4952 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4954 masked_const
= i
& 0xf8000000;
4955 if (masked_const
== 0 || masked_const
== 0xf8000000)
4964 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4965 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4969 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4970 will stall until the multiplication is complete. */
4971 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4972 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
4974 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4978 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4984 /* RTX costs for 9e (and later) cores. */
4987 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4989 enum machine_mode mode
= GET_MODE (x
);
4998 *total
= COSTS_N_INSNS (3);
5002 *total
= thumb_rtx_costs (x
, code
, outer_code
);
5010 /* There is no point basing this on the tuning, since it is always the
5011 fast variant if it exists at all. */
5013 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5014 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5015 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5022 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5039 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5040 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5044 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5048 /* All address computations that can be done are free, but rtx cost returns
5049 the same for practically all of them. So we weight the different types
5050 of address here in the order (most pref first):
5051 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5053 arm_arm_address_cost (rtx x
)
5055 enum rtx_code c
= GET_CODE (x
);
5057 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5059 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5062 if (c
== PLUS
|| c
== MINUS
)
5064 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5067 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5077 arm_thumb_address_cost (rtx x
)
5079 enum rtx_code c
= GET_CODE (x
);
5084 && GET_CODE (XEXP (x
, 0)) == REG
5085 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5092 arm_address_cost (rtx x
)
5094 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5098 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5102 /* Some true dependencies can have a higher cost depending
5103 on precisely how certain input operands are used. */
5105 && REG_NOTE_KIND (link
) == 0
5106 && recog_memoized (insn
) >= 0
5107 && recog_memoized (dep
) >= 0)
5109 int shift_opnum
= get_attr_shift (insn
);
5110 enum attr_type attr_type
= get_attr_type (dep
);
5112 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5113 operand for INSN. If we have a shifted input operand and the
5114 instruction we depend on is another ALU instruction, then we may
5115 have to account for an additional stall. */
5116 if (shift_opnum
!= 0
5117 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5119 rtx shifted_operand
;
5122 /* Get the shifted operand. */
5123 extract_insn (insn
);
5124 shifted_operand
= recog_data
.operand
[shift_opnum
];
5126 /* Iterate over all the operands in DEP. If we write an operand
5127 that overlaps with SHIFTED_OPERAND, then we have increase the
5128 cost of this dependency. */
5130 preprocess_constraints ();
5131 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5133 /* We can ignore strict inputs. */
5134 if (recog_data
.operand_type
[opno
] == OP_IN
)
5137 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5144 /* XXX This is not strictly true for the FPA. */
5145 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5146 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5149 /* Call insns don't incur a stall, even if they follow a load. */
5150 if (REG_NOTE_KIND (link
) == 0
5151 && GET_CODE (insn
) == CALL_INSN
)
5154 if ((i_pat
= single_set (insn
)) != NULL
5155 && GET_CODE (SET_SRC (i_pat
)) == MEM
5156 && (d_pat
= single_set (dep
)) != NULL
5157 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5159 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5160 /* This is a load after a store, there is no conflict if the load reads
5161 from a cached area. Assume that loads from the stack, and from the
5162 constant pool are cached, and that others will miss. This is a
5165 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5166 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5167 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5168 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5175 static int fp_consts_inited
= 0;
5177 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5178 static const char * const strings_fp
[8] =
5181 "4", "5", "0.5", "10"
5184 static REAL_VALUE_TYPE values_fp
[8];
5187 init_fp_table (void)
5193 fp_consts_inited
= 1;
5195 fp_consts_inited
= 8;
5197 for (i
= 0; i
< fp_consts_inited
; i
++)
5199 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5204 /* Return TRUE if rtx X is a valid immediate FP constant. */
5206 arm_const_double_rtx (rtx x
)
5211 if (!fp_consts_inited
)
5214 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5215 if (REAL_VALUE_MINUS_ZERO (r
))
5218 for (i
= 0; i
< fp_consts_inited
; i
++)
5219 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5225 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5227 neg_const_double_rtx_ok_for_fpa (rtx x
)
5232 if (!fp_consts_inited
)
5235 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5236 r
= REAL_VALUE_NEGATE (r
);
5237 if (REAL_VALUE_MINUS_ZERO (r
))
5240 for (i
= 0; i
< 8; i
++)
5241 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5247 /* Predicates for `match_operand' and `match_operator'. */
5249 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5251 cirrus_memory_offset (rtx op
)
5253 /* Reject eliminable registers. */
5254 if (! (reload_in_progress
|| reload_completed
)
5255 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5256 || reg_mentioned_p (arg_pointer_rtx
, op
)
5257 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5258 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5259 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5260 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5263 if (GET_CODE (op
) == MEM
)
5269 /* Match: (mem (reg)). */
5270 if (GET_CODE (ind
) == REG
)
5276 if (GET_CODE (ind
) == PLUS
5277 && GET_CODE (XEXP (ind
, 0)) == REG
5278 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5279 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5286 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5287 WB if true if writeback address modes are allowed. */
5290 arm_coproc_mem_operand (rtx op
, bool wb
)
5294 /* Reject eliminable registers. */
5295 if (! (reload_in_progress
|| reload_completed
)
5296 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5297 || reg_mentioned_p (arg_pointer_rtx
, op
)
5298 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5299 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5300 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5301 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5304 /* Constants are converted into offsets from labels. */
5305 if (GET_CODE (op
) != MEM
)
5310 if (reload_completed
5311 && (GET_CODE (ind
) == LABEL_REF
5312 || (GET_CODE (ind
) == CONST
5313 && GET_CODE (XEXP (ind
, 0)) == PLUS
5314 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5315 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5318 /* Match: (mem (reg)). */
5319 if (GET_CODE (ind
) == REG
)
5320 return arm_address_register_rtx_p (ind
, 0);
5322 /* Autoincremment addressing modes. */
5324 && (GET_CODE (ind
) == PRE_INC
5325 || GET_CODE (ind
) == POST_INC
5326 || GET_CODE (ind
) == PRE_DEC
5327 || GET_CODE (ind
) == POST_DEC
))
5328 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5331 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5332 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5333 && GET_CODE (XEXP (ind
, 1)) == PLUS
5334 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5335 ind
= XEXP (ind
, 1);
5340 if (GET_CODE (ind
) == PLUS
5341 && GET_CODE (XEXP (ind
, 0)) == REG
5342 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5343 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5344 && INTVAL (XEXP (ind
, 1)) > -1024
5345 && INTVAL (XEXP (ind
, 1)) < 1024
5346 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5352 /* Return true if X is a register that will be eliminated later on. */
5354 arm_eliminable_register (rtx x
)
5356 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5357 || REGNO (x
) == ARG_POINTER_REGNUM
5358 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5359 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5362 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5363 VFP registers. Otherwise return NO_REGS. */
5366 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5368 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5371 return GENERAL_REGS
;
5374 /* Values which must be returned in the most-significant end of the return
5378 arm_return_in_msb (tree valtype
)
5380 return (TARGET_AAPCS_BASED
5382 && (AGGREGATE_TYPE_P (valtype
)
5383 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5386 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5387 Use by the Cirrus Maverick code which has to workaround
5388 a hardware bug triggered by such instructions. */
5390 arm_memory_load_p (rtx insn
)
5392 rtx body
, lhs
, rhs
;;
5394 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5397 body
= PATTERN (insn
);
5399 if (GET_CODE (body
) != SET
)
5402 lhs
= XEXP (body
, 0);
5403 rhs
= XEXP (body
, 1);
5405 lhs
= REG_OR_SUBREG_RTX (lhs
);
5407 /* If the destination is not a general purpose
5408 register we do not have to worry. */
5409 if (GET_CODE (lhs
) != REG
5410 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5413 /* As well as loads from memory we also have to react
5414 to loads of invalid constants which will be turned
5415 into loads from the minipool. */
5416 return (GET_CODE (rhs
) == MEM
5417 || GET_CODE (rhs
) == SYMBOL_REF
5418 || note_invalid_constants (insn
, -1, false));
5421 /* Return TRUE if INSN is a Cirrus instruction. */
5423 arm_cirrus_insn_p (rtx insn
)
5425 enum attr_cirrus attr
;
5427 /* get_attr cannot accept USE or CLOBBER. */
5429 || GET_CODE (insn
) != INSN
5430 || GET_CODE (PATTERN (insn
)) == USE
5431 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5434 attr
= get_attr_cirrus (insn
);
5436 return attr
!= CIRRUS_NOT
;
5439 /* Cirrus reorg for invalid instruction combinations. */
5441 cirrus_reorg (rtx first
)
5443 enum attr_cirrus attr
;
5444 rtx body
= PATTERN (first
);
5448 /* Any branch must be followed by 2 non Cirrus instructions. */
5449 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5452 t
= next_nonnote_insn (first
);
5454 if (arm_cirrus_insn_p (t
))
5457 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5461 emit_insn_after (gen_nop (), first
);
5466 /* (float (blah)) is in parallel with a clobber. */
5467 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5468 body
= XVECEXP (body
, 0, 0);
5470 if (GET_CODE (body
) == SET
)
5472 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5474 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5475 be followed by a non Cirrus insn. */
5476 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5478 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5479 emit_insn_after (gen_nop (), first
);
5483 else if (arm_memory_load_p (first
))
5485 unsigned int arm_regno
;
5487 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5488 ldr/cfmv64hr combination where the Rd field is the same
5489 in both instructions must be split with a non Cirrus
5496 /* Get Arm register number for ldr insn. */
5497 if (GET_CODE (lhs
) == REG
)
5498 arm_regno
= REGNO (lhs
);
5501 gcc_assert (GET_CODE (rhs
) == REG
);
5502 arm_regno
= REGNO (rhs
);
5506 first
= next_nonnote_insn (first
);
5508 if (! arm_cirrus_insn_p (first
))
5511 body
= PATTERN (first
);
5513 /* (float (blah)) is in parallel with a clobber. */
5514 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5515 body
= XVECEXP (body
, 0, 0);
5517 if (GET_CODE (body
) == FLOAT
)
5518 body
= XEXP (body
, 0);
5520 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5521 && GET_CODE (XEXP (body
, 1)) == REG
5522 && arm_regno
== REGNO (XEXP (body
, 1)))
5523 emit_insn_after (gen_nop (), first
);
5529 /* get_attr cannot accept USE or CLOBBER. */
5531 || GET_CODE (first
) != INSN
5532 || GET_CODE (PATTERN (first
)) == USE
5533 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5536 attr
= get_attr_cirrus (first
);
5538 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5539 must be followed by a non-coprocessor instruction. */
5540 if (attr
== CIRRUS_COMPARE
)
5544 t
= next_nonnote_insn (first
);
5546 if (arm_cirrus_insn_p (t
))
5549 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5553 emit_insn_after (gen_nop (), first
);
5559 /* Return TRUE if X references a SYMBOL_REF. */
5561 symbol_mentioned_p (rtx x
)
5566 if (GET_CODE (x
) == SYMBOL_REF
)
5569 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5570 are constant offsets, not symbols. */
5571 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5574 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5576 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5582 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5583 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5586 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5593 /* Return TRUE if X references a LABEL_REF. */
5595 label_mentioned_p (rtx x
)
5600 if (GET_CODE (x
) == LABEL_REF
)
5603 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5604 instruction, but they are constant offsets, not symbols. */
5605 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5608 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5609 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5615 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5616 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5619 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5627 tls_mentioned_p (rtx x
)
5629 switch (GET_CODE (x
))
5632 return tls_mentioned_p (XEXP (x
, 0));
5635 if (XINT (x
, 1) == UNSPEC_TLS
)
5643 /* Must not copy a SET whose source operand is PC-relative. */
5646 arm_cannot_copy_insn_p (rtx insn
)
5648 rtx pat
= PATTERN (insn
);
5650 if (GET_CODE (pat
) == PARALLEL
5651 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
5653 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
5655 if (GET_CODE (rhs
) == UNSPEC
5656 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
5659 if (GET_CODE (rhs
) == MEM
5660 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
5661 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
5671 enum rtx_code code
= GET_CODE (x
);
5688 /* Return 1 if memory locations are adjacent. */
5690 adjacent_mem_locations (rtx a
, rtx b
)
5692 /* We don't guarantee to preserve the order of these memory refs. */
5693 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5696 if ((GET_CODE (XEXP (a
, 0)) == REG
5697 || (GET_CODE (XEXP (a
, 0)) == PLUS
5698 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5699 && (GET_CODE (XEXP (b
, 0)) == REG
5700 || (GET_CODE (XEXP (b
, 0)) == PLUS
5701 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5703 HOST_WIDE_INT val0
= 0, val1
= 0;
5707 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5709 reg0
= XEXP (XEXP (a
, 0), 0);
5710 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5715 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5717 reg1
= XEXP (XEXP (b
, 0), 0);
5718 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5723 /* Don't accept any offset that will require multiple
5724 instructions to handle, since this would cause the
5725 arith_adjacentmem pattern to output an overlong sequence. */
5726 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5729 /* Don't allow an eliminable register: register elimination can make
5730 the offset too large. */
5731 if (arm_eliminable_register (reg0
))
5734 val_diff
= val1
- val0
;
5738 /* If the target has load delay slots, then there's no benefit
5739 to using an ldm instruction unless the offset is zero and
5740 we are optimizing for size. */
5741 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5742 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5743 && (val_diff
== 4 || val_diff
== -4));
5746 return ((REGNO (reg0
) == REGNO (reg1
))
5747 && (val_diff
== 4 || val_diff
== -4));
5754 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5755 HOST_WIDE_INT
*load_offset
)
5757 int unsorted_regs
[4];
5758 HOST_WIDE_INT unsorted_offsets
[4];
5763 /* Can only handle 2, 3, or 4 insns at present,
5764 though could be easily extended if required. */
5765 gcc_assert (nops
>= 2 && nops
<= 4);
5767 /* Loop over the operands and check that the memory references are
5768 suitable (i.e. immediate offsets from the same base register). At
5769 the same time, extract the target register, and the memory
5771 for (i
= 0; i
< nops
; i
++)
5776 /* Convert a subreg of a mem into the mem itself. */
5777 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5778 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5780 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5782 /* Don't reorder volatile memory references; it doesn't seem worth
5783 looking for the case where the order is ok anyway. */
5784 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5787 offset
= const0_rtx
;
5789 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5790 || (GET_CODE (reg
) == SUBREG
5791 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5792 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5793 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5795 || (GET_CODE (reg
) == SUBREG
5796 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5797 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5802 base_reg
= REGNO (reg
);
5803 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5804 ? REGNO (operands
[i
])
5805 : REGNO (SUBREG_REG (operands
[i
])));
5810 if (base_reg
!= (int) REGNO (reg
))
5811 /* Not addressed from the same base register. */
5814 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5815 ? REGNO (operands
[i
])
5816 : REGNO (SUBREG_REG (operands
[i
])));
5817 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5821 /* If it isn't an integer register, or if it overwrites the
5822 base register but isn't the last insn in the list, then
5823 we can't do this. */
5824 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5825 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5828 unsorted_offsets
[i
] = INTVAL (offset
);
5831 /* Not a suitable memory address. */
5835 /* All the useful information has now been extracted from the
5836 operands into unsorted_regs and unsorted_offsets; additionally,
5837 order[0] has been set to the lowest numbered register in the
5838 list. Sort the registers into order, and check that the memory
5839 offsets are ascending and adjacent. */
5841 for (i
= 1; i
< nops
; i
++)
5845 order
[i
] = order
[i
- 1];
5846 for (j
= 0; j
< nops
; j
++)
5847 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5848 && (order
[i
] == order
[i
- 1]
5849 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5852 /* Have we found a suitable register? if not, one must be used more
5854 if (order
[i
] == order
[i
- 1])
5857 /* Is the memory address adjacent and ascending? */
5858 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5866 for (i
= 0; i
< nops
; i
++)
5867 regs
[i
] = unsorted_regs
[order
[i
]];
5869 *load_offset
= unsorted_offsets
[order
[0]];
5872 if (unsorted_offsets
[order
[0]] == 0)
5873 return 1; /* ldmia */
5875 if (unsorted_offsets
[order
[0]] == 4)
5876 return 2; /* ldmib */
5878 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5879 return 3; /* ldmda */
5881 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5882 return 4; /* ldmdb */
5884 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5885 if the offset isn't small enough. The reason 2 ldrs are faster
5886 is because these ARMs are able to do more than one cache access
5887 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5888 whilst the ARM8 has a double bandwidth cache. This means that
5889 these cores can do both an instruction fetch and a data fetch in
5890 a single cycle, so the trick of calculating the address into a
5891 scratch register (one of the result regs) and then doing a load
5892 multiple actually becomes slower (and no smaller in code size).
5893 That is the transformation
5895 ldr rd1, [rbase + offset]
5896 ldr rd2, [rbase + offset + 4]
5900 add rd1, rbase, offset
5901 ldmia rd1, {rd1, rd2}
5903 produces worse code -- '3 cycles + any stalls on rd2' instead of
5904 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5905 access per cycle, the first sequence could never complete in less
5906 than 6 cycles, whereas the ldm sequence would only take 5 and
5907 would make better use of sequential accesses if not hitting the
5910 We cheat here and test 'arm_ld_sched' which we currently know to
5911 only be true for the ARM8, ARM9 and StrongARM. If this ever
5912 changes, then the test below needs to be reworked. */
5913 if (nops
== 2 && arm_ld_sched
)
5916 /* Can't do it without setting up the offset, only do this if it takes
5917 no more than one insn. */
5918 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5919 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5923 emit_ldm_seq (rtx
*operands
, int nops
)
5927 HOST_WIDE_INT offset
;
5931 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5934 strcpy (buf
, "ldm%?ia\t");
5938 strcpy (buf
, "ldm%?ib\t");
5942 strcpy (buf
, "ldm%?da\t");
5946 strcpy (buf
, "ldm%?db\t");
5951 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5952 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5955 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5956 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5958 output_asm_insn (buf
, operands
);
5960 strcpy (buf
, "ldm%?ia\t");
5967 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5968 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5970 for (i
= 1; i
< nops
; i
++)
5971 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5972 reg_names
[regs
[i
]]);
5974 strcat (buf
, "}\t%@ phole ldm");
5976 output_asm_insn (buf
, operands
);
5981 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5982 HOST_WIDE_INT
* load_offset
)
5984 int unsorted_regs
[4];
5985 HOST_WIDE_INT unsorted_offsets
[4];
5990 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5991 extended if required. */
5992 gcc_assert (nops
>= 2 && nops
<= 4);
5994 /* Loop over the operands and check that the memory references are
5995 suitable (i.e. immediate offsets from the same base register). At
5996 the same time, extract the target register, and the memory
5998 for (i
= 0; i
< nops
; i
++)
6003 /* Convert a subreg of a mem into the mem itself. */
6004 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6005 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6007 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6009 /* Don't reorder volatile memory references; it doesn't seem worth
6010 looking for the case where the order is ok anyway. */
6011 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6014 offset
= const0_rtx
;
6016 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6017 || (GET_CODE (reg
) == SUBREG
6018 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6019 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6020 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6022 || (GET_CODE (reg
) == SUBREG
6023 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6024 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6029 base_reg
= REGNO (reg
);
6030 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6031 ? REGNO (operands
[i
])
6032 : REGNO (SUBREG_REG (operands
[i
])));
6037 if (base_reg
!= (int) REGNO (reg
))
6038 /* Not addressed from the same base register. */
6041 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6042 ? REGNO (operands
[i
])
6043 : REGNO (SUBREG_REG (operands
[i
])));
6044 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6048 /* If it isn't an integer register, then we can't do this. */
6049 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6052 unsorted_offsets
[i
] = INTVAL (offset
);
6055 /* Not a suitable memory address. */
6059 /* All the useful information has now been extracted from the
6060 operands into unsorted_regs and unsorted_offsets; additionally,
6061 order[0] has been set to the lowest numbered register in the
6062 list. Sort the registers into order, and check that the memory
6063 offsets are ascending and adjacent. */
6065 for (i
= 1; i
< nops
; i
++)
6069 order
[i
] = order
[i
- 1];
6070 for (j
= 0; j
< nops
; j
++)
6071 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6072 && (order
[i
] == order
[i
- 1]
6073 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6076 /* Have we found a suitable register? if not, one must be used more
6078 if (order
[i
] == order
[i
- 1])
6081 /* Is the memory address adjacent and ascending? */
6082 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6090 for (i
= 0; i
< nops
; i
++)
6091 regs
[i
] = unsorted_regs
[order
[i
]];
6093 *load_offset
= unsorted_offsets
[order
[0]];
6096 if (unsorted_offsets
[order
[0]] == 0)
6097 return 1; /* stmia */
6099 if (unsorted_offsets
[order
[0]] == 4)
6100 return 2; /* stmib */
6102 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6103 return 3; /* stmda */
6105 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6106 return 4; /* stmdb */
6112 emit_stm_seq (rtx
*operands
, int nops
)
6116 HOST_WIDE_INT offset
;
6120 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6123 strcpy (buf
, "stm%?ia\t");
6127 strcpy (buf
, "stm%?ib\t");
6131 strcpy (buf
, "stm%?da\t");
6135 strcpy (buf
, "stm%?db\t");
6142 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6143 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6145 for (i
= 1; i
< nops
; i
++)
6146 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6147 reg_names
[regs
[i
]]);
6149 strcat (buf
, "}\t%@ phole stm");
6151 output_asm_insn (buf
, operands
);
6155 /* Routines for use in generating RTL. */
6158 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6159 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6161 HOST_WIDE_INT offset
= *offsetp
;
6164 int sign
= up
? 1 : -1;
6167 /* XScale has load-store double instructions, but they have stricter
6168 alignment requirements than load-store multiple, so we cannot
6171 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6172 the pipeline until completion.
6180 An ldr instruction takes 1-3 cycles, but does not block the
6189 Best case ldr will always win. However, the more ldr instructions
6190 we issue, the less likely we are to be able to schedule them well.
6191 Using ldr instructions also increases code size.
6193 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6194 for counts of 3 or 4 regs. */
6195 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6201 for (i
= 0; i
< count
; i
++)
6203 addr
= plus_constant (from
, i
* 4 * sign
);
6204 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6205 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6211 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6221 result
= gen_rtx_PARALLEL (VOIDmode
,
6222 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6225 XVECEXP (result
, 0, 0)
6226 = gen_rtx_SET (GET_MODE (from
), from
,
6227 plus_constant (from
, count
* 4 * sign
));
6232 for (j
= 0; i
< count
; i
++, j
++)
6234 addr
= plus_constant (from
, j
* 4 * sign
);
6235 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6236 XVECEXP (result
, 0, i
)
6237 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6248 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6249 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6251 HOST_WIDE_INT offset
= *offsetp
;
6254 int sign
= up
? 1 : -1;
6257 /* See arm_gen_load_multiple for discussion of
6258 the pros/cons of ldm/stm usage for XScale. */
6259 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6265 for (i
= 0; i
< count
; i
++)
6267 addr
= plus_constant (to
, i
* 4 * sign
);
6268 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6269 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6275 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6285 result
= gen_rtx_PARALLEL (VOIDmode
,
6286 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6289 XVECEXP (result
, 0, 0)
6290 = gen_rtx_SET (GET_MODE (to
), to
,
6291 plus_constant (to
, count
* 4 * sign
));
6296 for (j
= 0; i
< count
; i
++, j
++)
6298 addr
= plus_constant (to
, j
* 4 * sign
);
6299 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6300 XVECEXP (result
, 0, i
)
6301 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6312 arm_gen_movmemqi (rtx
*operands
)
6314 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6315 HOST_WIDE_INT srcoffset
, dstoffset
;
6317 rtx src
, dst
, srcbase
, dstbase
;
6318 rtx part_bytes_reg
= NULL
;
6321 if (GET_CODE (operands
[2]) != CONST_INT
6322 || GET_CODE (operands
[3]) != CONST_INT
6323 || INTVAL (operands
[2]) > 64
6324 || INTVAL (operands
[3]) & 3)
6327 dstbase
= operands
[0];
6328 srcbase
= operands
[1];
6330 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6331 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6333 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6334 out_words_to_go
= INTVAL (operands
[2]) / 4;
6335 last_bytes
= INTVAL (operands
[2]) & 3;
6336 dstoffset
= srcoffset
= 0;
6338 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6339 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6341 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6343 if (in_words_to_go
> 4)
6344 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6345 srcbase
, &srcoffset
));
6347 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6348 FALSE
, srcbase
, &srcoffset
));
6350 if (out_words_to_go
)
6352 if (out_words_to_go
> 4)
6353 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6354 dstbase
, &dstoffset
));
6355 else if (out_words_to_go
!= 1)
6356 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6360 dstbase
, &dstoffset
));
6363 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6364 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6365 if (last_bytes
!= 0)
6367 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6373 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6374 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6377 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6378 if (out_words_to_go
)
6382 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6383 sreg
= copy_to_reg (mem
);
6385 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6386 emit_move_insn (mem
, sreg
);
6389 gcc_assert (!in_words_to_go
); /* Sanity check */
6394 gcc_assert (in_words_to_go
> 0);
6396 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6397 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6400 gcc_assert (!last_bytes
|| part_bytes_reg
);
6402 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6404 rtx tmp
= gen_reg_rtx (SImode
);
6406 /* The bytes we want are in the top end of the word. */
6407 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6408 GEN_INT (8 * (4 - last_bytes
))));
6409 part_bytes_reg
= tmp
;
6413 mem
= adjust_automodify_address (dstbase
, QImode
,
6414 plus_constant (dst
, last_bytes
- 1),
6415 dstoffset
+ last_bytes
- 1);
6416 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6420 tmp
= gen_reg_rtx (SImode
);
6421 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6422 part_bytes_reg
= tmp
;
6431 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6432 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6436 rtx tmp
= gen_reg_rtx (SImode
);
6437 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6438 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6439 part_bytes_reg
= tmp
;
6446 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6447 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6454 /* Select a dominance comparison mode if possible for a test of the general
6455 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6456 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6457 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6458 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6459 In all cases OP will be either EQ or NE, but we don't need to know which
6460 here. If we are unable to support a dominance comparison we return
6461 CC mode. This will then fail to match for the RTL expressions that
6462 generate this call. */
6464 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6466 enum rtx_code cond1
, cond2
;
6469 /* Currently we will probably get the wrong result if the individual
6470 comparisons are not simple. This also ensures that it is safe to
6471 reverse a comparison if necessary. */
6472 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6474 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6478 /* The if_then_else variant of this tests the second condition if the
6479 first passes, but is true if the first fails. Reverse the first
6480 condition to get a true "inclusive-or" expression. */
6481 if (cond_or
== DOM_CC_NX_OR_Y
)
6482 cond1
= reverse_condition (cond1
);
6484 /* If the comparisons are not equal, and one doesn't dominate the other,
6485 then we can't do this. */
6487 && !comparison_dominates_p (cond1
, cond2
)
6488 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6493 enum rtx_code temp
= cond1
;
6501 if (cond_or
== DOM_CC_X_AND_Y
)
6506 case EQ
: return CC_DEQmode
;
6507 case LE
: return CC_DLEmode
;
6508 case LEU
: return CC_DLEUmode
;
6509 case GE
: return CC_DGEmode
;
6510 case GEU
: return CC_DGEUmode
;
6511 default: gcc_unreachable ();
6515 if (cond_or
== DOM_CC_X_AND_Y
)
6531 if (cond_or
== DOM_CC_X_AND_Y
)
6547 if (cond_or
== DOM_CC_X_AND_Y
)
6563 if (cond_or
== DOM_CC_X_AND_Y
)
6578 /* The remaining cases only occur when both comparisons are the
6581 gcc_assert (cond1
== cond2
);
6585 gcc_assert (cond1
== cond2
);
6589 gcc_assert (cond1
== cond2
);
6593 gcc_assert (cond1
== cond2
);
6597 gcc_assert (cond1
== cond2
);
6606 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6608 /* All floating point compares return CCFP if it is an equality
6609 comparison, and CCFPE otherwise. */
6610 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6630 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6639 /* A compare with a shifted operand. Because of canonicalization, the
6640 comparison will have to be swapped when we emit the assembler. */
6641 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6642 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6643 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6644 || GET_CODE (x
) == ROTATERT
))
6647 /* This operation is performed swapped, but since we only rely on the Z
6648 flag we don't need an additional mode. */
6649 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6650 && GET_CODE (x
) == NEG
6651 && (op
== EQ
|| op
== NE
))
6654 /* This is a special case that is used by combine to allow a
6655 comparison of a shifted byte load to be split into a zero-extend
6656 followed by a comparison of the shifted integer (only valid for
6657 equalities and unsigned inequalities). */
6658 if (GET_MODE (x
) == SImode
6659 && GET_CODE (x
) == ASHIFT
6660 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6661 && GET_CODE (XEXP (x
, 0)) == SUBREG
6662 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6663 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6664 && (op
== EQ
|| op
== NE
6665 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6666 && GET_CODE (y
) == CONST_INT
)
6669 /* A construct for a conditional compare, if the false arm contains
6670 0, then both conditions must be true, otherwise either condition
6671 must be true. Not all conditions are possible, so CCmode is
6672 returned if it can't be done. */
6673 if (GET_CODE (x
) == IF_THEN_ELSE
6674 && (XEXP (x
, 2) == const0_rtx
6675 || XEXP (x
, 2) == const1_rtx
)
6676 && COMPARISON_P (XEXP (x
, 0))
6677 && COMPARISON_P (XEXP (x
, 1)))
6678 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6679 INTVAL (XEXP (x
, 2)));
6681 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6682 if (GET_CODE (x
) == AND
6683 && COMPARISON_P (XEXP (x
, 0))
6684 && COMPARISON_P (XEXP (x
, 1)))
6685 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6688 if (GET_CODE (x
) == IOR
6689 && COMPARISON_P (XEXP (x
, 0))
6690 && COMPARISON_P (XEXP (x
, 1)))
6691 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6694 /* An operation (on Thumb) where we want to test for a single bit.
6695 This is done by shifting that bit up into the top bit of a
6696 scratch register; we can then branch on the sign bit. */
6698 && GET_MODE (x
) == SImode
6699 && (op
== EQ
|| op
== NE
)
6700 && (GET_CODE (x
) == ZERO_EXTRACT
))
6703 /* An operation that sets the condition codes as a side-effect, the
6704 V flag is not set correctly, so we can only use comparisons where
6705 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6707 if (GET_MODE (x
) == SImode
6709 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6710 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6711 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6712 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6713 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6714 || GET_CODE (x
) == LSHIFTRT
6715 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6716 || GET_CODE (x
) == ROTATERT
6717 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6720 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6723 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6724 && GET_CODE (x
) == PLUS
6725 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6731 /* X and Y are two things to compare using CODE. Emit the compare insn and
6732 return the rtx for register 0 in the proper mode. FP means this is a
6733 floating point compare: I don't think that it is needed on the arm. */
6735 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6737 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6738 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6740 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6741 gen_rtx_COMPARE (mode
, x
, y
)));
6746 /* Generate a sequence of insns that will generate the correct return
6747 address mask depending on the physical architecture that the program
6750 arm_gen_return_addr_mask (void)
6752 rtx reg
= gen_reg_rtx (Pmode
);
6754 emit_insn (gen_return_addr_mask (reg
));
6759 arm_reload_in_hi (rtx
*operands
)
6761 rtx ref
= operands
[1];
6763 HOST_WIDE_INT offset
= 0;
6765 if (GET_CODE (ref
) == SUBREG
)
6767 offset
= SUBREG_BYTE (ref
);
6768 ref
= SUBREG_REG (ref
);
6771 if (GET_CODE (ref
) == REG
)
6773 /* We have a pseudo which has been spilt onto the stack; there
6774 are two cases here: the first where there is a simple
6775 stack-slot replacement and a second where the stack-slot is
6776 out of range, or is used as a subreg. */
6777 if (reg_equiv_mem
[REGNO (ref
)])
6779 ref
= reg_equiv_mem
[REGNO (ref
)];
6780 base
= find_replacement (&XEXP (ref
, 0));
6783 /* The slot is out of range, or was dressed up in a SUBREG. */
6784 base
= reg_equiv_address
[REGNO (ref
)];
6787 base
= find_replacement (&XEXP (ref
, 0));
6789 /* Handle the case where the address is too complex to be offset by 1. */
6790 if (GET_CODE (base
) == MINUS
6791 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6793 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6795 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6798 else if (GET_CODE (base
) == PLUS
)
6800 /* The addend must be CONST_INT, or we would have dealt with it above. */
6801 HOST_WIDE_INT hi
, lo
;
6803 offset
+= INTVAL (XEXP (base
, 1));
6804 base
= XEXP (base
, 0);
6806 /* Rework the address into a legal sequence of insns. */
6807 /* Valid range for lo is -4095 -> 4095 */
6810 : -((-offset
) & 0xfff));
6812 /* Corner case, if lo is the max offset then we would be out of range
6813 once we have added the additional 1 below, so bump the msb into the
6814 pre-loading insn(s). */
6818 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6819 ^ (HOST_WIDE_INT
) 0x80000000)
6820 - (HOST_WIDE_INT
) 0x80000000);
6822 gcc_assert (hi
+ lo
== offset
);
6826 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6828 /* Get the base address; addsi3 knows how to handle constants
6829 that require more than one insn. */
6830 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6836 /* Operands[2] may overlap operands[0] (though it won't overlap
6837 operands[1]), that's why we asked for a DImode reg -- so we can
6838 use the bit that does not overlap. */
6839 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6840 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6842 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6844 emit_insn (gen_zero_extendqisi2 (scratch
,
6845 gen_rtx_MEM (QImode
,
6846 plus_constant (base
,
6848 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6849 gen_rtx_MEM (QImode
,
6850 plus_constant (base
,
6852 if (!BYTES_BIG_ENDIAN
)
6853 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6854 gen_rtx_IOR (SImode
,
6857 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6861 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6862 gen_rtx_IOR (SImode
,
6863 gen_rtx_ASHIFT (SImode
, scratch
,
6865 gen_rtx_SUBREG (SImode
, operands
[0],
6869 /* Handle storing a half-word to memory during reload by synthesizing as two
6870 byte stores. Take care not to clobber the input values until after we
6871 have moved them somewhere safe. This code assumes that if the DImode
6872 scratch in operands[2] overlaps either the input value or output address
6873 in some way, then that value must die in this insn (we absolutely need
6874 two scratch registers for some corner cases). */
6876 arm_reload_out_hi (rtx
*operands
)
6878 rtx ref
= operands
[0];
6879 rtx outval
= operands
[1];
6881 HOST_WIDE_INT offset
= 0;
6883 if (GET_CODE (ref
) == SUBREG
)
6885 offset
= SUBREG_BYTE (ref
);
6886 ref
= SUBREG_REG (ref
);
6889 if (GET_CODE (ref
) == REG
)
6891 /* We have a pseudo which has been spilt onto the stack; there
6892 are two cases here: the first where there is a simple
6893 stack-slot replacement and a second where the stack-slot is
6894 out of range, or is used as a subreg. */
6895 if (reg_equiv_mem
[REGNO (ref
)])
6897 ref
= reg_equiv_mem
[REGNO (ref
)];
6898 base
= find_replacement (&XEXP (ref
, 0));
6901 /* The slot is out of range, or was dressed up in a SUBREG. */
6902 base
= reg_equiv_address
[REGNO (ref
)];
6905 base
= find_replacement (&XEXP (ref
, 0));
6907 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6909 /* Handle the case where the address is too complex to be offset by 1. */
6910 if (GET_CODE (base
) == MINUS
6911 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6913 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6915 /* Be careful not to destroy OUTVAL. */
6916 if (reg_overlap_mentioned_p (base_plus
, outval
))
6918 /* Updating base_plus might destroy outval, see if we can
6919 swap the scratch and base_plus. */
6920 if (!reg_overlap_mentioned_p (scratch
, outval
))
6923 scratch
= base_plus
;
6928 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6930 /* Be conservative and copy OUTVAL into the scratch now,
6931 this should only be necessary if outval is a subreg
6932 of something larger than a word. */
6933 /* XXX Might this clobber base? I can't see how it can,
6934 since scratch is known to overlap with OUTVAL, and
6935 must be wider than a word. */
6936 emit_insn (gen_movhi (scratch_hi
, outval
));
6937 outval
= scratch_hi
;
6941 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6944 else if (GET_CODE (base
) == PLUS
)
6946 /* The addend must be CONST_INT, or we would have dealt with it above. */
6947 HOST_WIDE_INT hi
, lo
;
6949 offset
+= INTVAL (XEXP (base
, 1));
6950 base
= XEXP (base
, 0);
6952 /* Rework the address into a legal sequence of insns. */
6953 /* Valid range for lo is -4095 -> 4095 */
6956 : -((-offset
) & 0xfff));
6958 /* Corner case, if lo is the max offset then we would be out of range
6959 once we have added the additional 1 below, so bump the msb into the
6960 pre-loading insn(s). */
6964 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6965 ^ (HOST_WIDE_INT
) 0x80000000)
6966 - (HOST_WIDE_INT
) 0x80000000);
6968 gcc_assert (hi
+ lo
== offset
);
6972 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6974 /* Be careful not to destroy OUTVAL. */
6975 if (reg_overlap_mentioned_p (base_plus
, outval
))
6977 /* Updating base_plus might destroy outval, see if we
6978 can swap the scratch and base_plus. */
6979 if (!reg_overlap_mentioned_p (scratch
, outval
))
6982 scratch
= base_plus
;
6987 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6989 /* Be conservative and copy outval into scratch now,
6990 this should only be necessary if outval is a
6991 subreg of something larger than a word. */
6992 /* XXX Might this clobber base? I can't see how it
6993 can, since scratch is known to overlap with
6995 emit_insn (gen_movhi (scratch_hi
, outval
));
6996 outval
= scratch_hi
;
7000 /* Get the base address; addsi3 knows how to handle constants
7001 that require more than one insn. */
7002 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7008 if (BYTES_BIG_ENDIAN
)
7010 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7011 plus_constant (base
, offset
+ 1)),
7012 gen_lowpart (QImode
, outval
)));
7013 emit_insn (gen_lshrsi3 (scratch
,
7014 gen_rtx_SUBREG (SImode
, outval
, 0),
7016 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7017 gen_lowpart (QImode
, scratch
)));
7021 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7022 gen_lowpart (QImode
, outval
)));
7023 emit_insn (gen_lshrsi3 (scratch
,
7024 gen_rtx_SUBREG (SImode
, outval
, 0),
7026 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7027 plus_constant (base
, offset
+ 1)),
7028 gen_lowpart (QImode
, scratch
)));
7032 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7033 (padded to the size of a word) should be passed in a register. */
7036 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7038 if (TARGET_AAPCS_BASED
)
7039 return must_pass_in_stack_var_size (mode
, type
);
7041 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7045 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7046 Return true if an argument passed on the stack should be padded upwards,
7047 i.e. if the least-significant byte has useful data.
7048 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7049 aggregate types are placed in the lowest memory address. */
7052 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7054 if (!TARGET_AAPCS_BASED
)
7055 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7057 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7064 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7065 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7066 byte of the register has useful data, and return the opposite if the
7067 most significant byte does.
7068 For AAPCS, small aggregates and small complex types are always padded
7072 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7073 tree type
, int first ATTRIBUTE_UNUSED
)
7075 if (TARGET_AAPCS_BASED
7077 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7078 && int_size_in_bytes (type
) <= 4)
7081 /* Otherwise, use default padding. */
7082 return !BYTES_BIG_ENDIAN
;
7086 /* Print a symbolic form of X to the debug file, F. */
7088 arm_print_value (FILE *f
, rtx x
)
7090 switch (GET_CODE (x
))
7093 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7097 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7105 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7107 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7108 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7116 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7120 fprintf (f
, "`%s'", XSTR (x
, 0));
7124 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7128 arm_print_value (f
, XEXP (x
, 0));
7132 arm_print_value (f
, XEXP (x
, 0));
7134 arm_print_value (f
, XEXP (x
, 1));
7142 fprintf (f
, "????");
7147 /* Routines for manipulation of the constant pool. */
7149 /* Arm instructions cannot load a large constant directly into a
7150 register; they have to come from a pc relative load. The constant
7151 must therefore be placed in the addressable range of the pc
7152 relative load. Depending on the precise pc relative load
7153 instruction the range is somewhere between 256 bytes and 4k. This
7154 means that we often have to dump a constant inside a function, and
7155 generate code to branch around it.
7157 It is important to minimize this, since the branches will slow
7158 things down and make the code larger.
7160 Normally we can hide the table after an existing unconditional
7161 branch so that there is no interruption of the flow, but in the
7162 worst case the code looks like this:
7180 We fix this by performing a scan after scheduling, which notices
7181 which instructions need to have their operands fetched from the
7182 constant table and builds the table.
7184 The algorithm starts by building a table of all the constants that
7185 need fixing up and all the natural barriers in the function (places
7186 where a constant table can be dropped without breaking the flow).
7187 For each fixup we note how far the pc-relative replacement will be
7188 able to reach and the offset of the instruction into the function.
7190 Having built the table we then group the fixes together to form
7191 tables that are as large as possible (subject to addressing
7192 constraints) and emit each table of constants after the last
7193 barrier that is within range of all the instructions in the group.
7194 If a group does not contain a barrier, then we forcibly create one
7195 by inserting a jump instruction into the flow. Once the table has
7196 been inserted, the insns are then modified to reference the
7197 relevant entry in the pool.
7199 Possible enhancements to the algorithm (not implemented) are:
7201 1) For some processors and object formats, there may be benefit in
7202 aligning the pools to the start of cache lines; this alignment
7203 would need to be taken into account when calculating addressability
7206 /* These typedefs are located at the start of this file, so that
7207 they can be used in the prototypes there. This comment is to
7208 remind readers of that fact so that the following structures
7209 can be understood more easily.
7211 typedef struct minipool_node Mnode;
7212 typedef struct minipool_fixup Mfix; */
7214 struct minipool_node
7216 /* Doubly linked chain of entries. */
7219 /* The maximum offset into the code that this entry can be placed. While
7220 pushing fixes for forward references, all entries are sorted in order
7221 of increasing max_address. */
7222 HOST_WIDE_INT max_address
;
7223 /* Similarly for an entry inserted for a backwards ref. */
7224 HOST_WIDE_INT min_address
;
7225 /* The number of fixes referencing this entry. This can become zero
7226 if we "unpush" an entry. In this case we ignore the entry when we
7227 come to emit the code. */
7229 /* The offset from the start of the minipool. */
7230 HOST_WIDE_INT offset
;
7231 /* The value in table. */
7233 /* The mode of value. */
7234 enum machine_mode mode
;
7235 /* The size of the value. With iWMMXt enabled
7236 sizes > 4 also imply an alignment of 8-bytes. */
7240 struct minipool_fixup
7244 HOST_WIDE_INT address
;
7246 enum machine_mode mode
;
7250 HOST_WIDE_INT forwards
;
7251 HOST_WIDE_INT backwards
;
7254 /* Fixes less than a word need padding out to a word boundary. */
7255 #define MINIPOOL_FIX_SIZE(mode) \
7256 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7258 static Mnode
* minipool_vector_head
;
7259 static Mnode
* minipool_vector_tail
;
7260 static rtx minipool_vector_label
;
7262 /* The linked list of all minipool fixes required for this function. */
7263 Mfix
* minipool_fix_head
;
7264 Mfix
* minipool_fix_tail
;
7265 /* The fix entry for the current minipool, once it has been placed. */
7266 Mfix
* minipool_barrier
;
7268 /* Determines if INSN is the start of a jump table. Returns the end
7269 of the TABLE or NULL_RTX. */
7271 is_jump_table (rtx insn
)
7275 if (GET_CODE (insn
) == JUMP_INSN
7276 && JUMP_LABEL (insn
) != NULL
7277 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7278 == next_real_insn (insn
))
7280 && GET_CODE (table
) == JUMP_INSN
7281 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7282 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7288 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7289 #define JUMP_TABLES_IN_TEXT_SECTION 0
7292 static HOST_WIDE_INT
7293 get_jump_table_size (rtx insn
)
7295 /* ADDR_VECs only take room if read-only data does into the text
7297 if (JUMP_TABLES_IN_TEXT_SECTION
7298 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
7303 rtx body
= PATTERN (insn
);
7304 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7306 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7312 /* Move a minipool fix MP from its current location to before MAX_MP.
7313 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7314 constraints may need updating. */
7316 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7317 HOST_WIDE_INT max_address
)
7319 /* The code below assumes these are different. */
7320 gcc_assert (mp
!= max_mp
);
7324 if (max_address
< mp
->max_address
)
7325 mp
->max_address
= max_address
;
7329 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7330 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7332 mp
->max_address
= max_address
;
7334 /* Unlink MP from its current position. Since max_mp is non-null,
7335 mp->prev must be non-null. */
7336 mp
->prev
->next
= mp
->next
;
7337 if (mp
->next
!= NULL
)
7338 mp
->next
->prev
= mp
->prev
;
7340 minipool_vector_tail
= mp
->prev
;
7342 /* Re-insert it before MAX_MP. */
7344 mp
->prev
= max_mp
->prev
;
7347 if (mp
->prev
!= NULL
)
7348 mp
->prev
->next
= mp
;
7350 minipool_vector_head
= mp
;
7353 /* Save the new entry. */
7356 /* Scan over the preceding entries and adjust their addresses as
7358 while (mp
->prev
!= NULL
7359 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7361 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7368 /* Add a constant to the minipool for a forward reference. Returns the
7369 node added or NULL if the constant will not fit in this pool. */
7371 add_minipool_forward_ref (Mfix
*fix
)
7373 /* If set, max_mp is the first pool_entry that has a lower
7374 constraint than the one we are trying to add. */
7375 Mnode
* max_mp
= NULL
;
7376 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7379 /* If this fix's address is greater than the address of the first
7380 entry, then we can't put the fix in this pool. We subtract the
7381 size of the current fix to ensure that if the table is fully
7382 packed we still have enough room to insert this value by shuffling
7383 the other fixes forwards. */
7384 if (minipool_vector_head
&&
7385 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7388 /* Scan the pool to see if a constant with the same value has
7389 already been added. While we are doing this, also note the
7390 location where we must insert the constant if it doesn't already
7392 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7394 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7395 && fix
->mode
== mp
->mode
7396 && (GET_CODE (fix
->value
) != CODE_LABEL
7397 || (CODE_LABEL_NUMBER (fix
->value
)
7398 == CODE_LABEL_NUMBER (mp
->value
)))
7399 && rtx_equal_p (fix
->value
, mp
->value
))
7401 /* More than one fix references this entry. */
7403 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7406 /* Note the insertion point if necessary. */
7408 && mp
->max_address
> max_address
)
7411 /* If we are inserting an 8-bytes aligned quantity and
7412 we have not already found an insertion point, then
7413 make sure that all such 8-byte aligned quantities are
7414 placed at the start of the pool. */
7415 if (ARM_DOUBLEWORD_ALIGN
7417 && fix
->fix_size
== 8
7418 && mp
->fix_size
!= 8)
7421 max_address
= mp
->max_address
;
7425 /* The value is not currently in the minipool, so we need to create
7426 a new entry for it. If MAX_MP is NULL, the entry will be put on
7427 the end of the list since the placement is less constrained than
7428 any existing entry. Otherwise, we insert the new fix before
7429 MAX_MP and, if necessary, adjust the constraints on the other
7431 mp
= xmalloc (sizeof (* mp
));
7432 mp
->fix_size
= fix
->fix_size
;
7433 mp
->mode
= fix
->mode
;
7434 mp
->value
= fix
->value
;
7436 /* Not yet required for a backwards ref. */
7437 mp
->min_address
= -65536;
7441 mp
->max_address
= max_address
;
7443 mp
->prev
= minipool_vector_tail
;
7445 if (mp
->prev
== NULL
)
7447 minipool_vector_head
= mp
;
7448 minipool_vector_label
= gen_label_rtx ();
7451 mp
->prev
->next
= mp
;
7453 minipool_vector_tail
= mp
;
7457 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7458 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7460 mp
->max_address
= max_address
;
7463 mp
->prev
= max_mp
->prev
;
7465 if (mp
->prev
!= NULL
)
7466 mp
->prev
->next
= mp
;
7468 minipool_vector_head
= mp
;
7471 /* Save the new entry. */
7474 /* Scan over the preceding entries and adjust their addresses as
7476 while (mp
->prev
!= NULL
7477 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7479 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7487 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7488 HOST_WIDE_INT min_address
)
7490 HOST_WIDE_INT offset
;
7492 /* The code below assumes these are different. */
7493 gcc_assert (mp
!= min_mp
);
7497 if (min_address
> mp
->min_address
)
7498 mp
->min_address
= min_address
;
7502 /* We will adjust this below if it is too loose. */
7503 mp
->min_address
= min_address
;
7505 /* Unlink MP from its current position. Since min_mp is non-null,
7506 mp->next must be non-null. */
7507 mp
->next
->prev
= mp
->prev
;
7508 if (mp
->prev
!= NULL
)
7509 mp
->prev
->next
= mp
->next
;
7511 minipool_vector_head
= mp
->next
;
7513 /* Reinsert it after MIN_MP. */
7515 mp
->next
= min_mp
->next
;
7517 if (mp
->next
!= NULL
)
7518 mp
->next
->prev
= mp
;
7520 minipool_vector_tail
= mp
;
7526 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7528 mp
->offset
= offset
;
7529 if (mp
->refcount
> 0)
7530 offset
+= mp
->fix_size
;
7532 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7533 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7539 /* Add a constant to the minipool for a backward reference. Returns the
7540 node added or NULL if the constant will not fit in this pool.
7542 Note that the code for insertion for a backwards reference can be
7543 somewhat confusing because the calculated offsets for each fix do
7544 not take into account the size of the pool (which is still under
7547 add_minipool_backward_ref (Mfix
*fix
)
7549 /* If set, min_mp is the last pool_entry that has a lower constraint
7550 than the one we are trying to add. */
7551 Mnode
*min_mp
= NULL
;
7552 /* This can be negative, since it is only a constraint. */
7553 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7556 /* If we can't reach the current pool from this insn, or if we can't
7557 insert this entry at the end of the pool without pushing other
7558 fixes out of range, then we don't try. This ensures that we
7559 can't fail later on. */
7560 if (min_address
>= minipool_barrier
->address
7561 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7562 >= minipool_barrier
->address
))
7565 /* Scan the pool to see if a constant with the same value has
7566 already been added. While we are doing this, also note the
7567 location where we must insert the constant if it doesn't already
7569 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7571 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7572 && fix
->mode
== mp
->mode
7573 && (GET_CODE (fix
->value
) != CODE_LABEL
7574 || (CODE_LABEL_NUMBER (fix
->value
)
7575 == CODE_LABEL_NUMBER (mp
->value
)))
7576 && rtx_equal_p (fix
->value
, mp
->value
)
7577 /* Check that there is enough slack to move this entry to the
7578 end of the table (this is conservative). */
7580 > (minipool_barrier
->address
7581 + minipool_vector_tail
->offset
7582 + minipool_vector_tail
->fix_size
)))
7585 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7589 mp
->min_address
+= fix
->fix_size
;
7592 /* Note the insertion point if necessary. */
7593 if (mp
->min_address
< min_address
)
7595 /* For now, we do not allow the insertion of 8-byte alignment
7596 requiring nodes anywhere but at the start of the pool. */
7597 if (ARM_DOUBLEWORD_ALIGN
7598 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7603 else if (mp
->max_address
7604 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7606 /* Inserting before this entry would push the fix beyond
7607 its maximum address (which can happen if we have
7608 re-located a forwards fix); force the new fix to come
7611 min_address
= mp
->min_address
+ fix
->fix_size
;
7613 /* If we are inserting an 8-bytes aligned quantity and
7614 we have not already found an insertion point, then
7615 make sure that all such 8-byte aligned quantities are
7616 placed at the start of the pool. */
7617 else if (ARM_DOUBLEWORD_ALIGN
7619 && fix
->fix_size
== 8
7620 && mp
->fix_size
< 8)
7623 min_address
= mp
->min_address
+ fix
->fix_size
;
7628 /* We need to create a new entry. */
7629 mp
= xmalloc (sizeof (* mp
));
7630 mp
->fix_size
= fix
->fix_size
;
7631 mp
->mode
= fix
->mode
;
7632 mp
->value
= fix
->value
;
7634 mp
->max_address
= minipool_barrier
->address
+ 65536;
7636 mp
->min_address
= min_address
;
7641 mp
->next
= minipool_vector_head
;
7643 if (mp
->next
== NULL
)
7645 minipool_vector_tail
= mp
;
7646 minipool_vector_label
= gen_label_rtx ();
7649 mp
->next
->prev
= mp
;
7651 minipool_vector_head
= mp
;
7655 mp
->next
= min_mp
->next
;
7659 if (mp
->next
!= NULL
)
7660 mp
->next
->prev
= mp
;
7662 minipool_vector_tail
= mp
;
7665 /* Save the new entry. */
7673 /* Scan over the following entries and adjust their offsets. */
7674 while (mp
->next
!= NULL
)
7676 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7677 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7680 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7682 mp
->next
->offset
= mp
->offset
;
7691 assign_minipool_offsets (Mfix
*barrier
)
7693 HOST_WIDE_INT offset
= 0;
7696 minipool_barrier
= barrier
;
7698 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7700 mp
->offset
= offset
;
7702 if (mp
->refcount
> 0)
7703 offset
+= mp
->fix_size
;
7707 /* Output the literal table */
7709 dump_minipool (rtx scan
)
7715 if (ARM_DOUBLEWORD_ALIGN
)
7716 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7717 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7725 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7726 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7728 scan
= emit_label_after (gen_label_rtx (), scan
);
7729 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7730 scan
= emit_label_after (minipool_vector_label
, scan
);
7732 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7734 if (mp
->refcount
> 0)
7739 ";; Offset %u, min %ld, max %ld ",
7740 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7741 (unsigned long) mp
->max_address
);
7742 arm_print_value (dump_file
, mp
->value
);
7743 fputc ('\n', dump_file
);
7746 switch (mp
->fix_size
)
7748 #ifdef HAVE_consttable_1
7750 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7754 #ifdef HAVE_consttable_2
7756 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7760 #ifdef HAVE_consttable_4
7762 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7766 #ifdef HAVE_consttable_8
7768 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7781 minipool_vector_head
= minipool_vector_tail
= NULL
;
7782 scan
= emit_insn_after (gen_consttable_end (), scan
);
7783 scan
= emit_barrier_after (scan
);
7786 /* Return the cost of forcibly inserting a barrier after INSN. */
7788 arm_barrier_cost (rtx insn
)
7790 /* Basing the location of the pool on the loop depth is preferable,
7791 but at the moment, the basic block information seems to be
7792 corrupt by this stage of the compilation. */
7794 rtx next
= next_nonnote_insn (insn
);
7796 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7799 switch (GET_CODE (insn
))
7802 /* It will always be better to place the table before the label, rather
7811 return base_cost
- 10;
7814 return base_cost
+ 10;
7818 /* Find the best place in the insn stream in the range
7819 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7820 Create the barrier by inserting a jump and add a new fix entry for
7823 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7825 HOST_WIDE_INT count
= 0;
7827 rtx from
= fix
->insn
;
7828 rtx selected
= from
;
7830 HOST_WIDE_INT selected_address
;
7832 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7833 rtx label
= gen_label_rtx ();
7835 selected_cost
= arm_barrier_cost (from
);
7836 selected_address
= fix
->address
;
7838 while (from
&& count
< max_count
)
7843 /* This code shouldn't have been called if there was a natural barrier
7845 gcc_assert (GET_CODE (from
) != BARRIER
);
7847 /* Count the length of this insn. */
7848 count
+= get_attr_length (from
);
7850 /* If there is a jump table, add its length. */
7851 tmp
= is_jump_table (from
);
7854 count
+= get_jump_table_size (tmp
);
7856 /* Jump tables aren't in a basic block, so base the cost on
7857 the dispatch insn. If we select this location, we will
7858 still put the pool after the table. */
7859 new_cost
= arm_barrier_cost (from
);
7861 if (count
< max_count
&& new_cost
<= selected_cost
)
7864 selected_cost
= new_cost
;
7865 selected_address
= fix
->address
+ count
;
7868 /* Continue after the dispatch table. */
7869 from
= NEXT_INSN (tmp
);
7873 new_cost
= arm_barrier_cost (from
);
7875 if (count
< max_count
&& new_cost
<= selected_cost
)
7878 selected_cost
= new_cost
;
7879 selected_address
= fix
->address
+ count
;
7882 from
= NEXT_INSN (from
);
7885 /* Create a new JUMP_INSN that branches around a barrier. */
7886 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7887 JUMP_LABEL (from
) = label
;
7888 barrier
= emit_barrier_after (from
);
7889 emit_label_after (label
, barrier
);
7891 /* Create a minipool barrier entry for the new barrier. */
7892 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7893 new_fix
->insn
= barrier
;
7894 new_fix
->address
= selected_address
;
7895 new_fix
->next
= fix
->next
;
7896 fix
->next
= new_fix
;
7901 /* Record that there is a natural barrier in the insn stream at
7904 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7906 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7909 fix
->address
= address
;
7912 if (minipool_fix_head
!= NULL
)
7913 minipool_fix_tail
->next
= fix
;
7915 minipool_fix_head
= fix
;
7917 minipool_fix_tail
= fix
;
7920 /* Record INSN, which will need fixing up to load a value from the
7921 minipool. ADDRESS is the offset of the insn since the start of the
7922 function; LOC is a pointer to the part of the insn which requires
7923 fixing; VALUE is the constant that must be loaded, which is of type
7926 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7927 enum machine_mode mode
, rtx value
)
7929 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7931 #ifdef AOF_ASSEMBLER
7932 /* PIC symbol references need to be converted into offsets into the
7934 /* XXX This shouldn't be done here. */
7935 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7936 value
= aof_pic_entry (value
);
7937 #endif /* AOF_ASSEMBLER */
7940 fix
->address
= address
;
7943 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7945 fix
->forwards
= get_attr_pool_range (insn
);
7946 fix
->backwards
= get_attr_neg_pool_range (insn
);
7947 fix
->minipool
= NULL
;
7949 /* If an insn doesn't have a range defined for it, then it isn't
7950 expecting to be reworked by this code. Better to stop now than
7951 to generate duff assembly code. */
7952 gcc_assert (fix
->forwards
|| fix
->backwards
);
7954 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7955 So there might be an empty word before the start of the pool.
7956 Hence we reduce the forward range by 4 to allow for this
7958 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7964 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7965 GET_MODE_NAME (mode
),
7966 INSN_UID (insn
), (unsigned long) address
,
7967 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7968 arm_print_value (dump_file
, fix
->value
);
7969 fprintf (dump_file
, "\n");
7972 /* Add it to the chain of fixes. */
7975 if (minipool_fix_head
!= NULL
)
7976 minipool_fix_tail
->next
= fix
;
7978 minipool_fix_head
= fix
;
7980 minipool_fix_tail
= fix
;
7983 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7984 Returns the number of insns needed, or 99 if we don't know how to
7987 arm_const_double_inline_cost (rtx val
)
7989 rtx lowpart
, highpart
;
7990 enum machine_mode mode
;
7992 mode
= GET_MODE (val
);
7994 if (mode
== VOIDmode
)
7997 gcc_assert (GET_MODE_SIZE (mode
) == 8);
7999 lowpart
= gen_lowpart (SImode
, val
);
8000 highpart
= gen_highpart_mode (SImode
, mode
, val
);
8002 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
8003 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
8005 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
8006 NULL_RTX
, NULL_RTX
, 0, 0)
8007 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
8008 NULL_RTX
, NULL_RTX
, 0, 0));
8011 /* Return true if it is worthwhile to split a 64-bit constant into two
8012 32-bit operations. This is the case if optimizing for size, or
8013 if we have load delay slots, or if one 32-bit part can be done with
8014 a single data operation. */
8016 arm_const_double_by_parts (rtx val
)
8018 enum machine_mode mode
= GET_MODE (val
);
8021 if (optimize_size
|| arm_ld_sched
)
8024 if (mode
== VOIDmode
)
8027 part
= gen_highpart_mode (SImode
, mode
, val
);
8029 gcc_assert (GET_CODE (part
) == CONST_INT
);
8031 if (const_ok_for_arm (INTVAL (part
))
8032 || const_ok_for_arm (~INTVAL (part
)))
8035 part
= gen_lowpart (SImode
, val
);
8037 gcc_assert (GET_CODE (part
) == CONST_INT
);
8039 if (const_ok_for_arm (INTVAL (part
))
8040 || const_ok_for_arm (~INTVAL (part
)))
8046 /* Scan INSN and note any of its operands that need fixing.
8047 If DO_PUSHES is false we do not actually push any of the fixups
8048 needed. The function returns TRUE if any fixups were needed/pushed.
8049 This is used by arm_memory_load_p() which needs to know about loads
8050 of constants that will be converted into minipool loads. */
8052 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8054 bool result
= false;
8057 extract_insn (insn
);
8059 if (!constrain_operands (1))
8060 fatal_insn_not_found (insn
);
8062 if (recog_data
.n_alternatives
== 0)
8065 /* Fill in recog_op_alt with information about the constraints of
8067 preprocess_constraints ();
8069 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8071 /* Things we need to fix can only occur in inputs. */
8072 if (recog_data
.operand_type
[opno
] != OP_IN
)
8075 /* If this alternative is a memory reference, then any mention
8076 of constants in this alternative is really to fool reload
8077 into allowing us to accept one there. We need to fix them up
8078 now so that we output the right code. */
8079 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8081 rtx op
= recog_data
.operand
[opno
];
8083 if (CONSTANT_P (op
))
8086 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8087 recog_data
.operand_mode
[opno
], op
);
8090 else if (GET_CODE (op
) == MEM
8091 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8092 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8096 rtx cop
= avoid_constant_pool_reference (op
);
8098 /* Casting the address of something to a mode narrower
8099 than a word can cause avoid_constant_pool_reference()
8100 to return the pool reference itself. That's no good to
8101 us here. Lets just hope that we can use the
8102 constant pool value directly. */
8104 cop
= get_pool_constant (XEXP (op
, 0));
8106 push_minipool_fix (insn
, address
,
8107 recog_data
.operand_loc
[opno
],
8108 recog_data
.operand_mode
[opno
], cop
);
8119 /* Gcc puts the pool in the wrong place for ARM, since we can only
8120 load addresses a limited distance around the pc. We do some
8121 special munging to move the constant pool values to the correct
8122 point in the code. */
8127 HOST_WIDE_INT address
= 0;
8130 minipool_fix_head
= minipool_fix_tail
= NULL
;
8132 /* The first insn must always be a note, or the code below won't
8133 scan it properly. */
8134 insn
= get_insns ();
8135 gcc_assert (GET_CODE (insn
) == NOTE
);
8137 /* Scan all the insns and record the operands that will need fixing. */
8138 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8140 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8141 && (arm_cirrus_insn_p (insn
)
8142 || GET_CODE (insn
) == JUMP_INSN
8143 || arm_memory_load_p (insn
)))
8144 cirrus_reorg (insn
);
8146 if (GET_CODE (insn
) == BARRIER
)
8147 push_minipool_barrier (insn
, address
);
8148 else if (INSN_P (insn
))
8152 note_invalid_constants (insn
, address
, true);
8153 address
+= get_attr_length (insn
);
8155 /* If the insn is a vector jump, add the size of the table
8156 and skip the table. */
8157 if ((table
= is_jump_table (insn
)) != NULL
)
8159 address
+= get_jump_table_size (table
);
8165 fix
= minipool_fix_head
;
8167 /* Now scan the fixups and perform the required changes. */
8172 Mfix
* last_added_fix
;
8173 Mfix
* last_barrier
= NULL
;
8176 /* Skip any further barriers before the next fix. */
8177 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8180 /* No more fixes. */
8184 last_added_fix
= NULL
;
8186 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8188 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8190 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8193 last_barrier
= ftmp
;
8195 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8198 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8201 /* If we found a barrier, drop back to that; any fixes that we
8202 could have reached but come after the barrier will now go in
8203 the next mini-pool. */
8204 if (last_barrier
!= NULL
)
8206 /* Reduce the refcount for those fixes that won't go into this
8208 for (fdel
= last_barrier
->next
;
8209 fdel
&& fdel
!= ftmp
;
8212 fdel
->minipool
->refcount
--;
8213 fdel
->minipool
= NULL
;
8216 ftmp
= last_barrier
;
8220 /* ftmp is first fix that we can't fit into this pool and
8221 there no natural barriers that we could use. Insert a
8222 new barrier in the code somewhere between the previous
8223 fix and this one, and arrange to jump around it. */
8224 HOST_WIDE_INT max_address
;
8226 /* The last item on the list of fixes must be a barrier, so
8227 we can never run off the end of the list of fixes without
8228 last_barrier being set. */
8231 max_address
= minipool_vector_head
->max_address
;
8232 /* Check that there isn't another fix that is in range that
8233 we couldn't fit into this pool because the pool was
8234 already too large: we need to put the pool before such an
8236 if (ftmp
->address
< max_address
)
8237 max_address
= ftmp
->address
;
8239 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8242 assign_minipool_offsets (last_barrier
);
8246 if (GET_CODE (ftmp
->insn
) != BARRIER
8247 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8254 /* Scan over the fixes we have identified for this pool, fixing them
8255 up and adding the constants to the pool itself. */
8256 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8257 this_fix
= this_fix
->next
)
8258 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8261 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8262 minipool_vector_label
),
8263 this_fix
->minipool
->offset
);
8264 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8267 dump_minipool (last_barrier
->insn
);
8271 /* From now on we must synthesize any constants that we can't handle
8272 directly. This can happen if the RTL gets split during final
8273 instruction generation. */
8274 after_arm_reorg
= 1;
8276 /* Free the minipool memory. */
8277 obstack_free (&minipool_obstack
, minipool_startobj
);
8280 /* Routines to output assembly language. */
8282 /* If the rtx is the correct value then return the string of the number.
8283 In this way we can ensure that valid double constants are generated even
8284 when cross compiling. */
8286 fp_immediate_constant (rtx x
)
8291 if (!fp_consts_inited
)
8294 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8295 for (i
= 0; i
< 8; i
++)
8296 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8297 return strings_fp
[i
];
8302 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8304 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8308 if (!fp_consts_inited
)
8311 for (i
= 0; i
< 8; i
++)
8312 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8313 return strings_fp
[i
];
8318 /* Output the operands of a LDM/STM instruction to STREAM.
8319 MASK is the ARM register set mask of which only bits 0-15 are important.
8320 REG is the base register, either the frame pointer or the stack pointer,
8321 INSTR is the possibly suffixed load or store instruction. */
8324 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8328 bool not_first
= FALSE
;
8330 fputc ('\t', stream
);
8331 asm_fprintf (stream
, instr
, reg
);
8332 fputs (", {", stream
);
8334 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8335 if (mask
& (1 << i
))
8338 fprintf (stream
, ", ");
8340 asm_fprintf (stream
, "%r", i
);
8344 fprintf (stream
, "}\n");
8348 /* Output a FLDMX instruction to STREAM.
8349 BASE if the register containing the address.
8350 REG and COUNT specify the register range.
8351 Extra registers may be added to avoid hardware bugs. */
8354 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8358 /* Workaround ARM10 VFPr1 bug. */
8359 if (count
== 2 && !arm_arch6
)
8366 fputc ('\t', stream
);
8367 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8369 for (i
= reg
; i
< reg
+ count
; i
++)
8372 fputs (", ", stream
);
8373 asm_fprintf (stream
, "d%d", i
);
8375 fputs ("}\n", stream
);
8380 /* Output the assembly for a store multiple. */
8383 vfp_output_fstmx (rtx
* operands
)
8390 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8391 p
= strlen (pattern
);
8393 gcc_assert (GET_CODE (operands
[1]) == REG
);
8395 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8396 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8398 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8400 strcpy (&pattern
[p
], "}");
8402 output_asm_insn (pattern
, operands
);
8407 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8408 number of bytes pushed. */
8411 vfp_emit_fstmx (int base_reg
, int count
)
8418 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8419 register pairs are stored by a store multiple insn. We avoid this
8420 by pushing an extra pair. */
8421 if (count
== 2 && !arm_arch6
)
8423 if (base_reg
== LAST_VFP_REGNUM
- 3)
8428 /* ??? The frame layout is implementation defined. We describe
8429 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8430 We really need some way of representing the whole block so that the
8431 unwinder can figure it out at runtime. */
8432 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8433 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8435 reg
= gen_rtx_REG (DFmode
, base_reg
);
8439 = gen_rtx_SET (VOIDmode
,
8440 gen_frame_mem (BLKmode
,
8441 gen_rtx_PRE_DEC (BLKmode
,
8442 stack_pointer_rtx
)),
8443 gen_rtx_UNSPEC (BLKmode
,
8447 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8448 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8449 GEN_INT (-(count
* 8 + 4))));
8450 RTX_FRAME_RELATED_P (tmp
) = 1;
8451 XVECEXP (dwarf
, 0, 0) = tmp
;
8453 tmp
= gen_rtx_SET (VOIDmode
,
8454 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8456 RTX_FRAME_RELATED_P (tmp
) = 1;
8457 XVECEXP (dwarf
, 0, 1) = tmp
;
8459 for (i
= 1; i
< count
; i
++)
8461 reg
= gen_rtx_REG (DFmode
, base_reg
);
8463 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8465 tmp
= gen_rtx_SET (VOIDmode
,
8466 gen_frame_mem (DFmode
,
8467 gen_rtx_PLUS (SImode
,
8471 RTX_FRAME_RELATED_P (tmp
) = 1;
8472 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8475 par
= emit_insn (par
);
8476 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8478 RTX_FRAME_RELATED_P (par
) = 1;
8480 return count
* 8 + 4;
8484 /* Output a 'call' insn. */
8486 output_call (rtx
*operands
)
8488 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8490 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8491 if (REGNO (operands
[0]) == LR_REGNUM
)
8493 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8494 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8497 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8499 if (TARGET_INTERWORK
|| arm_arch4t
)
8500 output_asm_insn ("bx%?\t%0", operands
);
8502 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8507 /* Output a 'call' insn that is a reference in memory. */
8509 output_call_mem (rtx
*operands
)
8511 if (TARGET_INTERWORK
&& !arm_arch5
)
8513 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8514 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8515 output_asm_insn ("bx%?\t%|ip", operands
);
8517 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8519 /* LR is used in the memory address. We load the address in the
8520 first instruction. It's safe to use IP as the target of the
8521 load since the call will kill it anyway. */
8522 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8524 output_asm_insn ("blx%?\t%|ip", operands
);
8527 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8529 output_asm_insn ("bx%?\t%|ip", operands
);
8531 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8536 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8537 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8544 /* Output a move from arm registers to an fpa registers.
8545 OPERANDS[0] is an fpa register.
8546 OPERANDS[1] is the first registers of an arm register pair. */
8548 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8550 int arm_reg0
= REGNO (operands
[1]);
8553 gcc_assert (arm_reg0
!= IP_REGNUM
);
8555 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8556 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8557 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8559 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8560 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8565 /* Output a move from an fpa register to arm registers.
8566 OPERANDS[0] is the first registers of an arm register pair.
8567 OPERANDS[1] is an fpa register. */
8569 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8571 int arm_reg0
= REGNO (operands
[0]);
8574 gcc_assert (arm_reg0
!= IP_REGNUM
);
8576 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8577 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8578 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8580 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8581 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8585 /* Output a move from arm registers to arm registers of a long double
8586 OPERANDS[0] is the destination.
8587 OPERANDS[1] is the source. */
8589 output_mov_long_double_arm_from_arm (rtx
*operands
)
8591 /* We have to be careful here because the two might overlap. */
8592 int dest_start
= REGNO (operands
[0]);
8593 int src_start
= REGNO (operands
[1]);
8597 if (dest_start
< src_start
)
8599 for (i
= 0; i
< 3; i
++)
8601 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8602 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8603 output_asm_insn ("mov%?\t%0, %1", ops
);
8608 for (i
= 2; i
>= 0; i
--)
8610 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8611 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8612 output_asm_insn ("mov%?\t%0, %1", ops
);
8620 /* Output a move from arm registers to an fpa registers.
8621 OPERANDS[0] is an fpa register.
8622 OPERANDS[1] is the first registers of an arm register pair. */
8624 output_mov_double_fpa_from_arm (rtx
*operands
)
8626 int arm_reg0
= REGNO (operands
[1]);
8629 gcc_assert (arm_reg0
!= IP_REGNUM
);
8631 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8632 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8633 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8634 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8638 /* Output a move from an fpa register to arm registers.
8639 OPERANDS[0] is the first registers of an arm register pair.
8640 OPERANDS[1] is an fpa register. */
8642 output_mov_double_arm_from_fpa (rtx
*operands
)
8644 int arm_reg0
= REGNO (operands
[0]);
8647 gcc_assert (arm_reg0
!= IP_REGNUM
);
8649 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8650 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8651 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8652 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8656 /* Output a move between double words.
8657 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8658 or MEM<-REG and all MEMs must be offsettable addresses. */
8660 output_move_double (rtx
*operands
)
8662 enum rtx_code code0
= GET_CODE (operands
[0]);
8663 enum rtx_code code1
= GET_CODE (operands
[1]);
8668 int reg0
= REGNO (operands
[0]);
8670 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8672 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8674 switch (GET_CODE (XEXP (operands
[1], 0)))
8677 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8681 gcc_assert (TARGET_LDRD
);
8682 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8686 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8690 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8694 gcc_assert (TARGET_LDRD
);
8695 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8700 otherops
[0] = operands
[0];
8701 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8702 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8704 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8706 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8708 /* Registers overlap so split out the increment. */
8709 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8710 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8713 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8717 /* We only allow constant increments, so this is safe. */
8718 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8724 output_asm_insn ("adr%?\t%0, %1", operands
);
8725 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8729 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8730 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8732 otherops
[0] = operands
[0];
8733 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8734 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8736 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8738 if (GET_CODE (otherops
[2]) == CONST_INT
)
8740 switch ((int) INTVAL (otherops
[2]))
8743 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8746 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8749 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8754 && (GET_CODE (otherops
[2]) == REG
8755 || (GET_CODE (otherops
[2]) == CONST_INT
8756 && INTVAL (otherops
[2]) > -256
8757 && INTVAL (otherops
[2]) < 256)))
8759 if (reg_overlap_mentioned_p (otherops
[0],
8762 /* Swap base and index registers over to
8763 avoid a conflict. */
8764 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8765 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8767 /* If both registers conflict, it will usually
8768 have been fixed by a splitter. */
8769 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8771 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8772 output_asm_insn ("ldr%?d\t%0, [%1]",
8776 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8780 if (GET_CODE (otherops
[2]) == CONST_INT
)
8782 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8783 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8785 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8788 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8791 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8793 return "ldm%?ia\t%0, %M0";
8797 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8798 /* Take care of overlapping base/data reg. */
8799 if (reg_mentioned_p (operands
[0], operands
[1]))
8801 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8802 output_asm_insn ("ldr%?\t%0, %1", operands
);
8806 output_asm_insn ("ldr%?\t%0, %1", operands
);
8807 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8814 /* Constraints should ensure this. */
8815 gcc_assert (code0
== MEM
&& code1
== REG
);
8816 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8818 switch (GET_CODE (XEXP (operands
[0], 0)))
8821 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8825 gcc_assert (TARGET_LDRD
);
8826 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8830 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8834 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8838 gcc_assert (TARGET_LDRD
);
8839 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8844 otherops
[0] = operands
[1];
8845 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8846 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8848 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8849 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8851 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8855 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8856 if (GET_CODE (otherops
[2]) == CONST_INT
)
8858 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8861 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8865 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8869 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8874 && (GET_CODE (otherops
[2]) == REG
8875 || (GET_CODE (otherops
[2]) == CONST_INT
8876 && INTVAL (otherops
[2]) > -256
8877 && INTVAL (otherops
[2]) < 256)))
8879 otherops
[0] = operands
[1];
8880 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8881 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8887 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8888 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8889 output_asm_insn ("str%?\t%1, %0", operands
);
8890 output_asm_insn ("str%?\t%1, %0", otherops
);
8897 /* Output an ADD r, s, #n where n may be too big for one instruction.
8898 If adding zero to one register, output nothing. */
8900 output_add_immediate (rtx
*operands
)
8902 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8904 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8907 output_multi_immediate (operands
,
8908 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8911 output_multi_immediate (operands
,
8912 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8919 /* Output a multiple immediate operation.
8920 OPERANDS is the vector of operands referred to in the output patterns.
8921 INSTR1 is the output pattern to use for the first constant.
8922 INSTR2 is the output pattern to use for subsequent constants.
8923 IMMED_OP is the index of the constant slot in OPERANDS.
8924 N is the constant value. */
8926 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8927 int immed_op
, HOST_WIDE_INT n
)
8929 #if HOST_BITS_PER_WIDE_INT > 32
8935 /* Quick and easy output. */
8936 operands
[immed_op
] = const0_rtx
;
8937 output_asm_insn (instr1
, operands
);
8942 const char * instr
= instr1
;
8944 /* Note that n is never zero here (which would give no output). */
8945 for (i
= 0; i
< 32; i
+= 2)
8949 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8950 output_asm_insn (instr
, operands
);
8960 /* Return the appropriate ARM instruction for the operation code.
8961 The returned result should not be overwritten. OP is the rtx of the
8962 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8965 arithmetic_instr (rtx op
, int shift_first_arg
)
8967 switch (GET_CODE (op
))
8973 return shift_first_arg
? "rsb" : "sub";
8989 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8990 for the operation code. The returned result should not be overwritten.
8991 OP is the rtx code of the shift.
8992 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8995 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8998 enum rtx_code code
= GET_CODE (op
);
9000 switch (GET_CODE (XEXP (op
, 1)))
9008 *amountp
= INTVAL (XEXP (op
, 1));
9030 gcc_assert (*amountp
!= -1);
9031 *amountp
= 32 - *amountp
;
9040 /* We never have to worry about the amount being other than a
9041 power of 2, since this case can never be reloaded from a reg. */
9042 gcc_assert (*amountp
!= -1);
9043 *amountp
= int_log2 (*amountp
);
9052 /* This is not 100% correct, but follows from the desire to merge
9053 multiplication by a power of 2 with the recognizer for a
9054 shift. >=32 is not a valid shift for "asl", so we must try and
9055 output a shift that produces the correct arithmetical result.
9056 Using lsr #32 is identical except for the fact that the carry bit
9057 is not set correctly if we set the flags; but we never use the
9058 carry bit from such an operation, so we can ignore that. */
9059 if (code
== ROTATERT
)
9060 /* Rotate is just modulo 32. */
9062 else if (*amountp
!= (*amountp
& 31))
9069 /* Shifts of 0 are no-ops. */
9077 /* Obtain the shift from the POWER of two. */
9079 static HOST_WIDE_INT
9080 int_log2 (HOST_WIDE_INT power
)
9082 HOST_WIDE_INT shift
= 0;
9084 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9086 gcc_assert (shift
<= 31);
9093 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9094 because /bin/as is horribly restrictive. The judgement about
9095 whether or not each character is 'printable' (and can be output as
9096 is) or not (and must be printed with an octal escape) must be made
9097 with reference to the *host* character set -- the situation is
9098 similar to that discussed in the comments above pp_c_char in
9099 c-pretty-print.c. */
9101 #define MAX_ASCII_LEN 51
9104 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9109 fputs ("\t.ascii\t\"", stream
);
9111 for (i
= 0; i
< len
; i
++)
9115 if (len_so_far
>= MAX_ASCII_LEN
)
9117 fputs ("\"\n\t.ascii\t\"", stream
);
9123 if (c
== '\\' || c
== '\"')
9125 putc ('\\', stream
);
9133 fprintf (stream
, "\\%03o", c
);
9138 fputs ("\"\n", stream
);
9141 /* Compute the register save mask for registers 0 through 12
9142 inclusive. This code is used by arm_compute_save_reg_mask. */
9144 static unsigned long
9145 arm_compute_save_reg0_reg12_mask (void)
9147 unsigned long func_type
= arm_current_func_type ();
9148 unsigned long save_reg_mask
= 0;
9151 if (IS_INTERRUPT (func_type
))
9153 unsigned int max_reg
;
9154 /* Interrupt functions must not corrupt any registers,
9155 even call clobbered ones. If this is a leaf function
9156 we can just examine the registers used by the RTL, but
9157 otherwise we have to assume that whatever function is
9158 called might clobber anything, and so we have to save
9159 all the call-clobbered registers as well. */
9160 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9161 /* FIQ handlers have registers r8 - r12 banked, so
9162 we only need to check r0 - r7, Normal ISRs only
9163 bank r14 and r15, so we must check up to r12.
9164 r13 is the stack pointer which is always preserved,
9165 so we do not need to consider it here. */
9170 for (reg
= 0; reg
<= max_reg
; reg
++)
9171 if (regs_ever_live
[reg
]
9172 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9173 save_reg_mask
|= (1 << reg
);
9175 /* Also save the pic base register if necessary. */
9177 && !TARGET_SINGLE_PIC_BASE
9178 && current_function_uses_pic_offset_table
)
9179 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9183 /* In the normal case we only need to save those registers
9184 which are call saved and which are used by this function. */
9185 for (reg
= 0; reg
<= 10; reg
++)
9186 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9187 save_reg_mask
|= (1 << reg
);
9189 /* Handle the frame pointer as a special case. */
9190 if (! TARGET_APCS_FRAME
9191 && ! frame_pointer_needed
9192 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9193 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9194 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9196 /* If we aren't loading the PIC register,
9197 don't stack it even though it may be live. */
9199 && !TARGET_SINGLE_PIC_BASE
9200 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9201 || current_function_uses_pic_offset_table
))
9202 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9205 /* Save registers so the exception handler can modify them. */
9206 if (current_function_calls_eh_return
)
9212 reg
= EH_RETURN_DATA_REGNO (i
);
9213 if (reg
== INVALID_REGNUM
)
9215 save_reg_mask
|= 1 << reg
;
9219 return save_reg_mask
;
9222 /* Compute a bit mask of which registers need to be
9223 saved on the stack for the current function. */
9225 static unsigned long
9226 arm_compute_save_reg_mask (void)
9228 unsigned int save_reg_mask
= 0;
9229 unsigned long func_type
= arm_current_func_type ();
9231 if (IS_NAKED (func_type
))
9232 /* This should never really happen. */
9235 /* If we are creating a stack frame, then we must save the frame pointer,
9236 IP (which will hold the old stack pointer), LR and the PC. */
9237 if (frame_pointer_needed
)
9239 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9244 /* Volatile functions do not return, so there
9245 is no need to save any other registers. */
9246 if (IS_VOLATILE (func_type
))
9247 return save_reg_mask
;
9249 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9251 /* Decide if we need to save the link register.
9252 Interrupt routines have their own banked link register,
9253 so they never need to save it.
9254 Otherwise if we do not use the link register we do not need to save
9255 it. If we are pushing other registers onto the stack however, we
9256 can save an instruction in the epilogue by pushing the link register
9257 now and then popping it back into the PC. This incurs extra memory
9258 accesses though, so we only do it when optimizing for size, and only
9259 if we know that we will not need a fancy return sequence. */
9260 if (regs_ever_live
[LR_REGNUM
]
9263 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9264 && !current_function_calls_eh_return
))
9265 save_reg_mask
|= 1 << LR_REGNUM
;
9267 if (cfun
->machine
->lr_save_eliminated
)
9268 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9270 if (TARGET_REALLY_IWMMXT
9271 && ((bit_count (save_reg_mask
)
9272 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9276 /* The total number of registers that are going to be pushed
9277 onto the stack is odd. We need to ensure that the stack
9278 is 64-bit aligned before we start to save iWMMXt registers,
9279 and also before we start to create locals. (A local variable
9280 might be a double or long long which we will load/store using
9281 an iWMMXt instruction). Therefore we need to push another
9282 ARM register, so that the stack will be 64-bit aligned. We
9283 try to avoid using the arg registers (r0 -r3) as they might be
9284 used to pass values in a tail call. */
9285 for (reg
= 4; reg
<= 12; reg
++)
9286 if ((save_reg_mask
& (1 << reg
)) == 0)
9290 save_reg_mask
|= (1 << reg
);
9293 cfun
->machine
->sibcall_blocked
= 1;
9294 save_reg_mask
|= (1 << 3);
9298 return save_reg_mask
;
9302 /* Compute a bit mask of which registers need to be
9303 saved on the stack for the current function. */
9304 static unsigned long
9305 thumb_compute_save_reg_mask (void)
9311 for (reg
= 0; reg
< 12; reg
++)
9312 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9316 && !TARGET_SINGLE_PIC_BASE
9317 && current_function_uses_pic_offset_table
)
9318 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9320 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9321 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9322 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9324 /* LR will also be pushed if any lo regs are pushed. */
9325 if (mask
& 0xff || thumb_force_lr_save ())
9326 mask
|= (1 << LR_REGNUM
);
9328 /* Make sure we have a low work register if we need one.
9329 We will need one if we are going to push a high register,
9330 but we are not currently intending to push a low register. */
9331 if ((mask
& 0xff) == 0
9332 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9334 /* Use thumb_find_work_register to choose which register
9335 we will use. If the register is live then we will
9336 have to push it. Use LAST_LO_REGNUM as our fallback
9337 choice for the register to select. */
9338 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9340 if (! call_used_regs
[reg
])
9348 /* Return the number of bytes required to save VFP registers. */
9350 arm_get_vfp_saved_size (void)
9357 /* Space for saved VFP registers. */
9358 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9361 for (regno
= FIRST_VFP_REGNUM
;
9362 regno
< LAST_VFP_REGNUM
;
9365 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9366 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9370 /* Workaround ARM10 VFPr1 bug. */
9371 if (count
== 2 && !arm_arch6
)
9373 saved
+= count
* 8 + 4;
9382 if (count
== 2 && !arm_arch6
)
9384 saved
+= count
* 8 + 4;
9391 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9392 everything bar the final return instruction. */
9394 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9396 char conditional
[10];
9399 unsigned long live_regs_mask
;
9400 unsigned long func_type
;
9401 arm_stack_offsets
*offsets
;
9403 func_type
= arm_current_func_type ();
9405 if (IS_NAKED (func_type
))
9408 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9410 /* If this function was declared non-returning, and we have
9411 found a tail call, then we have to trust that the called
9412 function won't return. */
9417 /* Otherwise, trap an attempted return by aborting. */
9419 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9421 assemble_external_libcall (ops
[1]);
9422 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9428 gcc_assert (!current_function_calls_alloca
|| really_return
);
9430 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9432 return_used_this_function
= 1;
9434 live_regs_mask
= arm_compute_save_reg_mask ();
9438 const char * return_reg
;
9440 /* If we do not have any special requirements for function exit
9441 (e.g. interworking, or ISR) then we can load the return address
9442 directly into the PC. Otherwise we must load it into LR. */
9444 && ! TARGET_INTERWORK
)
9445 return_reg
= reg_names
[PC_REGNUM
];
9447 return_reg
= reg_names
[LR_REGNUM
];
9449 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9451 /* There are three possible reasons for the IP register
9452 being saved. 1) a stack frame was created, in which case
9453 IP contains the old stack pointer, or 2) an ISR routine
9454 corrupted it, or 3) it was saved to align the stack on
9455 iWMMXt. In case 1, restore IP into SP, otherwise just
9457 if (frame_pointer_needed
)
9459 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9460 live_regs_mask
|= (1 << SP_REGNUM
);
9463 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9466 /* On some ARM architectures it is faster to use LDR rather than
9467 LDM to load a single register. On other architectures, the
9468 cost is the same. In 26 bit mode, or for exception handlers,
9469 we have to use LDM to load the PC so that the CPSR is also
9471 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9472 if (live_regs_mask
== (1U << reg
))
9475 if (reg
<= LAST_ARM_REGNUM
9476 && (reg
!= LR_REGNUM
9478 || ! IS_INTERRUPT (func_type
)))
9480 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9481 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9488 /* Generate the load multiple instruction to restore the
9489 registers. Note we can get here, even if
9490 frame_pointer_needed is true, but only if sp already
9491 points to the base of the saved core registers. */
9492 if (live_regs_mask
& (1 << SP_REGNUM
))
9494 unsigned HOST_WIDE_INT stack_adjust
;
9496 offsets
= arm_get_frame_offsets ();
9497 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9498 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9500 if (stack_adjust
&& arm_arch5
)
9501 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9504 /* If we can't use ldmib (SA110 bug),
9505 then try to pop r3 instead. */
9507 live_regs_mask
|= 1 << 3;
9508 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9512 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9514 p
= instr
+ strlen (instr
);
9516 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9517 if (live_regs_mask
& (1 << reg
))
9519 int l
= strlen (reg_names
[reg
]);
9525 memcpy (p
, ", ", 2);
9529 memcpy (p
, "%|", 2);
9530 memcpy (p
+ 2, reg_names
[reg
], l
);
9534 if (live_regs_mask
& (1 << LR_REGNUM
))
9536 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9537 /* If returning from an interrupt, restore the CPSR. */
9538 if (IS_INTERRUPT (func_type
))
9545 output_asm_insn (instr
, & operand
);
9547 /* See if we need to generate an extra instruction to
9548 perform the actual function return. */
9550 && func_type
!= ARM_FT_INTERWORKED
9551 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9553 /* The return has already been handled
9554 by loading the LR into the PC. */
9561 switch ((int) ARM_FUNC_TYPE (func_type
))
9565 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9568 case ARM_FT_INTERWORKED
:
9569 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9572 case ARM_FT_EXCEPTION
:
9573 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9577 /* Use bx if it's available. */
9578 if (arm_arch5
|| arm_arch4t
)
9579 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9581 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9585 output_asm_insn (instr
, & operand
);
9591 /* Write the function name into the code section, directly preceding
9592 the function prologue.
9594 Code will be output similar to this:
9596 .ascii "arm_poke_function_name", 0
9599 .word 0xff000000 + (t1 - t0)
9600 arm_poke_function_name
9602 stmfd sp!, {fp, ip, lr, pc}
9605 When performing a stack backtrace, code can inspect the value
9606 of 'pc' stored at 'fp' + 0. If the trace function then looks
9607 at location pc - 12 and the top 8 bits are set, then we know
9608 that there is a function name embedded immediately preceding this
9609 location and has length ((pc[-3]) & 0xff000000).
9611 We assume that pc is declared as a pointer to an unsigned long.
9613 It is of no benefit to output the function name if we are assembling
9614 a leaf function. These function types will not contain a stack
9615 backtrace structure, therefore it is not possible to determine the
9618 arm_poke_function_name (FILE *stream
, const char *name
)
9620 unsigned long alignlength
;
9621 unsigned long length
;
9624 length
= strlen (name
) + 1;
9625 alignlength
= ROUND_UP_WORD (length
);
9627 ASM_OUTPUT_ASCII (stream
, name
, length
);
9628 ASM_OUTPUT_ALIGN (stream
, 2);
9629 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9630 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9633 /* Place some comments into the assembler stream
9634 describing the current function. */
9636 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9638 unsigned long func_type
;
9642 thumb_output_function_prologue (f
, frame_size
);
9647 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9649 func_type
= arm_current_func_type ();
9651 switch ((int) ARM_FUNC_TYPE (func_type
))
9656 case ARM_FT_INTERWORKED
:
9657 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9660 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9663 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9665 case ARM_FT_EXCEPTION
:
9666 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9670 if (IS_NAKED (func_type
))
9671 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9673 if (IS_VOLATILE (func_type
))
9674 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9676 if (IS_NESTED (func_type
))
9677 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9679 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9680 current_function_args_size
,
9681 current_function_pretend_args_size
, frame_size
);
9683 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9684 frame_pointer_needed
,
9685 cfun
->machine
->uses_anonymous_args
);
9687 if (cfun
->machine
->lr_save_eliminated
)
9688 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9690 if (current_function_calls_eh_return
)
9691 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9693 #ifdef AOF_ASSEMBLER
9695 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9698 return_used_this_function
= 0;
9702 arm_output_epilogue (rtx sibling
)
9705 unsigned long saved_regs_mask
;
9706 unsigned long func_type
;
9707 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9708 frame that is $fp + 4 for a non-variadic function. */
9709 int floats_offset
= 0;
9711 FILE * f
= asm_out_file
;
9712 unsigned int lrm_count
= 0;
9713 int really_return
= (sibling
== NULL
);
9715 arm_stack_offsets
*offsets
;
9717 /* If we have already generated the return instruction
9718 then it is futile to generate anything else. */
9719 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9722 func_type
= arm_current_func_type ();
9724 if (IS_NAKED (func_type
))
9725 /* Naked functions don't have epilogues. */
9728 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9732 /* A volatile function should never return. Call abort. */
9733 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9734 assemble_external_libcall (op
);
9735 output_asm_insn ("bl\t%a0", &op
);
9740 /* If we are throwing an exception, then we really must be doing a
9741 return, so we can't tail-call. */
9742 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9744 offsets
= arm_get_frame_offsets ();
9745 saved_regs_mask
= arm_compute_save_reg_mask ();
9748 lrm_count
= bit_count (saved_regs_mask
);
9750 floats_offset
= offsets
->saved_args
;
9751 /* Compute how far away the floats will be. */
9752 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9753 if (saved_regs_mask
& (1 << reg
))
9756 if (frame_pointer_needed
)
9758 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9759 int vfp_offset
= offsets
->frame
;
9761 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9763 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9764 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9766 floats_offset
+= 12;
9767 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9768 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9773 start_reg
= LAST_FPA_REGNUM
;
9775 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9777 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9779 floats_offset
+= 12;
9781 /* We can't unstack more than four registers at once. */
9782 if (start_reg
- reg
== 3)
9784 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9785 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9786 start_reg
= reg
- 1;
9791 if (reg
!= start_reg
)
9792 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9793 reg
+ 1, start_reg
- reg
,
9794 FP_REGNUM
, floats_offset
- vfp_offset
);
9795 start_reg
= reg
- 1;
9799 /* Just in case the last register checked also needs unstacking. */
9800 if (reg
!= start_reg
)
9801 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9802 reg
+ 1, start_reg
- reg
,
9803 FP_REGNUM
, floats_offset
- vfp_offset
);
9806 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9810 /* The fldmx insn does not have base+offset addressing modes,
9811 so we use IP to hold the address. */
9812 saved_size
= arm_get_vfp_saved_size ();
9816 floats_offset
+= saved_size
;
9817 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9818 FP_REGNUM
, floats_offset
- vfp_offset
);
9820 start_reg
= FIRST_VFP_REGNUM
;
9821 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9823 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9824 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9826 if (start_reg
!= reg
)
9827 arm_output_fldmx (f
, IP_REGNUM
,
9828 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9829 (reg
- start_reg
) / 2);
9830 start_reg
= reg
+ 2;
9833 if (start_reg
!= reg
)
9834 arm_output_fldmx (f
, IP_REGNUM
,
9835 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9836 (reg
- start_reg
) / 2);
9841 /* The frame pointer is guaranteed to be non-double-word aligned.
9842 This is because it is set to (old_stack_pointer - 4) and the
9843 old_stack_pointer was double word aligned. Thus the offset to
9844 the iWMMXt registers to be loaded must also be non-double-word
9845 sized, so that the resultant address *is* double-word aligned.
9846 We can ignore floats_offset since that was already included in
9847 the live_regs_mask. */
9848 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9850 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9851 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9853 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9854 reg
, FP_REGNUM
, lrm_count
* 4);
9859 /* saved_regs_mask should contain the IP, which at the time of stack
9860 frame generation actually contains the old stack pointer. So a
9861 quick way to unwind the stack is just pop the IP register directly
9862 into the stack pointer. */
9863 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9864 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9865 saved_regs_mask
|= (1 << SP_REGNUM
);
9867 /* There are two registers left in saved_regs_mask - LR and PC. We
9868 only need to restore the LR register (the return address), but to
9869 save time we can load it directly into the PC, unless we need a
9870 special function exit sequence, or we are not really returning. */
9872 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9873 && !current_function_calls_eh_return
)
9874 /* Delete the LR from the register mask, so that the LR on
9875 the stack is loaded into the PC in the register mask. */
9876 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9878 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9880 /* We must use SP as the base register, because SP is one of the
9881 registers being restored. If an interrupt or page fault
9882 happens in the ldm instruction, the SP might or might not
9883 have been restored. That would be bad, as then SP will no
9884 longer indicate the safe area of stack, and we can get stack
9885 corruption. Using SP as the base register means that it will
9886 be reset correctly to the original value, should an interrupt
9887 occur. If the stack pointer already points at the right
9888 place, then omit the subtraction. */
9889 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9890 || current_function_calls_alloca
)
9891 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9892 4 * bit_count (saved_regs_mask
));
9893 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9895 if (IS_INTERRUPT (func_type
))
9896 /* Interrupt handlers will have pushed the
9897 IP onto the stack, so restore it now. */
9898 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9902 /* Restore stack pointer if necessary. */
9903 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9905 operands
[0] = operands
[1] = stack_pointer_rtx
;
9906 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9907 output_add_immediate (operands
);
9910 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9912 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9913 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9914 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9919 start_reg
= FIRST_FPA_REGNUM
;
9921 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9923 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9925 if (reg
- start_reg
== 3)
9927 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9928 start_reg
, SP_REGNUM
);
9929 start_reg
= reg
+ 1;
9934 if (reg
!= start_reg
)
9935 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9936 start_reg
, reg
- start_reg
,
9939 start_reg
= reg
+ 1;
9943 /* Just in case the last register checked also needs unstacking. */
9944 if (reg
!= start_reg
)
9945 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9946 start_reg
, reg
- start_reg
, SP_REGNUM
);
9949 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9951 start_reg
= FIRST_VFP_REGNUM
;
9952 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9954 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9955 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9957 if (start_reg
!= reg
)
9958 arm_output_fldmx (f
, SP_REGNUM
,
9959 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9960 (reg
- start_reg
) / 2);
9961 start_reg
= reg
+ 2;
9964 if (start_reg
!= reg
)
9965 arm_output_fldmx (f
, SP_REGNUM
,
9966 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9967 (reg
- start_reg
) / 2);
9970 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9971 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9972 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9974 /* If we can, restore the LR into the PC. */
9975 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9977 && current_function_pretend_args_size
== 0
9978 && saved_regs_mask
& (1 << LR_REGNUM
)
9979 && !current_function_calls_eh_return
)
9981 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9982 saved_regs_mask
|= (1 << PC_REGNUM
);
9985 /* Load the registers off the stack. If we only have one register
9986 to load use the LDR instruction - it is faster. */
9987 if (saved_regs_mask
== (1 << LR_REGNUM
))
9989 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9991 else if (saved_regs_mask
)
9993 if (saved_regs_mask
& (1 << SP_REGNUM
))
9994 /* Note - write back to the stack register is not enabled
9995 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9996 in the list of registers and if we add writeback the
9997 instruction becomes UNPREDICTABLE. */
9998 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
10000 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
10003 if (current_function_pretend_args_size
)
10005 /* Unwind the pre-pushed regs. */
10006 operands
[0] = operands
[1] = stack_pointer_rtx
;
10007 operands
[2] = GEN_INT (current_function_pretend_args_size
);
10008 output_add_immediate (operands
);
10012 /* We may have already restored PC directly from the stack. */
10013 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10016 /* Stack adjustment for exception handler. */
10017 if (current_function_calls_eh_return
)
10018 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10019 ARM_EH_STACKADJ_REGNUM
);
10021 /* Generate the return instruction. */
10022 switch ((int) ARM_FUNC_TYPE (func_type
))
10026 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10029 case ARM_FT_EXCEPTION
:
10030 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10033 case ARM_FT_INTERWORKED
:
10034 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10038 if (arm_arch5
|| arm_arch4t
)
10039 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10041 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10049 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10050 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10052 arm_stack_offsets
*offsets
;
10058 /* Emit any call-via-reg trampolines that are needed for v4t support
10059 of call_reg and call_value_reg type insns. */
10060 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10062 rtx label
= cfun
->machine
->call_via
[regno
];
10066 function_section (current_function_decl
);
10067 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10068 CODE_LABEL_NUMBER (label
));
10069 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10073 /* ??? Probably not safe to set this here, since it assumes that a
10074 function will be emitted as assembly immediately after we generate
10075 RTL for it. This does not happen for inline functions. */
10076 return_used_this_function
= 0;
10080 /* We need to take into account any stack-frame rounding. */
10081 offsets
= arm_get_frame_offsets ();
10083 gcc_assert (!use_return_insn (FALSE
, NULL
)
10084 || !return_used_this_function
10085 || offsets
->saved_regs
== offsets
->outgoing_args
10086 || frame_pointer_needed
);
10088 /* Reset the ARM-specific per-function variables. */
10089 after_arm_reorg
= 0;
10093 /* Generate and emit an insn that we will recognize as a push_multi.
10094 Unfortunately, since this insn does not reflect very well the actual
10095 semantics of the operation, we need to annotate the insn for the benefit
10096 of DWARF2 frame unwind information. */
10098 emit_multi_reg_push (unsigned long mask
)
10101 int num_dwarf_regs
;
10105 int dwarf_par_index
;
10108 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10109 if (mask
& (1 << i
))
10112 gcc_assert (num_regs
&& num_regs
<= 16);
10114 /* We don't record the PC in the dwarf frame information. */
10115 num_dwarf_regs
= num_regs
;
10116 if (mask
& (1 << PC_REGNUM
))
10119 /* For the body of the insn we are going to generate an UNSPEC in
10120 parallel with several USEs. This allows the insn to be recognized
10121 by the push_multi pattern in the arm.md file. The insn looks
10122 something like this:
10125 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10126 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10127 (use (reg:SI 11 fp))
10128 (use (reg:SI 12 ip))
10129 (use (reg:SI 14 lr))
10130 (use (reg:SI 15 pc))
10133 For the frame note however, we try to be more explicit and actually
10134 show each register being stored into the stack frame, plus a (single)
10135 decrement of the stack pointer. We do it this way in order to be
10136 friendly to the stack unwinding code, which only wants to see a single
10137 stack decrement per instruction. The RTL we generate for the note looks
10138 something like this:
10141 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10142 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10143 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10144 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10145 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10148 This sequence is used both by the code to support stack unwinding for
10149 exceptions handlers and the code to generate dwarf2 frame debugging. */
10151 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10152 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10153 dwarf_par_index
= 1;
10155 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10157 if (mask
& (1 << i
))
10159 reg
= gen_rtx_REG (SImode
, i
);
10161 XVECEXP (par
, 0, 0)
10162 = gen_rtx_SET (VOIDmode
,
10163 gen_frame_mem (BLKmode
,
10164 gen_rtx_PRE_DEC (BLKmode
,
10165 stack_pointer_rtx
)),
10166 gen_rtx_UNSPEC (BLKmode
,
10167 gen_rtvec (1, reg
),
10168 UNSPEC_PUSH_MULT
));
10170 if (i
!= PC_REGNUM
)
10172 tmp
= gen_rtx_SET (VOIDmode
,
10173 gen_frame_mem (SImode
, stack_pointer_rtx
),
10175 RTX_FRAME_RELATED_P (tmp
) = 1;
10176 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10184 for (j
= 1, i
++; j
< num_regs
; i
++)
10186 if (mask
& (1 << i
))
10188 reg
= gen_rtx_REG (SImode
, i
);
10190 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10192 if (i
!= PC_REGNUM
)
10195 = gen_rtx_SET (VOIDmode
,
10196 gen_frame_mem (SImode
,
10197 plus_constant (stack_pointer_rtx
,
10200 RTX_FRAME_RELATED_P (tmp
) = 1;
10201 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10208 par
= emit_insn (par
);
10210 tmp
= gen_rtx_SET (SImode
,
10212 gen_rtx_PLUS (SImode
,
10214 GEN_INT (-4 * num_regs
)));
10215 RTX_FRAME_RELATED_P (tmp
) = 1;
10216 XVECEXP (dwarf
, 0, 0) = tmp
;
10218 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10223 /* Calculate the size of the return value that is passed in registers. */
10225 arm_size_return_regs (void)
10227 enum machine_mode mode
;
10229 if (current_function_return_rtx
!= 0)
10230 mode
= GET_MODE (current_function_return_rtx
);
10232 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10234 return GET_MODE_SIZE (mode
);
10238 emit_sfm (int base_reg
, int count
)
10245 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10246 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10248 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10250 XVECEXP (par
, 0, 0)
10251 = gen_rtx_SET (VOIDmode
,
10252 gen_frame_mem (BLKmode
,
10253 gen_rtx_PRE_DEC (BLKmode
,
10254 stack_pointer_rtx
)),
10255 gen_rtx_UNSPEC (BLKmode
,
10256 gen_rtvec (1, reg
),
10257 UNSPEC_PUSH_MULT
));
10258 tmp
= gen_rtx_SET (VOIDmode
,
10259 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10260 RTX_FRAME_RELATED_P (tmp
) = 1;
10261 XVECEXP (dwarf
, 0, 1) = tmp
;
10263 for (i
= 1; i
< count
; i
++)
10265 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10266 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10268 tmp
= gen_rtx_SET (VOIDmode
,
10269 gen_frame_mem (XFmode
,
10270 plus_constant (stack_pointer_rtx
,
10273 RTX_FRAME_RELATED_P (tmp
) = 1;
10274 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10277 tmp
= gen_rtx_SET (VOIDmode
,
10279 gen_rtx_PLUS (SImode
,
10281 GEN_INT (-12 * count
)));
10282 RTX_FRAME_RELATED_P (tmp
) = 1;
10283 XVECEXP (dwarf
, 0, 0) = tmp
;
10285 par
= emit_insn (par
);
10286 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10292 /* Return true if the current function needs to save/restore LR. */
10295 thumb_force_lr_save (void)
10297 return !cfun
->machine
->lr_save_eliminated
10298 && (!leaf_function_p ()
10299 || thumb_far_jump_used_p ()
10300 || regs_ever_live
[LR_REGNUM
]);
10304 /* Compute the distance from register FROM to register TO.
10305 These can be the arg pointer (26), the soft frame pointer (25),
10306 the stack pointer (13) or the hard frame pointer (11).
10307 In thumb mode r7 is used as the soft frame pointer, if needed.
10308 Typical stack layout looks like this:
10310 old stack pointer -> | |
10313 | | saved arguments for
10314 | | vararg functions
10317 hard FP & arg pointer -> | | \
10325 soft frame pointer -> | | /
10330 locals base pointer -> | | /
10335 current stack pointer -> | | /
10338 For a given function some or all of these stack components
10339 may not be needed, giving rise to the possibility of
10340 eliminating some of the registers.
10342 The values returned by this function must reflect the behavior
10343 of arm_expand_prologue() and arm_compute_save_reg_mask().
10345 The sign of the number returned reflects the direction of stack
10346 growth, so the values are positive for all eliminations except
10347 from the soft frame pointer to the hard frame pointer.
10349 SFP may point just inside the local variables block to ensure correct
10353 /* Calculate stack offsets. These are used to calculate register elimination
10354 offsets and in prologue/epilogue code. */
10356 static arm_stack_offsets
*
10357 arm_get_frame_offsets (void)
10359 struct arm_stack_offsets
*offsets
;
10360 unsigned long func_type
;
10363 HOST_WIDE_INT frame_size
;
10365 offsets
= &cfun
->machine
->stack_offsets
;
10367 /* We need to know if we are a leaf function. Unfortunately, it
10368 is possible to be called after start_sequence has been called,
10369 which causes get_insns to return the insns for the sequence,
10370 not the function, which will cause leaf_function_p to return
10371 the incorrect result.
10373 to know about leaf functions once reload has completed, and the
10374 frame size cannot be changed after that time, so we can safely
10375 use the cached value. */
10377 if (reload_completed
)
10380 /* Initially this is the size of the local variables. It will translated
10381 into an offset once we have determined the size of preceding data. */
10382 frame_size
= ROUND_UP_WORD (get_frame_size ());
10384 leaf
= leaf_function_p ();
10386 /* Space for variadic functions. */
10387 offsets
->saved_args
= current_function_pretend_args_size
;
10389 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10393 unsigned int regno
;
10395 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10397 /* We know that SP will be doubleword aligned on entry, and we must
10398 preserve that condition at any subroutine call. We also require the
10399 soft frame pointer to be doubleword aligned. */
10401 if (TARGET_REALLY_IWMMXT
)
10403 /* Check for the call-saved iWMMXt registers. */
10404 for (regno
= FIRST_IWMMXT_REGNUM
;
10405 regno
<= LAST_IWMMXT_REGNUM
;
10407 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10411 func_type
= arm_current_func_type ();
10412 if (! IS_VOLATILE (func_type
))
10414 /* Space for saved FPA registers. */
10415 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10416 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10419 /* Space for saved VFP registers. */
10420 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10421 saved
+= arm_get_vfp_saved_size ();
10424 else /* TARGET_THUMB */
10426 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10427 if (TARGET_BACKTRACE
)
10431 /* Saved registers include the stack frame. */
10432 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10433 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10434 /* A leaf function does not need any stack alignment if it has nothing
10436 if (leaf
&& frame_size
== 0)
10438 offsets
->outgoing_args
= offsets
->soft_frame
;
10442 /* Ensure SFP has the correct alignment. */
10443 if (ARM_DOUBLEWORD_ALIGN
10444 && (offsets
->soft_frame
& 7))
10445 offsets
->soft_frame
+= 4;
10447 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10448 offsets
->outgoing_args
= (offsets
->locals_base
10449 + current_function_outgoing_args_size
);
10451 if (ARM_DOUBLEWORD_ALIGN
)
10453 /* Ensure SP remains doubleword aligned. */
10454 if (offsets
->outgoing_args
& 7)
10455 offsets
->outgoing_args
+= 4;
10456 gcc_assert (!(offsets
->outgoing_args
& 7));
10463 /* Calculate the relative offsets for the different stack pointers. Positive
10464 offsets are in the direction of stack growth. */
10467 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10469 arm_stack_offsets
*offsets
;
10471 offsets
= arm_get_frame_offsets ();
10473 /* OK, now we have enough information to compute the distances.
10474 There must be an entry in these switch tables for each pair
10475 of registers in ELIMINABLE_REGS, even if some of the entries
10476 seem to be redundant or useless. */
10479 case ARG_POINTER_REGNUM
:
10482 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10485 case FRAME_POINTER_REGNUM
:
10486 /* This is the reverse of the soft frame pointer
10487 to hard frame pointer elimination below. */
10488 return offsets
->soft_frame
- offsets
->saved_args
;
10490 case ARM_HARD_FRAME_POINTER_REGNUM
:
10491 /* If there is no stack frame then the hard
10492 frame pointer and the arg pointer coincide. */
10493 if (offsets
->frame
== offsets
->saved_regs
)
10495 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10496 return (frame_pointer_needed
10497 && cfun
->static_chain_decl
!= NULL
10498 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10500 case STACK_POINTER_REGNUM
:
10501 /* If nothing has been pushed on the stack at all
10502 then this will return -4. This *is* correct! */
10503 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10506 gcc_unreachable ();
10508 gcc_unreachable ();
10510 case FRAME_POINTER_REGNUM
:
10513 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10516 case ARM_HARD_FRAME_POINTER_REGNUM
:
10517 /* The hard frame pointer points to the top entry in the
10518 stack frame. The soft frame pointer to the bottom entry
10519 in the stack frame. If there is no stack frame at all,
10520 then they are identical. */
10522 return offsets
->frame
- offsets
->soft_frame
;
10524 case STACK_POINTER_REGNUM
:
10525 return offsets
->outgoing_args
- offsets
->soft_frame
;
10528 gcc_unreachable ();
10530 gcc_unreachable ();
10533 /* You cannot eliminate from the stack pointer.
10534 In theory you could eliminate from the hard frame
10535 pointer to the stack pointer, but this will never
10536 happen, since if a stack frame is not needed the
10537 hard frame pointer will never be used. */
10538 gcc_unreachable ();
10543 /* Generate the prologue instructions for entry into an ARM function. */
10545 arm_expand_prologue (void)
10551 unsigned long live_regs_mask
;
10552 unsigned long func_type
;
10554 int saved_pretend_args
= 0;
10555 int saved_regs
= 0;
10556 unsigned HOST_WIDE_INT args_to_push
;
10557 arm_stack_offsets
*offsets
;
10559 func_type
= arm_current_func_type ();
10561 /* Naked functions don't have prologues. */
10562 if (IS_NAKED (func_type
))
10565 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10566 args_to_push
= current_function_pretend_args_size
;
10568 /* Compute which register we will have to save onto the stack. */
10569 live_regs_mask
= arm_compute_save_reg_mask ();
10571 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10573 if (frame_pointer_needed
)
10575 if (IS_INTERRUPT (func_type
))
10577 /* Interrupt functions must not corrupt any registers.
10578 Creating a frame pointer however, corrupts the IP
10579 register, so we must push it first. */
10580 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10582 /* Do not set RTX_FRAME_RELATED_P on this insn.
10583 The dwarf stack unwinding code only wants to see one
10584 stack decrement per function, and this is not it. If
10585 this instruction is labeled as being part of the frame
10586 creation sequence then dwarf2out_frame_debug_expr will
10587 die when it encounters the assignment of IP to FP
10588 later on, since the use of SP here establishes SP as
10589 the CFA register and not IP.
10591 Anyway this instruction is not really part of the stack
10592 frame creation although it is part of the prologue. */
10594 else if (IS_NESTED (func_type
))
10596 /* The Static chain register is the same as the IP register
10597 used as a scratch register during stack frame creation.
10598 To get around this need to find somewhere to store IP
10599 whilst the frame is being created. We try the following
10602 1. The last argument register.
10603 2. A slot on the stack above the frame. (This only
10604 works if the function is not a varargs function).
10605 3. Register r3, after pushing the argument registers
10608 Note - we only need to tell the dwarf2 backend about the SP
10609 adjustment in the second variant; the static chain register
10610 doesn't need to be unwound, as it doesn't contain a value
10611 inherited from the caller. */
10613 if (regs_ever_live
[3] == 0)
10615 insn
= gen_rtx_REG (SImode
, 3);
10616 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10617 insn
= emit_insn (insn
);
10619 else if (args_to_push
== 0)
10622 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10623 insn
= gen_frame_mem (SImode
, insn
);
10624 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10625 insn
= emit_insn (insn
);
10629 /* Just tell the dwarf backend that we adjusted SP. */
10630 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10631 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10632 GEN_INT (-fp_offset
)));
10633 RTX_FRAME_RELATED_P (insn
) = 1;
10634 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10635 dwarf
, REG_NOTES (insn
));
10639 /* Store the args on the stack. */
10640 if (cfun
->machine
->uses_anonymous_args
)
10641 insn
= emit_multi_reg_push
10642 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10645 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10646 GEN_INT (- args_to_push
)));
10648 RTX_FRAME_RELATED_P (insn
) = 1;
10650 saved_pretend_args
= 1;
10651 fp_offset
= args_to_push
;
10654 /* Now reuse r3 to preserve IP. */
10655 insn
= gen_rtx_REG (SImode
, 3);
10656 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10657 (void) emit_insn (insn
);
10663 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10664 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10667 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10669 insn
= emit_insn (insn
);
10670 RTX_FRAME_RELATED_P (insn
) = 1;
10675 /* Push the argument registers, or reserve space for them. */
10676 if (cfun
->machine
->uses_anonymous_args
)
10677 insn
= emit_multi_reg_push
10678 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10681 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10682 GEN_INT (- args_to_push
)));
10683 RTX_FRAME_RELATED_P (insn
) = 1;
10686 /* If this is an interrupt service routine, and the link register
10687 is going to be pushed, and we are not creating a stack frame,
10688 (which would involve an extra push of IP and a pop in the epilogue)
10689 subtracting four from LR now will mean that the function return
10690 can be done with a single instruction. */
10691 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10692 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10693 && ! frame_pointer_needed
)
10694 emit_insn (gen_rtx_SET (SImode
,
10695 gen_rtx_REG (SImode
, LR_REGNUM
),
10696 gen_rtx_PLUS (SImode
,
10697 gen_rtx_REG (SImode
, LR_REGNUM
),
10700 if (live_regs_mask
)
10702 insn
= emit_multi_reg_push (live_regs_mask
);
10703 saved_regs
+= bit_count (live_regs_mask
) * 4;
10704 RTX_FRAME_RELATED_P (insn
) = 1;
10708 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10709 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10711 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10712 insn
= gen_frame_mem (V2SImode
, insn
);
10713 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10714 gen_rtx_REG (V2SImode
, reg
)));
10715 RTX_FRAME_RELATED_P (insn
) = 1;
10719 if (! IS_VOLATILE (func_type
))
10723 /* Save any floating point call-saved registers used by this
10725 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10727 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10728 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10730 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10731 insn
= gen_frame_mem (XFmode
, insn
);
10732 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10733 gen_rtx_REG (XFmode
, reg
)));
10734 RTX_FRAME_RELATED_P (insn
) = 1;
10740 start_reg
= LAST_FPA_REGNUM
;
10742 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10744 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10746 if (start_reg
- reg
== 3)
10748 insn
= emit_sfm (reg
, 4);
10749 RTX_FRAME_RELATED_P (insn
) = 1;
10751 start_reg
= reg
- 1;
10756 if (start_reg
!= reg
)
10758 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10759 RTX_FRAME_RELATED_P (insn
) = 1;
10760 saved_regs
+= (start_reg
- reg
) * 12;
10762 start_reg
= reg
- 1;
10766 if (start_reg
!= reg
)
10768 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10769 saved_regs
+= (start_reg
- reg
) * 12;
10770 RTX_FRAME_RELATED_P (insn
) = 1;
10773 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10775 start_reg
= FIRST_VFP_REGNUM
;
10777 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10779 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10780 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10782 if (start_reg
!= reg
)
10783 saved_regs
+= vfp_emit_fstmx (start_reg
,
10784 (reg
- start_reg
) / 2);
10785 start_reg
= reg
+ 2;
10788 if (start_reg
!= reg
)
10789 saved_regs
+= vfp_emit_fstmx (start_reg
,
10790 (reg
- start_reg
) / 2);
10794 if (frame_pointer_needed
)
10796 /* Create the new frame pointer. */
10797 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10798 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10799 RTX_FRAME_RELATED_P (insn
) = 1;
10801 if (IS_NESTED (func_type
))
10803 /* Recover the static chain register. */
10804 if (regs_ever_live
[3] == 0
10805 || saved_pretend_args
)
10806 insn
= gen_rtx_REG (SImode
, 3);
10807 else /* if (current_function_pretend_args_size == 0) */
10809 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10811 insn
= gen_frame_mem (SImode
, insn
);
10814 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10815 /* Add a USE to stop propagate_one_insn() from barfing. */
10816 emit_insn (gen_prologue_use (ip_rtx
));
10820 offsets
= arm_get_frame_offsets ();
10821 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10823 /* This add can produce multiple insns for a large constant, so we
10824 need to get tricky. */
10825 rtx last
= get_last_insn ();
10827 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10828 - offsets
->outgoing_args
);
10830 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10834 last
= last
? NEXT_INSN (last
) : get_insns ();
10835 RTX_FRAME_RELATED_P (last
) = 1;
10837 while (last
!= insn
);
10839 /* If the frame pointer is needed, emit a special barrier that
10840 will prevent the scheduler from moving stores to the frame
10841 before the stack adjustment. */
10842 if (frame_pointer_needed
)
10843 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10844 hard_frame_pointer_rtx
));
10849 arm_load_pic_register (0UL);
10851 /* If we are profiling, make sure no instructions are scheduled before
10852 the call to mcount. Similarly if the user has requested no
10853 scheduling in the prolog. Similarly if we want non-call exceptions
10854 using the EABI unwinder, to prevent faulting instructions from being
10855 swapped with a stack adjustment. */
10856 if (current_function_profile
|| !TARGET_SCHED_PROLOG
10857 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
10858 emit_insn (gen_blockage ());
10860 /* If the link register is being kept alive, with the return address in it,
10861 then make sure that it does not get reused by the ce2 pass. */
10862 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10864 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10865 cfun
->machine
->lr_save_eliminated
= 1;
10869 /* If CODE is 'd', then the X is a condition operand and the instruction
10870 should only be executed if the condition is true.
10871 if CODE is 'D', then the X is a condition operand and the instruction
10872 should only be executed if the condition is false: however, if the mode
10873 of the comparison is CCFPEmode, then always execute the instruction -- we
10874 do this because in these circumstances !GE does not necessarily imply LT;
10875 in these cases the instruction pattern will take care to make sure that
10876 an instruction containing %d will follow, thereby undoing the effects of
10877 doing this instruction unconditionally.
10878 If CODE is 'N' then X is a floating point operand that must be negated
10880 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10881 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10883 arm_print_operand (FILE *stream
, rtx x
, int code
)
10888 fputs (ASM_COMMENT_START
, stream
);
10892 fputs (user_label_prefix
, stream
);
10896 fputs (REGISTER_PREFIX
, stream
);
10900 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10904 output_operand_lossage ("predicated Thumb instruction");
10907 if (current_insn_predicate
!= NULL
)
10909 output_operand_lossage
10910 ("predicated instruction in conditional sequence");
10914 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10916 else if (current_insn_predicate
)
10918 enum arm_cond_code code
;
10922 output_operand_lossage ("predicated Thumb instruction");
10926 code
= get_arm_condition_code (current_insn_predicate
);
10927 fputs (arm_condition_codes
[code
], stream
);
10934 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10935 r
= REAL_VALUE_NEGATE (r
);
10936 fprintf (stream
, "%s", fp_const_from_val (&r
));
10941 if (GET_CODE (x
) == CONST_INT
)
10944 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10945 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10949 putc ('~', stream
);
10950 output_addr_const (stream
, x
);
10955 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10958 /* Truncate Cirrus shift counts. */
10960 if (GET_CODE (x
) == CONST_INT
)
10962 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10965 arm_print_operand (stream
, x
, 0);
10969 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10975 const char * shift
= shift_op (x
, &val
);
10979 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10981 arm_print_operand (stream
, XEXP (x
, 1), 0);
10983 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10988 /* An explanation of the 'Q', 'R' and 'H' register operands:
10990 In a pair of registers containing a DI or DF value the 'Q'
10991 operand returns the register number of the register containing
10992 the least significant part of the value. The 'R' operand returns
10993 the register number of the register containing the most
10994 significant part of the value.
10996 The 'H' operand returns the higher of the two register numbers.
10997 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10998 same as the 'Q' operand, since the most significant part of the
10999 value is held in the lower number register. The reverse is true
11000 on systems where WORDS_BIG_ENDIAN is false.
11002 The purpose of these operands is to distinguish between cases
11003 where the endian-ness of the values is important (for example
11004 when they are added together), and cases where the endian-ness
11005 is irrelevant, but the order of register operations is important.
11006 For example when loading a value from memory into a register
11007 pair, the endian-ness does not matter. Provided that the value
11008 from the lower memory address is put into the lower numbered
11009 register, and the value from the higher address is put into the
11010 higher numbered register, the load will work regardless of whether
11011 the value being loaded is big-wordian or little-wordian. The
11012 order of the two register loads can matter however, if the address
11013 of the memory location is actually held in one of the registers
11014 being overwritten by the load. */
11016 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11018 output_operand_lossage ("invalid operand for code '%c'", code
);
11022 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11026 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11028 output_operand_lossage ("invalid operand for code '%c'", code
);
11032 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11036 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11038 output_operand_lossage ("invalid operand for code '%c'", code
);
11042 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11046 asm_fprintf (stream
, "%r",
11047 GET_CODE (XEXP (x
, 0)) == REG
11048 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11052 asm_fprintf (stream
, "{%r-%r}",
11054 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11058 /* CONST_TRUE_RTX means always -- that's the default. */
11059 if (x
== const_true_rtx
)
11062 if (!COMPARISON_P (x
))
11064 output_operand_lossage ("invalid operand for code '%c'", code
);
11068 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11073 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11074 want to do that. */
11075 if (x
== const_true_rtx
)
11077 output_operand_lossage ("instruction never exectued");
11080 if (!COMPARISON_P (x
))
11082 output_operand_lossage ("invalid operand for code '%c'", code
);
11086 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11087 (get_arm_condition_code (x
))],
11091 /* Cirrus registers can be accessed in a variety of ways:
11092 single floating point (f)
11093 double floating point (d)
11095 64bit integer (dx). */
11096 case 'W': /* Cirrus register in F mode. */
11097 case 'X': /* Cirrus register in D mode. */
11098 case 'Y': /* Cirrus register in FX mode. */
11099 case 'Z': /* Cirrus register in DX mode. */
11100 gcc_assert (GET_CODE (x
) == REG
11101 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11103 fprintf (stream
, "mv%s%s",
11105 : code
== 'X' ? "d"
11106 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11110 /* Print cirrus register in the mode specified by the register's mode. */
11113 int mode
= GET_MODE (x
);
11115 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11117 output_operand_lossage ("invalid operand for code '%c'", code
);
11121 fprintf (stream
, "mv%s%s",
11122 mode
== DFmode
? "d"
11123 : mode
== SImode
? "fx"
11124 : mode
== DImode
? "dx"
11125 : "f", reg_names
[REGNO (x
)] + 2);
11131 if (GET_CODE (x
) != REG
11132 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11133 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11134 /* Bad value for wCG register number. */
11136 output_operand_lossage ("invalid operand for code '%c'", code
);
11141 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11144 /* Print an iWMMXt control register name. */
11146 if (GET_CODE (x
) != CONST_INT
11148 || INTVAL (x
) >= 16)
11149 /* Bad value for wC register number. */
11151 output_operand_lossage ("invalid operand for code '%c'", code
);
11157 static const char * wc_reg_names
[16] =
11159 "wCID", "wCon", "wCSSF", "wCASF",
11160 "wC4", "wC5", "wC6", "wC7",
11161 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11162 "wC12", "wC13", "wC14", "wC15"
11165 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11169 /* Print a VFP double precision register name. */
11172 int mode
= GET_MODE (x
);
11175 if (mode
!= DImode
&& mode
!= DFmode
)
11177 output_operand_lossage ("invalid operand for code '%c'", code
);
11181 if (GET_CODE (x
) != REG
11182 || !IS_VFP_REGNUM (REGNO (x
)))
11184 output_operand_lossage ("invalid operand for code '%c'", code
);
11188 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11191 output_operand_lossage ("invalid operand for code '%c'", code
);
11195 fprintf (stream
, "d%d", num
>> 1);
11202 output_operand_lossage ("missing operand");
11206 switch (GET_CODE (x
))
11209 asm_fprintf (stream
, "%r", REGNO (x
));
11213 output_memory_reference_mode
= GET_MODE (x
);
11214 output_address (XEXP (x
, 0));
11218 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11222 gcc_assert (GET_CODE (x
) != NEG
);
11223 fputc ('#', stream
);
11224 output_addr_const (stream
, x
);
11230 #ifndef AOF_ASSEMBLER
11231 /* Target hook for assembling integer objects. The ARM version needs to
11232 handle word-sized values specially. */
11234 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11236 if (size
== UNITS_PER_WORD
&& aligned_p
)
11238 fputs ("\t.word\t", asm_out_file
);
11239 output_addr_const (asm_out_file
, x
);
11241 /* Mark symbols as position independent. We only do this in the
11242 .text segment, not in the .data segment. */
11243 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11244 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11246 if (GET_CODE (x
) == SYMBOL_REF
11247 && (CONSTANT_POOL_ADDRESS_P (x
)
11248 || SYMBOL_REF_LOCAL_P (x
)))
11249 fputs ("(GOTOFF)", asm_out_file
);
11250 else if (GET_CODE (x
) == LABEL_REF
)
11251 fputs ("(GOTOFF)", asm_out_file
);
11253 fputs ("(GOT)", asm_out_file
);
11255 fputc ('\n', asm_out_file
);
11259 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11263 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11265 units
= CONST_VECTOR_NUNITS (x
);
11267 switch (GET_MODE (x
))
11269 case V2SImode
: size
= 4; break;
11270 case V4HImode
: size
= 2; break;
11271 case V8QImode
: size
= 1; break;
11273 gcc_unreachable ();
11276 for (i
= 0; i
< units
; i
++)
11280 elt
= CONST_VECTOR_ELT (x
, i
);
11282 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11288 return default_assemble_integer (x
, size
, aligned_p
);
11292 /* Add a function to the list of static constructors. */
11295 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
11297 if (!TARGET_AAPCS_BASED
)
11299 default_named_section_asm_out_constructor (symbol
, priority
);
11303 /* Put these in the .init_array section, using a special relocation. */
11305 assemble_align (POINTER_SIZE
);
11306 fputs ("\t.word\t", asm_out_file
);
11307 output_addr_const (asm_out_file
, symbol
);
11308 fputs ("(target1)\n", asm_out_file
);
11312 /* A finite state machine takes care of noticing whether or not instructions
11313 can be conditionally executed, and thus decrease execution time and code
11314 size by deleting branch instructions. The fsm is controlled by
11315 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11317 /* The state of the fsm controlling condition codes are:
11318 0: normal, do nothing special
11319 1: make ASM_OUTPUT_OPCODE not output this instruction
11320 2: make ASM_OUTPUT_OPCODE not output this instruction
11321 3: make instructions conditional
11322 4: make instructions conditional
11324 State transitions (state->state by whom under condition):
11325 0 -> 1 final_prescan_insn if the `target' is a label
11326 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11327 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11328 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11329 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11330 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11331 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11332 (the target insn is arm_target_insn).
11334 If the jump clobbers the conditions then we use states 2 and 4.
11336 A similar thing can be done with conditional return insns.
11338 XXX In case the `target' is an unconditional branch, this conditionalising
11339 of the instructions always reduces code size, but not always execution
11340 time. But then, I want to reduce the code size to somewhere near what
11341 /bin/cc produces. */
11343 /* Returns the index of the ARM condition code string in
11344 `arm_condition_codes'. COMPARISON should be an rtx like
11345 `(eq (...) (...))'. */
11346 static enum arm_cond_code
11347 get_arm_condition_code (rtx comparison
)
11349 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11351 enum rtx_code comp_code
= GET_CODE (comparison
);
11353 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11354 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11355 XEXP (comparison
, 1));
11359 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11360 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11361 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11362 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11363 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11364 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11365 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11366 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11367 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11368 case CC_DLTUmode
: code
= ARM_CC
;
11371 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11373 if (comp_code
== EQ
)
11374 return ARM_INVERSE_CONDITION_CODE (code
);
11380 case NE
: return ARM_NE
;
11381 case EQ
: return ARM_EQ
;
11382 case GE
: return ARM_PL
;
11383 case LT
: return ARM_MI
;
11384 default: gcc_unreachable ();
11390 case NE
: return ARM_NE
;
11391 case EQ
: return ARM_EQ
;
11392 default: gcc_unreachable ();
11398 case NE
: return ARM_MI
;
11399 case EQ
: return ARM_PL
;
11400 default: gcc_unreachable ();
11405 /* These encodings assume that AC=1 in the FPA system control
11406 byte. This allows us to handle all cases except UNEQ and
11410 case GE
: return ARM_GE
;
11411 case GT
: return ARM_GT
;
11412 case LE
: return ARM_LS
;
11413 case LT
: return ARM_MI
;
11414 case NE
: return ARM_NE
;
11415 case EQ
: return ARM_EQ
;
11416 case ORDERED
: return ARM_VC
;
11417 case UNORDERED
: return ARM_VS
;
11418 case UNLT
: return ARM_LT
;
11419 case UNLE
: return ARM_LE
;
11420 case UNGT
: return ARM_HI
;
11421 case UNGE
: return ARM_PL
;
11422 /* UNEQ and LTGT do not have a representation. */
11423 case UNEQ
: /* Fall through. */
11424 case LTGT
: /* Fall through. */
11425 default: gcc_unreachable ();
11431 case NE
: return ARM_NE
;
11432 case EQ
: return ARM_EQ
;
11433 case GE
: return ARM_LE
;
11434 case GT
: return ARM_LT
;
11435 case LE
: return ARM_GE
;
11436 case LT
: return ARM_GT
;
11437 case GEU
: return ARM_LS
;
11438 case GTU
: return ARM_CC
;
11439 case LEU
: return ARM_CS
;
11440 case LTU
: return ARM_HI
;
11441 default: gcc_unreachable ();
11447 case LTU
: return ARM_CS
;
11448 case GEU
: return ARM_CC
;
11449 default: gcc_unreachable ();
11455 case NE
: return ARM_NE
;
11456 case EQ
: return ARM_EQ
;
11457 case GE
: return ARM_GE
;
11458 case GT
: return ARM_GT
;
11459 case LE
: return ARM_LE
;
11460 case LT
: return ARM_LT
;
11461 case GEU
: return ARM_CS
;
11462 case GTU
: return ARM_HI
;
11463 case LEU
: return ARM_LS
;
11464 case LTU
: return ARM_CC
;
11465 default: gcc_unreachable ();
11468 default: gcc_unreachable ();
11473 arm_final_prescan_insn (rtx insn
)
11475 /* BODY will hold the body of INSN. */
11476 rtx body
= PATTERN (insn
);
11478 /* This will be 1 if trying to repeat the trick, and things need to be
11479 reversed if it appears to fail. */
11482 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11483 taken are clobbered, even if the rtl suggests otherwise. It also
11484 means that we have to grub around within the jump expression to find
11485 out what the conditions are when the jump isn't taken. */
11486 int jump_clobbers
= 0;
11488 /* If we start with a return insn, we only succeed if we find another one. */
11489 int seeking_return
= 0;
11491 /* START_INSN will hold the insn from where we start looking. This is the
11492 first insn after the following code_label if REVERSE is true. */
11493 rtx start_insn
= insn
;
11495 /* If in state 4, check if the target branch is reached, in order to
11496 change back to state 0. */
11497 if (arm_ccfsm_state
== 4)
11499 if (insn
== arm_target_insn
)
11501 arm_target_insn
= NULL
;
11502 arm_ccfsm_state
= 0;
11507 /* If in state 3, it is possible to repeat the trick, if this insn is an
11508 unconditional branch to a label, and immediately following this branch
11509 is the previous target label which is only used once, and the label this
11510 branch jumps to is not too far off. */
11511 if (arm_ccfsm_state
== 3)
11513 if (simplejump_p (insn
))
11515 start_insn
= next_nonnote_insn (start_insn
);
11516 if (GET_CODE (start_insn
) == BARRIER
)
11518 /* XXX Isn't this always a barrier? */
11519 start_insn
= next_nonnote_insn (start_insn
);
11521 if (GET_CODE (start_insn
) == CODE_LABEL
11522 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11523 && LABEL_NUSES (start_insn
) == 1)
11528 else if (GET_CODE (body
) == RETURN
)
11530 start_insn
= next_nonnote_insn (start_insn
);
11531 if (GET_CODE (start_insn
) == BARRIER
)
11532 start_insn
= next_nonnote_insn (start_insn
);
11533 if (GET_CODE (start_insn
) == CODE_LABEL
11534 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11535 && LABEL_NUSES (start_insn
) == 1)
11538 seeking_return
= 1;
11547 gcc_assert (!arm_ccfsm_state
|| reverse
);
11548 if (GET_CODE (insn
) != JUMP_INSN
)
11551 /* This jump might be paralleled with a clobber of the condition codes
11552 the jump should always come first */
11553 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11554 body
= XVECEXP (body
, 0, 0);
11557 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11558 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11561 int fail
= FALSE
, succeed
= FALSE
;
11562 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11563 int then_not_else
= TRUE
;
11564 rtx this_insn
= start_insn
, label
= 0;
11566 /* If the jump cannot be done with one instruction, we cannot
11567 conditionally execute the instruction in the inverse case. */
11568 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11574 /* Register the insn jumped to. */
11577 if (!seeking_return
)
11578 label
= XEXP (SET_SRC (body
), 0);
11580 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11581 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11582 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11584 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11585 then_not_else
= FALSE
;
11587 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11588 seeking_return
= 1;
11589 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11591 seeking_return
= 1;
11592 then_not_else
= FALSE
;
11595 gcc_unreachable ();
11597 /* See how many insns this branch skips, and what kind of insns. If all
11598 insns are okay, and the label or unconditional branch to the same
11599 label is not too far away, succeed. */
11600 for (insns_skipped
= 0;
11601 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11605 this_insn
= next_nonnote_insn (this_insn
);
11609 switch (GET_CODE (this_insn
))
11612 /* Succeed if it is the target label, otherwise fail since
11613 control falls in from somewhere else. */
11614 if (this_insn
== label
)
11618 arm_ccfsm_state
= 2;
11619 this_insn
= next_nonnote_insn (this_insn
);
11622 arm_ccfsm_state
= 1;
11630 /* Succeed if the following insn is the target label.
11632 If return insns are used then the last insn in a function
11633 will be a barrier. */
11634 this_insn
= next_nonnote_insn (this_insn
);
11635 if (this_insn
&& this_insn
== label
)
11639 arm_ccfsm_state
= 2;
11640 this_insn
= next_nonnote_insn (this_insn
);
11643 arm_ccfsm_state
= 1;
11651 /* The AAPCS says that conditional calls should not be
11652 used since they make interworking inefficient (the
11653 linker can't transform BL<cond> into BLX). That's
11654 only a problem if the machine has BLX. */
11661 /* Succeed if the following insn is the target label, or
11662 if the following two insns are a barrier and the
11664 this_insn
= next_nonnote_insn (this_insn
);
11665 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11666 this_insn
= next_nonnote_insn (this_insn
);
11668 if (this_insn
&& this_insn
== label
11669 && insns_skipped
< max_insns_skipped
)
11673 arm_ccfsm_state
= 2;
11674 this_insn
= next_nonnote_insn (this_insn
);
11677 arm_ccfsm_state
= 1;
11685 /* If this is an unconditional branch to the same label, succeed.
11686 If it is to another label, do nothing. If it is conditional,
11688 /* XXX Probably, the tests for SET and the PC are
11691 scanbody
= PATTERN (this_insn
);
11692 if (GET_CODE (scanbody
) == SET
11693 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11695 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11696 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11698 arm_ccfsm_state
= 2;
11701 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11704 /* Fail if a conditional return is undesirable (e.g. on a
11705 StrongARM), but still allow this if optimizing for size. */
11706 else if (GET_CODE (scanbody
) == RETURN
11707 && !use_return_insn (TRUE
, NULL
)
11710 else if (GET_CODE (scanbody
) == RETURN
11713 arm_ccfsm_state
= 2;
11716 else if (GET_CODE (scanbody
) == PARALLEL
)
11718 switch (get_attr_conds (this_insn
))
11728 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11733 /* Instructions using or affecting the condition codes make it
11735 scanbody
= PATTERN (this_insn
);
11736 if (!(GET_CODE (scanbody
) == SET
11737 || GET_CODE (scanbody
) == PARALLEL
)
11738 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11741 /* A conditional cirrus instruction must be followed by
11742 a non Cirrus instruction. However, since we
11743 conditionalize instructions in this function and by
11744 the time we get here we can't add instructions
11745 (nops), because shorten_branches() has already been
11746 called, we will disable conditionalizing Cirrus
11747 instructions to be safe. */
11748 if (GET_CODE (scanbody
) != USE
11749 && GET_CODE (scanbody
) != CLOBBER
11750 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11760 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11761 arm_target_label
= CODE_LABEL_NUMBER (label
);
11764 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11766 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11768 this_insn
= next_nonnote_insn (this_insn
);
11769 gcc_assert (!this_insn
11770 || (GET_CODE (this_insn
) != BARRIER
11771 && GET_CODE (this_insn
) != CODE_LABEL
));
11775 /* Oh, dear! we ran off the end.. give up. */
11776 recog (PATTERN (insn
), insn
, NULL
);
11777 arm_ccfsm_state
= 0;
11778 arm_target_insn
= NULL
;
11781 arm_target_insn
= this_insn
;
11785 gcc_assert (!reverse
);
11787 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11789 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11790 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11791 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11792 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11796 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11799 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11803 if (reverse
|| then_not_else
)
11804 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11807 /* Restore recog_data (getting the attributes of other insns can
11808 destroy this array, but final.c assumes that it remains intact
11809 across this call; since the insn has been recognized already we
11810 call recog direct). */
11811 recog (PATTERN (insn
), insn
, NULL
);
11815 /* Returns true if REGNO is a valid register
11816 for holding a quantity of type MODE. */
11818 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11820 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11821 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11824 /* For the Thumb we only allow values bigger than SImode in
11825 registers 0 - 6, so that there is always a second low
11826 register available to hold the upper part of the value.
11827 We probably we ought to ensure that the register is the
11828 start of an even numbered register pair. */
11829 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11831 if (IS_CIRRUS_REGNUM (regno
))
11832 /* We have outlawed SI values in Cirrus registers because they
11833 reside in the lower 32 bits, but SF values reside in the
11834 upper 32 bits. This causes gcc all sorts of grief. We can't
11835 even split the registers into pairs because Cirrus SI values
11836 get sign extended to 64bits-- aldyh. */
11837 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11839 if (IS_VFP_REGNUM (regno
))
11841 if (mode
== SFmode
|| mode
== SImode
)
11844 /* DFmode values are only valid in even register pairs. */
11845 if (mode
== DFmode
)
11846 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11850 if (IS_IWMMXT_GR_REGNUM (regno
))
11851 return mode
== SImode
;
11853 if (IS_IWMMXT_REGNUM (regno
))
11854 return VALID_IWMMXT_REG_MODE (mode
);
11856 /* We allow any value to be stored in the general registers.
11857 Restrict doubleword quantities to even register pairs so that we can
11859 if (regno
<= LAST_ARM_REGNUM
)
11860 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11862 if ( regno
== FRAME_POINTER_REGNUM
11863 || regno
== ARG_POINTER_REGNUM
)
11864 /* We only allow integers in the fake hard registers. */
11865 return GET_MODE_CLASS (mode
) == MODE_INT
;
11867 /* The only registers left are the FPA registers
11868 which we only allow to hold FP values. */
11869 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11870 && regno
>= FIRST_FPA_REGNUM
11871 && regno
<= LAST_FPA_REGNUM
;
11875 arm_regno_class (int regno
)
11879 if (regno
== STACK_POINTER_REGNUM
)
11881 if (regno
== CC_REGNUM
)
11888 if ( regno
<= LAST_ARM_REGNUM
11889 || regno
== FRAME_POINTER_REGNUM
11890 || regno
== ARG_POINTER_REGNUM
)
11891 return GENERAL_REGS
;
11893 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11896 if (IS_CIRRUS_REGNUM (regno
))
11897 return CIRRUS_REGS
;
11899 if (IS_VFP_REGNUM (regno
))
11902 if (IS_IWMMXT_REGNUM (regno
))
11903 return IWMMXT_REGS
;
11905 if (IS_IWMMXT_GR_REGNUM (regno
))
11906 return IWMMXT_GR_REGS
;
11911 /* Handle a special case when computing the offset
11912 of an argument from the frame pointer. */
11914 arm_debugger_arg_offset (int value
, rtx addr
)
11918 /* We are only interested if dbxout_parms() failed to compute the offset. */
11922 /* We can only cope with the case where the address is held in a register. */
11923 if (GET_CODE (addr
) != REG
)
11926 /* If we are using the frame pointer to point at the argument, then
11927 an offset of 0 is correct. */
11928 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11931 /* If we are using the stack pointer to point at the
11932 argument, then an offset of 0 is correct. */
11933 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11934 && REGNO (addr
) == SP_REGNUM
)
11937 /* Oh dear. The argument is pointed to by a register rather
11938 than being held in a register, or being stored at a known
11939 offset from the frame pointer. Since GDB only understands
11940 those two kinds of argument we must translate the address
11941 held in the register into an offset from the frame pointer.
11942 We do this by searching through the insns for the function
11943 looking to see where this register gets its value. If the
11944 register is initialized from the frame pointer plus an offset
11945 then we are in luck and we can continue, otherwise we give up.
11947 This code is exercised by producing debugging information
11948 for a function with arguments like this:
11950 double func (double a, double b, int c, double d) {return d;}
11952 Without this code the stab for parameter 'd' will be set to
11953 an offset of 0 from the frame pointer, rather than 8. */
11955 /* The if() statement says:
11957 If the insn is a normal instruction
11958 and if the insn is setting the value in a register
11959 and if the register being set is the register holding the address of the argument
11960 and if the address is computing by an addition
11961 that involves adding to a register
11962 which is the frame pointer
11967 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11969 if ( GET_CODE (insn
) == INSN
11970 && GET_CODE (PATTERN (insn
)) == SET
11971 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11972 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11973 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11974 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11975 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11978 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11987 warning (0, "unable to compute real location of stacked parameter");
11988 value
= 8; /* XXX magic hack */
11994 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11997 if ((MASK) & insn_flags) \
11998 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11999 BUILT_IN_MD, NULL, NULL_TREE); \
12003 struct builtin_description
12005 const unsigned int mask
;
12006 const enum insn_code icode
;
12007 const char * const name
;
12008 const enum arm_builtins code
;
12009 const enum rtx_code comparison
;
12010 const unsigned int flag
;
12013 static const struct builtin_description bdesc_2arg
[] =
12015 #define IWMMXT_BUILTIN(code, string, builtin) \
12016 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12017 ARM_BUILTIN_##builtin, 0, 0 },
12019 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12020 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12021 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12022 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12023 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12024 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12025 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12026 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12027 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12028 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12029 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12030 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12031 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12032 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12033 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12034 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12035 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12036 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12037 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12038 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12039 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12040 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12041 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12042 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12043 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12044 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12045 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12046 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12047 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12048 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12049 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12050 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12051 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12052 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12053 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12054 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12055 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12056 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12057 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12058 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12059 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12060 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12061 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12062 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12063 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12064 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12065 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12066 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12067 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12068 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12069 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12070 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12071 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12072 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12073 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12074 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12075 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12076 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12078 #define IWMMXT_BUILTIN2(code, builtin) \
12079 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12081 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12082 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12083 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12084 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12085 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12086 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12087 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12088 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12089 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12090 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12091 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12092 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12093 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12094 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12095 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12096 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12097 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12098 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12099 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12100 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12101 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12102 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12103 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12104 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12105 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12106 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12107 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12108 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12109 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12110 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12111 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12112 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12115 static const struct builtin_description bdesc_1arg
[] =
12117 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12118 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12119 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12120 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12121 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12122 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12123 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12124 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12125 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12126 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12127 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12128 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12129 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12130 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12131 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12132 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12133 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12134 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12137 /* Set up all the iWMMXt builtins. This is
12138 not called if TARGET_IWMMXT is zero. */
12141 arm_init_iwmmxt_builtins (void)
12143 const struct builtin_description
* d
;
12145 tree endlink
= void_list_node
;
12147 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12148 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12149 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12152 = build_function_type (integer_type_node
,
12153 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12154 tree v8qi_ftype_v8qi_v8qi_int
12155 = build_function_type (V8QI_type_node
,
12156 tree_cons (NULL_TREE
, V8QI_type_node
,
12157 tree_cons (NULL_TREE
, V8QI_type_node
,
12158 tree_cons (NULL_TREE
,
12161 tree v4hi_ftype_v4hi_int
12162 = build_function_type (V4HI_type_node
,
12163 tree_cons (NULL_TREE
, V4HI_type_node
,
12164 tree_cons (NULL_TREE
, integer_type_node
,
12166 tree v2si_ftype_v2si_int
12167 = build_function_type (V2SI_type_node
,
12168 tree_cons (NULL_TREE
, V2SI_type_node
,
12169 tree_cons (NULL_TREE
, integer_type_node
,
12171 tree v2si_ftype_di_di
12172 = build_function_type (V2SI_type_node
,
12173 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12174 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12176 tree di_ftype_di_int
12177 = build_function_type (long_long_integer_type_node
,
12178 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12179 tree_cons (NULL_TREE
, integer_type_node
,
12181 tree di_ftype_di_int_int
12182 = build_function_type (long_long_integer_type_node
,
12183 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12184 tree_cons (NULL_TREE
, integer_type_node
,
12185 tree_cons (NULL_TREE
,
12188 tree int_ftype_v8qi
12189 = build_function_type (integer_type_node
,
12190 tree_cons (NULL_TREE
, V8QI_type_node
,
12192 tree int_ftype_v4hi
12193 = build_function_type (integer_type_node
,
12194 tree_cons (NULL_TREE
, V4HI_type_node
,
12196 tree int_ftype_v2si
12197 = build_function_type (integer_type_node
,
12198 tree_cons (NULL_TREE
, V2SI_type_node
,
12200 tree int_ftype_v8qi_int
12201 = build_function_type (integer_type_node
,
12202 tree_cons (NULL_TREE
, V8QI_type_node
,
12203 tree_cons (NULL_TREE
, integer_type_node
,
12205 tree int_ftype_v4hi_int
12206 = build_function_type (integer_type_node
,
12207 tree_cons (NULL_TREE
, V4HI_type_node
,
12208 tree_cons (NULL_TREE
, integer_type_node
,
12210 tree int_ftype_v2si_int
12211 = build_function_type (integer_type_node
,
12212 tree_cons (NULL_TREE
, V2SI_type_node
,
12213 tree_cons (NULL_TREE
, integer_type_node
,
12215 tree v8qi_ftype_v8qi_int_int
12216 = build_function_type (V8QI_type_node
,
12217 tree_cons (NULL_TREE
, V8QI_type_node
,
12218 tree_cons (NULL_TREE
, integer_type_node
,
12219 tree_cons (NULL_TREE
,
12222 tree v4hi_ftype_v4hi_int_int
12223 = build_function_type (V4HI_type_node
,
12224 tree_cons (NULL_TREE
, V4HI_type_node
,
12225 tree_cons (NULL_TREE
, integer_type_node
,
12226 tree_cons (NULL_TREE
,
12229 tree v2si_ftype_v2si_int_int
12230 = build_function_type (V2SI_type_node
,
12231 tree_cons (NULL_TREE
, V2SI_type_node
,
12232 tree_cons (NULL_TREE
, integer_type_node
,
12233 tree_cons (NULL_TREE
,
12236 /* Miscellaneous. */
12237 tree v8qi_ftype_v4hi_v4hi
12238 = build_function_type (V8QI_type_node
,
12239 tree_cons (NULL_TREE
, V4HI_type_node
,
12240 tree_cons (NULL_TREE
, V4HI_type_node
,
12242 tree v4hi_ftype_v2si_v2si
12243 = build_function_type (V4HI_type_node
,
12244 tree_cons (NULL_TREE
, V2SI_type_node
,
12245 tree_cons (NULL_TREE
, V2SI_type_node
,
12247 tree v2si_ftype_v4hi_v4hi
12248 = build_function_type (V2SI_type_node
,
12249 tree_cons (NULL_TREE
, V4HI_type_node
,
12250 tree_cons (NULL_TREE
, V4HI_type_node
,
12252 tree v2si_ftype_v8qi_v8qi
12253 = build_function_type (V2SI_type_node
,
12254 tree_cons (NULL_TREE
, V8QI_type_node
,
12255 tree_cons (NULL_TREE
, V8QI_type_node
,
12257 tree v4hi_ftype_v4hi_di
12258 = build_function_type (V4HI_type_node
,
12259 tree_cons (NULL_TREE
, V4HI_type_node
,
12260 tree_cons (NULL_TREE
,
12261 long_long_integer_type_node
,
12263 tree v2si_ftype_v2si_di
12264 = build_function_type (V2SI_type_node
,
12265 tree_cons (NULL_TREE
, V2SI_type_node
,
12266 tree_cons (NULL_TREE
,
12267 long_long_integer_type_node
,
12269 tree void_ftype_int_int
12270 = build_function_type (void_type_node
,
12271 tree_cons (NULL_TREE
, integer_type_node
,
12272 tree_cons (NULL_TREE
, integer_type_node
,
12275 = build_function_type (long_long_unsigned_type_node
, endlink
);
12277 = build_function_type (long_long_integer_type_node
,
12278 tree_cons (NULL_TREE
, V8QI_type_node
,
12281 = build_function_type (long_long_integer_type_node
,
12282 tree_cons (NULL_TREE
, V4HI_type_node
,
12285 = build_function_type (long_long_integer_type_node
,
12286 tree_cons (NULL_TREE
, V2SI_type_node
,
12288 tree v2si_ftype_v4hi
12289 = build_function_type (V2SI_type_node
,
12290 tree_cons (NULL_TREE
, V4HI_type_node
,
12292 tree v4hi_ftype_v8qi
12293 = build_function_type (V4HI_type_node
,
12294 tree_cons (NULL_TREE
, V8QI_type_node
,
12297 tree di_ftype_di_v4hi_v4hi
12298 = build_function_type (long_long_unsigned_type_node
,
12299 tree_cons (NULL_TREE
,
12300 long_long_unsigned_type_node
,
12301 tree_cons (NULL_TREE
, V4HI_type_node
,
12302 tree_cons (NULL_TREE
,
12306 tree di_ftype_v4hi_v4hi
12307 = build_function_type (long_long_unsigned_type_node
,
12308 tree_cons (NULL_TREE
, V4HI_type_node
,
12309 tree_cons (NULL_TREE
, V4HI_type_node
,
12312 /* Normal vector binops. */
12313 tree v8qi_ftype_v8qi_v8qi
12314 = build_function_type (V8QI_type_node
,
12315 tree_cons (NULL_TREE
, V8QI_type_node
,
12316 tree_cons (NULL_TREE
, V8QI_type_node
,
12318 tree v4hi_ftype_v4hi_v4hi
12319 = build_function_type (V4HI_type_node
,
12320 tree_cons (NULL_TREE
, V4HI_type_node
,
12321 tree_cons (NULL_TREE
, V4HI_type_node
,
12323 tree v2si_ftype_v2si_v2si
12324 = build_function_type (V2SI_type_node
,
12325 tree_cons (NULL_TREE
, V2SI_type_node
,
12326 tree_cons (NULL_TREE
, V2SI_type_node
,
12328 tree di_ftype_di_di
12329 = build_function_type (long_long_unsigned_type_node
,
12330 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12331 tree_cons (NULL_TREE
,
12332 long_long_unsigned_type_node
,
12335 /* Add all builtins that are more or less simple operations on two
12337 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12339 /* Use one of the operands; the target can have a different mode for
12340 mask-generating compares. */
12341 enum machine_mode mode
;
12347 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12352 type
= v8qi_ftype_v8qi_v8qi
;
12355 type
= v4hi_ftype_v4hi_v4hi
;
12358 type
= v2si_ftype_v2si_v2si
;
12361 type
= di_ftype_di_di
;
12365 gcc_unreachable ();
12368 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12371 /* Add the remaining MMX insns with somewhat more complicated types. */
12372 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12373 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12374 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12376 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12377 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12378 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12379 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12380 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12381 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12383 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12384 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12385 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12386 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12387 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12388 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12390 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12391 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12392 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12393 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12394 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12395 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12397 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12398 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12399 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12400 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12401 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12402 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12404 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12406 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12407 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12408 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12409 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12411 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12412 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12413 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12414 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12415 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12416 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12417 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12418 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12419 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12421 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12422 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12423 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12425 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12426 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12427 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12429 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12430 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12431 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12432 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12433 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12434 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12436 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12437 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12438 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12439 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12440 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12441 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12442 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12443 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12444 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12445 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12446 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12447 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12449 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12450 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12451 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12452 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12454 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12455 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12456 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12457 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12458 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12459 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12460 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12464 arm_init_tls_builtins (void)
12467 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
12468 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
12470 ftype
= build_function_type (ptr_type_node
, void_list_node
);
12471 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
12472 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
12473 NULL
, const_nothrow
);
12477 arm_init_builtins (void)
12479 arm_init_tls_builtins ();
12481 if (TARGET_REALLY_IWMMXT
)
12482 arm_init_iwmmxt_builtins ();
12485 /* Errors in the source file can cause expand_expr to return const0_rtx
12486 where we expect a vector. To avoid crashing, use one of the vector
12487 clear instructions. */
12490 safe_vector_operand (rtx x
, enum machine_mode mode
)
12492 if (x
!= const0_rtx
)
12494 x
= gen_reg_rtx (mode
);
12496 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12497 : gen_rtx_SUBREG (DImode
, x
, 0)));
12501 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12504 arm_expand_binop_builtin (enum insn_code icode
,
12505 tree arglist
, rtx target
)
12508 tree arg0
= TREE_VALUE (arglist
);
12509 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12510 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12511 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12512 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12513 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12514 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12516 if (VECTOR_MODE_P (mode0
))
12517 op0
= safe_vector_operand (op0
, mode0
);
12518 if (VECTOR_MODE_P (mode1
))
12519 op1
= safe_vector_operand (op1
, mode1
);
12522 || GET_MODE (target
) != tmode
12523 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12524 target
= gen_reg_rtx (tmode
);
12526 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12528 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12529 op0
= copy_to_mode_reg (mode0
, op0
);
12530 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12531 op1
= copy_to_mode_reg (mode1
, op1
);
12533 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12540 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12543 arm_expand_unop_builtin (enum insn_code icode
,
12544 tree arglist
, rtx target
, int do_load
)
12547 tree arg0
= TREE_VALUE (arglist
);
12548 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12549 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12550 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12553 || GET_MODE (target
) != tmode
12554 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12555 target
= gen_reg_rtx (tmode
);
12557 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12560 if (VECTOR_MODE_P (mode0
))
12561 op0
= safe_vector_operand (op0
, mode0
);
12563 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12564 op0
= copy_to_mode_reg (mode0
, op0
);
12567 pat
= GEN_FCN (icode
) (target
, op0
);
12574 /* Expand an expression EXP that calls a built-in function,
12575 with result going to TARGET if that's convenient
12576 (and in mode MODE if that's convenient).
12577 SUBTARGET may be used as the target for computing one of EXP's operands.
12578 IGNORE is nonzero if the value is to be ignored. */
12581 arm_expand_builtin (tree exp
,
12583 rtx subtarget ATTRIBUTE_UNUSED
,
12584 enum machine_mode mode ATTRIBUTE_UNUSED
,
12585 int ignore ATTRIBUTE_UNUSED
)
12587 const struct builtin_description
* d
;
12588 enum insn_code icode
;
12589 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12590 tree arglist
= TREE_OPERAND (exp
, 1);
12598 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12600 enum machine_mode tmode
;
12601 enum machine_mode mode0
;
12602 enum machine_mode mode1
;
12603 enum machine_mode mode2
;
12607 case ARM_BUILTIN_TEXTRMSB
:
12608 case ARM_BUILTIN_TEXTRMUB
:
12609 case ARM_BUILTIN_TEXTRMSH
:
12610 case ARM_BUILTIN_TEXTRMUH
:
12611 case ARM_BUILTIN_TEXTRMSW
:
12612 case ARM_BUILTIN_TEXTRMUW
:
12613 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12614 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12615 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12616 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12617 : CODE_FOR_iwmmxt_textrmw
);
12619 arg0
= TREE_VALUE (arglist
);
12620 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12621 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12622 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12623 tmode
= insn_data
[icode
].operand
[0].mode
;
12624 mode0
= insn_data
[icode
].operand
[1].mode
;
12625 mode1
= insn_data
[icode
].operand
[2].mode
;
12627 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12628 op0
= copy_to_mode_reg (mode0
, op0
);
12629 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12631 /* @@@ better error message */
12632 error ("selector must be an immediate");
12633 return gen_reg_rtx (tmode
);
12636 || GET_MODE (target
) != tmode
12637 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12638 target
= gen_reg_rtx (tmode
);
12639 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12645 case ARM_BUILTIN_TINSRB
:
12646 case ARM_BUILTIN_TINSRH
:
12647 case ARM_BUILTIN_TINSRW
:
12648 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12649 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12650 : CODE_FOR_iwmmxt_tinsrw
);
12651 arg0
= TREE_VALUE (arglist
);
12652 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12653 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12654 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12655 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12656 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12657 tmode
= insn_data
[icode
].operand
[0].mode
;
12658 mode0
= insn_data
[icode
].operand
[1].mode
;
12659 mode1
= insn_data
[icode
].operand
[2].mode
;
12660 mode2
= insn_data
[icode
].operand
[3].mode
;
12662 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12663 op0
= copy_to_mode_reg (mode0
, op0
);
12664 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12665 op1
= copy_to_mode_reg (mode1
, op1
);
12666 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12668 /* @@@ better error message */
12669 error ("selector must be an immediate");
12673 || GET_MODE (target
) != tmode
12674 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12675 target
= gen_reg_rtx (tmode
);
12676 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12682 case ARM_BUILTIN_SETWCX
:
12683 arg0
= TREE_VALUE (arglist
);
12684 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12685 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12686 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12687 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12690 case ARM_BUILTIN_GETWCX
:
12691 arg0
= TREE_VALUE (arglist
);
12692 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12693 target
= gen_reg_rtx (SImode
);
12694 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12697 case ARM_BUILTIN_WSHUFH
:
12698 icode
= CODE_FOR_iwmmxt_wshufh
;
12699 arg0
= TREE_VALUE (arglist
);
12700 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12701 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12702 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12703 tmode
= insn_data
[icode
].operand
[0].mode
;
12704 mode1
= insn_data
[icode
].operand
[1].mode
;
12705 mode2
= insn_data
[icode
].operand
[2].mode
;
12707 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12708 op0
= copy_to_mode_reg (mode1
, op0
);
12709 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12711 /* @@@ better error message */
12712 error ("mask must be an immediate");
12716 || GET_MODE (target
) != tmode
12717 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12718 target
= gen_reg_rtx (tmode
);
12719 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12725 case ARM_BUILTIN_WSADB
:
12726 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12727 case ARM_BUILTIN_WSADH
:
12728 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12729 case ARM_BUILTIN_WSADBZ
:
12730 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12731 case ARM_BUILTIN_WSADHZ
:
12732 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12734 /* Several three-argument builtins. */
12735 case ARM_BUILTIN_WMACS
:
12736 case ARM_BUILTIN_WMACU
:
12737 case ARM_BUILTIN_WALIGN
:
12738 case ARM_BUILTIN_TMIA
:
12739 case ARM_BUILTIN_TMIAPH
:
12740 case ARM_BUILTIN_TMIATT
:
12741 case ARM_BUILTIN_TMIATB
:
12742 case ARM_BUILTIN_TMIABT
:
12743 case ARM_BUILTIN_TMIABB
:
12744 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12745 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12746 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12747 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12748 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12749 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12750 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12751 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12752 : CODE_FOR_iwmmxt_walign
);
12753 arg0
= TREE_VALUE (arglist
);
12754 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12755 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12756 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12757 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12758 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12759 tmode
= insn_data
[icode
].operand
[0].mode
;
12760 mode0
= insn_data
[icode
].operand
[1].mode
;
12761 mode1
= insn_data
[icode
].operand
[2].mode
;
12762 mode2
= insn_data
[icode
].operand
[3].mode
;
12764 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12765 op0
= copy_to_mode_reg (mode0
, op0
);
12766 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12767 op1
= copy_to_mode_reg (mode1
, op1
);
12768 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12769 op2
= copy_to_mode_reg (mode2
, op2
);
12771 || GET_MODE (target
) != tmode
12772 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12773 target
= gen_reg_rtx (tmode
);
12774 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12780 case ARM_BUILTIN_WZERO
:
12781 target
= gen_reg_rtx (DImode
);
12782 emit_insn (gen_iwmmxt_clrdi (target
));
12785 case ARM_BUILTIN_THREAD_POINTER
:
12786 return arm_load_tp (target
);
12792 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12793 if (d
->code
== (const enum arm_builtins
) fcode
)
12794 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12796 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12797 if (d
->code
== (const enum arm_builtins
) fcode
)
12798 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12800 /* @@@ Should really do something sensible here. */
12804 /* Return the number (counting from 0) of
12805 the least significant set bit in MASK. */
12808 number_of_first_bit_set (unsigned mask
)
12813 (mask
& (1 << bit
)) == 0;
12820 /* Emit code to push or pop registers to or from the stack. F is the
12821 assembly file. MASK is the registers to push or pop. PUSH is
12822 nonzero if we should push, and zero if we should pop. For debugging
12823 output, if pushing, adjust CFA_OFFSET by the amount of space added
12824 to the stack. REAL_REGS should have the same number of bits set as
12825 MASK, and will be used instead (in the same order) to describe which
12826 registers were saved - this is used to mark the save slots when we
12827 push high registers after moving them to low registers. */
12829 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12830 unsigned long real_regs
)
12833 int lo_mask
= mask
& 0xFF;
12834 int pushed_words
= 0;
12838 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12840 /* Special case. Do not generate a POP PC statement here, do it in
12842 thumb_exit (f
, -1);
12846 if (ARM_EABI_UNWIND_TABLES
&& push
)
12848 fprintf (f
, "\t.save\t{");
12849 for (regno
= 0; regno
< 15; regno
++)
12851 if (real_regs
& (1 << regno
))
12853 if (real_regs
& ((1 << regno
) -1))
12855 asm_fprintf (f
, "%r", regno
);
12858 fprintf (f
, "}\n");
12861 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12863 /* Look at the low registers first. */
12864 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12868 asm_fprintf (f
, "%r", regno
);
12870 if ((lo_mask
& ~1) != 0)
12877 if (push
&& (mask
& (1 << LR_REGNUM
)))
12879 /* Catch pushing the LR. */
12883 asm_fprintf (f
, "%r", LR_REGNUM
);
12887 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12889 /* Catch popping the PC. */
12890 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12891 || current_function_calls_eh_return
)
12893 /* The PC is never poped directly, instead
12894 it is popped into r3 and then BX is used. */
12895 fprintf (f
, "}\n");
12897 thumb_exit (f
, -1);
12906 asm_fprintf (f
, "%r", PC_REGNUM
);
12910 fprintf (f
, "}\n");
12912 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12914 char *l
= dwarf2out_cfi_label ();
12915 int pushed_mask
= real_regs
;
12917 *cfa_offset
+= pushed_words
* 4;
12918 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12921 pushed_mask
= real_regs
;
12922 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12924 if (pushed_mask
& 1)
12925 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12930 /* Generate code to return from a thumb function.
12931 If 'reg_containing_return_addr' is -1, then the return address is
12932 actually on the stack, at the stack pointer. */
12934 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12936 unsigned regs_available_for_popping
;
12937 unsigned regs_to_pop
;
12939 unsigned available
;
12943 int restore_a4
= FALSE
;
12945 /* Compute the registers we need to pop. */
12949 if (reg_containing_return_addr
== -1)
12951 regs_to_pop
|= 1 << LR_REGNUM
;
12955 if (TARGET_BACKTRACE
)
12957 /* Restore the (ARM) frame pointer and stack pointer. */
12958 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12962 /* If there is nothing to pop then just emit the BX instruction and
12964 if (pops_needed
== 0)
12966 if (current_function_calls_eh_return
)
12967 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12969 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12972 /* Otherwise if we are not supporting interworking and we have not created
12973 a backtrace structure and the function was not entered in ARM mode then
12974 just pop the return address straight into the PC. */
12975 else if (!TARGET_INTERWORK
12976 && !TARGET_BACKTRACE
12977 && !is_called_in_ARM_mode (current_function_decl
)
12978 && !current_function_calls_eh_return
)
12980 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12984 /* Find out how many of the (return) argument registers we can corrupt. */
12985 regs_available_for_popping
= 0;
12987 /* If returning via __builtin_eh_return, the bottom three registers
12988 all contain information needed for the return. */
12989 if (current_function_calls_eh_return
)
12993 /* If we can deduce the registers used from the function's
12994 return value. This is more reliable that examining
12995 regs_ever_live[] because that will be set if the register is
12996 ever used in the function, not just if the register is used
12997 to hold a return value. */
12999 if (current_function_return_rtx
!= 0)
13000 mode
= GET_MODE (current_function_return_rtx
);
13002 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13004 size
= GET_MODE_SIZE (mode
);
13008 /* In a void function we can use any argument register.
13009 In a function that returns a structure on the stack
13010 we can use the second and third argument registers. */
13011 if (mode
== VOIDmode
)
13012 regs_available_for_popping
=
13013 (1 << ARG_REGISTER (1))
13014 | (1 << ARG_REGISTER (2))
13015 | (1 << ARG_REGISTER (3));
13017 regs_available_for_popping
=
13018 (1 << ARG_REGISTER (2))
13019 | (1 << ARG_REGISTER (3));
13021 else if (size
<= 4)
13022 regs_available_for_popping
=
13023 (1 << ARG_REGISTER (2))
13024 | (1 << ARG_REGISTER (3));
13025 else if (size
<= 8)
13026 regs_available_for_popping
=
13027 (1 << ARG_REGISTER (3));
13030 /* Match registers to be popped with registers into which we pop them. */
13031 for (available
= regs_available_for_popping
,
13032 required
= regs_to_pop
;
13033 required
!= 0 && available
!= 0;
13034 available
&= ~(available
& - available
),
13035 required
&= ~(required
& - required
))
13038 /* If we have any popping registers left over, remove them. */
13040 regs_available_for_popping
&= ~available
;
13042 /* Otherwise if we need another popping register we can use
13043 the fourth argument register. */
13044 else if (pops_needed
)
13046 /* If we have not found any free argument registers and
13047 reg a4 contains the return address, we must move it. */
13048 if (regs_available_for_popping
== 0
13049 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13051 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13052 reg_containing_return_addr
= LR_REGNUM
;
13054 else if (size
> 12)
13056 /* Register a4 is being used to hold part of the return value,
13057 but we have dire need of a free, low register. */
13060 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13063 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13065 /* The fourth argument register is available. */
13066 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13072 /* Pop as many registers as we can. */
13073 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13074 regs_available_for_popping
);
13076 /* Process the registers we popped. */
13077 if (reg_containing_return_addr
== -1)
13079 /* The return address was popped into the lowest numbered register. */
13080 regs_to_pop
&= ~(1 << LR_REGNUM
);
13082 reg_containing_return_addr
=
13083 number_of_first_bit_set (regs_available_for_popping
);
13085 /* Remove this register for the mask of available registers, so that
13086 the return address will not be corrupted by further pops. */
13087 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13090 /* If we popped other registers then handle them here. */
13091 if (regs_available_for_popping
)
13095 /* Work out which register currently contains the frame pointer. */
13096 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13098 /* Move it into the correct place. */
13099 asm_fprintf (f
, "\tmov\t%r, %r\n",
13100 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13102 /* (Temporarily) remove it from the mask of popped registers. */
13103 regs_available_for_popping
&= ~(1 << frame_pointer
);
13104 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13106 if (regs_available_for_popping
)
13110 /* We popped the stack pointer as well,
13111 find the register that contains it. */
13112 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13114 /* Move it into the stack register. */
13115 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13117 /* At this point we have popped all necessary registers, so
13118 do not worry about restoring regs_available_for_popping
13119 to its correct value:
13121 assert (pops_needed == 0)
13122 assert (regs_available_for_popping == (1 << frame_pointer))
13123 assert (regs_to_pop == (1 << STACK_POINTER)) */
13127 /* Since we have just move the popped value into the frame
13128 pointer, the popping register is available for reuse, and
13129 we know that we still have the stack pointer left to pop. */
13130 regs_available_for_popping
|= (1 << frame_pointer
);
13134 /* If we still have registers left on the stack, but we no longer have
13135 any registers into which we can pop them, then we must move the return
13136 address into the link register and make available the register that
13138 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13140 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13142 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13143 reg_containing_return_addr
);
13145 reg_containing_return_addr
= LR_REGNUM
;
13148 /* If we have registers left on the stack then pop some more.
13149 We know that at most we will want to pop FP and SP. */
13150 if (pops_needed
> 0)
13155 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13156 regs_available_for_popping
);
13158 /* We have popped either FP or SP.
13159 Move whichever one it is into the correct register. */
13160 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13161 move_to
= number_of_first_bit_set (regs_to_pop
);
13163 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13165 regs_to_pop
&= ~(1 << move_to
);
13170 /* If we still have not popped everything then we must have only
13171 had one register available to us and we are now popping the SP. */
13172 if (pops_needed
> 0)
13176 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13177 regs_available_for_popping
);
13179 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13181 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13183 assert (regs_to_pop == (1 << STACK_POINTER))
13184 assert (pops_needed == 1)
13188 /* If necessary restore the a4 register. */
13191 if (reg_containing_return_addr
!= LR_REGNUM
)
13193 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13194 reg_containing_return_addr
= LR_REGNUM
;
13197 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13200 if (current_function_calls_eh_return
)
13201 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13203 /* Return to caller. */
13204 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13209 thumb_final_prescan_insn (rtx insn
)
13211 if (flag_print_asm_name
)
13212 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
13213 INSN_ADDRESSES (INSN_UID (insn
)));
13217 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
13219 unsigned HOST_WIDE_INT mask
= 0xff;
13222 if (val
== 0) /* XXX */
13225 for (i
= 0; i
< 25; i
++)
13226 if ((val
& (mask
<< i
)) == val
)
13232 /* Returns nonzero if the current function contains,
13233 or might contain a far jump. */
13235 thumb_far_jump_used_p (void)
13239 /* This test is only important for leaf functions. */
13240 /* assert (!leaf_function_p ()); */
13242 /* If we have already decided that far jumps may be used,
13243 do not bother checking again, and always return true even if
13244 it turns out that they are not being used. Once we have made
13245 the decision that far jumps are present (and that hence the link
13246 register will be pushed onto the stack) we cannot go back on it. */
13247 if (cfun
->machine
->far_jump_used
)
13250 /* If this function is not being called from the prologue/epilogue
13251 generation code then it must be being called from the
13252 INITIAL_ELIMINATION_OFFSET macro. */
13253 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13255 /* In this case we know that we are being asked about the elimination
13256 of the arg pointer register. If that register is not being used,
13257 then there are no arguments on the stack, and we do not have to
13258 worry that a far jump might force the prologue to push the link
13259 register, changing the stack offsets. In this case we can just
13260 return false, since the presence of far jumps in the function will
13261 not affect stack offsets.
13263 If the arg pointer is live (or if it was live, but has now been
13264 eliminated and so set to dead) then we do have to test to see if
13265 the function might contain a far jump. This test can lead to some
13266 false negatives, since before reload is completed, then length of
13267 branch instructions is not known, so gcc defaults to returning their
13268 longest length, which in turn sets the far jump attribute to true.
13270 A false negative will not result in bad code being generated, but it
13271 will result in a needless push and pop of the link register. We
13272 hope that this does not occur too often.
13274 If we need doubleword stack alignment this could affect the other
13275 elimination offsets so we can't risk getting it wrong. */
13276 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13277 cfun
->machine
->arg_pointer_live
= 1;
13278 else if (!cfun
->machine
->arg_pointer_live
)
13282 /* Check to see if the function contains a branch
13283 insn with the far jump attribute set. */
13284 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13286 if (GET_CODE (insn
) == JUMP_INSN
13287 /* Ignore tablejump patterns. */
13288 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13289 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13290 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13293 /* Record the fact that we have decided that
13294 the function does use far jumps. */
13295 cfun
->machine
->far_jump_used
= 1;
13303 /* Return nonzero if FUNC must be entered in ARM mode. */
13305 is_called_in_ARM_mode (tree func
)
13307 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
13309 /* Ignore the problem about functions whose address is taken. */
13310 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13314 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13320 /* The bits which aren't usefully expanded as rtl. */
13322 thumb_unexpanded_epilogue (void)
13325 unsigned long live_regs_mask
= 0;
13326 int high_regs_pushed
= 0;
13327 int had_to_push_lr
;
13330 if (return_used_this_function
)
13333 if (IS_NAKED (arm_current_func_type ()))
13336 live_regs_mask
= thumb_compute_save_reg_mask ();
13337 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13339 /* If we can deduce the registers used from the function's return value.
13340 This is more reliable that examining regs_ever_live[] because that
13341 will be set if the register is ever used in the function, not just if
13342 the register is used to hold a return value. */
13343 size
= arm_size_return_regs ();
13345 /* The prolog may have pushed some high registers to use as
13346 work registers. e.g. the testsuite file:
13347 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13348 compiles to produce:
13349 push {r4, r5, r6, r7, lr}
13353 as part of the prolog. We have to undo that pushing here. */
13355 if (high_regs_pushed
)
13357 unsigned long mask
= live_regs_mask
& 0xff;
13360 /* The available low registers depend on the size of the value we are
13368 /* Oh dear! We have no low registers into which we can pop
13371 ("no low registers available for popping high registers");
13373 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13374 if (live_regs_mask
& (1 << next_hi_reg
))
13377 while (high_regs_pushed
)
13379 /* Find lo register(s) into which the high register(s) can
13381 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13383 if (mask
& (1 << regno
))
13384 high_regs_pushed
--;
13385 if (high_regs_pushed
== 0)
13389 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13391 /* Pop the values into the low register(s). */
13392 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13394 /* Move the value(s) into the high registers. */
13395 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13397 if (mask
& (1 << regno
))
13399 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13402 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13403 if (live_regs_mask
& (1 << next_hi_reg
))
13408 live_regs_mask
&= ~0x0f00;
13411 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13412 live_regs_mask
&= 0xff;
13414 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13416 /* Pop the return address into the PC. */
13417 if (had_to_push_lr
)
13418 live_regs_mask
|= 1 << PC_REGNUM
;
13420 /* Either no argument registers were pushed or a backtrace
13421 structure was created which includes an adjusted stack
13422 pointer, so just pop everything. */
13423 if (live_regs_mask
)
13424 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13427 /* We have either just popped the return address into the
13428 PC or it is was kept in LR for the entire function. */
13429 if (!had_to_push_lr
)
13430 thumb_exit (asm_out_file
, LR_REGNUM
);
13434 /* Pop everything but the return address. */
13435 if (live_regs_mask
)
13436 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13439 if (had_to_push_lr
)
13443 /* We have no free low regs, so save one. */
13444 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13448 /* Get the return address into a temporary register. */
13449 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13450 1 << LAST_ARG_REGNUM
);
13454 /* Move the return address to lr. */
13455 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13457 /* Restore the low register. */
13458 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13463 regno
= LAST_ARG_REGNUM
;
13468 /* Remove the argument registers that were pushed onto the stack. */
13469 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13470 SP_REGNUM
, SP_REGNUM
,
13471 current_function_pretend_args_size
);
13473 thumb_exit (asm_out_file
, regno
);
13479 /* Functions to save and restore machine-specific function data. */
13480 static struct machine_function
*
13481 arm_init_machine_status (void)
13483 struct machine_function
*machine
;
13484 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13486 #if ARM_FT_UNKNOWN != 0
13487 machine
->func_type
= ARM_FT_UNKNOWN
;
13492 /* Return an RTX indicating where the return address to the
13493 calling function can be found. */
13495 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13500 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13503 /* Do anything needed before RTL is emitted for each function. */
13505 arm_init_expanders (void)
13507 /* Arrange to initialize and mark the machine per-function status. */
13508 init_machine_status
= arm_init_machine_status
;
13510 /* This is to stop the combine pass optimizing away the alignment
13511 adjustment of va_arg. */
13512 /* ??? It is claimed that this should not be necessary. */
13514 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13518 /* Like arm_compute_initial_elimination offset. Simpler because there
13519 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13520 to point at the base of the local variables after static stack
13521 space for a function has been allocated. */
13524 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13526 arm_stack_offsets
*offsets
;
13528 offsets
= arm_get_frame_offsets ();
13532 case ARG_POINTER_REGNUM
:
13535 case STACK_POINTER_REGNUM
:
13536 return offsets
->outgoing_args
- offsets
->saved_args
;
13538 case FRAME_POINTER_REGNUM
:
13539 return offsets
->soft_frame
- offsets
->saved_args
;
13541 case ARM_HARD_FRAME_POINTER_REGNUM
:
13542 return offsets
->saved_regs
- offsets
->saved_args
;
13544 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13545 return offsets
->locals_base
- offsets
->saved_args
;
13548 gcc_unreachable ();
13552 case FRAME_POINTER_REGNUM
:
13555 case STACK_POINTER_REGNUM
:
13556 return offsets
->outgoing_args
- offsets
->soft_frame
;
13558 case ARM_HARD_FRAME_POINTER_REGNUM
:
13559 return offsets
->saved_regs
- offsets
->soft_frame
;
13561 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13562 return offsets
->locals_base
- offsets
->soft_frame
;
13565 gcc_unreachable ();
13570 gcc_unreachable ();
13575 /* Generate the rest of a function's prologue. */
13577 thumb_expand_prologue (void)
13581 HOST_WIDE_INT amount
;
13582 arm_stack_offsets
*offsets
;
13583 unsigned long func_type
;
13585 unsigned long live_regs_mask
;
13587 func_type
= arm_current_func_type ();
13589 /* Naked functions don't have prologues. */
13590 if (IS_NAKED (func_type
))
13593 if (IS_INTERRUPT (func_type
))
13595 error ("interrupt Service Routines cannot be coded in Thumb mode");
13599 live_regs_mask
= thumb_compute_save_reg_mask ();
13600 /* Load the pic register before setting the frame pointer,
13601 so we can use r7 as a temporary work register. */
13603 arm_load_pic_register (live_regs_mask
);
13605 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13606 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13607 stack_pointer_rtx
);
13609 offsets
= arm_get_frame_offsets ();
13610 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13615 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13616 GEN_INT (- amount
)));
13617 RTX_FRAME_RELATED_P (insn
) = 1;
13623 /* The stack decrement is too big for an immediate value in a single
13624 insn. In theory we could issue multiple subtracts, but after
13625 three of them it becomes more space efficient to place the full
13626 value in the constant pool and load into a register. (Also the
13627 ARM debugger really likes to see only one stack decrement per
13628 function). So instead we look for a scratch register into which
13629 we can load the decrement, and then we subtract this from the
13630 stack pointer. Unfortunately on the thumb the only available
13631 scratch registers are the argument registers, and we cannot use
13632 these as they may hold arguments to the function. Instead we
13633 attempt to locate a call preserved register which is used by this
13634 function. If we can find one, then we know that it will have
13635 been pushed at the start of the prologue and so we can corrupt
13637 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13638 if (live_regs_mask
& (1 << regno
)
13639 && !(frame_pointer_needed
13640 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13643 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13645 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13647 /* Choose an arbitrary, non-argument low register. */
13648 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13650 /* Save it by copying it into a high, scratch register. */
13651 emit_insn (gen_movsi (spare
, reg
));
13652 /* Add a USE to stop propagate_one_insn() from barfing. */
13653 emit_insn (gen_prologue_use (spare
));
13655 /* Decrement the stack. */
13656 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13657 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13658 stack_pointer_rtx
, reg
));
13659 RTX_FRAME_RELATED_P (insn
) = 1;
13660 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13661 plus_constant (stack_pointer_rtx
,
13663 RTX_FRAME_RELATED_P (dwarf
) = 1;
13665 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13668 /* Restore the low register's original value. */
13669 emit_insn (gen_movsi (reg
, spare
));
13671 /* Emit a USE of the restored scratch register, so that flow
13672 analysis will not consider the restore redundant. The
13673 register won't be used again in this function and isn't
13674 restored by the epilogue. */
13675 emit_insn (gen_prologue_use (reg
));
13679 reg
= gen_rtx_REG (SImode
, regno
);
13681 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13683 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13684 stack_pointer_rtx
, reg
));
13685 RTX_FRAME_RELATED_P (insn
) = 1;
13686 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13687 plus_constant (stack_pointer_rtx
,
13689 RTX_FRAME_RELATED_P (dwarf
) = 1;
13691 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13697 if (frame_pointer_needed
)
13699 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13702 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13703 stack_pointer_rtx
, GEN_INT (amount
)));
13706 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13707 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13708 hard_frame_pointer_rtx
,
13709 stack_pointer_rtx
));
13710 dwarf
= gen_rtx_SET (SImode
, hard_frame_pointer_rtx
,
13711 plus_constant (stack_pointer_rtx
, amount
));
13712 RTX_FRAME_RELATED_P (dwarf
) = 1;
13713 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13717 RTX_FRAME_RELATED_P (insn
) = 1;
13720 /* If we are profiling, make sure no instructions are scheduled before
13721 the call to mcount. Similarly if the user has requested no
13722 scheduling in the prolog. Similarly if we want non-call exceptions
13723 using the EABI unwinder, to prevent faulting instructions from being
13724 swapped with a stack adjustment. */
13725 if (current_function_profile
|| !TARGET_SCHED_PROLOG
13726 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
13727 emit_insn (gen_blockage ());
13729 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13730 if (live_regs_mask
& 0xff)
13731 cfun
->machine
->lr_save_eliminated
= 0;
13733 /* If the link register is being kept alive, with the return address in it,
13734 then make sure that it does not get reused by the ce2 pass. */
13735 if (cfun
->machine
->lr_save_eliminated
)
13736 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13741 thumb_expand_epilogue (void)
13743 HOST_WIDE_INT amount
;
13744 arm_stack_offsets
*offsets
;
13747 /* Naked functions don't have prologues. */
13748 if (IS_NAKED (arm_current_func_type ()))
13751 offsets
= arm_get_frame_offsets ();
13752 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13754 if (frame_pointer_needed
)
13756 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13757 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13763 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13764 GEN_INT (amount
)));
13767 /* r3 is always free in the epilogue. */
13768 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13770 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13771 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13775 /* Emit a USE (stack_pointer_rtx), so that
13776 the stack adjustment will not be deleted. */
13777 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13779 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13780 emit_insn (gen_blockage ());
13782 /* Emit a clobber for each insn that will be restored in the epilogue,
13783 so that flow2 will get register lifetimes correct. */
13784 for (regno
= 0; regno
< 13; regno
++)
13785 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13786 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13788 if (! regs_ever_live
[LR_REGNUM
])
13789 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13793 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13795 unsigned long live_regs_mask
= 0;
13796 unsigned long l_mask
;
13797 unsigned high_regs_pushed
= 0;
13798 int cfa_offset
= 0;
13801 if (IS_NAKED (arm_current_func_type ()))
13804 if (is_called_in_ARM_mode (current_function_decl
))
13808 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13809 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13811 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13813 /* Generate code sequence to switch us into Thumb mode. */
13814 /* The .code 32 directive has already been emitted by
13815 ASM_DECLARE_FUNCTION_NAME. */
13816 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13817 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13819 /* Generate a label, so that the debugger will notice the
13820 change in instruction sets. This label is also used by
13821 the assembler to bypass the ARM code when this function
13822 is called from a Thumb encoded function elsewhere in the
13823 same file. Hence the definition of STUB_NAME here must
13824 agree with the definition in gas/config/tc-arm.c. */
13826 #define STUB_NAME ".real_start_of"
13828 fprintf (f
, "\t.code\t16\n");
13830 if (arm_dllexport_name_p (name
))
13831 name
= arm_strip_name_encoding (name
);
13833 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13834 fprintf (f
, "\t.thumb_func\n");
13835 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13838 if (current_function_pretend_args_size
)
13840 /* Output unwind directive for the stack adjustment. */
13841 if (ARM_EABI_UNWIND_TABLES
)
13842 fprintf (f
, "\t.pad #%d\n",
13843 current_function_pretend_args_size
);
13845 if (cfun
->machine
->uses_anonymous_args
)
13849 fprintf (f
, "\tpush\t{");
13851 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13853 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13854 regno
<= LAST_ARG_REGNUM
;
13856 asm_fprintf (f
, "%r%s", regno
,
13857 regno
== LAST_ARG_REGNUM
? "" : ", ");
13859 fprintf (f
, "}\n");
13862 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13863 SP_REGNUM
, SP_REGNUM
,
13864 current_function_pretend_args_size
);
13866 /* We don't need to record the stores for unwinding (would it
13867 help the debugger any if we did?), but record the change in
13868 the stack pointer. */
13869 if (dwarf2out_do_frame ())
13871 char *l
= dwarf2out_cfi_label ();
13873 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13874 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13878 /* Get the registers we are going to push. */
13879 live_regs_mask
= thumb_compute_save_reg_mask ();
13880 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13881 l_mask
= live_regs_mask
& 0x40ff;
13882 /* Then count how many other high registers will need to be pushed. */
13883 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13885 if (TARGET_BACKTRACE
)
13888 unsigned work_register
;
13890 /* We have been asked to create a stack backtrace structure.
13891 The code looks like this:
13895 0 sub SP, #16 Reserve space for 4 registers.
13896 2 push {R7} Push low registers.
13897 4 add R7, SP, #20 Get the stack pointer before the push.
13898 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13899 8 mov R7, PC Get hold of the start of this code plus 12.
13900 10 str R7, [SP, #16] Store it.
13901 12 mov R7, FP Get hold of the current frame pointer.
13902 14 str R7, [SP, #4] Store it.
13903 16 mov R7, LR Get hold of the current return address.
13904 18 str R7, [SP, #12] Store it.
13905 20 add R7, SP, #16 Point at the start of the backtrace structure.
13906 22 mov FP, R7 Put this value into the frame pointer. */
13908 work_register
= thumb_find_work_register (live_regs_mask
);
13910 if (ARM_EABI_UNWIND_TABLES
)
13911 asm_fprintf (f
, "\t.pad #16\n");
13914 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13915 SP_REGNUM
, SP_REGNUM
);
13917 if (dwarf2out_do_frame ())
13919 char *l
= dwarf2out_cfi_label ();
13921 cfa_offset
= cfa_offset
+ 16;
13922 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13927 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13928 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13933 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13934 offset
+ 16 + current_function_pretend_args_size
);
13936 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13939 /* Make sure that the instruction fetching the PC is in the right place
13940 to calculate "start of backtrace creation code + 12". */
13943 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13944 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13946 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13947 ARM_HARD_FRAME_POINTER_REGNUM
);
13948 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13953 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13954 ARM_HARD_FRAME_POINTER_REGNUM
);
13955 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13957 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13958 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13962 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13963 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13965 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13967 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13968 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13970 /* Optimization: If we are not pushing any low registers but we are going
13971 to push some high registers then delay our first push. This will just
13972 be a push of LR and we can combine it with the push of the first high
13974 else if ((l_mask
& 0xff) != 0
13975 || (high_regs_pushed
== 0 && l_mask
))
13976 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13978 if (high_regs_pushed
)
13980 unsigned pushable_regs
;
13981 unsigned next_hi_reg
;
13983 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13984 if (live_regs_mask
& (1 << next_hi_reg
))
13987 pushable_regs
= l_mask
& 0xff;
13989 if (pushable_regs
== 0)
13990 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13992 while (high_regs_pushed
> 0)
13994 unsigned long real_regs_mask
= 0;
13996 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13998 if (pushable_regs
& (1 << regno
))
14000 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
14002 high_regs_pushed
--;
14003 real_regs_mask
|= (1 << next_hi_reg
);
14005 if (high_regs_pushed
)
14007 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
14009 if (live_regs_mask
& (1 << next_hi_reg
))
14014 pushable_regs
&= ~((1 << regno
) - 1);
14020 /* If we had to find a work register and we have not yet
14021 saved the LR then add it to the list of regs to push. */
14022 if (l_mask
== (1 << LR_REGNUM
))
14024 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14026 real_regs_mask
| (1 << LR_REGNUM
));
14030 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14035 /* Handle the case of a double word load into a low register from
14036 a computed memory address. The computed address may involve a
14037 register which is overwritten by the load. */
14039 thumb_load_double_from_address (rtx
*operands
)
14047 gcc_assert (GET_CODE (operands
[0]) == REG
);
14048 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14050 /* Get the memory address. */
14051 addr
= XEXP (operands
[1], 0);
14053 /* Work out how the memory address is computed. */
14054 switch (GET_CODE (addr
))
14057 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14059 if (REGNO (operands
[0]) == REGNO (addr
))
14061 output_asm_insn ("ldr\t%H0, %2", operands
);
14062 output_asm_insn ("ldr\t%0, %1", operands
);
14066 output_asm_insn ("ldr\t%0, %1", operands
);
14067 output_asm_insn ("ldr\t%H0, %2", operands
);
14072 /* Compute <address> + 4 for the high order load. */
14073 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14075 output_asm_insn ("ldr\t%0, %1", operands
);
14076 output_asm_insn ("ldr\t%H0, %2", operands
);
14080 arg1
= XEXP (addr
, 0);
14081 arg2
= XEXP (addr
, 1);
14083 if (CONSTANT_P (arg1
))
14084 base
= arg2
, offset
= arg1
;
14086 base
= arg1
, offset
= arg2
;
14088 gcc_assert (GET_CODE (base
) == REG
);
14090 /* Catch the case of <address> = <reg> + <reg> */
14091 if (GET_CODE (offset
) == REG
)
14093 int reg_offset
= REGNO (offset
);
14094 int reg_base
= REGNO (base
);
14095 int reg_dest
= REGNO (operands
[0]);
14097 /* Add the base and offset registers together into the
14098 higher destination register. */
14099 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14100 reg_dest
+ 1, reg_base
, reg_offset
);
14102 /* Load the lower destination register from the address in
14103 the higher destination register. */
14104 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14105 reg_dest
, reg_dest
+ 1);
14107 /* Load the higher destination register from its own address
14109 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14110 reg_dest
+ 1, reg_dest
+ 1);
14114 /* Compute <address> + 4 for the high order load. */
14115 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14117 /* If the computed address is held in the low order register
14118 then load the high order register first, otherwise always
14119 load the low order register first. */
14120 if (REGNO (operands
[0]) == REGNO (base
))
14122 output_asm_insn ("ldr\t%H0, %2", operands
);
14123 output_asm_insn ("ldr\t%0, %1", operands
);
14127 output_asm_insn ("ldr\t%0, %1", operands
);
14128 output_asm_insn ("ldr\t%H0, %2", operands
);
14134 /* With no registers to worry about we can just load the value
14136 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14138 output_asm_insn ("ldr\t%H0, %2", operands
);
14139 output_asm_insn ("ldr\t%0, %1", operands
);
14143 gcc_unreachable ();
14150 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14157 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14160 operands
[4] = operands
[5];
14163 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14164 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14168 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14171 operands
[4] = operands
[5];
14174 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14177 operands
[5] = operands
[6];
14180 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14183 operands
[4] = operands
[5];
14187 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14188 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14192 gcc_unreachable ();
14198 /* Output a call-via instruction for thumb state. */
14200 thumb_call_via_reg (rtx reg
)
14202 int regno
= REGNO (reg
);
14205 gcc_assert (regno
< LR_REGNUM
);
14207 /* If we are in the normal text section we can use a single instance
14208 per compilation unit. If we are doing function sections, then we need
14209 an entry per section, since we can't rely on reachability. */
14210 if (in_text_section ())
14212 thumb_call_reg_needed
= 1;
14214 if (thumb_call_via_label
[regno
] == NULL
)
14215 thumb_call_via_label
[regno
] = gen_label_rtx ();
14216 labelp
= thumb_call_via_label
+ regno
;
14220 if (cfun
->machine
->call_via
[regno
] == NULL
)
14221 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
14222 labelp
= cfun
->machine
->call_via
+ regno
;
14225 output_asm_insn ("bl\t%a0", labelp
);
14229 /* Routines for generating rtl. */
14231 thumb_expand_movmemqi (rtx
*operands
)
14233 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
14234 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
14235 HOST_WIDE_INT len
= INTVAL (operands
[2]);
14236 HOST_WIDE_INT offset
= 0;
14240 emit_insn (gen_movmem12b (out
, in
, out
, in
));
14246 emit_insn (gen_movmem8b (out
, in
, out
, in
));
14252 rtx reg
= gen_reg_rtx (SImode
);
14253 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
14254 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
14261 rtx reg
= gen_reg_rtx (HImode
);
14262 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
14263 plus_constant (in
, offset
))));
14264 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
14272 rtx reg
= gen_reg_rtx (QImode
);
14273 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
14274 plus_constant (in
, offset
))));
14275 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
14281 thumb_reload_out_hi (rtx
*operands
)
14283 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14286 /* Handle reading a half-word from memory during reload. */
14288 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14290 gcc_unreachable ();
14293 /* Return the length of a function name prefix
14294 that starts with the character 'c'. */
14296 arm_get_strip_length (int c
)
14300 ARM_NAME_ENCODING_LENGTHS
14305 /* Return a pointer to a function's name with any
14306 and all prefix encodings stripped from it. */
14308 arm_strip_name_encoding (const char *name
)
14312 while ((skip
= arm_get_strip_length (* name
)))
14318 /* If there is a '*' anywhere in the name's prefix, then
14319 emit the stripped name verbatim, otherwise prepend an
14320 underscore if leading underscores are being used. */
14322 arm_asm_output_labelref (FILE *stream
, const char *name
)
14327 while ((skip
= arm_get_strip_length (* name
)))
14329 verbatim
|= (*name
== '*');
14334 fputs (name
, stream
);
14336 asm_fprintf (stream
, "%U%s", name
);
14340 arm_file_end (void)
14344 if (! thumb_call_reg_needed
)
14348 asm_fprintf (asm_out_file
, "\t.code 16\n");
14349 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
14351 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14353 rtx label
= thumb_call_via_label
[regno
];
14357 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14358 CODE_LABEL_NUMBER (label
));
14359 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14366 #ifdef AOF_ASSEMBLER
14367 /* Special functions only needed when producing AOF syntax assembler. */
14371 struct pic_chain
* next
;
14372 const char * symname
;
14375 static struct pic_chain
* aof_pic_chain
= NULL
;
14378 aof_pic_entry (rtx x
)
14380 struct pic_chain
** chainp
;
14383 if (aof_pic_label
== NULL_RTX
)
14385 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14388 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14389 offset
+= 4, chainp
= &(*chainp
)->next
)
14390 if ((*chainp
)->symname
== XSTR (x
, 0))
14391 return plus_constant (aof_pic_label
, offset
);
14393 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14394 (*chainp
)->next
= NULL
;
14395 (*chainp
)->symname
= XSTR (x
, 0);
14396 return plus_constant (aof_pic_label
, offset
);
14400 aof_dump_pic_table (FILE *f
)
14402 struct pic_chain
* chain
;
14404 if (aof_pic_chain
== NULL
)
14407 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14408 PIC_OFFSET_TABLE_REGNUM
,
14409 PIC_OFFSET_TABLE_REGNUM
);
14410 fputs ("|x$adcons|\n", f
);
14412 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14414 fputs ("\tDCD\t", f
);
14415 assemble_name (f
, chain
->symname
);
14420 int arm_text_section_count
= 1;
14423 aof_text_section (void )
14425 static char buf
[100];
14426 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14427 arm_text_section_count
++);
14429 strcat (buf
, ", PIC, REENTRANT");
14433 static int arm_data_section_count
= 1;
14436 aof_data_section (void)
14438 static char buf
[100];
14439 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14443 /* The AOF assembler is religiously strict about declarations of
14444 imported and exported symbols, so that it is impossible to declare
14445 a function as imported near the beginning of the file, and then to
14446 export it later on. It is, however, possible to delay the decision
14447 until all the functions in the file have been compiled. To get
14448 around this, we maintain a list of the imports and exports, and
14449 delete from it any that are subsequently defined. At the end of
14450 compilation we spit the remainder of the list out before the END
14455 struct import
* next
;
14459 static struct import
* imports_list
= NULL
;
14462 aof_add_import (const char *name
)
14464 struct import
* new;
14466 for (new = imports_list
; new; new = new->next
)
14467 if (new->name
== name
)
14470 new = (struct import
*) xmalloc (sizeof (struct import
));
14471 new->next
= imports_list
;
14472 imports_list
= new;
14477 aof_delete_import (const char *name
)
14479 struct import
** old
;
14481 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14483 if ((*old
)->name
== name
)
14485 *old
= (*old
)->next
;
14491 int arm_main_function
= 0;
14494 aof_dump_imports (FILE *f
)
14496 /* The AOF assembler needs this to cause the startup code to be extracted
14497 from the library. Brining in __main causes the whole thing to work
14499 if (arm_main_function
)
14502 fputs ("\tIMPORT __main\n", f
);
14503 fputs ("\tDCD __main\n", f
);
14506 /* Now dump the remaining imports. */
14507 while (imports_list
)
14509 fprintf (f
, "\tIMPORT\t");
14510 assemble_name (f
, imports_list
->name
);
14512 imports_list
= imports_list
->next
;
14517 aof_globalize_label (FILE *stream
, const char *name
)
14519 default_globalize_label (stream
, name
);
14520 if (! strcmp (name
, "main"))
14521 arm_main_function
= 1;
14525 aof_file_start (void)
14527 fputs ("__r0\tRN\t0\n", asm_out_file
);
14528 fputs ("__a1\tRN\t0\n", asm_out_file
);
14529 fputs ("__a2\tRN\t1\n", asm_out_file
);
14530 fputs ("__a3\tRN\t2\n", asm_out_file
);
14531 fputs ("__a4\tRN\t3\n", asm_out_file
);
14532 fputs ("__v1\tRN\t4\n", asm_out_file
);
14533 fputs ("__v2\tRN\t5\n", asm_out_file
);
14534 fputs ("__v3\tRN\t6\n", asm_out_file
);
14535 fputs ("__v4\tRN\t7\n", asm_out_file
);
14536 fputs ("__v5\tRN\t8\n", asm_out_file
);
14537 fputs ("__v6\tRN\t9\n", asm_out_file
);
14538 fputs ("__sl\tRN\t10\n", asm_out_file
);
14539 fputs ("__fp\tRN\t11\n", asm_out_file
);
14540 fputs ("__ip\tRN\t12\n", asm_out_file
);
14541 fputs ("__sp\tRN\t13\n", asm_out_file
);
14542 fputs ("__lr\tRN\t14\n", asm_out_file
);
14543 fputs ("__pc\tRN\t15\n", asm_out_file
);
14544 fputs ("__f0\tFN\t0\n", asm_out_file
);
14545 fputs ("__f1\tFN\t1\n", asm_out_file
);
14546 fputs ("__f2\tFN\t2\n", asm_out_file
);
14547 fputs ("__f3\tFN\t3\n", asm_out_file
);
14548 fputs ("__f4\tFN\t4\n", asm_out_file
);
14549 fputs ("__f5\tFN\t5\n", asm_out_file
);
14550 fputs ("__f6\tFN\t6\n", asm_out_file
);
14551 fputs ("__f7\tFN\t7\n", asm_out_file
);
14556 aof_file_end (void)
14559 aof_dump_pic_table (asm_out_file
);
14561 aof_dump_imports (asm_out_file
);
14562 fputs ("\tEND\n", asm_out_file
);
14564 #endif /* AOF_ASSEMBLER */
14567 /* Symbols in the text segment can be accessed without indirecting via the
14568 constant pool; it may take an extra binary operation, but this is still
14569 faster than indirecting via memory. Don't do this when not optimizing,
14570 since we won't be calculating al of the offsets necessary to do this
14574 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14576 /* This doesn't work with AOF syntax, since the string table may be in
14577 a different AREA. */
14578 #ifndef AOF_ASSEMBLER
14579 if (optimize
> 0 && TREE_CONSTANT (decl
))
14580 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14583 /* If we are referencing a function that is weak then encode a long call
14584 flag in the function name, otherwise if the function is static or
14585 or known to be defined in this file then encode a short call flag. */
14586 if (first
&& DECL_P (decl
))
14588 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14589 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14590 else if (! TREE_PUBLIC (decl
))
14591 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14594 default_encode_section_info (decl
, rtl
, first
);
14596 #endif /* !ARM_PE */
14599 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14601 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14602 && !strcmp (prefix
, "L"))
14604 arm_ccfsm_state
= 0;
14605 arm_target_insn
= NULL
;
14607 default_internal_label (stream
, prefix
, labelno
);
14610 /* Output code to add DELTA to the first argument, and then jump
14611 to FUNCTION. Used for C++ multiple inheritance. */
14613 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14614 HOST_WIDE_INT delta
,
14615 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14618 static int thunk_label
= 0;
14620 int mi_delta
= delta
;
14621 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14623 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14626 mi_delta
= - mi_delta
;
14629 int labelno
= thunk_label
++;
14630 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14631 fputs ("\tldr\tr12, ", file
);
14632 assemble_name (file
, label
);
14633 fputc ('\n', file
);
14635 while (mi_delta
!= 0)
14637 if ((mi_delta
& (3 << shift
)) == 0)
14641 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14642 mi_op
, this_regno
, this_regno
,
14643 mi_delta
& (0xff << shift
));
14644 mi_delta
&= ~(0xff << shift
);
14650 fprintf (file
, "\tbx\tr12\n");
14651 ASM_OUTPUT_ALIGN (file
, 2);
14652 assemble_name (file
, label
);
14653 fputs (":\n", file
);
14654 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14658 fputs ("\tb\t", file
);
14659 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14660 if (NEED_PLT_RELOC
)
14661 fputs ("(PLT)", file
);
14662 fputc ('\n', file
);
14667 arm_emit_vector_const (FILE *file
, rtx x
)
14670 const char * pattern
;
14672 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14674 switch (GET_MODE (x
))
14676 case V2SImode
: pattern
= "%08x"; break;
14677 case V4HImode
: pattern
= "%04x"; break;
14678 case V8QImode
: pattern
= "%02x"; break;
14679 default: gcc_unreachable ();
14682 fprintf (file
, "0x");
14683 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14687 element
= CONST_VECTOR_ELT (x
, i
);
14688 fprintf (file
, pattern
, INTVAL (element
));
14695 arm_output_load_gr (rtx
*operands
)
14702 if (GET_CODE (operands
[1]) != MEM
14703 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14704 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14705 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14706 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14707 return "wldrw%?\t%0, %1";
14709 /* Fix up an out-of-range load of a GR register. */
14710 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14711 wcgr
= operands
[0];
14713 output_asm_insn ("ldr%?\t%0, %1", operands
);
14715 operands
[0] = wcgr
;
14717 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14718 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14724 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14725 int incoming ATTRIBUTE_UNUSED
)
14728 /* FIXME: The ARM backend has special code to handle structure
14729 returns, and will reserve its own hidden first argument. So
14730 if this macro is enabled a *second* hidden argument will be
14731 reserved, which will break binary compatibility with old
14732 toolchains and also thunk handling. One day this should be
14736 /* Register in which address to store a structure value
14737 is passed to a function. */
14738 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14742 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14744 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14745 named arg and all anonymous args onto the stack.
14746 XXX I know the prologue shouldn't be pushing registers, but it is faster
14750 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14751 enum machine_mode mode ATTRIBUTE_UNUSED
,
14752 tree type ATTRIBUTE_UNUSED
,
14754 int second_time ATTRIBUTE_UNUSED
)
14756 cfun
->machine
->uses_anonymous_args
= 1;
14757 if (cum
->nregs
< NUM_ARG_REGS
)
14758 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14761 /* Return nonzero if the CONSUMER instruction (a store) does not need
14762 PRODUCER's value to calculate the address. */
14765 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14767 rtx value
= PATTERN (producer
);
14768 rtx addr
= PATTERN (consumer
);
14770 if (GET_CODE (value
) == COND_EXEC
)
14771 value
= COND_EXEC_CODE (value
);
14772 if (GET_CODE (value
) == PARALLEL
)
14773 value
= XVECEXP (value
, 0, 0);
14774 value
= XEXP (value
, 0);
14775 if (GET_CODE (addr
) == COND_EXEC
)
14776 addr
= COND_EXEC_CODE (addr
);
14777 if (GET_CODE (addr
) == PARALLEL
)
14778 addr
= XVECEXP (addr
, 0, 0);
14779 addr
= XEXP (addr
, 0);
14781 return !reg_overlap_mentioned_p (value
, addr
);
14784 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14785 have an early register shift value or amount dependency on the
14786 result of PRODUCER. */
14789 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14791 rtx value
= PATTERN (producer
);
14792 rtx op
= PATTERN (consumer
);
14795 if (GET_CODE (value
) == COND_EXEC
)
14796 value
= COND_EXEC_CODE (value
);
14797 if (GET_CODE (value
) == PARALLEL
)
14798 value
= XVECEXP (value
, 0, 0);
14799 value
= XEXP (value
, 0);
14800 if (GET_CODE (op
) == COND_EXEC
)
14801 op
= COND_EXEC_CODE (op
);
14802 if (GET_CODE (op
) == PARALLEL
)
14803 op
= XVECEXP (op
, 0, 0);
14806 early_op
= XEXP (op
, 0);
14807 /* This is either an actual independent shift, or a shift applied to
14808 the first operand of another operation. We want the whole shift
14810 if (GET_CODE (early_op
) == REG
)
14813 return !reg_overlap_mentioned_p (value
, early_op
);
14816 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14817 have an early register shift value dependency on the result of
14821 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14823 rtx value
= PATTERN (producer
);
14824 rtx op
= PATTERN (consumer
);
14827 if (GET_CODE (value
) == COND_EXEC
)
14828 value
= COND_EXEC_CODE (value
);
14829 if (GET_CODE (value
) == PARALLEL
)
14830 value
= XVECEXP (value
, 0, 0);
14831 value
= XEXP (value
, 0);
14832 if (GET_CODE (op
) == COND_EXEC
)
14833 op
= COND_EXEC_CODE (op
);
14834 if (GET_CODE (op
) == PARALLEL
)
14835 op
= XVECEXP (op
, 0, 0);
14838 early_op
= XEXP (op
, 0);
14840 /* This is either an actual independent shift, or a shift applied to
14841 the first operand of another operation. We want the value being
14842 shifted, in either case. */
14843 if (GET_CODE (early_op
) != REG
)
14844 early_op
= XEXP (early_op
, 0);
14846 return !reg_overlap_mentioned_p (value
, early_op
);
14849 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14850 have an early register mult dependency on the result of
14854 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14856 rtx value
= PATTERN (producer
);
14857 rtx op
= PATTERN (consumer
);
14859 if (GET_CODE (value
) == COND_EXEC
)
14860 value
= COND_EXEC_CODE (value
);
14861 if (GET_CODE (value
) == PARALLEL
)
14862 value
= XVECEXP (value
, 0, 0);
14863 value
= XEXP (value
, 0);
14864 if (GET_CODE (op
) == COND_EXEC
)
14865 op
= COND_EXEC_CODE (op
);
14866 if (GET_CODE (op
) == PARALLEL
)
14867 op
= XVECEXP (op
, 0, 0);
14870 return (GET_CODE (op
) == PLUS
14871 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14875 /* We can't rely on the caller doing the proper promotion when
14876 using APCS or ATPCS. */
14879 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14881 return !TARGET_AAPCS_BASED
;
14885 /* AAPCS based ABIs use short enums by default. */
14888 arm_default_short_enums (void)
14890 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
14894 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14897 arm_align_anon_bitfield (void)
14899 return TARGET_AAPCS_BASED
;
14903 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14906 arm_cxx_guard_type (void)
14908 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14912 /* The EABI says test the least significant bit of a guard variable. */
14915 arm_cxx_guard_mask_bit (void)
14917 return TARGET_AAPCS_BASED
;
14921 /* The EABI specifies that all array cookies are 8 bytes long. */
14924 arm_get_cookie_size (tree type
)
14928 if (!TARGET_AAPCS_BASED
)
14929 return default_cxx_get_cookie_size (type
);
14931 size
= build_int_cst (sizetype
, 8);
14936 /* The EABI says that array cookies should also contain the element size. */
14939 arm_cookie_has_size (void)
14941 return TARGET_AAPCS_BASED
;
14945 /* The EABI says constructors and destructors should return a pointer to
14946 the object constructed/destroyed. */
14949 arm_cxx_cdtor_returns_this (void)
14951 return TARGET_AAPCS_BASED
;
14954 /* The EABI says that an inline function may never be the key
14958 arm_cxx_key_method_may_be_inline (void)
14960 return !TARGET_AAPCS_BASED
;
14964 arm_cxx_determine_class_data_visibility (tree decl
)
14966 if (!TARGET_AAPCS_BASED
)
14969 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14970 is exported. However, on systems without dynamic vague linkage,
14971 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14972 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
14973 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
14975 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
14976 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
14980 arm_cxx_class_data_always_comdat (void)
14982 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14983 vague linkage if the class has no key function. */
14984 return !TARGET_AAPCS_BASED
;
14988 /* The EABI says __aeabi_atexit should be used to register static
14992 arm_cxx_use_aeabi_atexit (void)
14994 return TARGET_AAPCS_BASED
;
14999 arm_set_return_address (rtx source
, rtx scratch
)
15001 arm_stack_offsets
*offsets
;
15002 HOST_WIDE_INT delta
;
15004 unsigned long saved_regs
;
15006 saved_regs
= arm_compute_save_reg_mask ();
15008 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
15009 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15012 if (frame_pointer_needed
)
15013 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
15016 /* LR will be the first saved register. */
15017 offsets
= arm_get_frame_offsets ();
15018 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15023 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15024 GEN_INT (delta
& ~4095)));
15029 addr
= stack_pointer_rtx
;
15031 addr
= plus_constant (addr
, delta
);
15033 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15039 thumb_set_return_address (rtx source
, rtx scratch
)
15041 arm_stack_offsets
*offsets
;
15042 HOST_WIDE_INT delta
;
15045 unsigned long mask
;
15047 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15049 mask
= thumb_compute_save_reg_mask ();
15050 if (mask
& (1 << LR_REGNUM
))
15052 offsets
= arm_get_frame_offsets ();
15054 /* Find the saved regs. */
15055 if (frame_pointer_needed
)
15057 delta
= offsets
->soft_frame
- offsets
->saved_args
;
15058 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
15062 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
15065 /* Allow for the stack frame. */
15066 if (TARGET_BACKTRACE
)
15068 /* The link register is always the first saved register. */
15071 /* Construct the address. */
15072 addr
= gen_rtx_REG (SImode
, reg
);
15073 if ((reg
!= SP_REGNUM
&& delta
>= 128)
15076 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
15077 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
15081 addr
= plus_constant (addr
, delta
);
15083 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15086 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15089 /* Implements target hook vector_mode_supported_p. */
15091 arm_vector_mode_supported_p (enum machine_mode mode
)
15093 if ((mode
== V2SImode
)
15094 || (mode
== V4HImode
)
15095 || (mode
== V8QImode
))
15101 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15102 ARM insns and therefore guarantee that the shift count is modulo 256.
15103 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15104 guarantee no particular behavior for out-of-range counts. */
15106 static unsigned HOST_WIDE_INT
15107 arm_shift_truncation_mask (enum machine_mode mode
)
15109 return mode
== SImode
? 255 : 0;
15113 /* Map internal gcc register numbers to DWARF2 register numbers. */
15116 arm_dbx_register_number (unsigned int regno
)
15121 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15122 compatibility. The EABI defines them as registers 96-103. */
15123 if (IS_FPA_REGNUM (regno
))
15124 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
15126 if (IS_VFP_REGNUM (regno
))
15127 return 64 + regno
- FIRST_VFP_REGNUM
;
15129 if (IS_IWMMXT_GR_REGNUM (regno
))
15130 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
15132 if (IS_IWMMXT_REGNUM (regno
))
15133 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
15135 gcc_unreachable ();
15139 #ifdef TARGET_UNWIND_INFO
15140 /* Emit unwind directives for a store-multiple instruction. This should
15141 only ever be generated by the function prologue code, so we expect it
15142 to have a particular form. */
15145 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
15148 HOST_WIDE_INT offset
;
15149 HOST_WIDE_INT nregs
;
15155 /* First insn will adjust the stack pointer. */
15156 e
= XVECEXP (p
, 0, 0);
15157 if (GET_CODE (e
) != SET
15158 || GET_CODE (XEXP (e
, 0)) != REG
15159 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15160 || GET_CODE (XEXP (e
, 1)) != PLUS
)
15163 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
15164 nregs
= XVECLEN (p
, 0) - 1;
15166 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
15169 /* The function prologue may also push pc, but not annotate it as it is
15170 never restored. We turn this into a stack pointer adjustment. */
15171 if (nregs
* 4 == offset
- 4)
15173 fprintf (asm_out_file
, "\t.pad #4\n");
15178 else if (IS_VFP_REGNUM (reg
))
15180 /* FPA register saves use an additional word. */
15184 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
15186 /* FPA registers are done differently. */
15187 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
15191 /* Unknown register type. */
15194 /* If the stack increment doesn't match the size of the saved registers,
15195 something has gone horribly wrong. */
15196 if (offset
!= nregs
* reg_size
)
15199 fprintf (asm_out_file
, "\t.save {");
15203 /* The remaining insns will describe the stores. */
15204 for (i
= 1; i
<= nregs
; i
++)
15206 /* Expect (set (mem <addr>) (reg)).
15207 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15208 e
= XVECEXP (p
, 0, i
);
15209 if (GET_CODE (e
) != SET
15210 || GET_CODE (XEXP (e
, 0)) != MEM
15211 || GET_CODE (XEXP (e
, 1)) != REG
)
15214 reg
= REGNO (XEXP (e
, 1));
15219 fprintf (asm_out_file
, ", ");
15220 /* We can't use %r for vfp because we need to use the
15221 double precision register names. */
15222 if (IS_VFP_REGNUM (reg
))
15223 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
15225 asm_fprintf (asm_out_file
, "%r", reg
);
15227 #ifdef ENABLE_CHECKING
15228 /* Check that the addresses are consecutive. */
15229 e
= XEXP (XEXP (e
, 0), 0);
15230 if (GET_CODE (e
) == PLUS
)
15232 offset
+= reg_size
;
15233 if (GET_CODE (XEXP (e
, 0)) != REG
15234 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15235 || GET_CODE (XEXP (e
, 1)) != CONST_INT
15236 || offset
!= INTVAL (XEXP (e
, 1)))
15240 || GET_CODE (e
) != REG
15241 || REGNO (e
) != SP_REGNUM
)
15245 fprintf (asm_out_file
, "}\n");
15248 /* Emit unwind directives for a SET. */
15251 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
15258 switch (GET_CODE (e0
))
15261 /* Pushing a single register. */
15262 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
15263 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
15264 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
15267 asm_fprintf (asm_out_file
, "\t.save ");
15268 if (IS_VFP_REGNUM (REGNO (e1
)))
15269 asm_fprintf(asm_out_file
, "{d%d}\n",
15270 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
15272 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
15276 if (REGNO (e0
) == SP_REGNUM
)
15278 /* A stack increment. */
15279 if (GET_CODE (e1
) != PLUS
15280 || GET_CODE (XEXP (e1
, 0)) != REG
15281 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
15282 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15285 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
15286 -INTVAL (XEXP (e1
, 1)));
15288 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
15290 HOST_WIDE_INT offset
;
15293 if (GET_CODE (e1
) == PLUS
)
15295 if (GET_CODE (XEXP (e1
, 0)) != REG
15296 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15298 reg
= REGNO (XEXP (e1
, 0));
15299 offset
= INTVAL (XEXP (e1
, 1));
15300 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
15301 HARD_FRAME_POINTER_REGNUM
, reg
,
15302 INTVAL (XEXP (e1
, 1)));
15304 else if (GET_CODE (e1
) == REG
)
15307 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
15308 HARD_FRAME_POINTER_REGNUM
, reg
);
15313 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
15315 /* Move from sp to reg. */
15316 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
15328 /* Emit unwind directives for the given insn. */
15331 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
15335 if (!ARM_EABI_UNWIND_TABLES
)
15338 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
15341 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
15343 pat
= XEXP (pat
, 0);
15345 pat
= PATTERN (insn
);
15347 switch (GET_CODE (pat
))
15350 arm_unwind_emit_set (asm_out_file
, pat
);
15354 /* Store multiple. */
15355 arm_unwind_emit_stm (asm_out_file
, pat
);
15364 /* Output a reference from a function exception table to the type_info
15365 object X. The EABI specifies that the symbol should be relocated by
15366 an R_ARM_TARGET2 relocation. */
15369 arm_output_ttype (rtx x
)
15371 fputs ("\t.word\t", asm_out_file
);
15372 output_addr_const (asm_out_file
, x
);
15373 /* Use special relocations for symbol references. */
15374 if (GET_CODE (x
) != CONST_INT
)
15375 fputs ("(TARGET2)", asm_out_file
);
15376 fputc ('\n', asm_out_file
);
15380 #endif /* TARGET_UNWIND_INFO */
15383 /* Output unwind directives for the start/end of a function. */
15386 arm_output_fn_unwind (FILE * f
, bool prologue
)
15388 if (!ARM_EABI_UNWIND_TABLES
)
15392 fputs ("\t.fnstart\n", f
);
15394 fputs ("\t.fnend\n", f
);
15398 arm_emit_tls_decoration (FILE *fp
, rtx x
)
15400 enum tls_reloc reloc
;
15403 val
= XVECEXP (x
, 0, 0);
15404 reloc
= INTVAL (XVECEXP (x
, 0, 1));
15406 output_addr_const (fp
, val
);
15411 fputs ("(tlsgd)", fp
);
15414 fputs ("(tlsldm)", fp
);
15417 fputs ("(tlsldo)", fp
);
15420 fputs ("(gottpoff)", fp
);
15423 fputs ("(tpoff)", fp
);
15426 gcc_unreachable ();
15434 fputs (" + (. - ", fp
);
15435 output_addr_const (fp
, XVECEXP (x
, 0, 2));
15437 output_addr_const (fp
, XVECEXP (x
, 0, 3));
15448 arm_output_addr_const_extra (FILE *fp
, rtx x
)
15450 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
15451 return arm_emit_tls_decoration (fp
, x
);
15452 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
15455 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
15457 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
15458 assemble_name_raw (fp
, label
);
15462 else if (GET_CODE (x
) == CONST_VECTOR
)
15463 return arm_emit_vector_const (fp
, x
);
15468 #include "gt-arm.h"