1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb2_legitimate_index_p (enum machine_mode
, rtx
, int);
71 static int thumb1_base_register_rtx_p (rtx
, enum machine_mode
, int);
72 inline static int thumb1_index_register_rtx_p (rtx
, int);
73 static int thumb_far_jump_used_p (void);
74 static bool thumb_force_lr_save (void);
75 static unsigned long thumb1_compute_save_reg_mask (void);
76 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
77 static rtx
emit_sfm (int, int);
78 static int arm_size_return_regs (void);
80 static bool arm_assemble_integer (rtx
, unsigned int, int);
82 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
83 static arm_cc
get_arm_condition_code (rtx
);
84 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
85 static rtx
is_jump_table (rtx
);
86 static const char *output_multi_immediate (rtx
*, const char *, const char *,
88 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
89 static struct machine_function
*arm_init_machine_status (void);
90 static void thumb_exit (FILE *, int);
91 static rtx
is_jump_table (rtx
);
92 static HOST_WIDE_INT
get_jump_table_size (rtx
);
93 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_forward_ref (Mfix
*);
95 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
96 static Mnode
*add_minipool_backward_ref (Mfix
*);
97 static void assign_minipool_offsets (Mfix
*);
98 static void arm_print_value (FILE *, rtx
);
99 static void dump_minipool (rtx
);
100 static int arm_barrier_cost (rtx
);
101 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
102 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
103 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
107 static int current_file_function_operand (rtx
);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree
);
111 static unsigned long arm_compute_func_type (void);
112 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
113 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
114 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
115 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
119 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT
);
120 static int arm_comp_type_attributes (tree
, tree
);
121 static void arm_set_default_type_attributes (tree
);
122 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
123 static int count_insns_for_constant (HOST_WIDE_INT
, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree
, tree
);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
129 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
130 static bool arm_size_rtx_costs (rtx
, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
135 static int arm_address_cost (rtx
);
136 static bool arm_memory_load_p (rtx
);
137 static bool arm_cirrus_insn_p (rtx
);
138 static void cirrus_reorg (rtx
);
139 static void arm_init_builtins (void);
140 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
143 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
144 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
145 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
146 static void emit_constant_insn (rtx cond
, rtx pattern
);
147 static rtx
emit_set_insn (rtx
, rtx
);
148 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
151 #ifdef OBJECT_FORMAT_ELF
152 static void arm_elf_asm_constructor (rtx
, int);
155 static void arm_encode_section_info (tree
, rtx
, int);
158 static void arm_file_end (void);
159 static void arm_file_start (void);
162 static void aof_globalize_label (FILE *, const char *);
163 static void aof_dump_imports (FILE *);
164 static void aof_dump_pic_table (FILE *);
165 static void aof_file_start (void);
166 static void aof_file_end (void);
167 static void aof_asm_init_sections (void);
169 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
171 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
172 enum machine_mode
, tree
, bool);
173 static bool arm_promote_prototypes (tree
);
174 static bool arm_default_short_enums (void);
175 static bool arm_align_anon_bitfield (void);
176 static bool arm_return_in_msb (tree
);
177 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
178 #ifdef TARGET_UNWIND_INFO
179 static void arm_unwind_emit (FILE *, rtx
);
180 static bool arm_output_ttype (rtx
);
182 static void arm_dwarf_handle_frame_unspec (const char *, rtx
, int);
184 static tree
arm_cxx_guard_type (void);
185 static bool arm_cxx_guard_mask_bit (void);
186 static tree
arm_get_cookie_size (tree
);
187 static bool arm_cookie_has_size (void);
188 static bool arm_cxx_cdtor_returns_this (void);
189 static bool arm_cxx_key_method_may_be_inline (void);
190 static void arm_cxx_determine_class_data_visibility (tree
);
191 static bool arm_cxx_class_data_always_comdat (void);
192 static bool arm_cxx_use_aeabi_atexit (void);
193 static void arm_init_libfuncs (void);
194 static bool arm_handle_option (size_t, const char *, int);
195 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
196 static bool arm_cannot_copy_insn_p (rtx
);
197 static bool arm_tls_symbol_p (rtx x
);
200 /* Initialize the GCC target structure. */
201 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
202 #undef TARGET_MERGE_DECL_ATTRIBUTES
203 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
209 #undef TARGET_ASM_FILE_START
210 #define TARGET_ASM_FILE_START arm_file_start
211 #undef TARGET_ASM_FILE_END
212 #define TARGET_ASM_FILE_END arm_file_end
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tDCB\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
221 #undef TARGET_ASM_GLOBALIZE_LABEL
222 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
223 #undef TARGET_ASM_FILE_START
224 #define TARGET_ASM_FILE_START aof_file_start
225 #undef TARGET_ASM_FILE_END
226 #define TARGET_ASM_FILE_END aof_file_end
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP NULL
230 #undef TARGET_ASM_INTEGER
231 #define TARGET_ASM_INTEGER arm_assemble_integer
234 #undef TARGET_ASM_FUNCTION_PROLOGUE
235 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
237 #undef TARGET_ASM_FUNCTION_EPILOGUE
238 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
240 #undef TARGET_DEFAULT_TARGET_FLAGS
241 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
242 #undef TARGET_HANDLE_OPTION
243 #define TARGET_HANDLE_OPTION arm_handle_option
245 #undef TARGET_COMP_TYPE_ATTRIBUTES
246 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
248 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
249 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
251 #undef TARGET_SCHED_ADJUST_COST
252 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
254 #undef TARGET_ENCODE_SECTION_INFO
256 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
258 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
261 #undef TARGET_STRIP_NAME_ENCODING
262 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
264 #undef TARGET_ASM_INTERNAL_LABEL
265 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
267 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
268 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
270 #undef TARGET_ASM_OUTPUT_MI_THUNK
271 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
272 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
273 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
275 /* This will be overridden in arm_override_options. */
276 #undef TARGET_RTX_COSTS
277 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
278 #undef TARGET_ADDRESS_COST
279 #define TARGET_ADDRESS_COST arm_address_cost
281 #undef TARGET_SHIFT_TRUNCATION_MASK
282 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
283 #undef TARGET_VECTOR_MODE_SUPPORTED_P
284 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
286 #undef TARGET_MACHINE_DEPENDENT_REORG
287 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
289 #undef TARGET_INIT_BUILTINS
290 #define TARGET_INIT_BUILTINS arm_init_builtins
291 #undef TARGET_EXPAND_BUILTIN
292 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
294 #undef TARGET_INIT_LIBFUNCS
295 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
297 #undef TARGET_PROMOTE_FUNCTION_ARGS
298 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
299 #undef TARGET_PROMOTE_FUNCTION_RETURN
300 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
301 #undef TARGET_PROMOTE_PROTOTYPES
302 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
303 #undef TARGET_PASS_BY_REFERENCE
304 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
305 #undef TARGET_ARG_PARTIAL_BYTES
306 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
308 #undef TARGET_SETUP_INCOMING_VARARGS
309 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
311 #undef TARGET_DEFAULT_SHORT_ENUMS
312 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
314 #undef TARGET_ALIGN_ANON_BITFIELD
315 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
317 #undef TARGET_NARROW_VOLATILE_BITFIELD
318 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
320 #undef TARGET_CXX_GUARD_TYPE
321 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
323 #undef TARGET_CXX_GUARD_MASK_BIT
324 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
326 #undef TARGET_CXX_GET_COOKIE_SIZE
327 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
329 #undef TARGET_CXX_COOKIE_HAS_SIZE
330 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
332 #undef TARGET_CXX_CDTOR_RETURNS_THIS
333 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
335 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
336 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
338 #undef TARGET_CXX_USE_AEABI_ATEXIT
339 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
341 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
342 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
343 arm_cxx_determine_class_data_visibility
345 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
346 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
348 #undef TARGET_RETURN_IN_MSB
349 #define TARGET_RETURN_IN_MSB arm_return_in_msb
351 #undef TARGET_MUST_PASS_IN_STACK
352 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
354 #ifdef TARGET_UNWIND_INFO
355 #undef TARGET_UNWIND_EMIT
356 #define TARGET_UNWIND_EMIT arm_unwind_emit
358 /* EABI unwinding tables use a different format for the typeinfo tables. */
359 #undef TARGET_ASM_TTYPE
360 #define TARGET_ASM_TTYPE arm_output_ttype
362 #undef TARGET_ARM_EABI_UNWINDER
363 #define TARGET_ARM_EABI_UNWINDER true
364 #endif /* TARGET_UNWIND_INFO */
366 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
367 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
369 #undef TARGET_CANNOT_COPY_INSN_P
370 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
373 #undef TARGET_HAVE_TLS
374 #define TARGET_HAVE_TLS true
377 #undef TARGET_CANNOT_FORCE_CONST_MEM
378 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
380 struct gcc_target targetm
= TARGET_INITIALIZER
;
382 /* Obstack for minipool constant handling. */
383 static struct obstack minipool_obstack
;
384 static char * minipool_startobj
;
386 /* The maximum number of insns skipped which
387 will be conditionalised if possible. */
388 static int max_insns_skipped
= 5;
390 extern FILE * asm_out_file
;
392 /* True if we are currently building a constant table. */
393 int making_const_table
;
395 /* Define the information needed to generate branch insns. This is
396 stored from the compare operation. */
397 rtx arm_compare_op0
, arm_compare_op1
;
399 /* The processor for which instructions should be scheduled. */
400 enum processor_type arm_tune
= arm_none
;
402 /* The default processor used if not overridden by commandline. */
403 static enum processor_type arm_default_cpu
= arm_none
;
405 /* Which floating point model to use. */
406 enum arm_fp_model arm_fp_model
;
408 /* Which floating point hardware is available. */
409 enum fputype arm_fpu_arch
;
411 /* Which floating point hardware to schedule for. */
412 enum fputype arm_fpu_tune
;
414 /* Whether to use floating point hardware. */
415 enum float_abi_type arm_float_abi
;
417 /* Which ABI to use. */
418 enum arm_abi_type arm_abi
;
420 /* Which thread pointer model to use. */
421 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
423 /* Used to parse -mstructure_size_boundary command line option. */
424 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
426 /* Used for Thumb call_via trampolines. */
427 rtx thumb_call_via_label
[14];
428 static int thumb_call_reg_needed
;
430 /* Bit values used to identify processor capabilities. */
431 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
432 #define FL_ARCH3M (1 << 1) /* Extended multiply */
433 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
434 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
435 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
436 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
437 #define FL_THUMB (1 << 6) /* Thumb aware */
438 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
439 #define FL_STRONG (1 << 8) /* StrongARM */
440 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
441 #define FL_XSCALE (1 << 10) /* XScale */
442 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
443 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
444 media instructions. */
445 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
446 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
447 Note: ARM6 & 7 derivatives only. */
448 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
449 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
450 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
452 #define FL_DIV (1 << 18) /* Hardware divde. */
454 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
456 #define FL_FOR_ARCH2 FL_NOTM
457 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
458 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
459 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
460 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
461 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
462 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
463 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
464 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
465 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
466 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
467 #define FL_FOR_ARCH6J FL_FOR_ARCH6
468 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
469 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
470 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
471 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
472 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
473 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
474 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
475 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
477 /* The bits in this mask specify which
478 instructions we are allowed to generate. */
479 static unsigned long insn_flags
= 0;
481 /* The bits in this mask specify which instruction scheduling options should
483 static unsigned long tune_flags
= 0;
485 /* The following are used in the arm.md file as equivalents to bits
486 in the above two flag variables. */
488 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
491 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
494 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
497 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
500 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
503 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
506 /* Nonzero if this chip supports the ARM 6K extensions. */
509 /* Nonzero if instructions not present in the 'M' profile can be used. */
510 int arm_arch_notm
= 0;
512 /* Nonzero if this chip can benefit from load scheduling. */
513 int arm_ld_sched
= 0;
515 /* Nonzero if this chip is a StrongARM. */
516 int arm_tune_strongarm
= 0;
518 /* Nonzero if this chip is a Cirrus variant. */
519 int arm_arch_cirrus
= 0;
521 /* Nonzero if this chip supports Intel Wireless MMX technology. */
522 int arm_arch_iwmmxt
= 0;
524 /* Nonzero if this chip is an XScale. */
525 int arm_arch_xscale
= 0;
527 /* Nonzero if tuning for XScale */
528 int arm_tune_xscale
= 0;
530 /* Nonzero if we want to tune for stores that access the write-buffer.
531 This typically means an ARM6 or ARM7 with MMU or MPU. */
532 int arm_tune_wbuf
= 0;
534 /* Nonzero if generating Thumb instructions. */
537 /* Nonzero if we should define __THUMB_INTERWORK__ in the
539 XXX This is a bit of a hack, it's intended to help work around
540 problems in GLD which doesn't understand that armv5t code is
541 interworking clean. */
542 int arm_cpp_interwork
= 0;
544 /* Nonzero if chip supports Thumb 2. */
547 /* Nonzero if chip supports integer division instruction. */
550 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
551 must report the mode of the memory reference from PRINT_OPERAND to
552 PRINT_OPERAND_ADDRESS. */
553 enum machine_mode output_memory_reference_mode
;
555 /* The register number to be used for the PIC offset register. */
556 unsigned arm_pic_register
= INVALID_REGNUM
;
558 /* Set to 1 when a return insn is output, this means that the epilogue
560 int return_used_this_function
;
562 /* Set to 1 after arm_reorg has started. Reset to start at the start of
563 the next function. */
564 static int after_arm_reorg
= 0;
566 /* The maximum number of insns to be used when loading a constant. */
567 static int arm_constant_limit
= 3;
569 /* For an explanation of these variables, see final_prescan_insn below. */
571 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
572 enum arm_cond_code arm_current_cc
;
574 int arm_target_label
;
575 /* The number of conditionally executed insns, including the current insn. */
576 int arm_condexec_count
= 0;
577 /* A bitmask specifying the patterns for the IT block.
578 Zero means do not output an IT block before this insn. */
579 int arm_condexec_mask
= 0;
580 /* The number of bits used in arm_condexec_mask. */
581 int arm_condexec_masklen
= 0;
583 /* The condition codes of the ARM, and the inverse function. */
584 static const char * const arm_condition_codes
[] =
586 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
587 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
590 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
591 #define streq(string1, string2) (strcmp (string1, string2) == 0)
593 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
594 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
595 | (1 << PIC_OFFSET_TABLE_REGNUM)))
597 /* Initialization code. */
601 const char *const name
;
602 enum processor_type core
;
604 const unsigned long flags
;
605 bool (* rtx_costs
) (rtx
, int, int, int *);
608 /* Not all of these give usefully different compilation alternatives,
609 but there is no simple way of generalizing them. */
610 static const struct processors all_cores
[] =
613 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
614 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
615 #include "arm-cores.def"
617 {NULL
, arm_none
, NULL
, 0, NULL
}
620 static const struct processors all_architectures
[] =
622 /* ARM Architectures */
623 /* We don't specify rtx_costs here as it will be figured out
626 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
627 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
628 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
629 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
630 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
631 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
632 implementations that support it, so we will leave it out for now. */
633 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
634 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
635 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
636 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
637 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
638 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
639 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
640 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
641 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
642 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
643 {"armv6t2", arm1156t2s
, "6T2", FL_CO_PROC
| FL_FOR_ARCH6T2
, NULL
},
644 {"armv7", cortexa8
, "7", FL_CO_PROC
| FL_FOR_ARCH7
, NULL
},
645 {"armv7-a", cortexa8
, "7A", FL_CO_PROC
| FL_FOR_ARCH7A
, NULL
},
646 {"armv7-r", cortexr4
, "7R", FL_CO_PROC
| FL_FOR_ARCH7R
, NULL
},
647 {"armv7-m", cortexm3
, "7M", FL_CO_PROC
| FL_FOR_ARCH7M
, NULL
},
648 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
649 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
650 {NULL
, arm_none
, NULL
, 0 , NULL
}
653 struct arm_cpu_select
657 const struct processors
* processors
;
660 /* This is a magic structure. The 'string' field is magically filled in
661 with a pointer to the value specified by the user on the command line
662 assuming that the user has specified such a value. */
664 static struct arm_cpu_select arm_select
[] =
666 /* string name processors */
667 { NULL
, "-mcpu=", all_cores
},
668 { NULL
, "-march=", all_architectures
},
669 { NULL
, "-mtune=", all_cores
}
672 /* Defines representing the indexes into the above table. */
673 #define ARM_OPT_SET_CPU 0
674 #define ARM_OPT_SET_ARCH 1
675 #define ARM_OPT_SET_TUNE 2
677 /* The name of the preprocessor macro to define for this architecture. */
679 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
688 /* Available values for -mfpu=. */
690 static const struct fpu_desc all_fpus
[] =
692 {"fpa", FPUTYPE_FPA
},
693 {"fpe2", FPUTYPE_FPA_EMU2
},
694 {"fpe3", FPUTYPE_FPA_EMU2
},
695 {"maverick", FPUTYPE_MAVERICK
},
700 /* Floating point models used by the different hardware.
701 See fputype in arm.h. */
703 static const enum fputype fp_model_for_fpu
[] =
705 /* No FP hardware. */
706 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
707 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
708 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
709 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
710 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
711 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
718 enum float_abi_type abi_type
;
722 /* Available values for -mfloat-abi=. */
724 static const struct float_abi all_float_abis
[] =
726 {"soft", ARM_FLOAT_ABI_SOFT
},
727 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
728 {"hard", ARM_FLOAT_ABI_HARD
}
735 enum arm_abi_type abi_type
;
739 /* Available values for -mabi=. */
741 static const struct abi_name arm_all_abis
[] =
743 {"apcs-gnu", ARM_ABI_APCS
},
744 {"atpcs", ARM_ABI_ATPCS
},
745 {"aapcs", ARM_ABI_AAPCS
},
746 {"iwmmxt", ARM_ABI_IWMMXT
},
747 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
750 /* Supported TLS relocations. */
760 /* Emit an insn that's a simple single-set. Both the operands must be known
763 emit_set_insn (rtx x
, rtx y
)
765 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
768 /* Return the number of bits set in VALUE. */
770 bit_count (unsigned long value
)
772 unsigned long count
= 0;
777 value
&= value
- 1; /* Clear the least-significant set bit. */
783 /* Set up library functions unique to ARM. */
786 arm_init_libfuncs (void)
788 /* There are no special library functions unless we are using the
793 /* The functions below are described in Section 4 of the "Run-Time
794 ABI for the ARM architecture", Version 1.0. */
796 /* Double-precision floating-point arithmetic. Table 2. */
797 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
798 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
799 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
800 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
801 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
803 /* Double-precision comparisons. Table 3. */
804 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
805 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
806 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
807 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
808 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
809 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
810 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
812 /* Single-precision floating-point arithmetic. Table 4. */
813 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
814 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
815 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
816 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
817 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
819 /* Single-precision comparisons. Table 5. */
820 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
821 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
822 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
823 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
824 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
825 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
826 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
828 /* Floating-point to integer conversions. Table 6. */
829 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
830 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
831 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
832 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
833 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
834 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
835 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
836 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
838 /* Conversions between floating types. Table 7. */
839 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
840 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
842 /* Integer to floating-point conversions. Table 8. */
843 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
844 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
845 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
846 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
847 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
848 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
849 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
850 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
852 /* Long long. Table 9. */
853 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
854 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
855 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
856 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
857 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
858 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
859 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
860 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
862 /* Integer (32/32->32) division. \S 4.3.1. */
863 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
864 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
866 /* The divmod functions are designed so that they can be used for
867 plain division, even though they return both the quotient and the
868 remainder. The quotient is returned in the usual location (i.e.,
869 r0 for SImode, {r0, r1} for DImode), just as would be expected
870 for an ordinary division routine. Because the AAPCS calling
871 conventions specify that all of { r0, r1, r2, r3 } are
872 callee-saved registers, there is no need to tell the compiler
873 explicitly that those registers are clobbered by these
875 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
876 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
878 /* For SImode division the ABI provides div-without-mod routines,
880 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
881 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
883 /* We don't have mod libcalls. Fortunately gcc knows how to use the
884 divmod libcalls instead. */
885 set_optab_libfunc (smod_optab
, DImode
, NULL
);
886 set_optab_libfunc (umod_optab
, DImode
, NULL
);
887 set_optab_libfunc (smod_optab
, SImode
, NULL
);
888 set_optab_libfunc (umod_optab
, SImode
, NULL
);
891 /* Implement TARGET_HANDLE_OPTION. */
894 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
899 arm_select
[1].string
= arg
;
903 arm_select
[0].string
= arg
;
906 case OPT_mhard_float
:
907 target_float_abi_name
= "hard";
910 case OPT_msoft_float
:
911 target_float_abi_name
= "soft";
915 arm_select
[2].string
= arg
;
923 /* Fix up any incompatible options that the user has specified.
924 This has now turned into a maze. */
926 arm_override_options (void)
929 enum processor_type target_arch_cpu
= arm_none
;
931 /* Set up the flags based on the cpu/architecture selected by the user. */
932 for (i
= ARRAY_SIZE (arm_select
); i
--;)
934 struct arm_cpu_select
* ptr
= arm_select
+ i
;
936 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
938 const struct processors
* sel
;
940 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
941 if (streq (ptr
->string
, sel
->name
))
943 /* Set the architecture define. */
944 if (i
!= ARM_OPT_SET_TUNE
)
945 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
947 /* Determine the processor core for which we should
948 tune code-generation. */
949 if (/* -mcpu= is a sensible default. */
951 /* -mtune= overrides -mcpu= and -march=. */
952 || i
== ARM_OPT_SET_TUNE
)
953 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
955 /* Remember the CPU associated with this architecture.
956 If no other option is used to set the CPU type,
957 we'll use this to guess the most suitable tuning
959 if (i
== ARM_OPT_SET_ARCH
)
960 target_arch_cpu
= sel
->core
;
962 if (i
!= ARM_OPT_SET_TUNE
)
964 /* If we have been given an architecture and a processor
965 make sure that they are compatible. We only generate
966 a warning though, and we prefer the CPU over the
968 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
969 warning (0, "switch -mcpu=%s conflicts with -march= switch",
972 insn_flags
= sel
->flags
;
978 if (sel
->name
== NULL
)
979 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
983 /* Guess the tuning options from the architecture if necessary. */
984 if (arm_tune
== arm_none
)
985 arm_tune
= target_arch_cpu
;
987 /* If the user did not specify a processor, choose one for them. */
990 const struct processors
* sel
;
992 enum processor_type cpu
;
994 cpu
= TARGET_CPU_DEFAULT
;
997 #ifdef SUBTARGET_CPU_DEFAULT
998 /* Use the subtarget default CPU if none was specified by
1000 cpu
= SUBTARGET_CPU_DEFAULT
;
1002 /* Default to ARM6. */
1003 if (cpu
== arm_none
)
1006 sel
= &all_cores
[cpu
];
1008 insn_flags
= sel
->flags
;
1010 /* Now check to see if the user has specified some command line
1011 switch that require certain abilities from the cpu. */
1014 if (TARGET_INTERWORK
|| TARGET_THUMB
)
1016 sought
|= (FL_THUMB
| FL_MODE32
);
1018 /* There are no ARM processors that support both APCS-26 and
1019 interworking. Therefore we force FL_MODE26 to be removed
1020 from insn_flags here (if it was set), so that the search
1021 below will always be able to find a compatible processor. */
1022 insn_flags
&= ~FL_MODE26
;
1025 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
1027 /* Try to locate a CPU type that supports all of the abilities
1028 of the default CPU, plus the extra abilities requested by
1030 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1031 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
1034 if (sel
->name
== NULL
)
1036 unsigned current_bit_count
= 0;
1037 const struct processors
* best_fit
= NULL
;
1039 /* Ideally we would like to issue an error message here
1040 saying that it was not possible to find a CPU compatible
1041 with the default CPU, but which also supports the command
1042 line options specified by the programmer, and so they
1043 ought to use the -mcpu=<name> command line option to
1044 override the default CPU type.
1046 If we cannot find a cpu that has both the
1047 characteristics of the default cpu and the given
1048 command line options we scan the array again looking
1049 for a best match. */
1050 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1051 if ((sel
->flags
& sought
) == sought
)
1055 count
= bit_count (sel
->flags
& insn_flags
);
1057 if (count
>= current_bit_count
)
1060 current_bit_count
= count
;
1064 gcc_assert (best_fit
);
1068 insn_flags
= sel
->flags
;
1070 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1071 arm_default_cpu
= (enum processor_type
) (sel
- all_cores
);
1072 if (arm_tune
== arm_none
)
1073 arm_tune
= arm_default_cpu
;
1076 /* The processor for which we should tune should now have been
1078 gcc_assert (arm_tune
!= arm_none
);
1080 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1082 targetm
.rtx_costs
= arm_size_rtx_costs
;
1084 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1086 /* Make sure that the processor choice does not conflict with any of the
1087 other command line choices. */
1088 if (TARGET_ARM
&& !(insn_flags
& FL_NOTM
))
1089 error ("target CPU does not support ARM mode");
1091 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1093 warning (0, "target CPU does not support interworking" );
1094 target_flags
&= ~MASK_INTERWORK
;
1097 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1099 warning (0, "target CPU does not support THUMB instructions");
1100 target_flags
&= ~MASK_THUMB
;
1103 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1105 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1106 target_flags
&= ~MASK_APCS_FRAME
;
1109 /* Callee super interworking implies thumb interworking. Adding
1110 this to the flags here simplifies the logic elsewhere. */
1111 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1112 target_flags
|= MASK_INTERWORK
;
1114 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1115 from here where no function is being compiled currently. */
1116 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1117 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1119 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1120 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1122 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1123 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1125 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1127 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1128 target_flags
|= MASK_APCS_FRAME
;
1131 if (TARGET_POKE_FUNCTION_NAME
)
1132 target_flags
|= MASK_APCS_FRAME
;
1134 if (TARGET_APCS_REENT
&& flag_pic
)
1135 error ("-fpic and -mapcs-reent are incompatible");
1137 if (TARGET_APCS_REENT
)
1138 warning (0, "APCS reentrant code not supported. Ignored");
1140 /* If this target is normally configured to use APCS frames, warn if they
1141 are turned off and debugging is turned on. */
1143 && write_symbols
!= NO_DEBUG
1144 && !TARGET_APCS_FRAME
1145 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1146 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1148 /* If stack checking is disabled, we can use r10 as the PIC register,
1149 which keeps r9 available. */
1150 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
1151 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1153 if (TARGET_APCS_FLOAT
)
1154 warning (0, "passing floating point arguments in fp regs not yet supported");
1156 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1157 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1158 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1159 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1160 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1161 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1162 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1163 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1164 arm_arch_notm
= (insn_flags
& FL_NOTM
) != 0;
1165 arm_arch_thumb2
= (insn_flags
& FL_THUMB2
) != 0;
1166 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1167 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1169 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1170 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1171 thumb_code
= (TARGET_ARM
== 0);
1172 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1173 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1174 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1175 arm_arch_hwdiv
= (insn_flags
& FL_DIV
) != 0;
1177 /* V5 code we generate is completely interworking capable, so we turn off
1178 TARGET_INTERWORK here to avoid many tests later on. */
1180 /* XXX However, we must pass the right pre-processor defines to CPP
1181 or GLD can get confused. This is a hack. */
1182 if (TARGET_INTERWORK
)
1183 arm_cpp_interwork
= 1;
1186 target_flags
&= ~MASK_INTERWORK
;
1188 if (target_abi_name
)
1190 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1192 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1194 arm_abi
= arm_all_abis
[i
].abi_type
;
1198 if (i
== ARRAY_SIZE (arm_all_abis
))
1199 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1202 arm_abi
= ARM_DEFAULT_ABI
;
1204 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1205 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1207 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1208 error ("iwmmxt abi requires an iwmmxt capable cpu");
1210 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1211 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1213 if (streq (target_fpe_name
, "2"))
1214 target_fpu_name
= "fpe2";
1215 else if (streq (target_fpe_name
, "3"))
1216 target_fpu_name
= "fpe3";
1218 error ("invalid floating point emulation option: -mfpe=%s",
1221 if (target_fpu_name
!= NULL
)
1223 /* The user specified a FPU. */
1224 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1226 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1228 arm_fpu_arch
= all_fpus
[i
].fpu
;
1229 arm_fpu_tune
= arm_fpu_arch
;
1230 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1234 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1235 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1239 #ifdef FPUTYPE_DEFAULT
1240 /* Use the default if it is specified for this platform. */
1241 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1242 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1244 /* Pick one based on CPU type. */
1245 /* ??? Some targets assume FPA is the default.
1246 if ((insn_flags & FL_VFP) != 0)
1247 arm_fpu_arch = FPUTYPE_VFP;
1250 if (arm_arch_cirrus
)
1251 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1253 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1255 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1256 arm_fpu_tune
= FPUTYPE_FPA
;
1258 arm_fpu_tune
= arm_fpu_arch
;
1259 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1260 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1263 if (target_float_abi_name
!= NULL
)
1265 /* The user specified a FP ABI. */
1266 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1268 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1270 arm_float_abi
= all_float_abis
[i
].abi_type
;
1274 if (i
== ARRAY_SIZE (all_float_abis
))
1275 error ("invalid floating point abi: -mfloat-abi=%s",
1276 target_float_abi_name
);
1279 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1281 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1282 sorry ("-mfloat-abi=hard and VFP");
1284 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1285 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1286 will ever exist. GCC makes no attempt to support this combination. */
1287 if (TARGET_IWMMXT
&& !TARGET_SOFT_FLOAT
)
1288 sorry ("iWMMXt and hardware floating point");
1290 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1291 if (TARGET_THUMB2
&& TARGET_IWMMXT
)
1292 sorry ("Thumb-2 iWMMXt");
1294 /* If soft-float is specified then don't use FPU. */
1295 if (TARGET_SOFT_FLOAT
)
1296 arm_fpu_arch
= FPUTYPE_NONE
;
1298 /* For arm2/3 there is no need to do any scheduling if there is only
1299 a floating point emulator, or we are doing software floating-point. */
1300 if ((TARGET_SOFT_FLOAT
1301 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1302 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1303 && (tune_flags
& FL_MODE32
) == 0)
1304 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1306 if (target_thread_switch
)
1308 if (strcmp (target_thread_switch
, "soft") == 0)
1309 target_thread_pointer
= TP_SOFT
;
1310 else if (strcmp (target_thread_switch
, "auto") == 0)
1311 target_thread_pointer
= TP_AUTO
;
1312 else if (strcmp (target_thread_switch
, "cp15") == 0)
1313 target_thread_pointer
= TP_CP15
;
1315 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1318 /* Use the cp15 method if it is available. */
1319 if (target_thread_pointer
== TP_AUTO
)
1321 if (arm_arch6k
&& !TARGET_THUMB
)
1322 target_thread_pointer
= TP_CP15
;
1324 target_thread_pointer
= TP_SOFT
;
1327 if (TARGET_HARD_TP
&& TARGET_THUMB1
)
1328 error ("can not use -mtp=cp15 with 16-bit Thumb");
1330 /* Override the default structure alignment for AAPCS ABI. */
1331 if (TARGET_AAPCS_BASED
)
1332 arm_structure_size_boundary
= 8;
1334 if (structure_size_string
!= NULL
)
1336 int size
= strtol (structure_size_string
, NULL
, 0);
1338 if (size
== 8 || size
== 32
1339 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1340 arm_structure_size_boundary
= size
;
1342 warning (0, "structure size boundary can only be set to %s",
1343 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1346 if (arm_pic_register_string
!= NULL
)
1348 int pic_register
= decode_reg_name (arm_pic_register_string
);
1351 warning (0, "-mpic-register= is useless without -fpic");
1353 /* Prevent the user from choosing an obviously stupid PIC register. */
1354 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1355 || pic_register
== HARD_FRAME_POINTER_REGNUM
1356 || pic_register
== STACK_POINTER_REGNUM
1357 || pic_register
>= PC_REGNUM
)
1358 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1360 arm_pic_register
= pic_register
;
1363 /* ??? We might want scheduling for thumb2. */
1364 if (TARGET_THUMB
&& flag_schedule_insns
)
1366 /* Don't warn since it's on by default in -O2. */
1367 flag_schedule_insns
= 0;
1372 arm_constant_limit
= 1;
1374 /* If optimizing for size, bump the number of instructions that we
1375 are prepared to conditionally execute (even on a StrongARM). */
1376 max_insns_skipped
= 6;
1380 /* For processors with load scheduling, it never costs more than
1381 2 cycles to load a constant, and the load scheduler may well
1382 reduce that to 1. */
1384 arm_constant_limit
= 1;
1386 /* On XScale the longer latency of a load makes it more difficult
1387 to achieve a good schedule, so it's faster to synthesize
1388 constants that can be done in two insns. */
1389 if (arm_tune_xscale
)
1390 arm_constant_limit
= 2;
1392 /* StrongARM has early execution of branches, so a sequence
1393 that is worth skipping is shorter. */
1394 if (arm_tune_strongarm
)
1395 max_insns_skipped
= 3;
1398 /* Register global variables with the garbage collector. */
1399 arm_add_gc_roots ();
1403 arm_add_gc_roots (void)
1405 gcc_obstack_init(&minipool_obstack
);
1406 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1409 /* A table of known ARM exception types.
1410 For use with the interrupt function attribute. */
1414 const char *const arg
;
1415 const unsigned long return_value
;
1419 static const isr_attribute_arg isr_attribute_args
[] =
1421 { "IRQ", ARM_FT_ISR
},
1422 { "irq", ARM_FT_ISR
},
1423 { "FIQ", ARM_FT_FIQ
},
1424 { "fiq", ARM_FT_FIQ
},
1425 { "ABORT", ARM_FT_ISR
},
1426 { "abort", ARM_FT_ISR
},
1427 { "ABORT", ARM_FT_ISR
},
1428 { "abort", ARM_FT_ISR
},
1429 { "UNDEF", ARM_FT_EXCEPTION
},
1430 { "undef", ARM_FT_EXCEPTION
},
1431 { "SWI", ARM_FT_EXCEPTION
},
1432 { "swi", ARM_FT_EXCEPTION
},
1433 { NULL
, ARM_FT_NORMAL
}
1436 /* Returns the (interrupt) function type of the current
1437 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1439 static unsigned long
1440 arm_isr_value (tree argument
)
1442 const isr_attribute_arg
* ptr
;
1446 return ARM_FT_NORMAL
| ARM_FT_STACKALIGN
;
1448 /* No argument - default to IRQ. */
1449 if (argument
== NULL_TREE
)
1452 /* Get the value of the argument. */
1453 if (TREE_VALUE (argument
) == NULL_TREE
1454 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1455 return ARM_FT_UNKNOWN
;
1457 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1459 /* Check it against the list of known arguments. */
1460 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1461 if (streq (arg
, ptr
->arg
))
1462 return ptr
->return_value
;
1464 /* An unrecognized interrupt type. */
1465 return ARM_FT_UNKNOWN
;
1468 /* Computes the type of the current function. */
1470 static unsigned long
1471 arm_compute_func_type (void)
1473 unsigned long type
= ARM_FT_UNKNOWN
;
1477 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1479 /* Decide if the current function is volatile. Such functions
1480 never return, and many memory cycles can be saved by not storing
1481 register values that will never be needed again. This optimization
1482 was added to speed up context switching in a kernel application. */
1484 && (TREE_NOTHROW (current_function_decl
)
1485 || !(flag_unwind_tables
1486 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
)))
1487 && TREE_THIS_VOLATILE (current_function_decl
))
1488 type
|= ARM_FT_VOLATILE
;
1490 if (cfun
->static_chain_decl
!= NULL
)
1491 type
|= ARM_FT_NESTED
;
1493 attr
= DECL_ATTRIBUTES (current_function_decl
);
1495 a
= lookup_attribute ("naked", attr
);
1497 type
|= ARM_FT_NAKED
;
1499 a
= lookup_attribute ("isr", attr
);
1501 a
= lookup_attribute ("interrupt", attr
);
1504 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1506 type
|= arm_isr_value (TREE_VALUE (a
));
1511 /* Returns the type of the current function. */
1514 arm_current_func_type (void)
1516 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1517 cfun
->machine
->func_type
= arm_compute_func_type ();
1519 return cfun
->machine
->func_type
;
1522 /* Return 1 if it is possible to return using a single instruction.
1523 If SIBLING is non-null, this is a test for a return before a sibling
1524 call. SIBLING is the call insn, so we can examine its register usage. */
1527 use_return_insn (int iscond
, rtx sibling
)
1530 unsigned int func_type
;
1531 unsigned long saved_int_regs
;
1532 unsigned HOST_WIDE_INT stack_adjust
;
1533 arm_stack_offsets
*offsets
;
1535 /* Never use a return instruction before reload has run. */
1536 if (!reload_completed
)
1539 func_type
= arm_current_func_type ();
1541 /* Naked, volatile and stack alignment functions need special
1543 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
| ARM_FT_STACKALIGN
))
1546 /* So do interrupt functions that use the frame pointer. */
1547 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1550 offsets
= arm_get_frame_offsets ();
1551 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1553 /* As do variadic functions. */
1554 if (current_function_pretend_args_size
1555 || cfun
->machine
->uses_anonymous_args
1556 /* Or if the function calls __builtin_eh_return () */
1557 || current_function_calls_eh_return
1558 /* Or if the function calls alloca */
1559 || current_function_calls_alloca
1560 /* Or if there is a stack adjustment. However, if the stack pointer
1561 is saved on the stack, we can use a pre-incrementing stack load. */
1562 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1565 saved_int_regs
= arm_compute_save_reg_mask ();
1567 /* Unfortunately, the insn
1569 ldmib sp, {..., sp, ...}
1571 triggers a bug on most SA-110 based devices, such that the stack
1572 pointer won't be correctly restored if the instruction takes a
1573 page fault. We work around this problem by popping r3 along with
1574 the other registers, since that is never slower than executing
1575 another instruction.
1577 We test for !arm_arch5 here, because code for any architecture
1578 less than this could potentially be run on one of the buggy
1580 if (stack_adjust
== 4 && !arm_arch5
&& TARGET_ARM
)
1582 /* Validate that r3 is a call-clobbered register (always true in
1583 the default abi) ... */
1584 if (!call_used_regs
[3])
1587 /* ... that it isn't being used for a return value ... */
1588 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1591 /* ... or for a tail-call argument ... */
1594 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1596 if (find_regno_fusage (sibling
, USE
, 3))
1600 /* ... and that there are no call-saved registers in r0-r2
1601 (always true in the default ABI). */
1602 if (saved_int_regs
& 0x7)
1606 /* Can't be done if interworking with Thumb, and any registers have been
1608 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1611 /* On StrongARM, conditional returns are expensive if they aren't
1612 taken and multiple registers have been stacked. */
1613 if (iscond
&& arm_tune_strongarm
)
1615 /* Conditional return when just the LR is stored is a simple
1616 conditional-load instruction, that's not expensive. */
1617 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1621 && arm_pic_register
!= INVALID_REGNUM
1622 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1626 /* If there are saved registers but the LR isn't saved, then we need
1627 two instructions for the return. */
1628 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1631 /* Can't be done if any of the FPA regs are pushed,
1632 since this also requires an insn. */
1633 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1634 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1635 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1638 /* Likewise VFP regs. */
1639 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1640 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1641 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1644 if (TARGET_REALLY_IWMMXT
)
1645 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1646 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1652 /* Return TRUE if int I is a valid immediate ARM constant. */
1655 const_ok_for_arm (HOST_WIDE_INT i
)
1659 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1660 be all zero, or all one. */
1661 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1662 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1663 != ((~(unsigned HOST_WIDE_INT
) 0)
1664 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1667 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1669 /* Fast return for 0 and small values. We must do this for zero, since
1670 the code below can't handle that one case. */
1671 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1674 /* Get the number of trailing zeros. */
1675 lowbit
= ffs((int) i
) - 1;
1677 /* Only even shifts are allowed in ARM mode so round down to the
1678 nearest even number. */
1682 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1687 /* Allow rotated constants in ARM mode. */
1689 && ((i
& ~0xc000003f) == 0
1690 || (i
& ~0xf000000f) == 0
1691 || (i
& ~0xfc000003) == 0))
1698 /* Allow repeated pattern. */
1701 if (i
== v
|| i
== (v
| (v
<< 8)))
1708 /* Return true if I is a valid constant for the operation CODE. */
1710 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1712 if (const_ok_for_arm (i
))
1718 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1720 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1726 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1733 /* Emit a sequence of insns to handle a large constant.
1734 CODE is the code of the operation required, it can be any of SET, PLUS,
1735 IOR, AND, XOR, MINUS;
1736 MODE is the mode in which the operation is being performed;
1737 VAL is the integer to operate on;
1738 SOURCE is the other operand (a register, or a null-pointer for SET);
1739 SUBTARGETS means it is safe to create scratch registers if that will
1740 either produce a simpler sequence, or we will want to cse the values.
1741 Return value is the number of insns emitted. */
1743 /* ??? Tweak this for thumb2. */
1745 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1746 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1750 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1751 cond
= COND_EXEC_TEST (PATTERN (insn
));
1755 if (subtargets
|| code
== SET
1756 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1757 && REGNO (target
) != REGNO (source
)))
1759 /* After arm_reorg has been called, we can't fix up expensive
1760 constants by pushing them into memory so we must synthesize
1761 them in-line, regardless of the cost. This is only likely to
1762 be more costly on chips that have load delay slots and we are
1763 compiling without running the scheduler (so no splitting
1764 occurred before the final instruction emission).
1766 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1768 if (!after_arm_reorg
1770 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1772 > arm_constant_limit
+ (code
!= SET
)))
1776 /* Currently SET is the only monadic value for CODE, all
1777 the rest are diadic. */
1778 emit_set_insn (target
, GEN_INT (val
));
1783 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1785 emit_set_insn (temp
, GEN_INT (val
));
1786 /* For MINUS, the value is subtracted from, since we never
1787 have subtraction of a constant. */
1789 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
1791 emit_set_insn (target
,
1792 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
1798 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1802 /* Return the number of ARM instructions required to synthesize the given
1805 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1807 HOST_WIDE_INT temp1
;
1815 if (remainder
& (3 << (i
- 2)))
1820 temp1
= remainder
& ((0x0ff << end
)
1821 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1822 remainder
&= ~temp1
;
1827 } while (remainder
);
1831 /* Emit an instruction with the indicated PATTERN. If COND is
1832 non-NULL, conditionalize the execution of the instruction on COND
1836 emit_constant_insn (rtx cond
, rtx pattern
)
1839 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1840 emit_insn (pattern
);
1843 /* As above, but extra parameter GENERATE which, if clear, suppresses
1845 /* ??? This needs more work for thumb2. */
1848 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1849 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1854 int can_negate_initial
= 0;
1857 int num_bits_set
= 0;
1858 int set_sign_bit_copies
= 0;
1859 int clear_sign_bit_copies
= 0;
1860 int clear_zero_bit_copies
= 0;
1861 int set_zero_bit_copies
= 0;
1863 unsigned HOST_WIDE_INT temp1
, temp2
;
1864 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1866 /* Find out which operations are safe for a given CODE. Also do a quick
1867 check for degenerate cases; these can occur when DImode operations
1879 can_negate_initial
= 1;
1883 if (remainder
== 0xffffffff)
1886 emit_constant_insn (cond
,
1887 gen_rtx_SET (VOIDmode
, target
,
1888 GEN_INT (ARM_SIGN_EXTEND (val
))));
1893 if (reload_completed
&& rtx_equal_p (target
, source
))
1896 emit_constant_insn (cond
,
1897 gen_rtx_SET (VOIDmode
, target
, source
));
1906 emit_constant_insn (cond
,
1907 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1910 if (remainder
== 0xffffffff)
1912 if (reload_completed
&& rtx_equal_p (target
, source
))
1915 emit_constant_insn (cond
,
1916 gen_rtx_SET (VOIDmode
, target
, source
));
1925 if (reload_completed
&& rtx_equal_p (target
, source
))
1928 emit_constant_insn (cond
,
1929 gen_rtx_SET (VOIDmode
, target
, source
));
1933 /* We don't know how to handle other cases yet. */
1934 gcc_assert (remainder
== 0xffffffff);
1937 emit_constant_insn (cond
,
1938 gen_rtx_SET (VOIDmode
, target
,
1939 gen_rtx_NOT (mode
, source
)));
1943 /* We treat MINUS as (val - source), since (source - val) is always
1944 passed as (source + (-val)). */
1948 emit_constant_insn (cond
,
1949 gen_rtx_SET (VOIDmode
, target
,
1950 gen_rtx_NEG (mode
, source
)));
1953 if (const_ok_for_arm (val
))
1956 emit_constant_insn (cond
,
1957 gen_rtx_SET (VOIDmode
, target
,
1958 gen_rtx_MINUS (mode
, GEN_INT (val
),
1970 /* If we can do it in one insn get out quickly. */
1971 if (const_ok_for_arm (val
)
1972 || (can_negate_initial
&& const_ok_for_arm (-val
))
1973 || (can_invert
&& const_ok_for_arm (~val
)))
1976 emit_constant_insn (cond
,
1977 gen_rtx_SET (VOIDmode
, target
,
1979 ? gen_rtx_fmt_ee (code
, mode
, source
,
1985 /* Calculate a few attributes that may be useful for specific
1987 for (i
= 31; i
>= 0; i
--)
1989 if ((remainder
& (1 << i
)) == 0)
1990 clear_sign_bit_copies
++;
1995 for (i
= 31; i
>= 0; i
--)
1997 if ((remainder
& (1 << i
)) != 0)
1998 set_sign_bit_copies
++;
2003 for (i
= 0; i
<= 31; i
++)
2005 if ((remainder
& (1 << i
)) == 0)
2006 clear_zero_bit_copies
++;
2011 for (i
= 0; i
<= 31; i
++)
2013 if ((remainder
& (1 << i
)) != 0)
2014 set_zero_bit_copies
++;
2022 /* See if we can use movw. */
2023 if (arm_arch_thumb2
&& (remainder
& 0xffff0000) == 0)
2026 emit_constant_insn (cond
, gen_rtx_SET (VOIDmode
, target
,
2031 /* See if we can do this by sign_extending a constant that is known
2032 to be negative. This is a good, way of doing it, since the shift
2033 may well merge into a subsequent insn. */
2034 if (set_sign_bit_copies
> 1)
2036 if (const_ok_for_arm
2037 (temp1
= ARM_SIGN_EXTEND (remainder
2038 << (set_sign_bit_copies
- 1))))
2042 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2043 emit_constant_insn (cond
,
2044 gen_rtx_SET (VOIDmode
, new_src
,
2046 emit_constant_insn (cond
,
2047 gen_ashrsi3 (target
, new_src
,
2048 GEN_INT (set_sign_bit_copies
- 1)));
2052 /* For an inverted constant, we will need to set the low bits,
2053 these will be shifted out of harm's way. */
2054 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
2055 if (const_ok_for_arm (~temp1
))
2059 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2060 emit_constant_insn (cond
,
2061 gen_rtx_SET (VOIDmode
, new_src
,
2063 emit_constant_insn (cond
,
2064 gen_ashrsi3 (target
, new_src
,
2065 GEN_INT (set_sign_bit_copies
- 1)));
2071 /* See if we can calculate the value as the difference between two
2072 valid immediates. */
2073 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
2075 int topshift
= clear_sign_bit_copies
& ~1;
2077 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
2078 & (0xff000000 >> topshift
));
2080 /* If temp1 is zero, then that means the 9 most significant
2081 bits of remainder were 1 and we've caused it to overflow.
2082 When topshift is 0 we don't need to do anything since we
2083 can borrow from 'bit 32'. */
2084 if (temp1
== 0 && topshift
!= 0)
2085 temp1
= 0x80000000 >> (topshift
- 1);
2087 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
2089 if (const_ok_for_arm (temp2
))
2093 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2094 emit_constant_insn (cond
,
2095 gen_rtx_SET (VOIDmode
, new_src
,
2097 emit_constant_insn (cond
,
2098 gen_addsi3 (target
, new_src
,
2106 /* See if we can generate this by setting the bottom (or the top)
2107 16 bits, and then shifting these into the other half of the
2108 word. We only look for the simplest cases, to do more would cost
2109 too much. Be careful, however, not to generate this when the
2110 alternative would take fewer insns. */
2111 if (val
& 0xffff0000)
2113 temp1
= remainder
& 0xffff0000;
2114 temp2
= remainder
& 0x0000ffff;
2116 /* Overlaps outside this range are best done using other methods. */
2117 for (i
= 9; i
< 24; i
++)
2119 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2120 && !const_ok_for_arm (temp2
))
2122 rtx new_src
= (subtargets
2123 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2125 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2126 source
, subtargets
, generate
);
2134 gen_rtx_ASHIFT (mode
, source
,
2141 /* Don't duplicate cases already considered. */
2142 for (i
= 17; i
< 24; i
++)
2144 if (((temp1
| (temp1
>> i
)) == remainder
)
2145 && !const_ok_for_arm (temp1
))
2147 rtx new_src
= (subtargets
2148 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2150 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2151 source
, subtargets
, generate
);
2156 gen_rtx_SET (VOIDmode
, target
,
2159 gen_rtx_LSHIFTRT (mode
, source
,
2170 /* If we have IOR or XOR, and the constant can be loaded in a
2171 single instruction, and we can find a temporary to put it in,
2172 then this can be done in two instructions instead of 3-4. */
2174 /* TARGET can't be NULL if SUBTARGETS is 0 */
2175 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2177 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2181 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2183 emit_constant_insn (cond
,
2184 gen_rtx_SET (VOIDmode
, sub
,
2186 emit_constant_insn (cond
,
2187 gen_rtx_SET (VOIDmode
, target
,
2188 gen_rtx_fmt_ee (code
, mode
,
2198 if (set_sign_bit_copies
> 8
2199 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2203 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2204 rtx shift
= GEN_INT (set_sign_bit_copies
);
2208 gen_rtx_SET (VOIDmode
, sub
,
2210 gen_rtx_ASHIFT (mode
,
2215 gen_rtx_SET (VOIDmode
, target
,
2217 gen_rtx_LSHIFTRT (mode
, sub
,
2223 if (set_zero_bit_copies
> 8
2224 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2228 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2229 rtx shift
= GEN_INT (set_zero_bit_copies
);
2233 gen_rtx_SET (VOIDmode
, sub
,
2235 gen_rtx_LSHIFTRT (mode
,
2240 gen_rtx_SET (VOIDmode
, target
,
2242 gen_rtx_ASHIFT (mode
, sub
,
2248 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2252 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2253 emit_constant_insn (cond
,
2254 gen_rtx_SET (VOIDmode
, sub
,
2255 gen_rtx_NOT (mode
, source
)));
2258 sub
= gen_reg_rtx (mode
);
2259 emit_constant_insn (cond
,
2260 gen_rtx_SET (VOIDmode
, sub
,
2261 gen_rtx_AND (mode
, source
,
2263 emit_constant_insn (cond
,
2264 gen_rtx_SET (VOIDmode
, target
,
2265 gen_rtx_NOT (mode
, sub
)));
2272 /* See if two shifts will do 2 or more insn's worth of work. */
2273 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2275 HOST_WIDE_INT shift_mask
= ((0xffffffff
2276 << (32 - clear_sign_bit_copies
))
2279 if ((remainder
| shift_mask
) != 0xffffffff)
2283 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2284 insns
= arm_gen_constant (AND
, mode
, cond
,
2285 remainder
| shift_mask
,
2286 new_src
, source
, subtargets
, 1);
2291 rtx targ
= subtargets
? NULL_RTX
: target
;
2292 insns
= arm_gen_constant (AND
, mode
, cond
,
2293 remainder
| shift_mask
,
2294 targ
, source
, subtargets
, 0);
2300 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2301 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2303 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2304 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2310 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2312 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2314 if ((remainder
| shift_mask
) != 0xffffffff)
2318 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2320 insns
= arm_gen_constant (AND
, mode
, cond
,
2321 remainder
| shift_mask
,
2322 new_src
, source
, subtargets
, 1);
2327 rtx targ
= subtargets
? NULL_RTX
: target
;
2329 insns
= arm_gen_constant (AND
, mode
, cond
,
2330 remainder
| shift_mask
,
2331 targ
, source
, subtargets
, 0);
2337 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2338 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2340 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2341 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2353 for (i
= 0; i
< 32; i
++)
2354 if (remainder
& (1 << i
))
2357 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2358 remainder
= (~remainder
) & 0xffffffff;
2359 else if (code
== PLUS
&& num_bits_set
> 16)
2360 remainder
= (-remainder
) & 0xffffffff;
2367 /* Now try and find a way of doing the job in either two or three
2369 We start by looking for the largest block of zeros that are aligned on
2370 a 2-bit boundary, we then fill up the temps, wrapping around to the
2371 top of the word when we drop off the bottom.
2372 In the worst case this code should produce no more than four insns.
2373 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2374 best place to start. */
2376 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2382 int best_consecutive_zeros
= 0;
2384 for (i
= 0; i
< 32; i
+= 2)
2386 int consecutive_zeros
= 0;
2388 if (!(remainder
& (3 << i
)))
2390 while ((i
< 32) && !(remainder
& (3 << i
)))
2392 consecutive_zeros
+= 2;
2395 if (consecutive_zeros
> best_consecutive_zeros
)
2397 best_consecutive_zeros
= consecutive_zeros
;
2398 best_start
= i
- consecutive_zeros
;
2404 /* So long as it won't require any more insns to do so, it's
2405 desirable to emit a small constant (in bits 0...9) in the last
2406 insn. This way there is more chance that it can be combined with
2407 a later addressing insn to form a pre-indexed load or store
2408 operation. Consider:
2410 *((volatile int *)0xe0000100) = 1;
2411 *((volatile int *)0xe0000110) = 2;
2413 We want this to wind up as:
2417 str rB, [rA, #0x100]
2419 str rB, [rA, #0x110]
2421 rather than having to synthesize both large constants from scratch.
2423 Therefore, we calculate how many insns would be required to emit
2424 the constant starting from `best_start', and also starting from
2425 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2426 yield a shorter sequence, we may as well use zero. */
2428 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2429 && (count_insns_for_constant (remainder
, 0) <=
2430 count_insns_for_constant (remainder
, best_start
)))
2434 /* Now start emitting the insns. */
2442 if (remainder
& (3 << (i
- 2)))
2447 temp1
= remainder
& ((0x0ff << end
)
2448 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2449 remainder
&= ~temp1
;
2453 rtx new_src
, temp1_rtx
;
2455 if (code
== SET
|| code
== MINUS
)
2457 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2458 if (can_invert
&& code
!= MINUS
)
2463 if (remainder
&& subtargets
)
2464 new_src
= gen_reg_rtx (mode
);
2469 else if (can_negate
)
2473 temp1
= trunc_int_for_mode (temp1
, mode
);
2474 temp1_rtx
= GEN_INT (temp1
);
2478 else if (code
== MINUS
)
2479 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2481 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2483 emit_constant_insn (cond
,
2484 gen_rtx_SET (VOIDmode
, new_src
,
2494 else if (code
== MINUS
)
2503 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitary
2516 /* Canonicalize a comparison so that we are more likely to recognize it.
2517 This can be done for a few constant compares, where we can make the
2518 immediate value easier to load. */
2521 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2524 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2525 unsigned HOST_WIDE_INT maxval
;
2526 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2537 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2539 *op1
= GEN_INT (i
+ 1);
2540 return code
== GT
? GE
: LT
;
2547 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2549 *op1
= GEN_INT (i
- 1);
2550 return code
== GE
? GT
: LE
;
2556 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2557 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2559 *op1
= GEN_INT (i
+ 1);
2560 return code
== GTU
? GEU
: LTU
;
2567 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2569 *op1
= GEN_INT (i
- 1);
2570 return code
== GEU
? GTU
: LEU
;
2582 /* Define how to find the value returned by a function. */
2585 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2587 enum machine_mode mode
;
2588 int unsignedp ATTRIBUTE_UNUSED
;
2589 rtx r ATTRIBUTE_UNUSED
;
2591 mode
= TYPE_MODE (type
);
2592 /* Promote integer types. */
2593 if (INTEGRAL_TYPE_P (type
))
2594 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2596 /* Promotes small structs returned in a register to full-word size
2597 for big-endian AAPCS. */
2598 if (arm_return_in_msb (type
))
2600 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2601 if (size
% UNITS_PER_WORD
!= 0)
2603 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2604 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2608 return LIBCALL_VALUE(mode
);
2611 /* Determine the amount of memory needed to store the possible return
2612 registers of an untyped call. */
2614 arm_apply_result_size (void)
2620 if (TARGET_HARD_FLOAT_ABI
)
2624 if (TARGET_MAVERICK
)
2627 if (TARGET_IWMMXT_ABI
)
2634 /* Decide whether a type should be returned in memory (true)
2635 or in a register (false). This is called by the macro
2636 RETURN_IN_MEMORY. */
2638 arm_return_in_memory (tree type
)
2642 if (!AGGREGATE_TYPE_P (type
) &&
2643 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2644 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2645 /* All simple types are returned in registers.
2646 For AAPCS, complex types are treated the same as aggregates. */
2649 size
= int_size_in_bytes (type
);
2651 if (arm_abi
!= ARM_ABI_APCS
)
2653 /* ATPCS and later return aggregate types in memory only if they are
2654 larger than a word (or are variable size). */
2655 return (size
< 0 || size
> UNITS_PER_WORD
);
2658 /* To maximize backwards compatibility with previous versions of gcc,
2659 return vectors up to 4 words in registers. */
2660 if (TREE_CODE (type
) == VECTOR_TYPE
)
2661 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2663 /* For the arm-wince targets we choose to be compatible with Microsoft's
2664 ARM and Thumb compilers, which always return aggregates in memory. */
2666 /* All structures/unions bigger than one word are returned in memory.
2667 Also catch the case where int_size_in_bytes returns -1. In this case
2668 the aggregate is either huge or of variable size, and in either case
2669 we will want to return it via memory and not in a register. */
2670 if (size
< 0 || size
> UNITS_PER_WORD
)
2673 if (TREE_CODE (type
) == RECORD_TYPE
)
2677 /* For a struct the APCS says that we only return in a register
2678 if the type is 'integer like' and every addressable element
2679 has an offset of zero. For practical purposes this means
2680 that the structure can have at most one non bit-field element
2681 and that this element must be the first one in the structure. */
2683 /* Find the first field, ignoring non FIELD_DECL things which will
2684 have been created by C++. */
2685 for (field
= TYPE_FIELDS (type
);
2686 field
&& TREE_CODE (field
) != FIELD_DECL
;
2687 field
= TREE_CHAIN (field
))
2691 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2693 /* Check that the first field is valid for returning in a register. */
2695 /* ... Floats are not allowed */
2696 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2699 /* ... Aggregates that are not themselves valid for returning in
2700 a register are not allowed. */
2701 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2704 /* Now check the remaining fields, if any. Only bitfields are allowed,
2705 since they are not addressable. */
2706 for (field
= TREE_CHAIN (field
);
2708 field
= TREE_CHAIN (field
))
2710 if (TREE_CODE (field
) != FIELD_DECL
)
2713 if (!DECL_BIT_FIELD_TYPE (field
))
2720 if (TREE_CODE (type
) == UNION_TYPE
)
2724 /* Unions can be returned in registers if every element is
2725 integral, or can be returned in an integer register. */
2726 for (field
= TYPE_FIELDS (type
);
2728 field
= TREE_CHAIN (field
))
2730 if (TREE_CODE (field
) != FIELD_DECL
)
2733 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2736 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2742 #endif /* not ARM_WINCE */
2744 /* Return all other types in memory. */
2748 /* Indicate whether or not words of a double are in big-endian order. */
2751 arm_float_words_big_endian (void)
2753 if (TARGET_MAVERICK
)
2756 /* For FPA, float words are always big-endian. For VFP, floats words
2757 follow the memory system mode. */
2765 return (TARGET_BIG_END
? 1 : 0);
2770 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2771 for a call to a function whose data type is FNTYPE.
2772 For a library call, FNTYPE is NULL. */
2774 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2775 rtx libname ATTRIBUTE_UNUSED
,
2776 tree fndecl ATTRIBUTE_UNUSED
)
2778 /* On the ARM, the offset starts at 0. */
2780 pcum
->iwmmxt_nregs
= 0;
2781 pcum
->can_split
= true;
2783 pcum
->call_cookie
= CALL_NORMAL
;
2785 if (TARGET_LONG_CALLS
)
2786 pcum
->call_cookie
= CALL_LONG
;
2788 /* Check for long call/short call attributes. The attributes
2789 override any command line option. */
2792 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2793 pcum
->call_cookie
= CALL_SHORT
;
2794 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2795 pcum
->call_cookie
= CALL_LONG
;
2798 /* Varargs vectors are treated the same as long long.
2799 named_count avoids having to change the way arm handles 'named' */
2800 pcum
->named_count
= 0;
2803 if (TARGET_REALLY_IWMMXT
&& fntype
)
2807 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2809 fn_arg
= TREE_CHAIN (fn_arg
))
2810 pcum
->named_count
+= 1;
2812 if (! pcum
->named_count
)
2813 pcum
->named_count
= INT_MAX
;
2818 /* Return true if mode/type need doubleword alignment. */
2820 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2822 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2823 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2827 /* Determine where to put an argument to a function.
2828 Value is zero to push the argument on the stack,
2829 or a hard register in which to store the argument.
2831 MODE is the argument's machine mode.
2832 TYPE is the data type of the argument (as a tree).
2833 This is null for libcalls where that information may
2835 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2836 the preceding args and about the function being called.
2837 NAMED is nonzero if this argument is a named parameter
2838 (otherwise it is an extra parameter matching an ellipsis). */
2841 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2842 tree type
, int named
)
2846 /* Varargs vectors are treated the same as long long.
2847 named_count avoids having to change the way arm handles 'named' */
2848 if (TARGET_IWMMXT_ABI
2849 && arm_vector_mode_supported_p (mode
)
2850 && pcum
->named_count
> pcum
->nargs
+ 1)
2852 if (pcum
->iwmmxt_nregs
<= 9)
2853 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2856 pcum
->can_split
= false;
2861 /* Put doubleword aligned quantities in even register pairs. */
2863 && ARM_DOUBLEWORD_ALIGN
2864 && arm_needs_doubleword_align (mode
, type
))
2867 if (mode
== VOIDmode
)
2868 /* Compute operand 2 of the call insn. */
2869 return GEN_INT (pcum
->call_cookie
);
2871 /* Only allow splitting an arg between regs and memory if all preceding
2872 args were allocated to regs. For args passed by reference we only count
2873 the reference pointer. */
2874 if (pcum
->can_split
)
2877 nregs
= ARM_NUM_REGS2 (mode
, type
);
2879 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2882 return gen_rtx_REG (mode
, pcum
->nregs
);
2886 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2887 tree type
, bool named ATTRIBUTE_UNUSED
)
2889 int nregs
= pcum
->nregs
;
2891 if (arm_vector_mode_supported_p (mode
))
2894 if (NUM_ARG_REGS
> nregs
2895 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2897 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2902 /* Variable sized types are passed by reference. This is a GCC
2903 extension to the ARM ABI. */
2906 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2907 enum machine_mode mode ATTRIBUTE_UNUSED
,
2908 tree type
, bool named ATTRIBUTE_UNUSED
)
2910 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2913 /* Encode the current state of the #pragma [no_]long_calls. */
2916 OFF
, /* No #pragma [no_]long_calls is in effect. */
2917 LONG
, /* #pragma long_calls is in effect. */
2918 SHORT
/* #pragma no_long_calls is in effect. */
2921 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2924 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2926 arm_pragma_long_calls
= LONG
;
2930 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2932 arm_pragma_long_calls
= SHORT
;
2936 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2938 arm_pragma_long_calls
= OFF
;
2941 /* Table of machine attributes. */
2942 const struct attribute_spec arm_attribute_table
[] =
2944 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2945 /* Function calls made to this symbol must be done indirectly, because
2946 it may lie outside of the 26 bit addressing range of a normal function
2948 { "long_call", 0, 0, false, true, true, NULL
},
2949 /* Whereas these functions are always known to reside within the 26 bit
2950 addressing range. */
2951 { "short_call", 0, 0, false, true, true, NULL
},
2952 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2953 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2954 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2955 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2957 /* ARM/PE has three new attributes:
2959 dllexport - for exporting a function/variable that will live in a dll
2960 dllimport - for importing a function/variable from a dll
2962 Microsoft allows multiple declspecs in one __declspec, separating
2963 them with spaces. We do NOT support this. Instead, use __declspec
2966 { "dllimport", 0, 0, true, false, false, NULL
},
2967 { "dllexport", 0, 0, true, false, false, NULL
},
2968 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2969 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2970 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2971 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2972 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2974 { NULL
, 0, 0, false, false, false, NULL
}
2977 /* Handle an attribute requiring a FUNCTION_DECL;
2978 arguments as in struct attribute_spec.handler. */
2980 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2981 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2983 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2985 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2986 IDENTIFIER_POINTER (name
));
2987 *no_add_attrs
= true;
2993 /* Handle an "interrupt" or "isr" attribute;
2994 arguments as in struct attribute_spec.handler. */
2996 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
3001 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3003 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
3004 IDENTIFIER_POINTER (name
));
3005 *no_add_attrs
= true;
3007 /* FIXME: the argument if any is checked for type attributes;
3008 should it be checked for decl ones? */
3012 if (TREE_CODE (*node
) == FUNCTION_TYPE
3013 || TREE_CODE (*node
) == METHOD_TYPE
)
3015 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
3017 warning (OPT_Wattributes
, "%qs attribute ignored",
3018 IDENTIFIER_POINTER (name
));
3019 *no_add_attrs
= true;
3022 else if (TREE_CODE (*node
) == POINTER_TYPE
3023 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
3024 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
3025 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
3027 *node
= build_variant_type_copy (*node
);
3028 TREE_TYPE (*node
) = build_type_attribute_variant
3030 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
3031 *no_add_attrs
= true;
3035 /* Possibly pass this attribute on from the type to a decl. */
3036 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
3037 | (int) ATTR_FLAG_FUNCTION_NEXT
3038 | (int) ATTR_FLAG_ARRAY_NEXT
))
3040 *no_add_attrs
= true;
3041 return tree_cons (name
, args
, NULL_TREE
);
3045 warning (OPT_Wattributes
, "%qs attribute ignored",
3046 IDENTIFIER_POINTER (name
));
3054 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3055 /* Handle the "notshared" attribute. This attribute is another way of
3056 requesting hidden visibility. ARM's compiler supports
3057 "__declspec(notshared)"; we support the same thing via an
3061 arm_handle_notshared_attribute (tree
*node
,
3062 tree name ATTRIBUTE_UNUSED
,
3063 tree args ATTRIBUTE_UNUSED
,
3064 int flags ATTRIBUTE_UNUSED
,
3067 tree decl
= TYPE_NAME (*node
);
3071 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
3072 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
3073 *no_add_attrs
= false;
3079 /* Return 0 if the attributes for two types are incompatible, 1 if they
3080 are compatible, and 2 if they are nearly compatible (which causes a
3081 warning to be generated). */
3083 arm_comp_type_attributes (tree type1
, tree type2
)
3087 /* Check for mismatch of non-default calling convention. */
3088 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
3091 /* Check for mismatched call attributes. */
3092 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
3093 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
3094 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
3095 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
3097 /* Only bother to check if an attribute is defined. */
3098 if (l1
| l2
| s1
| s2
)
3100 /* If one type has an attribute, the other must have the same attribute. */
3101 if ((l1
!= l2
) || (s1
!= s2
))
3104 /* Disallow mixed attributes. */
3105 if ((l1
& s2
) || (l2
& s1
))
3109 /* Check for mismatched ISR attribute. */
3110 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
3112 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
3113 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
3115 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
3122 /* Encode long_call or short_call attribute by prefixing
3123 symbol name in DECL with a special character FLAG. */
3125 arm_encode_call_attribute (tree decl
, int flag
)
3127 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
3128 int len
= strlen (str
);
3131 /* Do not allow weak functions to be treated as short call. */
3132 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3135 newstr
= alloca (len
+ 2);
3137 strcpy (newstr
+ 1, str
);
3139 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3140 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3143 /* Assigns default attributes to newly defined type. This is used to
3144 set short_call/long_call attributes for function types of
3145 functions defined inside corresponding #pragma scopes. */
3147 arm_set_default_type_attributes (tree type
)
3149 /* Add __attribute__ ((long_call)) to all functions, when
3150 inside #pragma long_calls or __attribute__ ((short_call)),
3151 when inside #pragma no_long_calls. */
3152 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3154 tree type_attr_list
, attr_name
;
3155 type_attr_list
= TYPE_ATTRIBUTES (type
);
3157 if (arm_pragma_long_calls
== LONG
)
3158 attr_name
= get_identifier ("long_call");
3159 else if (arm_pragma_long_calls
== SHORT
)
3160 attr_name
= get_identifier ("short_call");
3164 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3165 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3169 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3170 defined within the current compilation unit. If this cannot be
3171 determined, then 0 is returned. */
3173 current_file_function_operand (rtx sym_ref
)
3175 /* This is a bit of a fib. A function will have a short call flag
3176 applied to its name if it has the short call attribute, or it has
3177 already been defined within the current compilation unit. */
3178 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3181 /* The current function is always defined within the current compilation
3182 unit. If it s a weak definition however, then this may not be the real
3183 definition of the function, and so we have to say no. */
3184 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3185 && !DECL_WEAK (current_function_decl
))
3188 /* We cannot make the determination - default to returning 0. */
3192 /* Return nonzero if a 32 bit "long_call" should be generated for
3193 this call. We generate a long_call if the function:
3195 a. has an __attribute__((long call))
3196 or b. is within the scope of a #pragma long_calls
3197 or c. the -mlong-calls command line switch has been specified
3199 1. -ffunction-sections is in effect
3200 or 2. the current function has __attribute__ ((section))
3201 or 3. the target function has __attribute__ ((section))
3203 However we do not generate a long call if the function:
3205 d. has an __attribute__ ((short_call))
3206 or e. is inside the scope of a #pragma no_long_calls
3207 or f. is defined within the current compilation unit.
3209 This function will be called by C fragments contained in the machine
3210 description file. SYM_REF and CALL_COOKIE correspond to the matched
3211 rtl operands. CALL_SYMBOL is used to distinguish between
3212 two different callers of the function. It is set to 1 in the
3213 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3214 and "call_value" patterns. This is because of the difference in the
3215 SYM_REFs passed by these patterns. */
3217 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3221 if (GET_CODE (sym_ref
) != MEM
)
3224 sym_ref
= XEXP (sym_ref
, 0);
3227 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3230 if (call_cookie
& CALL_SHORT
)
3233 if (TARGET_LONG_CALLS
)
3235 if (flag_function_sections
3236 || DECL_SECTION_NAME (current_function_decl
))
3237 /* c.3 is handled by the definition of the
3238 ARM_DECLARE_FUNCTION_SIZE macro. */
3242 if (current_file_function_operand (sym_ref
))
3245 return (call_cookie
& CALL_LONG
)
3246 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3247 || TARGET_LONG_CALLS
;
3250 /* Return nonzero if it is ok to make a tail-call to DECL. */
3252 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3254 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3255 unsigned long func_type
;
3257 if (cfun
->machine
->sibcall_blocked
)
3260 /* Never tailcall something for which we have no decl, or if we
3261 are in Thumb mode. */
3262 if (decl
== NULL
|| TARGET_THUMB
)
3265 /* Get the calling method. */
3266 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3267 call_type
= CALL_SHORT
;
3268 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3269 call_type
= CALL_LONG
;
3271 /* Cannot tail-call to long calls, since these are out of range of
3272 a branch instruction. However, if not compiling PIC, we know
3273 we can reach the symbol if it is in this compilation unit. */
3274 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3277 /* If we are interworking and the function is not declared static
3278 then we can't tail-call it unless we know that it exists in this
3279 compilation unit (since it might be a Thumb routine). */
3280 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3283 func_type
= arm_current_func_type ();
3284 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3285 if (IS_INTERRUPT (func_type
))
3288 /* Never tailcall if function may be called with a misaligned SP. */
3289 if (IS_STACKALIGN (func_type
))
3292 /* Everything else is ok. */
3297 /* Addressing mode support functions. */
3299 /* Return nonzero if X is a legitimate immediate operand when compiling
3300 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3302 legitimate_pic_operand_p (rtx x
)
3304 if (GET_CODE (x
) == SYMBOL_REF
3305 || (GET_CODE (x
) == CONST
3306 && GET_CODE (XEXP (x
, 0)) == PLUS
3307 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3314 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3316 if (GET_CODE (orig
) == SYMBOL_REF
3317 || GET_CODE (orig
) == LABEL_REF
)
3319 #ifndef AOF_ASSEMBLER
3320 rtx pic_ref
, address
;
3325 /* If this function doesn't have a pic register, create one now.
3326 A lot of the logic here is made obscure by the fact that this
3327 routine gets called as part of the rtx cost estimation
3328 process. We don't want those calls to affect any assumptions
3329 about the real function; and further, we can't call
3330 entry_of_function() until we start the real expansion
3332 if (!current_function_uses_pic_offset_table
)
3334 gcc_assert (!no_new_pseudos
);
3335 if (arm_pic_register
!= INVALID_REGNUM
)
3337 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
3339 /* Play games to avoid marking the function as needing pic
3340 if we are being called as part of the cost-estimation
3342 if (current_ir_type () != IR_GIMPLE
)
3343 current_function_uses_pic_offset_table
= 1;
3349 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
3351 /* Play games to avoid marking the function as needing pic
3352 if we are being called as part of the cost-estimation
3354 if (current_ir_type () != IR_GIMPLE
)
3356 current_function_uses_pic_offset_table
= 1;
3359 arm_load_pic_register (0UL);
3363 emit_insn_after (seq
, entry_of_function ());
3370 gcc_assert (!no_new_pseudos
);
3371 reg
= gen_reg_rtx (Pmode
);
3376 #ifdef AOF_ASSEMBLER
3377 /* The AOF assembler can generate relocations for these directly, and
3378 understands that the PIC register has to be added into the offset. */
3379 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3382 address
= gen_reg_rtx (Pmode
);
3387 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3388 else if (TARGET_THUMB2
)
3389 emit_insn (gen_pic_load_addr_thumb2 (address
, orig
));
3390 else /* TARGET_THUMB1 */
3391 emit_insn (gen_pic_load_addr_thumb1 (address
, orig
));
3393 if ((GET_CODE (orig
) == LABEL_REF
3394 || (GET_CODE (orig
) == SYMBOL_REF
&&
3395 SYMBOL_REF_LOCAL_P (orig
)))
3397 pic_ref
= gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
, address
);
3400 pic_ref
= gen_const_mem (Pmode
,
3401 gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
,
3405 insn
= emit_move_insn (reg
, pic_ref
);
3407 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3409 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3413 else if (GET_CODE (orig
) == CONST
)
3417 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3418 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
3421 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3422 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3427 gcc_assert (!no_new_pseudos
);
3428 reg
= gen_reg_rtx (Pmode
);
3431 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3433 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3434 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3435 base
== reg
? 0 : reg
);
3437 if (GET_CODE (offset
) == CONST_INT
)
3439 /* The base register doesn't really matter, we only want to
3440 test the index for the appropriate mode. */
3441 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3443 gcc_assert (!no_new_pseudos
);
3444 offset
= force_reg (Pmode
, offset
);
3447 if (GET_CODE (offset
) == CONST_INT
)
3448 return plus_constant (base
, INTVAL (offset
));
3451 if (GET_MODE_SIZE (mode
) > 4
3452 && (GET_MODE_CLASS (mode
) == MODE_INT
3453 || TARGET_SOFT_FLOAT
))
3455 emit_insn (gen_addsi3 (reg
, base
, offset
));
3459 return gen_rtx_PLUS (Pmode
, base
, offset
);
3466 /* Find a spare register to use during the prolog of a function. */
3469 thumb_find_work_register (unsigned long pushed_regs_mask
)
3473 /* Check the argument registers first as these are call-used. The
3474 register allocation order means that sometimes r3 might be used
3475 but earlier argument registers might not, so check them all. */
3476 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3477 if (!regs_ever_live
[reg
])
3480 /* Before going on to check the call-saved registers we can try a couple
3481 more ways of deducing that r3 is available. The first is when we are
3482 pushing anonymous arguments onto the stack and we have less than 4
3483 registers worth of fixed arguments(*). In this case r3 will be part of
3484 the variable argument list and so we can be sure that it will be
3485 pushed right at the start of the function. Hence it will be available
3486 for the rest of the prologue.
3487 (*): ie current_function_pretend_args_size is greater than 0. */
3488 if (cfun
->machine
->uses_anonymous_args
3489 && current_function_pretend_args_size
> 0)
3490 return LAST_ARG_REGNUM
;
3492 /* The other case is when we have fixed arguments but less than 4 registers
3493 worth. In this case r3 might be used in the body of the function, but
3494 it is not being used to convey an argument into the function. In theory
3495 we could just check current_function_args_size to see how many bytes are
3496 being passed in argument registers, but it seems that it is unreliable.
3497 Sometimes it will have the value 0 when in fact arguments are being
3498 passed. (See testcase execute/20021111-1.c for an example). So we also
3499 check the args_info.nregs field as well. The problem with this field is
3500 that it makes no allowances for arguments that are passed to the
3501 function but which are not used. Hence we could miss an opportunity
3502 when a function has an unused argument in r3. But it is better to be
3503 safe than to be sorry. */
3504 if (! cfun
->machine
->uses_anonymous_args
3505 && current_function_args_size
>= 0
3506 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3507 && cfun
->args_info
.nregs
< 4)
3508 return LAST_ARG_REGNUM
;
3510 /* Otherwise look for a call-saved register that is going to be pushed. */
3511 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3512 if (pushed_regs_mask
& (1 << reg
))
3517 /* Thumb-2 can use high regs. */
3518 for (reg
= FIRST_HI_REGNUM
; reg
< 15; reg
++)
3519 if (pushed_regs_mask
& (1 << reg
))
3522 /* Something went wrong - thumb_compute_save_reg_mask()
3523 should have arranged for a suitable register to be pushed. */
3527 static GTY(()) int pic_labelno
;
3529 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3533 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3535 #ifndef AOF_ASSEMBLER
3536 rtx l1
, labelno
, pic_tmp
, pic_tmp2
, pic_rtx
;
3537 rtx global_offset_table
;
3539 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3542 gcc_assert (flag_pic
);
3544 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3545 in the code stream. */
3547 labelno
= GEN_INT (pic_labelno
++);
3548 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3549 l1
= gen_rtx_CONST (VOIDmode
, l1
);
3551 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3552 /* On the ARM the PC register contains 'dot + 8' at the time of the
3553 addition, on the Thumb it is 'dot + 4'. */
3554 pic_tmp
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
3556 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3557 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3559 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3561 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3565 emit_insn (gen_pic_load_addr_arm (cfun
->machine
->pic_reg
, pic_rtx
));
3566 emit_insn (gen_pic_add_dot_plus_eight (cfun
->machine
->pic_reg
,
3567 cfun
->machine
->pic_reg
, labelno
));
3569 else if (TARGET_THUMB2
)
3571 /* Thumb-2 only allows very limited access to the PC. Calculate the
3572 address in a temporary register. */
3573 if (arm_pic_register
!= INVALID_REGNUM
)
3575 pic_tmp
= gen_rtx_REG (SImode
,
3576 thumb_find_work_register (saved_regs
));
3580 gcc_assert (!no_new_pseudos
);
3581 pic_tmp
= gen_reg_rtx (Pmode
);
3584 emit_insn (gen_pic_load_addr_thumb2 (cfun
->machine
->pic_reg
, pic_rtx
));
3585 emit_insn (gen_pic_load_dot_plus_four (pic_tmp
, labelno
));
3586 emit_insn (gen_addsi3(cfun
->machine
->pic_reg
, cfun
->machine
->pic_reg
,
3589 else /* TARGET_THUMB1 */
3591 if (arm_pic_register
!= INVALID_REGNUM
3592 && REGNO (cfun
->machine
->pic_reg
) > LAST_LO_REGNUM
)
3594 /* We will have pushed the pic register, so we should always be
3595 able to find a work register. */
3596 pic_tmp
= gen_rtx_REG (SImode
,
3597 thumb_find_work_register (saved_regs
));
3598 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp
, pic_rtx
));
3599 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3602 emit_insn (gen_pic_load_addr_thumb1 (cfun
->machine
->pic_reg
, pic_rtx
));
3603 emit_insn (gen_pic_add_dot_plus_four (cfun
->machine
->pic_reg
,
3604 cfun
->machine
->pic_reg
, labelno
));
3607 /* Need to emit this whether or not we obey regdecls,
3608 since setjmp/longjmp can cause life info to screw up. */
3609 emit_insn (gen_rtx_USE (VOIDmode
, cfun
->machine
->pic_reg
));
3610 #endif /* AOF_ASSEMBLER */
3614 /* Return nonzero if X is valid as an ARM state addressing register. */
3616 arm_address_register_rtx_p (rtx x
, int strict_p
)
3620 if (GET_CODE (x
) != REG
)
3626 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3628 return (regno
<= LAST_ARM_REGNUM
3629 || regno
>= FIRST_PSEUDO_REGISTER
3630 || regno
== FRAME_POINTER_REGNUM
3631 || regno
== ARG_POINTER_REGNUM
);
3634 /* Return TRUE if this rtx is the difference of a symbol and a label,
3635 and will reduce to a PC-relative relocation in the object file.
3636 Expressions like this can be left alone when generating PIC, rather
3637 than forced through the GOT. */
3639 pcrel_constant_p (rtx x
)
3641 if (GET_CODE (x
) == MINUS
)
3642 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3647 /* Return nonzero if X is a valid ARM state address operand. */
3649 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3653 enum rtx_code code
= GET_CODE (x
);
3655 if (arm_address_register_rtx_p (x
, strict_p
))
3658 use_ldrd
= (TARGET_LDRD
3660 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3662 if (code
== POST_INC
|| code
== PRE_DEC
3663 || ((code
== PRE_INC
|| code
== POST_DEC
)
3664 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3665 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3667 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3668 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3669 && GET_CODE (XEXP (x
, 1)) == PLUS
3670 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3672 rtx addend
= XEXP (XEXP (x
, 1), 1);
3674 /* Don't allow ldrd post increment by register because it's hard
3675 to fixup invalid register choices. */
3677 && GET_CODE (x
) == POST_MODIFY
3678 && GET_CODE (addend
) == REG
)
3681 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3682 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3685 /* After reload constants split into minipools will have addresses
3686 from a LABEL_REF. */
3687 else if (reload_completed
3688 && (code
== LABEL_REF
3690 && GET_CODE (XEXP (x
, 0)) == PLUS
3691 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3692 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3695 else if (mode
== TImode
)
3698 else if (code
== PLUS
)
3700 rtx xop0
= XEXP (x
, 0);
3701 rtx xop1
= XEXP (x
, 1);
3703 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3704 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3705 || (arm_address_register_rtx_p (xop1
, strict_p
)
3706 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3710 /* Reload currently can't handle MINUS, so disable this for now */
3711 else if (GET_CODE (x
) == MINUS
)
3713 rtx xop0
= XEXP (x
, 0);
3714 rtx xop1
= XEXP (x
, 1);
3716 return (arm_address_register_rtx_p (xop0
, strict_p
)
3717 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3721 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3722 && code
== SYMBOL_REF
3723 && CONSTANT_POOL_ADDRESS_P (x
)
3725 && symbol_mentioned_p (get_pool_constant (x
))
3726 && ! pcrel_constant_p (get_pool_constant (x
))))
3732 /* Return nonzero if X is a valid Thumb-2 address operand. */
3734 thumb2_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3737 enum rtx_code code
= GET_CODE (x
);
3739 if (arm_address_register_rtx_p (x
, strict_p
))
3742 use_ldrd
= (TARGET_LDRD
3744 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3746 if (code
== POST_INC
|| code
== PRE_DEC
3747 || ((code
== PRE_INC
|| code
== POST_DEC
)
3748 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3749 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3751 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3752 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3753 && GET_CODE (XEXP (x
, 1)) == PLUS
3754 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3756 /* Thumb-2 only has autoincrement by constant. */
3757 rtx addend
= XEXP (XEXP (x
, 1), 1);
3758 HOST_WIDE_INT offset
;
3760 if (GET_CODE (addend
) != CONST_INT
)
3763 offset
= INTVAL(addend
);
3764 if (GET_MODE_SIZE (mode
) <= 4)
3765 return (offset
> -256 && offset
< 256);
3767 return (use_ldrd
&& offset
> -1024 && offset
< 1024
3768 && (offset
& 3) == 0);
3771 /* After reload constants split into minipools will have addresses
3772 from a LABEL_REF. */
3773 else if (reload_completed
3774 && (code
== LABEL_REF
3776 && GET_CODE (XEXP (x
, 0)) == PLUS
3777 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3778 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3781 else if (mode
== TImode
)
3784 else if (code
== PLUS
)
3786 rtx xop0
= XEXP (x
, 0);
3787 rtx xop1
= XEXP (x
, 1);
3789 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3790 && thumb2_legitimate_index_p (mode
, xop1
, strict_p
))
3791 || (arm_address_register_rtx_p (xop1
, strict_p
)
3792 && thumb2_legitimate_index_p (mode
, xop0
, strict_p
)));
3795 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3796 && code
== SYMBOL_REF
3797 && CONSTANT_POOL_ADDRESS_P (x
)
3799 && symbol_mentioned_p (get_pool_constant (x
))
3800 && ! pcrel_constant_p (get_pool_constant (x
))))
3806 /* Return nonzero if INDEX is valid for an address index operand in
3809 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3812 HOST_WIDE_INT range
;
3813 enum rtx_code code
= GET_CODE (index
);
3815 /* Standard coprocessor addressing modes. */
3816 if (TARGET_HARD_FLOAT
3817 && (TARGET_FPA
|| TARGET_MAVERICK
)
3818 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3819 || (TARGET_MAVERICK
&& mode
== DImode
)))
3820 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3821 && INTVAL (index
) > -1024
3822 && (INTVAL (index
) & 3) == 0);
3824 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3825 return (code
== CONST_INT
3826 && INTVAL (index
) < 1024
3827 && INTVAL (index
) > -1024
3828 && (INTVAL (index
) & 3) == 0);
3830 if (arm_address_register_rtx_p (index
, strict_p
)
3831 && (GET_MODE_SIZE (mode
) <= 4))
3834 if (mode
== DImode
|| mode
== DFmode
)
3836 if (code
== CONST_INT
)
3838 HOST_WIDE_INT val
= INTVAL (index
);
3841 return val
> -256 && val
< 256;
3843 return val
> -4096 && val
< 4092;
3846 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3849 if (GET_MODE_SIZE (mode
) <= 4
3852 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3856 rtx xiop0
= XEXP (index
, 0);
3857 rtx xiop1
= XEXP (index
, 1);
3859 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3860 && power_of_two_operand (xiop1
, SImode
))
3861 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3862 && power_of_two_operand (xiop0
, SImode
)));
3864 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3865 || code
== ASHIFT
|| code
== ROTATERT
)
3867 rtx op
= XEXP (index
, 1);
3869 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3870 && GET_CODE (op
) == CONST_INT
3872 && INTVAL (op
) <= 31);
3876 /* For ARM v4 we may be doing a sign-extend operation during the
3880 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3886 range
= (mode
== HImode
) ? 4095 : 4096;
3888 return (code
== CONST_INT
3889 && INTVAL (index
) < range
3890 && INTVAL (index
) > -range
);
3893 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3894 index operand. i.e. 1, 2, 4 or 8. */
3896 thumb2_index_mul_operand (rtx op
)
3900 if (GET_CODE(op
) != CONST_INT
)
3904 return (val
== 1 || val
== 2 || val
== 4 || val
== 8);
3907 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
3909 thumb2_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
3911 enum rtx_code code
= GET_CODE (index
);
3913 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
3914 /* Standard coprocessor addressing modes. */
3915 if (TARGET_HARD_FLOAT
3916 && (TARGET_FPA
|| TARGET_MAVERICK
)
3917 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3918 || (TARGET_MAVERICK
&& mode
== DImode
)))
3919 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3920 && INTVAL (index
) > -1024
3921 && (INTVAL (index
) & 3) == 0);
3923 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3924 return (code
== CONST_INT
3925 && INTVAL (index
) < 1024
3926 && INTVAL (index
) > -1024
3927 && (INTVAL (index
) & 3) == 0);
3929 if (arm_address_register_rtx_p (index
, strict_p
)
3930 && (GET_MODE_SIZE (mode
) <= 4))
3933 if (mode
== DImode
|| mode
== DFmode
)
3935 HOST_WIDE_INT val
= INTVAL (index
);
3936 /* ??? Can we assume ldrd for thumb2? */
3937 /* Thumb-2 ldrd only has reg+const addressing modes. */
3938 if (code
!= CONST_INT
)
3941 /* ldrd supports offsets of +-1020.
3942 However the ldr fallback does not. */
3943 return val
> -256 && val
< 256 && (val
& 3) == 0;
3948 rtx xiop0
= XEXP (index
, 0);
3949 rtx xiop1
= XEXP (index
, 1);
3951 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3952 && thumb2_index_mul_operand (xiop1
))
3953 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3954 && thumb2_index_mul_operand (xiop0
)));
3956 else if (code
== ASHIFT
)
3958 rtx op
= XEXP (index
, 1);
3960 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3961 && GET_CODE (op
) == CONST_INT
3963 && INTVAL (op
) <= 3);
3966 return (code
== CONST_INT
3967 && INTVAL (index
) < 4096
3968 && INTVAL (index
) > -256);
3971 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
3973 thumb1_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3977 if (GET_CODE (x
) != REG
)
3983 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3985 return (regno
<= LAST_LO_REGNUM
3986 || regno
> LAST_VIRTUAL_REGISTER
3987 || regno
== FRAME_POINTER_REGNUM
3988 || (GET_MODE_SIZE (mode
) >= 4
3989 && (regno
== STACK_POINTER_REGNUM
3990 || regno
>= FIRST_PSEUDO_REGISTER
3991 || x
== hard_frame_pointer_rtx
3992 || x
== arg_pointer_rtx
)));
3995 /* Return nonzero if x is a legitimate index register. This is the case
3996 for any base register that can access a QImode object. */
3998 thumb1_index_register_rtx_p (rtx x
, int strict_p
)
4000 return thumb1_base_register_rtx_p (x
, QImode
, strict_p
);
4003 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
4005 The AP may be eliminated to either the SP or the FP, so we use the
4006 least common denominator, e.g. SImode, and offsets from 0 to 64.
4008 ??? Verify whether the above is the right approach.
4010 ??? Also, the FP may be eliminated to the SP, so perhaps that
4011 needs special handling also.
4013 ??? Look at how the mips16 port solves this problem. It probably uses
4014 better ways to solve some of these problems.
4016 Although it is not incorrect, we don't accept QImode and HImode
4017 addresses based on the frame pointer or arg pointer until the
4018 reload pass starts. This is so that eliminating such addresses
4019 into stack based ones won't produce impossible code. */
4021 thumb1_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
4023 /* ??? Not clear if this is right. Experiment. */
4024 if (GET_MODE_SIZE (mode
) < 4
4025 && !(reload_in_progress
|| reload_completed
)
4026 && (reg_mentioned_p (frame_pointer_rtx
, x
)
4027 || reg_mentioned_p (arg_pointer_rtx
, x
)
4028 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
4029 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
4030 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
4031 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
4034 /* Accept any base register. SP only in SImode or larger. */
4035 else if (thumb1_base_register_rtx_p (x
, mode
, strict_p
))
4038 /* This is PC relative data before arm_reorg runs. */
4039 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
4040 && GET_CODE (x
) == SYMBOL_REF
4041 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
4044 /* This is PC relative data after arm_reorg runs. */
4045 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
4046 && (GET_CODE (x
) == LABEL_REF
4047 || (GET_CODE (x
) == CONST
4048 && GET_CODE (XEXP (x
, 0)) == PLUS
4049 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
4050 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
4053 /* Post-inc indexing only supported for SImode and larger. */
4054 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
4055 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
))
4058 else if (GET_CODE (x
) == PLUS
)
4060 /* REG+REG address can be any two index registers. */
4061 /* We disallow FRAME+REG addressing since we know that FRAME
4062 will be replaced with STACK, and SP relative addressing only
4063 permits SP+OFFSET. */
4064 if (GET_MODE_SIZE (mode
) <= 4
4065 && XEXP (x
, 0) != frame_pointer_rtx
4066 && XEXP (x
, 1) != frame_pointer_rtx
4067 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
4068 && thumb1_index_register_rtx_p (XEXP (x
, 1), strict_p
))
4071 /* REG+const has 5-7 bit offset for non-SP registers. */
4072 else if ((thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
4073 || XEXP (x
, 0) == arg_pointer_rtx
)
4074 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4075 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4078 /* REG+const has 10 bit offset for SP, but only SImode and
4079 larger is supported. */
4080 /* ??? Should probably check for DI/DFmode overflow here
4081 just like GO_IF_LEGITIMATE_OFFSET does. */
4082 else if (GET_CODE (XEXP (x
, 0)) == REG
4083 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
4084 && GET_MODE_SIZE (mode
) >= 4
4085 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4086 && INTVAL (XEXP (x
, 1)) >= 0
4087 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
4088 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
4091 else if (GET_CODE (XEXP (x
, 0)) == REG
4092 && (REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
4093 || REGNO (XEXP (x
, 0)) == ARG_POINTER_REGNUM
4094 || (REGNO (XEXP (x
, 0)) >= FIRST_VIRTUAL_REGISTER
4095 && REGNO (XEXP (x
, 0)) <= LAST_VIRTUAL_REGISTER
))
4096 && GET_MODE_SIZE (mode
) >= 4
4097 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4098 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
4102 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4103 && GET_MODE_SIZE (mode
) == 4
4104 && GET_CODE (x
) == SYMBOL_REF
4105 && CONSTANT_POOL_ADDRESS_P (x
)
4107 && symbol_mentioned_p (get_pool_constant (x
))
4108 && ! pcrel_constant_p (get_pool_constant (x
))))
4114 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4115 instruction of mode MODE. */
4117 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
4119 switch (GET_MODE_SIZE (mode
))
4122 return val
>= 0 && val
< 32;
4125 return val
>= 0 && val
< 64 && (val
& 1) == 0;
4129 && (val
+ GET_MODE_SIZE (mode
)) <= 128
4134 /* Build the SYMBOL_REF for __tls_get_addr. */
4136 static GTY(()) rtx tls_get_addr_libfunc
;
4139 get_tls_get_addr (void)
4141 if (!tls_get_addr_libfunc
)
4142 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
4143 return tls_get_addr_libfunc
;
4147 arm_load_tp (rtx target
)
4150 target
= gen_reg_rtx (SImode
);
4154 /* Can return in any reg. */
4155 emit_insn (gen_load_tp_hard (target
));
4159 /* Always returned in r0. Immediately copy the result into a pseudo,
4160 otherwise other uses of r0 (e.g. setting up function arguments) may
4161 clobber the value. */
4165 emit_insn (gen_load_tp_soft ());
4167 tmp
= gen_rtx_REG (SImode
, 0);
4168 emit_move_insn (target
, tmp
);
4174 load_tls_operand (rtx x
, rtx reg
)
4178 if (reg
== NULL_RTX
)
4179 reg
= gen_reg_rtx (SImode
);
4181 tmp
= gen_rtx_CONST (SImode
, x
);
4183 emit_move_insn (reg
, tmp
);
4189 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
4191 rtx insns
, label
, labelno
, sum
;
4195 labelno
= GEN_INT (pic_labelno
++);
4196 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
4197 label
= gen_rtx_CONST (VOIDmode
, label
);
4199 sum
= gen_rtx_UNSPEC (Pmode
,
4200 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
4201 GEN_INT (TARGET_ARM
? 8 : 4)),
4203 reg
= load_tls_operand (sum
, reg
);
4206 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
4207 else if (TARGET_THUMB2
)
4210 /* Thumb-2 only allows very limited access to the PC. Calculate
4211 the address in a temporary register. */
4212 tmp
= gen_reg_rtx (SImode
);
4213 emit_insn (gen_pic_load_dot_plus_four (tmp
, labelno
));
4214 emit_insn (gen_addsi3(reg
, reg
, tmp
));
4216 else /* TARGET_THUMB1 */
4217 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
4219 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
4220 Pmode
, 1, reg
, Pmode
);
4222 insns
= get_insns ();
4229 legitimize_tls_address (rtx x
, rtx reg
)
4231 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
4232 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
4236 case TLS_MODEL_GLOBAL_DYNAMIC
:
4237 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
4238 dest
= gen_reg_rtx (Pmode
);
4239 emit_libcall_block (insns
, dest
, ret
, x
);
4242 case TLS_MODEL_LOCAL_DYNAMIC
:
4243 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
4245 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4246 share the LDM result with other LD model accesses. */
4247 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
4249 dest
= gen_reg_rtx (Pmode
);
4250 emit_libcall_block (insns
, dest
, ret
, eqv
);
4252 /* Load the addend. */
4253 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
4255 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
4256 return gen_rtx_PLUS (Pmode
, dest
, addend
);
4258 case TLS_MODEL_INITIAL_EXEC
:
4259 labelno
= GEN_INT (pic_labelno
++);
4260 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
4261 label
= gen_rtx_CONST (VOIDmode
, label
);
4262 sum
= gen_rtx_UNSPEC (Pmode
,
4263 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
4264 GEN_INT (TARGET_ARM
? 8 : 4)),
4266 reg
= load_tls_operand (sum
, reg
);
4269 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
4270 else if (TARGET_THUMB2
)
4273 /* Thumb-2 only allows very limited access to the PC. Calculate
4274 the address in a temporary register. */
4275 tmp
= gen_reg_rtx (SImode
);
4276 emit_insn (gen_pic_load_dot_plus_four (tmp
, labelno
));
4277 emit_insn (gen_addsi3(reg
, reg
, tmp
));
4278 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
4282 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
4283 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
4286 tp
= arm_load_tp (NULL_RTX
);
4288 return gen_rtx_PLUS (Pmode
, tp
, reg
);
4290 case TLS_MODEL_LOCAL_EXEC
:
4291 tp
= arm_load_tp (NULL_RTX
);
4293 reg
= gen_rtx_UNSPEC (Pmode
,
4294 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
4296 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
4298 return gen_rtx_PLUS (Pmode
, tp
, reg
);
4305 /* Try machine-dependent ways of modifying an illegitimate address
4306 to be legitimate. If we find one, return the new, valid address. */
4308 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4310 if (arm_tls_symbol_p (x
))
4311 return legitimize_tls_address (x
, NULL_RTX
);
4313 if (GET_CODE (x
) == PLUS
)
4315 rtx xop0
= XEXP (x
, 0);
4316 rtx xop1
= XEXP (x
, 1);
4318 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
4319 xop0
= force_reg (SImode
, xop0
);
4321 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
4322 xop1
= force_reg (SImode
, xop1
);
4324 if (ARM_BASE_REGISTER_RTX_P (xop0
)
4325 && GET_CODE (xop1
) == CONST_INT
)
4327 HOST_WIDE_INT n
, low_n
;
4331 /* VFP addressing modes actually allow greater offsets, but for
4332 now we just stick with the lowest common denominator. */
4334 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
4346 low_n
= ((mode
) == TImode
? 0
4347 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
4351 base_reg
= gen_reg_rtx (SImode
);
4352 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
4353 emit_move_insn (base_reg
, val
);
4354 x
= plus_constant (base_reg
, low_n
);
4356 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4357 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4360 /* XXX We don't allow MINUS any more -- see comment in
4361 arm_legitimate_address_p (). */
4362 else if (GET_CODE (x
) == MINUS
)
4364 rtx xop0
= XEXP (x
, 0);
4365 rtx xop1
= XEXP (x
, 1);
4367 if (CONSTANT_P (xop0
))
4368 xop0
= force_reg (SImode
, xop0
);
4370 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
4371 xop1
= force_reg (SImode
, xop1
);
4373 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4374 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
4377 /* Make sure to take full advantage of the pre-indexed addressing mode
4378 with absolute addresses which often allows for the base register to
4379 be factorized for multiple adjacent memory references, and it might
4380 even allows for the mini pool to be avoided entirely. */
4381 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
4384 HOST_WIDE_INT mask
, base
, index
;
4387 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4388 use a 8 bit index. So let's use a 12 bit index for SImode only and
4389 hope that arm_gen_constant will enable ldrb to use more bits. */
4390 bits
= (mode
== SImode
) ? 12 : 8;
4391 mask
= (1 << bits
) - 1;
4392 base
= INTVAL (x
) & ~mask
;
4393 index
= INTVAL (x
) & mask
;
4394 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4396 /* It'll most probably be more efficient to generate the base
4397 with more bits set and use a negative index instead. */
4401 base_reg
= force_reg (SImode
, GEN_INT (base
));
4402 x
= plus_constant (base_reg
, index
);
4407 /* We need to find and carefully transform any SYMBOL and LABEL
4408 references; so go back to the original address expression. */
4409 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4411 if (new_x
!= orig_x
)
4419 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4420 to be legitimate. If we find one, return the new, valid address. */
4422 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4424 if (arm_tls_symbol_p (x
))
4425 return legitimize_tls_address (x
, NULL_RTX
);
4427 if (GET_CODE (x
) == PLUS
4428 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4429 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4430 || INTVAL (XEXP (x
, 1)) < 0))
4432 rtx xop0
= XEXP (x
, 0);
4433 rtx xop1
= XEXP (x
, 1);
4434 HOST_WIDE_INT offset
= INTVAL (xop1
);
4436 /* Try and fold the offset into a biasing of the base register and
4437 then offsetting that. Don't do this when optimizing for space
4438 since it can cause too many CSEs. */
4439 if (optimize_size
&& offset
>= 0
4440 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4442 HOST_WIDE_INT delta
;
4445 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4446 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4447 delta
= 31 * GET_MODE_SIZE (mode
);
4449 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4451 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4453 x
= plus_constant (xop0
, delta
);
4455 else if (offset
< 0 && offset
> -256)
4456 /* Small negative offsets are best done with a subtract before the
4457 dereference, forcing these into a register normally takes two
4459 x
= force_operand (x
, NULL_RTX
);
4462 /* For the remaining cases, force the constant into a register. */
4463 xop1
= force_reg (SImode
, xop1
);
4464 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4467 else if (GET_CODE (x
) == PLUS
4468 && s_register_operand (XEXP (x
, 1), SImode
)
4469 && !s_register_operand (XEXP (x
, 0), SImode
))
4471 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4473 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4478 /* We need to find and carefully transform any SYMBOL and LABEL
4479 references; so go back to the original address expression. */
4480 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4482 if (new_x
!= orig_x
)
4490 thumb_legitimize_reload_address (rtx
*x_p
,
4491 enum machine_mode mode
,
4492 int opnum
, int type
,
4493 int ind_levels ATTRIBUTE_UNUSED
)
4497 if (GET_CODE (x
) == PLUS
4498 && GET_MODE_SIZE (mode
) < 4
4499 && REG_P (XEXP (x
, 0))
4500 && XEXP (x
, 0) == stack_pointer_rtx
4501 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4502 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4507 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4508 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4512 /* If both registers are hi-regs, then it's better to reload the
4513 entire expression rather than each register individually. That
4514 only requires one reload register rather than two. */
4515 if (GET_CODE (x
) == PLUS
4516 && REG_P (XEXP (x
, 0))
4517 && REG_P (XEXP (x
, 1))
4518 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4519 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4524 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4525 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4532 /* Test for various thread-local symbols. */
4534 /* Return TRUE if X is a thread-local symbol. */
4537 arm_tls_symbol_p (rtx x
)
4539 if (! TARGET_HAVE_TLS
)
4542 if (GET_CODE (x
) != SYMBOL_REF
)
4545 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4548 /* Helper for arm_tls_referenced_p. */
4551 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4553 if (GET_CODE (*x
) == SYMBOL_REF
)
4554 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4556 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4557 TLS offsets, not real symbol references. */
4558 if (GET_CODE (*x
) == UNSPEC
4559 && XINT (*x
, 1) == UNSPEC_TLS
)
4565 /* Return TRUE if X contains any TLS symbol references. */
4568 arm_tls_referenced_p (rtx x
)
4570 if (! TARGET_HAVE_TLS
)
4573 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4576 #define REG_OR_SUBREG_REG(X) \
4577 (GET_CODE (X) == REG \
4578 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4580 #define REG_OR_SUBREG_RTX(X) \
4581 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4583 #ifndef COSTS_N_INSNS
4584 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4587 thumb1_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4589 enum machine_mode mode
= GET_MODE (x
);
4602 return COSTS_N_INSNS (1);
4605 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4608 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4615 return COSTS_N_INSNS (2) + cycles
;
4617 return COSTS_N_INSNS (1) + 16;
4620 return (COSTS_N_INSNS (1)
4621 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4622 + GET_CODE (SET_DEST (x
)) == MEM
));
4627 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4629 if (thumb_shiftable_const (INTVAL (x
)))
4630 return COSTS_N_INSNS (2);
4631 return COSTS_N_INSNS (3);
4633 else if ((outer
== PLUS
|| outer
== COMPARE
)
4634 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4636 else if (outer
== AND
4637 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4638 return COSTS_N_INSNS (1);
4639 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4640 || outer
== LSHIFTRT
)
4642 return COSTS_N_INSNS (2);
4648 return COSTS_N_INSNS (3);
4666 /* XXX another guess. */
4667 /* Memory costs quite a lot for the first word, but subsequent words
4668 load at the equivalent of a single insn each. */
4669 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4670 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4675 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4680 /* XXX still guessing. */
4681 switch (GET_MODE (XEXP (x
, 0)))
4684 return (1 + (mode
== DImode
? 4 : 0)
4685 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4688 return (4 + (mode
== DImode
? 4 : 0)
4689 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4692 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4704 /* Worker routine for arm_rtx_costs. */
4705 /* ??? This needs updating for thumb2. */
4707 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4709 enum machine_mode mode
= GET_MODE (x
);
4710 enum rtx_code subcode
;
4716 /* Memory costs quite a lot for the first word, but subsequent words
4717 load at the equivalent of a single insn each. */
4718 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4719 + (GET_CODE (x
) == SYMBOL_REF
4720 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4726 return optimize_size
? COSTS_N_INSNS (2) : 100;
4729 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4736 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4738 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4739 + ((GET_CODE (XEXP (x
, 0)) == REG
4740 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4741 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4743 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4744 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4745 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4747 + ((GET_CODE (XEXP (x
, 1)) == REG
4748 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4749 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4750 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4755 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4756 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4757 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4758 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4761 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4762 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4763 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4764 && arm_const_double_rtx (XEXP (x
, 1))))
4766 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4767 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4768 && arm_const_double_rtx (XEXP (x
, 0))))
4771 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4772 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4773 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4774 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4775 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4776 || subcode
== ROTATE
|| subcode
== ROTATERT
4778 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4779 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4780 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4781 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4782 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4783 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4784 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4789 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4791 extra_cost
= rtx_cost (XEXP (x
, 0), code
);
4792 if (!REG_OR_SUBREG_REG (XEXP (x
, 1)))
4793 extra_cost
+= 4 * ARM_NUM_REGS (mode
);
4797 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4798 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4799 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4800 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4801 && arm_const_double_rtx (XEXP (x
, 1))))
4805 case AND
: case XOR
: case IOR
:
4808 /* Normally the frame registers will be spilt into reg+const during
4809 reload, so it is a bad idea to combine them with other instructions,
4810 since then they might not be moved outside of loops. As a compromise
4811 we allow integration with ops that have a constant as their second
4813 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4814 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4815 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4816 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4817 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4821 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4822 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4823 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4824 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4827 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4828 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4829 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4830 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4831 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4834 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4835 return (1 + extra_cost
4836 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4837 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4838 || subcode
== ROTATE
|| subcode
== ROTATERT
4840 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4841 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4842 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4843 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4844 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4845 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4851 /* This should have been handled by the CPU specific routines. */
4855 if (arm_arch3m
&& mode
== SImode
4856 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4857 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4858 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4859 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4860 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4861 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4866 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4867 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4871 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4873 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4876 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4884 return 4 + (mode
== DImode
? 4 : 0);
4887 /* ??? value extensions are cheaper on armv6. */
4888 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4889 return (4 + (mode
== DImode
? 4 : 0)
4890 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4893 switch (GET_MODE (XEXP (x
, 0)))
4896 return (1 + (mode
== DImode
? 4 : 0)
4897 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4900 return (4 + (mode
== DImode
? 4 : 0)
4901 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4904 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4919 if (const_ok_for_arm (INTVAL (x
)))
4920 return outer
== SET
? 2 : -1;
4921 else if (outer
== AND
4922 && const_ok_for_arm (~INTVAL (x
)))
4924 else if ((outer
== COMPARE
4925 || outer
== PLUS
|| outer
== MINUS
)
4926 && const_ok_for_arm (-INTVAL (x
)))
4937 if (arm_const_double_rtx (x
))
4938 return outer
== SET
? 2 : -1;
4939 else if ((outer
== COMPARE
|| outer
== PLUS
)
4940 && neg_const_double_rtx_ok_for_fpa (x
))
4949 /* RTX costs when optimizing for size. */
4951 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4953 enum machine_mode mode
= GET_MODE (x
);
4957 /* XXX TBD. For now, use the standard costs. */
4958 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
4965 /* A memory access costs 1 insn if the mode is small, or the address is
4966 a single register, otherwise it costs one insn per word. */
4967 if (REG_P (XEXP (x
, 0)))
4968 *total
= COSTS_N_INSNS (1);
4970 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4977 /* Needs a libcall, so it costs about this. */
4978 *total
= COSTS_N_INSNS (2);
4982 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4984 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4992 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4994 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4997 else if (mode
== SImode
)
4999 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
5000 /* Slightly disparage register shifts, but not by much. */
5001 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5002 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
5006 /* Needs a libcall. */
5007 *total
= COSTS_N_INSNS (2);
5011 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5013 *total
= COSTS_N_INSNS (1);
5019 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
5020 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
5022 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
5023 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
5024 || subcode1
== ROTATE
|| subcode1
== ROTATERT
5025 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
5026 || subcode1
== ASHIFTRT
)
5028 /* It's just the cost of the two operands. */
5033 *total
= COSTS_N_INSNS (1);
5037 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5041 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5043 *total
= COSTS_N_INSNS (1);
5048 case AND
: case XOR
: case IOR
:
5051 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
5053 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
5054 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
5055 || (code
== AND
&& subcode
== NOT
))
5057 /* It's just the cost of the two operands. */
5063 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5067 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5071 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5072 *total
= COSTS_N_INSNS (1);
5075 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5084 if (cc_register (XEXP (x
, 0), VOIDmode
))
5087 *total
= COSTS_N_INSNS (1);
5091 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5092 *total
= COSTS_N_INSNS (1);
5094 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
5099 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
5101 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
5102 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
5105 *total
+= COSTS_N_INSNS (1);
5110 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
5112 switch (GET_MODE (XEXP (x
, 0)))
5115 *total
+= COSTS_N_INSNS (1);
5119 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
5125 *total
+= COSTS_N_INSNS (2);
5130 *total
+= COSTS_N_INSNS (1);
5135 if (const_ok_for_arm (INTVAL (x
)))
5136 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
5137 else if (const_ok_for_arm (~INTVAL (x
)))
5138 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
5139 else if (const_ok_for_arm (-INTVAL (x
)))
5141 if (outer_code
== COMPARE
|| outer_code
== PLUS
5142 || outer_code
== MINUS
)
5145 *total
= COSTS_N_INSNS (1);
5148 *total
= COSTS_N_INSNS (2);
5154 *total
= COSTS_N_INSNS (2);
5158 *total
= COSTS_N_INSNS (4);
5162 if (mode
!= VOIDmode
)
5163 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5165 *total
= COSTS_N_INSNS (4); /* How knows? */
5170 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5171 supported on any "slowmul" cores, so it can be ignored. */
5174 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5176 enum machine_mode mode
= GET_MODE (x
);
5180 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5187 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5194 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5196 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
5197 & (unsigned HOST_WIDE_INT
) 0xffffffff);
5198 int cost
, const_ok
= const_ok_for_arm (i
);
5199 int j
, booth_unit_size
;
5201 /* Tune as appropriate. */
5202 cost
= const_ok
? 4 : 8;
5203 booth_unit_size
= 2;
5204 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
5206 i
>>= booth_unit_size
;
5214 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5215 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5219 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5225 /* RTX cost for cores with a fast multiply unit (M variants). */
5228 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5230 enum machine_mode mode
= GET_MODE (x
);
5234 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5238 /* ??? should thumb2 use different costs? */
5242 /* There is no point basing this on the tuning, since it is always the
5243 fast variant if it exists at all. */
5245 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5246 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5247 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5254 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5261 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5263 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
5264 & (unsigned HOST_WIDE_INT
) 0xffffffff);
5265 int cost
, const_ok
= const_ok_for_arm (i
);
5266 int j
, booth_unit_size
;
5268 /* Tune as appropriate. */
5269 cost
= const_ok
? 4 : 8;
5270 booth_unit_size
= 8;
5271 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
5273 i
>>= booth_unit_size
;
5281 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5282 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5286 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5292 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5293 so it can be ignored. */
5296 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5298 enum machine_mode mode
= GET_MODE (x
);
5302 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5309 /* There is no point basing this on the tuning, since it is always the
5310 fast variant if it exists at all. */
5312 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5313 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5314 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5321 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5328 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5330 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
5331 & (unsigned HOST_WIDE_INT
) 0xffffffff);
5332 int cost
, const_ok
= const_ok_for_arm (i
);
5333 unsigned HOST_WIDE_INT masked_const
;
5335 /* The cost will be related to two insns.
5336 First a load of the constant (MOV or LDR), then a multiply. */
5339 cost
+= 1; /* LDR is probably more expensive because
5340 of longer result latency. */
5341 masked_const
= i
& 0xffff8000;
5342 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
5344 masked_const
= i
& 0xf8000000;
5345 if (masked_const
== 0 || masked_const
== 0xf8000000)
5354 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5355 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5359 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5360 will stall until the multiplication is complete. */
5361 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5362 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
5364 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5368 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5374 /* RTX costs for 9e (and later) cores. */
5377 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5379 enum machine_mode mode
= GET_MODE (x
);
5388 *total
= COSTS_N_INSNS (3);
5392 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5400 /* There is no point basing this on the tuning, since it is always the
5401 fast variant if it exists at all. */
5403 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5404 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5405 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5412 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5429 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5430 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5434 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5438 /* All address computations that can be done are free, but rtx cost returns
5439 the same for practically all of them. So we weight the different types
5440 of address here in the order (most pref first):
5441 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5443 arm_arm_address_cost (rtx x
)
5445 enum rtx_code c
= GET_CODE (x
);
5447 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5449 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5452 if (c
== PLUS
|| c
== MINUS
)
5454 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5457 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5467 arm_thumb_address_cost (rtx x
)
5469 enum rtx_code c
= GET_CODE (x
);
5474 && GET_CODE (XEXP (x
, 0)) == REG
5475 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5482 arm_address_cost (rtx x
)
5484 return TARGET_32BIT
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5488 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5492 /* Some true dependencies can have a higher cost depending
5493 on precisely how certain input operands are used. */
5495 && REG_NOTE_KIND (link
) == 0
5496 && recog_memoized (insn
) >= 0
5497 && recog_memoized (dep
) >= 0)
5499 int shift_opnum
= get_attr_shift (insn
);
5500 enum attr_type attr_type
= get_attr_type (dep
);
5502 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5503 operand for INSN. If we have a shifted input operand and the
5504 instruction we depend on is another ALU instruction, then we may
5505 have to account for an additional stall. */
5506 if (shift_opnum
!= 0
5507 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5509 rtx shifted_operand
;
5512 /* Get the shifted operand. */
5513 extract_insn (insn
);
5514 shifted_operand
= recog_data
.operand
[shift_opnum
];
5516 /* Iterate over all the operands in DEP. If we write an operand
5517 that overlaps with SHIFTED_OPERAND, then we have increase the
5518 cost of this dependency. */
5520 preprocess_constraints ();
5521 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5523 /* We can ignore strict inputs. */
5524 if (recog_data
.operand_type
[opno
] == OP_IN
)
5527 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5534 /* XXX This is not strictly true for the FPA. */
5535 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5536 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5539 /* Call insns don't incur a stall, even if they follow a load. */
5540 if (REG_NOTE_KIND (link
) == 0
5541 && GET_CODE (insn
) == CALL_INSN
)
5544 if ((i_pat
= single_set (insn
)) != NULL
5545 && GET_CODE (SET_SRC (i_pat
)) == MEM
5546 && (d_pat
= single_set (dep
)) != NULL
5547 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5549 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5550 /* This is a load after a store, there is no conflict if the load reads
5551 from a cached area. Assume that loads from the stack, and from the
5552 constant pool are cached, and that others will miss. This is a
5555 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5556 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5557 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5558 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5565 static int fp_consts_inited
= 0;
5567 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5568 static const char * const strings_fp
[8] =
5571 "4", "5", "0.5", "10"
5574 static REAL_VALUE_TYPE values_fp
[8];
5577 init_fp_table (void)
5583 fp_consts_inited
= 1;
5585 fp_consts_inited
= 8;
5587 for (i
= 0; i
< fp_consts_inited
; i
++)
5589 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5594 /* Return TRUE if rtx X is a valid immediate FP constant. */
5596 arm_const_double_rtx (rtx x
)
5601 if (!fp_consts_inited
)
5604 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5605 if (REAL_VALUE_MINUS_ZERO (r
))
5608 for (i
= 0; i
< fp_consts_inited
; i
++)
5609 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5615 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5617 neg_const_double_rtx_ok_for_fpa (rtx x
)
5622 if (!fp_consts_inited
)
5625 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5626 r
= REAL_VALUE_NEGATE (r
);
5627 if (REAL_VALUE_MINUS_ZERO (r
))
5630 for (i
= 0; i
< 8; i
++)
5631 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5637 /* Predicates for `match_operand' and `match_operator'. */
5639 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5641 cirrus_memory_offset (rtx op
)
5643 /* Reject eliminable registers. */
5644 if (! (reload_in_progress
|| reload_completed
)
5645 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5646 || reg_mentioned_p (arg_pointer_rtx
, op
)
5647 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5648 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5649 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5650 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5653 if (GET_CODE (op
) == MEM
)
5659 /* Match: (mem (reg)). */
5660 if (GET_CODE (ind
) == REG
)
5666 if (GET_CODE (ind
) == PLUS
5667 && GET_CODE (XEXP (ind
, 0)) == REG
5668 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5669 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5676 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5677 WB is true if full writeback address modes are allowed and is false
5678 if limited writeback address modes (POST_INC and PRE_DEC) are
5682 arm_coproc_mem_operand (rtx op
, bool wb
)
5686 /* Reject eliminable registers. */
5687 if (! (reload_in_progress
|| reload_completed
)
5688 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5689 || reg_mentioned_p (arg_pointer_rtx
, op
)
5690 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5691 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5692 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5693 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5696 /* Constants are converted into offsets from labels. */
5697 if (GET_CODE (op
) != MEM
)
5702 if (reload_completed
5703 && (GET_CODE (ind
) == LABEL_REF
5704 || (GET_CODE (ind
) == CONST
5705 && GET_CODE (XEXP (ind
, 0)) == PLUS
5706 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5707 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5710 /* Match: (mem (reg)). */
5711 if (GET_CODE (ind
) == REG
)
5712 return arm_address_register_rtx_p (ind
, 0);
5714 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
5715 acceptable in any case (subject to verification by
5716 arm_address_register_rtx_p). We need WB to be true to accept
5717 PRE_INC and POST_DEC. */
5718 if (GET_CODE (ind
) == POST_INC
5719 || GET_CODE (ind
) == PRE_DEC
5721 && (GET_CODE (ind
) == PRE_INC
5722 || GET_CODE (ind
) == POST_DEC
)))
5723 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5726 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5727 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5728 && GET_CODE (XEXP (ind
, 1)) == PLUS
5729 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5730 ind
= XEXP (ind
, 1);
5735 if (GET_CODE (ind
) == PLUS
5736 && GET_CODE (XEXP (ind
, 0)) == REG
5737 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5738 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5739 && INTVAL (XEXP (ind
, 1)) > -1024
5740 && INTVAL (XEXP (ind
, 1)) < 1024
5741 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5747 /* Return true if X is a register that will be eliminated later on. */
5749 arm_eliminable_register (rtx x
)
5751 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5752 || REGNO (x
) == ARG_POINTER_REGNUM
5753 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5754 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5757 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5758 VFP registers. Otherwise return NO_REGS. */
5761 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5763 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5766 return GENERAL_REGS
;
5769 /* Values which must be returned in the most-significant end of the return
5773 arm_return_in_msb (tree valtype
)
5775 return (TARGET_AAPCS_BASED
5777 && (AGGREGATE_TYPE_P (valtype
)
5778 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5781 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5782 Use by the Cirrus Maverick code which has to workaround
5783 a hardware bug triggered by such instructions. */
5785 arm_memory_load_p (rtx insn
)
5787 rtx body
, lhs
, rhs
;;
5789 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5792 body
= PATTERN (insn
);
5794 if (GET_CODE (body
) != SET
)
5797 lhs
= XEXP (body
, 0);
5798 rhs
= XEXP (body
, 1);
5800 lhs
= REG_OR_SUBREG_RTX (lhs
);
5802 /* If the destination is not a general purpose
5803 register we do not have to worry. */
5804 if (GET_CODE (lhs
) != REG
5805 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5808 /* As well as loads from memory we also have to react
5809 to loads of invalid constants which will be turned
5810 into loads from the minipool. */
5811 return (GET_CODE (rhs
) == MEM
5812 || GET_CODE (rhs
) == SYMBOL_REF
5813 || note_invalid_constants (insn
, -1, false));
5816 /* Return TRUE if INSN is a Cirrus instruction. */
5818 arm_cirrus_insn_p (rtx insn
)
5820 enum attr_cirrus attr
;
5822 /* get_attr cannot accept USE or CLOBBER. */
5824 || GET_CODE (insn
) != INSN
5825 || GET_CODE (PATTERN (insn
)) == USE
5826 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5829 attr
= get_attr_cirrus (insn
);
5831 return attr
!= CIRRUS_NOT
;
5834 /* Cirrus reorg for invalid instruction combinations. */
5836 cirrus_reorg (rtx first
)
5838 enum attr_cirrus attr
;
5839 rtx body
= PATTERN (first
);
5843 /* Any branch must be followed by 2 non Cirrus instructions. */
5844 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5847 t
= next_nonnote_insn (first
);
5849 if (arm_cirrus_insn_p (t
))
5852 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5856 emit_insn_after (gen_nop (), first
);
5861 /* (float (blah)) is in parallel with a clobber. */
5862 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5863 body
= XVECEXP (body
, 0, 0);
5865 if (GET_CODE (body
) == SET
)
5867 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5869 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5870 be followed by a non Cirrus insn. */
5871 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5873 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5874 emit_insn_after (gen_nop (), first
);
5878 else if (arm_memory_load_p (first
))
5880 unsigned int arm_regno
;
5882 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5883 ldr/cfmv64hr combination where the Rd field is the same
5884 in both instructions must be split with a non Cirrus
5891 /* Get Arm register number for ldr insn. */
5892 if (GET_CODE (lhs
) == REG
)
5893 arm_regno
= REGNO (lhs
);
5896 gcc_assert (GET_CODE (rhs
) == REG
);
5897 arm_regno
= REGNO (rhs
);
5901 first
= next_nonnote_insn (first
);
5903 if (! arm_cirrus_insn_p (first
))
5906 body
= PATTERN (first
);
5908 /* (float (blah)) is in parallel with a clobber. */
5909 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5910 body
= XVECEXP (body
, 0, 0);
5912 if (GET_CODE (body
) == FLOAT
)
5913 body
= XEXP (body
, 0);
5915 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5916 && GET_CODE (XEXP (body
, 1)) == REG
5917 && arm_regno
== REGNO (XEXP (body
, 1)))
5918 emit_insn_after (gen_nop (), first
);
5924 /* get_attr cannot accept USE or CLOBBER. */
5926 || GET_CODE (first
) != INSN
5927 || GET_CODE (PATTERN (first
)) == USE
5928 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5931 attr
= get_attr_cirrus (first
);
5933 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5934 must be followed by a non-coprocessor instruction. */
5935 if (attr
== CIRRUS_COMPARE
)
5939 t
= next_nonnote_insn (first
);
5941 if (arm_cirrus_insn_p (t
))
5944 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5948 emit_insn_after (gen_nop (), first
);
5954 /* Return TRUE if X references a SYMBOL_REF. */
5956 symbol_mentioned_p (rtx x
)
5961 if (GET_CODE (x
) == SYMBOL_REF
)
5964 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5965 are constant offsets, not symbols. */
5966 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5969 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5971 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5977 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5978 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5981 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5988 /* Return TRUE if X references a LABEL_REF. */
5990 label_mentioned_p (rtx x
)
5995 if (GET_CODE (x
) == LABEL_REF
)
5998 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5999 instruction, but they are constant offsets, not symbols. */
6000 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
6003 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6004 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6010 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6011 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
6014 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
6022 tls_mentioned_p (rtx x
)
6024 switch (GET_CODE (x
))
6027 return tls_mentioned_p (XEXP (x
, 0));
6030 if (XINT (x
, 1) == UNSPEC_TLS
)
6038 /* Must not copy a SET whose source operand is PC-relative. */
6041 arm_cannot_copy_insn_p (rtx insn
)
6043 rtx pat
= PATTERN (insn
);
6045 if (GET_CODE (pat
) == PARALLEL
6046 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
6048 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
6050 if (GET_CODE (rhs
) == UNSPEC
6051 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
6054 if (GET_CODE (rhs
) == MEM
6055 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
6056 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
6066 enum rtx_code code
= GET_CODE (x
);
6083 /* Return 1 if memory locations are adjacent. */
6085 adjacent_mem_locations (rtx a
, rtx b
)
6087 /* We don't guarantee to preserve the order of these memory refs. */
6088 if (volatile_refs_p (a
) || volatile_refs_p (b
))
6091 if ((GET_CODE (XEXP (a
, 0)) == REG
6092 || (GET_CODE (XEXP (a
, 0)) == PLUS
6093 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
6094 && (GET_CODE (XEXP (b
, 0)) == REG
6095 || (GET_CODE (XEXP (b
, 0)) == PLUS
6096 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
6098 HOST_WIDE_INT val0
= 0, val1
= 0;
6102 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
6104 reg0
= XEXP (XEXP (a
, 0), 0);
6105 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
6110 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
6112 reg1
= XEXP (XEXP (b
, 0), 0);
6113 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
6118 /* Don't accept any offset that will require multiple
6119 instructions to handle, since this would cause the
6120 arith_adjacentmem pattern to output an overlong sequence. */
6121 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
6124 /* Don't allow an eliminable register: register elimination can make
6125 the offset too large. */
6126 if (arm_eliminable_register (reg0
))
6129 val_diff
= val1
- val0
;
6133 /* If the target has load delay slots, then there's no benefit
6134 to using an ldm instruction unless the offset is zero and
6135 we are optimizing for size. */
6136 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
6137 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
6138 && (val_diff
== 4 || val_diff
== -4));
6141 return ((REGNO (reg0
) == REGNO (reg1
))
6142 && (val_diff
== 4 || val_diff
== -4));
6149 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
6150 HOST_WIDE_INT
*load_offset
)
6152 int unsorted_regs
[4];
6153 HOST_WIDE_INT unsorted_offsets
[4];
6158 /* Can only handle 2, 3, or 4 insns at present,
6159 though could be easily extended if required. */
6160 gcc_assert (nops
>= 2 && nops
<= 4);
6162 /* Loop over the operands and check that the memory references are
6163 suitable (i.e. immediate offsets from the same base register). At
6164 the same time, extract the target register, and the memory
6166 for (i
= 0; i
< nops
; i
++)
6171 /* Convert a subreg of a mem into the mem itself. */
6172 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6173 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6175 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6177 /* Don't reorder volatile memory references; it doesn't seem worth
6178 looking for the case where the order is ok anyway. */
6179 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6182 offset
= const0_rtx
;
6184 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6185 || (GET_CODE (reg
) == SUBREG
6186 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6187 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6188 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6190 || (GET_CODE (reg
) == SUBREG
6191 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6192 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6197 base_reg
= REGNO (reg
);
6198 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6199 ? REGNO (operands
[i
])
6200 : REGNO (SUBREG_REG (operands
[i
])));
6205 if (base_reg
!= (int) REGNO (reg
))
6206 /* Not addressed from the same base register. */
6209 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6210 ? REGNO (operands
[i
])
6211 : REGNO (SUBREG_REG (operands
[i
])));
6212 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6216 /* If it isn't an integer register, or if it overwrites the
6217 base register but isn't the last insn in the list, then
6218 we can't do this. */
6219 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
6220 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
6223 unsorted_offsets
[i
] = INTVAL (offset
);
6226 /* Not a suitable memory address. */
6230 /* All the useful information has now been extracted from the
6231 operands into unsorted_regs and unsorted_offsets; additionally,
6232 order[0] has been set to the lowest numbered register in the
6233 list. Sort the registers into order, and check that the memory
6234 offsets are ascending and adjacent. */
6236 for (i
= 1; i
< nops
; i
++)
6240 order
[i
] = order
[i
- 1];
6241 for (j
= 0; j
< nops
; j
++)
6242 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6243 && (order
[i
] == order
[i
- 1]
6244 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6247 /* Have we found a suitable register? if not, one must be used more
6249 if (order
[i
] == order
[i
- 1])
6252 /* Is the memory address adjacent and ascending? */
6253 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6261 for (i
= 0; i
< nops
; i
++)
6262 regs
[i
] = unsorted_regs
[order
[i
]];
6264 *load_offset
= unsorted_offsets
[order
[0]];
6267 if (unsorted_offsets
[order
[0]] == 0)
6268 return 1; /* ldmia */
6270 if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
6271 return 2; /* ldmib */
6273 if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
6274 return 3; /* ldmda */
6276 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6277 return 4; /* ldmdb */
6279 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6280 if the offset isn't small enough. The reason 2 ldrs are faster
6281 is because these ARMs are able to do more than one cache access
6282 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6283 whilst the ARM8 has a double bandwidth cache. This means that
6284 these cores can do both an instruction fetch and a data fetch in
6285 a single cycle, so the trick of calculating the address into a
6286 scratch register (one of the result regs) and then doing a load
6287 multiple actually becomes slower (and no smaller in code size).
6288 That is the transformation
6290 ldr rd1, [rbase + offset]
6291 ldr rd2, [rbase + offset + 4]
6295 add rd1, rbase, offset
6296 ldmia rd1, {rd1, rd2}
6298 produces worse code -- '3 cycles + any stalls on rd2' instead of
6299 '2 cycles + any stalls on rd2'. On ARMs with only one cache
6300 access per cycle, the first sequence could never complete in less
6301 than 6 cycles, whereas the ldm sequence would only take 5 and
6302 would make better use of sequential accesses if not hitting the
6305 We cheat here and test 'arm_ld_sched' which we currently know to
6306 only be true for the ARM8, ARM9 and StrongARM. If this ever
6307 changes, then the test below needs to be reworked. */
6308 if (nops
== 2 && arm_ld_sched
)
6311 /* Can't do it without setting up the offset, only do this if it takes
6312 no more than one insn. */
6313 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
6314 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
6318 emit_ldm_seq (rtx
*operands
, int nops
)
6322 HOST_WIDE_INT offset
;
6326 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6329 strcpy (buf
, "ldm%(ia%)\t");
6333 strcpy (buf
, "ldm%(ib%)\t");
6337 strcpy (buf
, "ldm%(da%)\t");
6341 strcpy (buf
, "ldm%(db%)\t");
6346 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6347 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6350 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6351 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6353 output_asm_insn (buf
, operands
);
6355 strcpy (buf
, "ldm%(ia%)\t");
6362 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6363 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6365 for (i
= 1; i
< nops
; i
++)
6366 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6367 reg_names
[regs
[i
]]);
6369 strcat (buf
, "}\t%@ phole ldm");
6371 output_asm_insn (buf
, operands
);
6376 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
6377 HOST_WIDE_INT
* load_offset
)
6379 int unsorted_regs
[4];
6380 HOST_WIDE_INT unsorted_offsets
[4];
6385 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6386 extended if required. */
6387 gcc_assert (nops
>= 2 && nops
<= 4);
6389 /* Loop over the operands and check that the memory references are
6390 suitable (i.e. immediate offsets from the same base register). At
6391 the same time, extract the target register, and the memory
6393 for (i
= 0; i
< nops
; i
++)
6398 /* Convert a subreg of a mem into the mem itself. */
6399 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6400 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6402 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6404 /* Don't reorder volatile memory references; it doesn't seem worth
6405 looking for the case where the order is ok anyway. */
6406 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6409 offset
= const0_rtx
;
6411 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6412 || (GET_CODE (reg
) == SUBREG
6413 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6414 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6415 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6417 || (GET_CODE (reg
) == SUBREG
6418 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6419 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6424 base_reg
= REGNO (reg
);
6425 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6426 ? REGNO (operands
[i
])
6427 : REGNO (SUBREG_REG (operands
[i
])));
6432 if (base_reg
!= (int) REGNO (reg
))
6433 /* Not addressed from the same base register. */
6436 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6437 ? REGNO (operands
[i
])
6438 : REGNO (SUBREG_REG (operands
[i
])));
6439 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6443 /* If it isn't an integer register, then we can't do this. */
6444 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6447 unsorted_offsets
[i
] = INTVAL (offset
);
6450 /* Not a suitable memory address. */
6454 /* All the useful information has now been extracted from the
6455 operands into unsorted_regs and unsorted_offsets; additionally,
6456 order[0] has been set to the lowest numbered register in the
6457 list. Sort the registers into order, and check that the memory
6458 offsets are ascending and adjacent. */
6460 for (i
= 1; i
< nops
; i
++)
6464 order
[i
] = order
[i
- 1];
6465 for (j
= 0; j
< nops
; j
++)
6466 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6467 && (order
[i
] == order
[i
- 1]
6468 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6471 /* Have we found a suitable register? if not, one must be used more
6473 if (order
[i
] == order
[i
- 1])
6476 /* Is the memory address adjacent and ascending? */
6477 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6485 for (i
= 0; i
< nops
; i
++)
6486 regs
[i
] = unsorted_regs
[order
[i
]];
6488 *load_offset
= unsorted_offsets
[order
[0]];
6491 if (unsorted_offsets
[order
[0]] == 0)
6492 return 1; /* stmia */
6494 if (unsorted_offsets
[order
[0]] == 4)
6495 return 2; /* stmib */
6497 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6498 return 3; /* stmda */
6500 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6501 return 4; /* stmdb */
6507 emit_stm_seq (rtx
*operands
, int nops
)
6511 HOST_WIDE_INT offset
;
6515 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6518 strcpy (buf
, "stm%(ia%)\t");
6522 strcpy (buf
, "stm%(ib%)\t");
6526 strcpy (buf
, "stm%(da%)\t");
6530 strcpy (buf
, "stm%(db%)\t");
6537 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6538 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6540 for (i
= 1; i
< nops
; i
++)
6541 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6542 reg_names
[regs
[i
]]);
6544 strcat (buf
, "}\t%@ phole stm");
6546 output_asm_insn (buf
, operands
);
6550 /* Routines for use in generating RTL. */
6553 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6554 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6556 HOST_WIDE_INT offset
= *offsetp
;
6559 int sign
= up
? 1 : -1;
6562 /* XScale has load-store double instructions, but they have stricter
6563 alignment requirements than load-store multiple, so we cannot
6566 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6567 the pipeline until completion.
6575 An ldr instruction takes 1-3 cycles, but does not block the
6584 Best case ldr will always win. However, the more ldr instructions
6585 we issue, the less likely we are to be able to schedule them well.
6586 Using ldr instructions also increases code size.
6588 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6589 for counts of 3 or 4 regs. */
6590 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6596 for (i
= 0; i
< count
; i
++)
6598 addr
= plus_constant (from
, i
* 4 * sign
);
6599 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6600 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6606 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6616 result
= gen_rtx_PARALLEL (VOIDmode
,
6617 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6620 XVECEXP (result
, 0, 0)
6621 = gen_rtx_SET (VOIDmode
, from
, plus_constant (from
, count
* 4 * sign
));
6626 for (j
= 0; i
< count
; i
++, j
++)
6628 addr
= plus_constant (from
, j
* 4 * sign
);
6629 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6630 XVECEXP (result
, 0, i
)
6631 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6642 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6643 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6645 HOST_WIDE_INT offset
= *offsetp
;
6648 int sign
= up
? 1 : -1;
6651 /* See arm_gen_load_multiple for discussion of
6652 the pros/cons of ldm/stm usage for XScale. */
6653 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6659 for (i
= 0; i
< count
; i
++)
6661 addr
= plus_constant (to
, i
* 4 * sign
);
6662 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6663 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6669 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6679 result
= gen_rtx_PARALLEL (VOIDmode
,
6680 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6683 XVECEXP (result
, 0, 0)
6684 = gen_rtx_SET (VOIDmode
, to
,
6685 plus_constant (to
, count
* 4 * sign
));
6690 for (j
= 0; i
< count
; i
++, j
++)
6692 addr
= plus_constant (to
, j
* 4 * sign
);
6693 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6694 XVECEXP (result
, 0, i
)
6695 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6706 arm_gen_movmemqi (rtx
*operands
)
6708 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6709 HOST_WIDE_INT srcoffset
, dstoffset
;
6711 rtx src
, dst
, srcbase
, dstbase
;
6712 rtx part_bytes_reg
= NULL
;
6715 if (GET_CODE (operands
[2]) != CONST_INT
6716 || GET_CODE (operands
[3]) != CONST_INT
6717 || INTVAL (operands
[2]) > 64
6718 || INTVAL (operands
[3]) & 3)
6721 dstbase
= operands
[0];
6722 srcbase
= operands
[1];
6724 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6725 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6727 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6728 out_words_to_go
= INTVAL (operands
[2]) / 4;
6729 last_bytes
= INTVAL (operands
[2]) & 3;
6730 dstoffset
= srcoffset
= 0;
6732 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6733 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6735 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6737 if (in_words_to_go
> 4)
6738 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6739 srcbase
, &srcoffset
));
6741 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6742 FALSE
, srcbase
, &srcoffset
));
6744 if (out_words_to_go
)
6746 if (out_words_to_go
> 4)
6747 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6748 dstbase
, &dstoffset
));
6749 else if (out_words_to_go
!= 1)
6750 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6754 dstbase
, &dstoffset
));
6757 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6758 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6759 if (last_bytes
!= 0)
6761 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6767 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6768 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6771 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6772 if (out_words_to_go
)
6776 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6777 sreg
= copy_to_reg (mem
);
6779 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6780 emit_move_insn (mem
, sreg
);
6783 gcc_assert (!in_words_to_go
); /* Sanity check */
6788 gcc_assert (in_words_to_go
> 0);
6790 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6791 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6794 gcc_assert (!last_bytes
|| part_bytes_reg
);
6796 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6798 rtx tmp
= gen_reg_rtx (SImode
);
6800 /* The bytes we want are in the top end of the word. */
6801 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6802 GEN_INT (8 * (4 - last_bytes
))));
6803 part_bytes_reg
= tmp
;
6807 mem
= adjust_automodify_address (dstbase
, QImode
,
6808 plus_constant (dst
, last_bytes
- 1),
6809 dstoffset
+ last_bytes
- 1);
6810 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6814 tmp
= gen_reg_rtx (SImode
);
6815 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6816 part_bytes_reg
= tmp
;
6825 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6826 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6830 rtx tmp
= gen_reg_rtx (SImode
);
6831 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6832 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6833 part_bytes_reg
= tmp
;
6840 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6841 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6848 /* Select a dominance comparison mode if possible for a test of the general
6849 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6850 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6851 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6852 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6853 In all cases OP will be either EQ or NE, but we don't need to know which
6854 here. If we are unable to support a dominance comparison we return
6855 CC mode. This will then fail to match for the RTL expressions that
6856 generate this call. */
6858 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6860 enum rtx_code cond1
, cond2
;
6863 /* Currently we will probably get the wrong result if the individual
6864 comparisons are not simple. This also ensures that it is safe to
6865 reverse a comparison if necessary. */
6866 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6868 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6872 /* The if_then_else variant of this tests the second condition if the
6873 first passes, but is true if the first fails. Reverse the first
6874 condition to get a true "inclusive-or" expression. */
6875 if (cond_or
== DOM_CC_NX_OR_Y
)
6876 cond1
= reverse_condition (cond1
);
6878 /* If the comparisons are not equal, and one doesn't dominate the other,
6879 then we can't do this. */
6881 && !comparison_dominates_p (cond1
, cond2
)
6882 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6887 enum rtx_code temp
= cond1
;
6895 if (cond_or
== DOM_CC_X_AND_Y
)
6900 case EQ
: return CC_DEQmode
;
6901 case LE
: return CC_DLEmode
;
6902 case LEU
: return CC_DLEUmode
;
6903 case GE
: return CC_DGEmode
;
6904 case GEU
: return CC_DGEUmode
;
6905 default: gcc_unreachable ();
6909 if (cond_or
== DOM_CC_X_AND_Y
)
6925 if (cond_or
== DOM_CC_X_AND_Y
)
6941 if (cond_or
== DOM_CC_X_AND_Y
)
6957 if (cond_or
== DOM_CC_X_AND_Y
)
6972 /* The remaining cases only occur when both comparisons are the
6975 gcc_assert (cond1
== cond2
);
6979 gcc_assert (cond1
== cond2
);
6983 gcc_assert (cond1
== cond2
);
6987 gcc_assert (cond1
== cond2
);
6991 gcc_assert (cond1
== cond2
);
7000 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
7002 /* All floating point compares return CCFP if it is an equality
7003 comparison, and CCFPE otherwise. */
7004 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
7024 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
7033 /* A compare with a shifted operand. Because of canonicalization, the
7034 comparison will have to be swapped when we emit the assembler. */
7035 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
7036 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
7037 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
7038 || GET_CODE (x
) == ROTATERT
))
7041 /* This operation is performed swapped, but since we only rely on the Z
7042 flag we don't need an additional mode. */
7043 if (GET_MODE (y
) == SImode
&& REG_P (y
)
7044 && GET_CODE (x
) == NEG
7045 && (op
== EQ
|| op
== NE
))
7048 /* This is a special case that is used by combine to allow a
7049 comparison of a shifted byte load to be split into a zero-extend
7050 followed by a comparison of the shifted integer (only valid for
7051 equalities and unsigned inequalities). */
7052 if (GET_MODE (x
) == SImode
7053 && GET_CODE (x
) == ASHIFT
7054 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
7055 && GET_CODE (XEXP (x
, 0)) == SUBREG
7056 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
7057 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
7058 && (op
== EQ
|| op
== NE
7059 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
7060 && GET_CODE (y
) == CONST_INT
)
7063 /* A construct for a conditional compare, if the false arm contains
7064 0, then both conditions must be true, otherwise either condition
7065 must be true. Not all conditions are possible, so CCmode is
7066 returned if it can't be done. */
7067 if (GET_CODE (x
) == IF_THEN_ELSE
7068 && (XEXP (x
, 2) == const0_rtx
7069 || XEXP (x
, 2) == const1_rtx
)
7070 && COMPARISON_P (XEXP (x
, 0))
7071 && COMPARISON_P (XEXP (x
, 1)))
7072 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
7073 INTVAL (XEXP (x
, 2)));
7075 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7076 if (GET_CODE (x
) == AND
7077 && COMPARISON_P (XEXP (x
, 0))
7078 && COMPARISON_P (XEXP (x
, 1)))
7079 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
7082 if (GET_CODE (x
) == IOR
7083 && COMPARISON_P (XEXP (x
, 0))
7084 && COMPARISON_P (XEXP (x
, 1)))
7085 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
7088 /* An operation (on Thumb) where we want to test for a single bit.
7089 This is done by shifting that bit up into the top bit of a
7090 scratch register; we can then branch on the sign bit. */
7092 && GET_MODE (x
) == SImode
7093 && (op
== EQ
|| op
== NE
)
7094 && GET_CODE (x
) == ZERO_EXTRACT
7095 && XEXP (x
, 1) == const1_rtx
)
7098 /* An operation that sets the condition codes as a side-effect, the
7099 V flag is not set correctly, so we can only use comparisons where
7100 this doesn't matter. (For LT and GE we can use "mi" and "pl"
7102 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
7103 if (GET_MODE (x
) == SImode
7105 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
7106 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
7107 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
7108 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
7109 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
7110 || GET_CODE (x
) == LSHIFTRT
7111 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
7112 || GET_CODE (x
) == ROTATERT
7113 || (TARGET_32BIT
&& GET_CODE (x
) == ZERO_EXTRACT
)))
7116 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
7119 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
7120 && GET_CODE (x
) == PLUS
7121 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
7127 /* X and Y are two things to compare using CODE. Emit the compare insn and
7128 return the rtx for register 0 in the proper mode. FP means this is a
7129 floating point compare: I don't think that it is needed on the arm. */
7131 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
7133 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
7134 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
7136 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
7141 /* Generate a sequence of insns that will generate the correct return
7142 address mask depending on the physical architecture that the program
7145 arm_gen_return_addr_mask (void)
7147 rtx reg
= gen_reg_rtx (Pmode
);
7149 emit_insn (gen_return_addr_mask (reg
));
7154 arm_reload_in_hi (rtx
*operands
)
7156 rtx ref
= operands
[1];
7158 HOST_WIDE_INT offset
= 0;
7160 if (GET_CODE (ref
) == SUBREG
)
7162 offset
= SUBREG_BYTE (ref
);
7163 ref
= SUBREG_REG (ref
);
7166 if (GET_CODE (ref
) == REG
)
7168 /* We have a pseudo which has been spilt onto the stack; there
7169 are two cases here: the first where there is a simple
7170 stack-slot replacement and a second where the stack-slot is
7171 out of range, or is used as a subreg. */
7172 if (reg_equiv_mem
[REGNO (ref
)])
7174 ref
= reg_equiv_mem
[REGNO (ref
)];
7175 base
= find_replacement (&XEXP (ref
, 0));
7178 /* The slot is out of range, or was dressed up in a SUBREG. */
7179 base
= reg_equiv_address
[REGNO (ref
)];
7182 base
= find_replacement (&XEXP (ref
, 0));
7184 /* Handle the case where the address is too complex to be offset by 1. */
7185 if (GET_CODE (base
) == MINUS
7186 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
7188 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7190 emit_set_insn (base_plus
, base
);
7193 else if (GET_CODE (base
) == PLUS
)
7195 /* The addend must be CONST_INT, or we would have dealt with it above. */
7196 HOST_WIDE_INT hi
, lo
;
7198 offset
+= INTVAL (XEXP (base
, 1));
7199 base
= XEXP (base
, 0);
7201 /* Rework the address into a legal sequence of insns. */
7202 /* Valid range for lo is -4095 -> 4095 */
7205 : -((-offset
) & 0xfff));
7207 /* Corner case, if lo is the max offset then we would be out of range
7208 once we have added the additional 1 below, so bump the msb into the
7209 pre-loading insn(s). */
7213 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
7214 ^ (HOST_WIDE_INT
) 0x80000000)
7215 - (HOST_WIDE_INT
) 0x80000000);
7217 gcc_assert (hi
+ lo
== offset
);
7221 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7223 /* Get the base address; addsi3 knows how to handle constants
7224 that require more than one insn. */
7225 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7231 /* Operands[2] may overlap operands[0] (though it won't overlap
7232 operands[1]), that's why we asked for a DImode reg -- so we can
7233 use the bit that does not overlap. */
7234 if (REGNO (operands
[2]) == REGNO (operands
[0]))
7235 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7237 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
7239 emit_insn (gen_zero_extendqisi2 (scratch
,
7240 gen_rtx_MEM (QImode
,
7241 plus_constant (base
,
7243 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
7244 gen_rtx_MEM (QImode
,
7245 plus_constant (base
,
7247 if (!BYTES_BIG_ENDIAN
)
7248 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
7249 gen_rtx_IOR (SImode
,
7252 gen_rtx_SUBREG (SImode
, operands
[0], 0),
7256 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
7257 gen_rtx_IOR (SImode
,
7258 gen_rtx_ASHIFT (SImode
, scratch
,
7260 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
7263 /* Handle storing a half-word to memory during reload by synthesizing as two
7264 byte stores. Take care not to clobber the input values until after we
7265 have moved them somewhere safe. This code assumes that if the DImode
7266 scratch in operands[2] overlaps either the input value or output address
7267 in some way, then that value must die in this insn (we absolutely need
7268 two scratch registers for some corner cases). */
7270 arm_reload_out_hi (rtx
*operands
)
7272 rtx ref
= operands
[0];
7273 rtx outval
= operands
[1];
7275 HOST_WIDE_INT offset
= 0;
7277 if (GET_CODE (ref
) == SUBREG
)
7279 offset
= SUBREG_BYTE (ref
);
7280 ref
= SUBREG_REG (ref
);
7283 if (GET_CODE (ref
) == REG
)
7285 /* We have a pseudo which has been spilt onto the stack; there
7286 are two cases here: the first where there is a simple
7287 stack-slot replacement and a second where the stack-slot is
7288 out of range, or is used as a subreg. */
7289 if (reg_equiv_mem
[REGNO (ref
)])
7291 ref
= reg_equiv_mem
[REGNO (ref
)];
7292 base
= find_replacement (&XEXP (ref
, 0));
7295 /* The slot is out of range, or was dressed up in a SUBREG. */
7296 base
= reg_equiv_address
[REGNO (ref
)];
7299 base
= find_replacement (&XEXP (ref
, 0));
7301 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
7303 /* Handle the case where the address is too complex to be offset by 1. */
7304 if (GET_CODE (base
) == MINUS
7305 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
7307 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7309 /* Be careful not to destroy OUTVAL. */
7310 if (reg_overlap_mentioned_p (base_plus
, outval
))
7312 /* Updating base_plus might destroy outval, see if we can
7313 swap the scratch and base_plus. */
7314 if (!reg_overlap_mentioned_p (scratch
, outval
))
7317 scratch
= base_plus
;
7322 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7324 /* Be conservative and copy OUTVAL into the scratch now,
7325 this should only be necessary if outval is a subreg
7326 of something larger than a word. */
7327 /* XXX Might this clobber base? I can't see how it can,
7328 since scratch is known to overlap with OUTVAL, and
7329 must be wider than a word. */
7330 emit_insn (gen_movhi (scratch_hi
, outval
));
7331 outval
= scratch_hi
;
7335 emit_set_insn (base_plus
, base
);
7338 else if (GET_CODE (base
) == PLUS
)
7340 /* The addend must be CONST_INT, or we would have dealt with it above. */
7341 HOST_WIDE_INT hi
, lo
;
7343 offset
+= INTVAL (XEXP (base
, 1));
7344 base
= XEXP (base
, 0);
7346 /* Rework the address into a legal sequence of insns. */
7347 /* Valid range for lo is -4095 -> 4095 */
7350 : -((-offset
) & 0xfff));
7352 /* Corner case, if lo is the max offset then we would be out of range
7353 once we have added the additional 1 below, so bump the msb into the
7354 pre-loading insn(s). */
7358 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
7359 ^ (HOST_WIDE_INT
) 0x80000000)
7360 - (HOST_WIDE_INT
) 0x80000000);
7362 gcc_assert (hi
+ lo
== offset
);
7366 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7368 /* Be careful not to destroy OUTVAL. */
7369 if (reg_overlap_mentioned_p (base_plus
, outval
))
7371 /* Updating base_plus might destroy outval, see if we
7372 can swap the scratch and base_plus. */
7373 if (!reg_overlap_mentioned_p (scratch
, outval
))
7376 scratch
= base_plus
;
7381 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7383 /* Be conservative and copy outval into scratch now,
7384 this should only be necessary if outval is a
7385 subreg of something larger than a word. */
7386 /* XXX Might this clobber base? I can't see how it
7387 can, since scratch is known to overlap with
7389 emit_insn (gen_movhi (scratch_hi
, outval
));
7390 outval
= scratch_hi
;
7394 /* Get the base address; addsi3 knows how to handle constants
7395 that require more than one insn. */
7396 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7402 if (BYTES_BIG_ENDIAN
)
7404 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7405 plus_constant (base
, offset
+ 1)),
7406 gen_lowpart (QImode
, outval
)));
7407 emit_insn (gen_lshrsi3 (scratch
,
7408 gen_rtx_SUBREG (SImode
, outval
, 0),
7410 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7411 gen_lowpart (QImode
, scratch
)));
7415 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7416 gen_lowpart (QImode
, outval
)));
7417 emit_insn (gen_lshrsi3 (scratch
,
7418 gen_rtx_SUBREG (SImode
, outval
, 0),
7420 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7421 plus_constant (base
, offset
+ 1)),
7422 gen_lowpart (QImode
, scratch
)));
7426 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7427 (padded to the size of a word) should be passed in a register. */
7430 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7432 if (TARGET_AAPCS_BASED
)
7433 return must_pass_in_stack_var_size (mode
, type
);
7435 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7439 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7440 Return true if an argument passed on the stack should be padded upwards,
7441 i.e. if the least-significant byte has useful data.
7442 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7443 aggregate types are placed in the lowest memory address. */
7446 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7448 if (!TARGET_AAPCS_BASED
)
7449 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7451 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7458 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7459 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7460 byte of the register has useful data, and return the opposite if the
7461 most significant byte does.
7462 For AAPCS, small aggregates and small complex types are always padded
7466 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7467 tree type
, int first ATTRIBUTE_UNUSED
)
7469 if (TARGET_AAPCS_BASED
7471 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7472 && int_size_in_bytes (type
) <= 4)
7475 /* Otherwise, use default padding. */
7476 return !BYTES_BIG_ENDIAN
;
7480 /* Print a symbolic form of X to the debug file, F. */
7482 arm_print_value (FILE *f
, rtx x
)
7484 switch (GET_CODE (x
))
7487 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7491 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7499 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7501 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7502 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7510 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7514 fprintf (f
, "`%s'", XSTR (x
, 0));
7518 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7522 arm_print_value (f
, XEXP (x
, 0));
7526 arm_print_value (f
, XEXP (x
, 0));
7528 arm_print_value (f
, XEXP (x
, 1));
7536 fprintf (f
, "????");
7541 /* Routines for manipulation of the constant pool. */
7543 /* Arm instructions cannot load a large constant directly into a
7544 register; they have to come from a pc relative load. The constant
7545 must therefore be placed in the addressable range of the pc
7546 relative load. Depending on the precise pc relative load
7547 instruction the range is somewhere between 256 bytes and 4k. This
7548 means that we often have to dump a constant inside a function, and
7549 generate code to branch around it.
7551 It is important to minimize this, since the branches will slow
7552 things down and make the code larger.
7554 Normally we can hide the table after an existing unconditional
7555 branch so that there is no interruption of the flow, but in the
7556 worst case the code looks like this:
7574 We fix this by performing a scan after scheduling, which notices
7575 which instructions need to have their operands fetched from the
7576 constant table and builds the table.
7578 The algorithm starts by building a table of all the constants that
7579 need fixing up and all the natural barriers in the function (places
7580 where a constant table can be dropped without breaking the flow).
7581 For each fixup we note how far the pc-relative replacement will be
7582 able to reach and the offset of the instruction into the function.
7584 Having built the table we then group the fixes together to form
7585 tables that are as large as possible (subject to addressing
7586 constraints) and emit each table of constants after the last
7587 barrier that is within range of all the instructions in the group.
7588 If a group does not contain a barrier, then we forcibly create one
7589 by inserting a jump instruction into the flow. Once the table has
7590 been inserted, the insns are then modified to reference the
7591 relevant entry in the pool.
7593 Possible enhancements to the algorithm (not implemented) are:
7595 1) For some processors and object formats, there may be benefit in
7596 aligning the pools to the start of cache lines; this alignment
7597 would need to be taken into account when calculating addressability
7600 /* These typedefs are located at the start of this file, so that
7601 they can be used in the prototypes there. This comment is to
7602 remind readers of that fact so that the following structures
7603 can be understood more easily.
7605 typedef struct minipool_node Mnode;
7606 typedef struct minipool_fixup Mfix; */
7608 struct minipool_node
7610 /* Doubly linked chain of entries. */
7613 /* The maximum offset into the code that this entry can be placed. While
7614 pushing fixes for forward references, all entries are sorted in order
7615 of increasing max_address. */
7616 HOST_WIDE_INT max_address
;
7617 /* Similarly for an entry inserted for a backwards ref. */
7618 HOST_WIDE_INT min_address
;
7619 /* The number of fixes referencing this entry. This can become zero
7620 if we "unpush" an entry. In this case we ignore the entry when we
7621 come to emit the code. */
7623 /* The offset from the start of the minipool. */
7624 HOST_WIDE_INT offset
;
7625 /* The value in table. */
7627 /* The mode of value. */
7628 enum machine_mode mode
;
7629 /* The size of the value. With iWMMXt enabled
7630 sizes > 4 also imply an alignment of 8-bytes. */
7634 struct minipool_fixup
7638 HOST_WIDE_INT address
;
7640 enum machine_mode mode
;
7644 HOST_WIDE_INT forwards
;
7645 HOST_WIDE_INT backwards
;
7648 /* Fixes less than a word need padding out to a word boundary. */
7649 #define MINIPOOL_FIX_SIZE(mode) \
7650 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7652 static Mnode
* minipool_vector_head
;
7653 static Mnode
* minipool_vector_tail
;
7654 static rtx minipool_vector_label
;
7655 static int minipool_pad
;
7657 /* The linked list of all minipool fixes required for this function. */
7658 Mfix
* minipool_fix_head
;
7659 Mfix
* minipool_fix_tail
;
7660 /* The fix entry for the current minipool, once it has been placed. */
7661 Mfix
* minipool_barrier
;
7663 /* Determines if INSN is the start of a jump table. Returns the end
7664 of the TABLE or NULL_RTX. */
7666 is_jump_table (rtx insn
)
7670 if (GET_CODE (insn
) == JUMP_INSN
7671 && JUMP_LABEL (insn
) != NULL
7672 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7673 == next_real_insn (insn
))
7675 && GET_CODE (table
) == JUMP_INSN
7676 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7677 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7683 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7684 #define JUMP_TABLES_IN_TEXT_SECTION 0
7687 static HOST_WIDE_INT
7688 get_jump_table_size (rtx insn
)
7690 /* ADDR_VECs only take room if read-only data does into the text
7692 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
7694 rtx body
= PATTERN (insn
);
7695 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7697 HOST_WIDE_INT modesize
;
7699 modesize
= GET_MODE_SIZE (GET_MODE (body
));
7700 size
= modesize
* XVECLEN (body
, elt
);
7704 /* Round up size of TBB table to a hafword boundary. */
7705 size
= (size
+ 1) & ~(HOST_WIDE_INT
)1;
7708 /* No padding neccessary for TBH. */
7711 /* Add two bytes for alignment on Thumb. */
7724 /* Move a minipool fix MP from its current location to before MAX_MP.
7725 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7726 constraints may need updating. */
7728 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7729 HOST_WIDE_INT max_address
)
7731 /* The code below assumes these are different. */
7732 gcc_assert (mp
!= max_mp
);
7736 if (max_address
< mp
->max_address
)
7737 mp
->max_address
= max_address
;
7741 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7742 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7744 mp
->max_address
= max_address
;
7746 /* Unlink MP from its current position. Since max_mp is non-null,
7747 mp->prev must be non-null. */
7748 mp
->prev
->next
= mp
->next
;
7749 if (mp
->next
!= NULL
)
7750 mp
->next
->prev
= mp
->prev
;
7752 minipool_vector_tail
= mp
->prev
;
7754 /* Re-insert it before MAX_MP. */
7756 mp
->prev
= max_mp
->prev
;
7759 if (mp
->prev
!= NULL
)
7760 mp
->prev
->next
= mp
;
7762 minipool_vector_head
= mp
;
7765 /* Save the new entry. */
7768 /* Scan over the preceding entries and adjust their addresses as
7770 while (mp
->prev
!= NULL
7771 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7773 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7780 /* Add a constant to the minipool for a forward reference. Returns the
7781 node added or NULL if the constant will not fit in this pool. */
7783 add_minipool_forward_ref (Mfix
*fix
)
7785 /* If set, max_mp is the first pool_entry that has a lower
7786 constraint than the one we are trying to add. */
7787 Mnode
* max_mp
= NULL
;
7788 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
7791 /* If the minipool starts before the end of FIX->INSN then this FIX
7792 can not be placed into the current pool. Furthermore, adding the
7793 new constant pool entry may cause the pool to start FIX_SIZE bytes
7795 if (minipool_vector_head
&&
7796 (fix
->address
+ get_attr_length (fix
->insn
)
7797 >= minipool_vector_head
->max_address
- fix
->fix_size
))
7800 /* Scan the pool to see if a constant with the same value has
7801 already been added. While we are doing this, also note the
7802 location where we must insert the constant if it doesn't already
7804 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7806 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7807 && fix
->mode
== mp
->mode
7808 && (GET_CODE (fix
->value
) != CODE_LABEL
7809 || (CODE_LABEL_NUMBER (fix
->value
)
7810 == CODE_LABEL_NUMBER (mp
->value
)))
7811 && rtx_equal_p (fix
->value
, mp
->value
))
7813 /* More than one fix references this entry. */
7815 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7818 /* Note the insertion point if necessary. */
7820 && mp
->max_address
> max_address
)
7823 /* If we are inserting an 8-bytes aligned quantity and
7824 we have not already found an insertion point, then
7825 make sure that all such 8-byte aligned quantities are
7826 placed at the start of the pool. */
7827 if (ARM_DOUBLEWORD_ALIGN
7829 && fix
->fix_size
== 8
7830 && mp
->fix_size
!= 8)
7833 max_address
= mp
->max_address
;
7837 /* The value is not currently in the minipool, so we need to create
7838 a new entry for it. If MAX_MP is NULL, the entry will be put on
7839 the end of the list since the placement is less constrained than
7840 any existing entry. Otherwise, we insert the new fix before
7841 MAX_MP and, if necessary, adjust the constraints on the other
7844 mp
->fix_size
= fix
->fix_size
;
7845 mp
->mode
= fix
->mode
;
7846 mp
->value
= fix
->value
;
7848 /* Not yet required for a backwards ref. */
7849 mp
->min_address
= -65536;
7853 mp
->max_address
= max_address
;
7855 mp
->prev
= minipool_vector_tail
;
7857 if (mp
->prev
== NULL
)
7859 minipool_vector_head
= mp
;
7860 minipool_vector_label
= gen_label_rtx ();
7863 mp
->prev
->next
= mp
;
7865 minipool_vector_tail
= mp
;
7869 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7870 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7872 mp
->max_address
= max_address
;
7875 mp
->prev
= max_mp
->prev
;
7877 if (mp
->prev
!= NULL
)
7878 mp
->prev
->next
= mp
;
7880 minipool_vector_head
= mp
;
7883 /* Save the new entry. */
7886 /* Scan over the preceding entries and adjust their addresses as
7888 while (mp
->prev
!= NULL
7889 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7891 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7899 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7900 HOST_WIDE_INT min_address
)
7902 HOST_WIDE_INT offset
;
7904 /* The code below assumes these are different. */
7905 gcc_assert (mp
!= min_mp
);
7909 if (min_address
> mp
->min_address
)
7910 mp
->min_address
= min_address
;
7914 /* We will adjust this below if it is too loose. */
7915 mp
->min_address
= min_address
;
7917 /* Unlink MP from its current position. Since min_mp is non-null,
7918 mp->next must be non-null. */
7919 mp
->next
->prev
= mp
->prev
;
7920 if (mp
->prev
!= NULL
)
7921 mp
->prev
->next
= mp
->next
;
7923 minipool_vector_head
= mp
->next
;
7925 /* Reinsert it after MIN_MP. */
7927 mp
->next
= min_mp
->next
;
7929 if (mp
->next
!= NULL
)
7930 mp
->next
->prev
= mp
;
7932 minipool_vector_tail
= mp
;
7938 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7940 mp
->offset
= offset
;
7941 if (mp
->refcount
> 0)
7942 offset
+= mp
->fix_size
;
7944 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7945 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7951 /* Add a constant to the minipool for a backward reference. Returns the
7952 node added or NULL if the constant will not fit in this pool.
7954 Note that the code for insertion for a backwards reference can be
7955 somewhat confusing because the calculated offsets for each fix do
7956 not take into account the size of the pool (which is still under
7959 add_minipool_backward_ref (Mfix
*fix
)
7961 /* If set, min_mp is the last pool_entry that has a lower constraint
7962 than the one we are trying to add. */
7963 Mnode
*min_mp
= NULL
;
7964 /* This can be negative, since it is only a constraint. */
7965 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7968 /* If we can't reach the current pool from this insn, or if we can't
7969 insert this entry at the end of the pool without pushing other
7970 fixes out of range, then we don't try. This ensures that we
7971 can't fail later on. */
7972 if (min_address
>= minipool_barrier
->address
7973 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7974 >= minipool_barrier
->address
))
7977 /* Scan the pool to see if a constant with the same value has
7978 already been added. While we are doing this, also note the
7979 location where we must insert the constant if it doesn't already
7981 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7983 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7984 && fix
->mode
== mp
->mode
7985 && (GET_CODE (fix
->value
) != CODE_LABEL
7986 || (CODE_LABEL_NUMBER (fix
->value
)
7987 == CODE_LABEL_NUMBER (mp
->value
)))
7988 && rtx_equal_p (fix
->value
, mp
->value
)
7989 /* Check that there is enough slack to move this entry to the
7990 end of the table (this is conservative). */
7992 > (minipool_barrier
->address
7993 + minipool_vector_tail
->offset
7994 + minipool_vector_tail
->fix_size
)))
7997 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
8001 mp
->min_address
+= fix
->fix_size
;
8004 /* Note the insertion point if necessary. */
8005 if (mp
->min_address
< min_address
)
8007 /* For now, we do not allow the insertion of 8-byte alignment
8008 requiring nodes anywhere but at the start of the pool. */
8009 if (ARM_DOUBLEWORD_ALIGN
8010 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
8015 else if (mp
->max_address
8016 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
8018 /* Inserting before this entry would push the fix beyond
8019 its maximum address (which can happen if we have
8020 re-located a forwards fix); force the new fix to come
8023 min_address
= mp
->min_address
+ fix
->fix_size
;
8025 /* If we are inserting an 8-bytes aligned quantity and
8026 we have not already found an insertion point, then
8027 make sure that all such 8-byte aligned quantities are
8028 placed at the start of the pool. */
8029 else if (ARM_DOUBLEWORD_ALIGN
8031 && fix
->fix_size
== 8
8032 && mp
->fix_size
< 8)
8035 min_address
= mp
->min_address
+ fix
->fix_size
;
8040 /* We need to create a new entry. */
8042 mp
->fix_size
= fix
->fix_size
;
8043 mp
->mode
= fix
->mode
;
8044 mp
->value
= fix
->value
;
8046 mp
->max_address
= minipool_barrier
->address
+ 65536;
8048 mp
->min_address
= min_address
;
8053 mp
->next
= minipool_vector_head
;
8055 if (mp
->next
== NULL
)
8057 minipool_vector_tail
= mp
;
8058 minipool_vector_label
= gen_label_rtx ();
8061 mp
->next
->prev
= mp
;
8063 minipool_vector_head
= mp
;
8067 mp
->next
= min_mp
->next
;
8071 if (mp
->next
!= NULL
)
8072 mp
->next
->prev
= mp
;
8074 minipool_vector_tail
= mp
;
8077 /* Save the new entry. */
8085 /* Scan over the following entries and adjust their offsets. */
8086 while (mp
->next
!= NULL
)
8088 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
8089 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
8092 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
8094 mp
->next
->offset
= mp
->offset
;
8103 assign_minipool_offsets (Mfix
*barrier
)
8105 HOST_WIDE_INT offset
= 0;
8108 minipool_barrier
= barrier
;
8110 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
8112 mp
->offset
= offset
;
8114 if (mp
->refcount
> 0)
8115 offset
+= mp
->fix_size
;
8119 /* Output the literal table */
8121 dump_minipool (rtx scan
)
8127 if (ARM_DOUBLEWORD_ALIGN
)
8128 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
8129 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
8137 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8138 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
8140 scan
= emit_label_after (gen_label_rtx (), scan
);
8141 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
8142 scan
= emit_label_after (minipool_vector_label
, scan
);
8144 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
8146 if (mp
->refcount
> 0)
8151 ";; Offset %u, min %ld, max %ld ",
8152 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
8153 (unsigned long) mp
->max_address
);
8154 arm_print_value (dump_file
, mp
->value
);
8155 fputc ('\n', dump_file
);
8158 switch (mp
->fix_size
)
8160 #ifdef HAVE_consttable_1
8162 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
8166 #ifdef HAVE_consttable_2
8168 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
8172 #ifdef HAVE_consttable_4
8174 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
8178 #ifdef HAVE_consttable_8
8180 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
8193 minipool_vector_head
= minipool_vector_tail
= NULL
;
8194 scan
= emit_insn_after (gen_consttable_end (), scan
);
8195 scan
= emit_barrier_after (scan
);
8198 /* Return the cost of forcibly inserting a barrier after INSN. */
8200 arm_barrier_cost (rtx insn
)
8202 /* Basing the location of the pool on the loop depth is preferable,
8203 but at the moment, the basic block information seems to be
8204 corrupt by this stage of the compilation. */
8206 rtx next
= next_nonnote_insn (insn
);
8208 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
8211 switch (GET_CODE (insn
))
8214 /* It will always be better to place the table before the label, rather
8223 return base_cost
- 10;
8226 return base_cost
+ 10;
8230 /* Find the best place in the insn stream in the range
8231 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8232 Create the barrier by inserting a jump and add a new fix entry for
8235 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
8237 HOST_WIDE_INT count
= 0;
8239 rtx from
= fix
->insn
;
8240 /* The instruction after which we will insert the jump. */
8241 rtx selected
= NULL
;
8243 /* The address at which the jump instruction will be placed. */
8244 HOST_WIDE_INT selected_address
;
8246 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
8247 rtx label
= gen_label_rtx ();
8249 selected_cost
= arm_barrier_cost (from
);
8250 selected_address
= fix
->address
;
8252 while (from
&& count
< max_count
)
8257 /* This code shouldn't have been called if there was a natural barrier
8259 gcc_assert (GET_CODE (from
) != BARRIER
);
8261 /* Count the length of this insn. */
8262 count
+= get_attr_length (from
);
8264 /* If there is a jump table, add its length. */
8265 tmp
= is_jump_table (from
);
8268 count
+= get_jump_table_size (tmp
);
8270 /* Jump tables aren't in a basic block, so base the cost on
8271 the dispatch insn. If we select this location, we will
8272 still put the pool after the table. */
8273 new_cost
= arm_barrier_cost (from
);
8275 if (count
< max_count
8276 && (!selected
|| new_cost
<= selected_cost
))
8279 selected_cost
= new_cost
;
8280 selected_address
= fix
->address
+ count
;
8283 /* Continue after the dispatch table. */
8284 from
= NEXT_INSN (tmp
);
8288 new_cost
= arm_barrier_cost (from
);
8290 if (count
< max_count
8291 && (!selected
|| new_cost
<= selected_cost
))
8294 selected_cost
= new_cost
;
8295 selected_address
= fix
->address
+ count
;
8298 from
= NEXT_INSN (from
);
8301 /* Make sure that we found a place to insert the jump. */
8302 gcc_assert (selected
);
8304 /* Create a new JUMP_INSN that branches around a barrier. */
8305 from
= emit_jump_insn_after (gen_jump (label
), selected
);
8306 JUMP_LABEL (from
) = label
;
8307 barrier
= emit_barrier_after (from
);
8308 emit_label_after (label
, barrier
);
8310 /* Create a minipool barrier entry for the new barrier. */
8311 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
8312 new_fix
->insn
= barrier
;
8313 new_fix
->address
= selected_address
;
8314 new_fix
->next
= fix
->next
;
8315 fix
->next
= new_fix
;
8320 /* Record that there is a natural barrier in the insn stream at
8323 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
8325 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
8328 fix
->address
= address
;
8331 if (minipool_fix_head
!= NULL
)
8332 minipool_fix_tail
->next
= fix
;
8334 minipool_fix_head
= fix
;
8336 minipool_fix_tail
= fix
;
8339 /* Record INSN, which will need fixing up to load a value from the
8340 minipool. ADDRESS is the offset of the insn since the start of the
8341 function; LOC is a pointer to the part of the insn which requires
8342 fixing; VALUE is the constant that must be loaded, which is of type
8345 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
8346 enum machine_mode mode
, rtx value
)
8348 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
8350 #ifdef AOF_ASSEMBLER
8351 /* PIC symbol references need to be converted into offsets into the
8353 /* XXX This shouldn't be done here. */
8354 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
8355 value
= aof_pic_entry (value
);
8356 #endif /* AOF_ASSEMBLER */
8359 fix
->address
= address
;
8362 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
8364 fix
->forwards
= get_attr_pool_range (insn
);
8365 fix
->backwards
= get_attr_neg_pool_range (insn
);
8366 fix
->minipool
= NULL
;
8368 /* If an insn doesn't have a range defined for it, then it isn't
8369 expecting to be reworked by this code. Better to stop now than
8370 to generate duff assembly code. */
8371 gcc_assert (fix
->forwards
|| fix
->backwards
);
8373 /* If an entry requires 8-byte alignment then assume all constant pools
8374 require 4 bytes of padding. Trying to do this later on a per-pool
8375 basis is awkward because existing pool entries have to be modified. */
8376 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
8382 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8383 GET_MODE_NAME (mode
),
8384 INSN_UID (insn
), (unsigned long) address
,
8385 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
8386 arm_print_value (dump_file
, fix
->value
);
8387 fprintf (dump_file
, "\n");
8390 /* Add it to the chain of fixes. */
8393 if (minipool_fix_head
!= NULL
)
8394 minipool_fix_tail
->next
= fix
;
8396 minipool_fix_head
= fix
;
8398 minipool_fix_tail
= fix
;
8401 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8402 Returns the number of insns needed, or 99 if we don't know how to
8405 arm_const_double_inline_cost (rtx val
)
8407 rtx lowpart
, highpart
;
8408 enum machine_mode mode
;
8410 mode
= GET_MODE (val
);
8412 if (mode
== VOIDmode
)
8415 gcc_assert (GET_MODE_SIZE (mode
) == 8);
8417 lowpart
= gen_lowpart (SImode
, val
);
8418 highpart
= gen_highpart_mode (SImode
, mode
, val
);
8420 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
8421 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
8423 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
8424 NULL_RTX
, NULL_RTX
, 0, 0)
8425 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
8426 NULL_RTX
, NULL_RTX
, 0, 0));
8429 /* Return true if it is worthwhile to split a 64-bit constant into two
8430 32-bit operations. This is the case if optimizing for size, or
8431 if we have load delay slots, or if one 32-bit part can be done with
8432 a single data operation. */
8434 arm_const_double_by_parts (rtx val
)
8436 enum machine_mode mode
= GET_MODE (val
);
8439 if (optimize_size
|| arm_ld_sched
)
8442 if (mode
== VOIDmode
)
8445 part
= gen_highpart_mode (SImode
, mode
, val
);
8447 gcc_assert (GET_CODE (part
) == CONST_INT
);
8449 if (const_ok_for_arm (INTVAL (part
))
8450 || const_ok_for_arm (~INTVAL (part
)))
8453 part
= gen_lowpart (SImode
, val
);
8455 gcc_assert (GET_CODE (part
) == CONST_INT
);
8457 if (const_ok_for_arm (INTVAL (part
))
8458 || const_ok_for_arm (~INTVAL (part
)))
8464 /* Scan INSN and note any of its operands that need fixing.
8465 If DO_PUSHES is false we do not actually push any of the fixups
8466 needed. The function returns TRUE if any fixups were needed/pushed.
8467 This is used by arm_memory_load_p() which needs to know about loads
8468 of constants that will be converted into minipool loads. */
8470 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8472 bool result
= false;
8475 extract_insn (insn
);
8477 if (!constrain_operands (1))
8478 fatal_insn_not_found (insn
);
8480 if (recog_data
.n_alternatives
== 0)
8483 /* Fill in recog_op_alt with information about the constraints of
8485 preprocess_constraints ();
8487 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8489 /* Things we need to fix can only occur in inputs. */
8490 if (recog_data
.operand_type
[opno
] != OP_IN
)
8493 /* If this alternative is a memory reference, then any mention
8494 of constants in this alternative is really to fool reload
8495 into allowing us to accept one there. We need to fix them up
8496 now so that we output the right code. */
8497 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8499 rtx op
= recog_data
.operand
[opno
];
8501 if (CONSTANT_P (op
))
8504 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8505 recog_data
.operand_mode
[opno
], op
);
8508 else if (GET_CODE (op
) == MEM
8509 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8510 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8514 rtx cop
= avoid_constant_pool_reference (op
);
8516 /* Casting the address of something to a mode narrower
8517 than a word can cause avoid_constant_pool_reference()
8518 to return the pool reference itself. That's no good to
8519 us here. Lets just hope that we can use the
8520 constant pool value directly. */
8522 cop
= get_pool_constant (XEXP (op
, 0));
8524 push_minipool_fix (insn
, address
,
8525 recog_data
.operand_loc
[opno
],
8526 recog_data
.operand_mode
[opno
], cop
);
8537 /* Gcc puts the pool in the wrong place for ARM, since we can only
8538 load addresses a limited distance around the pc. We do some
8539 special munging to move the constant pool values to the correct
8540 point in the code. */
8545 HOST_WIDE_INT address
= 0;
8548 minipool_fix_head
= minipool_fix_tail
= NULL
;
8550 /* The first insn must always be a note, or the code below won't
8551 scan it properly. */
8552 insn
= get_insns ();
8553 gcc_assert (GET_CODE (insn
) == NOTE
);
8556 /* Scan all the insns and record the operands that will need fixing. */
8557 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8559 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8560 && (arm_cirrus_insn_p (insn
)
8561 || GET_CODE (insn
) == JUMP_INSN
8562 || arm_memory_load_p (insn
)))
8563 cirrus_reorg (insn
);
8565 if (GET_CODE (insn
) == BARRIER
)
8566 push_minipool_barrier (insn
, address
);
8567 else if (INSN_P (insn
))
8571 note_invalid_constants (insn
, address
, true);
8572 address
+= get_attr_length (insn
);
8574 /* If the insn is a vector jump, add the size of the table
8575 and skip the table. */
8576 if ((table
= is_jump_table (insn
)) != NULL
)
8578 address
+= get_jump_table_size (table
);
8584 fix
= minipool_fix_head
;
8586 /* Now scan the fixups and perform the required changes. */
8591 Mfix
* last_added_fix
;
8592 Mfix
* last_barrier
= NULL
;
8595 /* Skip any further barriers before the next fix. */
8596 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8599 /* No more fixes. */
8603 last_added_fix
= NULL
;
8605 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8607 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8609 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8612 last_barrier
= ftmp
;
8614 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8617 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8620 /* If we found a barrier, drop back to that; any fixes that we
8621 could have reached but come after the barrier will now go in
8622 the next mini-pool. */
8623 if (last_barrier
!= NULL
)
8625 /* Reduce the refcount for those fixes that won't go into this
8627 for (fdel
= last_barrier
->next
;
8628 fdel
&& fdel
!= ftmp
;
8631 fdel
->minipool
->refcount
--;
8632 fdel
->minipool
= NULL
;
8635 ftmp
= last_barrier
;
8639 /* ftmp is first fix that we can't fit into this pool and
8640 there no natural barriers that we could use. Insert a
8641 new barrier in the code somewhere between the previous
8642 fix and this one, and arrange to jump around it. */
8643 HOST_WIDE_INT max_address
;
8645 /* The last item on the list of fixes must be a barrier, so
8646 we can never run off the end of the list of fixes without
8647 last_barrier being set. */
8650 max_address
= minipool_vector_head
->max_address
;
8651 /* Check that there isn't another fix that is in range that
8652 we couldn't fit into this pool because the pool was
8653 already too large: we need to put the pool before such an
8654 instruction. The pool itself may come just after the
8655 fix because create_fix_barrier also allows space for a
8656 jump instruction. */
8657 if (ftmp
->address
< max_address
)
8658 max_address
= ftmp
->address
+ 1;
8660 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8663 assign_minipool_offsets (last_barrier
);
8667 if (GET_CODE (ftmp
->insn
) != BARRIER
8668 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8675 /* Scan over the fixes we have identified for this pool, fixing them
8676 up and adding the constants to the pool itself. */
8677 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8678 this_fix
= this_fix
->next
)
8679 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8682 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8683 minipool_vector_label
),
8684 this_fix
->minipool
->offset
);
8685 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8688 dump_minipool (last_barrier
->insn
);
8692 /* From now on we must synthesize any constants that we can't handle
8693 directly. This can happen if the RTL gets split during final
8694 instruction generation. */
8695 after_arm_reorg
= 1;
8697 /* Free the minipool memory. */
8698 obstack_free (&minipool_obstack
, minipool_startobj
);
8701 /* Routines to output assembly language. */
8703 /* If the rtx is the correct value then return the string of the number.
8704 In this way we can ensure that valid double constants are generated even
8705 when cross compiling. */
8707 fp_immediate_constant (rtx x
)
8712 if (!fp_consts_inited
)
8715 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8716 for (i
= 0; i
< 8; i
++)
8717 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8718 return strings_fp
[i
];
8723 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8725 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8729 if (!fp_consts_inited
)
8732 for (i
= 0; i
< 8; i
++)
8733 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8734 return strings_fp
[i
];
8739 /* Output the operands of a LDM/STM instruction to STREAM.
8740 MASK is the ARM register set mask of which only bits 0-15 are important.
8741 REG is the base register, either the frame pointer or the stack pointer,
8742 INSTR is the possibly suffixed load or store instruction. */
8745 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8749 bool not_first
= FALSE
;
8751 fputc ('\t', stream
);
8752 asm_fprintf (stream
, instr
, reg
);
8753 fputc ('{', stream
);
8755 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8756 if (mask
& (1 << i
))
8759 fprintf (stream
, ", ");
8761 asm_fprintf (stream
, "%r", i
);
8765 fprintf (stream
, "}\n");
8769 /* Output a FLDMD instruction to STREAM.
8770 BASE if the register containing the address.
8771 REG and COUNT specify the register range.
8772 Extra registers may be added to avoid hardware bugs.
8774 We output FLDMD even for ARMv5 VFP implementations. Although
8775 FLDMD is technically not supported until ARMv6, it is believed
8776 that all VFP implementations support its use in this context. */
8779 vfp_output_fldmd (FILE * stream
, unsigned int base
, int reg
, int count
)
8783 /* Workaround ARM10 VFPr1 bug. */
8784 if (count
== 2 && !arm_arch6
)
8791 fputc ('\t', stream
);
8792 asm_fprintf (stream
, "fldmfdd\t%r!, {", base
);
8794 for (i
= reg
; i
< reg
+ count
; i
++)
8797 fputs (", ", stream
);
8798 asm_fprintf (stream
, "d%d", i
);
8800 fputs ("}\n", stream
);
8805 /* Output the assembly for a store multiple. */
8808 vfp_output_fstmd (rtx
* operands
)
8815 strcpy (pattern
, "fstmfdd\t%m0!, {%P1");
8816 p
= strlen (pattern
);
8818 gcc_assert (GET_CODE (operands
[1]) == REG
);
8820 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8821 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8823 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8825 strcpy (&pattern
[p
], "}");
8827 output_asm_insn (pattern
, operands
);
8832 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8833 number of bytes pushed. */
8836 vfp_emit_fstmd (int base_reg
, int count
)
8843 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8844 register pairs are stored by a store multiple insn. We avoid this
8845 by pushing an extra pair. */
8846 if (count
== 2 && !arm_arch6
)
8848 if (base_reg
== LAST_VFP_REGNUM
- 3)
8853 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8854 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8856 reg
= gen_rtx_REG (DFmode
, base_reg
);
8860 = gen_rtx_SET (VOIDmode
,
8861 gen_frame_mem (BLKmode
,
8862 gen_rtx_PRE_DEC (BLKmode
,
8863 stack_pointer_rtx
)),
8864 gen_rtx_UNSPEC (BLKmode
,
8868 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8869 plus_constant (stack_pointer_rtx
, -(count
* 8)));
8870 RTX_FRAME_RELATED_P (tmp
) = 1;
8871 XVECEXP (dwarf
, 0, 0) = tmp
;
8873 tmp
= gen_rtx_SET (VOIDmode
,
8874 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8876 RTX_FRAME_RELATED_P (tmp
) = 1;
8877 XVECEXP (dwarf
, 0, 1) = tmp
;
8879 for (i
= 1; i
< count
; i
++)
8881 reg
= gen_rtx_REG (DFmode
, base_reg
);
8883 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8885 tmp
= gen_rtx_SET (VOIDmode
,
8886 gen_frame_mem (DFmode
,
8887 plus_constant (stack_pointer_rtx
,
8890 RTX_FRAME_RELATED_P (tmp
) = 1;
8891 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8894 par
= emit_insn (par
);
8895 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8897 RTX_FRAME_RELATED_P (par
) = 1;
8903 /* Output a 'call' insn. */
8905 output_call (rtx
*operands
)
8907 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8909 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8910 if (REGNO (operands
[0]) == LR_REGNUM
)
8912 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8913 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8916 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8918 if (TARGET_INTERWORK
|| arm_arch4t
)
8919 output_asm_insn ("bx%?\t%0", operands
);
8921 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8926 /* Output a 'call' insn that is a reference in memory. */
8928 output_call_mem (rtx
*operands
)
8930 if (TARGET_INTERWORK
&& !arm_arch5
)
8932 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8933 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8934 output_asm_insn ("bx%?\t%|ip", operands
);
8936 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8938 /* LR is used in the memory address. We load the address in the
8939 first instruction. It's safe to use IP as the target of the
8940 load since the call will kill it anyway. */
8941 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8943 output_asm_insn ("blx%?\t%|ip", operands
);
8946 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8948 output_asm_insn ("bx%?\t%|ip", operands
);
8950 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8955 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8956 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8963 /* Output a move from arm registers to an fpa registers.
8964 OPERANDS[0] is an fpa register.
8965 OPERANDS[1] is the first registers of an arm register pair. */
8967 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8969 int arm_reg0
= REGNO (operands
[1]);
8972 gcc_assert (arm_reg0
!= IP_REGNUM
);
8974 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8975 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8976 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8978 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
8979 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8984 /* Output a move from an fpa register to arm registers.
8985 OPERANDS[0] is the first registers of an arm register pair.
8986 OPERANDS[1] is an fpa register. */
8988 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8990 int arm_reg0
= REGNO (operands
[0]);
8993 gcc_assert (arm_reg0
!= IP_REGNUM
);
8995 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8996 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8997 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8999 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
9000 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
9004 /* Output a move from arm registers to arm registers of a long double
9005 OPERANDS[0] is the destination.
9006 OPERANDS[1] is the source. */
9008 output_mov_long_double_arm_from_arm (rtx
*operands
)
9010 /* We have to be careful here because the two might overlap. */
9011 int dest_start
= REGNO (operands
[0]);
9012 int src_start
= REGNO (operands
[1]);
9016 if (dest_start
< src_start
)
9018 for (i
= 0; i
< 3; i
++)
9020 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
9021 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
9022 output_asm_insn ("mov%?\t%0, %1", ops
);
9027 for (i
= 2; i
>= 0; i
--)
9029 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
9030 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
9031 output_asm_insn ("mov%?\t%0, %1", ops
);
9039 /* Output a move from arm registers to an fpa registers.
9040 OPERANDS[0] is an fpa register.
9041 OPERANDS[1] is the first registers of an arm register pair. */
9043 output_mov_double_fpa_from_arm (rtx
*operands
)
9045 int arm_reg0
= REGNO (operands
[1]);
9048 gcc_assert (arm_reg0
!= IP_REGNUM
);
9050 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
9051 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
9052 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops
);
9053 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
9057 /* Output a move from an fpa register to arm registers.
9058 OPERANDS[0] is the first registers of an arm register pair.
9059 OPERANDS[1] is an fpa register. */
9061 output_mov_double_arm_from_fpa (rtx
*operands
)
9063 int arm_reg0
= REGNO (operands
[0]);
9066 gcc_assert (arm_reg0
!= IP_REGNUM
);
9068 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
9069 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
9070 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
9071 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops
);
9075 /* Output a move between double words.
9076 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9077 or MEM<-REG and all MEMs must be offsettable addresses. */
9079 output_move_double (rtx
*operands
)
9081 enum rtx_code code0
= GET_CODE (operands
[0]);
9082 enum rtx_code code1
= GET_CODE (operands
[1]);
9087 int reg0
= REGNO (operands
[0]);
9089 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
9091 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
9093 switch (GET_CODE (XEXP (operands
[1], 0)))
9096 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
9100 gcc_assert (TARGET_LDRD
);
9101 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands
);
9106 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands
);
9108 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands
);
9112 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands
);
9116 gcc_assert (TARGET_LDRD
);
9117 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands
);
9122 otherops
[0] = operands
[0];
9123 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
9124 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
9126 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
9128 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
9130 /* Registers overlap so split out the increment. */
9131 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
9132 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops
);
9135 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops
);
9139 /* We only allow constant increments, so this is safe. */
9140 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops
);
9146 output_asm_insn ("adr%?\t%0, %1", operands
);
9147 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands
);
9150 /* ??? This needs checking for thumb2. */
9152 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
9153 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
9155 otherops
[0] = operands
[0];
9156 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
9157 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
9159 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
9161 if (GET_CODE (otherops
[2]) == CONST_INT
)
9163 switch ((int) INTVAL (otherops
[2]))
9166 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops
);
9171 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops
);
9176 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops
);
9181 && (GET_CODE (otherops
[2]) == REG
9182 || (GET_CODE (otherops
[2]) == CONST_INT
9183 && INTVAL (otherops
[2]) > -256
9184 && INTVAL (otherops
[2]) < 256)))
9186 if (reg_overlap_mentioned_p (otherops
[0],
9189 /* Swap base and index registers over to
9190 avoid a conflict. */
9191 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
9192 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
9194 /* If both registers conflict, it will usually
9195 have been fixed by a splitter. */
9196 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
9198 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
9199 output_asm_insn ("ldr%(d%)\t%0, [%1]",
9203 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops
);
9207 if (GET_CODE (otherops
[2]) == CONST_INT
)
9209 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
9210 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
9212 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
9215 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
9218 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
9220 return "ldm%(ia%)\t%0, %M0";
9224 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
9225 /* Take care of overlapping base/data reg. */
9226 if (reg_mentioned_p (operands
[0], operands
[1]))
9228 output_asm_insn ("ldr%?\t%0, %1", otherops
);
9229 output_asm_insn ("ldr%?\t%0, %1", operands
);
9233 output_asm_insn ("ldr%?\t%0, %1", operands
);
9234 output_asm_insn ("ldr%?\t%0, %1", otherops
);
9241 /* Constraints should ensure this. */
9242 gcc_assert (code0
== MEM
&& code1
== REG
);
9243 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
9245 switch (GET_CODE (XEXP (operands
[0], 0)))
9248 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
9252 gcc_assert (TARGET_LDRD
);
9253 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands
);
9258 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands
);
9260 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands
);
9264 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands
);
9268 gcc_assert (TARGET_LDRD
);
9269 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands
);
9274 otherops
[0] = operands
[1];
9275 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
9276 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
9278 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
9279 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops
);
9281 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops
);
9285 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
9286 if (GET_CODE (otherops
[2]) == CONST_INT
)
9288 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
9291 output_asm_insn ("stm%(db%)\t%m0, %M1", operands
);
9297 output_asm_insn ("stm%(da%)\t%m0, %M1", operands
);
9303 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands
);
9308 && (GET_CODE (otherops
[2]) == REG
9309 || (GET_CODE (otherops
[2]) == CONST_INT
9310 && INTVAL (otherops
[2]) > -256
9311 && INTVAL (otherops
[2]) < 256)))
9313 otherops
[0] = operands
[1];
9314 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
9315 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops
);
9321 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
9322 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
9323 output_asm_insn ("str%?\t%1, %0", operands
);
9324 output_asm_insn ("str%?\t%1, %0", otherops
);
9331 /* Output a VFP load or store instruction. */
9334 output_move_vfp (rtx
*operands
)
9336 rtx reg
, mem
, addr
, ops
[2];
9337 int load
= REG_P (operands
[0]);
9338 int dp
= GET_MODE_SIZE (GET_MODE (operands
[0])) == 8;
9339 int integer_p
= GET_MODE_CLASS (GET_MODE (operands
[0])) == MODE_INT
;
9340 const char *template;
9343 reg
= operands
[!load
];
9344 mem
= operands
[load
];
9346 gcc_assert (REG_P (reg
));
9347 gcc_assert (IS_VFP_REGNUM (REGNO (reg
)));
9348 gcc_assert (GET_MODE (reg
) == SFmode
9349 || GET_MODE (reg
) == DFmode
9350 || GET_MODE (reg
) == SImode
9351 || GET_MODE (reg
) == DImode
);
9352 gcc_assert (MEM_P (mem
));
9354 addr
= XEXP (mem
, 0);
9356 switch (GET_CODE (addr
))
9359 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
9360 ops
[0] = XEXP (addr
, 0);
9365 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
9366 ops
[0] = XEXP (addr
, 0);
9371 template = "f%s%c%%?\t%%%s0, %%1%s";
9377 sprintf (buff
, template,
9381 integer_p
? "\t%@ int" : "");
9382 output_asm_insn (buff
, ops
);
9387 /* Output an ADD r, s, #n where n may be too big for one instruction.
9388 If adding zero to one register, output nothing. */
9390 output_add_immediate (rtx
*operands
)
9392 HOST_WIDE_INT n
= INTVAL (operands
[2]);
9394 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
9397 output_multi_immediate (operands
,
9398 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9401 output_multi_immediate (operands
,
9402 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9409 /* Output a multiple immediate operation.
9410 OPERANDS is the vector of operands referred to in the output patterns.
9411 INSTR1 is the output pattern to use for the first constant.
9412 INSTR2 is the output pattern to use for subsequent constants.
9413 IMMED_OP is the index of the constant slot in OPERANDS.
9414 N is the constant value. */
9416 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
9417 int immed_op
, HOST_WIDE_INT n
)
9419 #if HOST_BITS_PER_WIDE_INT > 32
9425 /* Quick and easy output. */
9426 operands
[immed_op
] = const0_rtx
;
9427 output_asm_insn (instr1
, operands
);
9432 const char * instr
= instr1
;
9434 /* Note that n is never zero here (which would give no output). */
9435 for (i
= 0; i
< 32; i
+= 2)
9439 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
9440 output_asm_insn (instr
, operands
);
9450 /* Return the name of a shifter operation. */
9452 arm_shift_nmem(enum rtx_code code
)
9457 return ARM_LSL_NAME
;
9473 /* Return the appropriate ARM instruction for the operation code.
9474 The returned result should not be overwritten. OP is the rtx of the
9475 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9478 arithmetic_instr (rtx op
, int shift_first_arg
)
9480 switch (GET_CODE (op
))
9486 return shift_first_arg
? "rsb" : "sub";
9501 return arm_shift_nmem(GET_CODE(op
));
9508 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9509 for the operation code. The returned result should not be overwritten.
9510 OP is the rtx code of the shift.
9511 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9514 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
9517 enum rtx_code code
= GET_CODE (op
);
9519 switch (GET_CODE (XEXP (op
, 1)))
9527 *amountp
= INTVAL (XEXP (op
, 1));
9537 gcc_assert (*amountp
!= -1);
9538 *amountp
= 32 - *amountp
;
9547 mnem
= arm_shift_nmem(code
);
9551 /* We never have to worry about the amount being other than a
9552 power of 2, since this case can never be reloaded from a reg. */
9553 gcc_assert (*amountp
!= -1);
9554 *amountp
= int_log2 (*amountp
);
9555 return ARM_LSL_NAME
;
9563 /* This is not 100% correct, but follows from the desire to merge
9564 multiplication by a power of 2 with the recognizer for a
9565 shift. >=32 is not a valid shift for "lsl", so we must try and
9566 output a shift that produces the correct arithmetical result.
9567 Using lsr #32 is identical except for the fact that the carry bit
9568 is not set correctly if we set the flags; but we never use the
9569 carry bit from such an operation, so we can ignore that. */
9570 if (code
== ROTATERT
)
9571 /* Rotate is just modulo 32. */
9573 else if (*amountp
!= (*amountp
& 31))
9580 /* Shifts of 0 are no-ops. */
9588 /* Obtain the shift from the POWER of two. */
9590 static HOST_WIDE_INT
9591 int_log2 (HOST_WIDE_INT power
)
9593 HOST_WIDE_INT shift
= 0;
9595 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9597 gcc_assert (shift
<= 31);
9604 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9605 because /bin/as is horribly restrictive. The judgement about
9606 whether or not each character is 'printable' (and can be output as
9607 is) or not (and must be printed with an octal escape) must be made
9608 with reference to the *host* character set -- the situation is
9609 similar to that discussed in the comments above pp_c_char in
9610 c-pretty-print.c. */
9612 #define MAX_ASCII_LEN 51
9615 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9620 fputs ("\t.ascii\t\"", stream
);
9622 for (i
= 0; i
< len
; i
++)
9626 if (len_so_far
>= MAX_ASCII_LEN
)
9628 fputs ("\"\n\t.ascii\t\"", stream
);
9634 if (c
== '\\' || c
== '\"')
9636 putc ('\\', stream
);
9644 fprintf (stream
, "\\%03o", c
);
9649 fputs ("\"\n", stream
);
9652 /* Compute the register save mask for registers 0 through 12
9653 inclusive. This code is used by arm_compute_save_reg_mask. */
9655 static unsigned long
9656 arm_compute_save_reg0_reg12_mask (void)
9658 unsigned long func_type
= arm_current_func_type ();
9659 unsigned long save_reg_mask
= 0;
9662 if (IS_INTERRUPT (func_type
))
9664 unsigned int max_reg
;
9665 /* Interrupt functions must not corrupt any registers,
9666 even call clobbered ones. If this is a leaf function
9667 we can just examine the registers used by the RTL, but
9668 otherwise we have to assume that whatever function is
9669 called might clobber anything, and so we have to save
9670 all the call-clobbered registers as well. */
9671 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9672 /* FIQ handlers have registers r8 - r12 banked, so
9673 we only need to check r0 - r7, Normal ISRs only
9674 bank r14 and r15, so we must check up to r12.
9675 r13 is the stack pointer which is always preserved,
9676 so we do not need to consider it here. */
9681 for (reg
= 0; reg
<= max_reg
; reg
++)
9682 if (regs_ever_live
[reg
]
9683 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9684 save_reg_mask
|= (1 << reg
);
9686 /* Also save the pic base register if necessary. */
9688 && !TARGET_SINGLE_PIC_BASE
9689 && arm_pic_register
!= INVALID_REGNUM
9690 && current_function_uses_pic_offset_table
)
9691 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9695 /* In arm mode we handle r11 (FP) as a special case. */
9696 unsigned last_reg
= TARGET_ARM
? 10 : 11;
9698 /* In the normal case we only need to save those registers
9699 which are call saved and which are used by this function. */
9700 for (reg
= 0; reg
<= last_reg
; reg
++)
9701 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9702 save_reg_mask
|= (1 << reg
);
9704 /* Handle the frame pointer as a special case. */
9705 if (TARGET_THUMB2
&& frame_pointer_needed
)
9706 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9707 else if (! TARGET_APCS_FRAME
9708 && ! frame_pointer_needed
9709 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9710 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9711 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9713 /* If we aren't loading the PIC register,
9714 don't stack it even though it may be live. */
9716 && !TARGET_SINGLE_PIC_BASE
9717 && arm_pic_register
!= INVALID_REGNUM
9718 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9719 || current_function_uses_pic_offset_table
))
9720 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9722 /* The prologue will copy SP into R0, so save it. */
9723 if (IS_STACKALIGN (func_type
))
9727 /* Save registers so the exception handler can modify them. */
9728 if (current_function_calls_eh_return
)
9734 reg
= EH_RETURN_DATA_REGNO (i
);
9735 if (reg
== INVALID_REGNUM
)
9737 save_reg_mask
|= 1 << reg
;
9741 return save_reg_mask
;
9745 /* Compute a bit mask of which registers need to be
9746 saved on the stack for the current function. */
9748 static unsigned long
9749 arm_compute_save_reg_mask (void)
9751 unsigned int save_reg_mask
= 0;
9752 unsigned long func_type
= arm_current_func_type ();
9755 if (IS_NAKED (func_type
))
9756 /* This should never really happen. */
9759 /* If we are creating a stack frame, then we must save the frame pointer,
9760 IP (which will hold the old stack pointer), LR and the PC. */
9761 if (frame_pointer_needed
&& TARGET_ARM
)
9763 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9768 /* Volatile functions do not return, so there
9769 is no need to save any other registers. */
9770 if (IS_VOLATILE (func_type
))
9771 return save_reg_mask
;
9773 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9775 /* Decide if we need to save the link register.
9776 Interrupt routines have their own banked link register,
9777 so they never need to save it.
9778 Otherwise if we do not use the link register we do not need to save
9779 it. If we are pushing other registers onto the stack however, we
9780 can save an instruction in the epilogue by pushing the link register
9781 now and then popping it back into the PC. This incurs extra memory
9782 accesses though, so we only do it when optimizing for size, and only
9783 if we know that we will not need a fancy return sequence. */
9784 if (regs_ever_live
[LR_REGNUM
]
9787 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9788 && !current_function_calls_eh_return
))
9789 save_reg_mask
|= 1 << LR_REGNUM
;
9791 if (cfun
->machine
->lr_save_eliminated
)
9792 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9794 if (TARGET_REALLY_IWMMXT
9795 && ((bit_count (save_reg_mask
)
9796 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9798 /* The total number of registers that are going to be pushed
9799 onto the stack is odd. We need to ensure that the stack
9800 is 64-bit aligned before we start to save iWMMXt registers,
9801 and also before we start to create locals. (A local variable
9802 might be a double or long long which we will load/store using
9803 an iWMMXt instruction). Therefore we need to push another
9804 ARM register, so that the stack will be 64-bit aligned. We
9805 try to avoid using the arg registers (r0 -r3) as they might be
9806 used to pass values in a tail call. */
9807 for (reg
= 4; reg
<= 12; reg
++)
9808 if ((save_reg_mask
& (1 << reg
)) == 0)
9812 save_reg_mask
|= (1 << reg
);
9815 cfun
->machine
->sibcall_blocked
= 1;
9816 save_reg_mask
|= (1 << 3);
9820 /* We may need to push an additional register for use initializing the
9821 PIC base register. */
9822 if (TARGET_THUMB2
&& IS_NESTED (func_type
) && flag_pic
9823 && (save_reg_mask
& THUMB2_WORK_REGS
) == 0)
9825 reg
= thumb_find_work_register (1 << 4);
9826 if (!call_used_regs
[reg
])
9827 save_reg_mask
|= (1 << reg
);
9830 return save_reg_mask
;
9834 /* Compute a bit mask of which registers need to be
9835 saved on the stack for the current function. */
9836 static unsigned long
9837 thumb1_compute_save_reg_mask (void)
9843 for (reg
= 0; reg
< 12; reg
++)
9844 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9848 && !TARGET_SINGLE_PIC_BASE
9849 && arm_pic_register
!= INVALID_REGNUM
9850 && current_function_uses_pic_offset_table
)
9851 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9853 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9854 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9855 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9857 /* LR will also be pushed if any lo regs are pushed. */
9858 if (mask
& 0xff || thumb_force_lr_save ())
9859 mask
|= (1 << LR_REGNUM
);
9861 /* Make sure we have a low work register if we need one.
9862 We will need one if we are going to push a high register,
9863 but we are not currently intending to push a low register. */
9864 if ((mask
& 0xff) == 0
9865 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9867 /* Use thumb_find_work_register to choose which register
9868 we will use. If the register is live then we will
9869 have to push it. Use LAST_LO_REGNUM as our fallback
9870 choice for the register to select. */
9871 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9873 if (! call_used_regs
[reg
])
9881 /* Return the number of bytes required to save VFP registers. */
9883 arm_get_vfp_saved_size (void)
9890 /* Space for saved VFP registers. */
9891 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9894 for (regno
= FIRST_VFP_REGNUM
;
9895 regno
< LAST_VFP_REGNUM
;
9898 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9899 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9903 /* Workaround ARM10 VFPr1 bug. */
9904 if (count
== 2 && !arm_arch6
)
9915 if (count
== 2 && !arm_arch6
)
9924 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9925 everything bar the final return instruction. */
9927 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9929 char conditional
[10];
9932 unsigned long live_regs_mask
;
9933 unsigned long func_type
;
9934 arm_stack_offsets
*offsets
;
9936 func_type
= arm_current_func_type ();
9938 if (IS_NAKED (func_type
))
9941 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9943 /* If this function was declared non-returning, and we have
9944 found a tail call, then we have to trust that the called
9945 function won't return. */
9950 /* Otherwise, trap an attempted return by aborting. */
9952 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9954 assemble_external_libcall (ops
[1]);
9955 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9961 gcc_assert (!current_function_calls_alloca
|| really_return
);
9963 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9965 return_used_this_function
= 1;
9967 live_regs_mask
= arm_compute_save_reg_mask ();
9971 const char * return_reg
;
9973 /* If we do not have any special requirements for function exit
9974 (e.g. interworking, or ISR) then we can load the return address
9975 directly into the PC. Otherwise we must load it into LR. */
9977 && ! TARGET_INTERWORK
)
9978 return_reg
= reg_names
[PC_REGNUM
];
9980 return_reg
= reg_names
[LR_REGNUM
];
9982 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9984 /* There are three possible reasons for the IP register
9985 being saved. 1) a stack frame was created, in which case
9986 IP contains the old stack pointer, or 2) an ISR routine
9987 corrupted it, or 3) it was saved to align the stack on
9988 iWMMXt. In case 1, restore IP into SP, otherwise just
9990 if (frame_pointer_needed
)
9992 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9993 live_regs_mask
|= (1 << SP_REGNUM
);
9996 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9999 /* On some ARM architectures it is faster to use LDR rather than
10000 LDM to load a single register. On other architectures, the
10001 cost is the same. In 26 bit mode, or for exception handlers,
10002 we have to use LDM to load the PC so that the CPSR is also
10004 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
10005 if (live_regs_mask
== (1U << reg
))
10008 if (reg
<= LAST_ARM_REGNUM
10009 && (reg
!= LR_REGNUM
10011 || ! IS_INTERRUPT (func_type
)))
10013 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
10014 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
10021 /* Generate the load multiple instruction to restore the
10022 registers. Note we can get here, even if
10023 frame_pointer_needed is true, but only if sp already
10024 points to the base of the saved core registers. */
10025 if (live_regs_mask
& (1 << SP_REGNUM
))
10027 unsigned HOST_WIDE_INT stack_adjust
;
10029 offsets
= arm_get_frame_offsets ();
10030 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
10031 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
10033 if (stack_adjust
&& arm_arch5
&& TARGET_ARM
)
10034 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
10037 /* If we can't use ldmib (SA110 bug),
10038 then try to pop r3 instead. */
10040 live_regs_mask
|= 1 << 3;
10041 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
10045 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
10047 p
= instr
+ strlen (instr
);
10049 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
10050 if (live_regs_mask
& (1 << reg
))
10052 int l
= strlen (reg_names
[reg
]);
10058 memcpy (p
, ", ", 2);
10062 memcpy (p
, "%|", 2);
10063 memcpy (p
+ 2, reg_names
[reg
], l
);
10067 if (live_regs_mask
& (1 << LR_REGNUM
))
10069 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
10070 /* If returning from an interrupt, restore the CPSR. */
10071 if (IS_INTERRUPT (func_type
))
10078 output_asm_insn (instr
, & operand
);
10080 /* See if we need to generate an extra instruction to
10081 perform the actual function return. */
10083 && func_type
!= ARM_FT_INTERWORKED
10084 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
10086 /* The return has already been handled
10087 by loading the LR into the PC. */
10094 switch ((int) ARM_FUNC_TYPE (func_type
))
10098 /* ??? This is wrong for unified assembly syntax. */
10099 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
10102 case ARM_FT_INTERWORKED
:
10103 sprintf (instr
, "bx%s\t%%|lr", conditional
);
10106 case ARM_FT_EXCEPTION
:
10107 /* ??? This is wrong for unified assembly syntax. */
10108 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
10112 /* Use bx if it's available. */
10113 if (arm_arch5
|| arm_arch4t
)
10114 sprintf (instr
, "bx%s\t%%|lr", conditional
);
10116 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
10120 output_asm_insn (instr
, & operand
);
10126 /* Write the function name into the code section, directly preceding
10127 the function prologue.
10129 Code will be output similar to this:
10131 .ascii "arm_poke_function_name", 0
10134 .word 0xff000000 + (t1 - t0)
10135 arm_poke_function_name
10137 stmfd sp!, {fp, ip, lr, pc}
10140 When performing a stack backtrace, code can inspect the value
10141 of 'pc' stored at 'fp' + 0. If the trace function then looks
10142 at location pc - 12 and the top 8 bits are set, then we know
10143 that there is a function name embedded immediately preceding this
10144 location and has length ((pc[-3]) & 0xff000000).
10146 We assume that pc is declared as a pointer to an unsigned long.
10148 It is of no benefit to output the function name if we are assembling
10149 a leaf function. These function types will not contain a stack
10150 backtrace structure, therefore it is not possible to determine the
10153 arm_poke_function_name (FILE *stream
, const char *name
)
10155 unsigned long alignlength
;
10156 unsigned long length
;
10159 length
= strlen (name
) + 1;
10160 alignlength
= ROUND_UP_WORD (length
);
10162 ASM_OUTPUT_ASCII (stream
, name
, length
);
10163 ASM_OUTPUT_ALIGN (stream
, 2);
10164 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
10165 assemble_aligned_integer (UNITS_PER_WORD
, x
);
10168 /* Place some comments into the assembler stream
10169 describing the current function. */
10171 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
10173 unsigned long func_type
;
10177 thumb1_output_function_prologue (f
, frame_size
);
10181 /* Sanity check. */
10182 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
10184 func_type
= arm_current_func_type ();
10186 switch ((int) ARM_FUNC_TYPE (func_type
))
10189 case ARM_FT_NORMAL
:
10191 case ARM_FT_INTERWORKED
:
10192 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
10195 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
10198 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
10200 case ARM_FT_EXCEPTION
:
10201 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
10205 if (IS_NAKED (func_type
))
10206 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
10208 if (IS_VOLATILE (func_type
))
10209 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
10211 if (IS_NESTED (func_type
))
10212 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
10213 if (IS_STACKALIGN (func_type
))
10214 asm_fprintf (f
, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
10216 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
10217 current_function_args_size
,
10218 current_function_pretend_args_size
, frame_size
);
10220 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
10221 frame_pointer_needed
,
10222 cfun
->machine
->uses_anonymous_args
);
10224 if (cfun
->machine
->lr_save_eliminated
)
10225 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
10227 if (current_function_calls_eh_return
)
10228 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
10230 #ifdef AOF_ASSEMBLER
10232 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
10235 return_used_this_function
= 0;
10239 arm_output_epilogue (rtx sibling
)
10242 unsigned long saved_regs_mask
;
10243 unsigned long func_type
;
10244 /* Floats_offset is the offset from the "virtual" frame. In an APCS
10245 frame that is $fp + 4 for a non-variadic function. */
10246 int floats_offset
= 0;
10248 FILE * f
= asm_out_file
;
10249 unsigned int lrm_count
= 0;
10250 int really_return
= (sibling
== NULL
);
10252 arm_stack_offsets
*offsets
;
10254 /* If we have already generated the return instruction
10255 then it is futile to generate anything else. */
10256 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
10259 func_type
= arm_current_func_type ();
10261 if (IS_NAKED (func_type
))
10262 /* Naked functions don't have epilogues. */
10265 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
10269 /* A volatile function should never return. Call abort. */
10270 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
10271 assemble_external_libcall (op
);
10272 output_asm_insn ("bl\t%a0", &op
);
10277 /* If we are throwing an exception, then we really must be doing a
10278 return, so we can't tail-call. */
10279 gcc_assert (!current_function_calls_eh_return
|| really_return
);
10281 offsets
= arm_get_frame_offsets ();
10282 saved_regs_mask
= arm_compute_save_reg_mask ();
10285 lrm_count
= bit_count (saved_regs_mask
);
10287 floats_offset
= offsets
->saved_args
;
10288 /* Compute how far away the floats will be. */
10289 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
10290 if (saved_regs_mask
& (1 << reg
))
10291 floats_offset
+= 4;
10293 if (frame_pointer_needed
&& TARGET_ARM
)
10295 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
10296 int vfp_offset
= offsets
->frame
;
10298 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10300 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10301 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10303 floats_offset
+= 12;
10304 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
10305 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
10310 start_reg
= LAST_FPA_REGNUM
;
10312 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10314 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10316 floats_offset
+= 12;
10318 /* We can't unstack more than four registers at once. */
10319 if (start_reg
- reg
== 3)
10321 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
10322 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
10323 start_reg
= reg
- 1;
10328 if (reg
!= start_reg
)
10329 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
10330 reg
+ 1, start_reg
- reg
,
10331 FP_REGNUM
, floats_offset
- vfp_offset
);
10332 start_reg
= reg
- 1;
10336 /* Just in case the last register checked also needs unstacking. */
10337 if (reg
!= start_reg
)
10338 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
10339 reg
+ 1, start_reg
- reg
,
10340 FP_REGNUM
, floats_offset
- vfp_offset
);
10343 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10347 /* The fldmd insns do not have base+offset addressing
10348 modes, so we use IP to hold the address. */
10349 saved_size
= arm_get_vfp_saved_size ();
10351 if (saved_size
> 0)
10353 floats_offset
+= saved_size
;
10354 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
10355 FP_REGNUM
, floats_offset
- vfp_offset
);
10357 start_reg
= FIRST_VFP_REGNUM
;
10358 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10360 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10361 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10363 if (start_reg
!= reg
)
10364 vfp_output_fldmd (f
, IP_REGNUM
,
10365 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10366 (reg
- start_reg
) / 2);
10367 start_reg
= reg
+ 2;
10370 if (start_reg
!= reg
)
10371 vfp_output_fldmd (f
, IP_REGNUM
,
10372 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10373 (reg
- start_reg
) / 2);
10378 /* The frame pointer is guaranteed to be non-double-word aligned.
10379 This is because it is set to (old_stack_pointer - 4) and the
10380 old_stack_pointer was double word aligned. Thus the offset to
10381 the iWMMXt registers to be loaded must also be non-double-word
10382 sized, so that the resultant address *is* double-word aligned.
10383 We can ignore floats_offset since that was already included in
10384 the live_regs_mask. */
10385 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
10387 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10388 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10390 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
10391 reg
, FP_REGNUM
, lrm_count
* 4);
10396 /* saved_regs_mask should contain the IP, which at the time of stack
10397 frame generation actually contains the old stack pointer. So a
10398 quick way to unwind the stack is just pop the IP register directly
10399 into the stack pointer. */
10400 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
10401 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
10402 saved_regs_mask
|= (1 << SP_REGNUM
);
10404 /* There are two registers left in saved_regs_mask - LR and PC. We
10405 only need to restore the LR register (the return address), but to
10406 save time we can load it directly into the PC, unless we need a
10407 special function exit sequence, or we are not really returning. */
10409 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
10410 && !current_function_calls_eh_return
)
10411 /* Delete the LR from the register mask, so that the LR on
10412 the stack is loaded into the PC in the register mask. */
10413 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
10415 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
10417 /* We must use SP as the base register, because SP is one of the
10418 registers being restored. If an interrupt or page fault
10419 happens in the ldm instruction, the SP might or might not
10420 have been restored. That would be bad, as then SP will no
10421 longer indicate the safe area of stack, and we can get stack
10422 corruption. Using SP as the base register means that it will
10423 be reset correctly to the original value, should an interrupt
10424 occur. If the stack pointer already points at the right
10425 place, then omit the subtraction. */
10426 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
10427 || current_function_calls_alloca
)
10428 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
10429 4 * bit_count (saved_regs_mask
));
10430 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
);
10432 if (IS_INTERRUPT (func_type
))
10433 /* Interrupt handlers will have pushed the
10434 IP onto the stack, so restore it now. */
10435 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, 1 << IP_REGNUM
);
10439 HOST_WIDE_INT amount
;
10440 /* Restore stack pointer if necessary. */
10441 if (frame_pointer_needed
)
10443 /* For Thumb-2 restore sp from the frame pointer.
10444 Operand restrictions mean we have to incrememnt FP, then copy
10446 amount
= offsets
->locals_base
- offsets
->saved_regs
;
10447 operands
[0] = hard_frame_pointer_rtx
;
10451 operands
[0] = stack_pointer_rtx
;
10452 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
10457 operands
[1] = operands
[0];
10458 operands
[2] = GEN_INT (amount
);
10459 output_add_immediate (operands
);
10461 if (frame_pointer_needed
)
10462 asm_fprintf (f
, "\tmov\t%r, %r\n",
10463 SP_REGNUM
, HARD_FRAME_POINTER_REGNUM
);
10465 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10467 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
10468 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10469 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
10474 start_reg
= FIRST_FPA_REGNUM
;
10476 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
10478 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10480 if (reg
- start_reg
== 3)
10482 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
10483 start_reg
, SP_REGNUM
);
10484 start_reg
= reg
+ 1;
10489 if (reg
!= start_reg
)
10490 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
10491 start_reg
, reg
- start_reg
,
10494 start_reg
= reg
+ 1;
10498 /* Just in case the last register checked also needs unstacking. */
10499 if (reg
!= start_reg
)
10500 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
10501 start_reg
, reg
- start_reg
, SP_REGNUM
);
10504 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10506 start_reg
= FIRST_VFP_REGNUM
;
10507 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10509 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10510 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10512 if (start_reg
!= reg
)
10513 vfp_output_fldmd (f
, SP_REGNUM
,
10514 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10515 (reg
- start_reg
) / 2);
10516 start_reg
= reg
+ 2;
10519 if (start_reg
!= reg
)
10520 vfp_output_fldmd (f
, SP_REGNUM
,
10521 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10522 (reg
- start_reg
) / 2);
10525 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
10526 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10527 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
10529 /* If we can, restore the LR into the PC. */
10530 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
10531 && !IS_STACKALIGN (func_type
)
10533 && current_function_pretend_args_size
== 0
10534 && saved_regs_mask
& (1 << LR_REGNUM
)
10535 && !current_function_calls_eh_return
)
10537 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
10538 saved_regs_mask
|= (1 << PC_REGNUM
);
10541 /* Load the registers off the stack. If we only have one register
10542 to load use the LDR instruction - it is faster. For Thumb-2
10543 always use pop and the assembler will pick the best instruction.*/
10544 if (TARGET_ARM
&& saved_regs_mask
== (1 << LR_REGNUM
))
10546 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
10548 else if (saved_regs_mask
)
10550 if (saved_regs_mask
& (1 << SP_REGNUM
))
10551 /* Note - write back to the stack register is not enabled
10552 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10553 in the list of registers and if we add writeback the
10554 instruction becomes UNPREDICTABLE. */
10555 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
);
10556 else if (TARGET_ARM
)
10557 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, saved_regs_mask
);
10559 print_multi_reg (f
, "pop\t", SP_REGNUM
, saved_regs_mask
);
10562 if (current_function_pretend_args_size
)
10564 /* Unwind the pre-pushed regs. */
10565 operands
[0] = operands
[1] = stack_pointer_rtx
;
10566 operands
[2] = GEN_INT (current_function_pretend_args_size
);
10567 output_add_immediate (operands
);
10571 /* We may have already restored PC directly from the stack. */
10572 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10575 /* Stack adjustment for exception handler. */
10576 if (current_function_calls_eh_return
)
10577 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10578 ARM_EH_STACKADJ_REGNUM
);
10580 /* Generate the return instruction. */
10581 switch ((int) ARM_FUNC_TYPE (func_type
))
10585 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10588 case ARM_FT_EXCEPTION
:
10589 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10592 case ARM_FT_INTERWORKED
:
10593 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10597 if (IS_STACKALIGN (func_type
))
10599 /* See comment in arm_expand_prologue. */
10600 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, 0);
10602 if (arm_arch5
|| arm_arch4t
)
10603 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10605 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10613 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10614 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10616 arm_stack_offsets
*offsets
;
10622 /* Emit any call-via-reg trampolines that are needed for v4t support
10623 of call_reg and call_value_reg type insns. */
10624 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10626 rtx label
= cfun
->machine
->call_via
[regno
];
10630 switch_to_section (function_section (current_function_decl
));
10631 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10632 CODE_LABEL_NUMBER (label
));
10633 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10637 /* ??? Probably not safe to set this here, since it assumes that a
10638 function will be emitted as assembly immediately after we generate
10639 RTL for it. This does not happen for inline functions. */
10640 return_used_this_function
= 0;
10642 else /* TARGET_32BIT */
10644 /* We need to take into account any stack-frame rounding. */
10645 offsets
= arm_get_frame_offsets ();
10647 gcc_assert (!use_return_insn (FALSE
, NULL
)
10648 || !return_used_this_function
10649 || offsets
->saved_regs
== offsets
->outgoing_args
10650 || frame_pointer_needed
);
10652 /* Reset the ARM-specific per-function variables. */
10653 after_arm_reorg
= 0;
10657 /* Generate and emit an insn that we will recognize as a push_multi.
10658 Unfortunately, since this insn does not reflect very well the actual
10659 semantics of the operation, we need to annotate the insn for the benefit
10660 of DWARF2 frame unwind information. */
10662 emit_multi_reg_push (unsigned long mask
)
10665 int num_dwarf_regs
;
10669 int dwarf_par_index
;
10672 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10673 if (mask
& (1 << i
))
10676 gcc_assert (num_regs
&& num_regs
<= 16);
10678 /* We don't record the PC in the dwarf frame information. */
10679 num_dwarf_regs
= num_regs
;
10680 if (mask
& (1 << PC_REGNUM
))
10683 /* For the body of the insn we are going to generate an UNSPEC in
10684 parallel with several USEs. This allows the insn to be recognized
10685 by the push_multi pattern in the arm.md file. The insn looks
10686 something like this:
10689 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10690 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10691 (use (reg:SI 11 fp))
10692 (use (reg:SI 12 ip))
10693 (use (reg:SI 14 lr))
10694 (use (reg:SI 15 pc))
10697 For the frame note however, we try to be more explicit and actually
10698 show each register being stored into the stack frame, plus a (single)
10699 decrement of the stack pointer. We do it this way in order to be
10700 friendly to the stack unwinding code, which only wants to see a single
10701 stack decrement per instruction. The RTL we generate for the note looks
10702 something like this:
10705 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10706 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10707 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10708 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10709 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10712 This sequence is used both by the code to support stack unwinding for
10713 exceptions handlers and the code to generate dwarf2 frame debugging. */
10715 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10716 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10717 dwarf_par_index
= 1;
10719 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10721 if (mask
& (1 << i
))
10723 reg
= gen_rtx_REG (SImode
, i
);
10725 XVECEXP (par
, 0, 0)
10726 = gen_rtx_SET (VOIDmode
,
10727 gen_frame_mem (BLKmode
,
10728 gen_rtx_PRE_DEC (BLKmode
,
10729 stack_pointer_rtx
)),
10730 gen_rtx_UNSPEC (BLKmode
,
10731 gen_rtvec (1, reg
),
10732 UNSPEC_PUSH_MULT
));
10734 if (i
!= PC_REGNUM
)
10736 tmp
= gen_rtx_SET (VOIDmode
,
10737 gen_frame_mem (SImode
, stack_pointer_rtx
),
10739 RTX_FRAME_RELATED_P (tmp
) = 1;
10740 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10748 for (j
= 1, i
++; j
< num_regs
; i
++)
10750 if (mask
& (1 << i
))
10752 reg
= gen_rtx_REG (SImode
, i
);
10754 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10756 if (i
!= PC_REGNUM
)
10759 = gen_rtx_SET (VOIDmode
,
10760 gen_frame_mem (SImode
,
10761 plus_constant (stack_pointer_rtx
,
10764 RTX_FRAME_RELATED_P (tmp
) = 1;
10765 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10772 par
= emit_insn (par
);
10774 tmp
= gen_rtx_SET (VOIDmode
,
10776 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
10777 RTX_FRAME_RELATED_P (tmp
) = 1;
10778 XVECEXP (dwarf
, 0, 0) = tmp
;
10780 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10785 /* Calculate the size of the return value that is passed in registers. */
10787 arm_size_return_regs (void)
10789 enum machine_mode mode
;
10791 if (current_function_return_rtx
!= 0)
10792 mode
= GET_MODE (current_function_return_rtx
);
10794 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10796 return GET_MODE_SIZE (mode
);
10800 emit_sfm (int base_reg
, int count
)
10807 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10808 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10810 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10812 XVECEXP (par
, 0, 0)
10813 = gen_rtx_SET (VOIDmode
,
10814 gen_frame_mem (BLKmode
,
10815 gen_rtx_PRE_DEC (BLKmode
,
10816 stack_pointer_rtx
)),
10817 gen_rtx_UNSPEC (BLKmode
,
10818 gen_rtvec (1, reg
),
10819 UNSPEC_PUSH_MULT
));
10820 tmp
= gen_rtx_SET (VOIDmode
,
10821 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10822 RTX_FRAME_RELATED_P (tmp
) = 1;
10823 XVECEXP (dwarf
, 0, 1) = tmp
;
10825 for (i
= 1; i
< count
; i
++)
10827 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10828 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10830 tmp
= gen_rtx_SET (VOIDmode
,
10831 gen_frame_mem (XFmode
,
10832 plus_constant (stack_pointer_rtx
,
10835 RTX_FRAME_RELATED_P (tmp
) = 1;
10836 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10839 tmp
= gen_rtx_SET (VOIDmode
,
10841 plus_constant (stack_pointer_rtx
, -12 * count
));
10843 RTX_FRAME_RELATED_P (tmp
) = 1;
10844 XVECEXP (dwarf
, 0, 0) = tmp
;
10846 par
= emit_insn (par
);
10847 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10853 /* Return true if the current function needs to save/restore LR. */
10856 thumb_force_lr_save (void)
10858 return !cfun
->machine
->lr_save_eliminated
10859 && (!leaf_function_p ()
10860 || thumb_far_jump_used_p ()
10861 || regs_ever_live
[LR_REGNUM
]);
10865 /* Compute the distance from register FROM to register TO.
10866 These can be the arg pointer (26), the soft frame pointer (25),
10867 the stack pointer (13) or the hard frame pointer (11).
10868 In thumb mode r7 is used as the soft frame pointer, if needed.
10869 Typical stack layout looks like this:
10871 old stack pointer -> | |
10874 | | saved arguments for
10875 | | vararg functions
10878 hard FP & arg pointer -> | | \
10886 soft frame pointer -> | | /
10891 locals base pointer -> | | /
10896 current stack pointer -> | | /
10899 For a given function some or all of these stack components
10900 may not be needed, giving rise to the possibility of
10901 eliminating some of the registers.
10903 The values returned by this function must reflect the behavior
10904 of arm_expand_prologue() and arm_compute_save_reg_mask().
10906 The sign of the number returned reflects the direction of stack
10907 growth, so the values are positive for all eliminations except
10908 from the soft frame pointer to the hard frame pointer.
10910 SFP may point just inside the local variables block to ensure correct
10914 /* Calculate stack offsets. These are used to calculate register elimination
10915 offsets and in prologue/epilogue code. */
10917 static arm_stack_offsets
*
10918 arm_get_frame_offsets (void)
10920 struct arm_stack_offsets
*offsets
;
10921 unsigned long func_type
;
10924 HOST_WIDE_INT frame_size
;
10926 offsets
= &cfun
->machine
->stack_offsets
;
10928 /* We need to know if we are a leaf function. Unfortunately, it
10929 is possible to be called after start_sequence has been called,
10930 which causes get_insns to return the insns for the sequence,
10931 not the function, which will cause leaf_function_p to return
10932 the incorrect result.
10934 to know about leaf functions once reload has completed, and the
10935 frame size cannot be changed after that time, so we can safely
10936 use the cached value. */
10938 if (reload_completed
)
10941 /* Initially this is the size of the local variables. It will translated
10942 into an offset once we have determined the size of preceding data. */
10943 frame_size
= ROUND_UP_WORD (get_frame_size ());
10945 leaf
= leaf_function_p ();
10947 /* Space for variadic functions. */
10948 offsets
->saved_args
= current_function_pretend_args_size
;
10950 /* In Thumb mode this is incorrect, but never used. */
10951 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10955 unsigned int regno
;
10957 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10959 /* We know that SP will be doubleword aligned on entry, and we must
10960 preserve that condition at any subroutine call. We also require the
10961 soft frame pointer to be doubleword aligned. */
10963 if (TARGET_REALLY_IWMMXT
)
10965 /* Check for the call-saved iWMMXt registers. */
10966 for (regno
= FIRST_IWMMXT_REGNUM
;
10967 regno
<= LAST_IWMMXT_REGNUM
;
10969 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10973 func_type
= arm_current_func_type ();
10974 if (! IS_VOLATILE (func_type
))
10976 /* Space for saved FPA registers. */
10977 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10978 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10981 /* Space for saved VFP registers. */
10982 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10983 saved
+= arm_get_vfp_saved_size ();
10986 else /* TARGET_THUMB1 */
10988 saved
= bit_count (thumb1_compute_save_reg_mask ()) * 4;
10989 if (TARGET_BACKTRACE
)
10993 /* Saved registers include the stack frame. */
10994 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10995 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10996 /* A leaf function does not need any stack alignment if it has nothing
10998 if (leaf
&& frame_size
== 0)
11000 offsets
->outgoing_args
= offsets
->soft_frame
;
11004 /* Ensure SFP has the correct alignment. */
11005 if (ARM_DOUBLEWORD_ALIGN
11006 && (offsets
->soft_frame
& 7))
11007 offsets
->soft_frame
+= 4;
11009 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
11010 offsets
->outgoing_args
= (offsets
->locals_base
11011 + current_function_outgoing_args_size
);
11013 if (ARM_DOUBLEWORD_ALIGN
)
11015 /* Ensure SP remains doubleword aligned. */
11016 if (offsets
->outgoing_args
& 7)
11017 offsets
->outgoing_args
+= 4;
11018 gcc_assert (!(offsets
->outgoing_args
& 7));
11025 /* Calculate the relative offsets for the different stack pointers. Positive
11026 offsets are in the direction of stack growth. */
11029 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
11031 arm_stack_offsets
*offsets
;
11033 offsets
= arm_get_frame_offsets ();
11035 /* OK, now we have enough information to compute the distances.
11036 There must be an entry in these switch tables for each pair
11037 of registers in ELIMINABLE_REGS, even if some of the entries
11038 seem to be redundant or useless. */
11041 case ARG_POINTER_REGNUM
:
11044 case THUMB_HARD_FRAME_POINTER_REGNUM
:
11047 case FRAME_POINTER_REGNUM
:
11048 /* This is the reverse of the soft frame pointer
11049 to hard frame pointer elimination below. */
11050 return offsets
->soft_frame
- offsets
->saved_args
;
11052 case ARM_HARD_FRAME_POINTER_REGNUM
:
11053 /* If there is no stack frame then the hard
11054 frame pointer and the arg pointer coincide. */
11055 if (offsets
->frame
== offsets
->saved_regs
)
11057 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
11058 return (frame_pointer_needed
11059 && cfun
->static_chain_decl
!= NULL
11060 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
11062 case STACK_POINTER_REGNUM
:
11063 /* If nothing has been pushed on the stack at all
11064 then this will return -4. This *is* correct! */
11065 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
11068 gcc_unreachable ();
11070 gcc_unreachable ();
11072 case FRAME_POINTER_REGNUM
:
11075 case THUMB_HARD_FRAME_POINTER_REGNUM
:
11078 case ARM_HARD_FRAME_POINTER_REGNUM
:
11079 /* The hard frame pointer points to the top entry in the
11080 stack frame. The soft frame pointer to the bottom entry
11081 in the stack frame. If there is no stack frame at all,
11082 then they are identical. */
11084 return offsets
->frame
- offsets
->soft_frame
;
11086 case STACK_POINTER_REGNUM
:
11087 return offsets
->outgoing_args
- offsets
->soft_frame
;
11090 gcc_unreachable ();
11092 gcc_unreachable ();
11095 /* You cannot eliminate from the stack pointer.
11096 In theory you could eliminate from the hard frame
11097 pointer to the stack pointer, but this will never
11098 happen, since if a stack frame is not needed the
11099 hard frame pointer will never be used. */
11100 gcc_unreachable ();
11105 /* Emit RTL to save coprocessor registers on funciton entry. Returns the
11106 number of bytes pushed. */
11109 arm_save_coproc_regs(void)
11111 int saved_size
= 0;
11113 unsigned start_reg
;
11116 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
11117 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
11119 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
11120 insn
= gen_rtx_MEM (V2SImode
, insn
);
11121 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
11122 RTX_FRAME_RELATED_P (insn
) = 1;
11126 /* Save any floating point call-saved registers used by this
11128 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
11130 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
11131 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
11133 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
11134 insn
= gen_rtx_MEM (XFmode
, insn
);
11135 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
11136 RTX_FRAME_RELATED_P (insn
) = 1;
11142 start_reg
= LAST_FPA_REGNUM
;
11144 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
11146 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
11148 if (start_reg
- reg
== 3)
11150 insn
= emit_sfm (reg
, 4);
11151 RTX_FRAME_RELATED_P (insn
) = 1;
11153 start_reg
= reg
- 1;
11158 if (start_reg
!= reg
)
11160 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
11161 RTX_FRAME_RELATED_P (insn
) = 1;
11162 saved_size
+= (start_reg
- reg
) * 12;
11164 start_reg
= reg
- 1;
11168 if (start_reg
!= reg
)
11170 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
11171 saved_size
+= (start_reg
- reg
) * 12;
11172 RTX_FRAME_RELATED_P (insn
) = 1;
11175 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
11177 start_reg
= FIRST_VFP_REGNUM
;
11179 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
11181 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
11182 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
11184 if (start_reg
!= reg
)
11185 saved_size
+= vfp_emit_fstmd (start_reg
,
11186 (reg
- start_reg
) / 2);
11187 start_reg
= reg
+ 2;
11190 if (start_reg
!= reg
)
11191 saved_size
+= vfp_emit_fstmd (start_reg
,
11192 (reg
- start_reg
) / 2);
11198 /* Set the Thumb frame pointer from the stack pointer. */
11201 thumb_set_frame_pointer (arm_stack_offsets
*offsets
)
11203 HOST_WIDE_INT amount
;
11206 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
11208 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
11209 stack_pointer_rtx
, GEN_INT (amount
)));
11212 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
11213 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
11214 hard_frame_pointer_rtx
,
11215 stack_pointer_rtx
));
11216 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11217 plus_constant (stack_pointer_rtx
, amount
));
11218 RTX_FRAME_RELATED_P (dwarf
) = 1;
11219 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
11223 RTX_FRAME_RELATED_P (insn
) = 1;
11226 /* Generate the prologue instructions for entry into an ARM or Thumb-2
11229 arm_expand_prologue (void)
11234 unsigned long live_regs_mask
;
11235 unsigned long func_type
;
11237 int saved_pretend_args
= 0;
11238 int saved_regs
= 0;
11239 unsigned HOST_WIDE_INT args_to_push
;
11240 arm_stack_offsets
*offsets
;
11242 func_type
= arm_current_func_type ();
11244 /* Naked functions don't have prologues. */
11245 if (IS_NAKED (func_type
))
11248 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
11249 args_to_push
= current_function_pretend_args_size
;
11251 /* Compute which register we will have to save onto the stack. */
11252 live_regs_mask
= arm_compute_save_reg_mask ();
11254 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
11256 if (IS_STACKALIGN (func_type
))
11261 /* Handle a word-aligned stack pointer. We generate the following:
11266 <save and restore r0 in normal prologue/epilogue>
11270 The unwinder doesn't need to know about the stack realignment.
11271 Just tell it we saved SP in r0. */
11272 gcc_assert (TARGET_THUMB2
&& !arm_arch_notm
&& args_to_push
== 0);
11274 r0
= gen_rtx_REG (SImode
, 0);
11275 r1
= gen_rtx_REG (SImode
, 1);
11276 dwarf
= gen_rtx_UNSPEC (SImode
, NULL_RTVEC
, UNSPEC_STACK_ALIGN
);
11277 dwarf
= gen_rtx_SET (VOIDmode
, r0
, dwarf
);
11278 insn
= gen_movsi (r0
, stack_pointer_rtx
);
11279 RTX_FRAME_RELATED_P (insn
) = 1;
11280 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
11281 dwarf
, REG_NOTES (insn
));
11283 emit_insn (gen_andsi3 (r1
, r0
, GEN_INT (~(HOST_WIDE_INT
)7)));
11284 emit_insn (gen_movsi (stack_pointer_rtx
, r1
));
11287 if (frame_pointer_needed
&& TARGET_ARM
)
11289 if (IS_INTERRUPT (func_type
))
11291 /* Interrupt functions must not corrupt any registers.
11292 Creating a frame pointer however, corrupts the IP
11293 register, so we must push it first. */
11294 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
11296 /* Do not set RTX_FRAME_RELATED_P on this insn.
11297 The dwarf stack unwinding code only wants to see one
11298 stack decrement per function, and this is not it. If
11299 this instruction is labeled as being part of the frame
11300 creation sequence then dwarf2out_frame_debug_expr will
11301 die when it encounters the assignment of IP to FP
11302 later on, since the use of SP here establishes SP as
11303 the CFA register and not IP.
11305 Anyway this instruction is not really part of the stack
11306 frame creation although it is part of the prologue. */
11308 else if (IS_NESTED (func_type
))
11310 /* The Static chain register is the same as the IP register
11311 used as a scratch register during stack frame creation.
11312 To get around this need to find somewhere to store IP
11313 whilst the frame is being created. We try the following
11316 1. The last argument register.
11317 2. A slot on the stack above the frame. (This only
11318 works if the function is not a varargs function).
11319 3. Register r3, after pushing the argument registers
11322 Note - we only need to tell the dwarf2 backend about the SP
11323 adjustment in the second variant; the static chain register
11324 doesn't need to be unwound, as it doesn't contain a value
11325 inherited from the caller. */
11327 if (regs_ever_live
[3] == 0)
11328 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
11329 else if (args_to_push
== 0)
11333 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
11334 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
11337 /* Just tell the dwarf backend that we adjusted SP. */
11338 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11339 plus_constant (stack_pointer_rtx
,
11341 RTX_FRAME_RELATED_P (insn
) = 1;
11342 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
11343 dwarf
, REG_NOTES (insn
));
11347 /* Store the args on the stack. */
11348 if (cfun
->machine
->uses_anonymous_args
)
11349 insn
= emit_multi_reg_push
11350 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
11353 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11354 GEN_INT (- args_to_push
)));
11356 RTX_FRAME_RELATED_P (insn
) = 1;
11358 saved_pretend_args
= 1;
11359 fp_offset
= args_to_push
;
11362 /* Now reuse r3 to preserve IP. */
11363 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
11367 insn
= emit_set_insn (ip_rtx
,
11368 plus_constant (stack_pointer_rtx
, fp_offset
));
11369 RTX_FRAME_RELATED_P (insn
) = 1;
11374 /* Push the argument registers, or reserve space for them. */
11375 if (cfun
->machine
->uses_anonymous_args
)
11376 insn
= emit_multi_reg_push
11377 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
11380 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11381 GEN_INT (- args_to_push
)));
11382 RTX_FRAME_RELATED_P (insn
) = 1;
11385 /* If this is an interrupt service routine, and the link register
11386 is going to be pushed, and we are not creating a stack frame,
11387 (which would involve an extra push of IP and a pop in the epilogue)
11388 subtracting four from LR now will mean that the function return
11389 can be done with a single instruction. */
11390 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
11391 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
11392 && ! frame_pointer_needed
)
11394 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
11396 emit_set_insn (lr
, plus_constant (lr
, -4));
11399 if (live_regs_mask
)
11401 insn
= emit_multi_reg_push (live_regs_mask
);
11402 saved_regs
+= bit_count (live_regs_mask
) * 4;
11403 RTX_FRAME_RELATED_P (insn
) = 1;
11406 if (! IS_VOLATILE (func_type
))
11407 saved_regs
+= arm_save_coproc_regs ();
11409 if (frame_pointer_needed
&& TARGET_ARM
)
11411 /* Create the new frame pointer. */
11413 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
11414 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
11415 RTX_FRAME_RELATED_P (insn
) = 1;
11417 if (IS_NESTED (func_type
))
11419 /* Recover the static chain register. */
11420 if (regs_ever_live
[3] == 0
11421 || saved_pretend_args
)
11422 insn
= gen_rtx_REG (SImode
, 3);
11423 else /* if (current_function_pretend_args_size == 0) */
11425 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
11426 insn
= gen_frame_mem (SImode
, insn
);
11428 emit_set_insn (ip_rtx
, insn
);
11429 /* Add a USE to stop propagate_one_insn() from barfing. */
11430 emit_insn (gen_prologue_use (ip_rtx
));
11435 offsets
= arm_get_frame_offsets ();
11436 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
11438 /* This add can produce multiple insns for a large constant, so we
11439 need to get tricky. */
11440 rtx last
= get_last_insn ();
11442 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
11443 - offsets
->outgoing_args
);
11445 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11449 last
= last
? NEXT_INSN (last
) : get_insns ();
11450 RTX_FRAME_RELATED_P (last
) = 1;
11452 while (last
!= insn
);
11454 /* If the frame pointer is needed, emit a special barrier that
11455 will prevent the scheduler from moving stores to the frame
11456 before the stack adjustment. */
11457 if (frame_pointer_needed
)
11458 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
11459 hard_frame_pointer_rtx
));
11463 if (frame_pointer_needed
&& TARGET_THUMB2
)
11464 thumb_set_frame_pointer (offsets
);
11466 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
11468 unsigned long mask
;
11470 mask
= live_regs_mask
;
11471 mask
&= THUMB2_WORK_REGS
;
11472 if (!IS_NESTED (func_type
))
11473 mask
|= (1 << IP_REGNUM
);
11474 arm_load_pic_register (mask
);
11477 /* If we are profiling, make sure no instructions are scheduled before
11478 the call to mcount. Similarly if the user has requested no
11479 scheduling in the prolog. Similarly if we want non-call exceptions
11480 using the EABI unwinder, to prevent faulting instructions from being
11481 swapped with a stack adjustment. */
11482 if (current_function_profile
|| !TARGET_SCHED_PROLOG
11483 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
11484 emit_insn (gen_blockage ());
11486 /* If the link register is being kept alive, with the return address in it,
11487 then make sure that it does not get reused by the ce2 pass. */
11488 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
11490 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
11491 cfun
->machine
->lr_save_eliminated
= 1;
11495 /* Print condition code to STREAM. Helper function for arm_print_operand. */
11497 arm_print_condition (FILE *stream
)
11499 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
11501 /* Branch conversion is not implemented for Thumb-2. */
11504 output_operand_lossage ("predicated Thumb instruction");
11507 if (current_insn_predicate
!= NULL
)
11509 output_operand_lossage
11510 ("predicated instruction in conditional sequence");
11514 fputs (arm_condition_codes
[arm_current_cc
], stream
);
11516 else if (current_insn_predicate
)
11518 enum arm_cond_code code
;
11522 output_operand_lossage ("predicated Thumb instruction");
11526 code
= get_arm_condition_code (current_insn_predicate
);
11527 fputs (arm_condition_codes
[code
], stream
);
11532 /* If CODE is 'd', then the X is a condition operand and the instruction
11533 should only be executed if the condition is true.
11534 if CODE is 'D', then the X is a condition operand and the instruction
11535 should only be executed if the condition is false: however, if the mode
11536 of the comparison is CCFPEmode, then always execute the instruction -- we
11537 do this because in these circumstances !GE does not necessarily imply LT;
11538 in these cases the instruction pattern will take care to make sure that
11539 an instruction containing %d will follow, thereby undoing the effects of
11540 doing this instruction unconditionally.
11541 If CODE is 'N' then X is a floating point operand that must be negated
11543 If CODE is 'B' then output a bitwise inverted value of X (a const int).
11544 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
11546 arm_print_operand (FILE *stream
, rtx x
, int code
)
11551 fputs (ASM_COMMENT_START
, stream
);
11555 fputs (user_label_prefix
, stream
);
11559 fputs (REGISTER_PREFIX
, stream
);
11563 arm_print_condition (stream
);
11567 /* Nothing in unified syntax, otherwise the current condition code. */
11568 if (!TARGET_UNIFIED_ASM
)
11569 arm_print_condition (stream
);
11573 /* The current condition code in unified syntax, otherwise nothing. */
11574 if (TARGET_UNIFIED_ASM
)
11575 arm_print_condition (stream
);
11579 /* The current condition code for a condition code setting instruction.
11580 Preceeded by 's' in unified syntax, otherwise followed by 's'. */
11581 if (TARGET_UNIFIED_ASM
)
11583 fputc('s', stream
);
11584 arm_print_condition (stream
);
11588 arm_print_condition (stream
);
11589 fputc('s', stream
);
11594 /* If the instruction is conditionally executed then print
11595 the current condition code, otherwise print 's'. */
11596 gcc_assert (TARGET_THUMB2
&& TARGET_UNIFIED_ASM
);
11597 if (current_insn_predicate
)
11598 arm_print_condition (stream
);
11600 fputc('s', stream
);
11606 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
11607 r
= REAL_VALUE_NEGATE (r
);
11608 fprintf (stream
, "%s", fp_const_from_val (&r
));
11613 if (GET_CODE (x
) == CONST_INT
)
11616 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
11617 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
11621 putc ('~', stream
);
11622 output_addr_const (stream
, x
);
11627 /* The low 16 bits of an immediate constant. */
11628 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL(x
) & 0xffff);
11632 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
11635 /* Truncate Cirrus shift counts. */
11637 if (GET_CODE (x
) == CONST_INT
)
11639 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
11642 arm_print_operand (stream
, x
, 0);
11646 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
11654 if (!shift_operator (x
, SImode
))
11656 output_operand_lossage ("invalid shift operand");
11660 shift
= shift_op (x
, &val
);
11664 fprintf (stream
, ", %s ", shift
);
11666 arm_print_operand (stream
, XEXP (x
, 1), 0);
11668 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
11673 /* An explanation of the 'Q', 'R' and 'H' register operands:
11675 In a pair of registers containing a DI or DF value the 'Q'
11676 operand returns the register number of the register containing
11677 the least significant part of the value. The 'R' operand returns
11678 the register number of the register containing the most
11679 significant part of the value.
11681 The 'H' operand returns the higher of the two register numbers.
11682 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11683 same as the 'Q' operand, since the most significant part of the
11684 value is held in the lower number register. The reverse is true
11685 on systems where WORDS_BIG_ENDIAN is false.
11687 The purpose of these operands is to distinguish between cases
11688 where the endian-ness of the values is important (for example
11689 when they are added together), and cases where the endian-ness
11690 is irrelevant, but the order of register operations is important.
11691 For example when loading a value from memory into a register
11692 pair, the endian-ness does not matter. Provided that the value
11693 from the lower memory address is put into the lower numbered
11694 register, and the value from the higher address is put into the
11695 higher numbered register, the load will work regardless of whether
11696 the value being loaded is big-wordian or little-wordian. The
11697 order of the two register loads can matter however, if the address
11698 of the memory location is actually held in one of the registers
11699 being overwritten by the load. */
11701 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11703 output_operand_lossage ("invalid operand for code '%c'", code
);
11707 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11711 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11713 output_operand_lossage ("invalid operand for code '%c'", code
);
11717 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11721 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11723 output_operand_lossage ("invalid operand for code '%c'", code
);
11727 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11731 asm_fprintf (stream
, "%r",
11732 GET_CODE (XEXP (x
, 0)) == REG
11733 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11737 asm_fprintf (stream
, "{%r-%r}",
11739 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11743 /* CONST_TRUE_RTX means always -- that's the default. */
11744 if (x
== const_true_rtx
)
11747 if (!COMPARISON_P (x
))
11749 output_operand_lossage ("invalid operand for code '%c'", code
);
11753 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11758 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11759 want to do that. */
11760 if (x
== const_true_rtx
)
11762 output_operand_lossage ("instruction never exectued");
11765 if (!COMPARISON_P (x
))
11767 output_operand_lossage ("invalid operand for code '%c'", code
);
11771 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11772 (get_arm_condition_code (x
))],
11776 /* Cirrus registers can be accessed in a variety of ways:
11777 single floating point (f)
11778 double floating point (d)
11780 64bit integer (dx). */
11781 case 'W': /* Cirrus register in F mode. */
11782 case 'X': /* Cirrus register in D mode. */
11783 case 'Y': /* Cirrus register in FX mode. */
11784 case 'Z': /* Cirrus register in DX mode. */
11785 gcc_assert (GET_CODE (x
) == REG
11786 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11788 fprintf (stream
, "mv%s%s",
11790 : code
== 'X' ? "d"
11791 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11795 /* Print cirrus register in the mode specified by the register's mode. */
11798 int mode
= GET_MODE (x
);
11800 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11802 output_operand_lossage ("invalid operand for code '%c'", code
);
11806 fprintf (stream
, "mv%s%s",
11807 mode
== DFmode
? "d"
11808 : mode
== SImode
? "fx"
11809 : mode
== DImode
? "dx"
11810 : "f", reg_names
[REGNO (x
)] + 2);
11816 if (GET_CODE (x
) != REG
11817 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11818 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11819 /* Bad value for wCG register number. */
11821 output_operand_lossage ("invalid operand for code '%c'", code
);
11826 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11829 /* Print an iWMMXt control register name. */
11831 if (GET_CODE (x
) != CONST_INT
11833 || INTVAL (x
) >= 16)
11834 /* Bad value for wC register number. */
11836 output_operand_lossage ("invalid operand for code '%c'", code
);
11842 static const char * wc_reg_names
[16] =
11844 "wCID", "wCon", "wCSSF", "wCASF",
11845 "wC4", "wC5", "wC6", "wC7",
11846 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11847 "wC12", "wC13", "wC14", "wC15"
11850 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11854 /* Print a VFP double precision register name. */
11857 int mode
= GET_MODE (x
);
11860 if (mode
!= DImode
&& mode
!= DFmode
)
11862 output_operand_lossage ("invalid operand for code '%c'", code
);
11866 if (GET_CODE (x
) != REG
11867 || !IS_VFP_REGNUM (REGNO (x
)))
11869 output_operand_lossage ("invalid operand for code '%c'", code
);
11873 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11876 output_operand_lossage ("invalid operand for code '%c'", code
);
11880 fprintf (stream
, "d%d", num
>> 1);
11887 output_operand_lossage ("missing operand");
11891 switch (GET_CODE (x
))
11894 asm_fprintf (stream
, "%r", REGNO (x
));
11898 output_memory_reference_mode
= GET_MODE (x
);
11899 output_address (XEXP (x
, 0));
11903 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11907 gcc_assert (GET_CODE (x
) != NEG
);
11908 fputc ('#', stream
);
11909 output_addr_const (stream
, x
);
11915 #ifndef AOF_ASSEMBLER
11916 /* Target hook for assembling integer objects. The ARM version needs to
11917 handle word-sized values specially. */
11919 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11921 if (size
== UNITS_PER_WORD
&& aligned_p
)
11923 fputs ("\t.word\t", asm_out_file
);
11924 output_addr_const (asm_out_file
, x
);
11926 /* Mark symbols as position independent. We only do this in the
11927 .text segment, not in the .data segment. */
11928 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11929 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11931 if (GET_CODE (x
) == SYMBOL_REF
11932 && (CONSTANT_POOL_ADDRESS_P (x
)
11933 || SYMBOL_REF_LOCAL_P (x
)))
11934 fputs ("(GOTOFF)", asm_out_file
);
11935 else if (GET_CODE (x
) == LABEL_REF
)
11936 fputs ("(GOTOFF)", asm_out_file
);
11938 fputs ("(GOT)", asm_out_file
);
11940 fputc ('\n', asm_out_file
);
11944 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11948 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11950 units
= CONST_VECTOR_NUNITS (x
);
11952 switch (GET_MODE (x
))
11954 case V2SImode
: size
= 4; break;
11955 case V4HImode
: size
= 2; break;
11956 case V8QImode
: size
= 1; break;
11958 gcc_unreachable ();
11961 for (i
= 0; i
< units
; i
++)
11965 elt
= CONST_VECTOR_ELT (x
, i
);
11967 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11973 return default_assemble_integer (x
, size
, aligned_p
);
11977 /* Add a function to the list of static constructors. */
11980 arm_elf_asm_constructor (rtx symbol
, int priority
)
11984 if (!TARGET_AAPCS_BASED
)
11986 default_named_section_asm_out_constructor (symbol
, priority
);
11990 /* Put these in the .init_array section, using a special relocation. */
11991 if (priority
!= DEFAULT_INIT_PRIORITY
)
11994 sprintf (buf
, ".init_array.%.5u", priority
);
11995 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
12000 switch_to_section (s
);
12001 assemble_align (POINTER_SIZE
);
12002 fputs ("\t.word\t", asm_out_file
);
12003 output_addr_const (asm_out_file
, symbol
);
12004 fputs ("(target1)\n", asm_out_file
);
12008 /* A finite state machine takes care of noticing whether or not instructions
12009 can be conditionally executed, and thus decrease execution time and code
12010 size by deleting branch instructions. The fsm is controlled by
12011 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
12013 /* The state of the fsm controlling condition codes are:
12014 0: normal, do nothing special
12015 1: make ASM_OUTPUT_OPCODE not output this instruction
12016 2: make ASM_OUTPUT_OPCODE not output this instruction
12017 3: make instructions conditional
12018 4: make instructions conditional
12020 State transitions (state->state by whom under condition):
12021 0 -> 1 final_prescan_insn if the `target' is a label
12022 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
12023 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
12024 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
12025 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
12026 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
12027 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
12028 (the target insn is arm_target_insn).
12030 If the jump clobbers the conditions then we use states 2 and 4.
12032 A similar thing can be done with conditional return insns.
12034 XXX In case the `target' is an unconditional branch, this conditionalising
12035 of the instructions always reduces code size, but not always execution
12036 time. But then, I want to reduce the code size to somewhere near what
12037 /bin/cc produces. */
12039 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
12040 instructions. When a COND_EXEC instruction is seen the subsequent
12041 instructions are scanned so that multiple conditional instructions can be
12042 combined into a single IT block. arm_condexec_count and arm_condexec_mask
12043 specify the length and true/false mask for the IT block. These will be
12044 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
12046 /* Returns the index of the ARM condition code string in
12047 `arm_condition_codes'. COMPARISON should be an rtx like
12048 `(eq (...) (...))'. */
12049 static enum arm_cond_code
12050 get_arm_condition_code (rtx comparison
)
12052 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
12054 enum rtx_code comp_code
= GET_CODE (comparison
);
12056 if (GET_MODE_CLASS (mode
) != MODE_CC
)
12057 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
12058 XEXP (comparison
, 1));
12062 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
12063 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
12064 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
12065 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
12066 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
12067 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
12068 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
12069 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
12070 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
12071 case CC_DLTUmode
: code
= ARM_CC
;
12074 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
12076 if (comp_code
== EQ
)
12077 return ARM_INVERSE_CONDITION_CODE (code
);
12083 case NE
: return ARM_NE
;
12084 case EQ
: return ARM_EQ
;
12085 case GE
: return ARM_PL
;
12086 case LT
: return ARM_MI
;
12087 default: gcc_unreachable ();
12093 case NE
: return ARM_NE
;
12094 case EQ
: return ARM_EQ
;
12095 default: gcc_unreachable ();
12101 case NE
: return ARM_MI
;
12102 case EQ
: return ARM_PL
;
12103 default: gcc_unreachable ();
12108 /* These encodings assume that AC=1 in the FPA system control
12109 byte. This allows us to handle all cases except UNEQ and
12113 case GE
: return ARM_GE
;
12114 case GT
: return ARM_GT
;
12115 case LE
: return ARM_LS
;
12116 case LT
: return ARM_MI
;
12117 case NE
: return ARM_NE
;
12118 case EQ
: return ARM_EQ
;
12119 case ORDERED
: return ARM_VC
;
12120 case UNORDERED
: return ARM_VS
;
12121 case UNLT
: return ARM_LT
;
12122 case UNLE
: return ARM_LE
;
12123 case UNGT
: return ARM_HI
;
12124 case UNGE
: return ARM_PL
;
12125 /* UNEQ and LTGT do not have a representation. */
12126 case UNEQ
: /* Fall through. */
12127 case LTGT
: /* Fall through. */
12128 default: gcc_unreachable ();
12134 case NE
: return ARM_NE
;
12135 case EQ
: return ARM_EQ
;
12136 case GE
: return ARM_LE
;
12137 case GT
: return ARM_LT
;
12138 case LE
: return ARM_GE
;
12139 case LT
: return ARM_GT
;
12140 case GEU
: return ARM_LS
;
12141 case GTU
: return ARM_CC
;
12142 case LEU
: return ARM_CS
;
12143 case LTU
: return ARM_HI
;
12144 default: gcc_unreachable ();
12150 case LTU
: return ARM_CS
;
12151 case GEU
: return ARM_CC
;
12152 default: gcc_unreachable ();
12158 case NE
: return ARM_NE
;
12159 case EQ
: return ARM_EQ
;
12160 case GE
: return ARM_GE
;
12161 case GT
: return ARM_GT
;
12162 case LE
: return ARM_LE
;
12163 case LT
: return ARM_LT
;
12164 case GEU
: return ARM_CS
;
12165 case GTU
: return ARM_HI
;
12166 case LEU
: return ARM_LS
;
12167 case LTU
: return ARM_CC
;
12168 default: gcc_unreachable ();
12171 default: gcc_unreachable ();
12175 /* Tell arm_asm_ouput_opcode to output IT blocks for conditionally executed
12178 thumb2_final_prescan_insn (rtx insn
)
12180 rtx first_insn
= insn
;
12181 rtx body
= PATTERN (insn
);
12183 enum arm_cond_code code
;
12187 /* Remove the previous insn from the count of insns to be output. */
12188 if (arm_condexec_count
)
12189 arm_condexec_count
--;
12191 /* Nothing to do if we are already inside a conditional block. */
12192 if (arm_condexec_count
)
12195 if (GET_CODE (body
) != COND_EXEC
)
12198 /* Conditional jumps are implemented directly. */
12199 if (GET_CODE (insn
) == JUMP_INSN
)
12202 predicate
= COND_EXEC_TEST (body
);
12203 arm_current_cc
= get_arm_condition_code (predicate
);
12205 n
= get_attr_ce_count (insn
);
12206 arm_condexec_count
= 1;
12207 arm_condexec_mask
= (1 << n
) - 1;
12208 arm_condexec_masklen
= n
;
12209 /* See if subsequent instructions can be combined into the same block. */
12212 insn
= next_nonnote_insn (insn
);
12214 /* Jumping into the middle of an IT block is illegal, so a label or
12215 barrier terminates the block. */
12216 if (GET_CODE (insn
) != INSN
&& GET_CODE(insn
) != JUMP_INSN
)
12219 body
= PATTERN (insn
);
12220 /* USE and CLOBBER aren't really insns, so just skip them. */
12221 if (GET_CODE (body
) == USE
12222 || GET_CODE (body
) == CLOBBER
)
12224 arm_condexec_count
++;
12228 /* ??? Recognise conditional jumps, and combine them with IT blocks. */
12229 if (GET_CODE (body
) != COND_EXEC
)
12231 /* Allow up to 4 conditionally executed instructions in a block. */
12232 n
= get_attr_ce_count (insn
);
12233 if (arm_condexec_masklen
+ n
> 4)
12236 predicate
= COND_EXEC_TEST (body
);
12237 code
= get_arm_condition_code (predicate
);
12238 mask
= (1 << n
) - 1;
12239 if (arm_current_cc
== code
)
12240 arm_condexec_mask
|= (mask
<< arm_condexec_masklen
);
12241 else if (arm_current_cc
!= ARM_INVERSE_CONDITION_CODE(code
))
12244 arm_condexec_count
++;
12245 arm_condexec_masklen
+= n
;
12247 /* A jump must be the last instruction in a conditional block. */
12248 if (GET_CODE(insn
) == JUMP_INSN
)
12251 /* Restore recog_data (getting the attributes of other insns can
12252 destroy this array, but final.c assumes that it remains intact
12253 across this call). */
12254 extract_constrain_insn_cached (first_insn
);
12258 arm_final_prescan_insn (rtx insn
)
12260 /* BODY will hold the body of INSN. */
12261 rtx body
= PATTERN (insn
);
12263 /* This will be 1 if trying to repeat the trick, and things need to be
12264 reversed if it appears to fail. */
12267 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
12268 taken are clobbered, even if the rtl suggests otherwise. It also
12269 means that we have to grub around within the jump expression to find
12270 out what the conditions are when the jump isn't taken. */
12271 int jump_clobbers
= 0;
12273 /* If we start with a return insn, we only succeed if we find another one. */
12274 int seeking_return
= 0;
12276 /* START_INSN will hold the insn from where we start looking. This is the
12277 first insn after the following code_label if REVERSE is true. */
12278 rtx start_insn
= insn
;
12280 /* If in state 4, check if the target branch is reached, in order to
12281 change back to state 0. */
12282 if (arm_ccfsm_state
== 4)
12284 if (insn
== arm_target_insn
)
12286 arm_target_insn
= NULL
;
12287 arm_ccfsm_state
= 0;
12292 /* If in state 3, it is possible to repeat the trick, if this insn is an
12293 unconditional branch to a label, and immediately following this branch
12294 is the previous target label which is only used once, and the label this
12295 branch jumps to is not too far off. */
12296 if (arm_ccfsm_state
== 3)
12298 if (simplejump_p (insn
))
12300 start_insn
= next_nonnote_insn (start_insn
);
12301 if (GET_CODE (start_insn
) == BARRIER
)
12303 /* XXX Isn't this always a barrier? */
12304 start_insn
= next_nonnote_insn (start_insn
);
12306 if (GET_CODE (start_insn
) == CODE_LABEL
12307 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
12308 && LABEL_NUSES (start_insn
) == 1)
12313 else if (GET_CODE (body
) == RETURN
)
12315 start_insn
= next_nonnote_insn (start_insn
);
12316 if (GET_CODE (start_insn
) == BARRIER
)
12317 start_insn
= next_nonnote_insn (start_insn
);
12318 if (GET_CODE (start_insn
) == CODE_LABEL
12319 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
12320 && LABEL_NUSES (start_insn
) == 1)
12323 seeking_return
= 1;
12332 gcc_assert (!arm_ccfsm_state
|| reverse
);
12333 if (GET_CODE (insn
) != JUMP_INSN
)
12336 /* This jump might be paralleled with a clobber of the condition codes
12337 the jump should always come first */
12338 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
12339 body
= XVECEXP (body
, 0, 0);
12342 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
12343 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
12346 int fail
= FALSE
, succeed
= FALSE
;
12347 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
12348 int then_not_else
= TRUE
;
12349 rtx this_insn
= start_insn
, label
= 0;
12351 /* If the jump cannot be done with one instruction, we cannot
12352 conditionally execute the instruction in the inverse case. */
12353 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
12359 /* Register the insn jumped to. */
12362 if (!seeking_return
)
12363 label
= XEXP (SET_SRC (body
), 0);
12365 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
12366 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
12367 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
12369 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
12370 then_not_else
= FALSE
;
12372 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
12373 seeking_return
= 1;
12374 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
12376 seeking_return
= 1;
12377 then_not_else
= FALSE
;
12380 gcc_unreachable ();
12382 /* See how many insns this branch skips, and what kind of insns. If all
12383 insns are okay, and the label or unconditional branch to the same
12384 label is not too far away, succeed. */
12385 for (insns_skipped
= 0;
12386 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
12390 this_insn
= next_nonnote_insn (this_insn
);
12394 switch (GET_CODE (this_insn
))
12397 /* Succeed if it is the target label, otherwise fail since
12398 control falls in from somewhere else. */
12399 if (this_insn
== label
)
12403 arm_ccfsm_state
= 2;
12404 this_insn
= next_nonnote_insn (this_insn
);
12407 arm_ccfsm_state
= 1;
12415 /* Succeed if the following insn is the target label.
12417 If return insns are used then the last insn in a function
12418 will be a barrier. */
12419 this_insn
= next_nonnote_insn (this_insn
);
12420 if (this_insn
&& this_insn
== label
)
12424 arm_ccfsm_state
= 2;
12425 this_insn
= next_nonnote_insn (this_insn
);
12428 arm_ccfsm_state
= 1;
12436 /* The AAPCS says that conditional calls should not be
12437 used since they make interworking inefficient (the
12438 linker can't transform BL<cond> into BLX). That's
12439 only a problem if the machine has BLX. */
12446 /* Succeed if the following insn is the target label, or
12447 if the following two insns are a barrier and the
12449 this_insn
= next_nonnote_insn (this_insn
);
12450 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
12451 this_insn
= next_nonnote_insn (this_insn
);
12453 if (this_insn
&& this_insn
== label
12454 && insns_skipped
< max_insns_skipped
)
12458 arm_ccfsm_state
= 2;
12459 this_insn
= next_nonnote_insn (this_insn
);
12462 arm_ccfsm_state
= 1;
12470 /* If this is an unconditional branch to the same label, succeed.
12471 If it is to another label, do nothing. If it is conditional,
12473 /* XXX Probably, the tests for SET and the PC are
12476 scanbody
= PATTERN (this_insn
);
12477 if (GET_CODE (scanbody
) == SET
12478 && GET_CODE (SET_DEST (scanbody
)) == PC
)
12480 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
12481 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
12483 arm_ccfsm_state
= 2;
12486 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
12489 /* Fail if a conditional return is undesirable (e.g. on a
12490 StrongARM), but still allow this if optimizing for size. */
12491 else if (GET_CODE (scanbody
) == RETURN
12492 && !use_return_insn (TRUE
, NULL
)
12495 else if (GET_CODE (scanbody
) == RETURN
12498 arm_ccfsm_state
= 2;
12501 else if (GET_CODE (scanbody
) == PARALLEL
)
12503 switch (get_attr_conds (this_insn
))
12513 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
12518 /* Instructions using or affecting the condition codes make it
12520 scanbody
= PATTERN (this_insn
);
12521 if (!(GET_CODE (scanbody
) == SET
12522 || GET_CODE (scanbody
) == PARALLEL
)
12523 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
12526 /* A conditional cirrus instruction must be followed by
12527 a non Cirrus instruction. However, since we
12528 conditionalize instructions in this function and by
12529 the time we get here we can't add instructions
12530 (nops), because shorten_branches() has already been
12531 called, we will disable conditionalizing Cirrus
12532 instructions to be safe. */
12533 if (GET_CODE (scanbody
) != USE
12534 && GET_CODE (scanbody
) != CLOBBER
12535 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
12545 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
12546 arm_target_label
= CODE_LABEL_NUMBER (label
);
12549 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
12551 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
12553 this_insn
= next_nonnote_insn (this_insn
);
12554 gcc_assert (!this_insn
12555 || (GET_CODE (this_insn
) != BARRIER
12556 && GET_CODE (this_insn
) != CODE_LABEL
));
12560 /* Oh, dear! we ran off the end.. give up. */
12561 extract_constrain_insn_cached (insn
);
12562 arm_ccfsm_state
= 0;
12563 arm_target_insn
= NULL
;
12566 arm_target_insn
= this_insn
;
12570 gcc_assert (!reverse
);
12572 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
12574 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
12575 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
12576 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
12577 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
12581 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
12584 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
12588 if (reverse
|| then_not_else
)
12589 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
12592 /* Restore recog_data (getting the attributes of other insns can
12593 destroy this array, but final.c assumes that it remains intact
12594 across this call. */
12595 extract_constrain_insn_cached (insn
);
12599 /* Output IT instructions. */
12601 thumb2_asm_output_opcode (FILE * stream
)
12606 if (arm_condexec_mask
)
12608 for (n
= 0; n
< arm_condexec_masklen
; n
++)
12609 buff
[n
] = (arm_condexec_mask
& (1 << n
)) ? 't' : 'e';
12611 asm_fprintf(stream
, "i%s\t%s\n\t", buff
,
12612 arm_condition_codes
[arm_current_cc
]);
12613 arm_condexec_mask
= 0;
12617 /* Returns true if REGNO is a valid register
12618 for holding a quantity of type MODE. */
12620 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
12622 if (GET_MODE_CLASS (mode
) == MODE_CC
)
12623 return (regno
== CC_REGNUM
12624 || (TARGET_HARD_FLOAT
&& TARGET_VFP
12625 && regno
== VFPCC_REGNUM
));
12628 /* For the Thumb we only allow values bigger than SImode in
12629 registers 0 - 6, so that there is always a second low
12630 register available to hold the upper part of the value.
12631 We probably we ought to ensure that the register is the
12632 start of an even numbered register pair. */
12633 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
12635 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
12636 && IS_CIRRUS_REGNUM (regno
))
12637 /* We have outlawed SI values in Cirrus registers because they
12638 reside in the lower 32 bits, but SF values reside in the
12639 upper 32 bits. This causes gcc all sorts of grief. We can't
12640 even split the registers into pairs because Cirrus SI values
12641 get sign extended to 64bits-- aldyh. */
12642 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
12644 if (TARGET_HARD_FLOAT
&& TARGET_VFP
12645 && IS_VFP_REGNUM (regno
))
12647 if (mode
== SFmode
|| mode
== SImode
)
12650 /* DFmode values are only valid in even register pairs. */
12651 if (mode
== DFmode
)
12652 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
12656 if (TARGET_REALLY_IWMMXT
)
12658 if (IS_IWMMXT_GR_REGNUM (regno
))
12659 return mode
== SImode
;
12661 if (IS_IWMMXT_REGNUM (regno
))
12662 return VALID_IWMMXT_REG_MODE (mode
);
12665 /* We allow any value to be stored in the general registers.
12666 Restrict doubleword quantities to even register pairs so that we can
12668 if (regno
<= LAST_ARM_REGNUM
)
12669 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
12671 if (regno
== FRAME_POINTER_REGNUM
12672 || regno
== ARG_POINTER_REGNUM
)
12673 /* We only allow integers in the fake hard registers. */
12674 return GET_MODE_CLASS (mode
) == MODE_INT
;
12676 /* The only registers left are the FPA registers
12677 which we only allow to hold FP values. */
12678 return (TARGET_HARD_FLOAT
&& TARGET_FPA
12679 && GET_MODE_CLASS (mode
) == MODE_FLOAT
12680 && regno
>= FIRST_FPA_REGNUM
12681 && regno
<= LAST_FPA_REGNUM
);
12684 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
12685 not used in arm mode. */
12687 arm_regno_class (int regno
)
12691 if (regno
== STACK_POINTER_REGNUM
)
12693 if (regno
== CC_REGNUM
)
12700 if (TARGET_THUMB2
&& regno
< 8)
12703 if ( regno
<= LAST_ARM_REGNUM
12704 || regno
== FRAME_POINTER_REGNUM
12705 || regno
== ARG_POINTER_REGNUM
)
12706 return TARGET_THUMB2
? HI_REGS
: GENERAL_REGS
;
12708 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
12709 return TARGET_THUMB2
? CC_REG
: NO_REGS
;
12711 if (IS_CIRRUS_REGNUM (regno
))
12712 return CIRRUS_REGS
;
12714 if (IS_VFP_REGNUM (regno
))
12717 if (IS_IWMMXT_REGNUM (regno
))
12718 return IWMMXT_REGS
;
12720 if (IS_IWMMXT_GR_REGNUM (regno
))
12721 return IWMMXT_GR_REGS
;
12726 /* Handle a special case when computing the offset
12727 of an argument from the frame pointer. */
12729 arm_debugger_arg_offset (int value
, rtx addr
)
12733 /* We are only interested if dbxout_parms() failed to compute the offset. */
12737 /* We can only cope with the case where the address is held in a register. */
12738 if (GET_CODE (addr
) != REG
)
12741 /* If we are using the frame pointer to point at the argument, then
12742 an offset of 0 is correct. */
12743 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
12746 /* If we are using the stack pointer to point at the
12747 argument, then an offset of 0 is correct. */
12748 /* ??? Check this is consistent with thumb2 frame layout. */
12749 if ((TARGET_THUMB
|| !frame_pointer_needed
)
12750 && REGNO (addr
) == SP_REGNUM
)
12753 /* Oh dear. The argument is pointed to by a register rather
12754 than being held in a register, or being stored at a known
12755 offset from the frame pointer. Since GDB only understands
12756 those two kinds of argument we must translate the address
12757 held in the register into an offset from the frame pointer.
12758 We do this by searching through the insns for the function
12759 looking to see where this register gets its value. If the
12760 register is initialized from the frame pointer plus an offset
12761 then we are in luck and we can continue, otherwise we give up.
12763 This code is exercised by producing debugging information
12764 for a function with arguments like this:
12766 double func (double a, double b, int c, double d) {return d;}
12768 Without this code the stab for parameter 'd' will be set to
12769 an offset of 0 from the frame pointer, rather than 8. */
12771 /* The if() statement says:
12773 If the insn is a normal instruction
12774 and if the insn is setting the value in a register
12775 and if the register being set is the register holding the address of the argument
12776 and if the address is computing by an addition
12777 that involves adding to a register
12778 which is the frame pointer
12783 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12785 if ( GET_CODE (insn
) == INSN
12786 && GET_CODE (PATTERN (insn
)) == SET
12787 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
12788 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
12789 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
12790 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12791 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
12794 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
12803 warning (0, "unable to compute real location of stacked parameter");
12804 value
= 8; /* XXX magic hack */
12810 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12813 if ((MASK) & insn_flags) \
12814 add_builtin_function ((NAME), (TYPE), (CODE), \
12815 BUILT_IN_MD, NULL, NULL_TREE); \
12819 struct builtin_description
12821 const unsigned int mask
;
12822 const enum insn_code icode
;
12823 const char * const name
;
12824 const enum arm_builtins code
;
12825 const enum rtx_code comparison
;
12826 const unsigned int flag
;
12829 static const struct builtin_description bdesc_2arg
[] =
12831 #define IWMMXT_BUILTIN(code, string, builtin) \
12832 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12833 ARM_BUILTIN_##builtin, 0, 0 },
12835 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12836 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12837 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12838 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12839 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12840 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12841 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12842 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12843 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12844 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12845 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12846 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12847 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12848 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12849 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12850 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12851 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12852 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12853 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12854 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12855 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12856 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12857 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12858 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12859 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12860 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12861 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12862 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12863 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12864 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12865 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12866 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12867 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12868 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12869 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12870 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12871 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12872 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12873 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12874 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12875 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12876 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12877 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12878 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12879 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12880 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12881 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12882 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12883 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12884 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12885 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12886 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12887 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12888 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12889 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12890 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12891 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12892 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12894 #define IWMMXT_BUILTIN2(code, builtin) \
12895 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12897 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12898 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12899 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12900 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12901 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12902 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12903 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12904 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12905 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12906 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12907 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12908 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12909 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12910 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12911 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12912 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12913 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12914 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12915 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12916 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12917 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12918 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12919 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12920 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12921 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12922 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12923 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12924 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12925 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12926 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12927 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12928 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12931 static const struct builtin_description bdesc_1arg
[] =
12933 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12934 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12935 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12936 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12937 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12938 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12939 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12940 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12941 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12942 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12943 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12944 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12945 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12946 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12947 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12948 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12949 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12950 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12953 /* Set up all the iWMMXt builtins. This is
12954 not called if TARGET_IWMMXT is zero. */
12957 arm_init_iwmmxt_builtins (void)
12959 const struct builtin_description
* d
;
12961 tree endlink
= void_list_node
;
12963 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12964 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12965 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12968 = build_function_type (integer_type_node
,
12969 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12970 tree v8qi_ftype_v8qi_v8qi_int
12971 = build_function_type (V8QI_type_node
,
12972 tree_cons (NULL_TREE
, V8QI_type_node
,
12973 tree_cons (NULL_TREE
, V8QI_type_node
,
12974 tree_cons (NULL_TREE
,
12977 tree v4hi_ftype_v4hi_int
12978 = build_function_type (V4HI_type_node
,
12979 tree_cons (NULL_TREE
, V4HI_type_node
,
12980 tree_cons (NULL_TREE
, integer_type_node
,
12982 tree v2si_ftype_v2si_int
12983 = build_function_type (V2SI_type_node
,
12984 tree_cons (NULL_TREE
, V2SI_type_node
,
12985 tree_cons (NULL_TREE
, integer_type_node
,
12987 tree v2si_ftype_di_di
12988 = build_function_type (V2SI_type_node
,
12989 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12990 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12992 tree di_ftype_di_int
12993 = build_function_type (long_long_integer_type_node
,
12994 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12995 tree_cons (NULL_TREE
, integer_type_node
,
12997 tree di_ftype_di_int_int
12998 = build_function_type (long_long_integer_type_node
,
12999 tree_cons (NULL_TREE
, long_long_integer_type_node
,
13000 tree_cons (NULL_TREE
, integer_type_node
,
13001 tree_cons (NULL_TREE
,
13004 tree int_ftype_v8qi
13005 = build_function_type (integer_type_node
,
13006 tree_cons (NULL_TREE
, V8QI_type_node
,
13008 tree int_ftype_v4hi
13009 = build_function_type (integer_type_node
,
13010 tree_cons (NULL_TREE
, V4HI_type_node
,
13012 tree int_ftype_v2si
13013 = build_function_type (integer_type_node
,
13014 tree_cons (NULL_TREE
, V2SI_type_node
,
13016 tree int_ftype_v8qi_int
13017 = build_function_type (integer_type_node
,
13018 tree_cons (NULL_TREE
, V8QI_type_node
,
13019 tree_cons (NULL_TREE
, integer_type_node
,
13021 tree int_ftype_v4hi_int
13022 = build_function_type (integer_type_node
,
13023 tree_cons (NULL_TREE
, V4HI_type_node
,
13024 tree_cons (NULL_TREE
, integer_type_node
,
13026 tree int_ftype_v2si_int
13027 = build_function_type (integer_type_node
,
13028 tree_cons (NULL_TREE
, V2SI_type_node
,
13029 tree_cons (NULL_TREE
, integer_type_node
,
13031 tree v8qi_ftype_v8qi_int_int
13032 = build_function_type (V8QI_type_node
,
13033 tree_cons (NULL_TREE
, V8QI_type_node
,
13034 tree_cons (NULL_TREE
, integer_type_node
,
13035 tree_cons (NULL_TREE
,
13038 tree v4hi_ftype_v4hi_int_int
13039 = build_function_type (V4HI_type_node
,
13040 tree_cons (NULL_TREE
, V4HI_type_node
,
13041 tree_cons (NULL_TREE
, integer_type_node
,
13042 tree_cons (NULL_TREE
,
13045 tree v2si_ftype_v2si_int_int
13046 = build_function_type (V2SI_type_node
,
13047 tree_cons (NULL_TREE
, V2SI_type_node
,
13048 tree_cons (NULL_TREE
, integer_type_node
,
13049 tree_cons (NULL_TREE
,
13052 /* Miscellaneous. */
13053 tree v8qi_ftype_v4hi_v4hi
13054 = build_function_type (V8QI_type_node
,
13055 tree_cons (NULL_TREE
, V4HI_type_node
,
13056 tree_cons (NULL_TREE
, V4HI_type_node
,
13058 tree v4hi_ftype_v2si_v2si
13059 = build_function_type (V4HI_type_node
,
13060 tree_cons (NULL_TREE
, V2SI_type_node
,
13061 tree_cons (NULL_TREE
, V2SI_type_node
,
13063 tree v2si_ftype_v4hi_v4hi
13064 = build_function_type (V2SI_type_node
,
13065 tree_cons (NULL_TREE
, V4HI_type_node
,
13066 tree_cons (NULL_TREE
, V4HI_type_node
,
13068 tree v2si_ftype_v8qi_v8qi
13069 = build_function_type (V2SI_type_node
,
13070 tree_cons (NULL_TREE
, V8QI_type_node
,
13071 tree_cons (NULL_TREE
, V8QI_type_node
,
13073 tree v4hi_ftype_v4hi_di
13074 = build_function_type (V4HI_type_node
,
13075 tree_cons (NULL_TREE
, V4HI_type_node
,
13076 tree_cons (NULL_TREE
,
13077 long_long_integer_type_node
,
13079 tree v2si_ftype_v2si_di
13080 = build_function_type (V2SI_type_node
,
13081 tree_cons (NULL_TREE
, V2SI_type_node
,
13082 tree_cons (NULL_TREE
,
13083 long_long_integer_type_node
,
13085 tree void_ftype_int_int
13086 = build_function_type (void_type_node
,
13087 tree_cons (NULL_TREE
, integer_type_node
,
13088 tree_cons (NULL_TREE
, integer_type_node
,
13091 = build_function_type (long_long_unsigned_type_node
, endlink
);
13093 = build_function_type (long_long_integer_type_node
,
13094 tree_cons (NULL_TREE
, V8QI_type_node
,
13097 = build_function_type (long_long_integer_type_node
,
13098 tree_cons (NULL_TREE
, V4HI_type_node
,
13101 = build_function_type (long_long_integer_type_node
,
13102 tree_cons (NULL_TREE
, V2SI_type_node
,
13104 tree v2si_ftype_v4hi
13105 = build_function_type (V2SI_type_node
,
13106 tree_cons (NULL_TREE
, V4HI_type_node
,
13108 tree v4hi_ftype_v8qi
13109 = build_function_type (V4HI_type_node
,
13110 tree_cons (NULL_TREE
, V8QI_type_node
,
13113 tree di_ftype_di_v4hi_v4hi
13114 = build_function_type (long_long_unsigned_type_node
,
13115 tree_cons (NULL_TREE
,
13116 long_long_unsigned_type_node
,
13117 tree_cons (NULL_TREE
, V4HI_type_node
,
13118 tree_cons (NULL_TREE
,
13122 tree di_ftype_v4hi_v4hi
13123 = build_function_type (long_long_unsigned_type_node
,
13124 tree_cons (NULL_TREE
, V4HI_type_node
,
13125 tree_cons (NULL_TREE
, V4HI_type_node
,
13128 /* Normal vector binops. */
13129 tree v8qi_ftype_v8qi_v8qi
13130 = build_function_type (V8QI_type_node
,
13131 tree_cons (NULL_TREE
, V8QI_type_node
,
13132 tree_cons (NULL_TREE
, V8QI_type_node
,
13134 tree v4hi_ftype_v4hi_v4hi
13135 = build_function_type (V4HI_type_node
,
13136 tree_cons (NULL_TREE
, V4HI_type_node
,
13137 tree_cons (NULL_TREE
, V4HI_type_node
,
13139 tree v2si_ftype_v2si_v2si
13140 = build_function_type (V2SI_type_node
,
13141 tree_cons (NULL_TREE
, V2SI_type_node
,
13142 tree_cons (NULL_TREE
, V2SI_type_node
,
13144 tree di_ftype_di_di
13145 = build_function_type (long_long_unsigned_type_node
,
13146 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
13147 tree_cons (NULL_TREE
,
13148 long_long_unsigned_type_node
,
13151 /* Add all builtins that are more or less simple operations on two
13153 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13155 /* Use one of the operands; the target can have a different mode for
13156 mask-generating compares. */
13157 enum machine_mode mode
;
13163 mode
= insn_data
[d
->icode
].operand
[1].mode
;
13168 type
= v8qi_ftype_v8qi_v8qi
;
13171 type
= v4hi_ftype_v4hi_v4hi
;
13174 type
= v2si_ftype_v2si_v2si
;
13177 type
= di_ftype_di_di
;
13181 gcc_unreachable ();
13184 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
13187 /* Add the remaining MMX insns with somewhat more complicated types. */
13188 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
13189 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
13190 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
13192 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
13193 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
13194 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
13195 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
13196 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
13197 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
13199 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
13200 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
13201 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
13202 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
13203 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
13204 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
13206 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
13207 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
13208 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
13209 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
13210 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
13211 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
13213 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
13214 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
13215 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
13216 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
13217 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
13218 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
13220 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
13222 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
13223 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
13224 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
13225 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
13227 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
13228 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
13229 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
13230 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
13231 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
13232 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
13233 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
13234 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
13235 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
13237 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
13238 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
13239 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
13241 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
13242 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
13243 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
13245 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
13246 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
13247 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
13248 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
13249 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
13250 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
13252 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
13253 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
13254 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
13255 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
13256 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
13257 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
13258 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
13259 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
13260 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
13261 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
13262 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
13263 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
13265 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
13266 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
13267 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
13268 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
13270 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
13271 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
13272 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
13273 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
13274 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
13275 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
13276 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
13280 arm_init_tls_builtins (void)
13283 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
13284 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
13286 ftype
= build_function_type (ptr_type_node
, void_list_node
);
13287 add_builtin_function ("__builtin_thread_pointer", ftype
,
13288 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
13289 NULL
, const_nothrow
);
13293 arm_init_builtins (void)
13295 arm_init_tls_builtins ();
13297 if (TARGET_REALLY_IWMMXT
)
13298 arm_init_iwmmxt_builtins ();
13301 /* Errors in the source file can cause expand_expr to return const0_rtx
13302 where we expect a vector. To avoid crashing, use one of the vector
13303 clear instructions. */
13306 safe_vector_operand (rtx x
, enum machine_mode mode
)
13308 if (x
!= const0_rtx
)
13310 x
= gen_reg_rtx (mode
);
13312 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
13313 : gen_rtx_SUBREG (DImode
, x
, 0)));
13317 /* Subroutine of arm_expand_builtin to take care of binop insns. */
13320 arm_expand_binop_builtin (enum insn_code icode
,
13321 tree arglist
, rtx target
)
13324 tree arg0
= TREE_VALUE (arglist
);
13325 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13326 rtx op0
= expand_normal (arg0
);
13327 rtx op1
= expand_normal (arg1
);
13328 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13329 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13330 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13332 if (VECTOR_MODE_P (mode0
))
13333 op0
= safe_vector_operand (op0
, mode0
);
13334 if (VECTOR_MODE_P (mode1
))
13335 op1
= safe_vector_operand (op1
, mode1
);
13338 || GET_MODE (target
) != tmode
13339 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13340 target
= gen_reg_rtx (tmode
);
13342 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
13344 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13345 op0
= copy_to_mode_reg (mode0
, op0
);
13346 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13347 op1
= copy_to_mode_reg (mode1
, op1
);
13349 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13356 /* Subroutine of arm_expand_builtin to take care of unop insns. */
13359 arm_expand_unop_builtin (enum insn_code icode
,
13360 tree arglist
, rtx target
, int do_load
)
13363 tree arg0
= TREE_VALUE (arglist
);
13364 rtx op0
= expand_normal (arg0
);
13365 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13366 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13369 || GET_MODE (target
) != tmode
13370 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13371 target
= gen_reg_rtx (tmode
);
13373 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13376 if (VECTOR_MODE_P (mode0
))
13377 op0
= safe_vector_operand (op0
, mode0
);
13379 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13380 op0
= copy_to_mode_reg (mode0
, op0
);
13383 pat
= GEN_FCN (icode
) (target
, op0
);
13390 /* Expand an expression EXP that calls a built-in function,
13391 with result going to TARGET if that's convenient
13392 (and in mode MODE if that's convenient).
13393 SUBTARGET may be used as the target for computing one of EXP's operands.
13394 IGNORE is nonzero if the value is to be ignored. */
13397 arm_expand_builtin (tree exp
,
13399 rtx subtarget ATTRIBUTE_UNUSED
,
13400 enum machine_mode mode ATTRIBUTE_UNUSED
,
13401 int ignore ATTRIBUTE_UNUSED
)
13403 const struct builtin_description
* d
;
13404 enum insn_code icode
;
13405 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
13406 tree arglist
= TREE_OPERAND (exp
, 1);
13414 int fcode
= DECL_FUNCTION_CODE (fndecl
);
13416 enum machine_mode tmode
;
13417 enum machine_mode mode0
;
13418 enum machine_mode mode1
;
13419 enum machine_mode mode2
;
13423 case ARM_BUILTIN_TEXTRMSB
:
13424 case ARM_BUILTIN_TEXTRMUB
:
13425 case ARM_BUILTIN_TEXTRMSH
:
13426 case ARM_BUILTIN_TEXTRMUH
:
13427 case ARM_BUILTIN_TEXTRMSW
:
13428 case ARM_BUILTIN_TEXTRMUW
:
13429 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
13430 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
13431 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
13432 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
13433 : CODE_FOR_iwmmxt_textrmw
);
13435 arg0
= TREE_VALUE (arglist
);
13436 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13437 op0
= expand_normal (arg0
);
13438 op1
= expand_normal (arg1
);
13439 tmode
= insn_data
[icode
].operand
[0].mode
;
13440 mode0
= insn_data
[icode
].operand
[1].mode
;
13441 mode1
= insn_data
[icode
].operand
[2].mode
;
13443 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13444 op0
= copy_to_mode_reg (mode0
, op0
);
13445 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13447 /* @@@ better error message */
13448 error ("selector must be an immediate");
13449 return gen_reg_rtx (tmode
);
13452 || GET_MODE (target
) != tmode
13453 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13454 target
= gen_reg_rtx (tmode
);
13455 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13461 case ARM_BUILTIN_TINSRB
:
13462 case ARM_BUILTIN_TINSRH
:
13463 case ARM_BUILTIN_TINSRW
:
13464 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
13465 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
13466 : CODE_FOR_iwmmxt_tinsrw
);
13467 arg0
= TREE_VALUE (arglist
);
13468 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13469 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13470 op0
= expand_normal (arg0
);
13471 op1
= expand_normal (arg1
);
13472 op2
= expand_normal (arg2
);
13473 tmode
= insn_data
[icode
].operand
[0].mode
;
13474 mode0
= insn_data
[icode
].operand
[1].mode
;
13475 mode1
= insn_data
[icode
].operand
[2].mode
;
13476 mode2
= insn_data
[icode
].operand
[3].mode
;
13478 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13479 op0
= copy_to_mode_reg (mode0
, op0
);
13480 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13481 op1
= copy_to_mode_reg (mode1
, op1
);
13482 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13484 /* @@@ better error message */
13485 error ("selector must be an immediate");
13489 || GET_MODE (target
) != tmode
13490 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13491 target
= gen_reg_rtx (tmode
);
13492 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13498 case ARM_BUILTIN_SETWCX
:
13499 arg0
= TREE_VALUE (arglist
);
13500 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13501 op0
= force_reg (SImode
, expand_normal (arg0
));
13502 op1
= expand_normal (arg1
);
13503 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
13506 case ARM_BUILTIN_GETWCX
:
13507 arg0
= TREE_VALUE (arglist
);
13508 op0
= expand_normal (arg0
);
13509 target
= gen_reg_rtx (SImode
);
13510 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
13513 case ARM_BUILTIN_WSHUFH
:
13514 icode
= CODE_FOR_iwmmxt_wshufh
;
13515 arg0
= TREE_VALUE (arglist
);
13516 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13517 op0
= expand_normal (arg0
);
13518 op1
= expand_normal (arg1
);
13519 tmode
= insn_data
[icode
].operand
[0].mode
;
13520 mode1
= insn_data
[icode
].operand
[1].mode
;
13521 mode2
= insn_data
[icode
].operand
[2].mode
;
13523 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
13524 op0
= copy_to_mode_reg (mode1
, op0
);
13525 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
13527 /* @@@ better error message */
13528 error ("mask must be an immediate");
13532 || GET_MODE (target
) != tmode
13533 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13534 target
= gen_reg_rtx (tmode
);
13535 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13541 case ARM_BUILTIN_WSADB
:
13542 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
13543 case ARM_BUILTIN_WSADH
:
13544 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
13545 case ARM_BUILTIN_WSADBZ
:
13546 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
13547 case ARM_BUILTIN_WSADHZ
:
13548 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
13550 /* Several three-argument builtins. */
13551 case ARM_BUILTIN_WMACS
:
13552 case ARM_BUILTIN_WMACU
:
13553 case ARM_BUILTIN_WALIGN
:
13554 case ARM_BUILTIN_TMIA
:
13555 case ARM_BUILTIN_TMIAPH
:
13556 case ARM_BUILTIN_TMIATT
:
13557 case ARM_BUILTIN_TMIATB
:
13558 case ARM_BUILTIN_TMIABT
:
13559 case ARM_BUILTIN_TMIABB
:
13560 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
13561 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
13562 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
13563 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
13564 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
13565 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
13566 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
13567 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
13568 : CODE_FOR_iwmmxt_walign
);
13569 arg0
= TREE_VALUE (arglist
);
13570 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13571 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13572 op0
= expand_normal (arg0
);
13573 op1
= expand_normal (arg1
);
13574 op2
= expand_normal (arg2
);
13575 tmode
= insn_data
[icode
].operand
[0].mode
;
13576 mode0
= insn_data
[icode
].operand
[1].mode
;
13577 mode1
= insn_data
[icode
].operand
[2].mode
;
13578 mode2
= insn_data
[icode
].operand
[3].mode
;
13580 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13581 op0
= copy_to_mode_reg (mode0
, op0
);
13582 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13583 op1
= copy_to_mode_reg (mode1
, op1
);
13584 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13585 op2
= copy_to_mode_reg (mode2
, op2
);
13587 || GET_MODE (target
) != tmode
13588 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13589 target
= gen_reg_rtx (tmode
);
13590 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13596 case ARM_BUILTIN_WZERO
:
13597 target
= gen_reg_rtx (DImode
);
13598 emit_insn (gen_iwmmxt_clrdi (target
));
13601 case ARM_BUILTIN_THREAD_POINTER
:
13602 return arm_load_tp (target
);
13608 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13609 if (d
->code
== (const enum arm_builtins
) fcode
)
13610 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
13612 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13613 if (d
->code
== (const enum arm_builtins
) fcode
)
13614 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
13616 /* @@@ Should really do something sensible here. */
13620 /* Return the number (counting from 0) of
13621 the least significant set bit in MASK. */
13624 number_of_first_bit_set (unsigned mask
)
13629 (mask
& (1 << bit
)) == 0;
13636 /* Emit code to push or pop registers to or from the stack. F is the
13637 assembly file. MASK is the registers to push or pop. PUSH is
13638 nonzero if we should push, and zero if we should pop. For debugging
13639 output, if pushing, adjust CFA_OFFSET by the amount of space added
13640 to the stack. REAL_REGS should have the same number of bits set as
13641 MASK, and will be used instead (in the same order) to describe which
13642 registers were saved - this is used to mark the save slots when we
13643 push high registers after moving them to low registers. */
13645 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
13646 unsigned long real_regs
)
13649 int lo_mask
= mask
& 0xFF;
13650 int pushed_words
= 0;
13654 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
13656 /* Special case. Do not generate a POP PC statement here, do it in
13658 thumb_exit (f
, -1);
13662 if (ARM_EABI_UNWIND_TABLES
&& push
)
13664 fprintf (f
, "\t.save\t{");
13665 for (regno
= 0; regno
< 15; regno
++)
13667 if (real_regs
& (1 << regno
))
13669 if (real_regs
& ((1 << regno
) -1))
13671 asm_fprintf (f
, "%r", regno
);
13674 fprintf (f
, "}\n");
13677 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
13679 /* Look at the low registers first. */
13680 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
13684 asm_fprintf (f
, "%r", regno
);
13686 if ((lo_mask
& ~1) != 0)
13693 if (push
&& (mask
& (1 << LR_REGNUM
)))
13695 /* Catch pushing the LR. */
13699 asm_fprintf (f
, "%r", LR_REGNUM
);
13703 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
13705 /* Catch popping the PC. */
13706 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
13707 || current_function_calls_eh_return
)
13709 /* The PC is never poped directly, instead
13710 it is popped into r3 and then BX is used. */
13711 fprintf (f
, "}\n");
13713 thumb_exit (f
, -1);
13722 asm_fprintf (f
, "%r", PC_REGNUM
);
13726 fprintf (f
, "}\n");
13728 if (push
&& pushed_words
&& dwarf2out_do_frame ())
13730 char *l
= dwarf2out_cfi_label ();
13731 int pushed_mask
= real_regs
;
13733 *cfa_offset
+= pushed_words
* 4;
13734 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
13737 pushed_mask
= real_regs
;
13738 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
13740 if (pushed_mask
& 1)
13741 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
13746 /* Generate code to return from a thumb function.
13747 If 'reg_containing_return_addr' is -1, then the return address is
13748 actually on the stack, at the stack pointer. */
13750 thumb_exit (FILE *f
, int reg_containing_return_addr
)
13752 unsigned regs_available_for_popping
;
13753 unsigned regs_to_pop
;
13755 unsigned available
;
13759 int restore_a4
= FALSE
;
13761 /* Compute the registers we need to pop. */
13765 if (reg_containing_return_addr
== -1)
13767 regs_to_pop
|= 1 << LR_REGNUM
;
13771 if (TARGET_BACKTRACE
)
13773 /* Restore the (ARM) frame pointer and stack pointer. */
13774 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
13778 /* If there is nothing to pop then just emit the BX instruction and
13780 if (pops_needed
== 0)
13782 if (current_function_calls_eh_return
)
13783 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13785 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13788 /* Otherwise if we are not supporting interworking and we have not created
13789 a backtrace structure and the function was not entered in ARM mode then
13790 just pop the return address straight into the PC. */
13791 else if (!TARGET_INTERWORK
13792 && !TARGET_BACKTRACE
13793 && !is_called_in_ARM_mode (current_function_decl
)
13794 && !current_function_calls_eh_return
)
13796 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
13800 /* Find out how many of the (return) argument registers we can corrupt. */
13801 regs_available_for_popping
= 0;
13803 /* If returning via __builtin_eh_return, the bottom three registers
13804 all contain information needed for the return. */
13805 if (current_function_calls_eh_return
)
13809 /* If we can deduce the registers used from the function's
13810 return value. This is more reliable that examining
13811 regs_ever_live[] because that will be set if the register is
13812 ever used in the function, not just if the register is used
13813 to hold a return value. */
13815 if (current_function_return_rtx
!= 0)
13816 mode
= GET_MODE (current_function_return_rtx
);
13818 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13820 size
= GET_MODE_SIZE (mode
);
13824 /* In a void function we can use any argument register.
13825 In a function that returns a structure on the stack
13826 we can use the second and third argument registers. */
13827 if (mode
== VOIDmode
)
13828 regs_available_for_popping
=
13829 (1 << ARG_REGISTER (1))
13830 | (1 << ARG_REGISTER (2))
13831 | (1 << ARG_REGISTER (3));
13833 regs_available_for_popping
=
13834 (1 << ARG_REGISTER (2))
13835 | (1 << ARG_REGISTER (3));
13837 else if (size
<= 4)
13838 regs_available_for_popping
=
13839 (1 << ARG_REGISTER (2))
13840 | (1 << ARG_REGISTER (3));
13841 else if (size
<= 8)
13842 regs_available_for_popping
=
13843 (1 << ARG_REGISTER (3));
13846 /* Match registers to be popped with registers into which we pop them. */
13847 for (available
= regs_available_for_popping
,
13848 required
= regs_to_pop
;
13849 required
!= 0 && available
!= 0;
13850 available
&= ~(available
& - available
),
13851 required
&= ~(required
& - required
))
13854 /* If we have any popping registers left over, remove them. */
13856 regs_available_for_popping
&= ~available
;
13858 /* Otherwise if we need another popping register we can use
13859 the fourth argument register. */
13860 else if (pops_needed
)
13862 /* If we have not found any free argument registers and
13863 reg a4 contains the return address, we must move it. */
13864 if (regs_available_for_popping
== 0
13865 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13867 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13868 reg_containing_return_addr
= LR_REGNUM
;
13870 else if (size
> 12)
13872 /* Register a4 is being used to hold part of the return value,
13873 but we have dire need of a free, low register. */
13876 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13879 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13881 /* The fourth argument register is available. */
13882 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13888 /* Pop as many registers as we can. */
13889 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13890 regs_available_for_popping
);
13892 /* Process the registers we popped. */
13893 if (reg_containing_return_addr
== -1)
13895 /* The return address was popped into the lowest numbered register. */
13896 regs_to_pop
&= ~(1 << LR_REGNUM
);
13898 reg_containing_return_addr
=
13899 number_of_first_bit_set (regs_available_for_popping
);
13901 /* Remove this register for the mask of available registers, so that
13902 the return address will not be corrupted by further pops. */
13903 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13906 /* If we popped other registers then handle them here. */
13907 if (regs_available_for_popping
)
13911 /* Work out which register currently contains the frame pointer. */
13912 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13914 /* Move it into the correct place. */
13915 asm_fprintf (f
, "\tmov\t%r, %r\n",
13916 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13918 /* (Temporarily) remove it from the mask of popped registers. */
13919 regs_available_for_popping
&= ~(1 << frame_pointer
);
13920 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13922 if (regs_available_for_popping
)
13926 /* We popped the stack pointer as well,
13927 find the register that contains it. */
13928 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13930 /* Move it into the stack register. */
13931 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13933 /* At this point we have popped all necessary registers, so
13934 do not worry about restoring regs_available_for_popping
13935 to its correct value:
13937 assert (pops_needed == 0)
13938 assert (regs_available_for_popping == (1 << frame_pointer))
13939 assert (regs_to_pop == (1 << STACK_POINTER)) */
13943 /* Since we have just move the popped value into the frame
13944 pointer, the popping register is available for reuse, and
13945 we know that we still have the stack pointer left to pop. */
13946 regs_available_for_popping
|= (1 << frame_pointer
);
13950 /* If we still have registers left on the stack, but we no longer have
13951 any registers into which we can pop them, then we must move the return
13952 address into the link register and make available the register that
13954 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13956 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13958 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13959 reg_containing_return_addr
);
13961 reg_containing_return_addr
= LR_REGNUM
;
13964 /* If we have registers left on the stack then pop some more.
13965 We know that at most we will want to pop FP and SP. */
13966 if (pops_needed
> 0)
13971 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13972 regs_available_for_popping
);
13974 /* We have popped either FP or SP.
13975 Move whichever one it is into the correct register. */
13976 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13977 move_to
= number_of_first_bit_set (regs_to_pop
);
13979 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13981 regs_to_pop
&= ~(1 << move_to
);
13986 /* If we still have not popped everything then we must have only
13987 had one register available to us and we are now popping the SP. */
13988 if (pops_needed
> 0)
13992 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13993 regs_available_for_popping
);
13995 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13997 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13999 assert (regs_to_pop == (1 << STACK_POINTER))
14000 assert (pops_needed == 1)
14004 /* If necessary restore the a4 register. */
14007 if (reg_containing_return_addr
!= LR_REGNUM
)
14009 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
14010 reg_containing_return_addr
= LR_REGNUM
;
14013 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
14016 if (current_function_calls_eh_return
)
14017 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
14019 /* Return to caller. */
14020 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
14025 thumb1_final_prescan_insn (rtx insn
)
14027 if (flag_print_asm_name
)
14028 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
14029 INSN_ADDRESSES (INSN_UID (insn
)));
14033 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
14035 unsigned HOST_WIDE_INT mask
= 0xff;
14038 if (val
== 0) /* XXX */
14041 for (i
= 0; i
< 25; i
++)
14042 if ((val
& (mask
<< i
)) == val
)
14048 /* Returns nonzero if the current function contains,
14049 or might contain a far jump. */
14051 thumb_far_jump_used_p (void)
14055 /* This test is only important for leaf functions. */
14056 /* assert (!leaf_function_p ()); */
14058 /* If we have already decided that far jumps may be used,
14059 do not bother checking again, and always return true even if
14060 it turns out that they are not being used. Once we have made
14061 the decision that far jumps are present (and that hence the link
14062 register will be pushed onto the stack) we cannot go back on it. */
14063 if (cfun
->machine
->far_jump_used
)
14066 /* If this function is not being called from the prologue/epilogue
14067 generation code then it must be being called from the
14068 INITIAL_ELIMINATION_OFFSET macro. */
14069 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
14071 /* In this case we know that we are being asked about the elimination
14072 of the arg pointer register. If that register is not being used,
14073 then there are no arguments on the stack, and we do not have to
14074 worry that a far jump might force the prologue to push the link
14075 register, changing the stack offsets. In this case we can just
14076 return false, since the presence of far jumps in the function will
14077 not affect stack offsets.
14079 If the arg pointer is live (or if it was live, but has now been
14080 eliminated and so set to dead) then we do have to test to see if
14081 the function might contain a far jump. This test can lead to some
14082 false negatives, since before reload is completed, then length of
14083 branch instructions is not known, so gcc defaults to returning their
14084 longest length, which in turn sets the far jump attribute to true.
14086 A false negative will not result in bad code being generated, but it
14087 will result in a needless push and pop of the link register. We
14088 hope that this does not occur too often.
14090 If we need doubleword stack alignment this could affect the other
14091 elimination offsets so we can't risk getting it wrong. */
14092 if (regs_ever_live
[ARG_POINTER_REGNUM
])
14093 cfun
->machine
->arg_pointer_live
= 1;
14094 else if (!cfun
->machine
->arg_pointer_live
)
14098 /* Check to see if the function contains a branch
14099 insn with the far jump attribute set. */
14100 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14102 if (GET_CODE (insn
) == JUMP_INSN
14103 /* Ignore tablejump patterns. */
14104 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
14105 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
14106 && get_attr_far_jump (insn
) == FAR_JUMP_YES
14109 /* Record the fact that we have decided that
14110 the function does use far jumps. */
14111 cfun
->machine
->far_jump_used
= 1;
14119 /* Return nonzero if FUNC must be entered in ARM mode. */
14121 is_called_in_ARM_mode (tree func
)
14123 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
14125 /* Ignore the problem about functions whose address is taken. */
14126 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
14130 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
14136 /* The bits which aren't usefully expanded as rtl. */
14138 thumb_unexpanded_epilogue (void)
14141 unsigned long live_regs_mask
= 0;
14142 int high_regs_pushed
= 0;
14143 int had_to_push_lr
;
14146 if (return_used_this_function
)
14149 if (IS_NAKED (arm_current_func_type ()))
14152 live_regs_mask
= thumb1_compute_save_reg_mask ();
14153 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
14155 /* If we can deduce the registers used from the function's return value.
14156 This is more reliable that examining regs_ever_live[] because that
14157 will be set if the register is ever used in the function, not just if
14158 the register is used to hold a return value. */
14159 size
= arm_size_return_regs ();
14161 /* The prolog may have pushed some high registers to use as
14162 work registers. e.g. the testsuite file:
14163 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
14164 compiles to produce:
14165 push {r4, r5, r6, r7, lr}
14169 as part of the prolog. We have to undo that pushing here. */
14171 if (high_regs_pushed
)
14173 unsigned long mask
= live_regs_mask
& 0xff;
14176 /* The available low registers depend on the size of the value we are
14184 /* Oh dear! We have no low registers into which we can pop
14187 ("no low registers available for popping high registers");
14189 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
14190 if (live_regs_mask
& (1 << next_hi_reg
))
14193 while (high_regs_pushed
)
14195 /* Find lo register(s) into which the high register(s) can
14197 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
14199 if (mask
& (1 << regno
))
14200 high_regs_pushed
--;
14201 if (high_regs_pushed
== 0)
14205 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
14207 /* Pop the values into the low register(s). */
14208 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
14210 /* Move the value(s) into the high registers. */
14211 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
14213 if (mask
& (1 << regno
))
14215 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
14218 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
14219 if (live_regs_mask
& (1 << next_hi_reg
))
14224 live_regs_mask
&= ~0x0f00;
14227 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
14228 live_regs_mask
&= 0xff;
14230 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
14232 /* Pop the return address into the PC. */
14233 if (had_to_push_lr
)
14234 live_regs_mask
|= 1 << PC_REGNUM
;
14236 /* Either no argument registers were pushed or a backtrace
14237 structure was created which includes an adjusted stack
14238 pointer, so just pop everything. */
14239 if (live_regs_mask
)
14240 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
14243 /* We have either just popped the return address into the
14244 PC or it is was kept in LR for the entire function. */
14245 if (!had_to_push_lr
)
14246 thumb_exit (asm_out_file
, LR_REGNUM
);
14250 /* Pop everything but the return address. */
14251 if (live_regs_mask
)
14252 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
14255 if (had_to_push_lr
)
14259 /* We have no free low regs, so save one. */
14260 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
14264 /* Get the return address into a temporary register. */
14265 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
14266 1 << LAST_ARG_REGNUM
);
14270 /* Move the return address to lr. */
14271 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
14273 /* Restore the low register. */
14274 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
14279 regno
= LAST_ARG_REGNUM
;
14284 /* Remove the argument registers that were pushed onto the stack. */
14285 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
14286 SP_REGNUM
, SP_REGNUM
,
14287 current_function_pretend_args_size
);
14289 thumb_exit (asm_out_file
, regno
);
14295 /* Functions to save and restore machine-specific function data. */
14296 static struct machine_function
*
14297 arm_init_machine_status (void)
14299 struct machine_function
*machine
;
14300 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
14302 #if ARM_FT_UNKNOWN != 0
14303 machine
->func_type
= ARM_FT_UNKNOWN
;
14308 /* Return an RTX indicating where the return address to the
14309 calling function can be found. */
14311 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
14316 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
14319 /* Do anything needed before RTL is emitted for each function. */
14321 arm_init_expanders (void)
14323 /* Arrange to initialize and mark the machine per-function status. */
14324 init_machine_status
= arm_init_machine_status
;
14326 /* This is to stop the combine pass optimizing away the alignment
14327 adjustment of va_arg. */
14328 /* ??? It is claimed that this should not be necessary. */
14330 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
14334 /* Like arm_compute_initial_elimination offset. Simpler because there
14335 isn't an ABI specified frame pointer for Thumb. Instead, we set it
14336 to point at the base of the local variables after static stack
14337 space for a function has been allocated. */
14340 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
14342 arm_stack_offsets
*offsets
;
14344 offsets
= arm_get_frame_offsets ();
14348 case ARG_POINTER_REGNUM
:
14351 case STACK_POINTER_REGNUM
:
14352 return offsets
->outgoing_args
- offsets
->saved_args
;
14354 case FRAME_POINTER_REGNUM
:
14355 return offsets
->soft_frame
- offsets
->saved_args
;
14357 case ARM_HARD_FRAME_POINTER_REGNUM
:
14358 return offsets
->saved_regs
- offsets
->saved_args
;
14360 case THUMB_HARD_FRAME_POINTER_REGNUM
:
14361 return offsets
->locals_base
- offsets
->saved_args
;
14364 gcc_unreachable ();
14368 case FRAME_POINTER_REGNUM
:
14371 case STACK_POINTER_REGNUM
:
14372 return offsets
->outgoing_args
- offsets
->soft_frame
;
14374 case ARM_HARD_FRAME_POINTER_REGNUM
:
14375 return offsets
->saved_regs
- offsets
->soft_frame
;
14377 case THUMB_HARD_FRAME_POINTER_REGNUM
:
14378 return offsets
->locals_base
- offsets
->soft_frame
;
14381 gcc_unreachable ();
14386 gcc_unreachable ();
14390 /* Generate the rest of a function's prologue. */
14392 thumb1_expand_prologue (void)
14396 HOST_WIDE_INT amount
;
14397 arm_stack_offsets
*offsets
;
14398 unsigned long func_type
;
14400 unsigned long live_regs_mask
;
14402 func_type
= arm_current_func_type ();
14404 /* Naked functions don't have prologues. */
14405 if (IS_NAKED (func_type
))
14408 if (IS_INTERRUPT (func_type
))
14410 error ("interrupt Service Routines cannot be coded in Thumb mode");
14414 live_regs_mask
= thumb1_compute_save_reg_mask ();
14415 /* Load the pic register before setting the frame pointer,
14416 so we can use r7 as a temporary work register. */
14417 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
14418 arm_load_pic_register (live_regs_mask
);
14420 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
14421 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
14422 stack_pointer_rtx
);
14424 offsets
= arm_get_frame_offsets ();
14425 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
14430 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
14431 GEN_INT (- amount
)));
14432 RTX_FRAME_RELATED_P (insn
) = 1;
14438 /* The stack decrement is too big for an immediate value in a single
14439 insn. In theory we could issue multiple subtracts, but after
14440 three of them it becomes more space efficient to place the full
14441 value in the constant pool and load into a register. (Also the
14442 ARM debugger really likes to see only one stack decrement per
14443 function). So instead we look for a scratch register into which
14444 we can load the decrement, and then we subtract this from the
14445 stack pointer. Unfortunately on the thumb the only available
14446 scratch registers are the argument registers, and we cannot use
14447 these as they may hold arguments to the function. Instead we
14448 attempt to locate a call preserved register which is used by this
14449 function. If we can find one, then we know that it will have
14450 been pushed at the start of the prologue and so we can corrupt
14452 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
14453 if (live_regs_mask
& (1 << regno
)
14454 && !(frame_pointer_needed
14455 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
14458 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
14460 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
14462 /* Choose an arbitrary, non-argument low register. */
14463 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
14465 /* Save it by copying it into a high, scratch register. */
14466 emit_insn (gen_movsi (spare
, reg
));
14467 /* Add a USE to stop propagate_one_insn() from barfing. */
14468 emit_insn (gen_prologue_use (spare
));
14470 /* Decrement the stack. */
14471 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
14472 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
14473 stack_pointer_rtx
, reg
));
14474 RTX_FRAME_RELATED_P (insn
) = 1;
14475 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
14476 plus_constant (stack_pointer_rtx
,
14478 RTX_FRAME_RELATED_P (dwarf
) = 1;
14480 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
14483 /* Restore the low register's original value. */
14484 emit_insn (gen_movsi (reg
, spare
));
14486 /* Emit a USE of the restored scratch register, so that flow
14487 analysis will not consider the restore redundant. The
14488 register won't be used again in this function and isn't
14489 restored by the epilogue. */
14490 emit_insn (gen_prologue_use (reg
));
14494 reg
= gen_rtx_REG (SImode
, regno
);
14496 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
14498 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
14499 stack_pointer_rtx
, reg
));
14500 RTX_FRAME_RELATED_P (insn
) = 1;
14501 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
14502 plus_constant (stack_pointer_rtx
,
14504 RTX_FRAME_RELATED_P (dwarf
) = 1;
14506 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
14512 if (frame_pointer_needed
)
14513 thumb_set_frame_pointer (offsets
);
14515 /* If we are profiling, make sure no instructions are scheduled before
14516 the call to mcount. Similarly if the user has requested no
14517 scheduling in the prolog. Similarly if we want non-call exceptions
14518 using the EABI unwinder, to prevent faulting instructions from being
14519 swapped with a stack adjustment. */
14520 if (current_function_profile
|| !TARGET_SCHED_PROLOG
14521 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
14522 emit_insn (gen_blockage ());
14524 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
14525 if (live_regs_mask
& 0xff)
14526 cfun
->machine
->lr_save_eliminated
= 0;
14528 /* If the link register is being kept alive, with the return address in it,
14529 then make sure that it does not get reused by the ce2 pass. */
14530 if (cfun
->machine
->lr_save_eliminated
)
14531 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
14536 thumb1_expand_epilogue (void)
14538 HOST_WIDE_INT amount
;
14539 arm_stack_offsets
*offsets
;
14542 /* Naked functions don't have prologues. */
14543 if (IS_NAKED (arm_current_func_type ()))
14546 offsets
= arm_get_frame_offsets ();
14547 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
14549 if (frame_pointer_needed
)
14551 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
14552 amount
= offsets
->locals_base
- offsets
->saved_regs
;
14558 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
14559 GEN_INT (amount
)));
14562 /* r3 is always free in the epilogue. */
14563 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
14565 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
14566 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
14570 /* Emit a USE (stack_pointer_rtx), so that
14571 the stack adjustment will not be deleted. */
14572 emit_insn (gen_prologue_use (stack_pointer_rtx
));
14574 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
14575 emit_insn (gen_blockage ());
14577 /* Emit a clobber for each insn that will be restored in the epilogue,
14578 so that flow2 will get register lifetimes correct. */
14579 for (regno
= 0; regno
< 13; regno
++)
14580 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
14581 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
14583 if (! regs_ever_live
[LR_REGNUM
])
14584 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
14588 thumb1_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
14590 unsigned long live_regs_mask
= 0;
14591 unsigned long l_mask
;
14592 unsigned high_regs_pushed
= 0;
14593 int cfa_offset
= 0;
14596 if (IS_NAKED (arm_current_func_type ()))
14599 if (is_called_in_ARM_mode (current_function_decl
))
14603 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
14604 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
14606 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
14608 /* Generate code sequence to switch us into Thumb mode. */
14609 /* The .code 32 directive has already been emitted by
14610 ASM_DECLARE_FUNCTION_NAME. */
14611 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
14612 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
14614 /* Generate a label, so that the debugger will notice the
14615 change in instruction sets. This label is also used by
14616 the assembler to bypass the ARM code when this function
14617 is called from a Thumb encoded function elsewhere in the
14618 same file. Hence the definition of STUB_NAME here must
14619 agree with the definition in gas/config/tc-arm.c. */
14621 #define STUB_NAME ".real_start_of"
14623 fprintf (f
, "\t.code\t16\n");
14625 if (arm_dllexport_name_p (name
))
14626 name
= arm_strip_name_encoding (name
);
14628 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
14629 fprintf (f
, "\t.thumb_func\n");
14630 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
14633 if (current_function_pretend_args_size
)
14635 /* Output unwind directive for the stack adjustment. */
14636 if (ARM_EABI_UNWIND_TABLES
)
14637 fprintf (f
, "\t.pad #%d\n",
14638 current_function_pretend_args_size
);
14640 if (cfun
->machine
->uses_anonymous_args
)
14644 fprintf (f
, "\tpush\t{");
14646 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
14648 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
14649 regno
<= LAST_ARG_REGNUM
;
14651 asm_fprintf (f
, "%r%s", regno
,
14652 regno
== LAST_ARG_REGNUM
? "" : ", ");
14654 fprintf (f
, "}\n");
14657 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
14658 SP_REGNUM
, SP_REGNUM
,
14659 current_function_pretend_args_size
);
14661 /* We don't need to record the stores for unwinding (would it
14662 help the debugger any if we did?), but record the change in
14663 the stack pointer. */
14664 if (dwarf2out_do_frame ())
14666 char *l
= dwarf2out_cfi_label ();
14668 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
14669 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
14673 /* Get the registers we are going to push. */
14674 live_regs_mask
= thumb1_compute_save_reg_mask ();
14675 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
14676 l_mask
= live_regs_mask
& 0x40ff;
14677 /* Then count how many other high registers will need to be pushed. */
14678 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
14680 if (TARGET_BACKTRACE
)
14683 unsigned work_register
;
14685 /* We have been asked to create a stack backtrace structure.
14686 The code looks like this:
14690 0 sub SP, #16 Reserve space for 4 registers.
14691 2 push {R7} Push low registers.
14692 4 add R7, SP, #20 Get the stack pointer before the push.
14693 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
14694 8 mov R7, PC Get hold of the start of this code plus 12.
14695 10 str R7, [SP, #16] Store it.
14696 12 mov R7, FP Get hold of the current frame pointer.
14697 14 str R7, [SP, #4] Store it.
14698 16 mov R7, LR Get hold of the current return address.
14699 18 str R7, [SP, #12] Store it.
14700 20 add R7, SP, #16 Point at the start of the backtrace structure.
14701 22 mov FP, R7 Put this value into the frame pointer. */
14703 work_register
= thumb_find_work_register (live_regs_mask
);
14705 if (ARM_EABI_UNWIND_TABLES
)
14706 asm_fprintf (f
, "\t.pad #16\n");
14709 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
14710 SP_REGNUM
, SP_REGNUM
);
14712 if (dwarf2out_do_frame ())
14714 char *l
= dwarf2out_cfi_label ();
14716 cfa_offset
= cfa_offset
+ 16;
14717 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
14722 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14723 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
14728 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
14729 offset
+ 16 + current_function_pretend_args_size
);
14731 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14734 /* Make sure that the instruction fetching the PC is in the right place
14735 to calculate "start of backtrace creation code + 12". */
14738 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
14739 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14741 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
14742 ARM_HARD_FRAME_POINTER_REGNUM
);
14743 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14748 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
14749 ARM_HARD_FRAME_POINTER_REGNUM
);
14750 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14752 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
14753 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14757 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
14758 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14760 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
14762 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14763 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
14765 /* Optimization: If we are not pushing any low registers but we are going
14766 to push some high registers then delay our first push. This will just
14767 be a push of LR and we can combine it with the push of the first high
14769 else if ((l_mask
& 0xff) != 0
14770 || (high_regs_pushed
== 0 && l_mask
))
14771 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14773 if (high_regs_pushed
)
14775 unsigned pushable_regs
;
14776 unsigned next_hi_reg
;
14778 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
14779 if (live_regs_mask
& (1 << next_hi_reg
))
14782 pushable_regs
= l_mask
& 0xff;
14784 if (pushable_regs
== 0)
14785 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
14787 while (high_regs_pushed
> 0)
14789 unsigned long real_regs_mask
= 0;
14791 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
14793 if (pushable_regs
& (1 << regno
))
14795 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
14797 high_regs_pushed
--;
14798 real_regs_mask
|= (1 << next_hi_reg
);
14800 if (high_regs_pushed
)
14802 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
14804 if (live_regs_mask
& (1 << next_hi_reg
))
14809 pushable_regs
&= ~((1 << regno
) - 1);
14815 /* If we had to find a work register and we have not yet
14816 saved the LR then add it to the list of regs to push. */
14817 if (l_mask
== (1 << LR_REGNUM
))
14819 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14821 real_regs_mask
| (1 << LR_REGNUM
));
14825 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14830 /* Handle the case of a double word load into a low register from
14831 a computed memory address. The computed address may involve a
14832 register which is overwritten by the load. */
14834 thumb_load_double_from_address (rtx
*operands
)
14842 gcc_assert (GET_CODE (operands
[0]) == REG
);
14843 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14845 /* Get the memory address. */
14846 addr
= XEXP (operands
[1], 0);
14848 /* Work out how the memory address is computed. */
14849 switch (GET_CODE (addr
))
14852 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14854 if (REGNO (operands
[0]) == REGNO (addr
))
14856 output_asm_insn ("ldr\t%H0, %2", operands
);
14857 output_asm_insn ("ldr\t%0, %1", operands
);
14861 output_asm_insn ("ldr\t%0, %1", operands
);
14862 output_asm_insn ("ldr\t%H0, %2", operands
);
14867 /* Compute <address> + 4 for the high order load. */
14868 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14870 output_asm_insn ("ldr\t%0, %1", operands
);
14871 output_asm_insn ("ldr\t%H0, %2", operands
);
14875 arg1
= XEXP (addr
, 0);
14876 arg2
= XEXP (addr
, 1);
14878 if (CONSTANT_P (arg1
))
14879 base
= arg2
, offset
= arg1
;
14881 base
= arg1
, offset
= arg2
;
14883 gcc_assert (GET_CODE (base
) == REG
);
14885 /* Catch the case of <address> = <reg> + <reg> */
14886 if (GET_CODE (offset
) == REG
)
14888 int reg_offset
= REGNO (offset
);
14889 int reg_base
= REGNO (base
);
14890 int reg_dest
= REGNO (operands
[0]);
14892 /* Add the base and offset registers together into the
14893 higher destination register. */
14894 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14895 reg_dest
+ 1, reg_base
, reg_offset
);
14897 /* Load the lower destination register from the address in
14898 the higher destination register. */
14899 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14900 reg_dest
, reg_dest
+ 1);
14902 /* Load the higher destination register from its own address
14904 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14905 reg_dest
+ 1, reg_dest
+ 1);
14909 /* Compute <address> + 4 for the high order load. */
14910 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14912 /* If the computed address is held in the low order register
14913 then load the high order register first, otherwise always
14914 load the low order register first. */
14915 if (REGNO (operands
[0]) == REGNO (base
))
14917 output_asm_insn ("ldr\t%H0, %2", operands
);
14918 output_asm_insn ("ldr\t%0, %1", operands
);
14922 output_asm_insn ("ldr\t%0, %1", operands
);
14923 output_asm_insn ("ldr\t%H0, %2", operands
);
14929 /* With no registers to worry about we can just load the value
14931 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14933 output_asm_insn ("ldr\t%H0, %2", operands
);
14934 output_asm_insn ("ldr\t%0, %1", operands
);
14938 gcc_unreachable ();
14945 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14952 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14955 operands
[4] = operands
[5];
14958 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14959 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14963 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14966 operands
[4] = operands
[5];
14969 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14972 operands
[5] = operands
[6];
14975 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14978 operands
[4] = operands
[5];
14982 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14983 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14987 gcc_unreachable ();
14993 /* Output a call-via instruction for thumb state. */
14995 thumb_call_via_reg (rtx reg
)
14997 int regno
= REGNO (reg
);
15000 gcc_assert (regno
< LR_REGNUM
);
15002 /* If we are in the normal text section we can use a single instance
15003 per compilation unit. If we are doing function sections, then we need
15004 an entry per section, since we can't rely on reachability. */
15005 if (in_section
== text_section
)
15007 thumb_call_reg_needed
= 1;
15009 if (thumb_call_via_label
[regno
] == NULL
)
15010 thumb_call_via_label
[regno
] = gen_label_rtx ();
15011 labelp
= thumb_call_via_label
+ regno
;
15015 if (cfun
->machine
->call_via
[regno
] == NULL
)
15016 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
15017 labelp
= cfun
->machine
->call_via
+ regno
;
15020 output_asm_insn ("bl\t%a0", labelp
);
15024 /* Routines for generating rtl. */
15026 thumb_expand_movmemqi (rtx
*operands
)
15028 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
15029 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
15030 HOST_WIDE_INT len
= INTVAL (operands
[2]);
15031 HOST_WIDE_INT offset
= 0;
15035 emit_insn (gen_movmem12b (out
, in
, out
, in
));
15041 emit_insn (gen_movmem8b (out
, in
, out
, in
));
15047 rtx reg
= gen_reg_rtx (SImode
);
15048 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
15049 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
15056 rtx reg
= gen_reg_rtx (HImode
);
15057 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
15058 plus_constant (in
, offset
))));
15059 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
15067 rtx reg
= gen_reg_rtx (QImode
);
15068 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
15069 plus_constant (in
, offset
))));
15070 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
15076 thumb_reload_out_hi (rtx
*operands
)
15078 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
15081 /* Handle reading a half-word from memory during reload. */
15083 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
15085 gcc_unreachable ();
15088 /* Return the length of a function name prefix
15089 that starts with the character 'c'. */
15091 arm_get_strip_length (int c
)
15095 ARM_NAME_ENCODING_LENGTHS
15100 /* Return a pointer to a function's name with any
15101 and all prefix encodings stripped from it. */
15103 arm_strip_name_encoding (const char *name
)
15107 while ((skip
= arm_get_strip_length (* name
)))
15113 /* If there is a '*' anywhere in the name's prefix, then
15114 emit the stripped name verbatim, otherwise prepend an
15115 underscore if leading underscores are being used. */
15117 arm_asm_output_labelref (FILE *stream
, const char *name
)
15122 while ((skip
= arm_get_strip_length (* name
)))
15124 verbatim
|= (*name
== '*');
15129 fputs (name
, stream
);
15131 asm_fprintf (stream
, "%U%s", name
);
15135 arm_file_start (void)
15139 if (TARGET_UNIFIED_ASM
)
15140 asm_fprintf (asm_out_file
, "\t.syntax unified\n");
15144 const char *fpu_name
;
15145 if (arm_select
[0].string
)
15146 asm_fprintf (asm_out_file
, "\t.cpu %s\n", arm_select
[0].string
);
15147 else if (arm_select
[1].string
)
15148 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_select
[1].string
);
15150 asm_fprintf (asm_out_file
, "\t.cpu %s\n",
15151 all_cores
[arm_default_cpu
].name
);
15153 if (TARGET_SOFT_FLOAT
)
15156 fpu_name
= "softvfp";
15158 fpu_name
= "softfpa";
15162 switch (arm_fpu_arch
)
15167 case FPUTYPE_FPA_EMU2
:
15170 case FPUTYPE_FPA_EMU3
:
15173 case FPUTYPE_MAVERICK
:
15174 fpu_name
= "maverick";
15177 if (TARGET_HARD_FLOAT
)
15178 asm_fprintf (asm_out_file
, "\t.eabi_attribute 27, 3\n");
15179 if (TARGET_HARD_FLOAT_ABI
)
15180 asm_fprintf (asm_out_file
, "\t.eabi_attribute 28, 1\n");
15187 asm_fprintf (asm_out_file
, "\t.fpu %s\n", fpu_name
);
15189 /* Some of these attributes only apply when the corresponding features
15190 are used. However we don't have any easy way of figuring this out.
15191 Conservatively record the setting that would have been used. */
15193 /* Tag_ABI_PCS_wchar_t. */
15194 asm_fprintf (asm_out_file
, "\t.eabi_attribute 18, %d\n",
15195 (int)WCHAR_TYPE_SIZE
/ BITS_PER_UNIT
);
15197 /* Tag_ABI_FP_rounding. */
15198 if (flag_rounding_math
)
15199 asm_fprintf (asm_out_file
, "\t.eabi_attribute 19, 1\n");
15200 if (!flag_unsafe_math_optimizations
)
15202 /* Tag_ABI_FP_denomal. */
15203 asm_fprintf (asm_out_file
, "\t.eabi_attribute 20, 1\n");
15204 /* Tag_ABI_FP_exceptions. */
15205 asm_fprintf (asm_out_file
, "\t.eabi_attribute 21, 1\n");
15207 /* Tag_ABI_FP_user_exceptions. */
15208 if (flag_signaling_nans
)
15209 asm_fprintf (asm_out_file
, "\t.eabi_attribute 22, 1\n");
15210 /* Tag_ABI_FP_number_model. */
15211 asm_fprintf (asm_out_file
, "\t.eabi_attribute 23, %d\n",
15212 flag_finite_math_only
? 1 : 3);
15214 /* Tag_ABI_align8_needed. */
15215 asm_fprintf (asm_out_file
, "\t.eabi_attribute 24, 1\n");
15216 /* Tag_ABI_align8_preserved. */
15217 asm_fprintf (asm_out_file
, "\t.eabi_attribute 25, 1\n");
15218 /* Tag_ABI_enum_size. */
15219 asm_fprintf (asm_out_file
, "\t.eabi_attribute 26, %d\n",
15220 flag_short_enums
? 1 : 2);
15222 /* Tag_ABI_optimization_goals. */
15225 else if (optimize
>= 2)
15231 asm_fprintf (asm_out_file
, "\t.eabi_attribute 30, %d\n", val
);
15233 default_file_start();
15237 arm_file_end (void)
15241 if (NEED_INDICATE_EXEC_STACK
)
15242 /* Add .note.GNU-stack. */
15243 file_end_indicate_exec_stack ();
15245 if (! thumb_call_reg_needed
)
15248 switch_to_section (text_section
);
15249 asm_fprintf (asm_out_file
, "\t.code 16\n");
15250 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
15252 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
15254 rtx label
= thumb_call_via_label
[regno
];
15258 targetm
.asm_out
.internal_label (asm_out_file
, "L",
15259 CODE_LABEL_NUMBER (label
));
15260 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
15267 #ifdef AOF_ASSEMBLER
15268 /* Special functions only needed when producing AOF syntax assembler. */
15272 struct pic_chain
* next
;
15273 const char * symname
;
15276 static struct pic_chain
* aof_pic_chain
= NULL
;
15279 aof_pic_entry (rtx x
)
15281 struct pic_chain
** chainp
;
15284 if (aof_pic_label
== NULL_RTX
)
15286 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
15289 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
15290 offset
+= 4, chainp
= &(*chainp
)->next
)
15291 if ((*chainp
)->symname
== XSTR (x
, 0))
15292 return plus_constant (aof_pic_label
, offset
);
15294 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
15295 (*chainp
)->next
= NULL
;
15296 (*chainp
)->symname
= XSTR (x
, 0);
15297 return plus_constant (aof_pic_label
, offset
);
15301 aof_dump_pic_table (FILE *f
)
15303 struct pic_chain
* chain
;
15305 if (aof_pic_chain
== NULL
)
15308 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
15309 PIC_OFFSET_TABLE_REGNUM
,
15310 PIC_OFFSET_TABLE_REGNUM
);
15311 fputs ("|x$adcons|\n", f
);
15313 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
15315 fputs ("\tDCD\t", f
);
15316 assemble_name (f
, chain
->symname
);
15321 int arm_text_section_count
= 1;
15323 /* A get_unnamed_section callback for switching to the text section. */
15326 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
15328 fprintf (asm_out_file
, "\tAREA |C$$code%d|, CODE, READONLY",
15329 arm_text_section_count
++);
15331 fprintf (asm_out_file
, ", PIC, REENTRANT");
15332 fprintf (asm_out_file
, "\n");
15335 static int arm_data_section_count
= 1;
15337 /* A get_unnamed_section callback for switching to the data section. */
15340 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
15342 fprintf (asm_out_file
, "\tAREA |C$$data%d|, DATA\n",
15343 arm_data_section_count
++);
15346 /* Implement TARGET_ASM_INIT_SECTIONS.
15348 AOF Assembler syntax is a nightmare when it comes to areas, since once
15349 we change from one area to another, we can't go back again. Instead,
15350 we must create a new area with the same attributes and add the new output
15351 to that. Unfortunately, there is nothing we can do here to guarantee that
15352 two areas with the same attributes will be linked adjacently in the
15353 resulting executable, so we have to be careful not to do pc-relative
15354 addressing across such boundaries. */
15357 aof_asm_init_sections (void)
15359 text_section
= get_unnamed_section (SECTION_CODE
,
15360 aof_output_text_section_asm_op
, NULL
);
15361 data_section
= get_unnamed_section (SECTION_WRITE
,
15362 aof_output_data_section_asm_op
, NULL
);
15363 readonly_data_section
= text_section
;
15367 zero_init_section (void)
15369 static int zero_init_count
= 1;
15371 fprintf (asm_out_file
, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count
++);
15375 /* The AOF assembler is religiously strict about declarations of
15376 imported and exported symbols, so that it is impossible to declare
15377 a function as imported near the beginning of the file, and then to
15378 export it later on. It is, however, possible to delay the decision
15379 until all the functions in the file have been compiled. To get
15380 around this, we maintain a list of the imports and exports, and
15381 delete from it any that are subsequently defined. At the end of
15382 compilation we spit the remainder of the list out before the END
15387 struct import
* next
;
15391 static struct import
* imports_list
= NULL
;
15394 aof_add_import (const char *name
)
15396 struct import
* new;
15398 for (new = imports_list
; new; new = new->next
)
15399 if (new->name
== name
)
15402 new = (struct import
*) xmalloc (sizeof (struct import
));
15403 new->next
= imports_list
;
15404 imports_list
= new;
15409 aof_delete_import (const char *name
)
15411 struct import
** old
;
15413 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
15415 if ((*old
)->name
== name
)
15417 *old
= (*old
)->next
;
15423 int arm_main_function
= 0;
15426 aof_dump_imports (FILE *f
)
15428 /* The AOF assembler needs this to cause the startup code to be extracted
15429 from the library. Brining in __main causes the whole thing to work
15431 if (arm_main_function
)
15433 switch_to_section (text_section
);
15434 fputs ("\tIMPORT __main\n", f
);
15435 fputs ("\tDCD __main\n", f
);
15438 /* Now dump the remaining imports. */
15439 while (imports_list
)
15441 fprintf (f
, "\tIMPORT\t");
15442 assemble_name (f
, imports_list
->name
);
15444 imports_list
= imports_list
->next
;
15449 aof_globalize_label (FILE *stream
, const char *name
)
15451 default_globalize_label (stream
, name
);
15452 if (! strcmp (name
, "main"))
15453 arm_main_function
= 1;
15457 aof_file_start (void)
15459 fputs ("__r0\tRN\t0\n", asm_out_file
);
15460 fputs ("__a1\tRN\t0\n", asm_out_file
);
15461 fputs ("__a2\tRN\t1\n", asm_out_file
);
15462 fputs ("__a3\tRN\t2\n", asm_out_file
);
15463 fputs ("__a4\tRN\t3\n", asm_out_file
);
15464 fputs ("__v1\tRN\t4\n", asm_out_file
);
15465 fputs ("__v2\tRN\t5\n", asm_out_file
);
15466 fputs ("__v3\tRN\t6\n", asm_out_file
);
15467 fputs ("__v4\tRN\t7\n", asm_out_file
);
15468 fputs ("__v5\tRN\t8\n", asm_out_file
);
15469 fputs ("__v6\tRN\t9\n", asm_out_file
);
15470 fputs ("__sl\tRN\t10\n", asm_out_file
);
15471 fputs ("__fp\tRN\t11\n", asm_out_file
);
15472 fputs ("__ip\tRN\t12\n", asm_out_file
);
15473 fputs ("__sp\tRN\t13\n", asm_out_file
);
15474 fputs ("__lr\tRN\t14\n", asm_out_file
);
15475 fputs ("__pc\tRN\t15\n", asm_out_file
);
15476 fputs ("__f0\tFN\t0\n", asm_out_file
);
15477 fputs ("__f1\tFN\t1\n", asm_out_file
);
15478 fputs ("__f2\tFN\t2\n", asm_out_file
);
15479 fputs ("__f3\tFN\t3\n", asm_out_file
);
15480 fputs ("__f4\tFN\t4\n", asm_out_file
);
15481 fputs ("__f5\tFN\t5\n", asm_out_file
);
15482 fputs ("__f6\tFN\t6\n", asm_out_file
);
15483 fputs ("__f7\tFN\t7\n", asm_out_file
);
15484 switch_to_section (text_section
);
15488 aof_file_end (void)
15491 aof_dump_pic_table (asm_out_file
);
15493 aof_dump_imports (asm_out_file
);
15494 fputs ("\tEND\n", asm_out_file
);
15496 #endif /* AOF_ASSEMBLER */
15499 /* Symbols in the text segment can be accessed without indirecting via the
15500 constant pool; it may take an extra binary operation, but this is still
15501 faster than indirecting via memory. Don't do this when not optimizing,
15502 since we won't be calculating al of the offsets necessary to do this
15506 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
15508 /* This doesn't work with AOF syntax, since the string table may be in
15509 a different AREA. */
15510 #ifndef AOF_ASSEMBLER
15511 if (optimize
> 0 && TREE_CONSTANT (decl
))
15512 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
15515 /* If we are referencing a function that is weak then encode a long call
15516 flag in the function name, otherwise if the function is static or
15517 or known to be defined in this file then encode a short call flag. */
15518 if (first
&& DECL_P (decl
))
15520 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
15521 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
15522 else if (! TREE_PUBLIC (decl
))
15523 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
15526 default_encode_section_info (decl
, rtl
, first
);
15528 #endif /* !ARM_PE */
15531 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
15533 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
15534 && !strcmp (prefix
, "L"))
15536 arm_ccfsm_state
= 0;
15537 arm_target_insn
= NULL
;
15539 default_internal_label (stream
, prefix
, labelno
);
15542 /* Output code to add DELTA to the first argument, and then jump
15543 to FUNCTION. Used for C++ multiple inheritance. */
15545 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
15546 HOST_WIDE_INT delta
,
15547 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
15550 static int thunk_label
= 0;
15553 int mi_delta
= delta
;
15554 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
15556 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
15559 mi_delta
= - mi_delta
;
15560 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
15563 int labelno
= thunk_label
++;
15564 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
15565 fputs ("\tldr\tr12, ", file
);
15566 assemble_name (file
, label
);
15567 fputc ('\n', file
);
15570 /* If we are generating PIC, the ldr instruction below loads
15571 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
15572 the address of the add + 8, so we have:
15574 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
15577 Note that we have "+ 1" because some versions of GNU ld
15578 don't set the low bit of the result for R_ARM_REL32
15579 relocations against thumb function symbols. */
15580 ASM_GENERATE_INTERNAL_LABEL (labelpc
, "LTHUNKPC", labelno
);
15581 assemble_name (file
, labelpc
);
15582 fputs (":\n", file
);
15583 fputs ("\tadd\tr12, pc, r12\n", file
);
15586 /* TODO: Use movw/movt for large constants when available. */
15587 while (mi_delta
!= 0)
15589 if ((mi_delta
& (3 << shift
)) == 0)
15593 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
15594 mi_op
, this_regno
, this_regno
,
15595 mi_delta
& (0xff << shift
));
15596 mi_delta
&= ~(0xff << shift
);
15602 fprintf (file
, "\tbx\tr12\n");
15603 ASM_OUTPUT_ALIGN (file
, 2);
15604 assemble_name (file
, label
);
15605 fputs (":\n", file
);
15608 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
15609 rtx tem
= XEXP (DECL_RTL (function
), 0);
15610 tem
= gen_rtx_PLUS (GET_MODE (tem
), tem
, GEN_INT (-7));
15611 tem
= gen_rtx_MINUS (GET_MODE (tem
),
15613 gen_rtx_SYMBOL_REF (Pmode
,
15614 ggc_strdup (labelpc
)));
15615 assemble_integer (tem
, 4, BITS_PER_WORD
, 1);
15618 /* Output ".word .LTHUNKn". */
15619 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
15623 fputs ("\tb\t", file
);
15624 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
15625 if (NEED_PLT_RELOC
)
15626 fputs ("(PLT)", file
);
15627 fputc ('\n', file
);
15632 arm_emit_vector_const (FILE *file
, rtx x
)
15635 const char * pattern
;
15637 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
15639 switch (GET_MODE (x
))
15641 case V2SImode
: pattern
= "%08x"; break;
15642 case V4HImode
: pattern
= "%04x"; break;
15643 case V8QImode
: pattern
= "%02x"; break;
15644 default: gcc_unreachable ();
15647 fprintf (file
, "0x");
15648 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
15652 element
= CONST_VECTOR_ELT (x
, i
);
15653 fprintf (file
, pattern
, INTVAL (element
));
15660 arm_output_load_gr (rtx
*operands
)
15667 if (GET_CODE (operands
[1]) != MEM
15668 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
15669 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
15670 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
15671 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
15672 return "wldrw%?\t%0, %1";
15674 /* Fix up an out-of-range load of a GR register. */
15675 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
15676 wcgr
= operands
[0];
15678 output_asm_insn ("ldr%?\t%0, %1", operands
);
15680 operands
[0] = wcgr
;
15682 output_asm_insn ("tmcr%?\t%0, %1", operands
);
15683 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
15688 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
15690 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
15691 named arg and all anonymous args onto the stack.
15692 XXX I know the prologue shouldn't be pushing registers, but it is faster
15696 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
15697 enum machine_mode mode ATTRIBUTE_UNUSED
,
15698 tree type ATTRIBUTE_UNUSED
,
15700 int second_time ATTRIBUTE_UNUSED
)
15702 cfun
->machine
->uses_anonymous_args
= 1;
15703 if (cum
->nregs
< NUM_ARG_REGS
)
15704 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
15707 /* Return nonzero if the CONSUMER instruction (a store) does not need
15708 PRODUCER's value to calculate the address. */
15711 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
15713 rtx value
= PATTERN (producer
);
15714 rtx addr
= PATTERN (consumer
);
15716 if (GET_CODE (value
) == COND_EXEC
)
15717 value
= COND_EXEC_CODE (value
);
15718 if (GET_CODE (value
) == PARALLEL
)
15719 value
= XVECEXP (value
, 0, 0);
15720 value
= XEXP (value
, 0);
15721 if (GET_CODE (addr
) == COND_EXEC
)
15722 addr
= COND_EXEC_CODE (addr
);
15723 if (GET_CODE (addr
) == PARALLEL
)
15724 addr
= XVECEXP (addr
, 0, 0);
15725 addr
= XEXP (addr
, 0);
15727 return !reg_overlap_mentioned_p (value
, addr
);
15730 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15731 have an early register shift value or amount dependency on the
15732 result of PRODUCER. */
15735 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
15737 rtx value
= PATTERN (producer
);
15738 rtx op
= PATTERN (consumer
);
15741 if (GET_CODE (value
) == COND_EXEC
)
15742 value
= COND_EXEC_CODE (value
);
15743 if (GET_CODE (value
) == PARALLEL
)
15744 value
= XVECEXP (value
, 0, 0);
15745 value
= XEXP (value
, 0);
15746 if (GET_CODE (op
) == COND_EXEC
)
15747 op
= COND_EXEC_CODE (op
);
15748 if (GET_CODE (op
) == PARALLEL
)
15749 op
= XVECEXP (op
, 0, 0);
15752 early_op
= XEXP (op
, 0);
15753 /* This is either an actual independent shift, or a shift applied to
15754 the first operand of another operation. We want the whole shift
15756 if (GET_CODE (early_op
) == REG
)
15759 return !reg_overlap_mentioned_p (value
, early_op
);
15762 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15763 have an early register shift value dependency on the result of
15767 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
15769 rtx value
= PATTERN (producer
);
15770 rtx op
= PATTERN (consumer
);
15773 if (GET_CODE (value
) == COND_EXEC
)
15774 value
= COND_EXEC_CODE (value
);
15775 if (GET_CODE (value
) == PARALLEL
)
15776 value
= XVECEXP (value
, 0, 0);
15777 value
= XEXP (value
, 0);
15778 if (GET_CODE (op
) == COND_EXEC
)
15779 op
= COND_EXEC_CODE (op
);
15780 if (GET_CODE (op
) == PARALLEL
)
15781 op
= XVECEXP (op
, 0, 0);
15784 early_op
= XEXP (op
, 0);
15786 /* This is either an actual independent shift, or a shift applied to
15787 the first operand of another operation. We want the value being
15788 shifted, in either case. */
15789 if (GET_CODE (early_op
) != REG
)
15790 early_op
= XEXP (early_op
, 0);
15792 return !reg_overlap_mentioned_p (value
, early_op
);
15795 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15796 have an early register mult dependency on the result of
15800 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
15802 rtx value
= PATTERN (producer
);
15803 rtx op
= PATTERN (consumer
);
15805 if (GET_CODE (value
) == COND_EXEC
)
15806 value
= COND_EXEC_CODE (value
);
15807 if (GET_CODE (value
) == PARALLEL
)
15808 value
= XVECEXP (value
, 0, 0);
15809 value
= XEXP (value
, 0);
15810 if (GET_CODE (op
) == COND_EXEC
)
15811 op
= COND_EXEC_CODE (op
);
15812 if (GET_CODE (op
) == PARALLEL
)
15813 op
= XVECEXP (op
, 0, 0);
15816 return (GET_CODE (op
) == PLUS
15817 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
15821 /* We can't rely on the caller doing the proper promotion when
15822 using APCS or ATPCS. */
15825 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
15827 return !TARGET_AAPCS_BASED
;
15831 /* AAPCS based ABIs use short enums by default. */
15834 arm_default_short_enums (void)
15836 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
15840 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15843 arm_align_anon_bitfield (void)
15845 return TARGET_AAPCS_BASED
;
15849 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15852 arm_cxx_guard_type (void)
15854 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
15858 /* The EABI says test the least significant bit of a guard variable. */
15861 arm_cxx_guard_mask_bit (void)
15863 return TARGET_AAPCS_BASED
;
15867 /* The EABI specifies that all array cookies are 8 bytes long. */
15870 arm_get_cookie_size (tree type
)
15874 if (!TARGET_AAPCS_BASED
)
15875 return default_cxx_get_cookie_size (type
);
15877 size
= build_int_cst (sizetype
, 8);
15882 /* The EABI says that array cookies should also contain the element size. */
15885 arm_cookie_has_size (void)
15887 return TARGET_AAPCS_BASED
;
15891 /* The EABI says constructors and destructors should return a pointer to
15892 the object constructed/destroyed. */
15895 arm_cxx_cdtor_returns_this (void)
15897 return TARGET_AAPCS_BASED
;
15900 /* The EABI says that an inline function may never be the key
15904 arm_cxx_key_method_may_be_inline (void)
15906 return !TARGET_AAPCS_BASED
;
15910 arm_cxx_determine_class_data_visibility (tree decl
)
15912 if (!TARGET_AAPCS_BASED
)
15915 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15916 is exported. However, on systems without dynamic vague linkage,
15917 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15918 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
15919 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
15921 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
15922 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
15926 arm_cxx_class_data_always_comdat (void)
15928 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15929 vague linkage if the class has no key function. */
15930 return !TARGET_AAPCS_BASED
;
15934 /* The EABI says __aeabi_atexit should be used to register static
15938 arm_cxx_use_aeabi_atexit (void)
15940 return TARGET_AAPCS_BASED
;
15945 arm_set_return_address (rtx source
, rtx scratch
)
15947 arm_stack_offsets
*offsets
;
15948 HOST_WIDE_INT delta
;
15950 unsigned long saved_regs
;
15952 saved_regs
= arm_compute_save_reg_mask ();
15954 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
15955 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15958 if (frame_pointer_needed
)
15959 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
15962 /* LR will be the first saved register. */
15963 offsets
= arm_get_frame_offsets ();
15964 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15969 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15970 GEN_INT (delta
& ~4095)));
15975 addr
= stack_pointer_rtx
;
15977 addr
= plus_constant (addr
, delta
);
15979 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15985 thumb_set_return_address (rtx source
, rtx scratch
)
15987 arm_stack_offsets
*offsets
;
15988 HOST_WIDE_INT delta
;
15989 HOST_WIDE_INT limit
;
15992 unsigned long mask
;
15994 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15996 mask
= thumb1_compute_save_reg_mask ();
15997 if (mask
& (1 << LR_REGNUM
))
15999 offsets
= arm_get_frame_offsets ();
16002 /* Find the saved regs. */
16003 if (frame_pointer_needed
)
16005 delta
= offsets
->soft_frame
- offsets
->saved_args
;
16006 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
16012 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
16015 /* Allow for the stack frame. */
16016 if (TARGET_THUMB1
&& TARGET_BACKTRACE
)
16018 /* The link register is always the first saved register. */
16021 /* Construct the address. */
16022 addr
= gen_rtx_REG (SImode
, reg
);
16025 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
16026 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
16030 addr
= plus_constant (addr
, delta
);
16032 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
16035 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
16038 /* Implements target hook vector_mode_supported_p. */
16040 arm_vector_mode_supported_p (enum machine_mode mode
)
16042 if ((mode
== V2SImode
)
16043 || (mode
== V4HImode
)
16044 || (mode
== V8QImode
))
16050 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
16051 ARM insns and therefore guarantee that the shift count is modulo 256.
16052 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
16053 guarantee no particular behavior for out-of-range counts. */
16055 static unsigned HOST_WIDE_INT
16056 arm_shift_truncation_mask (enum machine_mode mode
)
16058 return mode
== SImode
? 255 : 0;
16062 /* Map internal gcc register numbers to DWARF2 register numbers. */
16065 arm_dbx_register_number (unsigned int regno
)
16070 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
16071 compatibility. The EABI defines them as registers 96-103. */
16072 if (IS_FPA_REGNUM (regno
))
16073 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
16075 if (IS_VFP_REGNUM (regno
))
16076 return 64 + regno
- FIRST_VFP_REGNUM
;
16078 if (IS_IWMMXT_GR_REGNUM (regno
))
16079 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
16081 if (IS_IWMMXT_REGNUM (regno
))
16082 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
16084 gcc_unreachable ();
16088 #ifdef TARGET_UNWIND_INFO
16089 /* Emit unwind directives for a store-multiple instruction or stack pointer
16090 push during alignment.
16091 These should only ever be generated by the function prologue code, so
16092 expect them to have a particular form. */
16095 arm_unwind_emit_sequence (FILE * asm_out_file
, rtx p
)
16098 HOST_WIDE_INT offset
;
16099 HOST_WIDE_INT nregs
;
16105 e
= XVECEXP (p
, 0, 0);
16106 if (GET_CODE (e
) != SET
)
16109 /* First insn will adjust the stack pointer. */
16110 if (GET_CODE (e
) != SET
16111 || GET_CODE (XEXP (e
, 0)) != REG
16112 || REGNO (XEXP (e
, 0)) != SP_REGNUM
16113 || GET_CODE (XEXP (e
, 1)) != PLUS
)
16116 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
16117 nregs
= XVECLEN (p
, 0) - 1;
16119 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
16122 /* The function prologue may also push pc, but not annotate it as it is
16123 never restored. We turn this into a stack pointer adjustment. */
16124 if (nregs
* 4 == offset
- 4)
16126 fprintf (asm_out_file
, "\t.pad #4\n");
16130 fprintf (asm_out_file
, "\t.save {");
16132 else if (IS_VFP_REGNUM (reg
))
16135 fprintf (asm_out_file
, "\t.vsave {");
16137 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
16139 /* FPA registers are done differently. */
16140 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
16144 /* Unknown register type. */
16147 /* If the stack increment doesn't match the size of the saved registers,
16148 something has gone horribly wrong. */
16149 if (offset
!= nregs
* reg_size
)
16154 /* The remaining insns will describe the stores. */
16155 for (i
= 1; i
<= nregs
; i
++)
16157 /* Expect (set (mem <addr>) (reg)).
16158 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
16159 e
= XVECEXP (p
, 0, i
);
16160 if (GET_CODE (e
) != SET
16161 || GET_CODE (XEXP (e
, 0)) != MEM
16162 || GET_CODE (XEXP (e
, 1)) != REG
)
16165 reg
= REGNO (XEXP (e
, 1));
16170 fprintf (asm_out_file
, ", ");
16171 /* We can't use %r for vfp because we need to use the
16172 double precision register names. */
16173 if (IS_VFP_REGNUM (reg
))
16174 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
16176 asm_fprintf (asm_out_file
, "%r", reg
);
16178 #ifdef ENABLE_CHECKING
16179 /* Check that the addresses are consecutive. */
16180 e
= XEXP (XEXP (e
, 0), 0);
16181 if (GET_CODE (e
) == PLUS
)
16183 offset
+= reg_size
;
16184 if (GET_CODE (XEXP (e
, 0)) != REG
16185 || REGNO (XEXP (e
, 0)) != SP_REGNUM
16186 || GET_CODE (XEXP (e
, 1)) != CONST_INT
16187 || offset
!= INTVAL (XEXP (e
, 1)))
16191 || GET_CODE (e
) != REG
16192 || REGNO (e
) != SP_REGNUM
)
16196 fprintf (asm_out_file
, "}\n");
16199 /* Emit unwind directives for a SET. */
16202 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
16210 switch (GET_CODE (e0
))
16213 /* Pushing a single register. */
16214 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
16215 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
16216 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
16219 asm_fprintf (asm_out_file
, "\t.save ");
16220 if (IS_VFP_REGNUM (REGNO (e1
)))
16221 asm_fprintf(asm_out_file
, "{d%d}\n",
16222 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
16224 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
16228 if (REGNO (e0
) == SP_REGNUM
)
16230 /* A stack increment. */
16231 if (GET_CODE (e1
) != PLUS
16232 || GET_CODE (XEXP (e1
, 0)) != REG
16233 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
16234 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
16237 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
16238 -INTVAL (XEXP (e1
, 1)));
16240 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
16242 HOST_WIDE_INT offset
;
16244 if (GET_CODE (e1
) == PLUS
)
16246 if (GET_CODE (XEXP (e1
, 0)) != REG
16247 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
16249 reg
= REGNO (XEXP (e1
, 0));
16250 offset
= INTVAL (XEXP (e1
, 1));
16251 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
16252 HARD_FRAME_POINTER_REGNUM
, reg
,
16253 INTVAL (XEXP (e1
, 1)));
16255 else if (GET_CODE (e1
) == REG
)
16258 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
16259 HARD_FRAME_POINTER_REGNUM
, reg
);
16264 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
16266 /* Move from sp to reg. */
16267 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
16269 else if (GET_CODE (e1
) == PLUS
16270 && GET_CODE (XEXP (e1
, 0)) == REG
16271 && REGNO (XEXP (e1
, 0)) == SP_REGNUM
16272 && GET_CODE (XEXP (e1
, 1)) == CONST_INT
)
16274 /* Set reg to offset from sp. */
16275 asm_fprintf (asm_out_file
, "\t.movsp %r, #%d\n",
16276 REGNO (e0
), (int)INTVAL(XEXP (e1
, 1)));
16278 else if (GET_CODE (e1
) == UNSPEC
&& XINT (e1
, 1) == UNSPEC_STACK_ALIGN
)
16280 /* Stack pointer save before alignment. */
16282 asm_fprintf (asm_out_file
, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
16295 /* Emit unwind directives for the given insn. */
16298 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
16302 if (!ARM_EABI_UNWIND_TABLES
)
16305 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
16308 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
16310 pat
= XEXP (pat
, 0);
16312 pat
= PATTERN (insn
);
16314 switch (GET_CODE (pat
))
16317 arm_unwind_emit_set (asm_out_file
, pat
);
16321 /* Store multiple. */
16322 arm_unwind_emit_sequence (asm_out_file
, pat
);
16331 /* Output a reference from a function exception table to the type_info
16332 object X. The EABI specifies that the symbol should be relocated by
16333 an R_ARM_TARGET2 relocation. */
16336 arm_output_ttype (rtx x
)
16338 fputs ("\t.word\t", asm_out_file
);
16339 output_addr_const (asm_out_file
, x
);
16340 /* Use special relocations for symbol references. */
16341 if (GET_CODE (x
) != CONST_INT
)
16342 fputs ("(TARGET2)", asm_out_file
);
16343 fputc ('\n', asm_out_file
);
16347 #endif /* TARGET_UNWIND_INFO */
16350 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
16351 stack alignment. */
16354 arm_dwarf_handle_frame_unspec (const char *label
, rtx pattern
, int index
)
16356 rtx unspec
= SET_SRC (pattern
);
16357 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
16361 case UNSPEC_STACK_ALIGN
:
16362 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
16363 put anything on the stack, so hopefully it won't matter.
16364 CFA = SP will be correct after alignment. */
16365 dwarf2out_reg_save_reg (label
, stack_pointer_rtx
,
16366 SET_DEST (pattern
));
16369 gcc_unreachable ();
16374 /* Output unwind directives for the start/end of a function. */
16377 arm_output_fn_unwind (FILE * f
, bool prologue
)
16379 if (!ARM_EABI_UNWIND_TABLES
)
16383 fputs ("\t.fnstart\n", f
);
16385 fputs ("\t.fnend\n", f
);
16389 arm_emit_tls_decoration (FILE *fp
, rtx x
)
16391 enum tls_reloc reloc
;
16394 val
= XVECEXP (x
, 0, 0);
16395 reloc
= INTVAL (XVECEXP (x
, 0, 1));
16397 output_addr_const (fp
, val
);
16402 fputs ("(tlsgd)", fp
);
16405 fputs ("(tlsldm)", fp
);
16408 fputs ("(tlsldo)", fp
);
16411 fputs ("(gottpoff)", fp
);
16414 fputs ("(tpoff)", fp
);
16417 gcc_unreachable ();
16425 fputs (" + (. - ", fp
);
16426 output_addr_const (fp
, XVECEXP (x
, 0, 2));
16428 output_addr_const (fp
, XVECEXP (x
, 0, 3));
16439 arm_output_addr_const_extra (FILE *fp
, rtx x
)
16441 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
16442 return arm_emit_tls_decoration (fp
, x
);
16443 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
16446 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
16448 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
16449 assemble_name_raw (fp
, label
);
16453 else if (GET_CODE (x
) == CONST_VECTOR
)
16454 return arm_emit_vector_const (fp
, x
);
16459 /* Output assembly for a shift instruction.
16460 SET_FLAGS determines how the instruction modifies the condition codes.
16461 0 - Do not set conditiona codes.
16462 1 - Set condition codes.
16463 2 - Use smallest instruction. */
16465 arm_output_shift(rtx
* operands
, int set_flags
)
16468 static const char flag_chars
[3] = {'?', '.', '!'};
16473 c
= flag_chars
[set_flags
];
16474 if (TARGET_UNIFIED_ASM
)
16476 shift
= shift_op(operands
[3], &val
);
16480 operands
[2] = GEN_INT(val
);
16481 sprintf (pattern
, "%s%%%c\t%%0, %%1, %%2", shift
, c
);
16484 sprintf (pattern
, "mov%%%c\t%%0, %%1", c
);
16487 sprintf (pattern
, "mov%%%c\t%%0, %%1%%S3", c
);
16488 output_asm_insn (pattern
, operands
);
16492 /* Output a Thumb-2 casesi instruction. */
16494 thumb2_output_casesi (rtx
*operands
)
16496 rtx diff_vec
= PATTERN (next_real_insn (operands
[2]));
16498 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
16500 output_asm_insn ("cmp\t%0, %1", operands
);
16501 output_asm_insn ("bhi\t%l3", operands
);
16502 switch (GET_MODE(diff_vec
))
16505 return "tbb\t[%|pc, %0]";
16507 return "tbh\t[%|pc, %0, lsl #1]";
16511 output_asm_insn ("adr\t%4, %l2", operands
);
16512 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands
);
16513 output_asm_insn ("add\t%4, %4, %5", operands
);
16518 output_asm_insn ("adr\t%4, %l2", operands
);
16519 return "ldr\t%|pc, [%4, %0, lsl #2]";
16522 gcc_unreachable ();
16526 #include "gt-arm.h"