drivers/libglamo/hw.c

   1 /*
   2  * Library's hardware interface.
   3  *
   4  * Copyright (C) 2007 OpenMoko, Inc.
   5  * Author: Chia-I Wu <olv@openmoko.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #include <stdio.h>
  23 #include <unistd.h>
  24 #include "glamo.h"
  25 #include "hw.h"
  26
  27 #define STATUS_ENABLED  0x1
  28 static int engine_status[GLAMO_ENGINE_2D + 1];
  29
  30 void glamo_hw_engine_reset(enum glamo_engine engine)
  31 {
  32         int reg, mask;
  33
  34         if (!(engine_status[engine] & STATUS_ENABLED))
  35                 return;
  36
  37         switch (engine) {
  38         case GLAMO_ENGINE_MPEG:
  39                 reg = GLAMO_REG_CLOCK_MPEG;
  40                 mask = GLAMO_CLOCK_MPEG_DEC_RESET;
  41                 break;
  42         case GLAMO_ENGINE_ISP:
  43                 reg = GLAMO_REG_CLOCK_ISP;
  44                 mask = GLAMO_CLOCK_ISP2_RESET;
  45                 break;
  46         case GLAMO_ENGINE_CMDQ:
  47                 reg = GLAMO_REG_CLOCK_2D;
  48                 mask = GLAMO_CLOCK_2D_CMDQ_RESET;
  49                 break;
  50         case GLAMO_ENGINE_2D:
  51                 reg = GLAMO_REG_CLOCK_2D;
  52                 mask = GLAMO_CLOCK_2D_RESET;
  53                 break;
  54         default:
  55                 return;
  56         }
  57
  58         glamo_set_bit_mask(reg, mask, 0xffff);
  59         while ((GLAMO_IN_REG(reg) & mask) != mask);
  60         glamo_set_bit_mask(reg, mask, 0);
  61         while ((GLAMO_IN_REG(reg) & mask) != 0);
  62 }
  63
  64 void glamo_hw_engine_enable(enum glamo_engine engine)
  65 {
  66         if (engine_status[engine] & STATUS_ENABLED)
  67                 return;
  68
  69         glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_MCLK, 0xffff);
  70
  71         switch (engine) {
  72         case GLAMO_ENGINE_MPEG:
  73                 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPEG,
  74                                    GLAMO_CLOCK_MPEG_EN_X6CLK |
  75                                    GLAMO_CLOCK_MPEG_DG_X6CLK |
  76                                    GLAMO_CLOCK_MPEG_EN_X4CLK |
  77                                    GLAMO_CLOCK_MPEG_DG_X4CLK |
  78                                    GLAMO_CLOCK_MPEG_EN_X2CLK |
  79                                    GLAMO_CLOCK_MPEG_DG_X2CLK |
  80                                    GLAMO_CLOCK_MPEG_EN_X0CLK |
  81                                    GLAMO_CLOCK_MPEG_DG_X0CLK,
  82                                    0xffff & ~GLAMO_CLOCK_MPEG_DG_X0CLK);
  83                 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC,
  84                                    GLAMO_CLOCK_MPROC_EN_M4CLK,
  85                                    0xffff);
  86                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1,
  87                                    GLAMO_CLOCK_GEN51_EN_DIV_JCLK,
  88                                    0xffff);
  89                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
  90                                    GLAMO_HOSTBUS2_MMIO_EN_MPEG |
  91                                    GLAMO_HOSTBUS2_MMIO_EN_MICROP1,
  92                                    0xffff);
  93                 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC,
  94                                    GLAMO_CLOCK_MPROC_EN_KCLK,
  95                                    0xffff);
  96                 break;
  97         case GLAMO_ENGINE_ISP:
  98                 glamo_set_bit_mask(GLAMO_REG_CLOCK_ISP,
  99                                    GLAMO_CLOCK_ISP_EN_M2CLK |
 100                                    GLAMO_CLOCK_ISP_EN_I1CLK,
 101                                    0xffff);
 102                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_2,
 103                                    GLAMO_CLOCK_GEN52_EN_DIV_ICLK,
 104                                    0xffff);
 105                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1,
 106                                    GLAMO_CLOCK_GEN51_EN_DIV_JCLK,
 107                                    0xffff);
 108                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
 109                                    GLAMO_HOSTBUS2_MMIO_EN_ISP,
 110                                    0xffff);
 111                 break;
 112         case GLAMO_ENGINE_CMDQ:
 113                 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D,
 114                                    GLAMO_CLOCK_2D_EN_M6CLK,
 115                                    0xffff);
 116                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
 117                                    GLAMO_HOSTBUS2_MMIO_EN_CMDQ,
 118                                    0xffff);
 119                 break;
 120         case GLAMO_ENGINE_2D:
 121                 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D,
 122                                    GLAMO_CLOCK_2D_EN_M7CLK |
 123                                    GLAMO_CLOCK_2D_EN_GCLK |
 124                                    GLAMO_CLOCK_2D_DG_M7CLK |
 125                                    GLAMO_CLOCK_2D_DG_GCLK,
 126                                    0xffff);
 127                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
 128                                    GLAMO_HOSTBUS2_MMIO_EN_2D,
 129                                    0xffff);
 130                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1,
 131                                    GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
 132                                    0xffff);
 133                 break;
 134         }
 135
 136         engine_status[engine] |= STATUS_ENABLED;
 137 }
 138
 139 void glamo_hw_engine_disable(enum glamo_engine engine)
 140 {
 141         if (!(engine_status[engine] & STATUS_ENABLED))
 142                 return;
 143
 144         switch (engine) {
 145         case GLAMO_ENGINE_MPEG:
 146                 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPEG,
 147                                    GLAMO_CLOCK_MPEG_EN_X6CLK |
 148                                    GLAMO_CLOCK_MPEG_DG_X6CLK |
 149                                    GLAMO_CLOCK_MPEG_EN_X4CLK |
 150                                    GLAMO_CLOCK_MPEG_DG_X4CLK |
 151                                    GLAMO_CLOCK_MPEG_EN_X2CLK |
 152                                    GLAMO_CLOCK_MPEG_DG_X2CLK |
 153                                    GLAMO_CLOCK_MPEG_EN_X0CLK |
 154                                    GLAMO_CLOCK_MPEG_DG_X0CLK,
 155                                    0);
 156                 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC,
 157                                    GLAMO_CLOCK_MPROC_EN_M4CLK,
 158                                    0);
 159                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1,
 160                                    GLAMO_CLOCK_GEN51_EN_DIV_JCLK,
 161                                    0);
 162                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
 163                                    GLAMO_HOSTBUS2_MMIO_EN_MPEG |
 164                                    GLAMO_HOSTBUS2_MMIO_EN_MICROP1,
 165                                    0);
 166                 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC,
 167                                    GLAMO_CLOCK_MPROC_EN_KCLK,
 168                                    0);
 169                 break;
 170         case GLAMO_ENGINE_ISP:
 171                 glamo_set_bit_mask(GLAMO_REG_CLOCK_ISP,
 172                                    GLAMO_CLOCK_ISP_EN_M2CLK |
 173                                    GLAMO_CLOCK_ISP_EN_I1CLK,
 174                                    0);
 175                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_2,
 176                                    GLAMO_CLOCK_GEN52_EN_DIV_ICLK,
 177                                    0);
 178                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1,
 179                                    GLAMO_CLOCK_GEN51_EN_DIV_JCLK,
 180                                    0);
 181                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
 182                                    GLAMO_HOSTBUS2_MMIO_EN_ISP,
 183                                    0);
 184                 break;
 185         case GLAMO_ENGINE_CMDQ:
 186                 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D,
 187                                    GLAMO_CLOCK_2D_EN_M6CLK,
 188                                    0);
 189                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
 190                                    GLAMO_HOSTBUS2_MMIO_EN_CMDQ,
 191                                    0);
 192                 break;
 193         case GLAMO_ENGINE_2D:
 194                 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D,
 195                                    GLAMO_CLOCK_2D_EN_M7CLK |
 196                                    GLAMO_CLOCK_2D_EN_GCLK |
 197                                    GLAMO_CLOCK_2D_DG_M7CLK |
 198                                    GLAMO_CLOCK_2D_DG_GCLK,
 199                                    0);
 200                 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
 201                                    GLAMO_HOSTBUS2_MMIO_EN_2D,
 202                                    0);
 203                 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1,
 204                                    GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
 205                                    0);
 206                 break;
 207         }
 208
 209         /* simply commented out;  we don't want a clock manager to do things right */
 210         //glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_MCLK, 0);
 211
 212         engine_status[engine] &= ~STATUS_ENABLED;
 213 }
 214
 215 void glamo_hw_dump(int reg, int len)
 216 {
 217         int i, val;
 218
 219         printf("reg       val\n");
 220
 221         for (i = 0; i < len; i++, reg += 2)
 222         {
 223                 val = GLAMO_IN_REG(reg);
 224
 225                 printf("0x%06x: 0x%04x\n", reg, val);
 226         }
 227 }