2 * Library's hardware interface.
4 * Copyright (C) 2007 OpenMoko, Inc.
5 * Author: Chia-I Wu <olv@openmoko.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define STATUS_ENABLED 0x1
28 static int engine_status
[GLAMO_ENGINE_2D
+ 1];
30 void glamo_hw_engine_reset(enum glamo_engine engine
)
34 if (!(engine_status
[engine
] & STATUS_ENABLED
))
38 case GLAMO_ENGINE_MPEG
:
39 reg
= GLAMO_REG_CLOCK_MPEG
;
40 mask
= GLAMO_CLOCK_MPEG_DEC_RESET
;
42 case GLAMO_ENGINE_ISP
:
43 reg
= GLAMO_REG_CLOCK_ISP
;
44 mask
= GLAMO_CLOCK_ISP2_RESET
;
46 case GLAMO_ENGINE_CMDQ
:
47 reg
= GLAMO_REG_CLOCK_2D
;
48 mask
= GLAMO_CLOCK_2D_CMDQ_RESET
;
51 reg
= GLAMO_REG_CLOCK_2D
;
52 mask
= GLAMO_CLOCK_2D_RESET
;
58 glamo_set_bit_mask(reg
, mask
, 0xffff);
59 while ((GLAMO_IN_REG(reg
) & mask
) != mask
);
60 glamo_set_bit_mask(reg
, mask
, 0);
61 while ((GLAMO_IN_REG(reg
) & mask
) != 0);
64 void glamo_hw_engine_enable(enum glamo_engine engine
)
66 if (engine_status
[engine
] & STATUS_ENABLED
)
69 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1
, GLAMO_CLOCK_GEN51_EN_DIV_MCLK
, 0xffff);
72 case GLAMO_ENGINE_MPEG
:
73 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPEG
,
74 GLAMO_CLOCK_MPEG_EN_X6CLK
|
75 GLAMO_CLOCK_MPEG_DG_X6CLK
|
76 GLAMO_CLOCK_MPEG_EN_X4CLK
|
77 GLAMO_CLOCK_MPEG_DG_X4CLK
|
78 GLAMO_CLOCK_MPEG_EN_X2CLK
|
79 GLAMO_CLOCK_MPEG_DG_X2CLK
|
80 GLAMO_CLOCK_MPEG_EN_X0CLK
|
81 GLAMO_CLOCK_MPEG_DG_X0CLK
,
82 0xffff & ~GLAMO_CLOCK_MPEG_DG_X0CLK
);
83 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC
,
84 GLAMO_CLOCK_MPROC_EN_M4CLK
,
86 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1
,
87 GLAMO_CLOCK_GEN51_EN_DIV_JCLK
,
89 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
90 GLAMO_HOSTBUS2_MMIO_EN_MPEG
|
91 GLAMO_HOSTBUS2_MMIO_EN_MICROP1
,
93 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC
,
94 GLAMO_CLOCK_MPROC_EN_KCLK
,
97 case GLAMO_ENGINE_ISP
:
98 glamo_set_bit_mask(GLAMO_REG_CLOCK_ISP
,
99 GLAMO_CLOCK_ISP_EN_M2CLK
|
100 GLAMO_CLOCK_ISP_EN_I1CLK
,
102 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_2
,
103 GLAMO_CLOCK_GEN52_EN_DIV_ICLK
,
105 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1
,
106 GLAMO_CLOCK_GEN51_EN_DIV_JCLK
,
108 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
109 GLAMO_HOSTBUS2_MMIO_EN_ISP
,
112 case GLAMO_ENGINE_CMDQ
:
113 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D
,
114 GLAMO_CLOCK_2D_EN_M6CLK
,
116 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
117 GLAMO_HOSTBUS2_MMIO_EN_CMDQ
,
120 case GLAMO_ENGINE_2D
:
121 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D
,
122 GLAMO_CLOCK_2D_EN_M7CLK
|
123 GLAMO_CLOCK_2D_EN_GCLK
|
124 GLAMO_CLOCK_2D_DG_M7CLK
|
125 GLAMO_CLOCK_2D_DG_GCLK
,
127 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
128 GLAMO_HOSTBUS2_MMIO_EN_2D
,
130 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1
,
131 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
136 engine_status
[engine
] |= STATUS_ENABLED
;
139 void glamo_hw_engine_disable(enum glamo_engine engine
)
141 if (!(engine_status
[engine
] & STATUS_ENABLED
))
145 case GLAMO_ENGINE_MPEG
:
146 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPEG
,
147 GLAMO_CLOCK_MPEG_EN_X6CLK
|
148 GLAMO_CLOCK_MPEG_DG_X6CLK
|
149 GLAMO_CLOCK_MPEG_EN_X4CLK
|
150 GLAMO_CLOCK_MPEG_DG_X4CLK
|
151 GLAMO_CLOCK_MPEG_EN_X2CLK
|
152 GLAMO_CLOCK_MPEG_DG_X2CLK
|
153 GLAMO_CLOCK_MPEG_EN_X0CLK
|
154 GLAMO_CLOCK_MPEG_DG_X0CLK
,
156 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC
,
157 GLAMO_CLOCK_MPROC_EN_M4CLK
,
159 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1
,
160 GLAMO_CLOCK_GEN51_EN_DIV_JCLK
,
162 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
163 GLAMO_HOSTBUS2_MMIO_EN_MPEG
|
164 GLAMO_HOSTBUS2_MMIO_EN_MICROP1
,
166 glamo_set_bit_mask(GLAMO_REG_CLOCK_MPROC
,
167 GLAMO_CLOCK_MPROC_EN_KCLK
,
170 case GLAMO_ENGINE_ISP
:
171 glamo_set_bit_mask(GLAMO_REG_CLOCK_ISP
,
172 GLAMO_CLOCK_ISP_EN_M2CLK
|
173 GLAMO_CLOCK_ISP_EN_I1CLK
,
175 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_2
,
176 GLAMO_CLOCK_GEN52_EN_DIV_ICLK
,
178 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1
,
179 GLAMO_CLOCK_GEN51_EN_DIV_JCLK
,
181 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
182 GLAMO_HOSTBUS2_MMIO_EN_ISP
,
185 case GLAMO_ENGINE_CMDQ
:
186 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D
,
187 GLAMO_CLOCK_2D_EN_M6CLK
,
189 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
190 GLAMO_HOSTBUS2_MMIO_EN_CMDQ
,
193 case GLAMO_ENGINE_2D
:
194 glamo_set_bit_mask(GLAMO_REG_CLOCK_2D
,
195 GLAMO_CLOCK_2D_EN_M7CLK
|
196 GLAMO_CLOCK_2D_EN_GCLK
|
197 GLAMO_CLOCK_2D_DG_M7CLK
|
198 GLAMO_CLOCK_2D_DG_GCLK
,
200 glamo_set_bit_mask(GLAMO_REG_HOSTBUS(2),
201 GLAMO_HOSTBUS2_MMIO_EN_2D
,
203 glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1
,
204 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
209 /* simply commented out; we don't want a clock manager to do things right */
210 //glamo_set_bit_mask(GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_MCLK, 0);
212 engine_status
[engine
] &= ~STATUS_ENABLED
;
215 void glamo_hw_dump(int reg
, int len
)
221 for (i
= 0; i
< len
; i
++, reg
+= 2)
223 val
= GLAMO_IN_REG(reg
);
225 printf("0x%06x: 0x%04x\n", reg
, val
);