1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright(c) 2002-2005 S2IO Technologies
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 * ring_num : This can be used to program the number of receive rings used
31 * frame_len: This is an array of size 8. Using this we can set the maximum
32 * size of the received frame that can be steered into the corrsponding
34 * ring_len: This defines the number of descriptors each ring can have. This
35 * is also an array of size 8.
36 * fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * latency_timer: This input is programmed into the Latency timer register
40 * in PCI Configuration space.
41 ************************************************************************/
43 #include<linux/config.h>
44 #include<linux/module.h>
45 #include<linux/types.h>
46 #include<linux/errno.h>
47 #include<linux/ioport.h>
49 #include<linux/kernel.h>
50 #include<linux/netdevice.h>
51 #include<linux/etherdevice.h>
52 #include<linux/skbuff.h>
53 #include<linux/init.h>
54 #include<linux/delay.h>
55 #include<linux/stddef.h>
56 #include<linux/ioctl.h>
57 #include<linux/timex.h>
58 #include<linux/sched.h>
59 #include<linux/ethtool.h>
60 #include<asm/system.h>
61 #include<asm/uaccess.h>
62 #include<linux/version.h>
64 #include<linux/workqueue.h>
68 #include "s2io-regs.h"
70 /* S2io Driver name & version. */
71 static char s2io_driver_name
[] = "s2io";
72 static char s2io_driver_version
[] = "Version 1.0";
74 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
75 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
76 #define TASKLET_IN_USE test_and_set_bit(0, \
77 (unsigned long *)(&sp->tasklet_status))
80 static inline int rx_buffer_level(nic_t
* sp
, int rxb_size
, int ring
)
83 if ((sp
->pkt_cnt
[ring
] - rxb_size
) > 128) {
85 if (rxb_size
< sp
->pkt_cnt
[ring
] / 8)
92 /* Ethtool related variables and Macros. */
93 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
94 "Register test\t(offline)",
95 "Eeprom test\t(offline)",
96 "Link test\t(online)",
97 "RLDRAM test\t(offline)",
98 "BIST Test\t(offline)"
101 static char ethtool_stats_keys
[][ETH_GSTRING_LEN
] = {
107 "tmac_pause_ctrl_frms",
109 "tmac_vld_ip_octets",
120 "rmac_vld_mcst_frms",
121 "rmac_vld_bcst_frms",
122 "rmac_in_rng_len_err_frms",
124 "rmac_pause_ctrl_frms",
125 "rmac_discarded_frms",
143 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
144 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
146 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
147 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
150 /* Constants to be programmed into the Xena's registers to configure
154 #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
157 static u64 default_mdio_cfg
[] = {
159 0xC001010000000000ULL
, 0xC0010100000000E0ULL
,
160 0xC0010100008000E4ULL
,
161 /* Remove Reset from PMA PLL */
162 0xC001010000000000ULL
, 0xC0010100000000E0ULL
,
163 0xC0010100000000E4ULL
,
167 static u64 default_dtx_cfg
[] = {
168 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
169 0x80000515D93500E4ULL
, 0x8001051500000000ULL
,
170 0x80010515000000E0ULL
, 0x80010515001E00E4ULL
,
171 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
172 0x80020515F21000E4ULL
,
173 /* Set PADLOOPBACKN */
174 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
175 0x80020515B20000E4ULL
, 0x8003051500000000ULL
,
176 0x80030515000000E0ULL
, 0x80030515B20000E4ULL
,
177 0x8004051500000000ULL
, 0x80040515000000E0ULL
,
178 0x80040515B20000E4ULL
, 0x8005051500000000ULL
,
179 0x80050515000000E0ULL
, 0x80050515B20000E4ULL
,
181 /* Remove PADLOOPBACKN */
182 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
183 0x80020515F20000E4ULL
, 0x8003051500000000ULL
,
184 0x80030515000000E0ULL
, 0x80030515F20000E4ULL
,
185 0x8004051500000000ULL
, 0x80040515000000E0ULL
,
186 0x80040515F20000E4ULL
, 0x8005051500000000ULL
,
187 0x80050515000000E0ULL
, 0x80050515F20000E4ULL
,
191 /* Constants for Fixing the MacAddress problem seen mostly on
194 static u64 fix_mac
[] = {
195 0x0060000000000000ULL
, 0x0060600000000000ULL
,
196 0x0040600000000000ULL
, 0x0000600000000000ULL
,
197 0x0020600000000000ULL
, 0x0060600000000000ULL
,
198 0x0020600000000000ULL
, 0x0060600000000000ULL
,
199 0x0020600000000000ULL
, 0x0060600000000000ULL
,
200 0x0020600000000000ULL
, 0x0060600000000000ULL
,
201 0x0020600000000000ULL
, 0x0060600000000000ULL
,
202 0x0020600000000000ULL
, 0x0060600000000000ULL
,
203 0x0020600000000000ULL
, 0x0060600000000000ULL
,
204 0x0020600000000000ULL
, 0x0060600000000000ULL
,
205 0x0020600000000000ULL
, 0x0060600000000000ULL
,
206 0x0020600000000000ULL
, 0x0060600000000000ULL
,
207 0x0020600000000000ULL
, 0x0000600000000000ULL
,
208 0x0040600000000000ULL
, 0x0060600000000000ULL
,
213 /* Module Loadable parameters. */
215 static u32 frame_len
[MAX_RX_RINGS
];
216 static u32 ring_len
[MAX_RX_RINGS
];
218 static u32 fifo_len
[MAX_TX_FIFOS
];
221 static u8 latency_timer
= 0;
225 * This table lists all the devices that this driver supports.
227 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
228 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
229 PCI_ANY_ID
, PCI_ANY_ID
},
230 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
231 PCI_ANY_ID
, PCI_ANY_ID
},
235 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
237 static struct pci_driver s2io_driver
= {
239 .id_table
= s2io_tbl
,
240 .probe
= s2io_init_nic
,
241 .remove
= __devexit_p(s2io_rem_nic
),
246 * Device private variable.
248 * SUCCESS on success and an appropriate -ve value on failure.
250 * The function allocates the all memory areas shared
251 * between the NIC and the driver. This includes Tx descriptors,
252 * Rx descriptors and the statistics block.
254 static int initSharedMem(struct s2io_nic
*nic
)
257 void *tmp_v_addr
, *tmp_v_addr_next
;
258 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
259 RxD_block_t
*pre_rxd_blk
= NULL
;
261 struct net_device
*dev
= nic
->dev
;
263 mac_info_t
*mac_control
;
264 struct config_param
*config
;
266 mac_control
= &nic
->mac_control
;
267 config
= &nic
->config
;
270 /* Allocation and initialization of TXDLs in FIOFs */
272 for (i
= 0; i
< config
->TxFIFONum
; i
++) {
273 size
+= config
->TxCfg
[i
].FifoLen
;
275 if (size
> MAX_AVAILABLE_TXDS
) {
276 DBG_PRINT(ERR_DBG
, "%s: Total number of Tx FIFOs ",
278 DBG_PRINT(ERR_DBG
, "exceeds the maximum value ");
279 DBG_PRINT(ERR_DBG
, "that can be used\n");
282 size
*= (sizeof(TxD_t
) * config
->MaxTxDs
);
284 mac_control
->txd_list_mem
= pci_alloc_consistent
285 (nic
->pdev
, size
, &mac_control
->txd_list_mem_phy
);
286 if (!mac_control
->txd_list_mem
) {
289 mac_control
->txd_list_mem_sz
= size
;
291 tmp_v_addr
= mac_control
->txd_list_mem
;
292 tmp_p_addr
= mac_control
->txd_list_mem_phy
;
293 memset(tmp_v_addr
, 0, size
);
295 DBG_PRINT(INIT_DBG
, "%s:List Mem PHY: 0x%llx\n", dev
->name
,
296 (unsigned long long) tmp_p_addr
);
298 for (i
= 0; i
< config
->TxFIFONum
; i
++) {
299 mac_control
->txdl_start_phy
[i
] = tmp_p_addr
;
300 mac_control
->txdl_start
[i
] = (TxD_t
*) tmp_v_addr
;
301 mac_control
->tx_curr_put_info
[i
].offset
= 0;
302 mac_control
->tx_curr_put_info
[i
].fifo_len
=
303 config
->TxCfg
[i
].FifoLen
- 1;
304 mac_control
->tx_curr_get_info
[i
].offset
= 0;
305 mac_control
->tx_curr_get_info
[i
].fifo_len
=
306 config
->TxCfg
[i
].FifoLen
- 1;
309 (config
->TxCfg
[i
].FifoLen
* (sizeof(TxD_t
)) *
312 (config
->TxCfg
[i
].FifoLen
* (sizeof(TxD_t
)) *
316 /* Allocation and initialization of RXDs in Rings */
318 for (i
= 0; i
< config
->RxRingNum
; i
++) {
319 if (config
->RxCfg
[i
].NumRxd
% (MAX_RXDS_PER_BLOCK
+ 1)) {
320 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
321 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
323 DBG_PRINT(ERR_DBG
, "RxDs per Block");
326 size
+= config
->RxCfg
[i
].NumRxd
;
327 nic
->block_count
[i
] =
328 config
->RxCfg
[i
].NumRxd
/ (MAX_RXDS_PER_BLOCK
+ 1);
330 config
->RxCfg
[i
].NumRxd
- nic
->block_count
[i
];
332 size
= (size
* (sizeof(RxD_t
)));
333 mac_control
->rxd_ring_mem_sz
= size
;
335 for (i
= 0; i
< config
->RxRingNum
; i
++) {
336 mac_control
->rx_curr_get_info
[i
].block_index
= 0;
337 mac_control
->rx_curr_get_info
[i
].offset
= 0;
338 mac_control
->rx_curr_get_info
[i
].ring_len
=
339 config
->RxCfg
[i
].NumRxd
- 1;
340 mac_control
->rx_curr_put_info
[i
].block_index
= 0;
341 mac_control
->rx_curr_put_info
[i
].offset
= 0;
342 mac_control
->rx_curr_put_info
[i
].ring_len
=
343 config
->RxCfg
[i
].NumRxd
- 1;
345 config
->RxCfg
[i
].NumRxd
/ (MAX_RXDS_PER_BLOCK
+ 1);
346 /* Allocating all the Rx blocks */
347 for (j
= 0; j
< blk_cnt
; j
++) {
348 size
= (MAX_RXDS_PER_BLOCK
+ 1) * (sizeof(RxD_t
));
349 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
351 if (tmp_v_addr
== NULL
) {
352 /* In case of failure, freeSharedMem()
353 * is called, which should free any
354 * memory that was alloced till the
357 nic
->rx_blocks
[i
][j
].block_virt_addr
=
361 memset(tmp_v_addr
, 0, size
);
362 nic
->rx_blocks
[i
][j
].block_virt_addr
= tmp_v_addr
;
363 nic
->rx_blocks
[i
][j
].block_dma_addr
= tmp_p_addr
;
365 /* Interlinking all Rx Blocks */
366 for (j
= 0; j
< blk_cnt
; j
++) {
367 tmp_v_addr
= nic
->rx_blocks
[i
][j
].block_virt_addr
;
369 nic
->rx_blocks
[i
][(j
+ 1) %
370 blk_cnt
].block_virt_addr
;
371 tmp_p_addr
= nic
->rx_blocks
[i
][j
].block_dma_addr
;
373 nic
->rx_blocks
[i
][(j
+ 1) %
374 blk_cnt
].block_dma_addr
;
376 pre_rxd_blk
= (RxD_block_t
*) tmp_v_addr
;
377 pre_rxd_blk
->reserved_1
= END_OF_BLOCK
; /* last RxD
380 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
381 (unsigned long) tmp_v_addr_next
;
382 pre_rxd_blk
->pNext_RxD_Blk_physical
=
383 (u64
) tmp_p_addr_next
;
387 /* Allocation and initialization of Statistics block */
388 size
= sizeof(StatInfo_t
);
389 mac_control
->stats_mem
= pci_alloc_consistent
390 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
392 if (!mac_control
->stats_mem
) {
393 /* In case of failure, freeSharedMem() is called, which
394 * should free any memory that was alloced till the
399 mac_control
->stats_mem_sz
= size
;
401 tmp_v_addr
= mac_control
->stats_mem
;
402 mac_control
->StatsInfo
= (StatInfo_t
*) tmp_v_addr
;
403 memset(tmp_v_addr
, 0, size
);
405 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
406 (unsigned long long) tmp_p_addr
);
413 * Device peivate variable.
417 * This function is to free all memory locations allocated by
418 * the initSharedMem() function and return it to the kernel.
420 static void freeSharedMem(struct s2io_nic
*nic
)
422 int i
, j
, blk_cnt
, size
;
424 dma_addr_t tmp_p_addr
;
425 mac_info_t
*mac_control
;
426 struct config_param
*config
;
432 mac_control
= &nic
->mac_control
;
433 config
= &nic
->config
;
435 if (mac_control
->txd_list_mem
) {
436 pci_free_consistent(nic
->pdev
,
437 mac_control
->txd_list_mem_sz
,
438 mac_control
->txd_list_mem
,
439 mac_control
->txd_list_mem_phy
);
442 size
= (MAX_RXDS_PER_BLOCK
+ 1) * (sizeof(RxD_t
));
443 for (i
= 0; i
< config
->RxRingNum
; i
++) {
444 blk_cnt
= nic
->block_count
[i
];
445 for (j
= 0; j
< blk_cnt
; j
++) {
446 tmp_v_addr
= nic
->rx_blocks
[i
][j
].block_virt_addr
;
447 tmp_p_addr
= nic
->rx_blocks
[i
][j
].block_dma_addr
;
448 if (tmp_v_addr
== NULL
)
450 pci_free_consistent(nic
->pdev
, size
,
451 tmp_v_addr
, tmp_p_addr
);
455 if (mac_control
->stats_mem
) {
456 pci_free_consistent(nic
->pdev
,
457 mac_control
->stats_mem_sz
,
458 mac_control
->stats_mem
,
459 mac_control
->stats_mem_phy
);
465 * device peivate variable
467 * SUCCESS on success and '-1' on failure (endian settings incorrect).
469 * The function sequentially configures every block
470 * of the H/W from their reset values.
472 static int initNic(struct s2io_nic
*nic
)
474 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
475 struct net_device
*dev
= nic
->dev
;
476 register u64 val64
= 0;
480 mac_info_t
*mac_control
;
481 struct config_param
*config
;
482 int mdio_cnt
= 0, dtx_cnt
= 0;
483 unsigned long long print_var
, mem_share
;
485 mac_control
= &nic
->mac_control
;
486 config
= &nic
->config
;
488 /* Set proper endian settings and verify the same by
489 * reading the PIF Feed-back register.
492 /* The device by default set to a big endian format, so
493 * a big endian driver need not set anything.
495 writeq(0xffffffffffffffffULL
, &bar0
->swapper_ctrl
);
496 val64
= (SWAPPER_CTRL_PIF_R_FE
|
497 SWAPPER_CTRL_PIF_R_SE
|
498 SWAPPER_CTRL_PIF_W_FE
|
499 SWAPPER_CTRL_PIF_W_SE
|
500 SWAPPER_CTRL_TXP_FE
|
501 SWAPPER_CTRL_TXP_SE
|
502 SWAPPER_CTRL_TXD_R_FE
|
503 SWAPPER_CTRL_TXD_W_FE
|
504 SWAPPER_CTRL_TXF_R_FE
|
505 SWAPPER_CTRL_RXD_R_FE
|
506 SWAPPER_CTRL_RXD_W_FE
|
507 SWAPPER_CTRL_RXF_W_FE
|
508 SWAPPER_CTRL_XMSI_FE
|
509 SWAPPER_CTRL_XMSI_SE
|
510 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
511 writeq(val64
, &bar0
->swapper_ctrl
);
513 /* Initially we enable all bits to make it accessible by
514 * the driver, then we selectively enable only those bits
515 * that we want to set.
517 writeq(0xffffffffffffffffULL
, &bar0
->swapper_ctrl
);
518 val64
= (SWAPPER_CTRL_PIF_R_FE
|
519 SWAPPER_CTRL_PIF_R_SE
|
520 SWAPPER_CTRL_PIF_W_FE
|
521 SWAPPER_CTRL_PIF_W_SE
|
522 SWAPPER_CTRL_TXP_FE
|
523 SWAPPER_CTRL_TXP_SE
|
524 SWAPPER_CTRL_TXD_R_FE
|
525 SWAPPER_CTRL_TXD_R_SE
|
526 SWAPPER_CTRL_TXD_W_FE
|
527 SWAPPER_CTRL_TXD_W_SE
|
528 SWAPPER_CTRL_TXF_R_FE
|
529 SWAPPER_CTRL_RXD_R_FE
|
530 SWAPPER_CTRL_RXD_R_SE
|
531 SWAPPER_CTRL_RXD_W_FE
|
532 SWAPPER_CTRL_RXD_W_SE
|
533 SWAPPER_CTRL_RXF_W_FE
|
534 SWAPPER_CTRL_XMSI_FE
|
535 SWAPPER_CTRL_XMSI_SE
|
536 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
537 writeq(val64
, &bar0
->swapper_ctrl
);
540 /* Verifying if endian settings are accurate by reading
541 * a feedback register.
543 val64
= readq(&bar0
->pif_rd_swapper_fb
);
544 if (val64
!= 0x0123456789ABCDEFULL
) {
545 /* Endian settings are incorrect, calls for another dekko. */
546 print_var
= (unsigned long long) val64
;
547 DBG_PRINT(INIT_DBG
, "%s: Endian settings are wrong",
549 DBG_PRINT(ERR_DBG
, ", feedback read %llx\n", print_var
);
554 /* Remove XGXS from reset state */
556 writeq(val64
, &bar0
->sw_reset
);
557 val64
= readq(&bar0
->sw_reset
);
558 set_current_state(TASK_UNINTERRUPTIBLE
);
559 schedule_timeout(HZ
/ 2);
561 /* Enable Receiving broadcasts */
562 val64
= readq(&bar0
->mac_cfg
);
563 val64
|= MAC_RMAC_BCAST_ENABLE
;
564 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
565 writeq(val64
, &bar0
->mac_cfg
);
567 /* Read registers in all blocks */
568 val64
= readq(&bar0
->mac_int_mask
);
569 val64
= readq(&bar0
->mc_int_mask
);
570 val64
= readq(&bar0
->xgxs_int_mask
);
574 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
576 /* Configuring the XAUI Interface of Xena.
577 *****************************************
578 * To Configure the Xena's XAUI, one has to write a series
579 * of 64 bit values into two registers in a particular
580 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
581 * which will be defined in the array of configuration values
582 * (default_dtx_cfg & default_mdio_cfg) at appropriate places
583 * to switch writing from one regsiter to another. We continue
584 * writing these values until we encounter the 'END_SIGN' macro.
585 * For example, After making a series of 21 writes into
586 * dtx_control register the 'SWITCH_SIGN' appears and hence we
587 * start writing into mdio_control until we encounter END_SIGN.
591 while (default_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
592 if (default_dtx_cfg
[dtx_cnt
] == SWITCH_SIGN
) {
596 writeq(default_dtx_cfg
[dtx_cnt
],
598 val64
= readq(&bar0
->dtx_control
);
602 while (default_mdio_cfg
[mdio_cnt
] != END_SIGN
) {
603 if (default_mdio_cfg
[mdio_cnt
] == SWITCH_SIGN
) {
607 writeq(default_mdio_cfg
[mdio_cnt
],
608 &bar0
->mdio_control
);
609 val64
= readq(&bar0
->mdio_control
);
612 if ((default_dtx_cfg
[dtx_cnt
] == END_SIGN
) &&
613 (default_mdio_cfg
[mdio_cnt
] == END_SIGN
)) {
620 /* Tx DMA Initialization */
622 writeq(val64
, &bar0
->tx_fifo_partition_0
);
623 writeq(val64
, &bar0
->tx_fifo_partition_1
);
624 writeq(val64
, &bar0
->tx_fifo_partition_2
);
625 writeq(val64
, &bar0
->tx_fifo_partition_3
);
628 for (i
= 0, j
= 0; i
< config
->TxFIFONum
; i
++) {
630 vBIT(config
->TxCfg
[i
].FifoLen
- 1, ((i
* 32) + 19),
631 13) | vBIT(config
->TxCfg
[i
].FifoPriority
,
634 if (i
== (config
->TxFIFONum
- 1)) {
641 writeq(val64
, &bar0
->tx_fifo_partition_0
);
645 writeq(val64
, &bar0
->tx_fifo_partition_1
);
649 writeq(val64
, &bar0
->tx_fifo_partition_2
);
653 writeq(val64
, &bar0
->tx_fifo_partition_3
);
658 /* Enable Tx FIFO partition 0. */
659 val64
= readq(&bar0
->tx_fifo_partition_0
);
660 val64
|= BIT(0); /* To enable the FIFO partition. */
661 writeq(val64
, &bar0
->tx_fifo_partition_0
);
663 val64
= readq(&bar0
->tx_fifo_partition_0
);
664 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
665 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
668 * Initialization of Tx_PA_CONFIG register to ignore packet
669 * integrity checking.
671 val64
= readq(&bar0
->tx_pa_cfg
);
672 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
673 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
674 writeq(val64
, &bar0
->tx_pa_cfg
);
676 /* Rx DMA intialization. */
678 for (i
= 0; i
< config
->RxRingNum
; i
++) {
680 vBIT(config
->RxCfg
[i
].RingPriority
, (5 + (i
* 8)), 3);
682 writeq(val64
, &bar0
->rx_queue_priority
);
684 /* Allocating equal share of memory to all the configured
688 for (i
= 0; i
< config
->RxRingNum
; i
++) {
691 mem_share
= (64 / config
->RxRingNum
+
692 64 % config
->RxRingNum
);
693 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
696 mem_share
= (64 / config
->RxRingNum
);
697 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
700 mem_share
= (64 / config
->RxRingNum
);
701 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
704 mem_share
= (64 / config
->RxRingNum
);
705 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
708 mem_share
= (64 / config
->RxRingNum
);
709 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
712 mem_share
= (64 / config
->RxRingNum
);
713 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
716 mem_share
= (64 / config
->RxRingNum
);
717 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
720 mem_share
= (64 / config
->RxRingNum
);
721 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
725 writeq(val64
, &bar0
->rx_queue_cfg
);
727 /* Initializing the Tx round robin registers to 0.
728 * Filling Tx and Rx round robin registers as per the
729 * number of FIFOs and Rings is still TODO.
731 writeq(0, &bar0
->tx_w_round_robin_0
);
732 writeq(0, &bar0
->tx_w_round_robin_1
);
733 writeq(0, &bar0
->tx_w_round_robin_2
);
734 writeq(0, &bar0
->tx_w_round_robin_3
);
735 writeq(0, &bar0
->tx_w_round_robin_4
);
737 /* Disable Rx steering. Hard coding all packets be steered to
741 u64 def
= 0x8000000000000000ULL
, tmp
;
742 for (i
= 0; i
< MAX_RX_RINGS
; i
++) {
743 tmp
= (u64
) (def
>> (i
% config
->RxRingNum
));
744 val64
|= (u64
) (tmp
>> (i
* 8));
746 writeq(val64
, &bar0
->rts_qos_steering
);
748 val64
= 0x8080808080808080ULL
;
749 writeq(val64
, &bar0
->rts_qos_steering
);
754 for (i
= 1; i
< 8; i
++)
755 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
757 /* Set rts_frm_len register for fifo 0 */
758 writeq(MAC_RTS_FRM_LEN_SET(dev
->mtu
+ 22),
759 &bar0
->rts_frm_len_n
[0]);
761 /* Enable statistics */
762 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
763 val64
= SET_UPDT_PERIOD(8) | STAT_CFG_STAT_RO
| STAT_CFG_STAT_EN
;
764 writeq(val64
, &bar0
->stat_cfg
);
766 /* Initializing the sampling rate for the device to calculate the
767 * bandwidth utilization.
769 val64
= MAC_TX_LINK_UTIL_VAL(0x5) | MAC_RX_LINK_UTIL_VAL(0x5);
770 writeq(val64
, &bar0
->mac_link_util
);
773 /* Initializing the Transmit and Receive Traffic Interrupt
776 /* TTI Initialization */
777 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0xFFF) |
778 TTI_DATA1_MEM_TX_URNG_A(0xA) | TTI_DATA1_MEM_TX_URNG_B(0x10) |
779 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN
;
780 writeq(val64
, &bar0
->tti_data1_mem
);
783 TTI_DATA2_MEM_TX_UFC_A(0x10) | TTI_DATA2_MEM_TX_UFC_B(0x20) |
784 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
785 writeq(val64
, &bar0
->tti_data2_mem
);
787 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
788 writeq(val64
, &bar0
->tti_command_mem
);
790 /* Once the operation completes, the Strobe bit of the command
791 * register will be reset. We poll for this particular condition
792 * We wait for a maximum of 500ms for the operation to complete,
793 * if it's not complete by then we return error.
797 val64
= readq(&bar0
->tti_command_mem
);
798 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
802 DBG_PRINT(ERR_DBG
, "%s: TTI init Failed\n",
806 set_current_state(TASK_UNINTERRUPTIBLE
);
807 schedule_timeout(HZ
/ 20);
811 /* RTI Initialization */
812 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) |
813 RTI_DATA1_MEM_RX_URNG_A(0xA) | RTI_DATA1_MEM_RX_URNG_B(0x10) |
814 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
815 writeq(val64
, &bar0
->rti_data1_mem
);
817 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) | RTI_DATA2_MEM_RX_UFC_B(0x2) |
818 RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
819 writeq(val64
, &bar0
->rti_data2_mem
);
821 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
;
822 writeq(val64
, &bar0
->rti_command_mem
);
824 /* Once the operation completes, the Strobe bit of the command
825 * register will be reset. We poll for this particular condition
826 * We wait for a maximum of 500ms for the operation to complete,
827 * if it's not complete by then we return error.
831 val64
= readq(&bar0
->rti_command_mem
);
832 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
836 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
841 set_current_state(TASK_UNINTERRUPTIBLE
);
842 schedule_timeout(HZ
/ 20);
845 /* Initializing proper values as Pause threshold into all
846 * the 8 Queues on Rx side.
848 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
849 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
851 /* Disable RMAC PAD STRIPPING */
852 add
= (void *) &bar0
->mac_cfg
;
853 val64
= readq(&bar0
->mac_cfg
);
854 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
855 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
856 writel((u32
) (val64
), add
);
857 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
858 writel((u32
) (val64
>> 32), (add
+ 4));
859 val64
= readq(&bar0
->mac_cfg
);
866 * device private variable,
867 * A mask indicating which Intr block must be modified and,
868 * A flag indicating whether to enable or disable the Intrs.
872 * This function will either disable or enable the interrupts
873 * depending on the flag argument. The mask argument can be used to
874 * enable/disable any Intr block.
876 static void en_dis_able_NicIntrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
878 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
879 register u64 val64
= 0, temp64
= 0;
881 /* Top level interrupt classification */
883 if ((mask
& (TX_PIC_INTR
| RX_PIC_INTR
))) {
884 /* Enable PIC Intrs in the general intr mask register */
885 val64
= TXPIC_INT_M
| PIC_RX_INT_M
;
886 if (flag
== ENABLE_INTRS
) {
887 temp64
= readq(&bar0
->general_int_mask
);
888 temp64
&= ~((u64
) val64
);
889 writeq(temp64
, &bar0
->general_int_mask
);
890 /* Disabled all PCIX, Flash, MDIO, IIC and GPIO
891 * interrupts for now.
893 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
894 /* No MSI Support is available presently, so TTI and
895 * RTI interrupts are also disabled.
897 } else if (flag
== DISABLE_INTRS
) {
898 /* Disable PIC Intrs in the general intr mask register
900 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
901 temp64
= readq(&bar0
->general_int_mask
);
903 writeq(val64
, &bar0
->general_int_mask
);
908 /* Enabling/Disabling Tx DMA interrupts */
909 if (mask
& TX_DMA_INTR
) {
910 /* Enable TxDMA Intrs in the general intr mask register */
912 if (flag
== ENABLE_INTRS
) {
913 temp64
= readq(&bar0
->general_int_mask
);
914 temp64
&= ~((u64
) val64
);
915 writeq(temp64
, &bar0
->general_int_mask
);
916 /* Disable all interrupts other than PFC interrupt in
919 val64
= DISABLE_ALL_INTRS
& (~TXDMA_PFC_INT_M
);
920 writeq(val64
, &bar0
->txdma_int_mask
);
921 /* Enable only the MISC error 1 interrupt in PFC block
923 val64
= DISABLE_ALL_INTRS
& (~PFC_MISC_ERR_1
);
924 writeq(val64
, &bar0
->pfc_err_mask
);
925 } else if (flag
== DISABLE_INTRS
) {
926 /* Disable TxDMA Intrs in the general intr mask
928 writeq(DISABLE_ALL_INTRS
, &bar0
->txdma_int_mask
);
929 writeq(DISABLE_ALL_INTRS
, &bar0
->pfc_err_mask
);
930 temp64
= readq(&bar0
->general_int_mask
);
932 writeq(val64
, &bar0
->general_int_mask
);
936 /* Enabling/Disabling Rx DMA interrupts */
937 if (mask
& RX_DMA_INTR
) {
938 /* Enable RxDMA Intrs in the general intr mask register */
940 if (flag
== ENABLE_INTRS
) {
941 temp64
= readq(&bar0
->general_int_mask
);
942 temp64
&= ~((u64
) val64
);
943 writeq(temp64
, &bar0
->general_int_mask
);
944 /* All RxDMA block interrupts are disabled for now
946 writeq(DISABLE_ALL_INTRS
, &bar0
->rxdma_int_mask
);
947 } else if (flag
== DISABLE_INTRS
) {
948 /* Disable RxDMA Intrs in the general intr mask
950 writeq(DISABLE_ALL_INTRS
, &bar0
->rxdma_int_mask
);
951 temp64
= readq(&bar0
->general_int_mask
);
953 writeq(val64
, &bar0
->general_int_mask
);
958 /* Enabling/Disabling MAC interrupts */
959 if (mask
& (TX_MAC_INTR
| RX_MAC_INTR
)) {
960 val64
= TXMAC_INT_M
| RXMAC_INT_M
;
961 if (flag
== ENABLE_INTRS
) {
962 temp64
= readq(&bar0
->general_int_mask
);
963 temp64
&= ~((u64
) val64
);
964 writeq(temp64
, &bar0
->general_int_mask
);
965 /* All MAC block error interrupts are disabled for now
966 * except the link status change interrupt.
968 val64
= MAC_INT_STATUS_RMAC_INT
;
969 temp64
= readq(&bar0
->mac_int_mask
);
970 temp64
&= ~((u64
) val64
);
971 writeq(temp64
, &bar0
->mac_int_mask
);
973 val64
= readq(&bar0
->mac_rmac_err_mask
);
974 val64
&= ~((u64
) RMAC_LINK_STATE_CHANGE_INT
);
975 writeq(val64
, &bar0
->mac_rmac_err_mask
);
976 } else if (flag
== DISABLE_INTRS
) {
977 /* Disable MAC Intrs in the general intr mask register
979 writeq(DISABLE_ALL_INTRS
, &bar0
->mac_int_mask
);
980 writeq(DISABLE_ALL_INTRS
,
981 &bar0
->mac_rmac_err_mask
);
983 temp64
= readq(&bar0
->general_int_mask
);
985 writeq(val64
, &bar0
->general_int_mask
);
989 /* XGXS Interrupts */
990 if (mask
& (TX_XGXS_INTR
| RX_XGXS_INTR
)) {
991 val64
= TXXGXS_INT_M
| RXXGXS_INT_M
;
992 if (flag
== ENABLE_INTRS
) {
993 temp64
= readq(&bar0
->general_int_mask
);
994 temp64
&= ~((u64
) val64
);
995 writeq(temp64
, &bar0
->general_int_mask
);
996 /* All XGXS block error interrupts are disabled for now
998 writeq(DISABLE_ALL_INTRS
, &bar0
->xgxs_int_mask
);
999 } else if (flag
== DISABLE_INTRS
) {
1000 /* Disable MC Intrs in the general intr mask register
1002 writeq(DISABLE_ALL_INTRS
, &bar0
->xgxs_int_mask
);
1003 temp64
= readq(&bar0
->general_int_mask
);
1005 writeq(val64
, &bar0
->general_int_mask
);
1009 /* Memory Controller(MC) interrupts */
1010 if (mask
& MC_INTR
) {
1012 if (flag
== ENABLE_INTRS
) {
1013 temp64
= readq(&bar0
->general_int_mask
);
1014 temp64
&= ~((u64
) val64
);
1015 writeq(temp64
, &bar0
->general_int_mask
);
1016 /* All MC block error interrupts are disabled for now
1018 writeq(DISABLE_ALL_INTRS
, &bar0
->mc_int_mask
);
1019 } else if (flag
== DISABLE_INTRS
) {
1020 /* Disable MC Intrs in the general intr mask register
1022 writeq(DISABLE_ALL_INTRS
, &bar0
->mc_int_mask
);
1023 temp64
= readq(&bar0
->general_int_mask
);
1025 writeq(val64
, &bar0
->general_int_mask
);
1030 /* Tx traffic interrupts */
1031 if (mask
& TX_TRAFFIC_INTR
) {
1032 val64
= TXTRAFFIC_INT_M
;
1033 if (flag
== ENABLE_INTRS
) {
1034 temp64
= readq(&bar0
->general_int_mask
);
1035 temp64
&= ~((u64
) val64
);
1036 writeq(temp64
, &bar0
->general_int_mask
);
1037 /* Enable all the Tx side interrupts */
1038 writeq(0x0, &bar0
->tx_traffic_mask
); /* '0' Enables
1043 } else if (flag
== DISABLE_INTRS
) {
1044 /* Disable Tx Traffic Intrs in the general intr mask
1047 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
1048 temp64
= readq(&bar0
->general_int_mask
);
1050 writeq(val64
, &bar0
->general_int_mask
);
1054 /* Rx traffic interrupts */
1055 if (mask
& RX_TRAFFIC_INTR
) {
1056 val64
= RXTRAFFIC_INT_M
;
1057 if (flag
== ENABLE_INTRS
) {
1058 temp64
= readq(&bar0
->general_int_mask
);
1059 temp64
&= ~((u64
) val64
);
1060 writeq(temp64
, &bar0
->general_int_mask
);
1061 writeq(0x0, &bar0
->rx_traffic_mask
); /* '0' Enables
1066 } else if (flag
== DISABLE_INTRS
) {
1067 /* Disable Rx Traffic Intrs in the general intr mask
1070 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
1071 temp64
= readq(&bar0
->general_int_mask
);
1073 writeq(val64
, &bar0
->general_int_mask
);
1080 * val64 - Value read from adapter status register.
1081 * flag - indicates if the adapter enable bit was ever written once before.
1085 * Returns whether the H/W is ready to go or not. Depending on whether
1086 * adapter enable bit was written or not the comparison differs and the
1087 * calling function passes the input argument flag to indicate this.
1089 static int verify_xena_quiescence(u64 val64
, int flag
)
1092 u64 tmp64
= ~((u64
) val64
);
1096 (ADAPTER_STATUS_TDMA_READY
| ADAPTER_STATUS_RDMA_READY
|
1097 ADAPTER_STATUS_PFC_READY
| ADAPTER_STATUS_TMAC_BUF_EMPTY
|
1098 ADAPTER_STATUS_PIC_QUIESCENT
| ADAPTER_STATUS_MC_DRAM_READY
|
1099 ADAPTER_STATUS_MC_QUEUES_READY
| ADAPTER_STATUS_M_PLL_LOCK
|
1100 ADAPTER_STATUS_P_PLL_LOCK
))) {
1101 if (flag
== FALSE
) {
1102 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) &&
1103 ((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1104 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
1110 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
1111 ADAPTER_STATUS_RMAC_PCC_IDLE
) &&
1112 (!(val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ||
1113 ((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1114 ADAPTER_STATUS_RC_PRC_QUIESCENT
))) {
1126 * New procedure to clear mac address reading problems on Alpha platforms
1129 void FixMacAddress(nic_t
* sp
)
1131 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
1135 while (fix_mac
[i
] != END_SIGN
) {
1136 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
1137 val64
= readq(&bar0
->gpio_control
);
1143 * device private variable.
1145 * SUCCESS on success and -1 on failure.
1147 * This function actually turns the device on. Before this
1148 * function is called, all Registers are configured from their reset states
1149 * and shared memory is allocated but the NIC is still quiescent. On
1150 * calling this function, the device interrupts are cleared and the NIC is
1151 * literally switched on by writing into the adapter control register.
1153 static int startNic(struct s2io_nic
*nic
)
1155 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
1156 struct net_device
*dev
= nic
->dev
;
1157 register u64 val64
= 0;
1158 u16 interruptible
, i
;
1160 mac_info_t
*mac_control
;
1161 struct config_param
*config
;
1163 mac_control
= &nic
->mac_control
;
1164 config
= &nic
->config
;
1166 /* PRC Initialization and configuration */
1167 for (i
= 0; i
< config
->RxRingNum
; i
++) {
1168 writeq((u64
) nic
->rx_blocks
[i
][0].block_dma_addr
,
1169 &bar0
->prc_rxd0_n
[i
]);
1171 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
1172 val64
|= PRC_CTRL_RC_ENABLED
;
1173 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
1176 /* Enabling MC-RLDRAM. After enabling the device, we timeout
1177 * for around 100ms, which is approximately the time required
1178 * for the device to be ready for operation.
1180 val64
= readq(&bar0
->mc_rldram_mrs
);
1181 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
1182 writeq(val64
, &bar0
->mc_rldram_mrs
);
1183 val64
= readq(&bar0
->mc_rldram_mrs
);
1185 set_current_state(TASK_UNINTERRUPTIBLE
);
1186 schedule_timeout(HZ
/ 10); /* Delay by around 100 ms. */
1188 /* Enabling ECC Protection. */
1189 val64
= readq(&bar0
->adapter_control
);
1190 val64
&= ~ADAPTER_ECC_EN
;
1191 writeq(val64
, &bar0
->adapter_control
);
1193 /* Clearing any possible Link state change interrupts that
1194 * could have popped up just before Enabling the card.
1196 val64
= readq(&bar0
->mac_rmac_err_reg
);
1198 writeq(val64
, &bar0
->mac_rmac_err_reg
);
1200 /* Verify if the device is ready to be enabled, if so enable
1203 val64
= readq(&bar0
->adapter_status
);
1204 if (!verify_xena_quiescence(val64
, nic
->device_enabled_once
)) {
1205 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
1206 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
1207 (unsigned long long) val64
);
1211 /* Enable select interrupts */
1212 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
| TX_MAC_INTR
|
1214 en_dis_able_NicIntrs(nic
, interruptible
, ENABLE_INTRS
);
1216 /* With some switches, link might be already up at this point.
1217 * Because of this weird behavior, when we enable laser,
1218 * we may not get link. We need to handle this. We cannot
1219 * figure out which switch is misbehaving. So we are forced to
1220 * make a global change.
1223 /* Enabling Laser. */
1224 val64
= readq(&bar0
->adapter_control
);
1225 val64
|= ADAPTER_EOI_TX_ON
;
1226 writeq(val64
, &bar0
->adapter_control
);
1228 /* SXE-002: Initialize link and activity LED */
1229 subid
= nic
->pdev
->subsystem_device
;
1230 if ((subid
& 0xFF) >= 0x07) {
1231 val64
= readq(&bar0
->gpio_control
);
1232 val64
|= 0x0000800000000000ULL
;
1233 writeq(val64
, &bar0
->gpio_control
);
1234 val64
= 0x0411040400000000ULL
;
1235 writeq(val64
, (void *) ((u8
*) bar0
+ 0x2700));
1239 * Here we are performing soft reset on XGXS to
1240 * force link down. Since link is already up, we will get
1241 * link state change interrupt after this reset
1243 writeq(0x8007051500000000ULL
, &bar0
->dtx_control
);
1244 val64
= readq(&bar0
->dtx_control
);
1245 writeq(0x80070515000000E0ULL
, &bar0
->dtx_control
);
1246 val64
= readq(&bar0
->dtx_control
);
1247 writeq(0x80070515001F00E4ULL
, &bar0
->dtx_control
);
1248 val64
= readq(&bar0
->dtx_control
);
1255 * nic - device private variable.
1259 * Free all queued Tx buffers.
1261 void freeTxBuffers(struct s2io_nic
*nic
)
1263 struct net_device
*dev
= nic
->dev
;
1264 struct sk_buff
*skb
;
1270 mac_info_t
*mac_control
;
1271 struct config_param
*config
;
1273 mac_control
= &nic
->mac_control
;
1274 config
= &nic
->config
;
1276 for (i
= 0; i
< config
->TxFIFONum
; i
++) {
1277 for (j
= 0; j
< config
->TxCfg
[i
].FifoLen
- 1; j
++) {
1278 txdp
= mac_control
->txdl_start
[i
] +
1279 (config
->MaxTxDs
* j
);
1281 if (!(txdp
->Control_1
& TXD_LIST_OWN_XENA
)) {
1282 /* If owned by host, ignore */
1286 (struct sk_buff
*) ((unsigned long) txdp
->
1289 DBG_PRINT(ERR_DBG
, "%s: NULL skb ",
1291 DBG_PRINT(ERR_DBG
, "in Tx Int\n");
1298 memset(txdp
, 0, sizeof(TxD_t
));
1302 "%s:forcibly freeing %d skbs on FIFO%d\n",
1310 * nic - device private variable.
1314 * This function does exactly the opposite of what the startNic()
1315 * function does. This function is called to stop
1318 static void stopNic(struct s2io_nic
*nic
)
1320 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
1321 register u64 val64
= 0;
1322 u16 interruptible
, i
;
1323 mac_info_t
*mac_control
;
1324 struct config_param
*config
;
1326 mac_control
= &nic
->mac_control
;
1327 config
= &nic
->config
;
1329 /* Disable all interrupts */
1330 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
| TX_MAC_INTR
|
1332 en_dis_able_NicIntrs(nic
, interruptible
, DISABLE_INTRS
);
1335 for (i
= 0; i
< config
->RxRingNum
; i
++) {
1336 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
1337 val64
&= ~((u64
) PRC_CTRL_RC_ENABLED
);
1338 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
1344 * device private variable
1346 * SUCCESS on success or an appropriate -ve value on failure.
1348 * The function allocates Rx side skbs and puts the physical
1349 * address of these buffers into the RxD buffer pointers, so that the NIC
1350 * can DMA the received frame into these locations.
1351 * The NIC supports 3 receive modes, viz
1353 * 2. three buffer and
1354 * 3. Five buffer modes.
1355 * Each mode defines how many fragments the received frame will be split
1356 * up into by the NIC. The frame is split into L3 header, L4 Header,
1357 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
1358 * is split into 3 fragments. As of now only single buffer mode is supported.
1360 int fill_rx_buffers(struct s2io_nic
*nic
, int ring_no
)
1362 struct net_device
*dev
= nic
->dev
;
1363 struct sk_buff
*skb
;
1365 int off
, off1
, size
, block_no
, block_no1
;
1366 int offset
, offset1
;
1368 u32 alloc_cnt
= nic
->pkt_cnt
[ring_no
] -
1369 atomic_read(&nic
->rx_bufs_left
[ring_no
]);
1370 mac_info_t
*mac_control
;
1371 struct config_param
*config
;
1373 mac_control
= &nic
->mac_control
;
1374 config
= &nic
->config
;
1376 if (frame_len
[ring_no
]) {
1377 if (frame_len
[ring_no
] > dev
->mtu
)
1378 dev
->mtu
= frame_len
[ring_no
];
1379 size
= frame_len
[ring_no
] + HEADER_ETHERNET_II_802_3_SIZE
+
1380 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
1382 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
1383 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
1386 while (alloc_tab
< alloc_cnt
) {
1387 block_no
= mac_control
->rx_curr_put_info
[ring_no
].
1389 block_no1
= mac_control
->rx_curr_get_info
[ring_no
].
1391 off
= mac_control
->rx_curr_put_info
[ring_no
].offset
;
1392 off1
= mac_control
->rx_curr_get_info
[ring_no
].offset
;
1393 offset
= block_no
* (MAX_RXDS_PER_BLOCK
+ 1) + off
;
1394 offset1
= block_no1
* (MAX_RXDS_PER_BLOCK
+ 1) + off1
;
1396 rxdp
= nic
->rx_blocks
[ring_no
][block_no
].
1397 block_virt_addr
+ off
;
1398 if ((offset
== offset1
) && (rxdp
->Host_Control
)) {
1399 DBG_PRINT(INTR_DBG
, "%s: Get and Put", dev
->name
);
1400 DBG_PRINT(INTR_DBG
, " info equated\n");
1404 if (rxdp
->Control_1
== END_OF_BLOCK
) {
1405 mac_control
->rx_curr_put_info
[ring_no
].
1407 mac_control
->rx_curr_put_info
[ring_no
].
1408 block_index
%= nic
->block_count
[ring_no
];
1409 block_no
= mac_control
->rx_curr_put_info
1410 [ring_no
].block_index
;
1412 off
%= (MAX_RXDS_PER_BLOCK
+ 1);
1413 mac_control
->rx_curr_put_info
[ring_no
].offset
=
1415 /*rxdp = nic->rx_blocks[ring_no][block_no].
1416 block_virt_addr + off; */
1417 rxdp
= (RxD_t
*) ((unsigned long) rxdp
->Control_2
);
1418 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
1422 if (rxdp
->Control_1
& RXD_OWN_XENA
) {
1423 mac_control
->rx_curr_put_info
[ring_no
].
1428 skb
= dev_alloc_skb(size
+ NET_IP_ALIGN
);
1430 DBG_PRINT(ERR_DBG
, "%s: Out of ", dev
->name
);
1431 DBG_PRINT(ERR_DBG
, "memory to allocate SKBs\n");
1434 skb_reserve(skb
, NET_IP_ALIGN
);
1435 memset(rxdp
, 0, sizeof(RxD_t
));
1436 rxdp
->Buffer0_ptr
= pci_map_single
1437 (nic
->pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1438 rxdp
->Control_2
&= (~MASK_BUFFER0_SIZE
);
1439 rxdp
->Control_2
|= SET_BUFFER0_SIZE(size
);
1440 rxdp
->Host_Control
= (unsigned long) (skb
);
1441 rxdp
->Control_1
|= RXD_OWN_XENA
;
1443 off
%= (MAX_RXDS_PER_BLOCK
+ 1);
1444 mac_control
->rx_curr_put_info
[ring_no
].offset
= off
;
1445 atomic_inc(&nic
->rx_bufs_left
[ring_no
]);
1455 * device private variable.
1459 * This function will free all Rx buffers allocated by host.
1461 static void freeRxBuffers(struct s2io_nic
*sp
)
1463 struct net_device
*dev
= sp
->dev
;
1464 int i
, j
, blk
= 0, off
, buf_cnt
= 0;
1466 struct sk_buff
*skb
;
1467 mac_info_t
*mac_control
;
1468 struct config_param
*config
;
1470 mac_control
= &sp
->mac_control
;
1471 config
= &sp
->config
;
1473 for (i
= 0; i
< config
->RxRingNum
; i
++) {
1474 for (j
= 0, blk
= 0; j
< config
->RxCfg
[i
].NumRxd
; j
++) {
1475 off
= j
% (MAX_RXDS_PER_BLOCK
+ 1);
1476 rxdp
= sp
->rx_blocks
[i
][blk
].block_virt_addr
+ off
;
1478 if (rxdp
->Control_1
== END_OF_BLOCK
) {
1480 (RxD_t
*) ((unsigned long) rxdp
->
1487 (struct sk_buff
*) ((unsigned long) rxdp
->
1490 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
1493 HEADER_ETHERNET_II_802_3_SIZE
1494 + HEADER_802_2_SIZE
+
1496 PCI_DMA_FROMDEVICE
);
1498 atomic_dec(&sp
->rx_bufs_left
[i
]);
1501 memset(rxdp
, 0, sizeof(RxD_t
));
1503 mac_control
->rx_curr_put_info
[i
].block_index
= 0;
1504 mac_control
->rx_curr_get_info
[i
].block_index
= 0;
1505 mac_control
->rx_curr_put_info
[i
].offset
= 0;
1506 mac_control
->rx_curr_get_info
[i
].offset
= 0;
1507 atomic_set(&sp
->rx_bufs_left
[i
], 0);
1508 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
1509 dev
->name
, buf_cnt
, i
);
1515 * dev - pointer to the device structure.
1516 * budget - The number of packets that were budgeted to be processed during
1517 * one pass through the 'Poll" function.
1519 * 0 on success and 1 if there are No Rx packets to be processed.
1521 * Comes into picture only if NAPI support has been incorporated. It does
1522 * the same thing that rxIntrHandler does, but not in a interrupt context
1523 * also It will process only a given number of packets.
1525 #ifdef CONFIG_S2IO_NAPI
1526 static int s2io_poll(struct net_device
*dev
, int *budget
)
1528 nic_t
*nic
= dev
->priv
;
1529 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
1530 int pkts_to_process
= *budget
, pkt_cnt
= 0;
1531 register u64 val64
= 0;
1532 rx_curr_get_info_t offset_info
;
1535 struct sk_buff
*skb
;
1537 mac_info_t
*mac_control
;
1538 struct config_param
*config
;
1540 mac_control
= &nic
->mac_control
;
1541 config
= &nic
->config
;
1543 if (pkts_to_process
> dev
->quota
)
1544 pkts_to_process
= dev
->quota
;
1546 val64
= readq(&bar0
->rx_traffic_int
);
1547 writeq(val64
, &bar0
->rx_traffic_int
);
1549 for (i
= 0; i
< config
->RxRingNum
; i
++) {
1550 if (--pkts_to_process
< 0) {
1553 offset_info
= mac_control
->rx_curr_get_info
[i
];
1554 block_no
= offset_info
.block_index
;
1555 rxdp
= nic
->rx_blocks
[i
][block_no
].block_virt_addr
+
1557 while (!(rxdp
->Control_1
& RXD_OWN_XENA
)) {
1558 if (rxdp
->Control_1
== END_OF_BLOCK
) {
1560 (RxD_t
*) ((unsigned long) rxdp
->
1562 offset_info
.offset
++;
1563 offset_info
.offset
%=
1564 (MAX_RXDS_PER_BLOCK
+ 1);
1566 block_no
%= nic
->block_count
[i
];
1567 mac_control
->rx_curr_get_info
[i
].
1568 offset
= offset_info
.offset
;
1569 mac_control
->rx_curr_get_info
[i
].
1570 block_index
= block_no
;
1574 (struct sk_buff
*) ((unsigned long) rxdp
->
1577 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
1579 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
1582 val64
= RXD_GET_BUFFER0_SIZE(rxdp
->Control_2
);
1583 val16
= (u16
) (val64
>> 48);
1584 cksum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
1585 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
1588 HEADER_ETHERNET_II_802_3_SIZE
+
1591 PCI_DMA_FROMDEVICE
);
1592 rxOsmHandler(nic
, val16
, rxdp
, i
);
1594 offset_info
.offset
++;
1595 offset_info
.offset
%= (MAX_RXDS_PER_BLOCK
+ 1);
1597 nic
->rx_blocks
[i
][block_no
].block_virt_addr
+
1599 mac_control
->rx_curr_get_info
[i
].offset
=
1606 for (i
= 0; i
< config
->RxRingNum
; i
++)
1607 fill_rx_buffers(nic
, i
);
1609 dev
->quota
-= pkt_cnt
;
1611 netif_rx_complete(dev
);
1613 /* Re enable the Rx interrupts. */
1614 en_dis_able_NicIntrs(nic
, RX_TRAFFIC_INTR
, ENABLE_INTRS
);
1618 for (i
= 0; i
< config
->RxRingNum
; i
++)
1619 fill_rx_buffers(nic
, i
);
1620 dev
->quota
-= pkt_cnt
;
1627 * device private variable.
1631 * If the interrupt is because of a received frame or if the
1632 * receive ring contains fresh as yet un-processed frames, this function is
1633 * called. It picks out the RxD at which place the last Rx processing had
1634 * stopped and sends the skb to the OSM's Rx handler and then increments
1637 static void rxIntrHandler(struct s2io_nic
*nic
)
1639 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
1640 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
1641 rx_curr_get_info_t offset_info
;
1643 struct sk_buff
*skb
;
1645 register u64 val64
= 0;
1647 mac_info_t
*mac_control
;
1648 struct config_param
*config
;
1650 mac_control
= &nic
->mac_control
;
1651 config
= &nic
->config
;
1657 /* rx_traffic_int reg is an R1 register, hence we read and write back
1658 * the samevalue in the register to clear it.
1660 val64
= readq(&bar0
->rx_traffic_int
);
1661 writeq(val64
, &bar0
->rx_traffic_int
);
1663 for (i
= 0; i
< config
->RxRingNum
; i
++) {
1664 offset_info
= mac_control
->rx_curr_get_info
[i
];
1665 block_no
= offset_info
.block_index
;
1666 rxdp
= nic
->rx_blocks
[i
][block_no
].block_virt_addr
+
1668 while (!(rxdp
->Control_1
& RXD_OWN_XENA
)) {
1669 if (rxdp
->Control_1
== END_OF_BLOCK
) {
1670 rxdp
= (RxD_t
*) ((unsigned long)
1672 offset_info
.offset
++;
1673 offset_info
.offset
%=
1674 (MAX_RXDS_PER_BLOCK
+ 1);
1676 block_no
%= nic
->block_count
[i
];
1677 mac_control
->rx_curr_get_info
[i
].
1678 offset
= offset_info
.offset
;
1679 mac_control
->rx_curr_get_info
[i
].
1680 block_index
= block_no
;
1683 skb
= (struct sk_buff
*) ((unsigned long)
1684 rxdp
->Host_Control
);
1686 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
1688 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
1691 val64
= RXD_GET_BUFFER0_SIZE(rxdp
->Control_2
);
1692 val16
= (u16
) (val64
>> 48);
1693 cksum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
1694 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
1697 HEADER_ETHERNET_II_802_3_SIZE
+
1700 PCI_DMA_FROMDEVICE
);
1701 rxOsmHandler(nic
, val16
, rxdp
, i
);
1702 offset_info
.offset
++;
1703 offset_info
.offset
%= (MAX_RXDS_PER_BLOCK
+ 1);
1705 nic
->rx_blocks
[i
][block_no
].block_virt_addr
+
1707 mac_control
->rx_curr_get_info
[i
].offset
=
1716 * device private variable
1720 * If an interrupt was raised to indicate DMA complete of the
1721 * Tx packet, this function is called. It identifies the last TxD whose buffer
1722 * was freed and frees all skbs whose data have already DMA'ed into the NICs
1725 static void txIntrHandler(struct s2io_nic
*nic
)
1727 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
1728 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
1729 tx_curr_get_info_t offset_info
, offset_info1
;
1730 struct sk_buff
*skb
;
1732 register u64 val64
= 0;
1735 mac_info_t
*mac_control
;
1736 struct config_param
*config
;
1742 mac_control
= &nic
->mac_control
;
1743 config
= &nic
->config
;
1745 /* tx_traffic_int reg is an R1 register, hence we read and write
1746 * back the samevalue in the register to clear it.
1748 val64
= readq(&bar0
->tx_traffic_int
);
1749 writeq(val64
, &bar0
->tx_traffic_int
);
1751 for (i
= 0; i
< config
->TxFIFONum
; i
++) {
1752 offset_info
= mac_control
->tx_curr_get_info
[i
];
1753 offset_info1
= mac_control
->tx_curr_put_info
[i
];
1754 txdlp
= mac_control
->txdl_start
[i
] +
1755 (config
->MaxTxDs
* offset_info
.offset
);
1756 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
1757 (offset_info
.offset
!= offset_info1
.offset
) &&
1758 (txdlp
->Host_Control
)) {
1759 /* Check for TxD errors */
1760 if (txdlp
->Control_1
& TXD_T_CODE
) {
1761 unsigned long long err
;
1762 err
= txdlp
->Control_1
& TXD_T_CODE
;
1763 DBG_PRINT(ERR_DBG
, "***TxD error %llx\n",
1767 skb
= (struct sk_buff
*) ((unsigned long)
1768 txdlp
->Host_Control
);
1770 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
1772 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
1775 nic
->tx_pkt_count
++;
1777 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
1779 /* For unfragmented skb */
1780 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
1781 txdlp
->Buffer_Pointer
,
1782 skb
->len
- skb
->data_len
,
1785 TxD_t
*temp
= txdlp
;
1787 for (j
= 0; j
< frg_cnt
; j
++, txdlp
++) {
1789 &skb_shinfo(skb
)->frags
[j
];
1790 pci_unmap_page(nic
->pdev
,
1800 (sizeof(TxD_t
) * config
->MaxTxDs
));
1802 /* Updating the statistics block */
1803 nic
->stats
.tx_packets
++;
1804 nic
->stats
.tx_bytes
+= skb
->len
;
1806 nic
->txpkt_bytes
+= skb
->len
;
1809 dev_kfree_skb_irq(skb
);
1811 offset_info
.offset
++;
1812 offset_info
.offset
%= offset_info
.fifo_len
+ 1;
1813 txdlp
= mac_control
->txdl_start
[i
] +
1814 (config
->MaxTxDs
* offset_info
.offset
);
1815 mac_control
->tx_curr_get_info
[i
].offset
=
1819 DBG_PRINT(INTR_DBG
, "%s: freed %d Tx Pkts\n", dev
->name
,
1824 spin_lock(&nic
->tx_lock
);
1825 if (netif_queue_stopped(dev
))
1826 netif_wake_queue(dev
);
1827 spin_unlock(&nic
->tx_lock
);
1832 * device private variable
1836 * If the interrupt was neither because of Rx packet or Tx
1837 * complete, this function is called. If the interrupt was to indicate a loss
1838 * of link, the OSM link status handler is invoked for any other alarm
1839 * interrupt the block that raised the interrupt is displayed and a H/W reset
1842 static void alarmIntrHandler(struct s2io_nic
*nic
)
1844 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
1845 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
1846 register u64 val64
= 0, err_reg
= 0;
1849 /* Handling link status change error Intr */
1850 err_reg
= readq(&bar0
->mac_rmac_err_reg
);
1851 if (err_reg
& RMAC_LINK_STATE_CHANGE_INT
) {
1852 schedule_work(&nic
->set_link_task
);
1855 /* Handling SERR errors by stopping device Xmit queue and forcing
1858 val64
= readq(&bar0
->serr_source
);
1859 if (val64
& SERR_SOURCE_ANY
) {
1860 DBG_PRINT(ERR_DBG
, "%s: Device indicates ", dev
->name
);
1861 DBG_PRINT(ERR_DBG
, "serious error!!\n");
1862 netif_stop_queue(dev
);
1864 /* Other type of interrupts are not being handled now, TODO*/
1869 * sp - private member of the device structure, which is a pointer to the
1870 * s2io_nic structure.
1872 * SUCCESS on success and FAILURE on failure.
1874 * Function that waits for a command to Write into RMAC ADDR DATA registers
1875 * to be completed and returns either success or error depending on whether
1876 * the command was complete or not.
1878 int waitForCmdComplete(nic_t
* sp
)
1880 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
1881 int ret
= FAILURE
, cnt
= 0;
1886 RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
1887 | RMAC_ADDR_CMD_MEM_OFFSET(0);
1888 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
1889 val64
= readq(&bar0
->rmac_addr_cmd_mem
);
1894 set_current_state(TASK_UNINTERRUPTIBLE
);
1895 schedule_timeout(HZ
/ 20);
1905 * sp - private member of the device structure, which is a pointer to the
1906 * s2io_nic structure.
1910 * Function to Reset the card. This function then also restores the previously
1911 * saved PCI configuration space registers as the card reset also resets the
1912 * Configration space.
1914 void s2io_reset(nic_t
* sp
)
1916 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
1920 val64
= SW_RESET_ALL
;
1921 writeq(val64
, &bar0
->sw_reset
);
1923 /* At this stage, if the PCI write is indeed completed, the
1924 * card is reset and so is the PCI Config space of the device.
1925 * So a read cannot be issued at this stage on any of the
1926 * registers to ensure the write into "sw_reset" register
1928 * Question: Is there any system call that will explicitly force
1929 * all the write commands still pending on the bus to be pushed
1931 * As of now I'am just giving a 250ms delay and hoping that the
1932 * PCI write to sw_reset register is done by this time.
1934 set_current_state(TASK_UNINTERRUPTIBLE
);
1935 schedule_timeout(HZ
/ 4);
1937 /* Restore the PCI state saved during initializarion. */
1938 pci_restore_state(sp
->pdev
, sp
->config_space
);
1941 set_current_state(TASK_UNINTERRUPTIBLE
);
1942 schedule_timeout(HZ
/ 4);
1944 /* SXE-002: Configure link and activity LED to turn it off */
1945 subid
= sp
->pdev
->subsystem_device
;
1946 if ((subid
& 0xFF) >= 0x07) {
1947 val64
= readq(&bar0
->gpio_control
);
1948 val64
|= 0x0000800000000000ULL
;
1949 writeq(val64
, &bar0
->gpio_control
);
1950 val64
= 0x0411040400000000ULL
;
1951 writeq(val64
, (void *) ((u8
*) bar0
+ 0x2700));
1954 sp
->device_enabled_once
= FALSE
;
1959 * sp - private member of the device structure, which is a pointer to the
1960 * s2io_nic structure.
1962 * SUCCESS on success and FAILURE on failure.
1964 * Function to set the swapper control on the card correctly depending on the
1965 * 'endianness' of the system.
1967 int s2io_set_swapper(nic_t
* sp
)
1969 struct net_device
*dev
= sp
->dev
;
1970 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
1973 /* Set proper endian settings and verify the same by reading the PIF
1974 * Feed-back register.
1977 /* The device by default set to a big endian format, so a big endian
1978 * driver need not set anything.
1980 writeq(0xffffffffffffffffULL
, &bar0
->swapper_ctrl
);
1981 val64
= (SWAPPER_CTRL_PIF_R_FE
|
1982 SWAPPER_CTRL_PIF_R_SE
|
1983 SWAPPER_CTRL_PIF_W_FE
|
1984 SWAPPER_CTRL_PIF_W_SE
|
1985 SWAPPER_CTRL_TXP_FE
|
1986 SWAPPER_CTRL_TXP_SE
|
1987 SWAPPER_CTRL_TXD_R_FE
|
1988 SWAPPER_CTRL_TXD_W_FE
|
1989 SWAPPER_CTRL_TXF_R_FE
|
1990 SWAPPER_CTRL_RXD_R_FE
|
1991 SWAPPER_CTRL_RXD_W_FE
|
1992 SWAPPER_CTRL_RXF_W_FE
|
1993 SWAPPER_CTRL_XMSI_FE
|
1994 SWAPPER_CTRL_XMSI_SE
|
1995 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
1996 writeq(val64
, &bar0
->swapper_ctrl
);
1998 /* Initially we enable all bits to make it accessible by the driver,
1999 * then we selectively enable only those bits that we want to set.
2001 writeq(0xffffffffffffffffULL
, &bar0
->swapper_ctrl
);
2002 val64
= (SWAPPER_CTRL_PIF_R_FE
|
2003 SWAPPER_CTRL_PIF_R_SE
|
2004 SWAPPER_CTRL_PIF_W_FE
|
2005 SWAPPER_CTRL_PIF_W_SE
|
2006 SWAPPER_CTRL_TXP_FE
|
2007 SWAPPER_CTRL_TXP_SE
|
2008 SWAPPER_CTRL_TXD_R_FE
|
2009 SWAPPER_CTRL_TXD_R_SE
|
2010 SWAPPER_CTRL_TXD_W_FE
|
2011 SWAPPER_CTRL_TXD_W_SE
|
2012 SWAPPER_CTRL_TXF_R_FE
|
2013 SWAPPER_CTRL_RXD_R_FE
|
2014 SWAPPER_CTRL_RXD_R_SE
|
2015 SWAPPER_CTRL_RXD_W_FE
|
2016 SWAPPER_CTRL_RXD_W_SE
|
2017 SWAPPER_CTRL_RXF_W_FE
|
2018 SWAPPER_CTRL_XMSI_FE
|
2019 SWAPPER_CTRL_XMSI_SE
|
2020 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
2021 writeq(val64
, &bar0
->swapper_ctrl
);
2024 /* Verifying if endian settings are accurate by reading a feedback
2027 val64
= readq(&bar0
->pif_rd_swapper_fb
);
2028 if (val64
!= 0x0123456789ABCDEFULL
) {
2029 /* Endian settings are incorrect, calls for another dekko. */
2030 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
2032 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
2033 (unsigned long long) val64
);
2040 /* ********************************************************* *
2041 * Functions defined below concern the OS part of the driver *
2042 * ********************************************************* */
2046 * dev - pointer to the device structure.
2048 * '0' on success and an appropriate (-)ve integer as defined in errno.h
2051 * This function is the open entry point of the driver. It mainly calls a
2052 * function to allocate Rx buffers and inserts them into the buffer
2053 * descriptors and then enables the Rx part of the NIC.
2055 int s2io_open(struct net_device
*dev
)
2057 nic_t
*sp
= dev
->priv
;
2058 int i
, ret
= 0, err
= 0;
2059 mac_info_t
*mac_control
;
2060 struct config_param
*config
;
2063 /* Make sure you have link off by default every time Nic is initialized*/
2064 netif_carrier_off(dev
);
2065 sp
->last_link_state
= LINK_DOWN
;
2067 /* Initialize the H/W I/O registers */
2068 if (initNic(sp
) != 0) {
2069 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
2074 /* After proper initialization of H/W, register ISR */
2076 request_irq((int) sp
->irq
, s2io_isr
, SA_SHIRQ
, sp
->name
, dev
);
2079 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
2083 if (s2io_set_mac_addr(dev
, dev
->dev_addr
) == FAILURE
) {
2084 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
2090 /* Setting its receive mode */
2091 s2io_set_multicast(dev
);
2093 /* Initializing the Rx buffers. For now we are considering only 1 Rx ring
2094 * and initializing buffers into 1016 RxDs or 8 Rx blocks
2096 mac_control
= &sp
->mac_control
;
2097 config
= &sp
->config
;
2099 for (i
= 0; i
< config
->RxRingNum
; i
++) {
2100 if ((ret
= fill_rx_buffers(sp
, i
))) {
2101 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
2104 free_irq(dev
->irq
, dev
);
2108 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
2109 atomic_read(&sp
->rx_bufs_left
[i
]));
2112 /* Enable tasklet for the device */
2113 tasklet_init(&sp
->task
, s2io_tasklet
, (unsigned long) dev
);
2115 /* Enable Rx Traffic and interrupts on the NIC */
2117 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
2118 tasklet_kill(&sp
->task
);
2120 free_irq(dev
->irq
, dev
);
2125 sp
->device_close_flag
= FALSE
; /* Device is up and running. */
2126 netif_start_queue(dev
);
2133 * dev - device pointer.
2135 * '0' on success and an appropriate (-)ve integer as defined in errno.h
2138 * This is the stop entry point of the driver. It needs to undo exactly
2139 * whatever was done by the open entry point, thus it's usually referred to
2140 * as the close function. Among other things this function mainly stops the
2141 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
2143 int s2io_close(struct net_device
*dev
)
2145 nic_t
*sp
= dev
->priv
;
2146 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2147 register u64 val64
= 0;
2150 spin_lock(&sp
->isr_lock
);
2151 netif_stop_queue(dev
);
2153 /* disable Tx and Rx traffic on the NIC */
2156 spin_unlock(&sp
->isr_lock
);
2158 /* If the device tasklet is running, wait till its done before killing it */
2159 while (atomic_read(&(sp
->tasklet_status
))) {
2160 set_current_state(TASK_UNINTERRUPTIBLE
);
2161 schedule_timeout(HZ
/ 10);
2163 tasklet_kill(&sp
->task
);
2165 /* Check if the device is Quiescent and then Reset the NIC */
2167 val64
= readq(&bar0
->adapter_status
);
2168 if (verify_xena_quiescence(val64
, sp
->device_enabled_once
)) {
2172 set_current_state(TASK_UNINTERRUPTIBLE
);
2173 schedule_timeout(HZ
/ 20);
2177 "s2io_close:Device not Quiescent ");
2178 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
2179 (unsigned long long) val64
);
2185 /* Free the Registered IRQ */
2186 free_irq(dev
->irq
, dev
);
2188 /* Free all Tx Buffers waiting for transmission */
2191 /* Free all Rx buffers allocated by host */
2194 sp
->device_close_flag
= TRUE
; /* Device is shut down. */
2201 * skb - the socket buffer containing the Tx data.
2202 * dev - device pointer.
2204 * '0' on success & 1 on failure.
2205 * NOTE: when device cant queue the pkt, just the trans_start variable will
2208 * This function is the Tx entry point of the driver. S2IO NIC supports
2209 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
2211 int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2213 nic_t
*sp
= dev
->priv
;
2214 u16 off
, txd_len
, frg_cnt
, frg_len
, i
, queue
, off1
, queue_len
;
2217 TxFIFO_element_t
*tx_fifo
;
2218 unsigned long flags
;
2222 mac_info_t
*mac_control
;
2223 struct config_param
*config
;
2225 mac_control
= &sp
->mac_control
;
2226 config
= &sp
->config
;
2228 DBG_PRINT(TX_DBG
, "%s: In S2IO Tx routine\n", dev
->name
);
2230 spin_lock_irqsave(&sp
->tx_lock
, flags
);
2232 /* Multi FIFO Tx is disabled for now. */
2233 if (!queue
&& tx_prio
) {
2234 u8 x
= (skb
->data
)[5];
2235 queue
= x
% config
->TxFIFONum
;
2239 off
= (u16
) mac_control
->tx_curr_put_info
[queue
].offset
;
2240 off1
= (u16
) mac_control
->tx_curr_get_info
[queue
].offset
;
2241 txd_len
= mac_control
->txdl_len
;
2242 txdp
= mac_control
->txdl_start
[queue
] + (config
->MaxTxDs
* off
);
2244 queue_len
= mac_control
->tx_curr_put_info
[queue
].fifo_len
+ 1;
2245 /* Avoid "put" pointer going beyond "get" pointer */
2246 if (txdp
->Host_Control
|| (((off
+ 1) % queue_len
) == off1
)) {
2247 DBG_PRINT(ERR_DBG
, "Error in xmit, No free TXDs.\n");
2248 netif_stop_queue(dev
);
2250 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
2255 mss
= skb_shinfo(skb
)->tso_size
;
2257 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
2258 txdp
->Control_1
|= TXD_TCP_LSO_MSS(mss
);
2262 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2263 frg_len
= skb
->len
- skb
->data_len
;
2265 txdp
->Host_Control
= (unsigned long) skb
;
2266 txdp
->Buffer_Pointer
= pci_map_single
2267 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
2268 if (skb
->ip_summed
== CHECKSUM_HW
) {
2270 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
2274 txdp
->Control_2
|= config
->TxIntrType
;
2276 txdp
->Control_1
|= (TXD_BUFFER0_SIZE(frg_len
) |
2277 TXD_GATHER_CODE_FIRST
);
2278 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
2280 /* For fragmented SKB. */
2281 for (i
= 0; i
< frg_cnt
; i
++) {
2282 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2284 txdp
->Buffer_Pointer
= (u64
) pci_map_page
2285 (sp
->pdev
, frag
->page
, frag
->page_offset
,
2286 frag
->size
, PCI_DMA_TODEVICE
);
2287 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frag
->size
);
2289 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
2291 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
2292 val64
= (mac_control
->txdl_start_phy
[queue
] +
2293 (sizeof(TxD_t
) * txd_len
* off
));
2294 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
2296 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
2300 val64
|= TX_FIFO_SPECIAL_FUNC
;
2302 writeq(val64
, &tx_fifo
->List_Control
);
2305 off
%= mac_control
->tx_curr_put_info
[queue
].fifo_len
+ 1;
2306 mac_control
->tx_curr_put_info
[queue
].offset
= off
;
2308 /* Avoid "put" pointer going beyond "get" pointer */
2309 if (((off
+ 1) % queue_len
) == off1
) {
2311 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
2313 netif_stop_queue(dev
);
2316 dev
->trans_start
= jiffies
;
2317 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
2324 * irq: the irq of the device.
2325 * dev_id: a void pointer to the dev structure of the NIC.
2326 * ptregs: pointer to the registers pushed on the stack.
2330 * This function is the ISR handler of the device. It identifies the reason
2331 * for the interrupt and calls the relevant service routines.
2332 * As a contongency measure, this ISR allocates the recv buffers, if their
2333 * numbers are below the panic value which is presently set to 25% of the
2334 * original number of rcv buffers allocated.
2337 static irqreturn_t
s2io_isr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2339 struct net_device
*dev
= (struct net_device
*) dev_id
;
2340 nic_t
*sp
= dev
->priv
;
2341 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2342 u64 reason
= 0, general_mask
= 0;
2343 mac_info_t
*mac_control
;
2344 struct config_param
*config
;
2346 mac_control
= &sp
->mac_control
;
2347 config
= &sp
->config
;
2349 spin_lock(&sp
->isr_lock
);
2351 /* Identify the cause for interrupt and call the appropriate
2352 * interrupt handler. Causes for the interrupt could be;
2356 * 4. Error in any functional blocks of the NIC.
2358 reason
= readq(&bar0
->general_int_status
);
2361 /* The interrupt was not raised by Xena. */
2362 spin_unlock(&sp
->isr_lock
);
2365 /* Mask the interrupts on the NIC */
2366 general_mask
= readq(&bar0
->general_int_mask
);
2367 writeq(0xFFFFFFFFFFFFFFFFULL
, &bar0
->general_int_mask
);
2373 /* If Intr is because of Tx Traffic */
2374 if (reason
& GEN_INTR_TXTRAFFIC
) {
2378 /* If Intr is because of an error */
2379 if (reason
& (GEN_ERROR_INTR
))
2380 alarmIntrHandler(sp
);
2382 #ifdef CONFIG_S2IO_NAPI
2383 if (reason
& GEN_INTR_RXTRAFFIC
) {
2384 if (netif_rx_schedule_prep(dev
)) {
2385 en_dis_able_NicIntrs(sp
, RX_TRAFFIC_INTR
,
2387 /* We retake the snap shot of the general interrupt
2390 general_mask
= readq(&bar0
->general_int_mask
);
2391 __netif_rx_schedule(dev
);
2395 /* If Intr is because of Rx Traffic */
2396 if (reason
& GEN_INTR_RXTRAFFIC
) {
2401 /* If the Rx buffer count is below the panic threshold then reallocate the
2402 * buffers from the interrupt handler itself, else schedule a tasklet to
2403 * reallocate the buffers.
2409 for (i
= 0; i
< config
->RxRingNum
; i
++) {
2410 int rxb_size
= atomic_read(&sp
->rx_bufs_left
[i
]);
2411 int level
= rx_buffer_level(sp
, rxb_size
, i
);
2413 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
2416 DBG_PRINT(ERR_DBG
, "%s: Rx BD hit ", dev
->name
);
2417 DBG_PRINT(ERR_DBG
, "PANIC levels\n");
2418 if ((ret
= fill_rx_buffers(sp
, i
)) == -ENOMEM
) {
2419 DBG_PRINT(ERR_DBG
, "%s:Out of memory",
2421 DBG_PRINT(ERR_DBG
, " in ISR!!\n");
2422 writeq(general_mask
,
2423 &bar0
->general_int_mask
);
2424 spin_unlock(&sp
->isr_lock
);
2428 (unsigned long *) (&sp
->tasklet_status
));
2429 } else if ((level
== LOW
)
2430 && (!atomic_read(&sp
->tasklet_status
))) {
2431 tasklet_schedule(&sp
->task
);
2438 tasklet_schedule(&sp
->task
);
2441 /* Unmask all the previously enabled interrupts on the NIC */
2442 writeq(general_mask
, &bar0
->general_int_mask
);
2444 spin_unlock(&sp
->isr_lock
);
2450 * dev - pointer to the device structure.
2452 * pointer to the updated net_device_stats structure.
2454 * This function updates the device statistics structure in the s2io_nic
2455 * structure and returns a pointer to the same.
2457 struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
2459 nic_t
*sp
= dev
->priv
;
2460 mac_info_t
*mac_control
;
2461 struct config_param
*config
;
2463 mac_control
= &sp
->mac_control
;
2464 config
= &sp
->config
;
2466 sp
->stats
.tx_errors
= mac_control
->StatsInfo
->tmac_any_err_frms
;
2467 sp
->stats
.rx_errors
= mac_control
->StatsInfo
->rmac_drop_frms
;
2468 sp
->stats
.multicast
= mac_control
->StatsInfo
->rmac_vld_mcst_frms
;
2469 sp
->stats
.rx_length_errors
=
2470 mac_control
->StatsInfo
->rmac_long_frms
;
2472 return (&sp
->stats
);
2477 * dev - pointer to the device structure
2481 * This function is a driver entry point which gets called by the kernel
2482 * whenever multicast addresses must be enabled/disabled. This also gets
2483 * called to set/reset promiscuous mode. Depending on the deivce flag, we
2484 * determine, if multicast address must be enabled or if promiscuous mode
2485 * is to be disabled etc.
2487 static void s2io_set_multicast(struct net_device
*dev
)
2490 struct dev_mc_list
*mclist
;
2491 nic_t
*sp
= dev
->priv
;
2492 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2493 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
2495 u64 dis_addr
= 0xffffffffffffULL
, mac_addr
= 0;
2498 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
2499 /* Enable all Multicast addresses */
2500 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
2501 &bar0
->rmac_addr_data0_mem
);
2502 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
2503 &bar0
->rmac_addr_data1_mem
);
2504 val64
= RMAC_ADDR_CMD_MEM_WE
|
2505 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
2506 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET
);
2507 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
2508 /* Wait till command completes */
2509 waitForCmdComplete(sp
);
2512 sp
->all_multi_pos
= MAC_MC_ALL_MC_ADDR_OFFSET
;
2513 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
2514 /* Disable all Multicast addresses */
2515 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
2516 &bar0
->rmac_addr_data0_mem
);
2517 val64
= RMAC_ADDR_CMD_MEM_WE
|
2518 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
2519 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
2520 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
2521 /* Wait till command completes */
2522 waitForCmdComplete(sp
);
2525 sp
->all_multi_pos
= 0;
2528 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
2529 /* Put the NIC into promiscuous mode */
2530 add
= (void *) &bar0
->mac_cfg
;
2531 val64
= readq(&bar0
->mac_cfg
);
2532 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
2534 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
2535 writel((u32
) val64
, add
);
2536 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
2537 writel((u32
) (val64
>> 32), (add
+ 4));
2539 val64
= readq(&bar0
->mac_cfg
);
2540 sp
->promisc_flg
= 1;
2541 DBG_PRINT(ERR_DBG
, "%s: entered promiscuous mode\n",
2543 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
2544 /* Remove the NIC from promiscuous mode */
2545 add
= (void *) &bar0
->mac_cfg
;
2546 val64
= readq(&bar0
->mac_cfg
);
2547 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
2549 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
2550 writel((u32
) val64
, add
);
2551 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
2552 writel((u32
) (val64
>> 32), (add
+ 4));
2554 val64
= readq(&bar0
->mac_cfg
);
2555 sp
->promisc_flg
= 0;
2556 DBG_PRINT(ERR_DBG
, "%s: left promiscuous mode\n",
2560 /* Update individual M_CAST address list */
2561 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
2563 (MAX_ADDRS_SUPPORTED
- MAC_MC_ADDR_START_OFFSET
- 1)) {
2564 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
2566 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
2567 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
2571 prev_cnt
= sp
->mc_addr_count
;
2572 sp
->mc_addr_count
= dev
->mc_count
;
2574 /* Clear out the previous list of Mc in the H/W. */
2575 for (i
= 0; i
< prev_cnt
; i
++) {
2576 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
2577 &bar0
->rmac_addr_data0_mem
);
2578 val64
= RMAC_ADDR_CMD_MEM_WE
|
2579 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
2580 RMAC_ADDR_CMD_MEM_OFFSET
2581 (MAC_MC_ADDR_START_OFFSET
+ i
);
2582 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
2584 /* Wait for command completes */
2585 if (waitForCmdComplete(sp
)) {
2586 DBG_PRINT(ERR_DBG
, "%s: Adding ",
2588 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
2593 /* Create the new Rx filter list and update the same in H/W. */
2594 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
2595 i
++, mclist
= mclist
->next
) {
2596 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
2598 for (j
= 0; j
< ETH_ALEN
; j
++) {
2599 mac_addr
|= mclist
->dmi_addr
[j
];
2602 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
2603 &bar0
->rmac_addr_data0_mem
);
2605 val64
= RMAC_ADDR_CMD_MEM_WE
|
2606 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
2607 RMAC_ADDR_CMD_MEM_OFFSET
2608 (i
+ MAC_MC_ADDR_START_OFFSET
);
2609 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
2611 /* Wait for command completes */
2612 if (waitForCmdComplete(sp
)) {
2613 DBG_PRINT(ERR_DBG
, "%s: Adding ",
2615 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
2624 * dev - pointer to the device structure.
2625 * new_mac - a uchar pointer to the new mac address which is to be set.
2627 * SUCCESS on success and an appropriate (-)ve integer as defined in errno.h
2630 * This procedure will program the Xframe to receive frames with new
2633 int s2io_set_mac_addr(struct net_device
*dev
, u8
* addr
)
2635 nic_t
*sp
= dev
->priv
;
2636 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2637 register u64 val64
, mac_addr
= 0;
2641 * Set the new MAC address as the new unicast filter and reflect this
2642 * change on the device address registered with the OS. It will be
2645 for (i
= 0; i
< ETH_ALEN
; i
++) {
2647 mac_addr
|= addr
[i
];
2650 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
2651 &bar0
->rmac_addr_data0_mem
);
2654 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
2655 RMAC_ADDR_CMD_MEM_OFFSET(0);
2656 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
2657 /* Wait till command completes */
2658 if (waitForCmdComplete(sp
)) {
2659 DBG_PRINT(ERR_DBG
, "%s: set_mac_addr failed\n", dev
->name
);
2668 * sp - private member of the device structure, which is a pointer to the
2669 * s2io_nic structure.
2670 * info - pointer to the structure with parameters given by ethtool to set
2675 * The function sets different link parameters provided by the user onto
2678 static int s2io_ethtool_sset(struct net_device
*dev
,
2679 struct ethtool_cmd
*info
)
2681 nic_t
*sp
= dev
->priv
;
2682 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
2683 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
2686 s2io_close(sp
->dev
);
2695 * sp - private member of the device structure, which is a pointer to the
2696 * s2io_nic structure.
2697 * info - pointer to the structure with parameters given by ethtool to return
2702 * Returns link specefic information like speed, duplex etc.. to ethtool.
2704 int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
2706 nic_t
*sp
= dev
->priv
;
2707 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
2708 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
2709 info
->port
= PORT_FIBRE
;
2710 /* info->transceiver?? TODO */
2712 if (netif_carrier_ok(sp
->dev
)) {
2713 info
->speed
= 10000;
2714 info
->duplex
= DUPLEX_FULL
;
2720 info
->autoneg
= AUTONEG_DISABLE
;
2726 * sp - private member of the device structure, which is a pointer to the
2727 * s2io_nic structure.
2728 * info - pointer to the structure with parameters given by ethtool to return
2729 * driver information.
2733 * Returns driver specefic information like name, version etc.. to ethtool.
2735 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
2736 struct ethtool_drvinfo
*info
)
2738 nic_t
*sp
= dev
->priv
;
2740 strncpy(info
->driver
, s2io_driver_name
, sizeof(s2io_driver_name
));
2741 strncpy(info
->version
, s2io_driver_version
,
2742 sizeof(s2io_driver_version
));
2743 strncpy(info
->fw_version
, "", 32);
2744 strncpy(info
->bus_info
, sp
->pdev
->slot_name
, 32);
2745 info
->regdump_len
= XENA_REG_SPACE
;
2746 info
->eedump_len
= XENA_EEPROM_SPACE
;
2747 info
->testinfo_len
= S2IO_TEST_LEN
;
2748 info
->n_stats
= S2IO_STAT_LEN
;
2753 * sp - private member of the device structure, which is a pointer to the
2754 * s2io_nic structure.
2755 * regs - pointer to the structure with parameters given by ethtool for
2756 * dumping the registers.
2757 * reg_space - The input argumnet into which all the registers are dumped.
2761 * Dumps the entire register space of xFrame NIC into the user given buffer
2764 static void s2io_ethtool_gregs(struct net_device
*dev
,
2765 struct ethtool_regs
*regs
, void *space
)
2769 u8
*reg_space
= (u8
*) space
;
2770 nic_t
*sp
= dev
->priv
;
2772 regs
->len
= XENA_REG_SPACE
;
2773 regs
->version
= sp
->pdev
->subsystem_device
;
2775 for (i
= 0; i
< regs
->len
; i
+= 8) {
2776 reg
= readq((void *) (sp
->bar0
+ i
));
2777 memcpy((reg_space
+ i
), ®
, 8);
2783 * data - address of the private member of the device structure, which
2784 * is a pointer to the s2io_nic structure, provided as an u32.
2788 * This is actually the timer function that alternates the adapter LED bit
2789 * of the adapter control bit to set/reset every time on invocation.
2790 * The timer is set for 1/2 a second, hence tha NIC blinks once every second.
2792 static void s2io_phy_id(unsigned long data
)
2794 nic_t
*sp
= (nic_t
*) data
;
2795 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2799 subid
= sp
->pdev
->subsystem_device
;
2800 if ((subid
& 0xFF) >= 0x07) {
2801 val64
= readq(&bar0
->gpio_control
);
2802 val64
^= GPIO_CTRL_GPIO_0
;
2803 writeq(val64
, &bar0
->gpio_control
);
2805 val64
= readq(&bar0
->adapter_control
);
2806 val64
^= ADAPTER_LED_ON
;
2807 writeq(val64
, &bar0
->adapter_control
);
2810 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
2815 * sp - private member of the device structure, which is a pointer to the
2816 * s2io_nic structure.
2817 * id - pointer to the structure with identification parameters given by
2820 * int , returns '0' on success
2822 * Used to physically identify the NIC on the system. The Link LED will blink
2823 * for a time specified by the user for identification.
2824 * NOTE: The Link has to be Up to be able to blink the LED. Hence
2825 * identification is possible only if it's link is up.
2827 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
2830 nic_t
*sp
= dev
->priv
;
2831 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2834 subid
= sp
->pdev
->subsystem_device
;
2835 if ((subid
& 0xFF) < 0x07) {
2836 val64
= readq(&bar0
->adapter_control
);
2837 if (!(val64
& ADAPTER_CNTL_EN
)) {
2839 "Adapter Link down, cannot blink LED\n");
2843 if (sp
->id_timer
.function
== NULL
) {
2844 init_timer(&sp
->id_timer
);
2845 sp
->id_timer
.function
= s2io_phy_id
;
2846 sp
->id_timer
.data
= (unsigned long) sp
;
2848 mod_timer(&sp
->id_timer
, jiffies
);
2849 set_current_state(TASK_INTERRUPTIBLE
);
2851 schedule_timeout(data
* HZ
);
2853 schedule_timeout(MAX_SCHEDULE_TIMEOUT
);
2854 del_timer_sync(&sp
->id_timer
);
2861 * sp - private member of the device structure, which is a pointer to the
2862 * s2io_nic structure.
2863 * ep - pointer to the structure with pause parameters given by ethtool.
2867 * Returns the Pause frame generation and reception capability of the NIC.
2869 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
2870 struct ethtool_pauseparam
*ep
)
2873 nic_t
*sp
= dev
->priv
;
2874 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2876 val64
= readq(&bar0
->rmac_pause_cfg
);
2877 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
2878 ep
->tx_pause
= TRUE
;
2879 if (val64
& RMAC_PAUSE_RX_ENABLE
)
2880 ep
->rx_pause
= TRUE
;
2881 ep
->autoneg
= FALSE
;
2886 * sp - private member of the device structure, which is a pointer to the
2887 * s2io_nic structure.
2888 * ep - pointer to the structure with pause parameters given by ethtool.
2890 * int, returns '0' on Success
2892 * It can be used to set or reset Pause frame generation or reception support
2895 int s2io_ethtool_setpause_data(struct net_device
*dev
,
2896 struct ethtool_pauseparam
*ep
)
2899 nic_t
*sp
= dev
->priv
;
2900 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2902 val64
= readq(&bar0
->rmac_pause_cfg
);
2904 val64
|= RMAC_PAUSE_GEN_ENABLE
;
2906 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
2908 val64
|= RMAC_PAUSE_RX_ENABLE
;
2910 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
2911 writeq(val64
, &bar0
->rmac_pause_cfg
);
2917 * sp - private member of the device structure, which is a pointer to the
2918 * s2io_nic structure.
2919 * off - offset at which the data must be written
2921 * -1 on failure and the value read from the Eeprom if successful.
2923 * Will read 4 bytes of data from the user given offset and return the
2925 * NOTE: Will allow to read only part of the EEPROM visible through the
2928 #define S2IO_DEV_ID 5
2929 static u32
readEeprom(nic_t
* sp
, int off
)
2931 u32 data
= -1, exit_cnt
= 0;
2933 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2935 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
2936 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
2937 I2C_CONTROL_CNTL_START
;
2938 writeq(val64
, &bar0
->i2c_control
);
2940 while (exit_cnt
< 5) {
2941 val64
= readq(&bar0
->i2c_control
);
2942 if (I2C_CONTROL_CNTL_END(val64
)) {
2943 data
= I2C_CONTROL_GET_DATA(val64
);
2946 set_current_state(TASK_UNINTERRUPTIBLE
);
2947 schedule_timeout(HZ
/ 20);
2956 * sp - private member of the device structure, which is a pointer to the
2957 * s2io_nic structure.
2958 * off - offset at which the data must be written
2959 * data - The data that is to be written
2960 * cnt - Number of bytes of the data that are actually to be written into
2961 * the Eeprom. (max of 3)
2963 * '0' on success, -1 on failure.
2965 * Actually writes the relevant part of the data value into the Eeprom
2966 * through the I2C bus.
2968 static int writeEeprom(nic_t
* sp
, int off
, u32 data
, int cnt
)
2970 int exit_cnt
= 0, ret
= -1;
2972 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
2974 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
2975 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA(data
) |
2976 I2C_CONTROL_CNTL_START
;
2977 writeq(val64
, &bar0
->i2c_control
);
2979 while (exit_cnt
< 5) {
2980 val64
= readq(&bar0
->i2c_control
);
2981 if (I2C_CONTROL_CNTL_END(val64
)) {
2982 if (!(val64
& I2C_CONTROL_NACK
))
2986 set_current_state(TASK_UNINTERRUPTIBLE
);
2987 schedule_timeout(HZ
/ 20);
2995 * A helper function used to invert the 4 byte u32 data field
2996 * byte by byte. This will be used by the Read Eeprom function
2997 * for display purposes.
3005 ret
= ((ret
<< 8) + c
);
3015 * sp - private member of the device structure, which is a pointer to the
3016 * s2io_nic structure.
3017 * eeprom - pointer to the user level structure provided by ethtool,
3018 * containing all relevant information.
3019 * data_buf - user defined value to be written into Eeprom.
3021 * int '0' on success
3023 * Reads the values stored in the Eeprom at given offset for a given length.
3024 * Stores these values int the input argument data buffer 'data_buf' and
3025 * returns these to the caller (ethtool.)
3027 int s2io_ethtool_geeprom(struct net_device
*dev
,
3028 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
3031 nic_t
*sp
= dev
->priv
;
3033 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
3035 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
3036 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
3038 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
3039 data
= readEeprom(sp
, eeprom
->offset
+ i
);
3041 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
3045 memcpy((data_buf
+ i
), &valid
, 4);
3052 * sp - private member of the device structure, which is a pointer to the
3053 * s2io_nic structure.
3054 * eeprom - pointer to the user level structure provided by ethtool,
3055 * containing all relevant information.
3056 * data_buf - user defined value to be written into Eeprom.
3058 * '0' on success, -EFAULT on failure.
3060 * Tries to write the user provided value in the Eeprom, at the offset
3061 * given by the user.
3063 static int s2io_ethtool_seeprom(struct net_device
*dev
,
3064 struct ethtool_eeprom
*eeprom
,
3067 int len
= eeprom
->len
, cnt
= 0;
3068 u32 valid
= 0, data
;
3069 nic_t
*sp
= dev
->priv
;
3071 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
3073 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
3074 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
3080 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
3082 valid
= (u32
) (data
<< 24);
3086 if (writeEeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
3088 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
3090 "write into the specified offset\n");
3102 * sp - private member of the device structure, which is a pointer to the
3103 * s2io_nic structure.
3104 * data - variable that returns the result of each of the test conducted by
3109 * Read and write into all clock domains. The NIC has 3 clock domains,
3110 * see that registers in all the three regions are accessible.
3112 static int s2io_registerTest(nic_t
* sp
, uint64_t * data
)
3114 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
3118 val64
= readq(&bar0
->pcc_enable
);
3119 if (val64
!= 0xff00000000000000ULL
) {
3121 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
3124 val64
= readq(&bar0
->rmac_pause_cfg
);
3125 if (val64
!= 0xc000ffff00000000ULL
) {
3127 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
3130 val64
= readq(&bar0
->rx_queue_cfg
);
3131 if (val64
!= 0x0808080808080808ULL
) {
3133 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
3136 val64
= readq(&bar0
->xgxs_efifo_cfg
);
3137 if (val64
!= 0x000000001923141EULL
) {
3139 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
3142 val64
= 0x5A5A5A5A5A5A5A5AULL
;
3143 writeq(val64
, &bar0
->xmsi_data
);
3144 val64
= readq(&bar0
->xmsi_data
);
3145 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
3147 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
3150 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
3151 writeq(val64
, &bar0
->xmsi_data
);
3152 val64
= readq(&bar0
->xmsi_data
);
3153 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
3155 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
3164 * sp - private member of the device structure, which is a pointer to the
3165 * s2io_nic structure.
3166 * data - variable that returns the result of each of the test conducted by
3171 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
3174 static int s2io_eepromTest(nic_t
* sp
, uint64_t * data
)
3176 int fail
= 0, ret_data
;
3178 /* Test Write Error at offset 0 */
3179 if (!writeEeprom(sp
, 0, 0, 3))
3182 /* Test Write at offset 4f0 */
3183 if (writeEeprom(sp
, 0x4F0, 0x01234567, 3))
3185 if ((ret_data
= readEeprom(sp
, 0x4f0)) < 0)
3188 if (ret_data
!= 0x01234567)
3191 /* Reset the EEPROM data go FFFF */
3192 writeEeprom(sp
, 0x4F0, 0xFFFFFFFF, 3);
3194 /* Test Write Request Error at offset 0x7c */
3195 if (!writeEeprom(sp
, 0x07C, 0, 3))
3198 /* Test Write Request at offset 0x7fc */
3199 if (writeEeprom(sp
, 0x7FC, 0x01234567, 3))
3201 if ((ret_data
= readEeprom(sp
, 0x7FC)) < 0)
3204 if (ret_data
!= 0x01234567)
3207 /* Reset the EEPROM data go FFFF */
3208 writeEeprom(sp
, 0x7FC, 0xFFFFFFFF, 3);
3210 /* Test Write Error at offset 0x80 */
3211 if (!writeEeprom(sp
, 0x080, 0, 3))
3214 /* Test Write Error at offset 0xfc */
3215 if (!writeEeprom(sp
, 0x0FC, 0, 3))
3218 /* Test Write Error at offset 0x100 */
3219 if (!writeEeprom(sp
, 0x100, 0, 3))
3222 /* Test Write Error at offset 4ec */
3223 if (!writeEeprom(sp
, 0x4EC, 0, 3))
3232 * sp - private member of the device structure, which is a pointer to the
3233 * s2io_nic structure.
3234 * data - variable that returns the result of each of the test conducted by
3237 * '0' on success and -1 on failure.
3239 * This invokes the MemBist test of the card. We give around
3240 * 2 secs time for the Test to complete. If it's still not complete
3241 * within this peiod, we consider that the test failed.
3243 static int s2io_bistTest(nic_t
* sp
, uint64_t * data
)
3246 int cnt
= 0, ret
= -1;
3248 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
3249 bist
|= PCI_BIST_START
;
3250 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
3253 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
3254 if (!(bist
& PCI_BIST_START
)) {
3255 *data
= (bist
& PCI_BIST_CODE_MASK
);
3259 set_current_state(TASK_UNINTERRUPTIBLE
);
3260 schedule_timeout(HZ
/ 10);
3269 * sp - private member of the device structure, which is a pointer to the
3270 * s2io_nic structure.
3271 * data - variable that returns the result of each of the test conducted by
3276 * The function verifies the link state of the NIC and updates the input
3277 * argument 'data' appropriately.
3279 static int s2io_linkTest(nic_t
* sp
, uint64_t * data
)
3281 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
3284 val64
= readq(&bar0
->adapter_status
);
3285 if (val64
& ADAPTER_STATUS_RMAC_LOCAL_FAULT
)
3293 * sp - private member of the device structure, which is a pointer to the
3294 * s2io_nic structure.
3295 * data - variable that returns the result of each of the test conducted by
3300 * This is one of the offline test that tests the read and write
3301 * access to the RldRam chip on the NIC.
3303 static int s2io_rldramTest(nic_t
* sp
, uint64_t * data
)
3305 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
3307 int cnt
, iteration
= 0, test_pass
= 0;
3309 val64
= readq(&bar0
->adapter_control
);
3310 val64
&= ~ADAPTER_ECC_EN
;
3311 writeq(val64
, &bar0
->adapter_control
);
3313 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
3314 val64
|= MC_RLDRAM_TEST_MODE
;
3315 writeq(val64
, &bar0
->mc_rldram_test_ctrl
);
3317 val64
= readq(&bar0
->mc_rldram_mrs
);
3318 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
3319 writeq(val64
, &bar0
->mc_rldram_mrs
);
3321 val64
|= MC_RLDRAM_MRS_ENABLE
;
3322 writeq(val64
, &bar0
->mc_rldram_mrs
);
3324 while (iteration
< 2) {
3325 val64
= 0x55555555aaaa0000ULL
;
3326 if (iteration
== 1) {
3327 val64
^= 0xFFFFFFFFFFFF0000ULL
;
3329 writeq(val64
, &bar0
->mc_rldram_test_d0
);
3331 val64
= 0xaaaa5a5555550000ULL
;
3332 if (iteration
== 1) {
3333 val64
^= 0xFFFFFFFFFFFF0000ULL
;
3335 writeq(val64
, &bar0
->mc_rldram_test_d1
);
3337 val64
= 0x55aaaaaaaa5a0000ULL
;
3338 if (iteration
== 1) {
3339 val64
^= 0xFFFFFFFFFFFF0000ULL
;
3341 writeq(val64
, &bar0
->mc_rldram_test_d2
);
3343 val64
= (u64
) (0x0000003fffff0000ULL
);
3344 writeq(val64
, &bar0
->mc_rldram_test_add
);
3347 val64
= MC_RLDRAM_TEST_MODE
;
3348 writeq(val64
, &bar0
->mc_rldram_test_ctrl
);
3351 MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
3353 writeq(val64
, &bar0
->mc_rldram_test_ctrl
);
3355 for (cnt
= 0; cnt
< 5; cnt
++) {
3356 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
3357 if (val64
& MC_RLDRAM_TEST_DONE
)
3359 set_current_state(TASK_UNINTERRUPTIBLE
);
3360 schedule_timeout(HZ
/ 5);
3366 val64
= MC_RLDRAM_TEST_MODE
;
3367 writeq(val64
, &bar0
->mc_rldram_test_ctrl
);
3369 val64
|= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
3370 writeq(val64
, &bar0
->mc_rldram_test_ctrl
);
3372 for (cnt
= 0; cnt
< 5; cnt
++) {
3373 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
3374 if (val64
& MC_RLDRAM_TEST_DONE
)
3376 set_current_state(TASK_UNINTERRUPTIBLE
);
3377 schedule_timeout(HZ
/ 2);
3383 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
3384 if (val64
& MC_RLDRAM_TEST_PASS
)
3400 * sp - private member of the device structure, which is a pointer to the
3401 * s2io_nic structure.
3402 * ethtest - pointer to a ethtool command specific structure that will be
3403 * returned to the user.
3404 * data - variable that returns the result of each of the test conducted by
3407 * SUCCESS on success and an appropriate -1 on failure.
3409 * This function conducts 6 tests ( 4 offline and 2 online) to determine
3410 * the health of the card.
3412 static void s2io_ethtool_test(struct net_device
*dev
,
3413 struct ethtool_test
*ethtest
,
3416 nic_t
*sp
= dev
->priv
;
3417 int orig_state
= netif_running(sp
->dev
);
3419 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
3420 /* Offline Tests. */
3422 s2io_close(sp
->dev
);
3423 s2io_set_swapper(sp
);
3425 s2io_set_swapper(sp
);
3427 if (s2io_registerTest(sp
, &data
[0]))
3428 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
3431 s2io_set_swapper(sp
);
3433 if (s2io_rldramTest(sp
, &data
[3]))
3434 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
3437 s2io_set_swapper(sp
);
3439 if (s2io_eepromTest(sp
, &data
[1]))
3440 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
3442 if (s2io_bistTest(sp
, &data
[4]))
3443 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
3453 "%s: is not up, cannot run test\n",
3462 if (s2io_linkTest(sp
, &data
[2]))
3463 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
3472 static void s2io_get_ethtool_stats(struct net_device
*dev
,
3473 struct ethtool_stats
*estats
,
3477 nic_t
*sp
= dev
->priv
;
3478 StatInfo_t
*stat_info
= sp
->mac_control
.StatsInfo
;
3480 tmp_stats
[i
++] = stat_info
->tmac_frms
;
3481 tmp_stats
[i
++] = stat_info
->tmac_data_octets
;
3482 tmp_stats
[i
++] = stat_info
->tmac_drop_frms
;
3483 tmp_stats
[i
++] = stat_info
->tmac_mcst_frms
;
3484 tmp_stats
[i
++] = stat_info
->tmac_bcst_frms
;
3485 tmp_stats
[i
++] = stat_info
->tmac_pause_ctrl_frms
;
3486 tmp_stats
[i
++] = stat_info
->tmac_any_err_frms
;
3487 tmp_stats
[i
++] = stat_info
->tmac_vld_ip_octets
;
3488 tmp_stats
[i
++] = stat_info
->tmac_vld_ip
;
3489 tmp_stats
[i
++] = stat_info
->tmac_drop_ip
;
3490 tmp_stats
[i
++] = stat_info
->tmac_icmp
;
3491 tmp_stats
[i
++] = stat_info
->tmac_rst_tcp
;
3492 tmp_stats
[i
++] = stat_info
->tmac_tcp
;
3493 tmp_stats
[i
++] = stat_info
->tmac_udp
;
3494 tmp_stats
[i
++] = stat_info
->rmac_vld_frms
;
3495 tmp_stats
[i
++] = stat_info
->rmac_data_octets
;
3496 tmp_stats
[i
++] = stat_info
->rmac_fcs_err_frms
;
3497 tmp_stats
[i
++] = stat_info
->rmac_drop_frms
;
3498 tmp_stats
[i
++] = stat_info
->rmac_vld_mcst_frms
;
3499 tmp_stats
[i
++] = stat_info
->rmac_vld_bcst_frms
;
3500 tmp_stats
[i
++] = stat_info
->rmac_in_rng_len_err_frms
;
3501 tmp_stats
[i
++] = stat_info
->rmac_long_frms
;
3502 tmp_stats
[i
++] = stat_info
->rmac_pause_ctrl_frms
;
3503 tmp_stats
[i
++] = stat_info
->rmac_discarded_frms
;
3504 tmp_stats
[i
++] = stat_info
->rmac_usized_frms
;
3505 tmp_stats
[i
++] = stat_info
->rmac_osized_frms
;
3506 tmp_stats
[i
++] = stat_info
->rmac_frag_frms
;
3507 tmp_stats
[i
++] = stat_info
->rmac_jabber_frms
;
3508 tmp_stats
[i
++] = stat_info
->rmac_ip
;
3509 tmp_stats
[i
++] = stat_info
->rmac_ip_octets
;
3510 tmp_stats
[i
++] = stat_info
->rmac_hdr_err_ip
;
3511 tmp_stats
[i
++] = stat_info
->rmac_drop_ip
;
3512 tmp_stats
[i
++] = stat_info
->rmac_icmp
;
3513 tmp_stats
[i
++] = stat_info
->rmac_tcp
;
3514 tmp_stats
[i
++] = stat_info
->rmac_udp
;
3515 tmp_stats
[i
++] = stat_info
->rmac_err_drp_udp
;
3516 tmp_stats
[i
++] = stat_info
->rmac_pause_cnt
;
3517 tmp_stats
[i
++] = stat_info
->rmac_accepted_ip
;
3518 tmp_stats
[i
++] = stat_info
->rmac_err_tcp
;
3521 int s2io_ethtool_get_regs_len(struct net_device
*dev
)
3523 return (XENA_REG_SPACE
);
3527 u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
3529 nic_t
*sp
= dev
->priv
;
3531 return (sp
->rx_csum
);
3533 int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
3535 nic_t
*sp
= dev
->priv
;
3544 int s2io_get_eeprom_len(struct net_device
*dev
)
3546 return (XENA_EEPROM_SPACE
);
3549 int s2io_ethtool_self_test_count(struct net_device
*dev
)
3551 return (S2IO_TEST_LEN
);
3553 void s2io_ethtool_get_strings(struct net_device
*dev
,
3554 u32 stringset
, u8
* data
)
3556 switch (stringset
) {
3558 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
3561 memcpy(data
, ðtool_stats_keys
,
3562 sizeof(ethtool_stats_keys
));
3565 static int s2io_ethtool_get_stats_count(struct net_device
*dev
)
3567 return (S2IO_STAT_LEN
);
3570 static struct ethtool_ops netdev_ethtool_ops
= {
3571 .get_settings
= s2io_ethtool_gset
,
3572 .set_settings
= s2io_ethtool_sset
,
3573 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
3574 .get_regs_len
= s2io_ethtool_get_regs_len
,
3575 .get_regs
= s2io_ethtool_gregs
,
3576 .get_link
= ethtool_op_get_link
,
3577 .get_eeprom_len
= s2io_get_eeprom_len
,
3578 .get_eeprom
= s2io_ethtool_geeprom
,
3579 .set_eeprom
= s2io_ethtool_seeprom
,
3580 .get_pauseparam
= s2io_ethtool_getpause_data
,
3581 .set_pauseparam
= s2io_ethtool_setpause_data
,
3582 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
3583 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
3584 .get_tx_csum
= ethtool_op_get_tx_csum
,
3585 .set_tx_csum
= ethtool_op_set_tx_csum
,
3586 .get_sg
= ethtool_op_get_sg
,
3587 .set_sg
= ethtool_op_set_sg
,
3589 .get_tso
= ethtool_op_get_tso
,
3590 .set_tso
= ethtool_op_set_tso
,
3592 .self_test_count
= s2io_ethtool_self_test_count
,
3593 .self_test
= s2io_ethtool_test
,
3594 .get_strings
= s2io_ethtool_get_strings
,
3595 .phys_id
= s2io_ethtool_idnic
,
3596 .get_stats_count
= s2io_ethtool_get_stats_count
,
3597 .get_ethtool_stats
= s2io_get_ethtool_stats
3602 * dev - Device pointer.
3603 * ifr - An IOCTL specefic structure, that can contain a pointer to
3604 * a proprietary structure used to pass information to the driver.
3605 * cmd - This is used to distinguish between the different commands that
3606 * can be passed to the IOCTL functions.
3608 * '0' on success and an appropriate (-)ve integer as defined in errno.h
3611 * This function has support for ethtool, adding multiple MAC addresses on
3612 * the NIC and some DBG commands for the util tool.
3614 int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
3621 * dev - device pointer.
3622 * new_mtu - the new MTU size for the device.
3624 * '0' on success and an appropriate (-)ve integer as defined in errno.h
3627 * A driver entry point to change MTU size for the device. Before changing
3628 * the MTU the device must be stopped.
3630 int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
3632 nic_t
*sp
= dev
->priv
;
3633 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) sp
->bar0
;
3636 if (netif_running(dev
)) {
3637 DBG_PRINT(ERR_DBG
, "%s: Must be stopped to ", dev
->name
);
3638 DBG_PRINT(ERR_DBG
, "change its MTU \n");
3642 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
3643 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
3648 /* Set the new MTU into the PYLD register of the NIC */
3650 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
3659 * dev_adr - address of the device structure in dma_addr_t format.
3663 * This is the tasklet or the bottom half of the ISR. This is
3664 * an extension of the ISR which is scheduled by the scheduler to be run
3665 * when the load on the CPU is low. All low priority tasks of the ISR can
3666 * be pushed into the tasklet. For now the tasklet is used only to
3667 * replenish the Rx buffers in the Rx buffer descriptors.
3669 static void s2io_tasklet(unsigned long dev_addr
)
3671 struct net_device
*dev
= (struct net_device
*) dev_addr
;
3672 nic_t
*sp
= dev
->priv
;
3674 mac_info_t
*mac_control
;
3675 struct config_param
*config
;
3677 mac_control
= &sp
->mac_control
;
3678 config
= &sp
->config
;
3680 if (!TASKLET_IN_USE
) {
3681 for (i
= 0; i
< config
->RxRingNum
; i
++) {
3682 ret
= fill_rx_buffers(sp
, i
);
3683 if (ret
== -ENOMEM
) {
3684 DBG_PRINT(ERR_DBG
, "%s: Out of ",
3686 DBG_PRINT(ERR_DBG
, "memory in tasklet\n");
3688 } else if (ret
== -EFILL
) {
3690 "%s: Rx Ring %d is full\n",
3695 clear_bit(0, (unsigned long *) (&sp
->tasklet_status
));
3704 static void s2io_set_link(unsigned long data
)
3706 nic_t
*nic
= (nic_t
*) data
;
3707 struct net_device
*dev
= nic
->dev
;
3708 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
3709 register u64 val64
, err_reg
;
3711 /* Allow a small delay for the NICs self initiated
3712 * cleanup to complete.
3714 set_current_state(TASK_UNINTERRUPTIBLE
);
3715 schedule_timeout(HZ
/ 10);
3717 val64
= readq(&bar0
->adapter_status
);
3718 if (verify_xena_quiescence(val64
, nic
->device_enabled_once
)) {
3719 /* Acknowledge interrupt and clear the R1 register */
3720 err_reg
= readq(&bar0
->mac_rmac_err_reg
);
3721 writeq(err_reg
, &bar0
->mac_rmac_err_reg
);
3723 if (LINK_IS_UP(val64
)) {
3724 val64
= readq(&bar0
->adapter_control
);
3725 val64
|= ADAPTER_CNTL_EN
;
3726 writeq(val64
, &bar0
->adapter_control
);
3727 val64
|= ADAPTER_LED_ON
;
3728 writeq(val64
, &bar0
->adapter_control
);
3729 val64
= readq(&bar0
->adapter_status
);
3730 if (!LINK_IS_UP(val64
)) {
3731 DBG_PRINT(ERR_DBG
, "%s:", dev
->name
);
3732 DBG_PRINT(ERR_DBG
, " Link down");
3733 DBG_PRINT(ERR_DBG
, "after ");
3734 DBG_PRINT(ERR_DBG
, "enabling ");
3735 DBG_PRINT(ERR_DBG
, "device \n");
3737 if (nic
->device_enabled_once
== FALSE
) {
3738 nic
->device_enabled_once
= TRUE
;
3740 s2io_link(nic
, LINK_UP
);
3742 s2io_link(nic
, LINK_DOWN
);
3744 } else { /* NIC is not Quiescent. */
3745 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
3746 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
3747 netif_stop_queue(dev
);
3753 * This function is scheduled to be run by the s2io_tx_watchdog
3754 * function after 0.5 secs to reset the NIC. The idea is to reduce
3755 * the run time of the watch dog routine which is run holding a
3758 static void s2io_restart_nic(unsigned long data
)
3760 struct net_device
*dev
= (struct net_device
*) data
;
3761 nic_t
*sp
= dev
->priv
;
3764 sp
->device_close_flag
= TRUE
;
3767 "%s: was reset by Tx watchdog timer.\n", dev
->name
);
3772 * dev - device pointer.
3776 * This function is triggered if the Tx Queue is stopped
3777 * for a pre-defined amount of time when the Interface is still up.
3778 * If the Interface is jammed in such a situation, the hardware is
3779 * reset (by s2io_close) and restarted again (by s2io_open) to
3780 * overcome any problem that might have been caused in the hardware.
3782 static void s2io_tx_watchdog(struct net_device
*dev
)
3784 nic_t
*sp
= dev
->priv
;
3786 if (netif_carrier_ok(dev
)) {
3787 schedule_work(&sp
->rst_timer_task
);
3793 * sp - private member of the device structure, which is a pointer to the
3794 * s2io_nic structure.
3795 * skb - the socket buffer pointer.
3796 * len - length of the packet
3797 * cksum - FCS checksum of the frame.
3798 * ring_no - the ring from which this RxD was extracted.
3800 * SUCCESS on success and -1 on failure.
3802 * This function is called by the Tx interrupt serivce routine to perform
3803 * some OS related operations on the SKB before passing it to the upper
3804 * layers. It mainly checks if the checksum is OK, if so adds it to the
3805 * SKBs cksum variable, increments the Rx packet count and passes the SKB
3806 * to the upper layer. If the checksum is wrong, it increments the Rx
3807 * packet error count, frees the SKB and returns error.
3809 static int rxOsmHandler(nic_t
* sp
, u16 len
, RxD_t
* rxdp
, int ring_no
)
3811 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
3812 struct sk_buff
*skb
=
3813 (struct sk_buff
*) ((unsigned long) rxdp
->Host_Control
);
3814 u16 l3_csum
, l4_csum
;
3816 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
3817 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) && (sp
->rx_csum
)) {
3818 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
3819 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
3820 /* NIC verifies if the Checksum of the received
3821 * frame is Ok or not and accordingly returns
3822 * a flag in the RxD.
3824 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3827 * Packet with erroneous checksum, let the
3828 * upper layers deal with it.
3830 skb
->ip_summed
= CHECKSUM_NONE
;
3833 skb
->ip_summed
= CHECKSUM_NONE
;
3838 skb
->protocol
= eth_type_trans(skb
, dev
);
3840 #ifdef CONFIG_S2IO_NAPI
3841 netif_receive_skb(skb
);
3846 dev
->last_rx
= jiffies
;
3851 sp
->stats
.rx_packets
++;
3852 sp
->stats
.rx_bytes
+= len
;
3853 sp
->rxpkt_bytes
+= len
;
3855 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
3856 rxdp
->Host_Control
= 0;
3860 int check_for_txSpace(nic_t
* sp
)
3862 u32 put_off
, get_off
, queue_len
;
3865 for (i
= 0; i
< sp
->config
.TxFIFONum
; i
++) {
3866 queue_len
= sp
->mac_control
.tx_curr_put_info
[i
].fifo_len
3868 put_off
= sp
->mac_control
.tx_curr_put_info
[i
].offset
;
3869 get_off
= sp
->mac_control
.tx_curr_get_info
[i
].offset
;
3870 if (((put_off
+ 1) % queue_len
) == get_off
) {
3881 * sp - private member of the device structure, which is a pointer to the
3882 * s2io_nic structure.
3883 * link - inidicates whether link is UP/DOWN.
3887 * This function stops/starts the Tx queue depending on whether the link
3888 * status of the NIC is is down or up. This is called by the Alarm interrupt
3889 * handler whenever a link change interrupt comes up.
3891 void s2io_link(nic_t
* sp
, int link
)
3893 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
3895 if (link
!= sp
->last_link_state
) {
3896 if (link
== LINK_DOWN
) {
3897 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
3898 netif_carrier_off(dev
);
3899 netif_stop_queue(dev
);
3901 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
3902 netif_carrier_on(dev
);
3903 if (check_for_txSpace(sp
) == TRUE
) {
3904 /* Don't wake the queue, if we know there
3905 * are no free TxDs available.
3907 netif_wake_queue(dev
);
3911 sp
->last_link_state
= link
;
3916 * pdev - structure containing the PCI related information of the device.
3918 * returns the revision ID of the device.
3920 * Function to identify the Revision ID of xena.
3922 int get_xena_rev_id(struct pci_dev
*pdev
)
3926 ret
= pci_read_config_byte(pdev
, PCI_REVISION_ID
, (u8
*) & id
);
3932 * sp - private member of the device structure, which is a pointer to the
3933 * s2io_nic structure.
3937 * This function initializes a few of the PCI and PCI-X configuration registers
3938 * with recommended values.
3940 static void s2io_init_pci(nic_t
* sp
)
3944 /* Enable Data Parity Error Recovery in PCI-X command register. */
3945 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
3947 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
3948 (sp
->pcix_cmd
| 1));
3949 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
3952 /* Set the PErr Response bit in PCI command register. */
3953 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
3954 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
3955 (pci_cmd
| PCI_COMMAND_PARITY
));
3956 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
3958 /* Set user specified value in Latency Timer */
3959 if (latency_timer
) {
3960 pci_write_config_byte(sp
->pdev
, PCI_LATENCY_TIMER
,
3962 pci_read_config_byte(sp
->pdev
, PCI_LATENCY_TIMER
,
3966 /* Set MMRB count to 4096 in PCI-X Command register. */
3967 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
3968 (sp
->pcix_cmd
| 0x0C));
3969 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
3972 /* Setting Maximum outstanding splits to two for now. */
3973 sp
->pcix_cmd
&= 0xFF1F;
3976 XENA_MAX_OUTSTANDING_SPLITS(XENA_TWO_SPLIT_TRANSACTION
);
3977 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
3979 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
3984 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@s2io.com>");
3985 MODULE_LICENSE("GPL");
3986 MODULE_PARM(ring_num
, "1-" __MODULE_STRING(1) "i");
3987 MODULE_PARM(frame_len
, "1-" __MODULE_STRING(8) "i");
3988 MODULE_PARM(ring_len
, "1-" __MODULE_STRING(8) "i");
3989 MODULE_PARM(fifo_num
, "1-" __MODULE_STRING(1) "i");
3990 MODULE_PARM(fifo_len
, "1-" __MODULE_STRING(8) "i");
3991 MODULE_PARM(rx_prio
, "1-" __MODULE_STRING(1) "i");
3992 MODULE_PARM(tx_prio
, "1-" __MODULE_STRING(1) "i");
3993 MODULE_PARM(latency_timer
, "1-" __MODULE_STRING(1) "i");
3997 * pdev - structure containing the PCI related information of the device.
3998 * pre - the List of PCI devices supported by the driver listed in s2io_tbl.
4000 * returns '0' on success and negative on failure.
4002 * The function initializes an adapter identified by the pci_dec structure.
4003 * All OS related initialization including memory and device structure and
4004 * initlaization of the device private variable is done. Also the swapper
4005 * control register is initialized to enable read and write into the I/O
4006 * registers of the device.
4009 static int __devinit
4010 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
4013 struct net_device
*dev
;
4014 char *dev_name
= "S2IO 10GE NIC";
4016 int dma_flag
= FALSE
;
4017 u32 mac_up
, mac_down
;
4018 u64 val64
= 0, tmp64
= 0;
4019 XENA_dev_config_t
*bar0
= NULL
;
4021 mac_info_t
*mac_control
;
4022 struct config_param
*config
;
4025 if ((ret
= pci_enable_device(pdev
))) {
4027 "s2io_init_nic: pci_enable_device failed\n");
4031 if (!pci_set_dma_mask(pdev
, 0xffffffffffffffffULL
)) {
4032 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
4034 if (pci_set_consistent_dma_mask
4035 (pdev
, 0xffffffffffffffffULL
)) {
4037 "Unable to obtain 64bit DMA for \
4038 consistent allocations\n");
4039 pci_disable_device(pdev
);
4042 } else if (!pci_set_dma_mask(pdev
, 0xffffffffUL
)) {
4043 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
4045 pci_disable_device(pdev
);
4049 if (pci_request_regions(pdev
, s2io_driver_name
)) {
4050 DBG_PRINT(ERR_DBG
, "Request Regions failed\n"),
4051 pci_disable_device(pdev
);
4055 dev
= alloc_etherdev(sizeof(nic_t
));
4057 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
4058 pci_disable_device(pdev
);
4059 pci_release_regions(pdev
);
4063 pci_set_master(pdev
);
4064 pci_set_drvdata(pdev
, dev
);
4065 SET_MODULE_OWNER(dev
);
4066 SET_NETDEV_DEV(dev
, &pdev
->dev
);
4068 /* Private member variable initialized to s2io NIC structure */
4070 memset(sp
, 0, sizeof(nic_t
));
4073 sp
->vendor_id
= pdev
->vendor
;
4074 sp
->device_id
= pdev
->device
;
4075 sp
->high_dma_flag
= dma_flag
;
4076 sp
->irq
= pdev
->irq
;
4077 sp
->device_enabled_once
= FALSE
;
4078 strcpy(sp
->name
, dev_name
);
4080 /* Initialize some PCI/PCI-X fields of the NIC. */
4083 /* Setting the device configuration parameters.
4084 * Most of these parameters can be specified by the user during
4085 * module insertion as they are module loadable parameters. If
4086 * these parameters are not not specified during load time, they
4087 * are initialized with default values.
4089 mac_control
= &sp
->mac_control
;
4090 config
= &sp
->config
;
4092 /* Tx side parameters. */
4093 config
->TxFIFONum
= fifo_num
? fifo_num
: 1;
4095 if (!fifo_len
[0] && (fifo_num
> 1)) {
4096 printk(KERN_ERR
"Fifo Lens not specified for all FIFOs\n");
4103 for (cnt
= 0; fifo_len
[cnt
]; cnt
++);
4105 if (cnt
< fifo_num
) {
4107 "Fifo Lens not specified for ");
4108 printk(KERN_ERR
"all FIFOs\n");
4112 for (cnt
= 0; cnt
< config
->TxFIFONum
; cnt
++) {
4113 config
->TxCfg
[cnt
].FifoLen
= fifo_len
[cnt
];
4114 config
->TxCfg
[cnt
].FifoPriority
= cnt
;
4117 config
->TxCfg
[0].FifoLen
= DEFAULT_FIFO_LEN
;
4118 config
->TxCfg
[0].FifoPriority
= 0;
4121 config
->TxIntrType
= TXD_INT_TYPE_UTILZ
;
4122 for (i
= 0; i
< config
->TxFIFONum
; i
++) {
4123 if (config
->TxCfg
[i
].FifoLen
< 65) {
4124 config
->TxIntrType
= TXD_INT_TYPE_PER_LIST
;
4129 config
->TxCfg
[0].fNoSnoop
= (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
4130 config
->MaxTxDs
= MAX_SKB_FRAGS
;
4131 config
->TxFlow
= TRUE
;
4133 /* Rx side parameters. */
4134 config
->RxRingNum
= ring_num
? ring_num
: 1;
4138 for (cnt
= 0; cnt
< config
->RxRingNum
; cnt
++) {
4139 config
->RxCfg
[cnt
].NumRxd
= ring_len
[cnt
];
4140 config
->RxCfg
[cnt
].RingPriority
= cnt
;
4144 if ((id
= get_xena_rev_id(pdev
)) == 1) {
4145 config
->RxCfg
[0].NumRxd
= LARGE_RXD_CNT
;
4148 config
->RxCfg
[0].NumRxd
= SMALL_RXD_CNT
;
4150 config
->RxCfg
[0].RingPriority
= 0;
4152 config
->RxCfg
[0].RingOrg
= RING_ORG_BUFF1
;
4153 config
->RxCfg
[0].RxdThresh
= DEFAULT_RXD_THRESHOLD
;
4154 config
->RxCfg
[0].fNoSnoop
= (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
4155 config
->RxCfg
[0].RxD_BackOff_Interval
= TBD
;
4156 config
->RxFlow
= TRUE
;
4158 /* Miscellaneous parameters. */
4159 config
->RxVLANEnable
= TRUE
;
4160 config
->MTU
= MAX_MTU_VLAN
;
4161 config
->JumboEnable
= FALSE
;
4163 /* Setting Mac Control parameters */
4164 mac_control
->txdl_len
= MAX_SKB_FRAGS
;
4165 mac_control
->rmac_pause_time
= 0;
4167 /* Initialize Ring buffer parameters. */
4168 for (i
= 0; i
< config
->RxRingNum
; i
++)
4169 atomic_set(&sp
->rx_bufs_left
[i
], 0);
4171 /* initialize the shared memory used by the NIC and the host */
4172 if (initSharedMem(sp
)) {
4173 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
4175 goto mem_alloc_failed
;
4178 sp
->bar0
= (caddr_t
) ioremap(pci_resource_start(pdev
, 0),
4179 pci_resource_len(pdev
, 0));
4181 DBG_PRINT(ERR_DBG
, "%s: S2IO: cannot remap io mem1\n",
4183 goto bar0_remap_failed
;
4186 sp
->bar1
= (caddr_t
) ioremap(pci_resource_start(pdev
, 2),
4187 pci_resource_len(pdev
, 2));
4189 DBG_PRINT(ERR_DBG
, "%s: S2IO: cannot remap io mem2\n",
4191 goto bar1_remap_failed
;
4194 dev
->irq
= pdev
->irq
;
4195 dev
->base_addr
= (unsigned long) sp
->bar0
;
4197 /* Initializing the BAR1 address as the start of the FIFO pointer. */
4198 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
4199 mac_control
->tx_FIFO_start
[j
] = (TxFIFO_element_t
*)
4200 (sp
->bar1
+ (j
* 0x00020000));
4203 /* Driver entry points */
4204 dev
->open
= &s2io_open
;
4205 dev
->stop
= &s2io_close
;
4206 dev
->hard_start_xmit
= &s2io_xmit
;
4207 dev
->get_stats
= &s2io_get_stats
;
4208 dev
->set_multicast_list
= &s2io_set_multicast
;
4209 dev
->do_ioctl
= &s2io_ioctl
;
4210 dev
->change_mtu
= &s2io_change_mtu
;
4211 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
4214 * will use eth_mac_addr() for dev->set_mac_address
4215 * mac address will be set every time dev->open() is called
4217 #ifdef CONFIG_S2IO_NAPI
4218 dev
->poll
= s2io_poll
;
4219 dev
->weight
= 128; /* For now. */
4222 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
4223 if (sp
->high_dma_flag
== TRUE
)
4224 dev
->features
|= NETIF_F_HIGHDMA
;
4226 dev
->features
|= NETIF_F_TSO
;
4229 dev
->tx_timeout
= &s2io_tx_watchdog
;
4230 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
4231 INIT_WORK(&sp
->rst_timer_task
,
4232 (void (*)(void *)) s2io_restart_nic
, dev
);
4233 INIT_WORK(&sp
->set_link_task
,
4234 (void (*)(void *)) s2io_set_link
, sp
);
4236 if (register_netdev(dev
)) {
4237 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
4238 goto register_failed
;
4241 pci_save_state(sp
->pdev
, sp
->config_space
);
4243 /* Setting swapper control on the NIC, for proper reset operation */
4244 if (s2io_set_swapper(sp
)) {
4245 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
4247 goto set_swap_failed
;
4250 /* Fix for all "FFs" MAC address problems observed on Alpha platforms */
4254 /* Setting swapper control on the NIC, so the MAC address can be read.
4256 if (s2io_set_swapper(sp
)) {
4258 "%s: S2IO: swapper settings are wrong\n",
4260 goto set_swap_failed
;
4263 /* MAC address initialization.
4264 * For now only one mac address will be read and used.
4266 bar0
= (XENA_dev_config_t
*) sp
->bar0
;
4267 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4268 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET
);
4269 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4270 waitForCmdComplete(sp
);
4272 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
4273 mac_down
= (u32
) tmp64
;
4274 mac_up
= (u32
) (tmp64
>> 32);
4276 memset(sp
->defMacAddr
[0].mac_addr
, 0, sizeof(ETH_ALEN
));
4278 sp
->defMacAddr
[0].mac_addr
[3] = (u8
) (mac_up
);
4279 sp
->defMacAddr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
4280 sp
->defMacAddr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
4281 sp
->defMacAddr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
4282 sp
->defMacAddr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
4283 sp
->defMacAddr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
4286 "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
4287 sp
->defMacAddr
[0].mac_addr
[0],
4288 sp
->defMacAddr
[0].mac_addr
[1],
4289 sp
->defMacAddr
[0].mac_addr
[2],
4290 sp
->defMacAddr
[0].mac_addr
[3],
4291 sp
->defMacAddr
[0].mac_addr
[4],
4292 sp
->defMacAddr
[0].mac_addr
[5]);
4294 /* Set the factory defined MAC address initially */
4295 dev
->addr_len
= ETH_ALEN
;
4296 memcpy(dev
->dev_addr
, sp
->defMacAddr
, ETH_ALEN
);
4298 /* Initialize the tasklet status flag */
4299 atomic_set(&(sp
->tasklet_status
), 0);
4302 /* Initialize spinlocks */
4303 spin_lock_init(&sp
->isr_lock
);
4304 spin_lock_init(&sp
->tx_lock
);
4306 /* SXE-002: Configure link and activity LED to init state
4309 subid
= sp
->pdev
->subsystem_device
;
4310 if ((subid
& 0xFF) >= 0x07) {
4311 val64
= readq(&bar0
->gpio_control
);
4312 val64
|= 0x0000800000000000ULL
;
4313 writeq(val64
, &bar0
->gpio_control
);
4314 val64
= 0x0411040400000000ULL
;
4315 writeq(val64
, (u64
*) ((u8
*) bar0
+ 0x2700));
4316 val64
= readq(&bar0
->gpio_control
);
4319 /* Make Link state as off at this point, when the Link change
4320 * interrupt comes the state will be automatically changed to
4323 netif_carrier_off(dev
);
4324 sp
->last_link_state
= LINK_DOWN
;
4326 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
4331 unregister_netdev(dev
);
4340 pci_disable_device(pdev
);
4341 pci_release_regions(pdev
);
4342 pci_set_drvdata(pdev
, NULL
);
4350 * pdev - structure containing the PCI related information of the device.
4354 * This function is called by the Pci subsystem to release a PCI device
4355 * and free up all resource held up by the device. This could be in response
4356 * to a Hot plug event or when the driver is to be removed from memory.
4358 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
4360 struct net_device
*dev
=
4361 (struct net_device
*) pci_get_drvdata(pdev
);
4365 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
4372 pci_disable_device(pdev
);
4373 pci_release_regions(pdev
);
4374 pci_set_drvdata(pdev
, NULL
);
4376 unregister_netdev(dev
);
4381 int __init
s2io_starter(void)
4383 return pci_module_init(&s2io_driver
);
4386 void s2io_closer(void)
4388 pci_unregister_driver(&s2io_driver
);
4389 DBG_PRINT(INIT_DBG
, "cleanup done\n");
4392 module_init(s2io_starter
);
4393 module_exit(s2io_closer
);