?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / s2io.c
blobc68c1c0e7163926950a0129e71bba1faf4dc6f03
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright(c) 2002-2005 S2IO Technologies
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 * ring_num : This can be used to program the number of receive rings used
30 * in the driver.
31 * frame_len: This is an array of size 8. Using this we can set the maximum
32 * size of the received frame that can be steered into the corrsponding
33 * receive ring.
34 * ring_len: This defines the number of descriptors each ring can have. This
35 * is also an array of size 8.
36 * fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * latency_timer: This input is programmed into the Latency timer register
40 * in PCI Configuration space.
41 ************************************************************************/
42
43 #include<linux/config.h>
44 #include<linux/module.h>
45 #include<linux/types.h>
46 #include<linux/errno.h>
47 #include<linux/ioport.h>
48 #include<linux/pci.h>
49 #include<linux/kernel.h>
50 #include<linux/netdevice.h>
51 #include<linux/etherdevice.h>
52 #include<linux/skbuff.h>
53 #include<linux/init.h>
54 #include<linux/delay.h>
55 #include<linux/stddef.h>
56 #include<linux/ioctl.h>
57 #include<linux/timex.h>
58 #include<linux/sched.h>
59 #include<linux/ethtool.h>
60 #include<asm/system.h>
61 #include<asm/uaccess.h>
62 #include<linux/version.h>
63 #include<asm/io.h>
64 #include<linux/workqueue.h>
65
66 /* local include */
67 #include "s2io.h"
68 #include "s2io-regs.h"
69
70 /* S2io Driver name & version. */
71 static char s2io_driver_name[] = "s2io";
72 static char s2io_driver_version[] = "Version 1.0";
73
74 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
75 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
76 #define TASKLET_IN_USE test_and_set_bit(0, \
77 (unsigned long *)(&sp->tasklet_status))
78 #define PANIC 1
79 #define LOW 2
80 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
81 {
82 int level = 0;
83 if ((sp->pkt_cnt[ring] - rxb_size) > 128) {
84 level = LOW;
85 if (rxb_size < sp->pkt_cnt[ring] / 8)
86 level = PANIC;
87 }
88
89 return level;
90 }
91
92 /* Ethtool related variables and Macros. */
93 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
94 "Register test\t(offline)",
95 "Eeprom test\t(offline)",
96 "Link test\t(online)",
97 "RLDRAM test\t(offline)",
98 "BIST Test\t(offline)"
99 };
100
101 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
102 "tmac_frms",
103 "tmac_data_octets",
104 "tmac_drop_frms",
105 "tmac_mcst_frms",
106 "tmac_bcst_frms",
107 "tmac_pause_ctrl_frms",
108 "tmac_any_err_frms",
109 "tmac_vld_ip_octets",
110 "tmac_vld_ip",
111 "tmac_drop_ip",
112 "tmac_icmp",
113 "tmac_rst_tcp",
114 "tmac_tcp",
115 "tmac_udp",
116 "rmac_vld_frms",
117 "rmac_data_octets",
118 "rmac_fcs_err_frms",
119 "rmac_drop_frms",
120 "rmac_vld_mcst_frms",
121 "rmac_vld_bcst_frms",
122 "rmac_in_rng_len_err_frms",
123 "rmac_long_frms",
124 "rmac_pause_ctrl_frms",
125 "rmac_discarded_frms",
126 "rmac_usized_frms",
127 "rmac_osized_frms",
128 "rmac_frag_frms",
129 "rmac_jabber_frms",
130 "rmac_ip",
131 "rmac_ip_octets",
132 "rmac_hdr_err_ip",
133 "rmac_drop_ip",
134 "rmac_icmp",
135 "rmac_tcp",
136 "rmac_udp",
137 "rmac_err_drp_udp",
138 "rmac_pause_cnt",
139 "rmac_accepted_ip",
140 "rmac_err_tcp",
141 };
142
143 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
144 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
145
146 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
147 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
148
149
150 /* Constants to be programmed into the Xena's registers to configure
151 * the XAUI.
152 */
153
154 #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
155 #define END_SIGN 0x0
156
157 static u64 default_mdio_cfg[] = {
158 /* Reset PMA PLL */
159 0xC001010000000000ULL, 0xC0010100000000E0ULL,
160 0xC0010100008000E4ULL,
161 /* Remove Reset from PMA PLL */
162 0xC001010000000000ULL, 0xC0010100000000E0ULL,
163 0xC0010100000000E4ULL,
164 END_SIGN
165 };
166
167 static u64 default_dtx_cfg[] = {
168 0x8000051500000000ULL, 0x80000515000000E0ULL,
169 0x80000515D93500E4ULL, 0x8001051500000000ULL,
170 0x80010515000000E0ULL, 0x80010515001E00E4ULL,
171 0x8002051500000000ULL, 0x80020515000000E0ULL,
172 0x80020515F21000E4ULL,
173 /* Set PADLOOPBACKN */
174 0x8002051500000000ULL, 0x80020515000000E0ULL,
175 0x80020515B20000E4ULL, 0x8003051500000000ULL,
176 0x80030515000000E0ULL, 0x80030515B20000E4ULL,
177 0x8004051500000000ULL, 0x80040515000000E0ULL,
178 0x80040515B20000E4ULL, 0x8005051500000000ULL,
179 0x80050515000000E0ULL, 0x80050515B20000E4ULL,
180 SWITCH_SIGN,
181 /* Remove PADLOOPBACKN */
182 0x8002051500000000ULL, 0x80020515000000E0ULL,
183 0x80020515F20000E4ULL, 0x8003051500000000ULL,
184 0x80030515000000E0ULL, 0x80030515F20000E4ULL,
185 0x8004051500000000ULL, 0x80040515000000E0ULL,
186 0x80040515F20000E4ULL, 0x8005051500000000ULL,
187 0x80050515000000E0ULL, 0x80050515F20000E4ULL,
188 END_SIGN
189 };
190
191 /* Constants for Fixing the MacAddress problem seen mostly on
192 * Alpha machines.
193 */
194 static u64 fix_mac[] = {
195 0x0060000000000000ULL, 0x0060600000000000ULL,
196 0x0040600000000000ULL, 0x0000600000000000ULL,
197 0x0020600000000000ULL, 0x0060600000000000ULL,
198 0x0020600000000000ULL, 0x0060600000000000ULL,
199 0x0020600000000000ULL, 0x0060600000000000ULL,
200 0x0020600000000000ULL, 0x0060600000000000ULL,
201 0x0020600000000000ULL, 0x0060600000000000ULL,
202 0x0020600000000000ULL, 0x0060600000000000ULL,
203 0x0020600000000000ULL, 0x0060600000000000ULL,
204 0x0020600000000000ULL, 0x0060600000000000ULL,
205 0x0020600000000000ULL, 0x0060600000000000ULL,
206 0x0020600000000000ULL, 0x0060600000000000ULL,
207 0x0020600000000000ULL, 0x0000600000000000ULL,
208 0x0040600000000000ULL, 0x0060600000000000ULL,
209 END_SIGN
210 };
211
212
213 /* Module Loadable parameters. */
214 static u32 ring_num;
215 static u32 frame_len[MAX_RX_RINGS];
216 static u32 ring_len[MAX_RX_RINGS];
217 static u32 fifo_num;
218 static u32 fifo_len[MAX_TX_FIFOS];
219 static u32 rx_prio;
220 static u32 tx_prio;
221 static u8 latency_timer = 0;
222
223 /*
224 * S2IO device table.
225 * This table lists all the devices that this driver supports.
226 */
227 static struct pci_device_id s2io_tbl[] __devinitdata = {
228 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
229 PCI_ANY_ID, PCI_ANY_ID},
230 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
231 PCI_ANY_ID, PCI_ANY_ID},
232 {0,}
233 };
234
235 MODULE_DEVICE_TABLE(pci, s2io_tbl);
236
237 static struct pci_driver s2io_driver = {
238 .name = "S2IO",
239 .id_table = s2io_tbl,
240 .probe = s2io_init_nic,
241 .remove = __devexit_p(s2io_rem_nic),
242 };
243
244 /*
245 * Input Arguments:
246 * Device private variable.
247 * Return Value:
248 * SUCCESS on success and an appropriate -ve value on failure.
249 * Description:
250 * The function allocates the all memory areas shared
251 * between the NIC and the driver. This includes Tx descriptors,
252 * Rx descriptors and the statistics block.
253 */
254 static int initSharedMem(struct s2io_nic *nic)
255 {
256 u32 size;
257 void *tmp_v_addr, *tmp_v_addr_next;
258 dma_addr_t tmp_p_addr, tmp_p_addr_next;
259 RxD_block_t *pre_rxd_blk = NULL;
260 int i, j, blk_cnt;
261 struct net_device *dev = nic->dev;
262
263 mac_info_t *mac_control;
264 struct config_param *config;
265
266 mac_control = &nic->mac_control;
267 config = &nic->config;
268
269
270 /* Allocation and initialization of TXDLs in FIOFs */
271 size = 0;
272 for (i = 0; i < config->TxFIFONum; i++) {
273 size += config->TxCfg[i].FifoLen;
274 }
275 if (size > MAX_AVAILABLE_TXDS) {
276 DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ",
277 dev->name);
278 DBG_PRINT(ERR_DBG, "exceeds the maximum value ");
279 DBG_PRINT(ERR_DBG, "that can be used\n");
280 return FAILURE;
281 }
282 size *= (sizeof(TxD_t) * config->MaxTxDs);
283
284 mac_control->txd_list_mem = pci_alloc_consistent
285 (nic->pdev, size, &mac_control->txd_list_mem_phy);
286 if (!mac_control->txd_list_mem) {
287 return -ENOMEM;
288 }
289 mac_control->txd_list_mem_sz = size;
290
291 tmp_v_addr = mac_control->txd_list_mem;
292 tmp_p_addr = mac_control->txd_list_mem_phy;
293 memset(tmp_v_addr, 0, size);
294
295 DBG_PRINT(INIT_DBG, "%s:List Mem PHY: 0x%llx\n", dev->name,
296 (unsigned long long) tmp_p_addr);
297
298 for (i = 0; i < config->TxFIFONum; i++) {
299 mac_control->txdl_start_phy[i] = tmp_p_addr;
300 mac_control->txdl_start[i] = (TxD_t *) tmp_v_addr;
301 mac_control->tx_curr_put_info[i].offset = 0;
302 mac_control->tx_curr_put_info[i].fifo_len =
303 config->TxCfg[i].FifoLen - 1;
304 mac_control->tx_curr_get_info[i].offset = 0;
305 mac_control->tx_curr_get_info[i].fifo_len =
306 config->TxCfg[i].FifoLen - 1;
307
308 tmp_p_addr +=
309 (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) *
310 config->MaxTxDs);
311 tmp_v_addr +=
312 (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) *
313 config->MaxTxDs);
314 }
315
316 /* Allocation and initialization of RXDs in Rings */
317 size = 0;
318 for (i = 0; i < config->RxRingNum; i++) {
319 if (config->RxCfg[i].NumRxd % (MAX_RXDS_PER_BLOCK + 1)) {
320 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
321 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
322 i);
323 DBG_PRINT(ERR_DBG, "RxDs per Block");
324 return FAILURE;
325 }
326 size += config->RxCfg[i].NumRxd;
327 nic->block_count[i] =
328 config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
329 nic->pkt_cnt[i] =
330 config->RxCfg[i].NumRxd - nic->block_count[i];
331 }
332 size = (size * (sizeof(RxD_t)));
333 mac_control->rxd_ring_mem_sz = size;
334
335 for (i = 0; i < config->RxRingNum; i++) {
336 mac_control->rx_curr_get_info[i].block_index = 0;
337 mac_control->rx_curr_get_info[i].offset = 0;
338 mac_control->rx_curr_get_info[i].ring_len =
339 config->RxCfg[i].NumRxd - 1;
340 mac_control->rx_curr_put_info[i].block_index = 0;
341 mac_control->rx_curr_put_info[i].offset = 0;
342 mac_control->rx_curr_put_info[i].ring_len =
343 config->RxCfg[i].NumRxd - 1;
344 blk_cnt =
345 config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
346 /* Allocating all the Rx blocks */
347 for (j = 0; j < blk_cnt; j++) {
348 size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
349 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
350 &tmp_p_addr);
351 if (tmp_v_addr == NULL) {
352 /* In case of failure, freeSharedMem()
353 * is called, which should free any
354 * memory that was alloced till the
355 * failure happened.
356 */
357 nic->rx_blocks[i][j].block_virt_addr =
358 tmp_v_addr;
359 return -ENOMEM;
360 }
361 memset(tmp_v_addr, 0, size);
362 nic->rx_blocks[i][j].block_virt_addr = tmp_v_addr;
363 nic->rx_blocks[i][j].block_dma_addr = tmp_p_addr;
364 }
365 /* Interlinking all Rx Blocks */
366 for (j = 0; j < blk_cnt; j++) {
367 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
368 tmp_v_addr_next =
369 nic->rx_blocks[i][(j + 1) %
370 blk_cnt].block_virt_addr;
371 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
372 tmp_p_addr_next =
373 nic->rx_blocks[i][(j + 1) %
374 blk_cnt].block_dma_addr;
375
376 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
377 pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
378 * marker.
379 */
380 pre_rxd_blk->reserved_2_pNext_RxD_block =
381 (unsigned long) tmp_v_addr_next;
382 pre_rxd_blk->pNext_RxD_Blk_physical =
383 (u64) tmp_p_addr_next;
384 }
385 }
386
387 /* Allocation and initialization of Statistics block */
388 size = sizeof(StatInfo_t);
389 mac_control->stats_mem = pci_alloc_consistent
390 (nic->pdev, size, &mac_control->stats_mem_phy);
391
392 if (!mac_control->stats_mem) {
393 /* In case of failure, freeSharedMem() is called, which
394 * should free any memory that was alloced till the
395 * failure happened.
396 */
397 return -ENOMEM;
398 }
399 mac_control->stats_mem_sz = size;
400
401 tmp_v_addr = mac_control->stats_mem;
402 mac_control->StatsInfo = (StatInfo_t *) tmp_v_addr;
403 memset(tmp_v_addr, 0, size);
404
405 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
406 (unsigned long long) tmp_p_addr);
407
408 return SUCCESS;
409 }
410
411 /*
412 * Input Arguments:
413 * Device peivate variable.
414 * Return Value:
415 * NONE
416 * Description:
417 * This function is to free all memory locations allocated by
418 * the initSharedMem() function and return it to the kernel.
419 */
420 static void freeSharedMem(struct s2io_nic *nic)
421 {
422 int i, j, blk_cnt, size;
423 void *tmp_v_addr;
424 dma_addr_t tmp_p_addr;
425 mac_info_t *mac_control;
426 struct config_param *config;
427
428
429 if (!nic)
430 return;
431
432 mac_control = &nic->mac_control;
433 config = &nic->config;
434
435 if (mac_control->txd_list_mem) {
436 pci_free_consistent(nic->pdev,
437 mac_control->txd_list_mem_sz,
438 mac_control->txd_list_mem,
439 mac_control->txd_list_mem_phy);
440 }
441
442 size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
443 for (i = 0; i < config->RxRingNum; i++) {
444 blk_cnt = nic->block_count[i];
445 for (j = 0; j < blk_cnt; j++) {
446 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
447 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
448 if (tmp_v_addr == NULL)
449 break;
450 pci_free_consistent(nic->pdev, size,
451 tmp_v_addr, tmp_p_addr);
452 }
453 }
454
455 if (mac_control->stats_mem) {
456 pci_free_consistent(nic->pdev,
457 mac_control->stats_mem_sz,
458 mac_control->stats_mem,
459 mac_control->stats_mem_phy);
460 }
461 }
462
463 /*
464 * Input Arguments:
465 * device peivate variable
466 * Return Value:
467 * SUCCESS on success and '-1' on failure (endian settings incorrect).
468 * Description:
469 * The function sequentially configures every block
470 * of the H/W from their reset values.
471 */
472 static int initNic(struct s2io_nic *nic)
473 {
474 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
475 struct net_device *dev = nic->dev;
476 register u64 val64 = 0;
477 void *add;
478 u32 time;
479 int i, j;
480 mac_info_t *mac_control;
481 struct config_param *config;
482 int mdio_cnt = 0, dtx_cnt = 0;
483 unsigned long long print_var, mem_share;
484
485 mac_control = &nic->mac_control;
486 config = &nic->config;
487
488 /* Set proper endian settings and verify the same by
489 * reading the PIF Feed-back register.
490 */
491 #ifdef __BIG_ENDIAN
492 /* The device by default set to a big endian format, so
493 * a big endian driver need not set anything.
494 */
495 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
496 val64 = (SWAPPER_CTRL_PIF_R_FE |
497 SWAPPER_CTRL_PIF_R_SE |
498 SWAPPER_CTRL_PIF_W_FE |
499 SWAPPER_CTRL_PIF_W_SE |
500 SWAPPER_CTRL_TXP_FE |
501 SWAPPER_CTRL_TXP_SE |
502 SWAPPER_CTRL_TXD_R_FE |
503 SWAPPER_CTRL_TXD_W_FE |
504 SWAPPER_CTRL_TXF_R_FE |
505 SWAPPER_CTRL_RXD_R_FE |
506 SWAPPER_CTRL_RXD_W_FE |
507 SWAPPER_CTRL_RXF_W_FE |
508 SWAPPER_CTRL_XMSI_FE |
509 SWAPPER_CTRL_XMSI_SE |
510 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
511 writeq(val64, &bar0->swapper_ctrl);
512 #else
513 /* Initially we enable all bits to make it accessible by
514 * the driver, then we selectively enable only those bits
515 * that we want to set.
516 */
517 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
518 val64 = (SWAPPER_CTRL_PIF_R_FE |
519 SWAPPER_CTRL_PIF_R_SE |
520 SWAPPER_CTRL_PIF_W_FE |
521 SWAPPER_CTRL_PIF_W_SE |
522 SWAPPER_CTRL_TXP_FE |
523 SWAPPER_CTRL_TXP_SE |
524 SWAPPER_CTRL_TXD_R_FE |
525 SWAPPER_CTRL_TXD_R_SE |
526 SWAPPER_CTRL_TXD_W_FE |
527 SWAPPER_CTRL_TXD_W_SE |
528 SWAPPER_CTRL_TXF_R_FE |
529 SWAPPER_CTRL_RXD_R_FE |
530 SWAPPER_CTRL_RXD_R_SE |
531 SWAPPER_CTRL_RXD_W_FE |
532 SWAPPER_CTRL_RXD_W_SE |
533 SWAPPER_CTRL_RXF_W_FE |
534 SWAPPER_CTRL_XMSI_FE |
535 SWAPPER_CTRL_XMSI_SE |
536 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
537 writeq(val64, &bar0->swapper_ctrl);
538 #endif
539
540 /* Verifying if endian settings are accurate by reading
541 * a feedback register.
542 */
543 val64 = readq(&bar0->pif_rd_swapper_fb);
544 if (val64 != 0x0123456789ABCDEFULL) {
545 /* Endian settings are incorrect, calls for another dekko. */
546 print_var = (unsigned long long) val64;
547 DBG_PRINT(INIT_DBG, "%s: Endian settings are wrong",
548 dev->name);
549 DBG_PRINT(ERR_DBG, ", feedback read %llx\n", print_var);
550
551 return FAILURE;
552 }
553
554 /* Remove XGXS from reset state */
555 val64 = 0;
556 writeq(val64, &bar0->sw_reset);
557 val64 = readq(&bar0->sw_reset);
558 set_current_state(TASK_UNINTERRUPTIBLE);
559 schedule_timeout(HZ / 2);
560
561 /* Enable Receiving broadcasts */
562 val64 = readq(&bar0->mac_cfg);
563 val64 |= MAC_RMAC_BCAST_ENABLE;
564 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
565 writeq(val64, &bar0->mac_cfg);
566
567 /* Read registers in all blocks */
568 val64 = readq(&bar0->mac_int_mask);
569 val64 = readq(&bar0->mc_int_mask);
570 val64 = readq(&bar0->xgxs_int_mask);
571
572 /* Set MTU */
573 val64 = dev->mtu;
574 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
575
576 /* Configuring the XAUI Interface of Xena.
577 *****************************************
578 * To Configure the Xena's XAUI, one has to write a series
579 * of 64 bit values into two registers in a particular
580 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
581 * which will be defined in the array of configuration values
582 * (default_dtx_cfg & default_mdio_cfg) at appropriate places
583 * to switch writing from one regsiter to another. We continue
584 * writing these values until we encounter the 'END_SIGN' macro.
585 * For example, After making a series of 21 writes into
586 * dtx_control register the 'SWITCH_SIGN' appears and hence we
587 * start writing into mdio_control until we encounter END_SIGN.
588 */
589 while (1) {
590 dtx_cfg:
591 while (default_dtx_cfg[dtx_cnt] != END_SIGN) {
592 if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
593 dtx_cnt++;
594 goto mdio_cfg;
595 }
596 writeq(default_dtx_cfg[dtx_cnt],
597 &bar0->dtx_control);
598 val64 = readq(&bar0->dtx_control);
599 dtx_cnt++;
600 }
601 mdio_cfg:
602 while (default_mdio_cfg[mdio_cnt] != END_SIGN) {
603 if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
604 mdio_cnt++;
605 goto dtx_cfg;
606 }
607 writeq(default_mdio_cfg[mdio_cnt],
608 &bar0->mdio_control);
609 val64 = readq(&bar0->mdio_control);
610 mdio_cnt++;
611 }
612 if ((default_dtx_cfg[dtx_cnt] == END_SIGN) &&
613 (default_mdio_cfg[mdio_cnt] == END_SIGN)) {
614 break;
615 } else {
616 goto dtx_cfg;
617 }
618 }
619
620 /* Tx DMA Initialization */
621 val64 = 0;
622 writeq(val64, &bar0->tx_fifo_partition_0);
623 writeq(val64, &bar0->tx_fifo_partition_1);
624 writeq(val64, &bar0->tx_fifo_partition_2);
625 writeq(val64, &bar0->tx_fifo_partition_3);
626
627
628 for (i = 0, j = 0; i < config->TxFIFONum; i++) {
629 val64 |=
630 vBIT(config->TxCfg[i].FifoLen - 1, ((i * 32) + 19),
631 13) | vBIT(config->TxCfg[i].FifoPriority,
632 ((i * 32) + 5), 3);
633
634 if (i == (config->TxFIFONum - 1)) {
635 if (i % 2 == 0)
636 i++;
637 }
638
639 switch (i) {
640 case 1:
641 writeq(val64, &bar0->tx_fifo_partition_0);
642 val64 = 0;
643 break;
644 case 3:
645 writeq(val64, &bar0->tx_fifo_partition_1);
646 val64 = 0;
647 break;
648 case 5:
649 writeq(val64, &bar0->tx_fifo_partition_2);
650 val64 = 0;
651 break;
652 case 7:
653 writeq(val64, &bar0->tx_fifo_partition_3);
654 break;
655 }
656 }
657
658 /* Enable Tx FIFO partition 0. */
659 val64 = readq(&bar0->tx_fifo_partition_0);
660 val64 |= BIT(0); /* To enable the FIFO partition. */
661 writeq(val64, &bar0->tx_fifo_partition_0);
662
663 val64 = readq(&bar0->tx_fifo_partition_0);
664 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
665 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
666
667 /*
668 * Initialization of Tx_PA_CONFIG register to ignore packet
669 * integrity checking.
670 */
671 val64 = readq(&bar0->tx_pa_cfg);
672 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
673 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
674 writeq(val64, &bar0->tx_pa_cfg);
675
676 /* Rx DMA intialization. */
677 val64 = 0;
678 for (i = 0; i < config->RxRingNum; i++) {
679 val64 |=
680 vBIT(config->RxCfg[i].RingPriority, (5 + (i * 8)), 3);
681 }
682 writeq(val64, &bar0->rx_queue_priority);
683
684 /* Allocating equal share of memory to all the configured
685 * Rings.
686 */
687 val64 = 0;
688 for (i = 0; i < config->RxRingNum; i++) {
689 switch (i) {
690 case 0:
691 mem_share = (64 / config->RxRingNum +
692 64 % config->RxRingNum);
693 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
694 continue;
695 case 1:
696 mem_share = (64 / config->RxRingNum);
697 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
698 continue;
699 case 2:
700 mem_share = (64 / config->RxRingNum);
701 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
702 continue;
703 case 3:
704 mem_share = (64 / config->RxRingNum);
705 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
706 continue;
707 case 4:
708 mem_share = (64 / config->RxRingNum);
709 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
710 continue;
711 case 5:
712 mem_share = (64 / config->RxRingNum);
713 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
714 continue;
715 case 6:
716 mem_share = (64 / config->RxRingNum);
717 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
718 continue;
719 case 7:
720 mem_share = (64 / config->RxRingNum);
721 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
722 continue;
723 }
724 }
725 writeq(val64, &bar0->rx_queue_cfg);
726
727 /* Initializing the Tx round robin registers to 0.
728 * Filling Tx and Rx round robin registers as per the
729 * number of FIFOs and Rings is still TODO.
730 */
731 writeq(0, &bar0->tx_w_round_robin_0);
732 writeq(0, &bar0->tx_w_round_robin_1);
733 writeq(0, &bar0->tx_w_round_robin_2);
734 writeq(0, &bar0->tx_w_round_robin_3);
735 writeq(0, &bar0->tx_w_round_robin_4);
736
737 /* Disable Rx steering. Hard coding all packets be steered to
738 * Queue 0 for now.
739 * TODO*/
740 if (rx_prio) {
741 u64 def = 0x8000000000000000ULL, tmp;
742 for (i = 0; i < MAX_RX_RINGS; i++) {
743 tmp = (u64) (def >> (i % config->RxRingNum));
744 val64 |= (u64) (tmp >> (i * 8));
745 }
746 writeq(val64, &bar0->rts_qos_steering);
747 } else {
748 val64 = 0x8080808080808080ULL;
749 writeq(val64, &bar0->rts_qos_steering);
750 }
751
752 /* UDP Fix */
753 val64 = 0;
754 for (i = 1; i < 8; i++)
755 writeq(val64, &bar0->rts_frm_len_n[i]);
756
757 /* Set rts_frm_len register for fifo 0 */
758 writeq(MAC_RTS_FRM_LEN_SET(dev->mtu + 22),
759 &bar0->rts_frm_len_n[0]);
760
761 /* Enable statistics */
762 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
763 val64 = SET_UPDT_PERIOD(8) | STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
764 writeq(val64, &bar0->stat_cfg);
765
766 /* Initializing the sampling rate for the device to calculate the
767 * bandwidth utilization.
768 */
769 val64 = MAC_TX_LINK_UTIL_VAL(0x5) | MAC_RX_LINK_UTIL_VAL(0x5);
770 writeq(val64, &bar0->mac_link_util);
771
772
773 /* Initializing the Transmit and Receive Traffic Interrupt
774 * Scheme.
775 */
776 /* TTI Initialization */
777 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0xFFF) |
778 TTI_DATA1_MEM_TX_URNG_A(0xA) | TTI_DATA1_MEM_TX_URNG_B(0x10) |
779 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
780 writeq(val64, &bar0->tti_data1_mem);
781
782 val64 =
783 TTI_DATA2_MEM_TX_UFC_A(0x10) | TTI_DATA2_MEM_TX_UFC_B(0x20) |
784 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
785 writeq(val64, &bar0->tti_data2_mem);
786
787 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
788 writeq(val64, &bar0->tti_command_mem);
789
790 /* Once the operation completes, the Strobe bit of the command
791 * register will be reset. We poll for this particular condition
792 * We wait for a maximum of 500ms for the operation to complete,
793 * if it's not complete by then we return error.
794 */
795 time = 0;
796 while (TRUE) {
797 val64 = readq(&bar0->tti_command_mem);
798 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
799 break;
800 }
801 if (time > 10) {
802 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
803 dev->name);
804 return -1;
805 }
806 set_current_state(TASK_UNINTERRUPTIBLE);
807 schedule_timeout(HZ / 20);
808 time++;
809 }
810
811 /* RTI Initialization */
812 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) |
813 RTI_DATA1_MEM_RX_URNG_A(0xA) | RTI_DATA1_MEM_RX_URNG_B(0x10) |
814 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
815 writeq(val64, &bar0->rti_data1_mem);
816
817 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | RTI_DATA2_MEM_RX_UFC_B(0x2) |
818 RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
819 writeq(val64, &bar0->rti_data2_mem);
820
821 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD;
822 writeq(val64, &bar0->rti_command_mem);
823
824 /* Once the operation completes, the Strobe bit of the command
825 * register will be reset. We poll for this particular condition
826 * We wait for a maximum of 500ms for the operation to complete,
827 * if it's not complete by then we return error.
828 */
829 time = 0;
830 while (TRUE) {
831 val64 = readq(&bar0->rti_command_mem);
832 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
833 break;
834 }
835 if (time > 10) {
836 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
837 dev->name);
838 return -1;
839 }
840 time++;
841 set_current_state(TASK_UNINTERRUPTIBLE);
842 schedule_timeout(HZ / 20);
843 }
844
845 /* Initializing proper values as Pause threshold into all
846 * the 8 Queues on Rx side.
847 */
848 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
849 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
850
851 /* Disable RMAC PAD STRIPPING */
852 add = (void *) &bar0->mac_cfg;
853 val64 = readq(&bar0->mac_cfg);
854 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
855 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
856 writel((u32) (val64), add);
857 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
858 writel((u32) (val64 >> 32), (add + 4));
859 val64 = readq(&bar0->mac_cfg);
860
861 return SUCCESS;
862 }
863
864 /*
865 * Input Arguments:
866 * device private variable,
867 * A mask indicating which Intr block must be modified and,
868 * A flag indicating whether to enable or disable the Intrs.
869 * Return Value:
870 * NONE.
871 * Description:
872 * This function will either disable or enable the interrupts
873 * depending on the flag argument. The mask argument can be used to
874 * enable/disable any Intr block.
875 */
876 static void en_dis_able_NicIntrs(struct s2io_nic *nic, u16 mask, int flag)
877 {
878 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
879 register u64 val64 = 0, temp64 = 0;
880
881 /* Top level interrupt classification */
882 /* PIC Interrupts */
883 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
884 /* Enable PIC Intrs in the general intr mask register */
885 val64 = TXPIC_INT_M | PIC_RX_INT_M;
886 if (flag == ENABLE_INTRS) {
887 temp64 = readq(&bar0->general_int_mask);
888 temp64 &= ~((u64) val64);
889 writeq(temp64, &bar0->general_int_mask);
890 /* Disabled all PCIX, Flash, MDIO, IIC and GPIO
891 * interrupts for now.
892 * TODO */
893 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
894 /* No MSI Support is available presently, so TTI and
895 * RTI interrupts are also disabled.
896 */
897 } else if (flag == DISABLE_INTRS) {
898 /* Disable PIC Intrs in the general intr mask register
899 */
900 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
901 temp64 = readq(&bar0->general_int_mask);
902 val64 |= temp64;
903 writeq(val64, &bar0->general_int_mask);
904 }
905 }
906
907 /* DMA Interrupts */
908 /* Enabling/Disabling Tx DMA interrupts */
909 if (mask & TX_DMA_INTR) {
910 /* Enable TxDMA Intrs in the general intr mask register */
911 val64 = TXDMA_INT_M;
912 if (flag == ENABLE_INTRS) {
913 temp64 = readq(&bar0->general_int_mask);
914 temp64 &= ~((u64) val64);
915 writeq(temp64, &bar0->general_int_mask);
916 /* Disable all interrupts other than PFC interrupt in
917 * DMA level.
918 */
919 val64 = DISABLE_ALL_INTRS & (~TXDMA_PFC_INT_M);
920 writeq(val64, &bar0->txdma_int_mask);
921 /* Enable only the MISC error 1 interrupt in PFC block
922 */
923 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
924 writeq(val64, &bar0->pfc_err_mask);
925 } else if (flag == DISABLE_INTRS) {
926 /* Disable TxDMA Intrs in the general intr mask
927 * register */
928 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
929 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
930 temp64 = readq(&bar0->general_int_mask);
931 val64 |= temp64;
932 writeq(val64, &bar0->general_int_mask);
933 }
934 }
935
936 /* Enabling/Disabling Rx DMA interrupts */
937 if (mask & RX_DMA_INTR) {
938 /* Enable RxDMA Intrs in the general intr mask register */
939 val64 = RXDMA_INT_M;
940 if (flag == ENABLE_INTRS) {
941 temp64 = readq(&bar0->general_int_mask);
942 temp64 &= ~((u64) val64);
943 writeq(temp64, &bar0->general_int_mask);
944 /* All RxDMA block interrupts are disabled for now
945 * TODO */
946 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
947 } else if (flag == DISABLE_INTRS) {
948 /* Disable RxDMA Intrs in the general intr mask
949 * register */
950 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
951 temp64 = readq(&bar0->general_int_mask);
952 val64 |= temp64;
953 writeq(val64, &bar0->general_int_mask);
954 }
955 }
956
957 /* MAC Interrupts */
958 /* Enabling/Disabling MAC interrupts */
959 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
960 val64 = TXMAC_INT_M | RXMAC_INT_M;
961 if (flag == ENABLE_INTRS) {
962 temp64 = readq(&bar0->general_int_mask);
963 temp64 &= ~((u64) val64);
964 writeq(temp64, &bar0->general_int_mask);
965 /* All MAC block error interrupts are disabled for now
966 * except the link status change interrupt.
967 * TODO*/
968 val64 = MAC_INT_STATUS_RMAC_INT;
969 temp64 = readq(&bar0->mac_int_mask);
970 temp64 &= ~((u64) val64);
971 writeq(temp64, &bar0->mac_int_mask);
972
973 val64 = readq(&bar0->mac_rmac_err_mask);
974 val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
975 writeq(val64, &bar0->mac_rmac_err_mask);
976 } else if (flag == DISABLE_INTRS) {
977 /* Disable MAC Intrs in the general intr mask register
978 */
979 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
980 writeq(DISABLE_ALL_INTRS,
981 &bar0->mac_rmac_err_mask);
982
983 temp64 = readq(&bar0->general_int_mask);
984 val64 |= temp64;
985 writeq(val64, &bar0->general_int_mask);
986 }
987 }
988
989 /* XGXS Interrupts */
990 if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
991 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
992 if (flag == ENABLE_INTRS) {
993 temp64 = readq(&bar0->general_int_mask);
994 temp64 &= ~((u64) val64);
995 writeq(temp64, &bar0->general_int_mask);
996 /* All XGXS block error interrupts are disabled for now
997 * TODO */
998 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
999 } else if (flag == DISABLE_INTRS) {
1000 /* Disable MC Intrs in the general intr mask register
1001 */
1002 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1003 temp64 = readq(&bar0->general_int_mask);
1004 val64 |= temp64;
1005 writeq(val64, &bar0->general_int_mask);
1006 }
1007 }
1008
1009 /* Memory Controller(MC) interrupts */
1010 if (mask & MC_INTR) {
1011 val64 = MC_INT_M;
1012 if (flag == ENABLE_INTRS) {
1013 temp64 = readq(&bar0->general_int_mask);
1014 temp64 &= ~((u64) val64);
1015 writeq(temp64, &bar0->general_int_mask);
1016 /* All MC block error interrupts are disabled for now
1017 * TODO */
1018 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1019 } else if (flag == DISABLE_INTRS) {
1020 /* Disable MC Intrs in the general intr mask register
1021 */
1022 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1023 temp64 = readq(&bar0->general_int_mask);
1024 val64 |= temp64;
1025 writeq(val64, &bar0->general_int_mask);
1026 }
1027 }
1028
1029
1030 /* Tx traffic interrupts */
1031 if (mask & TX_TRAFFIC_INTR) {
1032 val64 = TXTRAFFIC_INT_M;
1033 if (flag == ENABLE_INTRS) {
1034 temp64 = readq(&bar0->general_int_mask);
1035 temp64 &= ~((u64) val64);
1036 writeq(temp64, &bar0->general_int_mask);
1037 /* Enable all the Tx side interrupts */
1038 writeq(0x0, &bar0->tx_traffic_mask); /* '0' Enables
1039 * all 64 TX
1040 * interrupt
1041 * levels.
1042 */
1043 } else if (flag == DISABLE_INTRS) {
1044 /* Disable Tx Traffic Intrs in the general intr mask
1045 * register.
1046 */
1047 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1048 temp64 = readq(&bar0->general_int_mask);
1049 val64 |= temp64;
1050 writeq(val64, &bar0->general_int_mask);
1051 }
1052 }
1053
1054 /* Rx traffic interrupts */
1055 if (mask & RX_TRAFFIC_INTR) {
1056 val64 = RXTRAFFIC_INT_M;
1057 if (flag == ENABLE_INTRS) {
1058 temp64 = readq(&bar0->general_int_mask);
1059 temp64 &= ~((u64) val64);
1060 writeq(temp64, &bar0->general_int_mask);
1061 writeq(0x0, &bar0->rx_traffic_mask); /* '0' Enables
1062 * all 8 RX
1063 * interrupt
1064 * levels.
1065 */
1066 } else if (flag == DISABLE_INTRS) {
1067 /* Disable Rx Traffic Intrs in the general intr mask
1068 * register.
1069 */
1070 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1071 temp64 = readq(&bar0->general_int_mask);
1072 val64 |= temp64;
1073 writeq(val64, &bar0->general_int_mask);
1074 }
1075 }
1076 }
1077
1078 /*
1079 * Input Arguments:
1080 * val64 - Value read from adapter status register.
1081 * flag - indicates if the adapter enable bit was ever written once before.
1082 * Return Value:
1083 * void.
1084 * Description:
1085 * Returns whether the H/W is ready to go or not. Depending on whether
1086 * adapter enable bit was written or not the comparison differs and the
1087 * calling function passes the input argument flag to indicate this.
1088 */
1089 static int verify_xena_quiescence(u64 val64, int flag)
1090 {
1091 int ret = 0;
1092 u64 tmp64 = ~((u64) val64);
1093
1094 if (!
1095 (tmp64 &
1096 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1097 ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1098 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1099 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1100 ADAPTER_STATUS_P_PLL_LOCK))) {
1101 if (flag == FALSE) {
1102 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1103 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1104 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1105
1106 ret = 1;
1107
1108 }
1109 } else {
1110 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1111 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1112 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1113 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1114 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1115
1116 ret = 1;
1117
1118 }
1119 }
1120 }
1121
1122 return ret;
1123 }
1124
1125 /*
1126 * New procedure to clear mac address reading problems on Alpha platforms
1127 *
1128 */
1129 void FixMacAddress(nic_t * sp)
1130 {
1131 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
1132 u64 val64;
1133 int i = 0;
1134
1135 while (fix_mac[i] != END_SIGN) {
1136 writeq(fix_mac[i++], &bar0->gpio_control);
1137 val64 = readq(&bar0->gpio_control);
1138 }
1139 }
1140
1141 /*
1142 * Input Arguments:
1143 * device private variable.
1144 * Return Value:
1145 * SUCCESS on success and -1 on failure.
1146 * Description:
1147 * This function actually turns the device on. Before this
1148 * function is called, all Registers are configured from their reset states
1149 * and shared memory is allocated but the NIC is still quiescent. On
1150 * calling this function, the device interrupts are cleared and the NIC is
1151 * literally switched on by writing into the adapter control register.
1152 */
1153 static int startNic(struct s2io_nic *nic)
1154 {
1155 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1156 struct net_device *dev = nic->dev;
1157 register u64 val64 = 0;
1158 u16 interruptible, i;
1159 u16 subid;
1160 mac_info_t *mac_control;
1161 struct config_param *config;
1162
1163 mac_control = &nic->mac_control;
1164 config = &nic->config;
1165
1166 /* PRC Initialization and configuration */
1167 for (i = 0; i < config->RxRingNum; i++) {
1168 writeq((u64) nic->rx_blocks[i][0].block_dma_addr,
1169 &bar0->prc_rxd0_n[i]);
1170
1171 val64 = readq(&bar0->prc_ctrl_n[i]);
1172 val64 |= PRC_CTRL_RC_ENABLED;
1173 writeq(val64, &bar0->prc_ctrl_n[i]);
1174 }
1175
1176 /* Enabling MC-RLDRAM. After enabling the device, we timeout
1177 * for around 100ms, which is approximately the time required
1178 * for the device to be ready for operation.
1179 */
1180 val64 = readq(&bar0->mc_rldram_mrs);
1181 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1182 writeq(val64, &bar0->mc_rldram_mrs);
1183 val64 = readq(&bar0->mc_rldram_mrs);
1184
1185 set_current_state(TASK_UNINTERRUPTIBLE);
1186 schedule_timeout(HZ / 10); /* Delay by around 100 ms. */
1187
1188 /* Enabling ECC Protection. */
1189 val64 = readq(&bar0->adapter_control);
1190 val64 &= ~ADAPTER_ECC_EN;
1191 writeq(val64, &bar0->adapter_control);
1192
1193 /* Clearing any possible Link state change interrupts that
1194 * could have popped up just before Enabling the card.
1195 */
1196 val64 = readq(&bar0->mac_rmac_err_reg);
1197 if (val64)
1198 writeq(val64, &bar0->mac_rmac_err_reg);
1199
1200 /* Verify if the device is ready to be enabled, if so enable
1201 * it.
1202 */
1203 val64 = readq(&bar0->adapter_status);
1204 if (!verify_xena_quiescence(val64, nic->device_enabled_once)) {
1205 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1206 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1207 (unsigned long long) val64);
1208 return FAILURE;
1209 }
1210
1211 /* Enable select interrupts */
1212 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
1213 RX_MAC_INTR;
1214 en_dis_able_NicIntrs(nic, interruptible, ENABLE_INTRS);
1215
1216 /* With some switches, link might be already up at this point.
1217 * Because of this weird behavior, when we enable laser,
1218 * we may not get link. We need to handle this. We cannot
1219 * figure out which switch is misbehaving. So we are forced to
1220 * make a global change.
1221 */
1222
1223 /* Enabling Laser. */
1224 val64 = readq(&bar0->adapter_control);
1225 val64 |= ADAPTER_EOI_TX_ON;
1226 writeq(val64, &bar0->adapter_control);
1227
1228 /* SXE-002: Initialize link and activity LED */
1229 subid = nic->pdev->subsystem_device;
1230 if ((subid & 0xFF) >= 0x07) {
1231 val64 = readq(&bar0->gpio_control);
1232 val64 |= 0x0000800000000000ULL;
1233 writeq(val64, &bar0->gpio_control);
1234 val64 = 0x0411040400000000ULL;
1235 writeq(val64, (void *) ((u8 *) bar0 + 0x2700));
1236 }
1237
1238 /*
1239 * Here we are performing soft reset on XGXS to
1240 * force link down. Since link is already up, we will get
1241 * link state change interrupt after this reset
1242 */
1243 writeq(0x8007051500000000ULL, &bar0->dtx_control);
1244 val64 = readq(&bar0->dtx_control);
1245 writeq(0x80070515000000E0ULL, &bar0->dtx_control);
1246 val64 = readq(&bar0->dtx_control);
1247 writeq(0x80070515001F00E4ULL, &bar0->dtx_control);
1248 val64 = readq(&bar0->dtx_control);
1249
1250 return SUCCESS;
1251 }
1252
1253 /*
1254 * Input Arguments:
1255 * nic - device private variable.
1256 * Return Value:
1257 * void.
1258 * Description:
1259 * Free all queued Tx buffers.
1260 */
1261 void freeTxBuffers(struct s2io_nic *nic)
1262 {
1263 struct net_device *dev = nic->dev;
1264 struct sk_buff *skb;
1265 TxD_t *txdp;
1266 int i, j;
1267 #if DEBUG_ON
1268 int cnt = 0;
1269 #endif
1270 mac_info_t *mac_control;
1271 struct config_param *config;
1272
1273 mac_control = &nic->mac_control;
1274 config = &nic->config;
1275
1276 for (i = 0; i < config->TxFIFONum; i++) {
1277 for (j = 0; j < config->TxCfg[i].FifoLen - 1; j++) {
1278 txdp = mac_control->txdl_start[i] +
1279 (config->MaxTxDs * j);
1280
1281 if (!(txdp->Control_1 & TXD_LIST_OWN_XENA)) {
1282 /* If owned by host, ignore */
1283 continue;
1284 }
1285 skb =
1286 (struct sk_buff *) ((unsigned long) txdp->
1287 Host_Control);
1288 if (skb == NULL) {
1289 DBG_PRINT(ERR_DBG, "%s: NULL skb ",
1290 dev->name);
1291 DBG_PRINT(ERR_DBG, "in Tx Int\n");
1292 return;
1293 }
1294 #if DEBUG_ON
1295 cnt++;
1296 #endif
1297 dev_kfree_skb(skb);
1298 memset(txdp, 0, sizeof(TxD_t));
1299 }
1300 #if DEBUG_ON
1301 DBG_PRINT(INTR_DBG,
1302 "%s:forcibly freeing %d skbs on FIFO%d\n",
1303 dev->name, cnt, i);
1304 #endif
1305 }
1306 }
1307
1308 /*
1309 * Input Arguments:
1310 * nic - device private variable.
1311 * Return Value:
1312 * void.
1313 * Description:
1314 * This function does exactly the opposite of what the startNic()
1315 * function does. This function is called to stop
1316 * the device.
1317 */
1318 static void stopNic(struct s2io_nic *nic)
1319 {
1320 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1321 register u64 val64 = 0;
1322 u16 interruptible, i;
1323 mac_info_t *mac_control;
1324 struct config_param *config;
1325
1326 mac_control = &nic->mac_control;
1327 config = &nic->config;
1328
1329 /* Disable all interrupts */
1330 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
1331 RX_MAC_INTR;
1332 en_dis_able_NicIntrs(nic, interruptible, DISABLE_INTRS);
1333
1334 /* Disable PRCs */
1335 for (i = 0; i < config->RxRingNum; i++) {
1336 val64 = readq(&bar0->prc_ctrl_n[i]);
1337 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
1338 writeq(val64, &bar0->prc_ctrl_n[i]);
1339 }
1340 }
1341
1342 /*
1343 * Input Arguments:
1344 * device private variable
1345 * Return Value:
1346 * SUCCESS on success or an appropriate -ve value on failure.
1347 * Description:
1348 * The function allocates Rx side skbs and puts the physical
1349 * address of these buffers into the RxD buffer pointers, so that the NIC
1350 * can DMA the received frame into these locations.
1351 * The NIC supports 3 receive modes, viz
1352 * 1. single buffer,
1353 * 2. three buffer and
1354 * 3. Five buffer modes.
1355 * Each mode defines how many fragments the received frame will be split
1356 * up into by the NIC. The frame is split into L3 header, L4 Header,
1357 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
1358 * is split into 3 fragments. As of now only single buffer mode is supported.
1359 */
1360 int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1361 {
1362 struct net_device *dev = nic->dev;
1363 struct sk_buff *skb;
1364 RxD_t *rxdp;
1365 int off, off1, size, block_no, block_no1;
1366 int offset, offset1;
1367 u32 alloc_tab = 0;
1368 u32 alloc_cnt = nic->pkt_cnt[ring_no] -
1369 atomic_read(&nic->rx_bufs_left[ring_no]);
1370 mac_info_t *mac_control;
1371 struct config_param *config;
1372
1373 mac_control = &nic->mac_control;
1374 config = &nic->config;
1375
1376 if (frame_len[ring_no]) {
1377 if (frame_len[ring_no] > dev->mtu)
1378 dev->mtu = frame_len[ring_no];
1379 size = frame_len[ring_no] + HEADER_ETHERNET_II_802_3_SIZE +
1380 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
1381 } else {
1382 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
1383 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
1384 }
1385
1386 while (alloc_tab < alloc_cnt) {
1387 block_no = mac_control->rx_curr_put_info[ring_no].
1388 block_index;
1389 block_no1 = mac_control->rx_curr_get_info[ring_no].
1390 block_index;
1391 off = mac_control->rx_curr_put_info[ring_no].offset;
1392 off1 = mac_control->rx_curr_get_info[ring_no].offset;
1393 offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
1394 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
1395
1396 rxdp = nic->rx_blocks[ring_no][block_no].
1397 block_virt_addr + off;
1398 if ((offset == offset1) && (rxdp->Host_Control)) {
1399 DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
1400 DBG_PRINT(INTR_DBG, " info equated\n");
1401 goto end;
1402 }
1403
1404 if (rxdp->Control_1 == END_OF_BLOCK) {
1405 mac_control->rx_curr_put_info[ring_no].
1406 block_index++;
1407 mac_control->rx_curr_put_info[ring_no].
1408 block_index %= nic->block_count[ring_no];
1409 block_no = mac_control->rx_curr_put_info
1410 [ring_no].block_index;
1411 off++;
1412 off %= (MAX_RXDS_PER_BLOCK + 1);
1413 mac_control->rx_curr_put_info[ring_no].offset =
1414 off;
1415 /*rxdp = nic->rx_blocks[ring_no][block_no].
1416 block_virt_addr + off; */
1417 rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
1418 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
1419 dev->name, rxdp);
1420 }
1421
1422 if (rxdp->Control_1 & RXD_OWN_XENA) {
1423 mac_control->rx_curr_put_info[ring_no].
1424 offset = off;
1425 goto end;
1426 }
1427
1428 skb = dev_alloc_skb(size + NET_IP_ALIGN);
1429 if (!skb) {
1430 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
1431 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
1432 return -ENOMEM;
1433 }
1434 skb_reserve(skb, NET_IP_ALIGN);
1435 memset(rxdp, 0, sizeof(RxD_t));
1436 rxdp->Buffer0_ptr = pci_map_single
1437 (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1438 rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
1439 rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
1440 rxdp->Host_Control = (unsigned long) (skb);
1441 rxdp->Control_1 |= RXD_OWN_XENA;
1442 off++;
1443 off %= (MAX_RXDS_PER_BLOCK + 1);
1444 mac_control->rx_curr_put_info[ring_no].offset = off;
1445 atomic_inc(&nic->rx_bufs_left[ring_no]);
1446 alloc_tab++;
1447 }
1448
1449 end:
1450 return SUCCESS;
1451 }
1452
1453 /*
1454 * Input Arguments:
1455 * device private variable.
1456 * Return Value:
1457 * NONE.
1458 * Description:
1459 * This function will free all Rx buffers allocated by host.
1460 */
1461 static void freeRxBuffers(struct s2io_nic *sp)
1462 {
1463 struct net_device *dev = sp->dev;
1464 int i, j, blk = 0, off, buf_cnt = 0;
1465 RxD_t *rxdp;
1466 struct sk_buff *skb;
1467 mac_info_t *mac_control;
1468 struct config_param *config;
1469
1470 mac_control = &sp->mac_control;
1471 config = &sp->config;
1472
1473 for (i = 0; i < config->RxRingNum; i++) {
1474 for (j = 0, blk = 0; j < config->RxCfg[i].NumRxd; j++) {
1475 off = j % (MAX_RXDS_PER_BLOCK + 1);
1476 rxdp = sp->rx_blocks[i][blk].block_virt_addr + off;
1477
1478 if (rxdp->Control_1 == END_OF_BLOCK) {
1479 rxdp =
1480 (RxD_t *) ((unsigned long) rxdp->
1481 Control_2);
1482 j++;
1483 blk++;
1484 }
1485
1486 skb =
1487 (struct sk_buff *) ((unsigned long) rxdp->
1488 Host_Control);
1489 if (skb) {
1490 pci_unmap_single(sp->pdev, (dma_addr_t)
1491 rxdp->Buffer0_ptr,
1492 dev->mtu +
1493 HEADER_ETHERNET_II_802_3_SIZE
1494 + HEADER_802_2_SIZE +
1495 HEADER_SNAP_SIZE,
1496 PCI_DMA_FROMDEVICE);
1497 dev_kfree_skb(skb);
1498 atomic_dec(&sp->rx_bufs_left[i]);
1499 buf_cnt++;
1500 }
1501 memset(rxdp, 0, sizeof(RxD_t));
1502 }
1503 mac_control->rx_curr_put_info[i].block_index = 0;
1504 mac_control->rx_curr_get_info[i].block_index = 0;
1505 mac_control->rx_curr_put_info[i].offset = 0;
1506 mac_control->rx_curr_get_info[i].offset = 0;
1507 atomic_set(&sp->rx_bufs_left[i], 0);
1508 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
1509 dev->name, buf_cnt, i);
1510 }
1511 }
1512
1513 /*
1514 * Input Argument:
1515 * dev - pointer to the device structure.
1516 * budget - The number of packets that were budgeted to be processed during
1517 * one pass through the 'Poll" function.
1518 * Return value:
1519 * 0 on success and 1 if there are No Rx packets to be processed.
1520 * Description:
1521 * Comes into picture only if NAPI support has been incorporated. It does
1522 * the same thing that rxIntrHandler does, but not in a interrupt context
1523 * also It will process only a given number of packets.
1524 */
1525 #ifdef CONFIG_S2IO_NAPI
1526 static int s2io_poll(struct net_device *dev, int *budget)
1527 {
1528 nic_t *nic = dev->priv;
1529 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1530 int pkts_to_process = *budget, pkt_cnt = 0;
1531 register u64 val64 = 0;
1532 rx_curr_get_info_t offset_info;
1533 int i, block_no;
1534 u16 val16, cksum;
1535 struct sk_buff *skb;
1536 RxD_t *rxdp;
1537 mac_info_t *mac_control;
1538 struct config_param *config;
1539
1540 mac_control = &nic->mac_control;
1541 config = &nic->config;
1542
1543 if (pkts_to_process > dev->quota)
1544 pkts_to_process = dev->quota;
1545
1546 val64 = readq(&bar0->rx_traffic_int);
1547 writeq(val64, &bar0->rx_traffic_int);
1548
1549 for (i = 0; i < config->RxRingNum; i++) {
1550 if (--pkts_to_process < 0) {
1551 goto no_rx;
1552 }
1553 offset_info = mac_control->rx_curr_get_info[i];
1554 block_no = offset_info.block_index;
1555 rxdp = nic->rx_blocks[i][block_no].block_virt_addr +
1556 offset_info.offset;
1557 while (!(rxdp->Control_1 & RXD_OWN_XENA)) {
1558 if (rxdp->Control_1 == END_OF_BLOCK) {
1559 rxdp =
1560 (RxD_t *) ((unsigned long) rxdp->
1561 Control_2);
1562 offset_info.offset++;
1563 offset_info.offset %=
1564 (MAX_RXDS_PER_BLOCK + 1);
1565 block_no++;
1566 block_no %= nic->block_count[i];
1567 mac_control->rx_curr_get_info[i].
1568 offset = offset_info.offset;
1569 mac_control->rx_curr_get_info[i].
1570 block_index = block_no;
1571 continue;
1572 }
1573 skb =
1574 (struct sk_buff *) ((unsigned long) rxdp->
1575 Host_Control);
1576 if (skb == NULL) {
1577 DBG_PRINT(ERR_DBG, "%s: The skb is ",
1578 dev->name);
1579 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
1580 return 0;
1581 }
1582 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
1583 val16 = (u16) (val64 >> 48);
1584 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
1585 pci_unmap_single(nic->pdev, (dma_addr_t)
1586 rxdp->Buffer0_ptr,
1587 dev->mtu +
1588 HEADER_ETHERNET_II_802_3_SIZE +
1589 HEADER_802_2_SIZE +
1590 HEADER_SNAP_SIZE,
1591 PCI_DMA_FROMDEVICE);
1592 rxOsmHandler(nic, val16, rxdp, i);
1593 pkt_cnt++;
1594 offset_info.offset++;
1595 offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
1596 rxdp =
1597 nic->rx_blocks[i][block_no].block_virt_addr +
1598 offset_info.offset;
1599 mac_control->rx_curr_get_info[i].offset =
1600 offset_info.offset;
1601 }
1602 }
1603 if (!pkt_cnt)
1604 pkt_cnt = 1;
1605
1606 for (i = 0; i < config->RxRingNum; i++)
1607 fill_rx_buffers(nic, i);
1608
1609 dev->quota -= pkt_cnt;
1610 *budget -= pkt_cnt;
1611 netif_rx_complete(dev);
1612
1613 /* Re enable the Rx interrupts. */
1614 en_dis_able_NicIntrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
1615 return 0;
1616
1617 no_rx:
1618 for (i = 0; i < config->RxRingNum; i++)
1619 fill_rx_buffers(nic, i);
1620 dev->quota -= pkt_cnt;
1621 *budget -= pkt_cnt;
1622 return 1;
1623 }
1624 #else
1625 /*
1626 * Input Arguments:
1627 * device private variable.
1628 * Return Value:
1629 * NONE.
1630 * Description:
1631 * If the interrupt is because of a received frame or if the
1632 * receive ring contains fresh as yet un-processed frames, this function is
1633 * called. It picks out the RxD at which place the last Rx processing had
1634 * stopped and sends the skb to the OSM's Rx handler and then increments
1635 * the offset.
1636 */
1637 static void rxIntrHandler(struct s2io_nic *nic)
1638 {
1639 struct net_device *dev = (struct net_device *) nic->dev;
1640 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1641 rx_curr_get_info_t offset_info;
1642 RxD_t *rxdp;
1643 struct sk_buff *skb;
1644 u16 val16, cksum;
1645 register u64 val64 = 0;
1646 int i, block_no;
1647 mac_info_t *mac_control;
1648 struct config_param *config;
1649
1650 mac_control = &nic->mac_control;
1651 config = &nic->config;
1652
1653 #if DEBUG_ON
1654 nic->rxint_cnt++;
1655 #endif
1656
1657 /* rx_traffic_int reg is an R1 register, hence we read and write back
1658 * the samevalue in the register to clear it.
1659 */
1660 val64 = readq(&bar0->rx_traffic_int);
1661 writeq(val64, &bar0->rx_traffic_int);
1662
1663 for (i = 0; i < config->RxRingNum; i++) {
1664 offset_info = mac_control->rx_curr_get_info[i];
1665 block_no = offset_info.block_index;
1666 rxdp = nic->rx_blocks[i][block_no].block_virt_addr +
1667 offset_info.offset;
1668 while (!(rxdp->Control_1 & RXD_OWN_XENA)) {
1669 if (rxdp->Control_1 == END_OF_BLOCK) {
1670 rxdp = (RxD_t *) ((unsigned long)
1671 rxdp->Control_2);
1672 offset_info.offset++;
1673 offset_info.offset %=
1674 (MAX_RXDS_PER_BLOCK + 1);
1675 block_no++;
1676 block_no %= nic->block_count[i];
1677 mac_control->rx_curr_get_info[i].
1678 offset = offset_info.offset;
1679 mac_control->rx_curr_get_info[i].
1680 block_index = block_no;
1681 continue;
1682 }
1683 skb = (struct sk_buff *) ((unsigned long)
1684 rxdp->Host_Control);
1685 if (skb == NULL) {
1686 DBG_PRINT(ERR_DBG, "%s: The skb is ",
1687 dev->name);
1688 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
1689 return;
1690 }
1691 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
1692 val16 = (u16) (val64 >> 48);
1693 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
1694 pci_unmap_single(nic->pdev, (dma_addr_t)
1695 rxdp->Buffer0_ptr,
1696 dev->mtu +
1697 HEADER_ETHERNET_II_802_3_SIZE +
1698 HEADER_802_2_SIZE +
1699 HEADER_SNAP_SIZE,
1700 PCI_DMA_FROMDEVICE);
1701 rxOsmHandler(nic, val16, rxdp, i);
1702 offset_info.offset++;
1703 offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
1704 rxdp =
1705 nic->rx_blocks[i][block_no].block_virt_addr +
1706 offset_info.offset;
1707 mac_control->rx_curr_get_info[i].offset =
1708 offset_info.offset;
1709 }
1710 }
1711 }
1712 #endif
1713
1714 /*
1715 * Input Arguments:
1716 * device private variable
1717 * Return Value:
1718 * NONE
1719 * Description:
1720 * If an interrupt was raised to indicate DMA complete of the
1721 * Tx packet, this function is called. It identifies the last TxD whose buffer
1722 * was freed and frees all skbs whose data have already DMA'ed into the NICs
1723 * internal memory.
1724 */
1725 static void txIntrHandler(struct s2io_nic *nic)
1726 {
1727 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1728 struct net_device *dev = (struct net_device *) nic->dev;
1729 tx_curr_get_info_t offset_info, offset_info1;
1730 struct sk_buff *skb;
1731 TxD_t *txdlp;
1732 register u64 val64 = 0;
1733 int i;
1734 u16 j, frg_cnt;
1735 mac_info_t *mac_control;
1736 struct config_param *config;
1737 #if DEBUG_ON
1738 int cnt = 0;
1739 nic->txint_cnt++;
1740 #endif
1741
1742 mac_control = &nic->mac_control;
1743 config = &nic->config;
1744
1745 /* tx_traffic_int reg is an R1 register, hence we read and write
1746 * back the samevalue in the register to clear it.
1747 */
1748 val64 = readq(&bar0->tx_traffic_int);
1749 writeq(val64, &bar0->tx_traffic_int);
1750
1751 for (i = 0; i < config->TxFIFONum; i++) {
1752 offset_info = mac_control->tx_curr_get_info[i];
1753 offset_info1 = mac_control->tx_curr_put_info[i];
1754 txdlp = mac_control->txdl_start[i] +
1755 (config->MaxTxDs * offset_info.offset);
1756 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
1757 (offset_info.offset != offset_info1.offset) &&
1758 (txdlp->Host_Control)) {
1759 /* Check for TxD errors */
1760 if (txdlp->Control_1 & TXD_T_CODE) {
1761 unsigned long long err;
1762 err = txdlp->Control_1 & TXD_T_CODE;
1763 DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
1764 err);
1765 }
1766
1767 skb = (struct sk_buff *) ((unsigned long)
1768 txdlp->Host_Control);
1769 if (skb == NULL) {
1770 DBG_PRINT(ERR_DBG, "%s: Null skb ",
1771 dev->name);
1772 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
1773 return;
1774 }
1775 nic->tx_pkt_count++;
1776
1777 frg_cnt = skb_shinfo(skb)->nr_frags;
1778
1779 /* For unfragmented skb */
1780 pci_unmap_single(nic->pdev, (dma_addr_t)
1781 txdlp->Buffer_Pointer,
1782 skb->len - skb->data_len,
1783 PCI_DMA_TODEVICE);
1784 if (frg_cnt) {
1785 TxD_t *temp = txdlp;
1786 txdlp++;
1787 for (j = 0; j < frg_cnt; j++, txdlp++) {
1788 skb_frag_t *frag =
1789 &skb_shinfo(skb)->frags[j];
1790 pci_unmap_page(nic->pdev,
1791 (dma_addr_t)
1792 txdlp->
1793 Buffer_Pointer,
1794 frag->size,
1795 PCI_DMA_TODEVICE);
1796 }
1797 txdlp = temp;
1798 }
1799 memset(txdlp, 0,
1800 (sizeof(TxD_t) * config->MaxTxDs));
1801
1802 /* Updating the statistics block */
1803 nic->stats.tx_packets++;
1804 nic->stats.tx_bytes += skb->len;
1805 #if DEBUG_ON
1806 nic->txpkt_bytes += skb->len;
1807 cnt++;
1808 #endif
1809 dev_kfree_skb_irq(skb);
1810
1811 offset_info.offset++;
1812 offset_info.offset %= offset_info.fifo_len + 1;
1813 txdlp = mac_control->txdl_start[i] +
1814 (config->MaxTxDs * offset_info.offset);
1815 mac_control->tx_curr_get_info[i].offset =
1816 offset_info.offset;
1817 }
1818 #if DEBUG_ON
1819 DBG_PRINT(INTR_DBG, "%s: freed %d Tx Pkts\n", dev->name,
1820 cnt);
1821 #endif
1822 }
1823
1824 spin_lock(&nic->tx_lock);
1825 if (netif_queue_stopped(dev))
1826 netif_wake_queue(dev);
1827 spin_unlock(&nic->tx_lock);
1828 }
1829
1830 /*
1831 * Input Arguments:
1832 * device private variable
1833 * Return Value:
1834 * NONE
1835 * Description:
1836 * If the interrupt was neither because of Rx packet or Tx
1837 * complete, this function is called. If the interrupt was to indicate a loss
1838 * of link, the OSM link status handler is invoked for any other alarm
1839 * interrupt the block that raised the interrupt is displayed and a H/W reset
1840 * is issued.
1841 */
1842 static void alarmIntrHandler(struct s2io_nic *nic)
1843 {
1844 struct net_device *dev = (struct net_device *) nic->dev;
1845 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1846 register u64 val64 = 0, err_reg = 0;
1847
1848
1849 /* Handling link status change error Intr */
1850 err_reg = readq(&bar0->mac_rmac_err_reg);
1851 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
1852 schedule_work(&nic->set_link_task);
1853 }
1854
1855 /* Handling SERR errors by stopping device Xmit queue and forcing
1856 * a H/W reset.
1857 */
1858 val64 = readq(&bar0->serr_source);
1859 if (val64 & SERR_SOURCE_ANY) {
1860 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
1861 DBG_PRINT(ERR_DBG, "serious error!!\n");
1862 netif_stop_queue(dev);
1863 }
1864 /* Other type of interrupts are not being handled now, TODO*/
1865 }
1866
1867 /*
1868 * Input Argument:
1869 * sp - private member of the device structure, which is a pointer to the
1870 * s2io_nic structure.
1871 * Return value:
1872 * SUCCESS on success and FAILURE on failure.
1873 * Description:
1874 * Function that waits for a command to Write into RMAC ADDR DATA registers
1875 * to be completed and returns either success or error depending on whether
1876 * the command was complete or not.
1877 */
1878 int waitForCmdComplete(nic_t * sp)
1879 {
1880 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
1881 int ret = FAILURE, cnt = 0;
1882 u64 val64;
1883
1884 while (TRUE) {
1885 val64 =
1886 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
1887 | RMAC_ADDR_CMD_MEM_OFFSET(0);
1888 writeq(val64, &bar0->rmac_addr_cmd_mem);
1889 val64 = readq(&bar0->rmac_addr_cmd_mem);
1890 if (!val64) {
1891 ret = SUCCESS;
1892 break;
1893 }
1894 set_current_state(TASK_UNINTERRUPTIBLE);
1895 schedule_timeout(HZ / 20);
1896 if (cnt++ > 10)
1897 break;
1898 }
1899
1900 return ret;
1901 }
1902
1903 /*
1904 * Input Argument:
1905 * sp - private member of the device structure, which is a pointer to the
1906 * s2io_nic structure.
1907 * Return value:
1908 * void.
1909 * Description:
1910 * Function to Reset the card. This function then also restores the previously
1911 * saved PCI configuration space registers as the card reset also resets the
1912 * Configration space.
1913 */
1914 void s2io_reset(nic_t * sp)
1915 {
1916 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
1917 u64 val64;
1918 u16 subid;
1919
1920 val64 = SW_RESET_ALL;
1921 writeq(val64, &bar0->sw_reset);
1922
1923 /* At this stage, if the PCI write is indeed completed, the
1924 * card is reset and so is the PCI Config space of the device.
1925 * So a read cannot be issued at this stage on any of the
1926 * registers to ensure the write into "sw_reset" register
1927 * has gone through.
1928 * Question: Is there any system call that will explicitly force
1929 * all the write commands still pending on the bus to be pushed
1930 * through?
1931 * As of now I'am just giving a 250ms delay and hoping that the
1932 * PCI write to sw_reset register is done by this time.
1933 */
1934 set_current_state(TASK_UNINTERRUPTIBLE);
1935 schedule_timeout(HZ / 4);
1936
1937 /* Restore the PCI state saved during initializarion. */
1938 pci_restore_state(sp->pdev, sp->config_space);
1939 s2io_init_pci(sp);
1940
1941 set_current_state(TASK_UNINTERRUPTIBLE);
1942 schedule_timeout(HZ / 4);
1943
1944 /* SXE-002: Configure link and activity LED to turn it off */
1945 subid = sp->pdev->subsystem_device;
1946 if ((subid & 0xFF) >= 0x07) {
1947 val64 = readq(&bar0->gpio_control);
1948 val64 |= 0x0000800000000000ULL;
1949 writeq(val64, &bar0->gpio_control);
1950 val64 = 0x0411040400000000ULL;
1951 writeq(val64, (void *) ((u8 *) bar0 + 0x2700));
1952 }
1953
1954 sp->device_enabled_once = FALSE;
1955 }
1956
1957 /*
1958 * Input Argument:
1959 * sp - private member of the device structure, which is a pointer to the
1960 * s2io_nic structure.
1961 * Return value:
1962 * SUCCESS on success and FAILURE on failure.
1963 * Description:
1964 * Function to set the swapper control on the card correctly depending on the
1965 * 'endianness' of the system.
1966 */
1967 int s2io_set_swapper(nic_t * sp)
1968 {
1969 struct net_device *dev = sp->dev;
1970 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
1971 u64 val64;
1972
1973 /* Set proper endian settings and verify the same by reading the PIF
1974 * Feed-back register.
1975 */
1976 #ifdef __BIG_ENDIAN
1977 /* The device by default set to a big endian format, so a big endian
1978 * driver need not set anything.
1979 */
1980 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
1981 val64 = (SWAPPER_CTRL_PIF_R_FE |
1982 SWAPPER_CTRL_PIF_R_SE |
1983 SWAPPER_CTRL_PIF_W_FE |
1984 SWAPPER_CTRL_PIF_W_SE |
1985 SWAPPER_CTRL_TXP_FE |
1986 SWAPPER_CTRL_TXP_SE |
1987 SWAPPER_CTRL_TXD_R_FE |
1988 SWAPPER_CTRL_TXD_W_FE |
1989 SWAPPER_CTRL_TXF_R_FE |
1990 SWAPPER_CTRL_RXD_R_FE |
1991 SWAPPER_CTRL_RXD_W_FE |
1992 SWAPPER_CTRL_RXF_W_FE |
1993 SWAPPER_CTRL_XMSI_FE |
1994 SWAPPER_CTRL_XMSI_SE |
1995 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
1996 writeq(val64, &bar0->swapper_ctrl);
1997 #else
1998 /* Initially we enable all bits to make it accessible by the driver,
1999 * then we selectively enable only those bits that we want to set.
2000 */
2001 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
2002 val64 = (SWAPPER_CTRL_PIF_R_FE |
2003 SWAPPER_CTRL_PIF_R_SE |
2004 SWAPPER_CTRL_PIF_W_FE |
2005 SWAPPER_CTRL_PIF_W_SE |
2006 SWAPPER_CTRL_TXP_FE |
2007 SWAPPER_CTRL_TXP_SE |
2008 SWAPPER_CTRL_TXD_R_FE |
2009 SWAPPER_CTRL_TXD_R_SE |
2010 SWAPPER_CTRL_TXD_W_FE |
2011 SWAPPER_CTRL_TXD_W_SE |
2012 SWAPPER_CTRL_TXF_R_FE |
2013 SWAPPER_CTRL_RXD_R_FE |
2014 SWAPPER_CTRL_RXD_R_SE |
2015 SWAPPER_CTRL_RXD_W_FE |
2016 SWAPPER_CTRL_RXD_W_SE |
2017 SWAPPER_CTRL_RXF_W_FE |
2018 SWAPPER_CTRL_XMSI_FE |
2019 SWAPPER_CTRL_XMSI_SE |
2020 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
2021 writeq(val64, &bar0->swapper_ctrl);
2022 #endif
2023
2024 /* Verifying if endian settings are accurate by reading a feedback
2025 * register.
2026 */
2027 val64 = readq(&bar0->pif_rd_swapper_fb);
2028 if (val64 != 0x0123456789ABCDEFULL) {
2029 /* Endian settings are incorrect, calls for another dekko. */
2030 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
2031 dev->name);
2032 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
2033 (unsigned long long) val64);
2034 return FAILURE;
2035 }
2036
2037 return SUCCESS;
2038 }
2039
2040 /* ********************************************************* *
2041 * Functions defined below concern the OS part of the driver *
2042 * ********************************************************* */
2043
2044 /*
2045 * Input Argument:
2046 * dev - pointer to the device structure.
2047 * Return value:
2048 * '0' on success and an appropriate (-)ve integer as defined in errno.h
2049 * file on failure.
2050 * Description:
2051 * This function is the open entry point of the driver. It mainly calls a
2052 * function to allocate Rx buffers and inserts them into the buffer
2053 * descriptors and then enables the Rx part of the NIC.
2054 */
2055 int s2io_open(struct net_device *dev)
2056 {
2057 nic_t *sp = dev->priv;
2058 int i, ret = 0, err = 0;
2059 mac_info_t *mac_control;
2060 struct config_param *config;
2061
2062
2063 /* Make sure you have link off by default every time Nic is initialized*/
2064 netif_carrier_off(dev);
2065 sp->last_link_state = LINK_DOWN;
2066
2067 /* Initialize the H/W I/O registers */
2068 if (initNic(sp) != 0) {
2069 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
2070 dev->name);
2071 return -ENODEV;
2072 }
2073
2074 /* After proper initialization of H/W, register ISR */
2075 err =
2076 request_irq((int) sp->irq, s2io_isr, SA_SHIRQ, sp->name, dev);
2077 if (err) {
2078 s2io_reset(sp);
2079 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
2080 dev->name);
2081 return err;
2082 }
2083 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
2084 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
2085 s2io_reset(sp);
2086 return -ENODEV;
2087 }
2088
2089
2090 /* Setting its receive mode */
2091 s2io_set_multicast(dev);
2092
2093 /* Initializing the Rx buffers. For now we are considering only 1 Rx ring
2094 * and initializing buffers into 1016 RxDs or 8 Rx blocks
2095 */
2096 mac_control = &sp->mac_control;
2097 config = &sp->config;
2098
2099 for (i = 0; i < config->RxRingNum; i++) {
2100 if ((ret = fill_rx_buffers(sp, i))) {
2101 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
2102 dev->name);
2103 s2io_reset(sp);
2104 free_irq(dev->irq, dev);
2105 freeRxBuffers(sp);
2106 return -ENOMEM;
2107 }
2108 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
2109 atomic_read(&sp->rx_bufs_left[i]));
2110 }
2111
2112 /* Enable tasklet for the device */
2113 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
2114
2115 /* Enable Rx Traffic and interrupts on the NIC */
2116 if (startNic(sp)) {
2117 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
2118 tasklet_kill(&sp->task);
2119 s2io_reset(sp);
2120 free_irq(dev->irq, dev);
2121 freeRxBuffers(sp);
2122 return -ENODEV;
2123 }
2124
2125 sp->device_close_flag = FALSE; /* Device is up and running. */
2126 netif_start_queue(dev);
2127
2128 return 0;
2129 }
2130
2131 /*
2132 * Input Argument/s:
2133 * dev - device pointer.
2134 * Return value:
2135 * '0' on success and an appropriate (-)ve integer as defined in errno.h
2136 * file on failure.
2137 * Description:
2138 * This is the stop entry point of the driver. It needs to undo exactly
2139 * whatever was done by the open entry point, thus it's usually referred to
2140 * as the close function. Among other things this function mainly stops the
2141 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
2142 */
2143 int s2io_close(struct net_device *dev)
2144 {
2145 nic_t *sp = dev->priv;
2146 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2147 register u64 val64 = 0;
2148 u16 cnt = 0;
2149
2150 spin_lock(&sp->isr_lock);
2151 netif_stop_queue(dev);
2152
2153 /* disable Tx and Rx traffic on the NIC */
2154 stopNic(sp);
2155
2156 spin_unlock(&sp->isr_lock);
2157
2158 /* If the device tasklet is running, wait till its done before killing it */
2159 while (atomic_read(&(sp->tasklet_status))) {
2160 set_current_state(TASK_UNINTERRUPTIBLE);
2161 schedule_timeout(HZ / 10);
2162 }
2163 tasklet_kill(&sp->task);
2164
2165 /* Check if the device is Quiescent and then Reset the NIC */
2166 do {
2167 val64 = readq(&bar0->adapter_status);
2168 if (verify_xena_quiescence(val64, sp->device_enabled_once)) {
2169 break;
2170 }
2171
2172 set_current_state(TASK_UNINTERRUPTIBLE);
2173 schedule_timeout(HZ / 20);
2174 cnt++;
2175 if (cnt == 10) {
2176 DBG_PRINT(ERR_DBG,
2177 "s2io_close:Device not Quiescent ");
2178 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
2179 (unsigned long long) val64);
2180 break;
2181 }
2182 } while (1);
2183 s2io_reset(sp);
2184
2185 /* Free the Registered IRQ */
2186 free_irq(dev->irq, dev);
2187
2188 /* Free all Tx Buffers waiting for transmission */
2189 freeTxBuffers(sp);
2190
2191 /* Free all Rx buffers allocated by host */
2192 freeRxBuffers(sp);
2193
2194 sp->device_close_flag = TRUE; /* Device is shut down. */
2195
2196 return 0;
2197 }
2198
2199 /*
2200 * Input Argument/s:
2201 * skb - the socket buffer containing the Tx data.
2202 * dev - device pointer.
2203 * Return value:
2204 * '0' on success & 1 on failure.
2205 * NOTE: when device cant queue the pkt, just the trans_start variable will
2206 * not be upadted.
2207 * Description:
2208 * This function is the Tx entry point of the driver. S2IO NIC supports
2209 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
2210 */
2211 int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2212 {
2213 nic_t *sp = dev->priv;
2214 u16 off, txd_len, frg_cnt, frg_len, i, queue, off1, queue_len;
2215 register u64 val64;
2216 TxD_t *txdp;
2217 TxFIFO_element_t *tx_fifo;
2218 unsigned long flags;
2219 #ifdef NETIF_F_TSO
2220 int mss;
2221 #endif
2222 mac_info_t *mac_control;
2223 struct config_param *config;
2224
2225 mac_control = &sp->mac_control;
2226 config = &sp->config;
2227
2228 DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name);
2229
2230 spin_lock_irqsave(&sp->tx_lock, flags);
2231 queue = 0;
2232 /* Multi FIFO Tx is disabled for now. */
2233 if (!queue && tx_prio) {
2234 u8 x = (skb->data)[5];
2235 queue = x % config->TxFIFONum;
2236 }
2237
2238
2239 off = (u16) mac_control->tx_curr_put_info[queue].offset;
2240 off1 = (u16) mac_control->tx_curr_get_info[queue].offset;
2241 txd_len = mac_control->txdl_len;
2242 txdp = mac_control->txdl_start[queue] + (config->MaxTxDs * off);
2243
2244 queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1;
2245 /* Avoid "put" pointer going beyond "get" pointer */
2246 if (txdp->Host_Control || (((off + 1) % queue_len) == off1)) {
2247 DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
2248 netif_stop_queue(dev);
2249 dev_kfree_skb(skb);
2250 spin_unlock_irqrestore(&sp->tx_lock, flags);
2251 return 0;
2252 }
2253
2254 #ifdef NETIF_F_TSO
2255 mss = skb_shinfo(skb)->tso_size;
2256 if (mss) {
2257 txdp->Control_1 |= TXD_TCP_LSO_EN;
2258 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
2259 }
2260 #endif
2261
2262 frg_cnt = skb_shinfo(skb)->nr_frags;
2263 frg_len = skb->len - skb->data_len;
2264
2265 txdp->Host_Control = (unsigned long) skb;
2266 txdp->Buffer_Pointer = pci_map_single
2267 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
2268 if (skb->ip_summed == CHECKSUM_HW) {
2269 txdp->Control_2 |=
2270 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
2271 TXD_TX_CKO_UDP_EN);
2272 }
2273
2274 txdp->Control_2 |= config->TxIntrType;
2275
2276 txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
2277 TXD_GATHER_CODE_FIRST);
2278 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2279
2280 /* For fragmented SKB. */
2281 for (i = 0; i < frg_cnt; i++) {
2282 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2283 txdp++;
2284 txdp->Buffer_Pointer = (u64) pci_map_page
2285 (sp->pdev, frag->page, frag->page_offset,
2286 frag->size, PCI_DMA_TODEVICE);
2287 txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size);
2288 }
2289 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
2290
2291 tx_fifo = mac_control->tx_FIFO_start[queue];
2292 val64 = (mac_control->txdl_start_phy[queue] +
2293 (sizeof(TxD_t) * txd_len * off));
2294 writeq(val64, &tx_fifo->TxDL_Pointer);
2295
2296 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
2297 TX_FIFO_LAST_LIST);
2298 #ifdef NETIF_F_TSO
2299 if (mss)
2300 val64 |= TX_FIFO_SPECIAL_FUNC;
2301 #endif
2302 writeq(val64, &tx_fifo->List_Control);
2303
2304 off++;
2305 off %= mac_control->tx_curr_put_info[queue].fifo_len + 1;
2306 mac_control->tx_curr_put_info[queue].offset = off;
2307
2308 /* Avoid "put" pointer going beyond "get" pointer */
2309 if (((off + 1) % queue_len) == off1) {
2310 DBG_PRINT(TX_DBG,
2311 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
2312 off, off1);
2313 netif_stop_queue(dev);
2314 }
2315
2316 dev->trans_start = jiffies;
2317 spin_unlock_irqrestore(&sp->tx_lock, flags);
2318
2319 return 0;
2320 }
2321
2322 /*
2323 * Input Argument/s:
2324 * irq: the irq of the device.
2325 * dev_id: a void pointer to the dev structure of the NIC.
2326 * ptregs: pointer to the registers pushed on the stack.
2327 * Return value:
2328 * void.
2329 * Description:
2330 * This function is the ISR handler of the device. It identifies the reason
2331 * for the interrupt and calls the relevant service routines.
2332 * As a contongency measure, this ISR allocates the recv buffers, if their
2333 * numbers are below the panic value which is presently set to 25% of the
2334 * original number of rcv buffers allocated.
2335 */
2336
2337 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2338 {
2339 struct net_device *dev = (struct net_device *) dev_id;
2340 nic_t *sp = dev->priv;
2341 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2342 u64 reason = 0, general_mask = 0;
2343 mac_info_t *mac_control;
2344 struct config_param *config;
2345
2346 mac_control = &sp->mac_control;
2347 config = &sp->config;
2348
2349 spin_lock(&sp->isr_lock);
2350
2351 /* Identify the cause for interrupt and call the appropriate
2352 * interrupt handler. Causes for the interrupt could be;
2353 * 1. Rx of packet.
2354 * 2. Tx complete.
2355 * 3. Link down.
2356 * 4. Error in any functional blocks of the NIC.
2357 */
2358 reason = readq(&bar0->general_int_status);
2359
2360 if (!reason) {
2361 /* The interrupt was not raised by Xena. */
2362 spin_unlock(&sp->isr_lock);
2363 return IRQ_NONE;
2364 }
2365 /* Mask the interrupts on the NIC */
2366 general_mask = readq(&bar0->general_int_mask);
2367 writeq(0xFFFFFFFFFFFFFFFFULL, &bar0->general_int_mask);
2368
2369 #if DEBUG_ON
2370 sp->int_cnt++;
2371 #endif
2372
2373 /* If Intr is because of Tx Traffic */
2374 if (reason & GEN_INTR_TXTRAFFIC) {
2375 txIntrHandler(sp);
2376 }
2377
2378 /* If Intr is because of an error */
2379 if (reason & (GEN_ERROR_INTR))
2380 alarmIntrHandler(sp);
2381
2382 #ifdef CONFIG_S2IO_NAPI
2383 if (reason & GEN_INTR_RXTRAFFIC) {
2384 if (netif_rx_schedule_prep(dev)) {
2385 en_dis_able_NicIntrs(sp, RX_TRAFFIC_INTR,
2386 DISABLE_INTRS);
2387 /* We retake the snap shot of the general interrupt
2388 * register.
2389 */
2390 general_mask = readq(&bar0->general_int_mask);
2391 __netif_rx_schedule(dev);
2392 }
2393 }
2394 #else
2395 /* If Intr is because of Rx Traffic */
2396 if (reason & GEN_INTR_RXTRAFFIC) {
2397 rxIntrHandler(sp);
2398 }
2399 #endif
2400
2401 /* If the Rx buffer count is below the panic threshold then reallocate the
2402 * buffers from the interrupt handler itself, else schedule a tasklet to
2403 * reallocate the buffers.
2404 */
2405 #if 1
2406 {
2407 int i;
2408
2409 for (i = 0; i < config->RxRingNum; i++) {
2410 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
2411 int level = rx_buffer_level(sp, rxb_size, i);
2412
2413 if ((level == PANIC) && (!TASKLET_IN_USE)) {
2414 int ret;
2415
2416 DBG_PRINT(ERR_DBG, "%s: Rx BD hit ", dev->name);
2417 DBG_PRINT(ERR_DBG, "PANIC levels\n");
2418 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
2419 DBG_PRINT(ERR_DBG, "%s:Out of memory",
2420 dev->name);
2421 DBG_PRINT(ERR_DBG, " in ISR!!\n");
2422 writeq(general_mask,
2423 &bar0->general_int_mask);
2424 spin_unlock(&sp->isr_lock);
2425 return IRQ_HANDLED;
2426 }
2427 clear_bit(0,
2428 (unsigned long *) (&sp->tasklet_status));
2429 } else if ((level == LOW)
2430 && (!atomic_read(&sp->tasklet_status))) {
2431 tasklet_schedule(&sp->task);
2432 }
2433
2434 }
2435
2436 }
2437 #else
2438 tasklet_schedule(&sp->task);
2439 #endif
2440
2441 /* Unmask all the previously enabled interrupts on the NIC */
2442 writeq(general_mask, &bar0->general_int_mask);
2443
2444 spin_unlock(&sp->isr_lock);
2445 return IRQ_HANDLED;
2446 }
2447
2448 /*
2449 * Input Argument/s:
2450 * dev - pointer to the device structure.
2451 * Return value:
2452 * pointer to the updated net_device_stats structure.
2453 * Description:
2454 * This function updates the device statistics structure in the s2io_nic
2455 * structure and returns a pointer to the same.
2456 */
2457 struct net_device_stats *s2io_get_stats(struct net_device *dev)
2458 {
2459 nic_t *sp = dev->priv;
2460 mac_info_t *mac_control;
2461 struct config_param *config;
2462
2463 mac_control = &sp->mac_control;
2464 config = &sp->config;
2465
2466 sp->stats.tx_errors = mac_control->StatsInfo->tmac_any_err_frms;
2467 sp->stats.rx_errors = mac_control->StatsInfo->rmac_drop_frms;
2468 sp->stats.multicast = mac_control->StatsInfo->rmac_vld_mcst_frms;
2469 sp->stats.rx_length_errors =
2470 mac_control->StatsInfo->rmac_long_frms;
2471
2472 return (&sp->stats);
2473 }
2474
2475 /*
2476 * Input Argument/s:
2477 * dev - pointer to the device structure
2478 * Return value:
2479 * void.
2480 * Description:
2481 * This function is a driver entry point which gets called by the kernel
2482 * whenever multicast addresses must be enabled/disabled. This also gets
2483 * called to set/reset promiscuous mode. Depending on the deivce flag, we
2484 * determine, if multicast address must be enabled or if promiscuous mode
2485 * is to be disabled etc.
2486 */
2487 static void s2io_set_multicast(struct net_device *dev)
2488 {
2489 int i, j, prev_cnt;
2490 struct dev_mc_list *mclist;
2491 nic_t *sp = dev->priv;
2492 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2493 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
2494 0xfeffffffffffULL;
2495 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
2496 void *add;
2497
2498 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
2499 /* Enable all Multicast addresses */
2500 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
2501 &bar0->rmac_addr_data0_mem);
2502 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
2503 &bar0->rmac_addr_data1_mem);
2504 val64 = RMAC_ADDR_CMD_MEM_WE |
2505 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2506 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
2507 writeq(val64, &bar0->rmac_addr_cmd_mem);
2508 /* Wait till command completes */
2509 waitForCmdComplete(sp);
2510
2511 sp->m_cast_flg = 1;
2512 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
2513 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
2514 /* Disable all Multicast addresses */
2515 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
2516 &bar0->rmac_addr_data0_mem);
2517 val64 = RMAC_ADDR_CMD_MEM_WE |
2518 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2519 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
2520 writeq(val64, &bar0->rmac_addr_cmd_mem);
2521 /* Wait till command completes */
2522 waitForCmdComplete(sp);
2523
2524 sp->m_cast_flg = 0;
2525 sp->all_multi_pos = 0;
2526 }
2527
2528 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
2529 /* Put the NIC into promiscuous mode */
2530 add = (void *) &bar0->mac_cfg;
2531 val64 = readq(&bar0->mac_cfg);
2532 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
2533
2534 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
2535 writel((u32) val64, add);
2536 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
2537 writel((u32) (val64 >> 32), (add + 4));
2538
2539 val64 = readq(&bar0->mac_cfg);
2540 sp->promisc_flg = 1;
2541 DBG_PRINT(ERR_DBG, "%s: entered promiscuous mode\n",
2542 dev->name);
2543 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
2544 /* Remove the NIC from promiscuous mode */
2545 add = (void *) &bar0->mac_cfg;
2546 val64 = readq(&bar0->mac_cfg);
2547 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
2548
2549 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
2550 writel((u32) val64, add);
2551 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
2552 writel((u32) (val64 >> 32), (add + 4));
2553
2554 val64 = readq(&bar0->mac_cfg);
2555 sp->promisc_flg = 0;
2556 DBG_PRINT(ERR_DBG, "%s: left promiscuous mode\n",
2557 dev->name);
2558 }
2559
2560 /* Update individual M_CAST address list */
2561 if ((!sp->m_cast_flg) && dev->mc_count) {
2562 if (dev->mc_count >
2563 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
2564 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
2565 dev->name);
2566 DBG_PRINT(ERR_DBG, "can be added, please enable ");
2567 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
2568 return;
2569 }
2570
2571 prev_cnt = sp->mc_addr_count;
2572 sp->mc_addr_count = dev->mc_count;
2573
2574 /* Clear out the previous list of Mc in the H/W. */
2575 for (i = 0; i < prev_cnt; i++) {
2576 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
2577 &bar0->rmac_addr_data0_mem);
2578 val64 = RMAC_ADDR_CMD_MEM_WE |
2579 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2580 RMAC_ADDR_CMD_MEM_OFFSET
2581 (MAC_MC_ADDR_START_OFFSET + i);
2582 writeq(val64, &bar0->rmac_addr_cmd_mem);
2583
2584 /* Wait for command completes */
2585 if (waitForCmdComplete(sp)) {
2586 DBG_PRINT(ERR_DBG, "%s: Adding ",
2587 dev->name);
2588 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
2589 return;
2590 }
2591 }
2592
2593 /* Create the new Rx filter list and update the same in H/W. */
2594 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
2595 i++, mclist = mclist->next) {
2596 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
2597 ETH_ALEN);
2598 for (j = 0; j < ETH_ALEN; j++) {
2599 mac_addr |= mclist->dmi_addr[j];
2600 mac_addr <<= 8;
2601 }
2602 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
2603 &bar0->rmac_addr_data0_mem);
2604
2605 val64 = RMAC_ADDR_CMD_MEM_WE |
2606 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2607 RMAC_ADDR_CMD_MEM_OFFSET
2608 (i + MAC_MC_ADDR_START_OFFSET);
2609 writeq(val64, &bar0->rmac_addr_cmd_mem);
2610
2611 /* Wait for command completes */
2612 if (waitForCmdComplete(sp)) {
2613 DBG_PRINT(ERR_DBG, "%s: Adding ",
2614 dev->name);
2615 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
2616 return;
2617 }
2618 }
2619 }
2620 }
2621
2622 /*
2623 * Input Argument/s:
2624 * dev - pointer to the device structure.
2625 * new_mac - a uchar pointer to the new mac address which is to be set.
2626 * Return value:
2627 * SUCCESS on success and an appropriate (-)ve integer as defined in errno.h
2628 * file on failure.
2629 * Description:
2630 * This procedure will program the Xframe to receive frames with new
2631 * Mac Address
2632 */
2633 int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
2634 {
2635 nic_t *sp = dev->priv;
2636 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2637 register u64 val64, mac_addr = 0;
2638 int i;
2639
2640 /*
2641 * Set the new MAC address as the new unicast filter and reflect this
2642 * change on the device address registered with the OS. It will be
2643 * at offset 0.
2644 */
2645 for (i = 0; i < ETH_ALEN; i++) {
2646 mac_addr <<= 8;
2647 mac_addr |= addr[i];
2648 }
2649
2650 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
2651 &bar0->rmac_addr_data0_mem);
2652
2653 val64 =
2654 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2655 RMAC_ADDR_CMD_MEM_OFFSET(0);
2656 writeq(val64, &bar0->rmac_addr_cmd_mem);
2657 /* Wait till command completes */
2658 if (waitForCmdComplete(sp)) {
2659 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
2660 return FAILURE;
2661 }
2662
2663 return SUCCESS;
2664 }
2665
2666 /*
2667 * Input Argument/s:
2668 * sp - private member of the device structure, which is a pointer to the
2669 * s2io_nic structure.
2670 * info - pointer to the structure with parameters given by ethtool to set
2671 * link information.
2672 * Return value:
2673 * 0 on success.
2674 * Description:
2675 * The function sets different link parameters provided by the user onto
2676 * the NIC.
2677 */
2678 static int s2io_ethtool_sset(struct net_device *dev,
2679 struct ethtool_cmd *info)
2680 {
2681 nic_t *sp = dev->priv;
2682 if ((info->autoneg == AUTONEG_ENABLE) ||
2683 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
2684 return -EINVAL;
2685 else {
2686 s2io_close(sp->dev);
2687 s2io_open(sp->dev);
2688 }
2689
2690 return 0;
2691 }
2692
2693 /*
2694 * Input Argument/s:
2695 * sp - private member of the device structure, which is a pointer to the
2696 * s2io_nic structure.
2697 * info - pointer to the structure with parameters given by ethtool to return
2698 * link information.
2699 * Return value:
2700 * void
2701 * Description:
2702 * Returns link specefic information like speed, duplex etc.. to ethtool.
2703 */
2704 int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
2705 {
2706 nic_t *sp = dev->priv;
2707 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2708 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2709 info->port = PORT_FIBRE;
2710 /* info->transceiver?? TODO */
2711
2712 if (netif_carrier_ok(sp->dev)) {
2713 info->speed = 10000;
2714 info->duplex = DUPLEX_FULL;
2715 } else {
2716 info->speed = -1;
2717 info->duplex = -1;
2718 }
2719
2720 info->autoneg = AUTONEG_DISABLE;
2721 return 0;
2722 }
2723
2724 /*
2725 * Input Argument/s:
2726 * sp - private member of the device structure, which is a pointer to the
2727 * s2io_nic structure.
2728 * info - pointer to the structure with parameters given by ethtool to return
2729 * driver information.
2730 * Return value:
2731 * void
2732 * Description:
2733 * Returns driver specefic information like name, version etc.. to ethtool.
2734 */
2735 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
2736 struct ethtool_drvinfo *info)
2737 {
2738 nic_t *sp = dev->priv;
2739
2740 strncpy(info->driver, s2io_driver_name, sizeof(s2io_driver_name));
2741 strncpy(info->version, s2io_driver_version,
2742 sizeof(s2io_driver_version));
2743 strncpy(info->fw_version, "", 32);
2744 strncpy(info->bus_info, sp->pdev->slot_name, 32);
2745 info->regdump_len = XENA_REG_SPACE;
2746 info->eedump_len = XENA_EEPROM_SPACE;
2747 info->testinfo_len = S2IO_TEST_LEN;
2748 info->n_stats = S2IO_STAT_LEN;
2749 }
2750
2751 /*
2752 * Input Argument/s:
2753 * sp - private member of the device structure, which is a pointer to the
2754 * s2io_nic structure.
2755 * regs - pointer to the structure with parameters given by ethtool for
2756 * dumping the registers.
2757 * reg_space - The input argumnet into which all the registers are dumped.
2758 * Return value:
2759 * void
2760 * Description:
2761 * Dumps the entire register space of xFrame NIC into the user given buffer
2762 * area.
2763 */
2764 static void s2io_ethtool_gregs(struct net_device *dev,
2765 struct ethtool_regs *regs, void *space)
2766 {
2767 int i;
2768 u64 reg;
2769 u8 *reg_space = (u8 *) space;
2770 nic_t *sp = dev->priv;
2771
2772 regs->len = XENA_REG_SPACE;
2773 regs->version = sp->pdev->subsystem_device;
2774
2775 for (i = 0; i < regs->len; i += 8) {
2776 reg = readq((void *) (sp->bar0 + i));
2777 memcpy((reg_space + i), &reg, 8);
2778 }
2779 }
2780
2781 /*
2782 * Input Argument/s:
2783 * data - address of the private member of the device structure, which
2784 * is a pointer to the s2io_nic structure, provided as an u32.
2785 * Return value:
2786 * void
2787 * Description:
2788 * This is actually the timer function that alternates the adapter LED bit
2789 * of the adapter control bit to set/reset every time on invocation.
2790 * The timer is set for 1/2 a second, hence tha NIC blinks once every second.
2791 */
2792 static void s2io_phy_id(unsigned long data)
2793 {
2794 nic_t *sp = (nic_t *) data;
2795 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2796 u64 val64 = 0;
2797 u16 subid;
2798
2799 subid = sp->pdev->subsystem_device;
2800 if ((subid & 0xFF) >= 0x07) {
2801 val64 = readq(&bar0->gpio_control);
2802 val64 ^= GPIO_CTRL_GPIO_0;
2803 writeq(val64, &bar0->gpio_control);
2804 } else {
2805 val64 = readq(&bar0->adapter_control);
2806 val64 ^= ADAPTER_LED_ON;
2807 writeq(val64, &bar0->adapter_control);
2808 }
2809
2810 mod_timer(&sp->id_timer, jiffies + HZ / 2);
2811 }
2812
2813 /*
2814 * Input Argument/s:
2815 * sp - private member of the device structure, which is a pointer to the
2816 * s2io_nic structure.
2817 * id - pointer to the structure with identification parameters given by
2818 * ethtool.
2819 * Return value:
2820 * int , returns '0' on success
2821 * Description:
2822 * Used to physically identify the NIC on the system. The Link LED will blink
2823 * for a time specified by the user for identification.
2824 * NOTE: The Link has to be Up to be able to blink the LED. Hence
2825 * identification is possible only if it's link is up.
2826 */
2827 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
2828 {
2829 u64 val64 = 0;
2830 nic_t *sp = dev->priv;
2831 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2832 u16 subid;
2833
2834 subid = sp->pdev->subsystem_device;
2835 if ((subid & 0xFF) < 0x07) {
2836 val64 = readq(&bar0->adapter_control);
2837 if (!(val64 & ADAPTER_CNTL_EN)) {
2838 printk(KERN_ERR
2839 "Adapter Link down, cannot blink LED\n");
2840 return -EFAULT;
2841 }
2842 }
2843 if (sp->id_timer.function == NULL) {
2844 init_timer(&sp->id_timer);
2845 sp->id_timer.function = s2io_phy_id;
2846 sp->id_timer.data = (unsigned long) sp;
2847 }
2848 mod_timer(&sp->id_timer, jiffies);
2849 set_current_state(TASK_INTERRUPTIBLE);
2850 if (data)
2851 schedule_timeout(data * HZ);
2852 else
2853 schedule_timeout(MAX_SCHEDULE_TIMEOUT);
2854 del_timer_sync(&sp->id_timer);
2855
2856 return 0;
2857 }
2858
2859 /*
2860 * Input Argument/s:
2861 * sp - private member of the device structure, which is a pointer to the
2862 * s2io_nic structure.
2863 * ep - pointer to the structure with pause parameters given by ethtool.
2864 * Return value:
2865 * void
2866 * Description:
2867 * Returns the Pause frame generation and reception capability of the NIC.
2868 */
2869 static void s2io_ethtool_getpause_data(struct net_device *dev,
2870 struct ethtool_pauseparam *ep)
2871 {
2872 u64 val64;
2873 nic_t *sp = dev->priv;
2874 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2875
2876 val64 = readq(&bar0->rmac_pause_cfg);
2877 if (val64 & RMAC_PAUSE_GEN_ENABLE)
2878 ep->tx_pause = TRUE;
2879 if (val64 & RMAC_PAUSE_RX_ENABLE)
2880 ep->rx_pause = TRUE;
2881 ep->autoneg = FALSE;
2882 }
2883
2884 /*
2885 * Input Argument/s:
2886 * sp - private member of the device structure, which is a pointer to the
2887 * s2io_nic structure.
2888 * ep - pointer to the structure with pause parameters given by ethtool.
2889 * Return value:
2890 * int, returns '0' on Success
2891 * Description:
2892 * It can be used to set or reset Pause frame generation or reception support
2893 * of the NIC.
2894 */
2895 int s2io_ethtool_setpause_data(struct net_device *dev,
2896 struct ethtool_pauseparam *ep)
2897 {
2898 u64 val64;
2899 nic_t *sp = dev->priv;
2900 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2901
2902 val64 = readq(&bar0->rmac_pause_cfg);
2903 if (ep->tx_pause)
2904 val64 |= RMAC_PAUSE_GEN_ENABLE;
2905 else
2906 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
2907 if (ep->rx_pause)
2908 val64 |= RMAC_PAUSE_RX_ENABLE;
2909 else
2910 val64 &= ~RMAC_PAUSE_RX_ENABLE;
2911 writeq(val64, &bar0->rmac_pause_cfg);
2912 return 0;
2913 }
2914
2915 /*
2916 * Input Argument/s:
2917 * sp - private member of the device structure, which is a pointer to the
2918 * s2io_nic structure.
2919 * off - offset at which the data must be written
2920 * Return value:
2921 * -1 on failure and the value read from the Eeprom if successful.
2922 * Description:
2923 * Will read 4 bytes of data from the user given offset and return the
2924 * read data.
2925 * NOTE: Will allow to read only part of the EEPROM visible through the
2926 * I2C bus.
2927 */
2928 #define S2IO_DEV_ID 5
2929 static u32 readEeprom(nic_t * sp, int off)
2930 {
2931 u32 data = -1, exit_cnt = 0;
2932 u64 val64;
2933 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2934
2935 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
2936 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
2937 I2C_CONTROL_CNTL_START;
2938 writeq(val64, &bar0->i2c_control);
2939
2940 while (exit_cnt < 5) {
2941 val64 = readq(&bar0->i2c_control);
2942 if (I2C_CONTROL_CNTL_END(val64)) {
2943 data = I2C_CONTROL_GET_DATA(val64);
2944 break;
2945 }
2946 set_current_state(TASK_UNINTERRUPTIBLE);
2947 schedule_timeout(HZ / 20);
2948 exit_cnt++;
2949 }
2950
2951 return data;
2952 }
2953
2954 /*
2955 * Input Argument/s:
2956 * sp - private member of the device structure, which is a pointer to the
2957 * s2io_nic structure.
2958 * off - offset at which the data must be written
2959 * data - The data that is to be written
2960 * cnt - Number of bytes of the data that are actually to be written into
2961 * the Eeprom. (max of 3)
2962 * Return value:
2963 * '0' on success, -1 on failure.
2964 * Description:
2965 * Actually writes the relevant part of the data value into the Eeprom
2966 * through the I2C bus.
2967 */
2968 static int writeEeprom(nic_t * sp, int off, u32 data, int cnt)
2969 {
2970 int exit_cnt = 0, ret = -1;
2971 u64 val64;
2972 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
2973
2974 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
2975 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) |
2976 I2C_CONTROL_CNTL_START;
2977 writeq(val64, &bar0->i2c_control);
2978
2979 while (exit_cnt < 5) {
2980 val64 = readq(&bar0->i2c_control);
2981 if (I2C_CONTROL_CNTL_END(val64)) {
2982 if (!(val64 & I2C_CONTROL_NACK))
2983 ret = 0;
2984 break;
2985 }
2986 set_current_state(TASK_UNINTERRUPTIBLE);
2987 schedule_timeout(HZ / 20);
2988 exit_cnt++;
2989 }
2990
2991 return ret;
2992 }
2993
2994 /*
2995 * A helper function used to invert the 4 byte u32 data field
2996 * byte by byte. This will be used by the Read Eeprom function
2997 * for display purposes.
2998 */
2999 u32 inv(u32 data)
3000 {
3001 static u32 ret = 0;
3002
3003 if (data) {
3004 u8 c = data;
3005 ret = ((ret << 8) + c);
3006 data >>= 8;
3007 inv(data);
3008 }
3009
3010 return ret;
3011 }
3012
3013 /*
3014 * Input Argument/s:
3015 * sp - private member of the device structure, which is a pointer to the
3016 * s2io_nic structure.
3017 * eeprom - pointer to the user level structure provided by ethtool,
3018 * containing all relevant information.
3019 * data_buf - user defined value to be written into Eeprom.
3020 * Return value:
3021 * int '0' on success
3022 * Description:
3023 * Reads the values stored in the Eeprom at given offset for a given length.
3024 * Stores these values int the input argument data buffer 'data_buf' and
3025 * returns these to the caller (ethtool.)
3026 */
3027 int s2io_ethtool_geeprom(struct net_device *dev,
3028 struct ethtool_eeprom *eeprom, u8 * data_buf)
3029 {
3030 u32 data, i, valid;
3031 nic_t *sp = dev->priv;
3032
3033 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
3034
3035 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
3036 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
3037
3038 for (i = 0; i < eeprom->len; i += 4) {
3039 data = readEeprom(sp, eeprom->offset + i);
3040 if (data < 0) {
3041 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
3042 return -EFAULT;
3043 }
3044 valid = inv(data);
3045 memcpy((data_buf + i), &valid, 4);
3046 }
3047 return 0;
3048 }
3049
3050 /*
3051 * Input Argument/s:
3052 * sp - private member of the device structure, which is a pointer to the
3053 * s2io_nic structure.
3054 * eeprom - pointer to the user level structure provided by ethtool,
3055 * containing all relevant information.
3056 * data_buf - user defined value to be written into Eeprom.
3057 * Return value:
3058 * '0' on success, -EFAULT on failure.
3059 * Description:
3060 * Tries to write the user provided value in the Eeprom, at the offset
3061 * given by the user.
3062 */
3063 static int s2io_ethtool_seeprom(struct net_device *dev,
3064 struct ethtool_eeprom *eeprom,
3065 u8 * data_buf)
3066 {
3067 int len = eeprom->len, cnt = 0;
3068 u32 valid = 0, data;
3069 nic_t *sp = dev->priv;
3070
3071 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
3072 DBG_PRINT(ERR_DBG,
3073 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
3074 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
3075 eeprom->magic);
3076 return -EFAULT;
3077 }
3078
3079 while (len) {
3080 data = (u32) data_buf[cnt] & 0x000000FF;
3081 if (data) {
3082 valid = (u32) (data << 24);
3083 } else
3084 valid = data;
3085
3086 if (writeEeprom(sp, (eeprom->offset + cnt), valid, 0)) {
3087 DBG_PRINT(ERR_DBG,
3088 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
3089 DBG_PRINT(ERR_DBG,
3090 "write into the specified offset\n");
3091 return -EFAULT;
3092 }
3093 cnt++;
3094 len--;
3095 }
3096
3097 return 0;
3098 }
3099
3100 /*
3101 * Input Argument/s:
3102 * sp - private member of the device structure, which is a pointer to the
3103 * s2io_nic structure.
3104 * data - variable that returns the result of each of the test conducted by
3105 * the driver.
3106 * Return value:
3107 * '0' on success.
3108 * Description:
3109 * Read and write into all clock domains. The NIC has 3 clock domains,
3110 * see that registers in all the three regions are accessible.
3111 */
3112 static int s2io_registerTest(nic_t * sp, uint64_t * data)
3113 {
3114 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
3115 u64 val64 = 0;
3116 int fail = 0;
3117
3118 val64 = readq(&bar0->pcc_enable);
3119 if (val64 != 0xff00000000000000ULL) {
3120 fail = 1;
3121 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
3122 }
3123
3124 val64 = readq(&bar0->rmac_pause_cfg);
3125 if (val64 != 0xc000ffff00000000ULL) {
3126 fail = 1;
3127 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
3128 }
3129
3130 val64 = readq(&bar0->rx_queue_cfg);
3131 if (val64 != 0x0808080808080808ULL) {
3132 fail = 1;
3133 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
3134 }
3135
3136 val64 = readq(&bar0->xgxs_efifo_cfg);
3137 if (val64 != 0x000000001923141EULL) {
3138 fail = 1;
3139 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
3140 }
3141
3142 val64 = 0x5A5A5A5A5A5A5A5AULL;
3143 writeq(val64, &bar0->xmsi_data);
3144 val64 = readq(&bar0->xmsi_data);
3145 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
3146 fail = 1;
3147 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
3148 }
3149
3150 val64 = 0xA5A5A5A5A5A5A5A5ULL;
3151 writeq(val64, &bar0->xmsi_data);
3152 val64 = readq(&bar0->xmsi_data);
3153 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
3154 fail = 1;
3155 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
3156 }
3157
3158 *data = fail;
3159 return 0;
3160 }
3161
3162 /*
3163 * Input Argument/s:
3164 * sp - private member of the device structure, which is a pointer to the
3165 * s2io_nic structure.
3166 * data - variable that returns the result of each of the test conducted by
3167 * the driver.
3168 * Return value:
3169 * '0' on success.
3170 * Description:
3171 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
3172 * register.
3173 */
3174 static int s2io_eepromTest(nic_t * sp, uint64_t * data)
3175 {
3176 int fail = 0, ret_data;
3177
3178 /* Test Write Error at offset 0 */
3179 if (!writeEeprom(sp, 0, 0, 3))
3180 fail = 1;
3181
3182 /* Test Write at offset 4f0 */
3183 if (writeEeprom(sp, 0x4F0, 0x01234567, 3))
3184 fail = 1;
3185 if ((ret_data = readEeprom(sp, 0x4f0)) < 0)
3186 fail = 1;
3187
3188 if (ret_data != 0x01234567)
3189 fail = 1;
3190
3191 /* Reset the EEPROM data go FFFF */
3192 writeEeprom(sp, 0x4F0, 0xFFFFFFFF, 3);
3193
3194 /* Test Write Request Error at offset 0x7c */
3195 if (!writeEeprom(sp, 0x07C, 0, 3))
3196 fail = 1;
3197
3198 /* Test Write Request at offset 0x7fc */
3199 if (writeEeprom(sp, 0x7FC, 0x01234567, 3))
3200 fail = 1;
3201 if ((ret_data = readEeprom(sp, 0x7FC)) < 0)
3202 fail = 1;
3203
3204 if (ret_data != 0x01234567)
3205 fail = 1;
3206
3207 /* Reset the EEPROM data go FFFF */
3208 writeEeprom(sp, 0x7FC, 0xFFFFFFFF, 3);
3209
3210 /* Test Write Error at offset 0x80 */
3211 if (!writeEeprom(sp, 0x080, 0, 3))
3212 fail = 1;
3213
3214 /* Test Write Error at offset 0xfc */
3215 if (!writeEeprom(sp, 0x0FC, 0, 3))
3216 fail = 1;
3217
3218 /* Test Write Error at offset 0x100 */
3219 if (!writeEeprom(sp, 0x100, 0, 3))
3220 fail = 1;
3221
3222 /* Test Write Error at offset 4ec */
3223 if (!writeEeprom(sp, 0x4EC, 0, 3))
3224 fail = 1;
3225
3226 *data = fail;
3227 return 0;
3228 }
3229
3230 /*
3231 * Input Argument/s:
3232 * sp - private member of the device structure, which is a pointer to the
3233 * s2io_nic structure.
3234 * data - variable that returns the result of each of the test conducted by
3235 * the driver.
3236 * Return value:
3237 * '0' on success and -1 on failure.
3238 * Description:
3239 * This invokes the MemBist test of the card. We give around
3240 * 2 secs time for the Test to complete. If it's still not complete
3241 * within this peiod, we consider that the test failed.
3242 */
3243 static int s2io_bistTest(nic_t * sp, uint64_t * data)
3244 {
3245 u8 bist = 0;
3246 int cnt = 0, ret = -1;
3247
3248 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
3249 bist |= PCI_BIST_START;
3250 pci_write_config_word(sp->pdev, PCI_BIST, bist);
3251
3252 while (cnt < 20) {
3253 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
3254 if (!(bist & PCI_BIST_START)) {
3255 *data = (bist & PCI_BIST_CODE_MASK);
3256 ret = 0;
3257 break;
3258 }
3259 set_current_state(TASK_UNINTERRUPTIBLE);
3260 schedule_timeout(HZ / 10);
3261 cnt++;
3262 }
3263
3264 return ret;
3265 }
3266
3267 /*
3268 * Input Argument/s:
3269 * sp - private member of the device structure, which is a pointer to the
3270 * s2io_nic structure.
3271 * data - variable that returns the result of each of the test conducted by
3272 * the driver.
3273 * Return value:
3274 * '0' on success.
3275 * Description:
3276 * The function verifies the link state of the NIC and updates the input
3277 * argument 'data' appropriately.
3278 */
3279 static int s2io_linkTest(nic_t * sp, uint64_t * data)
3280 {
3281 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
3282 u64 val64;
3283
3284 val64 = readq(&bar0->adapter_status);
3285 if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
3286 *data = 1;
3287
3288 return 0;
3289 }
3290
3291 /*
3292 * Input Argument/s:
3293 * sp - private member of the device structure, which is a pointer to the
3294 * s2io_nic structure.
3295 * data - variable that returns the result of each of the test conducted by
3296 * the driver.
3297 * Return value:
3298 * '0' on success.
3299 * Description:
3300 * This is one of the offline test that tests the read and write
3301 * access to the RldRam chip on the NIC.
3302 */
3303 static int s2io_rldramTest(nic_t * sp, uint64_t * data)
3304 {
3305 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
3306 u64 val64;
3307 int cnt, iteration = 0, test_pass = 0;
3308
3309 val64 = readq(&bar0->adapter_control);
3310 val64 &= ~ADAPTER_ECC_EN;
3311 writeq(val64, &bar0->adapter_control);
3312
3313 val64 = readq(&bar0->mc_rldram_test_ctrl);
3314 val64 |= MC_RLDRAM_TEST_MODE;
3315 writeq(val64, &bar0->mc_rldram_test_ctrl);
3316
3317 val64 = readq(&bar0->mc_rldram_mrs);
3318 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
3319 writeq(val64, &bar0->mc_rldram_mrs);
3320
3321 val64 |= MC_RLDRAM_MRS_ENABLE;
3322 writeq(val64, &bar0->mc_rldram_mrs);
3323
3324 while (iteration < 2) {
3325 val64 = 0x55555555aaaa0000ULL;
3326 if (iteration == 1) {
3327 val64 ^= 0xFFFFFFFFFFFF0000ULL;
3328 }
3329 writeq(val64, &bar0->mc_rldram_test_d0);
3330
3331 val64 = 0xaaaa5a5555550000ULL;
3332 if (iteration == 1) {
3333 val64 ^= 0xFFFFFFFFFFFF0000ULL;
3334 }
3335 writeq(val64, &bar0->mc_rldram_test_d1);
3336
3337 val64 = 0x55aaaaaaaa5a0000ULL;
3338 if (iteration == 1) {
3339 val64 ^= 0xFFFFFFFFFFFF0000ULL;
3340 }
3341 writeq(val64, &bar0->mc_rldram_test_d2);
3342
3343 val64 = (u64) (0x0000003fffff0000ULL);
3344 writeq(val64, &bar0->mc_rldram_test_add);
3345
3346
3347 val64 = MC_RLDRAM_TEST_MODE;
3348 writeq(val64, &bar0->mc_rldram_test_ctrl);
3349
3350 val64 |=
3351 MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
3352 MC_RLDRAM_TEST_GO;
3353 writeq(val64, &bar0->mc_rldram_test_ctrl);
3354
3355 for (cnt = 0; cnt < 5; cnt++) {
3356 val64 = readq(&bar0->mc_rldram_test_ctrl);
3357 if (val64 & MC_RLDRAM_TEST_DONE)
3358 break;
3359 set_current_state(TASK_UNINTERRUPTIBLE);
3360 schedule_timeout(HZ / 5);
3361 }
3362
3363 if (cnt == 5)
3364 break;
3365
3366 val64 = MC_RLDRAM_TEST_MODE;
3367 writeq(val64, &bar0->mc_rldram_test_ctrl);
3368
3369 val64 |= MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
3370 writeq(val64, &bar0->mc_rldram_test_ctrl);
3371
3372 for (cnt = 0; cnt < 5; cnt++) {
3373 val64 = readq(&bar0->mc_rldram_test_ctrl);
3374 if (val64 & MC_RLDRAM_TEST_DONE)
3375 break;
3376 set_current_state(TASK_UNINTERRUPTIBLE);
3377 schedule_timeout(HZ / 2);
3378 }
3379
3380 if (cnt == 5)
3381 break;
3382
3383 val64 = readq(&bar0->mc_rldram_test_ctrl);
3384 if (val64 & MC_RLDRAM_TEST_PASS)
3385 test_pass = 1;
3386
3387 iteration++;
3388 }
3389
3390 if (!test_pass)
3391 *data = 1;
3392 else
3393 *data = 0;
3394
3395 return 0;
3396 }
3397
3398 /*
3399 * Input Argument/s:
3400 * sp - private member of the device structure, which is a pointer to the
3401 * s2io_nic structure.
3402 * ethtest - pointer to a ethtool command specific structure that will be
3403 * returned to the user.
3404 * data - variable that returns the result of each of the test conducted by
3405 * the driver.
3406 * Return value:
3407 * SUCCESS on success and an appropriate -1 on failure.
3408 * Description:
3409 * This function conducts 6 tests ( 4 offline and 2 online) to determine
3410 * the health of the card.
3411 */
3412 static void s2io_ethtool_test(struct net_device *dev,
3413 struct ethtool_test *ethtest,
3414 uint64_t * data)
3415 {
3416 nic_t *sp = dev->priv;
3417 int orig_state = netif_running(sp->dev);
3418
3419 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
3420 /* Offline Tests. */
3421 if (orig_state) {
3422 s2io_close(sp->dev);
3423 s2io_set_swapper(sp);
3424 } else
3425 s2io_set_swapper(sp);
3426
3427 if (s2io_registerTest(sp, &data[0]))
3428 ethtest->flags |= ETH_TEST_FL_FAILED;
3429
3430 s2io_reset(sp);
3431 s2io_set_swapper(sp);
3432
3433 if (s2io_rldramTest(sp, &data[3]))
3434 ethtest->flags |= ETH_TEST_FL_FAILED;
3435
3436 s2io_reset(sp);
3437 s2io_set_swapper(sp);
3438
3439 if (s2io_eepromTest(sp, &data[1]))
3440 ethtest->flags |= ETH_TEST_FL_FAILED;
3441
3442 if (s2io_bistTest(sp, &data[4]))
3443 ethtest->flags |= ETH_TEST_FL_FAILED;
3444
3445 if (orig_state)
3446 s2io_open(sp->dev);
3447
3448 data[2] = 0;
3449 } else {
3450 /* Online Tests. */
3451 if (!orig_state) {
3452 DBG_PRINT(ERR_DBG,
3453 "%s: is not up, cannot run test\n",
3454 dev->name);
3455 data[0] = -1;
3456 data[1] = -1;
3457 data[2] = -1;
3458 data[3] = -1;
3459 data[4] = -1;
3460 }
3461
3462 if (s2io_linkTest(sp, &data[2]))
3463 ethtest->flags |= ETH_TEST_FL_FAILED;
3464
3465 data[0] = 0;
3466 data[1] = 0;
3467 data[3] = 0;
3468 data[4] = 0;
3469 }
3470 }
3471
3472 static void s2io_get_ethtool_stats(struct net_device *dev,
3473 struct ethtool_stats *estats,
3474 u64 * tmp_stats)
3475 {
3476 int i = 0;
3477 nic_t *sp = dev->priv;
3478 StatInfo_t *stat_info = sp->mac_control.StatsInfo;
3479
3480 tmp_stats[i++] = stat_info->tmac_frms;
3481 tmp_stats[i++] = stat_info->tmac_data_octets;
3482 tmp_stats[i++] = stat_info->tmac_drop_frms;
3483 tmp_stats[i++] = stat_info->tmac_mcst_frms;
3484 tmp_stats[i++] = stat_info->tmac_bcst_frms;
3485 tmp_stats[i++] = stat_info->tmac_pause_ctrl_frms;
3486 tmp_stats[i++] = stat_info->tmac_any_err_frms;
3487 tmp_stats[i++] = stat_info->tmac_vld_ip_octets;
3488 tmp_stats[i++] = stat_info->tmac_vld_ip;
3489 tmp_stats[i++] = stat_info->tmac_drop_ip;
3490 tmp_stats[i++] = stat_info->tmac_icmp;
3491 tmp_stats[i++] = stat_info->tmac_rst_tcp;
3492 tmp_stats[i++] = stat_info->tmac_tcp;
3493 tmp_stats[i++] = stat_info->tmac_udp;
3494 tmp_stats[i++] = stat_info->rmac_vld_frms;
3495 tmp_stats[i++] = stat_info->rmac_data_octets;
3496 tmp_stats[i++] = stat_info->rmac_fcs_err_frms;
3497 tmp_stats[i++] = stat_info->rmac_drop_frms;
3498 tmp_stats[i++] = stat_info->rmac_vld_mcst_frms;
3499 tmp_stats[i++] = stat_info->rmac_vld_bcst_frms;
3500 tmp_stats[i++] = stat_info->rmac_in_rng_len_err_frms;
3501 tmp_stats[i++] = stat_info->rmac_long_frms;
3502 tmp_stats[i++] = stat_info->rmac_pause_ctrl_frms;
3503 tmp_stats[i++] = stat_info->rmac_discarded_frms;
3504 tmp_stats[i++] = stat_info->rmac_usized_frms;
3505 tmp_stats[i++] = stat_info->rmac_osized_frms;
3506 tmp_stats[i++] = stat_info->rmac_frag_frms;
3507 tmp_stats[i++] = stat_info->rmac_jabber_frms;
3508 tmp_stats[i++] = stat_info->rmac_ip;
3509 tmp_stats[i++] = stat_info->rmac_ip_octets;
3510 tmp_stats[i++] = stat_info->rmac_hdr_err_ip;
3511 tmp_stats[i++] = stat_info->rmac_drop_ip;
3512 tmp_stats[i++] = stat_info->rmac_icmp;
3513 tmp_stats[i++] = stat_info->rmac_tcp;
3514 tmp_stats[i++] = stat_info->rmac_udp;
3515 tmp_stats[i++] = stat_info->rmac_err_drp_udp;
3516 tmp_stats[i++] = stat_info->rmac_pause_cnt;
3517 tmp_stats[i++] = stat_info->rmac_accepted_ip;
3518 tmp_stats[i++] = stat_info->rmac_err_tcp;
3519 }
3520
3521 int s2io_ethtool_get_regs_len(struct net_device *dev)
3522 {
3523 return (XENA_REG_SPACE);
3524 }
3525
3526
3527 u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
3528 {
3529 nic_t *sp = dev->priv;
3530
3531 return (sp->rx_csum);
3532 }
3533 int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3534 {
3535 nic_t *sp = dev->priv;
3536
3537 if (data)
3538 sp->rx_csum = 1;
3539 else
3540 sp->rx_csum = 0;
3541
3542 return 0;
3543 }
3544 int s2io_get_eeprom_len(struct net_device *dev)
3545 {
3546 return (XENA_EEPROM_SPACE);
3547 }
3548
3549 int s2io_ethtool_self_test_count(struct net_device *dev)
3550 {
3551 return (S2IO_TEST_LEN);
3552 }
3553 void s2io_ethtool_get_strings(struct net_device *dev,
3554 u32 stringset, u8 * data)
3555 {
3556 switch (stringset) {
3557 case ETH_SS_TEST:
3558 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
3559 break;
3560 case ETH_SS_STATS:
3561 memcpy(data, &ethtool_stats_keys,
3562 sizeof(ethtool_stats_keys));
3563 }
3564 }
3565 static int s2io_ethtool_get_stats_count(struct net_device *dev)
3566 {
3567 return (S2IO_STAT_LEN);
3568 }
3569
3570 static struct ethtool_ops netdev_ethtool_ops = {
3571 .get_settings = s2io_ethtool_gset,
3572 .set_settings = s2io_ethtool_sset,
3573 .get_drvinfo = s2io_ethtool_gdrvinfo,
3574 .get_regs_len = s2io_ethtool_get_regs_len,
3575 .get_regs = s2io_ethtool_gregs,
3576 .get_link = ethtool_op_get_link,
3577 .get_eeprom_len = s2io_get_eeprom_len,
3578 .get_eeprom = s2io_ethtool_geeprom,
3579 .set_eeprom = s2io_ethtool_seeprom,
3580 .get_pauseparam = s2io_ethtool_getpause_data,
3581 .set_pauseparam = s2io_ethtool_setpause_data,
3582 .get_rx_csum = s2io_ethtool_get_rx_csum,
3583 .set_rx_csum = s2io_ethtool_set_rx_csum,
3584 .get_tx_csum = ethtool_op_get_tx_csum,
3585 .set_tx_csum = ethtool_op_set_tx_csum,
3586 .get_sg = ethtool_op_get_sg,
3587 .set_sg = ethtool_op_set_sg,
3588 #ifdef NETIF_F_TSO
3589 .get_tso = ethtool_op_get_tso,
3590 .set_tso = ethtool_op_set_tso,
3591 #endif
3592 .self_test_count = s2io_ethtool_self_test_count,
3593 .self_test = s2io_ethtool_test,
3594 .get_strings = s2io_ethtool_get_strings,
3595 .phys_id = s2io_ethtool_idnic,
3596 .get_stats_count = s2io_ethtool_get_stats_count,
3597 .get_ethtool_stats = s2io_get_ethtool_stats
3598 };
3599
3600 /*
3601 * Input Argument/s:
3602 * dev - Device pointer.
3603 * ifr - An IOCTL specefic structure, that can contain a pointer to
3604 * a proprietary structure used to pass information to the driver.
3605 * cmd - This is used to distinguish between the different commands that
3606 * can be passed to the IOCTL functions.
3607 * Return value:
3608 * '0' on success and an appropriate (-)ve integer as defined in errno.h
3609 * file on failure.
3610 * Description:
3611 * This function has support for ethtool, adding multiple MAC addresses on
3612 * the NIC and some DBG commands for the util tool.
3613 */
3614 int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3615 {
3616 return -EOPNOTSUPP;
3617 }
3618
3619 /*
3620 * Input Argument/s:
3621 * dev - device pointer.
3622 * new_mtu - the new MTU size for the device.
3623 * Return value:
3624 * '0' on success and an appropriate (-)ve integer as defined in errno.h
3625 * file on failure.
3626 * Description:
3627 * A driver entry point to change MTU size for the device. Before changing
3628 * the MTU the device must be stopped.
3629 */
3630 int s2io_change_mtu(struct net_device *dev, int new_mtu)
3631 {
3632 nic_t *sp = dev->priv;
3633 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
3634 register u64 val64;
3635
3636 if (netif_running(dev)) {
3637 DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name);
3638 DBG_PRINT(ERR_DBG, "change its MTU \n");
3639 return -EBUSY;
3640 }
3641
3642 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
3643 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
3644 dev->name);
3645 return -EPERM;
3646 }
3647
3648 /* Set the new MTU into the PYLD register of the NIC */
3649 val64 = new_mtu;
3650 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
3651
3652 dev->mtu = new_mtu;
3653
3654 return 0;
3655 }
3656
3657 /*
3658 * Input Argument/s:
3659 * dev_adr - address of the device structure in dma_addr_t format.
3660 * Return value:
3661 * void.
3662 * Description:
3663 * This is the tasklet or the bottom half of the ISR. This is
3664 * an extension of the ISR which is scheduled by the scheduler to be run
3665 * when the load on the CPU is low. All low priority tasks of the ISR can
3666 * be pushed into the tasklet. For now the tasklet is used only to
3667 * replenish the Rx buffers in the Rx buffer descriptors.
3668 */
3669 static void s2io_tasklet(unsigned long dev_addr)
3670 {
3671 struct net_device *dev = (struct net_device *) dev_addr;
3672 nic_t *sp = dev->priv;
3673 int i, ret;
3674 mac_info_t *mac_control;
3675 struct config_param *config;
3676
3677 mac_control = &sp->mac_control;
3678 config = &sp->config;
3679
3680 if (!TASKLET_IN_USE) {
3681 for (i = 0; i < config->RxRingNum; i++) {
3682 ret = fill_rx_buffers(sp, i);
3683 if (ret == -ENOMEM) {
3684 DBG_PRINT(ERR_DBG, "%s: Out of ",
3685 dev->name);
3686 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
3687 return;
3688 } else if (ret == -EFILL) {
3689 DBG_PRINT(ERR_DBG,
3690 "%s: Rx Ring %d is full\n",
3691 dev->name, i);
3692 return;
3693 }
3694 }
3695 clear_bit(0, (unsigned long *) (&sp->tasklet_status));
3696 }
3697 }
3698
3699
3700 /*
3701 * Description:
3702 *
3703 */
3704 static void s2io_set_link(unsigned long data)
3705 {
3706 nic_t *nic = (nic_t *) data;
3707 struct net_device *dev = nic->dev;
3708 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3709 register u64 val64, err_reg;
3710
3711 /* Allow a small delay for the NICs self initiated
3712 * cleanup to complete.
3713 */
3714 set_current_state(TASK_UNINTERRUPTIBLE);
3715 schedule_timeout(HZ / 10);
3716
3717 val64 = readq(&bar0->adapter_status);
3718 if (verify_xena_quiescence(val64, nic->device_enabled_once)) {
3719 /* Acknowledge interrupt and clear the R1 register */
3720 err_reg = readq(&bar0->mac_rmac_err_reg);
3721 writeq(err_reg, &bar0->mac_rmac_err_reg);
3722
3723 if (LINK_IS_UP(val64)) {
3724 val64 = readq(&bar0->adapter_control);
3725 val64 |= ADAPTER_CNTL_EN;
3726 writeq(val64, &bar0->adapter_control);
3727 val64 |= ADAPTER_LED_ON;
3728 writeq(val64, &bar0->adapter_control);
3729 val64 = readq(&bar0->adapter_status);
3730 if (!LINK_IS_UP(val64)) {
3731 DBG_PRINT(ERR_DBG, "%s:", dev->name);
3732 DBG_PRINT(ERR_DBG, " Link down");
3733 DBG_PRINT(ERR_DBG, "after ");
3734 DBG_PRINT(ERR_DBG, "enabling ");
3735 DBG_PRINT(ERR_DBG, "device \n");
3736 }
3737 if (nic->device_enabled_once == FALSE) {
3738 nic->device_enabled_once = TRUE;
3739 }
3740 s2io_link(nic, LINK_UP);
3741 } else {
3742 s2io_link(nic, LINK_DOWN);
3743 }
3744 } else { /* NIC is not Quiescent. */
3745 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
3746 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3747 netif_stop_queue(dev);
3748 }
3749 }
3750
3751 /*
3752 * Description:
3753 * This function is scheduled to be run by the s2io_tx_watchdog
3754 * function after 0.5 secs to reset the NIC. The idea is to reduce
3755 * the run time of the watch dog routine which is run holding a
3756 * spin lock.
3757 */
3758 static void s2io_restart_nic(unsigned long data)
3759 {
3760 struct net_device *dev = (struct net_device *) data;
3761 nic_t *sp = dev->priv;
3762
3763 s2io_close(dev);
3764 sp->device_close_flag = TRUE;
3765 s2io_open(dev);
3766 DBG_PRINT(ERR_DBG,
3767 "%s: was reset by Tx watchdog timer.\n", dev->name);
3768 }
3769
3770 /*
3771 * Input Argument/s:
3772 * dev - device pointer.
3773 * Return value:
3774 * void
3775 * Description:
3776 * This function is triggered if the Tx Queue is stopped
3777 * for a pre-defined amount of time when the Interface is still up.
3778 * If the Interface is jammed in such a situation, the hardware is
3779 * reset (by s2io_close) and restarted again (by s2io_open) to
3780 * overcome any problem that might have been caused in the hardware.
3781 */
3782 static void s2io_tx_watchdog(struct net_device *dev)
3783 {
3784 nic_t *sp = dev->priv;
3785
3786 if (netif_carrier_ok(dev)) {
3787 schedule_work(&sp->rst_timer_task);
3788 }
3789 }
3790
3791 /*
3792 * Input Argument/s:
3793 * sp - private member of the device structure, which is a pointer to the
3794 * s2io_nic structure.
3795 * skb - the socket buffer pointer.
3796 * len - length of the packet
3797 * cksum - FCS checksum of the frame.
3798 * ring_no - the ring from which this RxD was extracted.
3799 * Return value:
3800 * SUCCESS on success and -1 on failure.
3801 * Description:
3802 * This function is called by the Tx interrupt serivce routine to perform
3803 * some OS related operations on the SKB before passing it to the upper
3804 * layers. It mainly checks if the checksum is OK, if so adds it to the
3805 * SKBs cksum variable, increments the Rx packet count and passes the SKB
3806 * to the upper layer. If the checksum is wrong, it increments the Rx
3807 * packet error count, frees the SKB and returns error.
3808 */
3809 static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
3810 {
3811 struct net_device *dev = (struct net_device *) sp->dev;
3812 struct sk_buff *skb =
3813 (struct sk_buff *) ((unsigned long) rxdp->Host_Control);
3814 u16 l3_csum, l4_csum;
3815
3816 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
3817 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) {
3818 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
3819 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
3820 /* NIC verifies if the Checksum of the received
3821 * frame is Ok or not and accordingly returns
3822 * a flag in the RxD.
3823 */
3824 skb->ip_summed = CHECKSUM_UNNECESSARY;
3825 } else {
3826 /*
3827 * Packet with erroneous checksum, let the
3828 * upper layers deal with it.
3829 */
3830 skb->ip_summed = CHECKSUM_NONE;
3831 }
3832 } else {
3833 skb->ip_summed = CHECKSUM_NONE;
3834 }
3835
3836 skb->dev = dev;
3837 skb_put(skb, len);
3838 skb->protocol = eth_type_trans(skb, dev);
3839
3840 #ifdef CONFIG_S2IO_NAPI
3841 netif_receive_skb(skb);
3842 #else
3843 netif_rx(skb);
3844 #endif
3845
3846 dev->last_rx = jiffies;
3847 #if DEBUG_ON
3848 sp->rxpkt_cnt++;
3849 #endif
3850 sp->rx_pkt_count++;
3851 sp->stats.rx_packets++;
3852 sp->stats.rx_bytes += len;
3853 sp->rxpkt_bytes += len;
3854
3855 atomic_dec(&sp->rx_bufs_left[ring_no]);
3856 rxdp->Host_Control = 0;
3857 return SUCCESS;
3858 }
3859
3860 int check_for_txSpace(nic_t * sp)
3861 {
3862 u32 put_off, get_off, queue_len;
3863 int ret = TRUE, i;
3864
3865 for (i = 0; i < sp->config.TxFIFONum; i++) {
3866 queue_len = sp->mac_control.tx_curr_put_info[i].fifo_len
3867 + 1;
3868 put_off = sp->mac_control.tx_curr_put_info[i].offset;
3869 get_off = sp->mac_control.tx_curr_get_info[i].offset;
3870 if (((put_off + 1) % queue_len) == get_off) {
3871 ret = FALSE;
3872 break;
3873 }
3874 }
3875
3876 return ret;
3877 }
3878
3879 /*
3880 * Input Argument/s:
3881 * sp - private member of the device structure, which is a pointer to the
3882 * s2io_nic structure.
3883 * link - inidicates whether link is UP/DOWN.
3884 * Return value:
3885 * void.
3886 * Description:
3887 * This function stops/starts the Tx queue depending on whether the link
3888 * status of the NIC is is down or up. This is called by the Alarm interrupt
3889 * handler whenever a link change interrupt comes up.
3890 */
3891 void s2io_link(nic_t * sp, int link)
3892 {
3893 struct net_device *dev = (struct net_device *) sp->dev;
3894
3895 if (link != sp->last_link_state) {
3896 if (link == LINK_DOWN) {
3897 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3898 netif_carrier_off(dev);
3899 netif_stop_queue(dev);
3900 } else {
3901 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
3902 netif_carrier_on(dev);
3903 if (check_for_txSpace(sp) == TRUE) {
3904 /* Don't wake the queue, if we know there
3905 * are no free TxDs available.
3906 */
3907 netif_wake_queue(dev);
3908 }
3909 }
3910 }
3911 sp->last_link_state = link;
3912 }
3913
3914 /*
3915 * Input Argument/s:
3916 * pdev - structure containing the PCI related information of the device.
3917 * Return value:
3918 * returns the revision ID of the device.
3919 * Description:
3920 * Function to identify the Revision ID of xena.
3921 */
3922 int get_xena_rev_id(struct pci_dev *pdev)
3923 {
3924 u8 id = 0;
3925 int ret;
3926 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
3927 return id;
3928 }
3929
3930 /*
3931 * Input Argument/s:
3932 * sp - private member of the device structure, which is a pointer to the
3933 * s2io_nic structure.
3934 * Return value:
3935 * void
3936 * Description:
3937 * This function initializes a few of the PCI and PCI-X configuration registers
3938 * with recommended values.
3939 */
3940 static void s2io_init_pci(nic_t * sp)
3941 {
3942 u16 pci_cmd = 0;
3943
3944 /* Enable Data Parity Error Recovery in PCI-X command register. */
3945 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3946 &(sp->pcix_cmd));
3947 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3948 (sp->pcix_cmd | 1));
3949 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3950 &(sp->pcix_cmd));
3951
3952 /* Set the PErr Response bit in PCI command register. */
3953 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
3954 pci_write_config_word(sp->pdev, PCI_COMMAND,
3955 (pci_cmd | PCI_COMMAND_PARITY));
3956 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
3957
3958 /* Set user specified value in Latency Timer */
3959 if (latency_timer) {
3960 pci_write_config_byte(sp->pdev, PCI_LATENCY_TIMER,
3961 latency_timer);
3962 pci_read_config_byte(sp->pdev, PCI_LATENCY_TIMER,
3963 &latency_timer);
3964 }
3965
3966 /* Set MMRB count to 4096 in PCI-X Command register. */
3967 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3968 (sp->pcix_cmd | 0x0C));
3969 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3970 &(sp->pcix_cmd));
3971
3972 /* Setting Maximum outstanding splits to two for now. */
3973 sp->pcix_cmd &= 0xFF1F;
3974
3975 sp->pcix_cmd |=
3976 XENA_MAX_OUTSTANDING_SPLITS(XENA_TWO_SPLIT_TRANSACTION);
3977 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3978 sp->pcix_cmd);
3979 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3980 &(sp->pcix_cmd));
3981
3982 }
3983
3984 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@s2io.com>");
3985 MODULE_LICENSE("GPL");
3986 MODULE_PARM(ring_num, "1-" __MODULE_STRING(1) "i");
3987 MODULE_PARM(frame_len, "1-" __MODULE_STRING(8) "i");
3988 MODULE_PARM(ring_len, "1-" __MODULE_STRING(8) "i");
3989 MODULE_PARM(fifo_num, "1-" __MODULE_STRING(1) "i");
3990 MODULE_PARM(fifo_len, "1-" __MODULE_STRING(8) "i");
3991 MODULE_PARM(rx_prio, "1-" __MODULE_STRING(1) "i");
3992 MODULE_PARM(tx_prio, "1-" __MODULE_STRING(1) "i");
3993 MODULE_PARM(latency_timer, "1-" __MODULE_STRING(1) "i");
3994
3995 /*
3996 * Input Argument/s:
3997 * pdev - structure containing the PCI related information of the device.
3998 * pre - the List of PCI devices supported by the driver listed in s2io_tbl.
3999 * Return value:
4000 * returns '0' on success and negative on failure.
4001 * Description:
4002 * The function initializes an adapter identified by the pci_dec structure.
4003 * All OS related initialization including memory and device structure and
4004 * initlaization of the device private variable is done. Also the swapper
4005 * control register is initialized to enable read and write into the I/O
4006 * registers of the device.
4007 *
4008 */
4009 static int __devinit
4010 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4011 {
4012 nic_t *sp;
4013 struct net_device *dev;
4014 char *dev_name = "S2IO 10GE NIC";
4015 int i, j, ret;
4016 int dma_flag = FALSE;
4017 u32 mac_up, mac_down;
4018 u64 val64 = 0, tmp64 = 0;
4019 XENA_dev_config_t *bar0 = NULL;
4020 u16 subid;
4021 mac_info_t *mac_control;
4022 struct config_param *config;
4023
4024
4025 if ((ret = pci_enable_device(pdev))) {
4026 DBG_PRINT(ERR_DBG,
4027 "s2io_init_nic: pci_enable_device failed\n");
4028 return ret;
4029 }
4030
4031 if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
4032 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
4033 dma_flag = TRUE;
4034 if (pci_set_consistent_dma_mask
4035 (pdev, 0xffffffffffffffffULL)) {
4036 DBG_PRINT(ERR_DBG,
4037 "Unable to obtain 64bit DMA for \
4038 consistent allocations\n");
4039 pci_disable_device(pdev);
4040 return -ENOMEM;
4041 }
4042 } else if (!pci_set_dma_mask(pdev, 0xffffffffUL)) {
4043 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
4044 } else {
4045 pci_disable_device(pdev);
4046 return -ENOMEM;
4047 }
4048
4049 if (pci_request_regions(pdev, s2io_driver_name)) {
4050 DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
4051 pci_disable_device(pdev);
4052 return -ENODEV;
4053 }
4054
4055 dev = alloc_etherdev(sizeof(nic_t));
4056 if (dev == NULL) {
4057 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
4058 pci_disable_device(pdev);
4059 pci_release_regions(pdev);
4060 return -ENODEV;
4061 }
4062
4063 pci_set_master(pdev);
4064 pci_set_drvdata(pdev, dev);
4065 SET_MODULE_OWNER(dev);
4066 SET_NETDEV_DEV(dev, &pdev->dev);
4067
4068 /* Private member variable initialized to s2io NIC structure */
4069 sp = dev->priv;
4070 memset(sp, 0, sizeof(nic_t));
4071 sp->dev = dev;
4072 sp->pdev = pdev;
4073 sp->vendor_id = pdev->vendor;
4074 sp->device_id = pdev->device;
4075 sp->high_dma_flag = dma_flag;
4076 sp->irq = pdev->irq;
4077 sp->device_enabled_once = FALSE;
4078 strcpy(sp->name, dev_name);
4079
4080 /* Initialize some PCI/PCI-X fields of the NIC. */
4081 s2io_init_pci(sp);
4082
4083 /* Setting the device configuration parameters.
4084 * Most of these parameters can be specified by the user during
4085 * module insertion as they are module loadable parameters. If
4086 * these parameters are not not specified during load time, they
4087 * are initialized with default values.
4088 */
4089 mac_control = &sp->mac_control;
4090 config = &sp->config;
4091
4092 /* Tx side parameters. */
4093 config->TxFIFONum = fifo_num ? fifo_num : 1;
4094
4095 if (!fifo_len[0] && (fifo_num > 1)) {
4096 printk(KERN_ERR "Fifo Lens not specified for all FIFOs\n");
4097 goto init_failed;
4098 }
4099
4100 if (fifo_len[0]) {
4101 int cnt;
4102
4103 for (cnt = 0; fifo_len[cnt]; cnt++);
4104 if (fifo_num) {
4105 if (cnt < fifo_num) {
4106 printk(KERN_ERR
4107 "Fifo Lens not specified for ");
4108 printk(KERN_ERR "all FIFOs\n");
4109 goto init_failed;
4110 }
4111 }
4112 for (cnt = 0; cnt < config->TxFIFONum; cnt++) {
4113 config->TxCfg[cnt].FifoLen = fifo_len[cnt];
4114 config->TxCfg[cnt].FifoPriority = cnt;
4115 }
4116 } else {
4117 config->TxCfg[0].FifoLen = DEFAULT_FIFO_LEN;
4118 config->TxCfg[0].FifoPriority = 0;
4119 }
4120
4121 config->TxIntrType = TXD_INT_TYPE_UTILZ;
4122 for (i = 0; i < config->TxFIFONum; i++) {
4123 if (config->TxCfg[i].FifoLen < 65) {
4124 config->TxIntrType = TXD_INT_TYPE_PER_LIST;
4125 break;
4126 }
4127 }
4128
4129 config->TxCfg[0].fNoSnoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
4130 config->MaxTxDs = MAX_SKB_FRAGS;
4131 config->TxFlow = TRUE;
4132
4133 /* Rx side parameters. */
4134 config->RxRingNum = ring_num ? ring_num : 1;
4135
4136 if (ring_len[0]) {
4137 int cnt;
4138 for (cnt = 0; cnt < config->RxRingNum; cnt++) {
4139 config->RxCfg[cnt].NumRxd = ring_len[cnt];
4140 config->RxCfg[cnt].RingPriority = cnt;
4141 }
4142 } else {
4143 int id;
4144 if ((id = get_xena_rev_id(pdev)) == 1) {
4145 config->RxCfg[0].NumRxd = LARGE_RXD_CNT;
4146
4147 } else {
4148 config->RxCfg[0].NumRxd = SMALL_RXD_CNT;
4149 }
4150 config->RxCfg[0].RingPriority = 0;
4151 }
4152 config->RxCfg[0].RingOrg = RING_ORG_BUFF1;
4153 config->RxCfg[0].RxdThresh = DEFAULT_RXD_THRESHOLD;
4154 config->RxCfg[0].fNoSnoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
4155 config->RxCfg[0].RxD_BackOff_Interval = TBD;
4156 config->RxFlow = TRUE;
4157
4158 /* Miscellaneous parameters. */
4159 config->RxVLANEnable = TRUE;
4160 config->MTU = MAX_MTU_VLAN;
4161 config->JumboEnable = FALSE;
4162
4163 /* Setting Mac Control parameters */
4164 mac_control->txdl_len = MAX_SKB_FRAGS;
4165 mac_control->rmac_pause_time = 0;
4166
4167 /* Initialize Ring buffer parameters. */
4168 for (i = 0; i < config->RxRingNum; i++)
4169 atomic_set(&sp->rx_bufs_left[i], 0);
4170
4171 /* initialize the shared memory used by the NIC and the host */
4172 if (initSharedMem(sp)) {
4173 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
4174 dev->name);
4175 goto mem_alloc_failed;
4176 }
4177
4178 sp->bar0 = (caddr_t) ioremap(pci_resource_start(pdev, 0),
4179 pci_resource_len(pdev, 0));
4180 if (!sp->bar0) {
4181 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
4182 dev->name);
4183 goto bar0_remap_failed;
4184 }
4185
4186 sp->bar1 = (caddr_t) ioremap(pci_resource_start(pdev, 2),
4187 pci_resource_len(pdev, 2));
4188 if (!sp->bar1) {
4189 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
4190 dev->name);
4191 goto bar1_remap_failed;
4192 }
4193
4194 dev->irq = pdev->irq;
4195 dev->base_addr = (unsigned long) sp->bar0;
4196
4197 /* Initializing the BAR1 address as the start of the FIFO pointer. */
4198 for (j = 0; j < MAX_TX_FIFOS; j++) {
4199 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t *)
4200 (sp->bar1 + (j * 0x00020000));
4201 }
4202
4203 /* Driver entry points */
4204 dev->open = &s2io_open;
4205 dev->stop = &s2io_close;
4206 dev->hard_start_xmit = &s2io_xmit;
4207 dev->get_stats = &s2io_get_stats;
4208 dev->set_multicast_list = &s2io_set_multicast;
4209 dev->do_ioctl = &s2io_ioctl;
4210 dev->change_mtu = &s2io_change_mtu;
4211 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
4212
4213 /*
4214 * will use eth_mac_addr() for dev->set_mac_address
4215 * mac address will be set every time dev->open() is called
4216 */
4217 #ifdef CONFIG_S2IO_NAPI
4218 dev->poll = s2io_poll;
4219 dev->weight = 128; /* For now. */
4220 #endif
4221
4222 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
4223 if (sp->high_dma_flag == TRUE)
4224 dev->features |= NETIF_F_HIGHDMA;
4225 #ifdef NETIF_F_TSO
4226 dev->features |= NETIF_F_TSO;
4227 #endif
4228
4229 dev->tx_timeout = &s2io_tx_watchdog;
4230 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
4231 INIT_WORK(&sp->rst_timer_task,
4232 (void (*)(void *)) s2io_restart_nic, dev);
4233 INIT_WORK(&sp->set_link_task,
4234 (void (*)(void *)) s2io_set_link, sp);
4235
4236 if (register_netdev(dev)) {
4237 DBG_PRINT(ERR_DBG, "Device registration failed\n");
4238 goto register_failed;
4239 }
4240
4241 pci_save_state(sp->pdev, sp->config_space);
4242
4243 /* Setting swapper control on the NIC, for proper reset operation */
4244 if (s2io_set_swapper(sp)) {
4245 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
4246 dev->name);
4247 goto set_swap_failed;
4248 }
4249
4250 /* Fix for all "FFs" MAC address problems observed on Alpha platforms */
4251 FixMacAddress(sp);
4252 s2io_reset(sp);
4253
4254 /* Setting swapper control on the NIC, so the MAC address can be read.
4255 */
4256 if (s2io_set_swapper(sp)) {
4257 DBG_PRINT(ERR_DBG,
4258 "%s: S2IO: swapper settings are wrong\n",
4259 dev->name);
4260 goto set_swap_failed;
4261 }
4262
4263 /* MAC address initialization.
4264 * For now only one mac address will be read and used.
4265 */
4266 bar0 = (XENA_dev_config_t *) sp->bar0;
4267 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4268 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
4269 writeq(val64, &bar0->rmac_addr_cmd_mem);
4270 waitForCmdComplete(sp);
4271
4272 tmp64 = readq(&bar0->rmac_addr_data0_mem);
4273 mac_down = (u32) tmp64;
4274 mac_up = (u32) (tmp64 >> 32);
4275
4276 memset(sp->defMacAddr[0].mac_addr, 0, sizeof(ETH_ALEN));
4277
4278 sp->defMacAddr[0].mac_addr[3] = (u8) (mac_up);
4279 sp->defMacAddr[0].mac_addr[2] = (u8) (mac_up >> 8);
4280 sp->defMacAddr[0].mac_addr[1] = (u8) (mac_up >> 16);
4281 sp->defMacAddr[0].mac_addr[0] = (u8) (mac_up >> 24);
4282 sp->defMacAddr[0].mac_addr[5] = (u8) (mac_down >> 16);
4283 sp->defMacAddr[0].mac_addr[4] = (u8) (mac_down >> 24);
4284
4285 DBG_PRINT(INIT_DBG,
4286 "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
4287 sp->defMacAddr[0].mac_addr[0],
4288 sp->defMacAddr[0].mac_addr[1],
4289 sp->defMacAddr[0].mac_addr[2],
4290 sp->defMacAddr[0].mac_addr[3],
4291 sp->defMacAddr[0].mac_addr[4],
4292 sp->defMacAddr[0].mac_addr[5]);
4293
4294 /* Set the factory defined MAC address initially */
4295 dev->addr_len = ETH_ALEN;
4296 memcpy(dev->dev_addr, sp->defMacAddr, ETH_ALEN);
4297
4298 /* Initialize the tasklet status flag */
4299 atomic_set(&(sp->tasklet_status), 0);
4300
4301
4302 /* Initialize spinlocks */
4303 spin_lock_init(&sp->isr_lock);
4304 spin_lock_init(&sp->tx_lock);
4305
4306 /* SXE-002: Configure link and activity LED to init state
4307 * on driver load.
4308 */
4309 subid = sp->pdev->subsystem_device;
4310 if ((subid & 0xFF) >= 0x07) {
4311 val64 = readq(&bar0->gpio_control);
4312 val64 |= 0x0000800000000000ULL;
4313 writeq(val64, &bar0->gpio_control);
4314 val64 = 0x0411040400000000ULL;
4315 writeq(val64, (u64 *) ((u8 *) bar0 + 0x2700));
4316 val64 = readq(&bar0->gpio_control);
4317 }
4318
4319 /* Make Link state as off at this point, when the Link change
4320 * interrupt comes the state will be automatically changed to
4321 * the right state.
4322 */
4323 netif_carrier_off(dev);
4324 sp->last_link_state = LINK_DOWN;
4325
4326 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
4327
4328 return 0;
4329
4330 set_swap_failed:
4331 unregister_netdev(dev);
4332 register_failed:
4333 iounmap(sp->bar1);
4334 bar1_remap_failed:
4335 iounmap(sp->bar0);
4336 bar0_remap_failed:
4337 mem_alloc_failed:
4338 freeSharedMem(sp);
4339 init_failed:
4340 pci_disable_device(pdev);
4341 pci_release_regions(pdev);
4342 pci_set_drvdata(pdev, NULL);
4343 free_netdev(dev);
4344
4345 return -ENODEV;
4346 }
4347
4348 /*
4349 * Input Argument/s:
4350 * pdev - structure containing the PCI related information of the device.
4351 * Return value:
4352 * void
4353 * Description:
4354 * This function is called by the Pci subsystem to release a PCI device
4355 * and free up all resource held up by the device. This could be in response
4356 * to a Hot plug event or when the driver is to be removed from memory.
4357 */
4358 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
4359 {
4360 struct net_device *dev =
4361 (struct net_device *) pci_get_drvdata(pdev);
4362 nic_t *sp;
4363
4364 if (dev == NULL) {
4365 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
4366 return;
4367 }
4368 sp = dev->priv;
4369 freeSharedMem(sp);
4370 iounmap(sp->bar0);
4371 iounmap(sp->bar1);
4372 pci_disable_device(pdev);
4373 pci_release_regions(pdev);
4374 pci_set_drvdata(pdev, NULL);
4375
4376 unregister_netdev(dev);
4377
4378 free_netdev(dev);
4379 }
4380
4381 int __init s2io_starter(void)
4382 {
4383 return pci_module_init(&s2io_driver);
4384 }
4385
4386 void s2io_closer(void)
4387 {
4388 pci_unregister_driver(&s2io_driver);
4389 DBG_PRINT(INIT_DBG, "cleanup done\n");
4390 }
4391
4392 module_init(s2io_starter);
4393 module_exit(s2io_closer);
MOXA 2.6.9 from sdlinux-moxaart.tgz