2 * linux/arch/arm/mm/proc-xscale.S
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * MMU functions for the Intel XScale CPUs
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/procinfo.h>
27 #include <asm/pgtable.h>
28 #include <asm/pgtable-hwdef.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
34 #error "need to be revisited"
37 * This is the maximum size of an area which will be flushed. If the area
38 * is larger than this, then we flush the whole cache
40 #define MAX_AREA_SIZE 32768
43 * the cache line size of the I and D cache
45 #define CACHELINESIZE 32
48 * the size of the data cache
50 #define CACHESIZE 32768
53 * Virtual address used to allocate the cache when flushed
55 * This must be an address range which is _never_ used. It should
56 * apparently have a mapping in the corresponding page table for
57 * compatibility with future CPUs that _could_ require it. For instance we
60 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
61 * the 2 areas in alternance each time the clean_d_cache macro is used.
62 * Without this the XScale core exhibits cache eviction problems and no one
65 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
67 #define CLEAN_ADDR 0xfffe0000
70 * This macro is used to wait for a CP15 write and is needed
71 * when we have to ensure that the last operation to the co-pro
72 * was completed before continuing with operation.
75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
76 mov \rd, \rd @ wait for completion
77 sub pc, pc, #4 @ flush instruction pipeline
80 .macro cpwait_ret, lr, rd
81 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
82 sub pc, \lr, \rd, LSR #32 @ wait for completion and
83 @ flush instruction pipeline
87 * This macro cleans the entire dcache using line allocate.
88 * The main loop has been unrolled to reduce loop overhead.
89 * rd and rs are two scratch registers.
91 .macro clean_d_cache, rd, rs
94 eor \rd, \rd, #CACHESIZE
96 add \rs, \rd, #CACHESIZE
97 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 add \rd, \rd, #CACHELINESIZE
99 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 add \rd, \rd, #CACHELINESIZE
101 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
102 add \rd, \rd, #CACHELINESIZE
103 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
104 add \rd, \rd, #CACHELINESIZE
110 clean_addr: .word CLEAN_ADDR
115 * cpu_xscale_proc_init()
117 * Nothing too exciting at the moment
119 ENTRY(cpu_xscale_proc_init)
123 * cpu_xscale_proc_fin()
125 ENTRY(cpu_xscale_proc_fin)
127 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
129 bl xscale_flush_kern_cache_all @ clean caches
130 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
131 bic r0, r0, #0x1800 @ ...IZ...........
132 bic r0, r0, #0x0006 @ .............CA.
133 mcr p15, 0, r0, c1, c0, 0 @ disable caches
137 * cpu_xscale_reset(loc)
139 * Perform a soft reset of the system. Put the CPU into the
140 * same state as it would be if it had been reset, and branch
141 * to what would be the reset vector.
143 * loc: location to jump to for soft reset
145 * Beware PXA270 erratum E7.
148 ENTRY(cpu_xscale_reset)
149 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
150 msr cpsr_c, r1 @ reset CPSR
151 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
152 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
153 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
154 bic r1, r1, #0x0086 @ ........B....CA.
155 bic r1, r1, #0x3900 @ ..VIZ..S........
156 sub pc, pc, #4 @ flush pipeline
157 @ *** cache line aligned ***
158 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
159 bic r1, r1, #0x0001 @ ...............M
160 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
161 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
162 @ CAUTION: MMU turned off from this point. We count on the pipeline
163 @ already containing those two last instructions to survive.
164 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
168 * cpu_xscale_do_idle()
170 * Cause the processor to idle
172 * For now we do nothing but go to idle mode for every case
174 * XScale supports clock switching, but using idle mode support
175 * allows external hardware to react to system state changes.
179 ENTRY(cpu_xscale_do_idle)
181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
184 /* ================================= CACHE ================================ */
187 * flush_user_cache_all()
189 * Invalidate all cache entries in a particular address
192 ENTRY(xscale_flush_user_cache_all)
196 * flush_kern_cache_all()
198 * Clean and invalidate the entire cache.
200 ENTRY(xscale_flush_kern_cache_all)
206 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
207 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
211 * flush_user_cache_range(start, end, vm_flags)
213 * Invalidate a range of cache entries in the specified
216 * - start - start address (may not be aligned)
217 * - end - end address (exclusive, may not be aligned)
218 * - vma - vma_area_struct describing address space
221 ENTRY(xscale_flush_user_cache_range)
223 sub r3, r1, r0 @ calculate total size
224 cmp r3, #MAX_AREA_SIZE
225 bhs __flush_whole_cache
228 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
229 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
230 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
231 add r0, r0, #CACHELINESIZE
235 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
236 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
240 * coherent_kern_range(start, end)
242 * Ensure coherency between the Icache and the Dcache in the
243 * region described by start. If you have non-snooping
244 * Harvard caches, you need to implement this function.
246 * - start - virtual start address
247 * - end - virtual end address
249 * Note: single I-cache line invalidation isn't used here since
250 * it also trashes the mini I-cache used by JTAG debuggers.
252 ENTRY(xscale_coherent_kern_range)
253 bic r0, r0, #CACHELINESIZE - 1
254 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
255 add r0, r0, #CACHELINESIZE
259 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
260 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
264 * coherent_user_range(start, end)
266 * Ensure coherency between the Icache and the Dcache in the
267 * region described by start. If you have non-snooping
268 * Harvard caches, you need to implement this function.
270 * - start - virtual start address
271 * - end - virtual end address
273 ENTRY(xscale_coherent_user_range)
274 bic r0, r0, #CACHELINESIZE - 1
275 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
276 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
277 add r0, r0, #CACHELINESIZE
281 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
282 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
286 * flush_kern_dcache_page(void *page)
288 * Ensure no D cache aliasing occurs, either with itself or
291 * - addr - page aligned address
293 ENTRY(xscale_flush_kern_dcache_page)
295 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
297 add r0, r0, #CACHELINESIZE
301 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
302 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
306 * dma_inv_range(start, end)
308 * Invalidate (discard) the specified virtual address range.
309 * May not write back any entries. If 'start' or 'end'
310 * are not cache line aligned, those lines must be written
313 * - start - virtual start address
314 * - end - virtual end address
316 ENTRY(xscale_dma_inv_range)
317 tst r0, #CACHELINESIZE - 1
318 bic r0, r0, #CACHELINESIZE - 1
319 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
320 tst r1, #CACHELINESIZE - 1
321 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
322 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
323 add r0, r0, #CACHELINESIZE
326 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
330 * dma_clean_range(start, end)
332 * Clean the specified virtual address range.
334 * - start - virtual start address
335 * - end - virtual end address
337 ENTRY(xscale_dma_clean_range)
338 bic r0, r0, #CACHELINESIZE - 1
339 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
340 add r0, r0, #CACHELINESIZE
343 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
347 * dma_flush_range(start, end)
349 * Clean and invalidate the specified virtual address range.
351 * - start - virtual start address
352 * - end - virtual end address
354 ENTRY(xscale_dma_flush_range)
355 bic r0, r0, #CACHELINESIZE - 1
356 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
357 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
358 add r0, r0, #CACHELINESIZE
361 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
364 ENTRY(xscale_cache_fns)
365 .long xscale_flush_kern_cache_all
366 .long xscale_flush_user_cache_all
367 .long xscale_flush_user_cache_range
368 .long xscale_coherent_kern_range
369 .long xscale_coherent_user_range
370 .long xscale_flush_kern_dcache_page
371 .long xscale_dma_inv_range
372 .long xscale_dma_clean_range
373 .long xscale_dma_flush_range
376 * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
377 * clear the dirty bits, which means that if we invalidate a dirty line,
378 * the dirty data can still be written back to external memory later on.
380 * The recommended workaround is to always do a clean D-cache line before
381 * doing an invalidate D-cache line, so on the affected processors,
382 * dma_inv_range() is implemented as dma_flush_range().
384 * See erratum #25 of "Intel 80200 Processor Specification Update",
385 * revision January 22, 2003, available at:
386 * http://www.intel.com/design/iio/specupdt/273415.htm
388 ENTRY(xscale_80200_A0_A1_cache_fns)
389 .long xscale_flush_kern_cache_all
390 .long xscale_flush_user_cache_all
391 .long xscale_flush_user_cache_range
392 .long xscale_coherent_kern_range
393 .long xscale_coherent_user_range
394 .long xscale_flush_kern_dcache_page
395 .long xscale_dma_flush_range
396 .long xscale_dma_clean_range
397 .long xscale_dma_flush_range
399 ENTRY(cpu_xscale_dcache_clean_area)
400 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
401 add r0, r0, #CACHELINESIZE
402 subs r1, r1, #CACHELINESIZE
406 /* =============================== PageTable ============================== */
408 #define PTE_CACHE_WRITE_ALLOCATE 0
411 * cpu_xscale_switch_mm(pgd)
413 * Set the translation base pointer to be as described by pgd.
415 * pgd: new page tables
418 ENTRY(cpu_xscale_switch_mm)
420 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
421 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
422 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
423 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
427 * cpu_xscale_set_pte(ptep, pte)
429 * Set a PTE and flush it out
431 * Errata 40: must set memory to write-through for user read-only pages.
434 ENTRY(cpu_xscale_set_pte)
435 str r1, [r0], #-2048 @ linux version
438 orr r2, r2, #PTE_TYPE_EXT @ extended page
440 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
442 tst r3, #L_PTE_USER @ User?
443 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
445 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
446 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
447 @ combined with user -> user r/w
450 @ Handle the X bit. We want to set this bit for the minicache
451 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
452 @ and we have a writeable, cacheable region. If we ignore the
453 @ U and E bits, we can allow user space to use the minicache as
456 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
458 eor ip, r1, #L_PTE_CACHEABLE
459 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
460 #if PTE_CACHE_WRITE_ALLOCATE
461 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
462 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
464 orreq r2, r2, #PTE_EXT_TEX(1)
467 @ Erratum 40: The B bit must be cleared for a user read-only
470 @ B = B & ~(U & C & ~W)
472 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
473 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
474 biceq r2, r2, #PTE_BUFFERABLE
476 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
477 movne r2, #0 @ no -> fault
479 str r2, [r0] @ hardware version
481 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
482 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
492 .type __xscale_setup, #function
494 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
495 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
496 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
498 mov r0, #0 @ initially disallow access to CP0/CP1
500 mov r0, #1 @ Allow access to CP0
502 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
503 orr r0, r0, #1 << 13 @ Its undefined whether this
504 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
508 mrc p15, 0, r0, c1, c0, 0 @ get control register
512 .size __xscale_setup, . - __xscale_setup
516 * .RVI ZFRS BLDP WCAM
517 * ..11 1.01 .... .101
520 .type xscale_crval, #object
522 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
527 * Purpose : Function pointers used to access above functions - all calls
531 .type xscale_processor_functions, #object
532 ENTRY(xscale_processor_functions)
533 .word v5t_early_abort
534 .word cpu_xscale_proc_init
535 .word cpu_xscale_proc_fin
536 .word cpu_xscale_reset
537 .word cpu_xscale_do_idle
538 .word cpu_xscale_dcache_clean_area
539 .word cpu_xscale_switch_mm
540 .word cpu_xscale_set_pte
541 .size xscale_processor_functions, . - xscale_processor_functions
545 .type cpu_arch_name, #object
548 .size cpu_arch_name, . - cpu_arch_name
550 .type cpu_elf_name, #object
553 .size cpu_elf_name, . - cpu_elf_name
555 .type cpu_80200_A0_A1_name, #object
556 cpu_80200_A0_A1_name:
557 .asciz "XScale-80200 A0/A1"
558 .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
560 .type cpu_80200_name, #object
562 .asciz "XScale-80200"
563 .size cpu_80200_name, . - cpu_80200_name
565 .type cpu_80219_name, #object
567 .asciz "XScale-80219"
568 .size cpu_80219_name, . - cpu_80219_name
570 .type cpu_8032x_name, #object
572 .asciz "XScale-IOP8032x Family"
573 .size cpu_8032x_name, . - cpu_8032x_name
575 .type cpu_8033x_name, #object
577 .asciz "XScale-IOP8033x Family"
578 .size cpu_8033x_name, . - cpu_8033x_name
580 .type cpu_pxa250_name, #object
582 .asciz "XScale-PXA250"
583 .size cpu_pxa250_name, . - cpu_pxa250_name
585 .type cpu_pxa210_name, #object
587 .asciz "XScale-PXA210"
588 .size cpu_pxa210_name, . - cpu_pxa210_name
590 .type cpu_ixp42x_name, #object
592 .asciz "XScale-IXP42x Family"
593 .size cpu_ixp42x_name, . - cpu_ixp42x_name
595 .type cpu_ixp46x_name, #object
597 .asciz "XScale-IXP46x Family"
598 .size cpu_ixp46x_name, . - cpu_ixp46x_name
600 .type cpu_ixp2400_name, #object
602 .asciz "XScale-IXP2400"
603 .size cpu_ixp2400_name, . - cpu_ixp2400_name
605 .type cpu_ixp2800_name, #object
607 .asciz "XScale-IXP2800"
608 .size cpu_ixp2800_name, . - cpu_ixp2800_name
610 .type cpu_pxa255_name, #object
612 .asciz "XScale-PXA255"
613 .size cpu_pxa255_name, . - cpu_pxa255_name
615 .type cpu_pxa270_name, #object
617 .asciz "XScale-PXA270"
618 .size cpu_pxa270_name, . - cpu_pxa270_name
622 .section ".proc.info.init", #alloc, #execinstr
624 .type __80200_A0_A1_proc_info,#object
625 __80200_A0_A1_proc_info:
628 .long PMD_TYPE_SECT | \
629 PMD_SECT_BUFFERABLE | \
630 PMD_SECT_CACHEABLE | \
631 PMD_SECT_AP_WRITE | \
633 .long PMD_TYPE_SECT | \
634 PMD_SECT_AP_WRITE | \
639 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
641 .long xscale_processor_functions
643 .long xscale_mc_user_fns
644 .long xscale_80200_A0_A1_cache_fns
645 .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
647 .type __80200_proc_info,#object
651 .long PMD_TYPE_SECT | \
652 PMD_SECT_BUFFERABLE | \
653 PMD_SECT_CACHEABLE | \
654 PMD_SECT_AP_WRITE | \
656 .long PMD_TYPE_SECT | \
657 PMD_SECT_AP_WRITE | \
662 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
664 .long xscale_processor_functions
666 .long xscale_mc_user_fns
667 .long xscale_cache_fns
668 .size __80200_proc_info, . - __80200_proc_info
670 .type __80219_proc_info,#object
674 .long PMD_TYPE_SECT | \
675 PMD_SECT_BUFFERABLE | \
676 PMD_SECT_CACHEABLE | \
677 PMD_SECT_AP_WRITE | \
679 .long PMD_TYPE_SECT | \
680 PMD_SECT_AP_WRITE | \
685 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
687 .long xscale_processor_functions
689 .long xscale_mc_user_fns
690 .long xscale_cache_fns
691 .size __80219_proc_info, . - __80219_proc_info
693 .type __8032x_proc_info,#object
697 .long PMD_TYPE_SECT | \
698 PMD_SECT_BUFFERABLE | \
699 PMD_SECT_CACHEABLE | \
700 PMD_SECT_AP_WRITE | \
702 .long PMD_TYPE_SECT | \
703 PMD_SECT_AP_WRITE | \
708 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
710 .long xscale_processor_functions
712 .long xscale_mc_user_fns
713 .long xscale_cache_fns
714 .size __8032x_proc_info, . - __8032x_proc_info
716 .type __8033x_proc_info,#object
720 .long PMD_TYPE_SECT | \
721 PMD_SECT_BUFFERABLE | \
722 PMD_SECT_CACHEABLE | \
723 PMD_SECT_AP_WRITE | \
725 .long PMD_TYPE_SECT | \
726 PMD_SECT_AP_WRITE | \
731 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
733 .long xscale_processor_functions
735 .long xscale_mc_user_fns
736 .long xscale_cache_fns
737 .size __8033x_proc_info, . - __8033x_proc_info
739 .type __pxa250_proc_info,#object
743 .long PMD_TYPE_SECT | \
744 PMD_SECT_BUFFERABLE | \
745 PMD_SECT_CACHEABLE | \
746 PMD_SECT_AP_WRITE | \
748 .long PMD_TYPE_SECT | \
749 PMD_SECT_AP_WRITE | \
754 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
755 .long cpu_pxa250_name
756 .long xscale_processor_functions
758 .long xscale_mc_user_fns
759 .long xscale_cache_fns
760 .size __pxa250_proc_info, . - __pxa250_proc_info
762 .type __pxa210_proc_info,#object
766 .long PMD_TYPE_SECT | \
767 PMD_SECT_BUFFERABLE | \
768 PMD_SECT_CACHEABLE | \
769 PMD_SECT_AP_WRITE | \
771 .long PMD_TYPE_SECT | \
772 PMD_SECT_AP_WRITE | \
777 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
778 .long cpu_pxa210_name
779 .long xscale_processor_functions
781 .long xscale_mc_user_fns
782 .long xscale_cache_fns
783 .size __pxa210_proc_info, . - __pxa210_proc_info
785 .type __ixp2400_proc_info, #object
789 .long PMD_TYPE_SECT | \
790 PMD_SECT_BUFFERABLE | \
791 PMD_SECT_CACHEABLE | \
792 PMD_SECT_AP_WRITE | \
794 .long PMD_TYPE_SECT | \
795 PMD_SECT_AP_WRITE | \
800 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
801 .long cpu_ixp2400_name
802 .long xscale_processor_functions
804 .long xscale_mc_user_fns
805 .long xscale_cache_fns
806 .size __ixp2400_proc_info, . - __ixp2400_proc_info
808 .type __ixp2800_proc_info, #object
812 .long PMD_TYPE_SECT | \
813 PMD_SECT_BUFFERABLE | \
814 PMD_SECT_CACHEABLE | \
815 PMD_SECT_AP_WRITE | \
817 .long PMD_TYPE_SECT | \
818 PMD_SECT_AP_WRITE | \
823 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
824 .long cpu_ixp2800_name
825 .long xscale_processor_functions
827 .long xscale_mc_user_fns
828 .long xscale_cache_fns
829 .size __ixp2800_proc_info, . - __ixp2800_proc_info
831 .type __ixp42x_proc_info, #object
835 .long PMD_TYPE_SECT | \
836 PMD_SECT_BUFFERABLE | \
837 PMD_SECT_CACHEABLE | \
838 PMD_SECT_AP_WRITE | \
840 .long PMD_TYPE_SECT | \
841 PMD_SECT_AP_WRITE | \
846 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
847 .long cpu_ixp42x_name
848 .long xscale_processor_functions
850 .long xscale_mc_user_fns
851 .long xscale_cache_fns
852 .size __ixp42x_proc_info, . - __ixp42x_proc_info
854 .type __ixp46x_proc_info, #object
858 .long PMD_TYPE_SECT | \
859 PMD_SECT_BUFFERABLE | \
860 PMD_SECT_CACHEABLE | \
861 PMD_SECT_AP_WRITE | \
863 .long PMD_TYPE_SECT | \
864 PMD_SECT_AP_WRITE | \
869 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
870 .long cpu_ixp46x_name
871 .long xscale_processor_functions
873 .long xscale_mc_user_fns
874 .long xscale_cache_fns
875 .size __ixp46x_proc_info, . - __ixp46x_proc_info
877 .type __pxa255_proc_info,#object
881 .long PMD_TYPE_SECT | \
882 PMD_SECT_BUFFERABLE | \
883 PMD_SECT_CACHEABLE | \
884 PMD_SECT_AP_WRITE | \
886 .long PMD_TYPE_SECT | \
887 PMD_SECT_AP_WRITE | \
892 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
893 .long cpu_pxa255_name
894 .long xscale_processor_functions
896 .long xscale_mc_user_fns
897 .long xscale_cache_fns
898 .size __pxa255_proc_info, . - __pxa255_proc_info
900 .type __pxa270_proc_info,#object
904 .long PMD_TYPE_SECT | \
905 PMD_SECT_BUFFERABLE | \
906 PMD_SECT_CACHEABLE | \
907 PMD_SECT_AP_WRITE | \
909 .long PMD_TYPE_SECT | \
910 PMD_SECT_AP_WRITE | \
915 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_IWMMXT
916 .long cpu_pxa270_name
917 .long xscale_processor_functions
919 .long xscale_mc_user_fns
920 .long xscale_cache_fns
921 .size __pxa270_proc_info, . - __pxa270_proc_info