| blob | e5823a612fbb5e47020aae60e6d849e6397eb6f5 |
1 /*
2 * linux/arch/arm/mm/proc-xscale.S
3 *
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * MMU functions for the Intel XScale CPUs
13 *
14 * 2001 Aug 21:
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
17 *
18 * 2001 Sep 08:
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/procinfo.h>
27 #include <asm/pgtable.h>
28 #include <asm/pgtable-hwdef.h>
29 #include <asm/page.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
33 #ifndef CONFIG_MMU
34 #error "need to be revisited"
35 #endif
36 /*
37 * This is the maximum size of an area which will be flushed. If the area
38 * is larger than this, then we flush the whole cache
39 */
40 #define MAX_AREA_SIZE 32768
42 /*
43 * the cache line size of the I and D cache
44 */
45 #define CACHELINESIZE 32
47 /*
48 * the size of the data cache
49 */
50 #define CACHESIZE 32768
52 /*
53 * Virtual address used to allocate the cache when flushed
54 *
55 * This must be an address range which is _never_ used. It should
56 * apparently have a mapping in the corresponding page table for
57 * compatibility with future CPUs that _could_ require it. For instance we
58 * don't care.
59 *
60 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
61 * the 2 areas in alternance each time the clean_d_cache macro is used.
62 * Without this the XScale core exhibits cache eviction problems and no one
63 * knows why.
64 *
65 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
66 */
67 #define CLEAN_ADDR 0xfffe0000
69 /*
70 * This macro is used to wait for a CP15 write and is needed
71 * when we have to ensure that the last operation to the co-pro
72 * was completed before continuing with operation.
73 */
74 .macro cpwait, rd
75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
76 mov \rd, \rd @ wait for completion
77 sub pc, pc, #4 @ flush instruction pipeline
78 .endm
80 .macro cpwait_ret, lr, rd
81 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
82 sub pc, \lr, \rd, LSR #32 @ wait for completion and
83 @ flush instruction pipeline
84 .endm
86 /*
87 * This macro cleans the entire dcache using line allocate.
88 * The main loop has been unrolled to reduce loop overhead.
89 * rd and rs are two scratch registers.
90 */
91 .macro clean_d_cache, rd, rs
92 ldr \rs, =clean_addr
93 ldr \rd, [\rs]
94 eor \rd, \rd, #CACHESIZE
95 str \rd, [\rs]
96 add \rs, \rd, #CACHESIZE
97 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 add \rd, \rd, #CACHELINESIZE
99 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 add \rd, \rd, #CACHELINESIZE
101 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
102 add \rd, \rd, #CACHELINESIZE
103 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
104 add \rd, \rd, #CACHELINESIZE
105 teq \rd, \rs
106 bne 1b
107 .endm
109 .data
110 clean_addr: .word CLEAN_ADDR
112 .text
114 /*
115 * cpu_xscale_proc_init()
116 *
117 * Nothing too exciting at the moment
118 */
119 ENTRY(cpu_xscale_proc_init)
120 mov pc, lr
122 /*
123 * cpu_xscale_proc_fin()
124 */
125 ENTRY(cpu_xscale_proc_fin)
126 str lr, [sp, #-4]!
127 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
128 msr cpsr_c, r0
129 bl xscale_flush_kern_cache_all @ clean caches
130 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
131 bic r0, r0, #0x1800 @ ...IZ...........
132 bic r0, r0, #0x0006 @ .............CA.
133 mcr p15, 0, r0, c1, c0, 0 @ disable caches
134 ldr pc, [sp], #4
136 /*
137 * cpu_xscale_reset(loc)
138 *
139 * Perform a soft reset of the system. Put the CPU into the
140 * same state as it would be if it had been reset, and branch
141 * to what would be the reset vector.
142 *
143 * loc: location to jump to for soft reset
144 *
145 * Beware PXA270 erratum E7.
146 */
147 .align 5
148 ENTRY(cpu_xscale_reset)
149 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
150 msr cpsr_c, r1 @ reset CPSR
151 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
152 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
153 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
154 bic r1, r1, #0x0086 @ ........B....CA.
155 bic r1, r1, #0x3900 @ ..VIZ..S........
156 sub pc, pc, #4 @ flush pipeline
157 @ *** cache line aligned ***
158 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
159 bic r1, r1, #0x0001 @ ...............M
160 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
161 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
162 @ CAUTION: MMU turned off from this point. We count on the pipeline
163 @ already containing those two last instructions to survive.
164 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
165 mov pc, r0
167 /*
168 * cpu_xscale_do_idle()
169 *
170 * Cause the processor to idle
171 *
172 * For now we do nothing but go to idle mode for every case
173 *
174 * XScale supports clock switching, but using idle mode support
175 * allows external hardware to react to system state changes.
176 */
177 .align 5
179 ENTRY(cpu_xscale_do_idle)
180 mov r0, #1
181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
182 mov pc, lr
184 /* ================================= CACHE ================================ */
186 /*
187 * flush_user_cache_all()
188 *
189 * Invalidate all cache entries in a particular address
190 * space.
191 */
192 ENTRY(xscale_flush_user_cache_all)
193 /* FALLTHROUGH */
195 /*
196 * flush_kern_cache_all()
197 *
198 * Clean and invalidate the entire cache.
199 */
200 ENTRY(xscale_flush_kern_cache_all)
201 mov r2, #VM_EXEC
202 mov ip, #0
203 __flush_whole_cache:
204 clean_d_cache r0, r1
205 tst r2, #VM_EXEC
206 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
207 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
208 mov pc, lr
210 /*
211 * flush_user_cache_range(start, end, vm_flags)
212 *
213 * Invalidate a range of cache entries in the specified
214 * address space.
215 *
216 * - start - start address (may not be aligned)
217 * - end - end address (exclusive, may not be aligned)
218 * - vma - vma_area_struct describing address space
219 */
220 .align 5
221 ENTRY(xscale_flush_user_cache_range)
222 mov ip, #0
223 sub r3, r1, r0 @ calculate total size
224 cmp r3, #MAX_AREA_SIZE
225 bhs __flush_whole_cache
227 1: tst r2, #VM_EXEC
228 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
229 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
230 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
231 add r0, r0, #CACHELINESIZE
232 cmp r0, r1
233 blo 1b
234 tst r2, #VM_EXEC
235 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
236 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
237 mov pc, lr
239 /*
240 * coherent_kern_range(start, end)
241 *
242 * Ensure coherency between the Icache and the Dcache in the
243 * region described by start. If you have non-snooping
244 * Harvard caches, you need to implement this function.
245 *
246 * - start - virtual start address
247 * - end - virtual end address
248 *
249 * Note: single I-cache line invalidation isn't used here since
250 * it also trashes the mini I-cache used by JTAG debuggers.
251 */
252 ENTRY(xscale_coherent_kern_range)
253 bic r0, r0, #CACHELINESIZE - 1
254 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
255 add r0, r0, #CACHELINESIZE
256 cmp r0, r1
257 blo 1b
258 mov r0, #0
259 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
260 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
261 mov pc, lr
263 /*
264 * coherent_user_range(start, end)
265 *
266 * Ensure coherency between the Icache and the Dcache in the
267 * region described by start. If you have non-snooping
268 * Harvard caches, you need to implement this function.
269 *
270 * - start - virtual start address
271 * - end - virtual end address
272 */
273 ENTRY(xscale_coherent_user_range)
274 bic r0, r0, #CACHELINESIZE - 1
275 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
276 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
277 add r0, r0, #CACHELINESIZE
278 cmp r0, r1
279 blo 1b
280 mov r0, #0
281 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
282 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
283 mov pc, lr
285 /*
286 * flush_kern_dcache_page(void *page)
287 *
288 * Ensure no D cache aliasing occurs, either with itself or
289 * the I cache
290 *
291 * - addr - page aligned address
292 */
293 ENTRY(xscale_flush_kern_dcache_page)
294 add r1, r0, #PAGE_SZ
295 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
297 add r0, r0, #CACHELINESIZE
298 cmp r0, r1
299 blo 1b
300 mov r0, #0
301 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
302 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
303 mov pc, lr
305 /*
306 * dma_inv_range(start, end)
307 *
308 * Invalidate (discard) the specified virtual address range.
309 * May not write back any entries. If 'start' or 'end'
310 * are not cache line aligned, those lines must be written
311 * back.
312 *
313 * - start - virtual start address
314 * - end - virtual end address
315 */
316 ENTRY(xscale_dma_inv_range)
317 tst r0, #CACHELINESIZE - 1
318 bic r0, r0, #CACHELINESIZE - 1
319 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
320 tst r1, #CACHELINESIZE - 1
321 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
322 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
323 add r0, r0, #CACHELINESIZE
324 cmp r0, r1
325 blo 1b
326 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
327 mov pc, lr
329 /*
330 * dma_clean_range(start, end)
331 *
332 * Clean the specified virtual address range.
333 *
334 * - start - virtual start address
335 * - end - virtual end address
336 */
337 ENTRY(xscale_dma_clean_range)
338 bic r0, r0, #CACHELINESIZE - 1
339 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
340 add r0, r0, #CACHELINESIZE
341 cmp r0, r1
342 blo 1b
343 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
344 mov pc, lr
346 /*
347 * dma_flush_range(start, end)
348 *
349 * Clean and invalidate the specified virtual address range.
350 *
351 * - start - virtual start address
352 * - end - virtual end address
353 */
354 ENTRY(xscale_dma_flush_range)
355 bic r0, r0, #CACHELINESIZE - 1
356 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
357 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
358 add r0, r0, #CACHELINESIZE
359 cmp r0, r1
360 blo 1b
361 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
362 mov pc, lr
364 ENTRY(xscale_cache_fns)
365 .long xscale_flush_kern_cache_all
366 .long xscale_flush_user_cache_all
367 .long xscale_flush_user_cache_range
368 .long xscale_coherent_kern_range
369 .long xscale_coherent_user_range
370 .long xscale_flush_kern_dcache_page
371 .long xscale_dma_inv_range
372 .long xscale_dma_clean_range
373 .long xscale_dma_flush_range
375 /*
376 * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
377 * clear the dirty bits, which means that if we invalidate a dirty line,
378 * the dirty data can still be written back to external memory later on.
379 *
380 * The recommended workaround is to always do a clean D-cache line before
381 * doing an invalidate D-cache line, so on the affected processors,
382 * dma_inv_range() is implemented as dma_flush_range().
383 *
384 * See erratum #25 of "Intel 80200 Processor Specification Update",
385 * revision January 22, 2003, available at:
386 * http://www.intel.com/design/iio/specupdt/273415.htm
387 */
388 ENTRY(xscale_80200_A0_A1_cache_fns)
389 .long xscale_flush_kern_cache_all
390 .long xscale_flush_user_cache_all
391 .long xscale_flush_user_cache_range
392 .long xscale_coherent_kern_range
393 .long xscale_coherent_user_range
394 .long xscale_flush_kern_dcache_page
395 .long xscale_dma_flush_range
396 .long xscale_dma_clean_range
397 .long xscale_dma_flush_range
399 ENTRY(cpu_xscale_dcache_clean_area)
400 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
401 add r0, r0, #CACHELINESIZE
402 subs r1, r1, #CACHELINESIZE
403 bhi 1b
404 mov pc, lr
406 /* =============================== PageTable ============================== */
408 #define PTE_CACHE_WRITE_ALLOCATE 0
410 /*
411 * cpu_xscale_switch_mm(pgd)
412 *
413 * Set the translation base pointer to be as described by pgd.
414 *
415 * pgd: new page tables
416 */
417 .align 5
418 ENTRY(cpu_xscale_switch_mm)
419 clean_d_cache r1, r2
420 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
421 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
422 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
423 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
424 cpwait_ret lr, ip
426 /*
427 * cpu_xscale_set_pte(ptep, pte)
428 *
429 * Set a PTE and flush it out
430 *
431 * Errata 40: must set memory to write-through for user read-only pages.
432 */
433 .align 5
434 ENTRY(cpu_xscale_set_pte)
435 str r1, [r0], #-2048 @ linux version
437 bic r2, r1, #0xff0
438 orr r2, r2, #PTE_TYPE_EXT @ extended page
440 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
442 tst r3, #L_PTE_USER @ User?
443 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
445 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
446 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
447 @ combined with user -> user r/w
449 @
450 @ Handle the X bit. We want to set this bit for the minicache
451 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
452 @ and we have a writeable, cacheable region. If we ignore the
453 @ U and E bits, we can allow user space to use the minicache as
454 @ well.
455 @
456 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
457 @
458 eor ip, r1, #L_PTE_CACHEABLE
459 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
460 #if PTE_CACHE_WRITE_ALLOCATE
461 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
462 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
463 #endif
464 orreq r2, r2, #PTE_EXT_TEX(1)
466 @
467 @ Erratum 40: The B bit must be cleared for a user read-only
468 @ cacheable page.
469 @
470 @ B = B & ~(U & C & ~W)
471 @
472 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
473 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
474 biceq r2, r2, #PTE_BUFFERABLE
476 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
477 movne r2, #0 @ no -> fault
479 str r2, [r0] @ hardware version
480 mov ip, #0
481 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
482 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
483 mov pc, lr
486 .ltorg
488 .align
490 __INIT
492 .type __xscale_setup, #function
493 __xscale_setup:
494 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
495 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
496 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
497 #ifdef CONFIG_IWMMXT
498 mov r0, #0 @ initially disallow access to CP0/CP1
499 #else
500 mov r0, #1 @ Allow access to CP0
501 #endif
502 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
503 orr r0, r0, #1 << 13 @ Its undefined whether this
504 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
506 adr r5, xscale_crval
507 ldmia r5, {r5, r6}
508 mrc p15, 0, r0, c1, c0, 0 @ get control register
509 bic r0, r0, r5
510 orr r0, r0, r6
511 mov pc, lr
512 .size __xscale_setup, . - __xscale_setup
514 /*
515 * R
516 * .RVI ZFRS BLDP WCAM
517 * ..11 1.01 .... .101
518 *
519 */
520 .type xscale_crval, #object
521 xscale_crval:
522 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
524 __INITDATA
526 /*
527 * Purpose : Function pointers used to access above functions - all calls
528 * come through these
529 */
531 .type xscale_processor_functions, #object
532 ENTRY(xscale_processor_functions)
533 .word v5t_early_abort
534 .word cpu_xscale_proc_init
535 .word cpu_xscale_proc_fin
536 .word cpu_xscale_reset
537 .word cpu_xscale_do_idle
538 .word cpu_xscale_dcache_clean_area
539 .word cpu_xscale_switch_mm
540 .word cpu_xscale_set_pte
541 .size xscale_processor_functions, . - xscale_processor_functions
543 .section ".rodata"
545 .type cpu_arch_name, #object
546 cpu_arch_name:
547 .asciz "armv5te"
548 .size cpu_arch_name, . - cpu_arch_name
550 .type cpu_elf_name, #object
551 cpu_elf_name:
552 .asciz "v5"
553 .size cpu_elf_name, . - cpu_elf_name
555 .type cpu_80200_A0_A1_name, #object
556 cpu_80200_A0_A1_name:
557 .asciz "XScale-80200 A0/A1"
558 .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
560 .type cpu_80200_name, #object
561 cpu_80200_name:
562 .asciz "XScale-80200"
563 .size cpu_80200_name, . - cpu_80200_name
565 .type cpu_80219_name, #object
566 cpu_80219_name:
567 .asciz "XScale-80219"
568 .size cpu_80219_name, . - cpu_80219_name
570 .type cpu_8032x_name, #object
571 cpu_8032x_name:
572 .asciz "XScale-IOP8032x Family"
573 .size cpu_8032x_name, . - cpu_8032x_name
575 .type cpu_8033x_name, #object
576 cpu_8033x_name:
577 .asciz "XScale-IOP8033x Family"
578 .size cpu_8033x_name, . - cpu_8033x_name
580 .type cpu_pxa250_name, #object
581 cpu_pxa250_name:
582 .asciz "XScale-PXA250"
583 .size cpu_pxa250_name, . - cpu_pxa250_name
585 .type cpu_pxa210_name, #object
586 cpu_pxa210_name:
587 .asciz "XScale-PXA210"
588 .size cpu_pxa210_name, . - cpu_pxa210_name
590 .type cpu_ixp42x_name, #object
591 cpu_ixp42x_name:
592 .asciz "XScale-IXP42x Family"
593 .size cpu_ixp42x_name, . - cpu_ixp42x_name
595 .type cpu_ixp46x_name, #object
596 cpu_ixp46x_name:
597 .asciz "XScale-IXP46x Family"
598 .size cpu_ixp46x_name, . - cpu_ixp46x_name
600 .type cpu_ixp2400_name, #object
601 cpu_ixp2400_name:
602 .asciz "XScale-IXP2400"
603 .size cpu_ixp2400_name, . - cpu_ixp2400_name
605 .type cpu_ixp2800_name, #object
606 cpu_ixp2800_name:
607 .asciz "XScale-IXP2800"
608 .size cpu_ixp2800_name, . - cpu_ixp2800_name
610 .type cpu_pxa255_name, #object
611 cpu_pxa255_name:
612 .asciz "XScale-PXA255"
613 .size cpu_pxa255_name, . - cpu_pxa255_name
615 .type cpu_pxa270_name, #object
616 cpu_pxa270_name:
617 .asciz "XScale-PXA270"
618 .size cpu_pxa270_name, . - cpu_pxa270_name
620 .align
622 .section ".proc.info.init", #alloc, #execinstr
624 .type __80200_A0_A1_proc_info,#object
625 __80200_A0_A1_proc_info:
626 .long 0x69052000
627 .long 0xfffffffe
628 .long PMD_TYPE_SECT | \
629 PMD_SECT_BUFFERABLE | \
630 PMD_SECT_CACHEABLE | \
631 PMD_SECT_AP_WRITE | \
632 PMD_SECT_AP_READ
633 .long PMD_TYPE_SECT | \
634 PMD_SECT_AP_WRITE | \
635 PMD_SECT_AP_READ
636 b __xscale_setup
637 .long cpu_arch_name
638 .long cpu_elf_name
639 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
640 .long cpu_80200_name
641 .long xscale_processor_functions
642 .long v4wbi_tlb_fns
643 .long xscale_mc_user_fns
644 .long xscale_80200_A0_A1_cache_fns
645 .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
647 .type __80200_proc_info,#object
648 __80200_proc_info:
649 .long 0x69052000
650 .long 0xfffffff0
651 .long PMD_TYPE_SECT | \
652 PMD_SECT_BUFFERABLE | \
653 PMD_SECT_CACHEABLE | \
654 PMD_SECT_AP_WRITE | \
655 PMD_SECT_AP_READ
656 .long PMD_TYPE_SECT | \
657 PMD_SECT_AP_WRITE | \
658 PMD_SECT_AP_READ
659 b __xscale_setup
660 .long cpu_arch_name
661 .long cpu_elf_name
662 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
663 .long cpu_80200_name
664 .long xscale_processor_functions
665 .long v4wbi_tlb_fns
666 .long xscale_mc_user_fns
667 .long xscale_cache_fns
668 .size __80200_proc_info, . - __80200_proc_info
670 .type __80219_proc_info,#object
671 __80219_proc_info:
672 .long 0x69052e20
673 .long 0xffffffe0
674 .long PMD_TYPE_SECT | \
675 PMD_SECT_BUFFERABLE | \
676 PMD_SECT_CACHEABLE | \
677 PMD_SECT_AP_WRITE | \
678 PMD_SECT_AP_READ
679 .long PMD_TYPE_SECT | \
680 PMD_SECT_AP_WRITE | \
681 PMD_SECT_AP_READ
682 b __xscale_setup
683 .long cpu_arch_name
684 .long cpu_elf_name
685 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
686 .long cpu_80219_name
687 .long xscale_processor_functions
688 .long v4wbi_tlb_fns
689 .long xscale_mc_user_fns
690 .long xscale_cache_fns
691 .size __80219_proc_info, . - __80219_proc_info
693 .type __8032x_proc_info,#object
694 __8032x_proc_info:
695 .long 0x69052420
696 .long 0xfffff7e0
697 .long PMD_TYPE_SECT | \
698 PMD_SECT_BUFFERABLE | \
699 PMD_SECT_CACHEABLE | \
700 PMD_SECT_AP_WRITE | \
701 PMD_SECT_AP_READ
702 .long PMD_TYPE_SECT | \
703 PMD_SECT_AP_WRITE | \
704 PMD_SECT_AP_READ
705 b __xscale_setup
706 .long cpu_arch_name
707 .long cpu_elf_name
708 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
709 .long cpu_8032x_name
710 .long xscale_processor_functions
711 .long v4wbi_tlb_fns
712 .long xscale_mc_user_fns
713 .long xscale_cache_fns
714 .size __8032x_proc_info, . - __8032x_proc_info
716 .type __8033x_proc_info,#object
717 __8033x_proc_info:
718 .long 0x69054010
719 .long 0xffffff30
720 .long PMD_TYPE_SECT | \
721 PMD_SECT_BUFFERABLE | \
722 PMD_SECT_CACHEABLE | \
723 PMD_SECT_AP_WRITE | \
724 PMD_SECT_AP_READ
725 .long PMD_TYPE_SECT | \
726 PMD_SECT_AP_WRITE | \
727 PMD_SECT_AP_READ
728 b __xscale_setup
729 .long cpu_arch_name
730 .long cpu_elf_name
731 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
732 .long cpu_8033x_name
733 .long xscale_processor_functions
734 .long v4wbi_tlb_fns
735 .long xscale_mc_user_fns
736 .long xscale_cache_fns
737 .size __8033x_proc_info, . - __8033x_proc_info
739 .type __pxa250_proc_info,#object
740 __pxa250_proc_info:
741 .long 0x69052100
742 .long 0xfffff7f0
743 .long PMD_TYPE_SECT | \
744 PMD_SECT_BUFFERABLE | \
745 PMD_SECT_CACHEABLE | \
746 PMD_SECT_AP_WRITE | \
747 PMD_SECT_AP_READ
748 .long PMD_TYPE_SECT | \
749 PMD_SECT_AP_WRITE | \
750 PMD_SECT_AP_READ
751 b __xscale_setup
752 .long cpu_arch_name
753 .long cpu_elf_name
754 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
755 .long cpu_pxa250_name
756 .long xscale_processor_functions
757 .long v4wbi_tlb_fns
758 .long xscale_mc_user_fns
759 .long xscale_cache_fns
760 .size __pxa250_proc_info, . - __pxa250_proc_info
762 .type __pxa210_proc_info,#object
763 __pxa210_proc_info:
764 .long 0x69052120
765 .long 0xfffff3f0
766 .long PMD_TYPE_SECT | \
767 PMD_SECT_BUFFERABLE | \
768 PMD_SECT_CACHEABLE | \
769 PMD_SECT_AP_WRITE | \
770 PMD_SECT_AP_READ
771 .long PMD_TYPE_SECT | \
772 PMD_SECT_AP_WRITE | \
773 PMD_SECT_AP_READ
774 b __xscale_setup
775 .long cpu_arch_name
776 .long cpu_elf_name
777 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
778 .long cpu_pxa210_name
779 .long xscale_processor_functions
780 .long v4wbi_tlb_fns
781 .long xscale_mc_user_fns
782 .long xscale_cache_fns
783 .size __pxa210_proc_info, . - __pxa210_proc_info
785 .type __ixp2400_proc_info, #object
786 __ixp2400_proc_info:
787 .long 0x69054190
788 .long 0xfffffff0
789 .long PMD_TYPE_SECT | \
790 PMD_SECT_BUFFERABLE | \
791 PMD_SECT_CACHEABLE | \
792 PMD_SECT_AP_WRITE | \
793 PMD_SECT_AP_READ
794 .long PMD_TYPE_SECT | \
795 PMD_SECT_AP_WRITE | \
796 PMD_SECT_AP_READ
797 b __xscale_setup
798 .long cpu_arch_name
799 .long cpu_elf_name
800 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
801 .long cpu_ixp2400_name
802 .long xscale_processor_functions
803 .long v4wbi_tlb_fns
804 .long xscale_mc_user_fns
805 .long xscale_cache_fns
806 .size __ixp2400_proc_info, . - __ixp2400_proc_info
808 .type __ixp2800_proc_info, #object
809 __ixp2800_proc_info:
810 .long 0x690541a0
811 .long 0xfffffff0
812 .long PMD_TYPE_SECT | \
813 PMD_SECT_BUFFERABLE | \
814 PMD_SECT_CACHEABLE | \
815 PMD_SECT_AP_WRITE | \
816 PMD_SECT_AP_READ
817 .long PMD_TYPE_SECT | \
818 PMD_SECT_AP_WRITE | \
819 PMD_SECT_AP_READ
820 b __xscale_setup
821 .long cpu_arch_name
822 .long cpu_elf_name
823 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
824 .long cpu_ixp2800_name
825 .long xscale_processor_functions
826 .long v4wbi_tlb_fns
827 .long xscale_mc_user_fns
828 .long xscale_cache_fns
829 .size __ixp2800_proc_info, . - __ixp2800_proc_info
831 .type __ixp42x_proc_info, #object
832 __ixp42x_proc_info:
833 .long 0x690541c0
834 .long 0xffffffc0
835 .long PMD_TYPE_SECT | \
836 PMD_SECT_BUFFERABLE | \
837 PMD_SECT_CACHEABLE | \
838 PMD_SECT_AP_WRITE | \
839 PMD_SECT_AP_READ
840 .long PMD_TYPE_SECT | \
841 PMD_SECT_AP_WRITE | \
842 PMD_SECT_AP_READ
843 b __xscale_setup
844 .long cpu_arch_name
845 .long cpu_elf_name
846 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
847 .long cpu_ixp42x_name
848 .long xscale_processor_functions
849 .long v4wbi_tlb_fns
850 .long xscale_mc_user_fns
851 .long xscale_cache_fns
852 .size __ixp42x_proc_info, . - __ixp42x_proc_info
854 .type __ixp46x_proc_info, #object
855 __ixp46x_proc_info:
856 .long 0x69054200
857 .long 0xffffff00
858 .long PMD_TYPE_SECT | \
859 PMD_SECT_BUFFERABLE | \
860 PMD_SECT_CACHEABLE | \
861 PMD_SECT_AP_WRITE | \
862 PMD_SECT_AP_READ
863 .long PMD_TYPE_SECT | \
864 PMD_SECT_AP_WRITE | \
865 PMD_SECT_AP_READ
866 b __xscale_setup
867 .long cpu_arch_name
868 .long cpu_elf_name
869 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
870 .long cpu_ixp46x_name
871 .long xscale_processor_functions
872 .long v4wbi_tlb_fns
873 .long xscale_mc_user_fns
874 .long xscale_cache_fns
875 .size __ixp46x_proc_info, . - __ixp46x_proc_info
877 .type __pxa255_proc_info,#object
878 __pxa255_proc_info:
879 .long 0x69052d00
880 .long 0xfffffff0
881 .long PMD_TYPE_SECT | \
882 PMD_SECT_BUFFERABLE | \
883 PMD_SECT_CACHEABLE | \
884 PMD_SECT_AP_WRITE | \
885 PMD_SECT_AP_READ
886 .long PMD_TYPE_SECT | \
887 PMD_SECT_AP_WRITE | \
888 PMD_SECT_AP_READ
889 b __xscale_setup
890 .long cpu_arch_name
891 .long cpu_elf_name
892 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
893 .long cpu_pxa255_name
894 .long xscale_processor_functions
895 .long v4wbi_tlb_fns
896 .long xscale_mc_user_fns
897 .long xscale_cache_fns
898 .size __pxa255_proc_info, . - __pxa255_proc_info
900 .type __pxa270_proc_info,#object
901 __pxa270_proc_info:
902 .long 0x69054110
903 .long 0xfffffff0
904 .long PMD_TYPE_SECT | \
905 PMD_SECT_BUFFERABLE | \
906 PMD_SECT_CACHEABLE | \
907 PMD_SECT_AP_WRITE | \
908 PMD_SECT_AP_READ
909 .long PMD_TYPE_SECT | \
910 PMD_SECT_AP_WRITE | \
911 PMD_SECT_AP_READ
912 b __xscale_setup
913 .long cpu_arch_name
914 .long cpu_elf_name
915 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_IWMMXT
916 .long cpu_pxa270_name
917 .long xscale_processor_functions
918 .long v4wbi_tlb_fns
919 .long xscale_mc_user_fns
920 .long xscale_cache_fns
921 .size __pxa270_proc_info, . - __pxa270_proc_info