5 * We need the APIC definitions automatically as part of 'smp.h'
7 #include <linux/config.h>
8 #ifdef CONFIG_X86_LOCAL_APIC
10 #include <asm/fixmap.h>
11 #include <asm/i82489.h>
12 #include <asm/bitops.h>
19 #include <linux/tasks.h>
20 #include <linux/ptrace.h>
23 * Support definitions for SMP machines following the intel multiprocessing
28 * This tag identifies where the SMP configuration
32 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
34 struct intel_mp_floating
36 char mpf_signature
[4]; /* "_MP_" */
37 unsigned long mpf_physptr
; /* Configuration table address */
38 unsigned char mpf_length
; /* Our length (paragraphs) */
39 unsigned char mpf_specification
;/* Specification version */
40 unsigned char mpf_checksum
; /* Checksum (makes sum 0) */
41 unsigned char mpf_feature1
; /* Standard or configuration ? */
42 unsigned char mpf_feature2
; /* Bit7 set for IMCR|PIC */
43 unsigned char mpf_feature3
; /* Unused (0) */
44 unsigned char mpf_feature4
; /* Unused (0) */
45 unsigned char mpf_feature5
; /* Unused (0) */
48 struct mp_config_table
50 char mpc_signature
[4];
51 #define MPC_SIGNATURE "PCMP"
52 unsigned short mpc_length
; /* Size of table */
53 char mpc_spec
; /* 0x01 */
56 char mpc_productid
[12];
57 unsigned long mpc_oemptr
; /* 0 if not present */
58 unsigned short mpc_oemsize
; /* 0 if not present */
59 unsigned short mpc_oemcount
;
60 unsigned long mpc_lapic
; /* APIC address */
61 unsigned long reserved
;
64 /* Followed by entries */
66 #define MP_PROCESSOR 0
72 struct mpc_config_processor
74 unsigned char mpc_type
;
75 unsigned char mpc_apicid
; /* Local APIC number */
76 unsigned char mpc_apicver
; /* Its versions */
77 unsigned char mpc_cpuflag
;
78 #define CPU_ENABLED 1 /* Processor is available */
79 #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
80 unsigned long mpc_cpufeature
;
81 #define CPU_STEPPING_MASK 0x0F
82 #define CPU_MODEL_MASK 0xF0
83 #define CPU_FAMILY_MASK 0xF00
84 unsigned long mpc_featureflag
; /* CPUID feature value */
85 unsigned long mpc_reserved
[2];
90 unsigned char mpc_type
;
91 unsigned char mpc_busid
;
92 unsigned char mpc_bustype
[6] __attribute((packed
));
95 #define BUSTYPE_EISA "EISA"
96 #define BUSTYPE_ISA "ISA"
97 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */
98 #define BUSTYPE_MCA "MCA"
99 #define BUSTYPE_VL "VL" /* Local bus */
100 #define BUSTYPE_PCI "PCI"
101 #define BUSTYPE_PCMCIA "PCMCIA"
103 /* We don't understand the others */
105 struct mpc_config_ioapic
107 unsigned char mpc_type
;
108 unsigned char mpc_apicid
;
109 unsigned char mpc_apicver
;
110 unsigned char mpc_flags
;
111 #define MPC_APIC_USABLE 0x01
112 unsigned long mpc_apicaddr
;
115 struct mpc_config_intsrc
117 unsigned char mpc_type
;
118 unsigned char mpc_irqtype
;
119 unsigned short mpc_irqflag
;
120 unsigned char mpc_srcbus
;
121 unsigned char mpc_srcbusirq
;
122 unsigned char mpc_dstapic
;
123 unsigned char mpc_dstirq
;
126 #define MP_INT_VECTORED 0
129 #define MP_INT_EXTINT 3
131 #define MP_IRQDIR_DEFAULT 0
132 #define MP_IRQDIR_HIGH 1
133 #define MP_IRQDIR_LOW 3
136 struct mpc_config_intlocal
138 unsigned char mpc_type
;
139 unsigned char mpc_irqtype
;
140 unsigned short mpc_irqflag
;
141 unsigned char mpc_srcbusid
;
142 unsigned char mpc_srcbusirq
;
143 unsigned char mpc_destapic
;
144 #define MP_APIC_ALL 0xFF
145 unsigned char mpc_destapiclint
;
150 * Default configurations
152 * 1 2 CPU ISA 82489DX
153 * 2 2 CPU EISA 82489DX no IRQ 8 or timer chaining
154 * 3 2 CPU EISA 82489DX
155 * 4 2 CPU MCA 82489DX
162 * Private routines/data
165 extern int smp_found_config
;
166 extern void init_smp_config(void);
167 extern unsigned long smp_alloc_memory(unsigned long mem_base
);
168 extern unsigned char boot_cpu_id
;
169 extern unsigned long cpu_present_map
;
170 extern unsigned long cpu_online_map
;
171 extern volatile int cpu_number_map
[NR_CPUS
];
172 extern volatile unsigned long smp_invalidate_needed
;
173 extern void smp_flush_tlb(void);
175 extern volatile unsigned long cpu_callin_map
[NR_CPUS
];
176 extern void smp_message_irq(int cpl
, void *dev_id
, struct pt_regs
*regs
);
177 extern void smp_send_reschedule(int cpu
);
178 extern unsigned long ipi_count
;
179 extern void smp_invalidate_rcv(void); /* Process an NMI */
180 extern void smp_local_timer_interrupt(struct pt_regs
* regs
);
181 extern void (*mtrr_hook
) (void);
182 extern void setup_APIC_clock (void);
183 extern volatile int __cpu_logical_map
[NR_CPUS
];
184 extern inline int cpu_logical_map(int cpu
)
186 return __cpu_logical_map
[cpu
];
191 * General functions that each host system must provide.
194 extern void smp_callin(void);
195 extern void smp_boot_cpus(void);
196 extern void smp_store_cpu_info(int id
); /* Store per CPU info (like the initial udelay numbers */
199 * This function is needed by all SMP systems. It must _always_ be valid
200 * from the initial startup. We map APIC_BASE very early in page_setup(),
201 * so this is correct in the x86 case.
204 #define smp_processor_id() (current->processor)
206 extern __inline
int hard_smp_processor_id(void)
208 /* we don't want to mark this access volatile - bad code generation */
209 return GET_APIC_ID(*(unsigned long *)(APIC_BASE
+APIC_ID
));
212 #endif /* !ASSEMBLY */
214 #define NO_PROC_ID 0xFF /* No processor magic marker */
217 * This magic constant controls our willingness to transfer
218 * a process across CPUs. Such a transfer incurs misses on the L1
219 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
220 * gut feeling is this will vary by board in value. For a board
221 * with separate L2 cache it probably depends also on the RSS, and
222 * for a board with shared L2 cache it ought to decay fast as other
226 #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */