include/asm-i386/smp.h

   1 #ifndef __ASM_SMP_H
   2 #define __ASM_SMP_H
   3
   4 /*
   5  * We need the APIC definitions automatically as part of 'smp.h'
   6  */
   7 #include <linux/config.h>
   8 #ifdef CONFIG_X86_LOCAL_APIC
   9 #ifndef ASSEMBLY
  10 #include <asm/fixmap.h>
  11 #include <asm/i82489.h>
  12 #include <asm/bitops.h>
  13 #endif
  14 #endif
  15
  16 #ifdef __SMP__
  17 #ifndef ASSEMBLY
  18
  19 #include <linux/tasks.h>
  20 #include <linux/ptrace.h>
  21
  22 /*
  23  *      Support definitions for SMP machines following the intel multiprocessing
  24  *      specification
  25  */
  26
  27 /*
  28  *      This tag identifies where the SMP configuration
  29  *      information is.
  30  */
  31
  32 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
  33
  34 struct intel_mp_floating
  35 {
  36         char mpf_signature[4];          /* "_MP_"                       */
  37         unsigned long mpf_physptr;      /* Configuration table address  */
  38         unsigned char mpf_length;       /* Our length (paragraphs)      */
  39         unsigned char mpf_specification;/* Specification version        */
  40         unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
  41         unsigned char mpf_feature1;     /* Standard or configuration ?  */
  42         unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
  43         unsigned char mpf_feature3;     /* Unused (0)                   */
  44         unsigned char mpf_feature4;     /* Unused (0)                   */
  45         unsigned char mpf_feature5;     /* Unused (0)                   */
  46 };
  47
  48 struct mp_config_table
  49 {
  50         char mpc_signature[4];
  51 #define MPC_SIGNATURE "PCMP"
  52         unsigned short mpc_length;      /* Size of table */
  53         char  mpc_spec;                 /* 0x01 */
  54         char  mpc_checksum;
  55         char  mpc_oem[8];
  56         char  mpc_productid[12];
  57         unsigned long mpc_oemptr;       /* 0 if not present */
  58         unsigned short mpc_oemsize;     /* 0 if not present */
  59         unsigned short mpc_oemcount;
  60         unsigned long mpc_lapic;        /* APIC address */
  61         unsigned long reserved;
  62 };
  63
  64 /* Followed by entries */
  65
  66 #define MP_PROCESSOR    0
  67 #define MP_BUS          1
  68 #define MP_IOAPIC       2
  69 #define MP_INTSRC       3
  70 #define MP_LINTSRC      4
  71
  72 struct mpc_config_processor
  73 {
  74         unsigned char mpc_type;
  75         unsigned char mpc_apicid;       /* Local APIC number */
  76         unsigned char mpc_apicver;      /* Its versions */
  77         unsigned char mpc_cpuflag;
  78 #define CPU_ENABLED             1       /* Processor is available */
  79 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
  80         unsigned long mpc_cpufeature;
  81 #define CPU_STEPPING_MASK 0x0F
  82 #define CPU_MODEL_MASK  0xF0
  83 #define CPU_FAMILY_MASK 0xF00
  84         unsigned long mpc_featureflag;  /* CPUID feature value */
  85         unsigned long mpc_reserved[2];
  86 };
  87
  88 struct mpc_config_bus
  89 {
  90         unsigned char mpc_type;
  91         unsigned char mpc_busid;
  92         unsigned char mpc_bustype[6] __attribute((packed));
  93 };
  94
  95 #define BUSTYPE_EISA    "EISA"
  96 #define BUSTYPE_ISA     "ISA"
  97 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
  98 #define BUSTYPE_MCA     "MCA"
  99 #define BUSTYPE_VL      "VL"            /* Local bus */
 100 #define BUSTYPE_PCI     "PCI"
 101 #define BUSTYPE_PCMCIA  "PCMCIA"
 102
 103 /* We don't understand the others */
 104
 105 struct mpc_config_ioapic
 106 {
 107         unsigned char mpc_type;
 108         unsigned char mpc_apicid;
 109         unsigned char mpc_apicver;
 110         unsigned char mpc_flags;
 111 #define MPC_APIC_USABLE         0x01
 112         unsigned long mpc_apicaddr;
 113 };
 114
 115 struct mpc_config_intsrc
 116 {
 117         unsigned char mpc_type;
 118         unsigned char mpc_irqtype;
 119         unsigned short mpc_irqflag;
 120         unsigned char mpc_srcbus;
 121         unsigned char mpc_srcbusirq;
 122         unsigned char mpc_dstapic;
 123         unsigned char mpc_dstirq;
 124 };
 125
 126 #define MP_INT_VECTORED         0
 127 #define MP_INT_NMI              1
 128 #define MP_INT_SMI              2
 129 #define MP_INT_EXTINT           3
 130
 131 #define MP_IRQDIR_DEFAULT       0
 132 #define MP_IRQDIR_HIGH          1
 133 #define MP_IRQDIR_LOW           3
 134
 135
 136 struct mpc_config_intlocal
 137 {
 138         unsigned char mpc_type;
 139         unsigned char mpc_irqtype;
 140         unsigned short mpc_irqflag;
 141         unsigned char mpc_srcbusid;
 142         unsigned char mpc_srcbusirq;
 143         unsigned char mpc_destapic;
 144 #define MP_APIC_ALL     0xFF
 145         unsigned char mpc_destapiclint;
 146 };
 147
 148
 149 /*
 150  *      Default configurations
 151  *
 152  *      1       2 CPU ISA 82489DX
 153  *      2       2 CPU EISA 82489DX no IRQ 8 or timer chaining
 154  *      3       2 CPU EISA 82489DX
 155  *      4       2 CPU MCA 82489DX
 156  *      5       2 CPU ISA+PCI
 157  *      6       2 CPU EISA+PCI
 158  *      7       2 CPU MCA+PCI
 159  */
 160
 161 /*
 162  *      Private routines/data
 163  */
 164
 165 extern int smp_found_config;
 166 extern void init_smp_config(void);
 167 extern unsigned long smp_alloc_memory(unsigned long mem_base);
 168 extern unsigned char boot_cpu_id;
 169 extern unsigned long cpu_present_map;
 170 extern unsigned long cpu_online_map;
 171 extern volatile int cpu_number_map[NR_CPUS];
 172 extern volatile unsigned long smp_invalidate_needed;
 173 extern void smp_flush_tlb(void);
 174
 175 extern volatile unsigned long cpu_callin_map[NR_CPUS];
 176 extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
 177 extern void smp_send_reschedule(int cpu);
 178 extern unsigned long ipi_count;
 179 extern void smp_invalidate_rcv(void);           /* Process an NMI */
 180 extern void smp_local_timer_interrupt(struct pt_regs * regs);
 181 extern void (*mtrr_hook) (void);
 182 extern void setup_APIC_clock (void);
 183 extern volatile int __cpu_logical_map[NR_CPUS];
 184 extern inline int cpu_logical_map(int cpu)
 185 {
 186         return __cpu_logical_map[cpu];
 187 }
 188
 189
 190 /*
 191  *      General functions that each host system must provide.
 192  */
 193
 194 extern void smp_callin(void);
 195 extern void smp_boot_cpus(void);
 196 extern void smp_store_cpu_info(int id);         /* Store per CPU info (like the initial udelay numbers */
 197
 198 /*
 199  * This function is needed by all SMP systems. It must _always_ be valid
 200  * from the initial startup. We map APIC_BASE very early in page_setup(),
 201  * so this is correct in the x86 case.
 202  */
 203
 204 #define smp_processor_id() (current->processor)
 205
 206 extern __inline int hard_smp_processor_id(void)
 207 {
 208         /* we don't want to mark this access volatile - bad code generation */
 209         return GET_APIC_ID(*(unsigned long *)(APIC_BASE+APIC_ID));
 210 }
 211
 212 #endif /* !ASSEMBLY */
 213
 214 #define NO_PROC_ID              0xFF            /* No processor magic marker */
 215
 216 /*
 217  *      This magic constant controls our willingness to transfer
 218  *      a process across CPUs. Such a transfer incurs misses on the L1
 219  *      cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
 220  *      gut feeling is this will vary by board in value. For a board
 221  *      with separate L2 cache it probably depends also on the RSS, and
 222  *      for a board with shared L2 cache it ought to decay fast as other
 223  *      processes are run.
 224  */
 225
 226 #define PROC_CHANGE_PENALTY     15              /* Schedule penalty */
 227
 228 #endif
 229 #endif