include/asm-sparc64/irq.h

   1 /* $Id: irq.h,v 1.16 1999/09/06 01:17:52 davem Exp $
   2  * irq.h: IRQ registers on the 64-bit Sparc.
   3  *
   4  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
   6  */
   7
   8 #ifndef _SPARC64_IRQ_H
   9 #define _SPARC64_IRQ_H
  10
  11 #include <linux/linkage.h>
  12 #include <linux/kernel.h>
  13
  14 struct devid_cookie {
  15         int dummy;
  16 };
  17
  18 /* You should not mess with this directly. That's the job of irq.c.
  19  *
  20  * If you make changes here, please update hand coded assembler of
  21  * SBUS/floppy interrupt handler in entry.S -DaveM
  22  *
  23  * This is currently one DCACHE line, two buckets per L2 cache
  24  * line.  Keep this in mind please.
  25  */
  26 struct ino_bucket {
  27         /* Next handler in per-CPU PIL worklist.  We know that
  28          * bucket pointers have the high 32-bits clear, so to
  29          * save space we only store the bits we need.
  30          */
  31 /*0x00*/unsigned int irq_chain;
  32
  33         /* PIL to schedule this IVEC at. */
  34 /*0x04*/unsigned char pil;
  35
  36         /* If an IVEC arrives while irq_info is NULL, we
  37          * set this to notify request_irq() about the event.
  38          */
  39 /*0x05*/unsigned char pending;
  40
  41         /* Miscellaneous flags. */
  42 /*0x06*/unsigned char flags;
  43
  44         /* Unused right now, but we will use it for proper
  45          * enable_irq()/disable_irq() nesting.
  46          */
  47 /*0x07*/unsigned char __unused;
  48
  49         /* Reference to handler for this IRQ.  If this is
  50          * non-NULL this means it is active and should be
  51          * serviced.  Else the pending member is set to one
  52          * and later registry of the interrupt checks for
  53          * this condition.
  54          *
  55          * Normally this is just an irq_action structure.
  56          * But, on PCI, if multiple interrupt sources behind
  57          * a bridge have multiple interrupt sources that share
  58          * the same INO bucket, this points to an array of
  59          * pointers to four IRQ action structures.
  60          */
  61 /*0x08*/void *irq_info;
  62
  63         /* Sun5 Interrupt Clear Register. */
  64 /*0x10*/volatile unsigned int *iclr;
  65
  66         /* Sun5 Interrupt Mapping Register. */
  67 /*0x18*/volatile unsigned int *imap;
  68
  69 };
  70
  71 /* Only 8-bits are available, be careful.  -DaveM */
  72 #define IBF_DMA_SYNC    0x01    /* DMA synchronization behind PCI bridge needed. */
  73 #define IBF_PCI         0x02    /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt.  */
  74 #define IBF_ACTIVE      0x04    /* This interrupt is active and has a handler.   */
  75 #define IBF_MULTI       0x08    /* On PCI, indicates shared bucket.              */
  76
  77 #define NUM_IVECS       8192
  78 extern struct ino_bucket ivector_table[NUM_IVECS];
  79
  80 #define __irq_ino(irq) \
  81         (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
  82 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
  83 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
  84 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
  85
  86 static __inline__ char *__irq_itoa(unsigned int irq)
  87 {
  88         static char buff[16];
  89
  90         sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
  91         return buff;
  92 }
  93
  94 #define NR_IRQS    15
  95
  96 extern void disable_irq(unsigned int);
  97 #define disable_irq_nosync disable_irq
  98 extern void enable_irq(unsigned int);
  99 extern void init_timers(void (*lvl10_irq)(int, void *, struct pt_regs *),
 100                         unsigned long *);
 101 extern unsigned int build_irq(int pil, int inofixup, volatile unsigned int *iclr, volatile unsigned int *imap);
 102 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
 103 extern unsigned int psycho_build_irq(void *psycho, int imap_off, int ino, int need_dma_sync);
 104
 105 #ifdef __SMP__
 106 extern void set_cpu_int(int, int);
 107 extern void clear_cpu_int(int, int);
 108 extern void set_irq_udt(int);
 109 #endif
 110
 111 extern int request_fast_irq(unsigned int irq,
 112                             void (*handler)(int, void *, struct pt_regs *),
 113                             unsigned long flags, __const__ char *devname,
 114                             void *dev_id);
 115
 116 extern __inline__ void set_softint(unsigned long bits)
 117 {
 118         __asm__ __volatile__("wr        %0, 0x0, %%set_softint"
 119                              : /* No outputs */
 120                              : "r" (bits));
 121 }
 122
 123 extern __inline__ void clear_softint(unsigned long bits)
 124 {
 125         __asm__ __volatile__("wr        %0, 0x0, %%clear_softint"
 126                              : /* No outputs */
 127                              : "r" (bits));
 128 }
 129
 130 extern __inline__ unsigned long get_softint(void)
 131 {
 132         unsigned long retval;
 133
 134         __asm__ __volatile__("rd        %%softint, %0"
 135                              : "=r" (retval));
 136         return retval;
 137 }
 138
 139 #endif