1 /* $Id: irq.h,v 1.16 1999/09/06 01:17:52 davem Exp $
2 * irq.h: IRQ registers on the 64-bit Sparc.
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
11 #include <linux/linkage.h>
12 #include <linux/kernel.h>
18 /* You should not mess with this directly. That's the job of irq.c.
20 * If you make changes here, please update hand coded assembler of
21 * SBUS/floppy interrupt handler in entry.S -DaveM
23 * This is currently one DCACHE line, two buckets per L2 cache
24 * line. Keep this in mind please.
27 /* Next handler in per-CPU PIL worklist. We know that
28 * bucket pointers have the high 32-bits clear, so to
29 * save space we only store the bits we need.
31 /*0x00*/unsigned int irq_chain
;
33 /* PIL to schedule this IVEC at. */
34 /*0x04*/unsigned char pil
;
36 /* If an IVEC arrives while irq_info is NULL, we
37 * set this to notify request_irq() about the event.
39 /*0x05*/unsigned char pending
;
41 /* Miscellaneous flags. */
42 /*0x06*/unsigned char flags
;
44 /* Unused right now, but we will use it for proper
45 * enable_irq()/disable_irq() nesting.
47 /*0x07*/unsigned char __unused
;
49 /* Reference to handler for this IRQ. If this is
50 * non-NULL this means it is active and should be
51 * serviced. Else the pending member is set to one
52 * and later registry of the interrupt checks for
55 * Normally this is just an irq_action structure.
56 * But, on PCI, if multiple interrupt sources behind
57 * a bridge have multiple interrupt sources that share
58 * the same INO bucket, this points to an array of
59 * pointers to four IRQ action structures.
61 /*0x08*/void *irq_info
;
63 /* Sun5 Interrupt Clear Register. */
64 /*0x10*/volatile unsigned int *iclr
;
66 /* Sun5 Interrupt Mapping Register. */
67 /*0x18*/volatile unsigned int *imap
;
71 /* Only 8-bits are available, be careful. -DaveM */
72 #define IBF_DMA_SYNC 0x01 /* DMA synchronization behind PCI bridge needed. */
73 #define IBF_PCI 0x02 /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt. */
74 #define IBF_ACTIVE 0x04 /* This interrupt is active and has a handler. */
75 #define IBF_MULTI 0x08 /* On PCI, indicates shared bucket. */
77 #define NUM_IVECS 8192
78 extern struct ino_bucket ivector_table
[NUM_IVECS
];
80 #define __irq_ino(irq) \
81 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
82 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
83 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
84 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
86 static __inline__
char *__irq_itoa(unsigned int irq
)
90 sprintf(buff
, "%d,%x", __irq_pil(irq
), (unsigned int)__irq_ino(irq
));
96 extern void disable_irq(unsigned int);
97 #define disable_irq_nosync disable_irq
98 extern void enable_irq(unsigned int);
99 extern void init_timers(void (*lvl10_irq
)(int, void *, struct pt_regs
*),
101 extern unsigned int build_irq(int pil
, int inofixup
, volatile unsigned int *iclr
, volatile unsigned int *imap
);
102 extern unsigned int sbus_build_irq(void *sbus
, unsigned int ino
);
103 extern unsigned int psycho_build_irq(void *psycho
, int imap_off
, int ino
, int need_dma_sync
);
106 extern void set_cpu_int(int, int);
107 extern void clear_cpu_int(int, int);
108 extern void set_irq_udt(int);
111 extern int request_fast_irq(unsigned int irq
,
112 void (*handler
)(int, void *, struct pt_regs
*),
113 unsigned long flags
, __const__
char *devname
,
116 extern __inline__
void set_softint(unsigned long bits
)
118 __asm__
__volatile__("wr %0, 0x0, %%set_softint"
123 extern __inline__
void clear_softint(unsigned long bits
)
125 __asm__
__volatile__("wr %0, 0x0, %%clear_softint"
130 extern __inline__
unsigned long get_softint(void)
132 unsigned long retval
;
134 __asm__
__volatile__("rd %%softint, %0"