ram_dual_port.vhd

   1 library ieee;
   2     use ieee.std_logic_1164.all;
   3     use ieee.std_logic_unsigned.all;
   4
   5 entity ram_dual_port is
   6 generic (
   7     addr_width : natural := 9;  --512x8
   8     data_width : natural := 8
   9     );
  10 port (
  11     write_en    : in  std_logic;
  12     waddr       : in  std_logic_vector (addr_width - 1 downto 0);
  13     wclk        : in  std_logic;
  14     raddr       : in  std_logic_vector (addr_width - 1 downto 0);
  15     rclk        : in  std_logic;
  16     din         : in  std_logic_vector (data_width - 1 downto 0);
  17     dout        : out std_logic_vector (data_width - 1 downto 0)
  18   );
  19 end ram_dual_port;
  20 architecture rtl of ram_dual_port is
  21     type mem_type is array ((2** addr_width) - 1 downto 0) of std_logic_vector(data_width - 1 downto 0);
  22     signal mem : mem_type;
  23 begin
  24     process (wclk)   -- Write memory.
  25     begin
  26         if (rising_edge(wclk)) then
  27             if (write_en = '1') then
  28                 mem(conv_integer(waddr)) <= din; -- Using write address bus.
  29             end if;
  30         end if;
  31     end process;
  32
  33     process (rclk) -- Read memory.
  34     begin
  35         if (rising_edge(rclk)) then
  36             dout <= mem(conv_integer(raddr)); -- Using read address bus.
  37         end if;
  38     end process;
  39 end rtl;