pwm.vhd

   1 library ieee;
   2         use ieee.std_logic_1164.all;
   3         use ieee.numeric_std.all;
   4         use work.pwm_reg_pack.ALL;
   5
   6 entity pwm is
   7         port (
   8
   9                 clk             : in  std_logic;
  10                 rst                     : in  std_logic;
  11
  12                 -- signals from top module to registers sub-module
  13                 en                              : in std_logic;
  14                 duty                    : in std_logic_vector(DUTY_CYCLE_W-1 downto 0);
  15                 pwm_out                 : out std_logic
  16         );
  17
  18 end entity pwm;
  19
  20 architecture rtl of pwm is
  21
  22         signal clk_en                                           : std_logic;
  23         signal cnt                                                      : unsigned(PERIOD_W-1 downto 0);
  24         signal cnt_duty                                         : unsigned(DUTY_CYCLE_W-1 downto 0);
  25
  26 begin
  27
  28         cnt_pr : process(clk, rst)
  29         begin
  30         if (rst = '1') then
  31                 cnt                     <= (others => '0');
  32                 clk_en                  <= '0';
  33         elsif (rising_edge(clk)) then
  34                 -- default
  35                 clk_en  <= '0';
  36
  37                 if (en = '1') then
  38                         if (cnt = 0) then
  39                                 cnt     <= to_unsigned(PERIOD-1, cnt'length);
  40                                 clk_en  <= '1';
  41                         else
  42                                 cnt <= cnt - 1;
  43                         end if;
  44                 end if;
  45         end if;
  46         end process cnt_pr;
  47
  48         cnt_duty_pr : process(clk, rst)
  49         begin
  50         if (rst = '1') then
  51                 cnt_duty                <= (others => '0');
  52                 pwm_out                 <= '0';
  53         elsif (rising_edge(clk)) then
  54                 if (clk_en = '1') then
  55                         cnt_duty <= cnt_duty + 1;
  56                 end if;
  57                 if (cnt_duty < unsigned(duty)) then
  58                         pwm_out <= '1';
  59                 else
  60                         pwm_out <= '0';
  61                 end if;
  62         end if;
  63         end process cnt_duty_pr;
  64
  65 end rtl;