add ram dual and single port
[vhdl_digital_base_blocks.git] / hamcorr.vhd
blob60af0b5b0b1c67538cca2c4bd3141227d2cb3fd6
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;
5 entity hamcorr is
6 port (
7 -- TO DO: Make synchronous
8 du : in std_logic_vector(1 to 7);
9 dc : out std_logic_vector(1 to 7);
10 noerror : out std_logic
12 end hamcorr;
14 architecture hamcorr of hamcorr is
16 function syndrome (d:std_logic_vector)
17 return std_logic_vector is
18 variable syn: std_logic_vector (2 downto 0);
19 begin
20 syn(0):= d(1) xor d(3) xor d(5) xor d(7);
21 syn(1):= d(2) xor d(3) xor d(6) xor d(7);
22 syn(2):= d(4) xor d(5) xor d(6) xor d(7);
23 return(syn);
24 end syndrome;
26 begin
27 process(du)
28 variable i : integer;
29 begin
30 dc<=du;
31 i:=conv_integer(syndrome(du));
32 if i=0 then noerror <='1';
33 else noerror <='0'; dc(i) <=not du(i); end if;
34 end process;
35 end hamcorr;