2 use ieee.std_logic_1164.
all;
3 use ieee.numeric_std.
all;
7 data_in
: in std_logic_vector (3 downto 0);
8 data_out
: out std_logic_vector (6 downto 0)
12 architecture rtl
of decoder_7seg
is
16 with data_in
select data_out
<=
19 "
0100100"
when x"
2"
, --
20 "
0110000"
when x"
3"
, -- ---0---
21 "
0011001"
when x"
4"
, -- | |
22 "
0010010"
when x"
5"
, -- 5 1
23 "
0000010"
when x"
6"
, -- | |
24 "
1111000"
when x"
7"
, -- ---6---
25 "
0000000"
when x"
8"
, -- | |
26 "
0011000"
when x"
9"
, -- 4 2
27 "
0001000"
when x"a"
, -- | |
28 "
0000011"
when x"b"
, -- ---3---
29 "
1000110"
when x"c"
, --
33 "
1111111"
when others;
