arch/x86/kernel/platform/i86pc/include/sys/mach_mmu.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  *
  25  * Copyright 2018 Joyent, Inc.
  26  */
  27
  28 #ifndef _SYS_MACH_MMU_H
  29 #define _SYS_MACH_MMU_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 #ifndef _ASM
  36
  37 #include <sys/types.h>
  38 #include <sys/systm.h>
  39
  40 /*
  41  * Platform-dependent MMU routines and types.
  42  *
  43  * WARNING: this header file is used by both dboot and i86pc, so don't go using
  44  * normal kernel headers.
  45  */
  46
  47 #define TWO_MEG         (2 * 1024 * 1024)
  48
  49 /*
  50  * This is:
  51  *      The kernel nucleus pagesizes, ie: bi->bi_kseg_size
  52  *      The grub 64 bit file load address (see multiboot header in dboot_grub.s)
  53  *      The grub 32 bit and hypervisor physical load addresses of
  54  *          the kernel text/data (see Mapfile.unix)
  55  */
  56 #define FOUR_MEG        (4 * 1024 * 1024)
  57
  58 #define ONE_GIG         (1024 * 1024 * 1024)
  59 #define FOUR_GIG        ((uint64_t)4 * ONE_GIG)
  60
  61 #define MMU_STD_PAGESIZE        4096
  62 #ifdef __amd64
  63 #define MMU_STD_PAGEMASK        0xFFFFFFFFFFFFF000ULL
  64 #else
  65 #define MMU_STD_PAGEMASK        0xFFFFF000UL
  66 #endif
  67
  68 /*
  69  * Defines for the bits in X86 and AMD64 Page Tables
  70  *
  71  * Notes:
  72  *
  73  * Largepages and PAT bits:
  74  *
  75  * bit 7 at level 0 is the PAT bit
  76  * bit 7 above level 0 is the Pagesize bit (set for large page)
  77  * bit 12 (when a large page) is the PAT bit
  78  *
  79  * In Solaris the PAT/PWT/PCD values are set up so that:
  80  *
  81  * PAT & PWT -> Write Protected
  82  * PAT & PCD -> Write Combining
  83  * PAT by itself (PWT == 0 && PCD == 0) yields uncacheable (same as PCD == 1)
  84  *
  85  *
  86  * Permission bits:
  87  *
  88  * - PT_USER must be set in all levels for user pages
  89  * - PT_WRITE must be set in all levels for user writable pages
  90  * - PT_NX applies if set at any level
  91  *
  92  * For these, we use the "allow" settings in all tables above level 0 and only
  93  * ever disable things in PTEs.
  94  *
  95  * The use of PT_GLOBAL and PT_NX depend on being enabled in processor
  96  * control registers. Hence, we use a variable to reference these bit
  97  * masks. During hat_kern_setup() if the feature isn't enabled we
  98  * clear out the variables.
  99  */
 100 #define PT_VALID        (0x001) /* a valid translation is present */
 101 #define PT_WRITABLE     (0x002) /* the page is writable */
 102 #define PT_USER         (0x004) /* the page is accessible by user mode */
 103 #define PT_WRITETHRU    (0x008) /* write back caching is disabled (non-PAT) */
 104 #define PT_NOCACHE      (0x010) /* page is not cacheable (non-PAT) */
 105 #define PT_REF          (0x020) /* page was referenced */
 106 #define PT_MOD          (0x040) /* page was modified */
 107 #define PT_PAGESIZE     (0x080) /* above level 0, indicates a large page */
 108 #define PT_PAT_4K       (0x080) /* at level 0, used for write combining */
 109 #define PT_GLOBAL       (0x100) /* the mapping is global */
 110 #define PT_SOFTWARE     (0xe00) /* software bits */
 111
 112 #define PT_PAT_LARGE    (0x1000)        /* PAT bit for large pages */
 113
 114 #define PT_PTPBITS      (PT_VALID | PT_USER | PT_WRITABLE | PT_REF)
 115 #define PT_FLAGBITS     (0xfff) /* for masking off flag bits */
 116
 117 /*
 118  * The software bits are used by the HAT to track attributes.
 119  * Note that the attributes are inclusive as the values increase.
 120  *
 121  * PT_NOSYNC - The PT_REF/PT_MOD bits are not sync'd to page_t.
 122  *             The hat will install them as always set.
 123  *
 124  * PT_NOCONSIST - There is no hment entry for this mapping.
 125  *
 126  * PT_FOREIGN - used for the hypervisor, check via
 127  *              (pte & PT_SOFTWARE) >= PT_FOREIGN
 128  *              as it might set 0x800 for foreign grant table mappings.
 129  */
 130 #define PT_NOSYNC       (0x200) /* PTE was created with HAT_NOSYNC */
 131 #define PT_NOCONSIST    (0x400) /* PTE was created with HAT_LOAD_NOCONSIST */
 132 #define PT_FOREIGN      (0x600) /* MFN mapped on the hypervisor has no PFN */
 133
 134 #ifndef _BOOT
 135
 136 extern ulong_t getcr3(void);
 137 extern void setcr3(ulong_t);
 138
 139 #define getcr3_pa() (getcr3() & MMU_PAGEMASK)
 140 #define getpcid() ((getcr4() & CR4_PCIDE) ? \
 141         (getcr3() & MMU_PAGEOFFSET) : PCID_NONE)
 142
 143 extern void mmu_invlpg(caddr_t);
 144
 145 #endif
 146
 147 #ifdef __xpv
 148 #include <sys/xen_mmu.h>
 149 #else
 150 #include <sys/pc_mmu.h>
 151 #endif
 152
 153 /*
 154  * The software extraction for a single Page Table Entry will always
 155  * be a 64 bit unsigned int. If running a non-PAE hat, the page table
 156  * access routines know to extend/shorten it to 32 bits.
 157  */
 158 typedef uint64_t x86pte_t;
 159 typedef uint32_t x86pte32_t;
 160
 161 x86pte_t get_pteval(paddr_t, uint_t);
 162 void set_pteval(paddr_t, uint_t, uint_t, x86pte_t);
 163 paddr_t make_ptable(x86pte_t *, uint_t);
 164 x86pte_t *find_pte(uint64_t, paddr_t *, uint_t, uint_t);
 165 x86pte_t *map_pte(paddr_t, uint_t);
 166
 167 extern uint_t *shift_amt;
 168 extern uint_t ptes_per_table;
 169 extern paddr_t top_page_table;
 170 extern uint_t top_level;
 171 extern uint_t pte_size;
 172 extern uint_t shift_amt_nopae[];
 173 extern uint_t shift_amt_pae[];
 174 extern uint32_t lpagesize;
 175
 176 #ifdef __cplusplus
 177 }
 178 #endif
 179
 180 #endif /* _ASM */
 181
 182 #endif  /* _SYS_MACH_MMU_H */