4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright 2017, Joyent, Inc.
29 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
30 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
31 * Copyright (c) 2013 OSN Online Service Nuernberg GmbH. All rights reserved.
32 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
37 static char ixgbe_ident
[] = "Intel 10Gb Ethernet";
40 * Local function protoypes
42 static int ixgbe_register_mac(ixgbe_t
*);
43 static int ixgbe_identify_hardware(ixgbe_t
*);
44 static int ixgbe_regs_map(ixgbe_t
*);
45 static void ixgbe_init_properties(ixgbe_t
*);
46 static int ixgbe_init_driver_settings(ixgbe_t
*);
47 static void ixgbe_init_locks(ixgbe_t
*);
48 static void ixgbe_destroy_locks(ixgbe_t
*);
49 static int ixgbe_init(ixgbe_t
*);
50 static int ixgbe_chip_start(ixgbe_t
*);
51 static void ixgbe_chip_stop(ixgbe_t
*);
52 static int ixgbe_reset(ixgbe_t
*);
53 static void ixgbe_tx_clean(ixgbe_t
*);
54 static boolean_t
ixgbe_tx_drain(ixgbe_t
*);
55 static boolean_t
ixgbe_rx_drain(ixgbe_t
*);
56 static int ixgbe_alloc_rings(ixgbe_t
*);
57 static void ixgbe_free_rings(ixgbe_t
*);
58 static int ixgbe_alloc_rx_data(ixgbe_t
*);
59 static void ixgbe_free_rx_data(ixgbe_t
*);
60 static void ixgbe_setup_rings(ixgbe_t
*);
61 static void ixgbe_setup_rx(ixgbe_t
*);
62 static void ixgbe_setup_tx(ixgbe_t
*);
63 static void ixgbe_setup_rx_ring(ixgbe_rx_ring_t
*);
64 static void ixgbe_setup_tx_ring(ixgbe_tx_ring_t
*);
65 static void ixgbe_setup_rss(ixgbe_t
*);
66 static void ixgbe_setup_vmdq(ixgbe_t
*);
67 static void ixgbe_setup_vmdq_rss(ixgbe_t
*);
68 static void ixgbe_setup_rss_table(ixgbe_t
*);
69 static void ixgbe_init_unicst(ixgbe_t
*);
70 static int ixgbe_unicst_find(ixgbe_t
*, const uint8_t *);
71 static void ixgbe_setup_multicst(ixgbe_t
*);
72 static void ixgbe_get_hw_state(ixgbe_t
*);
73 static void ixgbe_setup_vmdq_rss_conf(ixgbe_t
*ixgbe
);
74 static void ixgbe_get_conf(ixgbe_t
*);
75 static void ixgbe_init_params(ixgbe_t
*);
76 static int ixgbe_get_prop(ixgbe_t
*, char *, int, int, int);
77 static void ixgbe_driver_link_check(ixgbe_t
*);
78 static void ixgbe_sfp_check(void *);
79 static void ixgbe_overtemp_check(void *);
80 static void ixgbe_phy_check(void *);
81 static void ixgbe_link_timer(void *);
82 static void ixgbe_local_timer(void *);
83 static void ixgbe_arm_watchdog_timer(ixgbe_t
*);
84 static void ixgbe_restart_watchdog_timer(ixgbe_t
*);
85 static void ixgbe_disable_adapter_interrupts(ixgbe_t
*);
86 static void ixgbe_enable_adapter_interrupts(ixgbe_t
*);
87 static boolean_t
is_valid_mac_addr(uint8_t *);
88 static boolean_t
ixgbe_stall_check(ixgbe_t
*);
89 static boolean_t
ixgbe_set_loopback_mode(ixgbe_t
*, uint32_t);
90 static void ixgbe_set_internal_mac_loopback(ixgbe_t
*);
91 static boolean_t
ixgbe_find_mac_address(ixgbe_t
*);
92 static int ixgbe_alloc_intrs(ixgbe_t
*);
93 static int ixgbe_alloc_intr_handles(ixgbe_t
*, int);
94 static int ixgbe_add_intr_handlers(ixgbe_t
*);
95 static void ixgbe_map_rxring_to_vector(ixgbe_t
*, int, int);
96 static void ixgbe_map_txring_to_vector(ixgbe_t
*, int, int);
97 static void ixgbe_setup_ivar(ixgbe_t
*, uint16_t, uint8_t, int8_t);
98 static void ixgbe_enable_ivar(ixgbe_t
*, uint16_t, int8_t);
99 static void ixgbe_disable_ivar(ixgbe_t
*, uint16_t, int8_t);
100 static uint32_t ixgbe_get_hw_rx_index(ixgbe_t
*ixgbe
, uint32_t sw_rx_index
);
101 static int ixgbe_map_intrs_to_vectors(ixgbe_t
*);
102 static void ixgbe_setup_adapter_vector(ixgbe_t
*);
103 static void ixgbe_rem_intr_handlers(ixgbe_t
*);
104 static void ixgbe_rem_intrs(ixgbe_t
*);
105 static int ixgbe_enable_intrs(ixgbe_t
*);
106 static int ixgbe_disable_intrs(ixgbe_t
*);
107 static uint_t
ixgbe_intr_legacy(void *, void *);
108 static uint_t
ixgbe_intr_msi(void *, void *);
109 static uint_t
ixgbe_intr_msix(void *, void *);
110 static void ixgbe_intr_rx_work(ixgbe_rx_ring_t
*);
111 static void ixgbe_intr_tx_work(ixgbe_tx_ring_t
*);
112 static void ixgbe_intr_other_work(ixgbe_t
*, uint32_t);
113 static void ixgbe_get_driver_control(struct ixgbe_hw
*);
114 static int ixgbe_addmac(void *, const uint8_t *);
115 static int ixgbe_remmac(void *, const uint8_t *);
116 static void ixgbe_release_driver_control(struct ixgbe_hw
*);
118 static int ixgbe_attach(dev_info_t
*, ddi_attach_cmd_t
);
119 static int ixgbe_detach(dev_info_t
*, ddi_detach_cmd_t
);
120 static int ixgbe_resume(dev_info_t
*);
121 static int ixgbe_suspend(dev_info_t
*);
122 static int ixgbe_quiesce(dev_info_t
*);
123 static void ixgbe_unconfigure(dev_info_t
*, ixgbe_t
*);
124 static uint8_t *ixgbe_mc_table_itr(struct ixgbe_hw
*, uint8_t **, uint32_t *);
125 static int ixgbe_cbfunc(dev_info_t
*, ddi_cb_action_t
, void *, void *, void *);
126 static int ixgbe_intr_cb_register(ixgbe_t
*);
127 static int ixgbe_intr_adjust(ixgbe_t
*, ddi_cb_action_t
, int);
129 static int ixgbe_fm_error_cb(dev_info_t
*dip
, ddi_fm_error_t
*err
,
130 const void *impl_data
);
131 static void ixgbe_fm_init(ixgbe_t
*);
132 static void ixgbe_fm_fini(ixgbe_t
*);
134 char *ixgbe_priv_props
[] = {
136 "_tx_recycle_thresh",
137 "_tx_overload_thresh",
138 "_tx_resched_thresh",
140 "_rx_limit_per_intr",
143 "_adv_asym_pause_cap",
147 #define IXGBE_MAX_PRIV_PROPS \
148 (sizeof (ixgbe_priv_props) / sizeof (mac_priv_prop_t))
150 static struct cb_ops ixgbe_cb_ops
= {
151 nulldev
, /* cb_open */
152 nulldev
, /* cb_close */
153 nodev
, /* cb_strategy */
154 nodev
, /* cb_print */
157 nodev
, /* cb_write */
158 nodev
, /* cb_ioctl */
159 nodev
, /* cb_devmap */
161 nodev
, /* cb_segmap */
162 nochpoll
, /* cb_chpoll */
163 ddi_prop_op
, /* cb_prop_op */
164 NULL
, /* cb_stream */
165 D_MP
| D_HOTPLUG
, /* cb_flag */
167 nodev
, /* cb_aread */
168 nodev
/* cb_awrite */
171 static struct dev_ops ixgbe_dev_ops
= {
172 DEVO_REV
, /* devo_rev */
174 NULL
, /* devo_getinfo */
175 nulldev
, /* devo_identify */
176 nulldev
, /* devo_probe */
177 ixgbe_attach
, /* devo_attach */
178 ixgbe_detach
, /* devo_detach */
179 nodev
, /* devo_reset */
180 &ixgbe_cb_ops
, /* devo_cb_ops */
181 NULL
, /* devo_bus_ops */
182 ddi_power
, /* devo_power */
183 ixgbe_quiesce
, /* devo_quiesce */
186 static struct modldrv ixgbe_modldrv
= {
187 &mod_driverops
, /* Type of module. This one is a driver */
188 ixgbe_ident
, /* Discription string */
189 &ixgbe_dev_ops
/* driver ops */
192 static struct modlinkage ixgbe_modlinkage
= {
193 MODREV_1
, &ixgbe_modldrv
, NULL
197 * Access attributes for register mapping
199 ddi_device_acc_attr_t ixgbe_regs_acc_attr
= {
201 DDI_STRUCTURE_LE_ACC
,
209 static lb_property_t lb_normal
= {
210 normal
, "normal", IXGBE_LB_NONE
213 static lb_property_t lb_mac
= {
214 internal
, "MAC", IXGBE_LB_INTERNAL_MAC
217 static lb_property_t lb_external
= {
218 external
, "External", IXGBE_LB_EXTERNAL
221 #define IXGBE_M_CALLBACK_FLAGS \
222 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
224 static mac_callbacks_t ixgbe_m_callbacks
= {
225 IXGBE_M_CALLBACK_FLAGS
,
244 * Initialize capabilities of each supported adapter type
246 static adapter_info_t ixgbe_82598eb_cap
= {
247 64, /* maximum number of rx queues */
248 1, /* minimum number of rx queues */
249 64, /* default number of rx queues */
250 16, /* maximum number of rx groups */
251 1, /* minimum number of rx groups */
252 1, /* default number of rx groups */
253 32, /* maximum number of tx queues */
254 1, /* minimum number of tx queues */
255 8, /* default number of tx queues */
256 16366, /* maximum MTU size */
257 0xFFFF, /* maximum interrupt throttle rate */
258 0, /* minimum interrupt throttle rate */
259 200, /* default interrupt throttle rate */
260 18, /* maximum total msix vectors */
261 16, /* maximum number of ring vectors */
262 2, /* maximum number of other vectors */
263 IXGBE_EICR_LSC
, /* "other" interrupt types handled */
264 0, /* "other" interrupt types enable mask */
265 (IXGBE_FLAG_DCA_CAPABLE
/* capability flags */
266 | IXGBE_FLAG_RSS_CAPABLE
267 | IXGBE_FLAG_VMDQ_CAPABLE
)
270 static adapter_info_t ixgbe_82599eb_cap
= {
271 128, /* maximum number of rx queues */
272 1, /* minimum number of rx queues */
273 128, /* default number of rx queues */
274 64, /* maximum number of rx groups */
275 1, /* minimum number of rx groups */
276 1, /* default number of rx groups */
277 128, /* maximum number of tx queues */
278 1, /* minimum number of tx queues */
279 8, /* default number of tx queues */
280 15500, /* maximum MTU size */
281 0xFF8, /* maximum interrupt throttle rate */
282 0, /* minimum interrupt throttle rate */
283 200, /* default interrupt throttle rate */
284 64, /* maximum total msix vectors */
285 16, /* maximum number of ring vectors */
286 2, /* maximum number of other vectors */
288 | IXGBE_EICR_GPI_SDP1
289 | IXGBE_EICR_GPI_SDP2
), /* "other" interrupt types handled */
292 | IXGBE_SDP2_GPIEN
), /* "other" interrupt types enable mask */
294 (IXGBE_FLAG_DCA_CAPABLE
295 | IXGBE_FLAG_RSS_CAPABLE
296 | IXGBE_FLAG_VMDQ_CAPABLE
297 | IXGBE_FLAG_RSC_CAPABLE
298 | IXGBE_FLAG_SFP_PLUG_CAPABLE
) /* capability flags */
301 static adapter_info_t ixgbe_X540_cap
= {
302 128, /* maximum number of rx queues */
303 1, /* minimum number of rx queues */
304 128, /* default number of rx queues */
305 64, /* maximum number of rx groups */
306 1, /* minimum number of rx groups */
307 1, /* default number of rx groups */
308 128, /* maximum number of tx queues */
309 1, /* minimum number of tx queues */
310 8, /* default number of tx queues */
311 15500, /* maximum MTU size */
312 0xFF8, /* maximum interrupt throttle rate */
313 0, /* minimum interrupt throttle rate */
314 200, /* default interrupt throttle rate */
315 64, /* maximum total msix vectors */
316 16, /* maximum number of ring vectors */
317 2, /* maximum number of other vectors */
319 | IXGBE_EICR_GPI_SDP1_X540
320 | IXGBE_EICR_GPI_SDP2_X540
), /* "other" interrupt types handled */
322 (IXGBE_SDP1_GPIEN_X540
323 | IXGBE_SDP2_GPIEN_X540
), /* "other" interrupt types enable mask */
325 (IXGBE_FLAG_DCA_CAPABLE
326 | IXGBE_FLAG_RSS_CAPABLE
327 | IXGBE_FLAG_VMDQ_CAPABLE
328 | IXGBE_FLAG_RSC_CAPABLE
) /* capability flags */
331 static adapter_info_t ixgbe_X550_cap
= {
332 128, /* maximum number of rx queues */
333 1, /* minimum number of rx queues */
334 128, /* default number of rx queues */
335 64, /* maximum number of rx groups */
336 1, /* minimum number of rx groups */
337 1, /* default number of rx groups */
338 128, /* maximum number of tx queues */
339 1, /* minimum number of tx queues */
340 8, /* default number of tx queues */
341 15500, /* maximum MTU size */
342 0xFF8, /* maximum interrupt throttle rate */
343 0, /* minimum interrupt throttle rate */
344 0x200, /* default interrupt throttle rate */
345 64, /* maximum total msix vectors */
346 16, /* maximum number of ring vectors */
347 2, /* maximum number of other vectors */
348 IXGBE_EICR_LSC
, /* "other" interrupt types handled */
349 0, /* "other" interrupt types enable mask */
350 (IXGBE_FLAG_RSS_CAPABLE
351 | IXGBE_FLAG_VMDQ_CAPABLE
352 | IXGBE_FLAG_RSC_CAPABLE
) /* capability flags */
356 * Module Initialization Functions.
364 mac_init_ops(&ixgbe_dev_ops
, MODULE_NAME
);
366 status
= mod_install(&ixgbe_modlinkage
);
368 if (status
!= DDI_SUCCESS
) {
369 mac_fini_ops(&ixgbe_dev_ops
);
380 status
= mod_remove(&ixgbe_modlinkage
);
382 if (status
== DDI_SUCCESS
) {
383 mac_fini_ops(&ixgbe_dev_ops
);
390 _info(struct modinfo
*modinfop
)
394 status
= mod_info(&ixgbe_modlinkage
, modinfop
);
400 * ixgbe_attach - Driver attach.
402 * This function is the device specific initialization entry
403 * point. This entry point is required and must be written.
404 * The DDI_ATTACH command must be provided in the attach entry
405 * point. When attach() is called with cmd set to DDI_ATTACH,
406 * all normal kernel services (such as kmem_alloc(9F)) are
407 * available for use by the driver.
409 * The attach() function will be called once for each instance
410 * of the device on the system with cmd set to DDI_ATTACH.
411 * Until attach() succeeds, the only driver entry points which
412 * may be called are open(9E) and getinfo(9E).
415 ixgbe_attach(dev_info_t
*devinfo
, ddi_attach_cmd_t cmd
)
418 struct ixgbe_osdep
*osdep
;
424 * Check the command and perform corresponding operations
428 return (DDI_FAILURE
);
431 return (ixgbe_resume(devinfo
));
437 /* Get the device instance */
438 instance
= ddi_get_instance(devinfo
);
440 /* Allocate memory for the instance data structure */
441 ixgbe
= kmem_zalloc(sizeof (ixgbe_t
), KM_SLEEP
);
443 ixgbe
->dip
= devinfo
;
444 ixgbe
->instance
= instance
;
447 osdep
= &ixgbe
->osdep
;
449 osdep
->ixgbe
= ixgbe
;
451 /* Attach the instance pointer to the dev_info data structure */
452 ddi_set_driver_private(devinfo
, ixgbe
);
455 * Initialize for FMA support
457 ixgbe
->fm_capabilities
= ixgbe_get_prop(ixgbe
, PROP_FM_CAPABLE
,
458 0, 0x0f, DDI_FM_EREPORT_CAPABLE
| DDI_FM_ACCCHK_CAPABLE
|
459 DDI_FM_DMACHK_CAPABLE
| DDI_FM_ERRCB_CAPABLE
);
460 ixgbe_fm_init(ixgbe
);
461 ixgbe
->attach_progress
|= ATTACH_PROGRESS_FM_INIT
;
464 * Map PCI config space registers
466 if (pci_config_setup(devinfo
, &osdep
->cfg_handle
) != DDI_SUCCESS
) {
467 ixgbe_error(ixgbe
, "Failed to map PCI configurations");
470 ixgbe
->attach_progress
|= ATTACH_PROGRESS_PCI_CONFIG
;
473 * Identify the chipset family
475 if (ixgbe_identify_hardware(ixgbe
) != IXGBE_SUCCESS
) {
476 ixgbe_error(ixgbe
, "Failed to identify hardware");
481 * Map device registers
483 if (ixgbe_regs_map(ixgbe
) != IXGBE_SUCCESS
) {
484 ixgbe_error(ixgbe
, "Failed to map device registers");
487 ixgbe
->attach_progress
|= ATTACH_PROGRESS_REGS_MAP
;
490 * Initialize driver parameters
492 ixgbe_init_properties(ixgbe
);
493 ixgbe
->attach_progress
|= ATTACH_PROGRESS_PROPS
;
496 * Register interrupt callback
498 if (ixgbe_intr_cb_register(ixgbe
) != IXGBE_SUCCESS
) {
499 ixgbe_error(ixgbe
, "Failed to register interrupt callback");
504 * Allocate interrupts
506 if (ixgbe_alloc_intrs(ixgbe
) != IXGBE_SUCCESS
) {
507 ixgbe_error(ixgbe
, "Failed to allocate interrupts");
510 ixgbe
->attach_progress
|= ATTACH_PROGRESS_ALLOC_INTR
;
513 * Allocate rx/tx rings based on the ring numbers.
514 * The actual numbers of rx/tx rings are decided by the number of
515 * allocated interrupt vectors, so we should allocate the rings after
516 * interrupts are allocated.
518 if (ixgbe_alloc_rings(ixgbe
) != IXGBE_SUCCESS
) {
519 ixgbe_error(ixgbe
, "Failed to allocate rx and tx rings");
522 ixgbe
->attach_progress
|= ATTACH_PROGRESS_ALLOC_RINGS
;
525 * Map rings to interrupt vectors
527 if (ixgbe_map_intrs_to_vectors(ixgbe
) != IXGBE_SUCCESS
) {
528 ixgbe_error(ixgbe
, "Failed to map interrupts to vectors");
533 * Add interrupt handlers
535 if (ixgbe_add_intr_handlers(ixgbe
) != IXGBE_SUCCESS
) {
536 ixgbe_error(ixgbe
, "Failed to add interrupt handlers");
539 ixgbe
->attach_progress
|= ATTACH_PROGRESS_ADD_INTR
;
542 * Create a taskq for sfp-change
544 (void) sprintf(taskqname
, "ixgbe%d_sfp_taskq", instance
);
545 if ((ixgbe
->sfp_taskq
= ddi_taskq_create(devinfo
, taskqname
,
546 1, TASKQ_DEFAULTPRI
, 0)) == NULL
) {
547 ixgbe_error(ixgbe
, "sfp_taskq create failed");
550 ixgbe
->attach_progress
|= ATTACH_PROGRESS_SFP_TASKQ
;
553 * Create a taskq for over-temp
555 (void) sprintf(taskqname
, "ixgbe%d_overtemp_taskq", instance
);
556 if ((ixgbe
->overtemp_taskq
= ddi_taskq_create(devinfo
, taskqname
,
557 1, TASKQ_DEFAULTPRI
, 0)) == NULL
) {
558 ixgbe_error(ixgbe
, "overtemp_taskq create failed");
561 ixgbe
->attach_progress
|= ATTACH_PROGRESS_OVERTEMP_TASKQ
;
564 * Create a taskq for processing external PHY interrupts
566 (void) sprintf(taskqname
, "ixgbe%d_phy_taskq", instance
);
567 if ((ixgbe
->phy_taskq
= ddi_taskq_create(devinfo
, taskqname
,
568 1, TASKQ_DEFAULTPRI
, 0)) == NULL
) {
569 ixgbe_error(ixgbe
, "phy_taskq create failed");
572 ixgbe
->attach_progress
|= ATTACH_PROGRESS_PHY_TASKQ
;
575 * Initialize driver parameters
577 if (ixgbe_init_driver_settings(ixgbe
) != IXGBE_SUCCESS
) {
578 ixgbe_error(ixgbe
, "Failed to initialize driver settings");
583 * Initialize mutexes for this device.
584 * Do this before enabling the interrupt handler and
585 * register the softint to avoid the condition where
586 * interrupt handler can try using uninitialized mutex.
588 ixgbe_init_locks(ixgbe
);
589 ixgbe
->attach_progress
|= ATTACH_PROGRESS_LOCKS
;
592 * Initialize chipset hardware
594 if (ixgbe_init(ixgbe
) != IXGBE_SUCCESS
) {
595 ixgbe_error(ixgbe
, "Failed to initialize adapter");
598 ixgbe
->link_check_complete
= B_FALSE
;
599 ixgbe
->link_check_hrtime
= gethrtime() +
600 (IXGBE_LINK_UP_TIME
* 100000000ULL);
601 ixgbe
->attach_progress
|= ATTACH_PROGRESS_INIT
;
603 if (ixgbe_check_acc_handle(ixgbe
->osdep
.cfg_handle
) != DDI_FM_OK
) {
604 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
609 * Initialize adapter capabilities
611 ixgbe_init_params(ixgbe
);
614 * Initialize statistics
616 if (ixgbe_init_stats(ixgbe
) != IXGBE_SUCCESS
) {
617 ixgbe_error(ixgbe
, "Failed to initialize statistics");
620 ixgbe
->attach_progress
|= ATTACH_PROGRESS_STATS
;
623 * Register the driver to the MAC
625 if (ixgbe_register_mac(ixgbe
) != IXGBE_SUCCESS
) {
626 ixgbe_error(ixgbe
, "Failed to register MAC");
629 mac_link_update(ixgbe
->mac_hdl
, LINK_STATE_UNKNOWN
);
630 ixgbe
->attach_progress
|= ATTACH_PROGRESS_MAC
;
632 ixgbe
->periodic_id
= ddi_periodic_add(ixgbe_link_timer
, ixgbe
,
633 IXGBE_CYCLIC_PERIOD
, DDI_IPL_0
);
634 if (ixgbe
->periodic_id
== 0) {
635 ixgbe_error(ixgbe
, "Failed to add the link check timer");
638 ixgbe
->attach_progress
|= ATTACH_PROGRESS_LINK_TIMER
;
641 * Now that mutex locks are initialized, and the chip is also
642 * initialized, enable interrupts.
644 if (ixgbe_enable_intrs(ixgbe
) != IXGBE_SUCCESS
) {
645 ixgbe_error(ixgbe
, "Failed to enable DDI interrupts");
648 ixgbe
->attach_progress
|= ATTACH_PROGRESS_ENABLE_INTR
;
650 ixgbe_log(ixgbe
, "%s", ixgbe_ident
);
651 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_INITIALIZED
);
653 return (DDI_SUCCESS
);
656 ixgbe_unconfigure(devinfo
, ixgbe
);
657 return (DDI_FAILURE
);
661 * ixgbe_detach - Driver detach.
663 * The detach() function is the complement of the attach routine.
664 * If cmd is set to DDI_DETACH, detach() is used to remove the
665 * state associated with a given instance of a device node
666 * prior to the removal of that instance from the system.
668 * The detach() function will be called once for each instance
669 * of the device for which there has been a successful attach()
670 * once there are no longer any opens on the device.
672 * Interrupts routine are disabled, All memory allocated by this
676 ixgbe_detach(dev_info_t
*devinfo
, ddi_detach_cmd_t cmd
)
681 * Check detach command
685 return (DDI_FAILURE
);
688 return (ixgbe_suspend(devinfo
));
695 * Get the pointer to the driver private data structure
697 ixgbe
= (ixgbe_t
*)ddi_get_driver_private(devinfo
);
699 return (DDI_FAILURE
);
702 * If the device is still running, it needs to be stopped first.
703 * This check is necessary because under some specific circumstances,
704 * the detach routine can be called without stopping the interface
707 if (ixgbe
->ixgbe_state
& IXGBE_STARTED
) {
708 atomic_and_32(&ixgbe
->ixgbe_state
, ~IXGBE_STARTED
);
709 mutex_enter(&ixgbe
->gen_lock
);
710 ixgbe_stop(ixgbe
, B_TRUE
);
711 mutex_exit(&ixgbe
->gen_lock
);
712 /* Disable and stop the watchdog timer */
713 ixgbe_disable_watchdog_timer(ixgbe
);
717 * Check if there are still rx buffers held by the upper layer.
718 * If so, fail the detach.
720 if (!ixgbe_rx_drain(ixgbe
))
721 return (DDI_FAILURE
);
724 * Do the remaining unconfigure routines
726 ixgbe_unconfigure(devinfo
, ixgbe
);
728 return (DDI_SUCCESS
);
732 * quiesce(9E) entry point.
734 * This function is called when the system is single-threaded at high
735 * PIL with preemption disabled. Therefore, this function must not be
738 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
739 * DDI_FAILURE indicates an error condition and should almost never happen.
742 ixgbe_quiesce(dev_info_t
*devinfo
)
747 ixgbe
= (ixgbe_t
*)ddi_get_driver_private(devinfo
);
750 return (DDI_FAILURE
);
755 * Disable the adapter interrupts
757 ixgbe_disable_adapter_interrupts(ixgbe
);
760 * Tell firmware driver is no longer in control
762 ixgbe_release_driver_control(hw
);
767 (void) ixgbe_reset_hw(hw
);
772 (void) ixgbe_reset_phy(hw
);
774 return (DDI_SUCCESS
);
778 ixgbe_unconfigure(dev_info_t
*devinfo
, ixgbe_t
*ixgbe
)
783 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_ENABLE_INTR
) {
784 (void) ixgbe_disable_intrs(ixgbe
);
788 * remove the link check timer
790 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_LINK_TIMER
) {
791 if (ixgbe
->periodic_id
!= NULL
) {
792 ddi_periodic_delete(ixgbe
->periodic_id
);
793 ixgbe
->periodic_id
= NULL
;
800 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_MAC
) {
801 (void) mac_unregister(ixgbe
->mac_hdl
);
807 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_STATS
) {
808 kstat_delete((kstat_t
*)ixgbe
->ixgbe_ks
);
812 * Remove interrupt handlers
814 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_ADD_INTR
) {
815 ixgbe_rem_intr_handlers(ixgbe
);
819 * Remove taskq for sfp-status-change
821 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_SFP_TASKQ
) {
822 ddi_taskq_destroy(ixgbe
->sfp_taskq
);
826 * Remove taskq for over-temp
828 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_OVERTEMP_TASKQ
) {
829 ddi_taskq_destroy(ixgbe
->overtemp_taskq
);
833 * Remove taskq for external PHYs
835 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_PHY_TASKQ
) {
836 ddi_taskq_destroy(ixgbe
->phy_taskq
);
842 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_ALLOC_INTR
) {
843 ixgbe_rem_intrs(ixgbe
);
847 * Unregister interrupt callback handler
849 if (ixgbe
->cb_hdl
!= NULL
) {
850 (void) ddi_cb_unregister(ixgbe
->cb_hdl
);
854 * Remove driver properties
856 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_PROPS
) {
857 (void) ddi_prop_remove_all(devinfo
);
863 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_INIT
) {
864 mutex_enter(&ixgbe
->gen_lock
);
865 ixgbe_chip_stop(ixgbe
);
866 mutex_exit(&ixgbe
->gen_lock
);
870 * Free register handle
872 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_REGS_MAP
) {
873 if (ixgbe
->osdep
.reg_handle
!= NULL
)
874 ddi_regs_map_free(&ixgbe
->osdep
.reg_handle
);
878 * Free PCI config handle
880 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_PCI_CONFIG
) {
881 if (ixgbe
->osdep
.cfg_handle
!= NULL
)
882 pci_config_teardown(&ixgbe
->osdep
.cfg_handle
);
888 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_LOCKS
) {
889 ixgbe_destroy_locks(ixgbe
);
893 * Free the rx/tx rings
895 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_ALLOC_RINGS
) {
896 ixgbe_free_rings(ixgbe
);
900 * Unregister FMA capabilities
902 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_FM_INIT
) {
903 ixgbe_fm_fini(ixgbe
);
907 * Free the driver data structure
909 kmem_free(ixgbe
, sizeof (ixgbe_t
));
911 ddi_set_driver_private(devinfo
, NULL
);
915 * ixgbe_register_mac - Register the driver and its function pointers with
919 ixgbe_register_mac(ixgbe_t
*ixgbe
)
921 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
925 if ((mac
= mac_alloc(MAC_VERSION
)) == NULL
)
926 return (IXGBE_FAILURE
);
928 mac
->m_type_ident
= MAC_PLUGIN_IDENT_ETHER
;
929 mac
->m_driver
= ixgbe
;
930 mac
->m_dip
= ixgbe
->dip
;
931 mac
->m_src_addr
= hw
->mac
.addr
;
932 mac
->m_callbacks
= &ixgbe_m_callbacks
;
934 mac
->m_max_sdu
= ixgbe
->default_mtu
;
935 mac
->m_margin
= VLAN_TAGSZ
;
936 mac
->m_priv_props
= ixgbe_priv_props
;
937 mac
->m_v12n
= MAC_VIRT_LEVEL1
;
939 status
= mac_register(mac
, &ixgbe
->mac_hdl
);
943 return ((status
== 0) ? IXGBE_SUCCESS
: IXGBE_FAILURE
);
947 * ixgbe_identify_hardware - Identify the type of the chipset.
950 ixgbe_identify_hardware(ixgbe_t
*ixgbe
)
952 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
953 struct ixgbe_osdep
*osdep
= &ixgbe
->osdep
;
959 pci_config_get16(osdep
->cfg_handle
, PCI_CONF_VENID
);
961 pci_config_get16(osdep
->cfg_handle
, PCI_CONF_DEVID
);
963 pci_config_get8(osdep
->cfg_handle
, PCI_CONF_REVID
);
964 hw
->subsystem_device_id
=
965 pci_config_get16(osdep
->cfg_handle
, PCI_CONF_SUBSYSID
);
966 hw
->subsystem_vendor_id
=
967 pci_config_get16(osdep
->cfg_handle
, PCI_CONF_SUBVENID
);
970 * Set the mac type of the adapter based on the device id
972 if (ixgbe_set_mac_type(hw
) != IXGBE_SUCCESS
) {
973 return (IXGBE_FAILURE
);
977 * Install adapter capabilities
979 switch (hw
->mac
.type
) {
980 case ixgbe_mac_82598EB
:
981 IXGBE_DEBUGLOG_0(ixgbe
, "identify 82598 adapter\n");
982 ixgbe
->capab
= &ixgbe_82598eb_cap
;
984 if (ixgbe_get_media_type(hw
) == ixgbe_media_type_copper
) {
985 ixgbe
->capab
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
986 ixgbe
->capab
->other_intr
|= IXGBE_EICR_GPI_SDP1
;
987 ixgbe
->capab
->other_gpie
|= IXGBE_SDP1_GPIEN
;
991 case ixgbe_mac_82599EB
:
992 IXGBE_DEBUGLOG_0(ixgbe
, "identify 82599 adapter\n");
993 ixgbe
->capab
= &ixgbe_82599eb_cap
;
995 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
) {
996 ixgbe
->capab
->flags
|= IXGBE_FLAG_TEMP_SENSOR_CAPABLE
;
997 ixgbe
->capab
->other_intr
|= IXGBE_EICR_GPI_SDP0
;
998 ixgbe
->capab
->other_gpie
|= IXGBE_SDP0_GPIEN
;
1002 case ixgbe_mac_X540
:
1003 IXGBE_DEBUGLOG_0(ixgbe
, "identify X540 adapter\n");
1004 ixgbe
->capab
= &ixgbe_X540_cap
;
1006 * For now, X540 is all set in its capab structure.
1007 * As other X540 variants show up, things can change here.
1011 case ixgbe_mac_X550
:
1012 case ixgbe_mac_X550EM_x
:
1013 IXGBE_DEBUGLOG_0(ixgbe
, "identify X550 adapter\n");
1014 ixgbe
->capab
= &ixgbe_X550_cap
;
1016 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_X_SFP
)
1017 ixgbe
->capab
->flags
|= IXGBE_FLAG_SFP_PLUG_CAPABLE
;
1020 * Link detection on X552 SFP+ and X552/X557-AT
1022 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_X_SFP
||
1023 hw
->device_id
== IXGBE_DEV_ID_X550EM_X_10G_T
) {
1024 ixgbe
->capab
->other_intr
|=
1025 IXGBE_EIMS_GPI_SDP0_BY_MAC(hw
);
1026 ixgbe
->capab
->other_gpie
|= IXGBE_SDP0_GPIEN_X540
;
1031 IXGBE_DEBUGLOG_1(ixgbe
,
1032 "adapter not supported in ixgbe_identify_hardware(): %d\n",
1034 return (IXGBE_FAILURE
);
1037 return (IXGBE_SUCCESS
);
1041 * ixgbe_regs_map - Map the device registers.
1045 ixgbe_regs_map(ixgbe_t
*ixgbe
)
1047 dev_info_t
*devinfo
= ixgbe
->dip
;
1048 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
1049 struct ixgbe_osdep
*osdep
= &ixgbe
->osdep
;
1053 * First get the size of device registers to be mapped.
1055 if (ddi_dev_regsize(devinfo
, IXGBE_ADAPTER_REGSET
, &mem_size
)
1057 return (IXGBE_FAILURE
);
1061 * Call ddi_regs_map_setup() to map registers
1063 if ((ddi_regs_map_setup(devinfo
, IXGBE_ADAPTER_REGSET
,
1064 (caddr_t
*)&hw
->hw_addr
, 0,
1065 mem_size
, &ixgbe_regs_acc_attr
,
1066 &osdep
->reg_handle
)) != DDI_SUCCESS
) {
1067 return (IXGBE_FAILURE
);
1070 return (IXGBE_SUCCESS
);
1074 * ixgbe_init_properties - Initialize driver properties.
1077 ixgbe_init_properties(ixgbe_t
*ixgbe
)
1080 * Get conf file properties, including link settings
1081 * jumbo frames, ring number, descriptor number, etc.
1083 ixgbe_get_conf(ixgbe
);
1087 * ixgbe_init_driver_settings - Initialize driver settings.
1089 * The settings include hardware function pointers, bus information,
1090 * rx/tx rings settings, link state, and any other parameters that
1091 * need to be setup during driver initialization.
1094 ixgbe_init_driver_settings(ixgbe_t
*ixgbe
)
1096 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
1097 dev_info_t
*devinfo
= ixgbe
->dip
;
1098 ixgbe_rx_ring_t
*rx_ring
;
1099 ixgbe_rx_group_t
*rx_group
;
1100 ixgbe_tx_ring_t
*tx_ring
;
1103 uint32_t ring_per_group
;
1107 * Initialize chipset specific hardware function pointers
1109 if (ixgbe_init_shared_code(hw
) != IXGBE_SUCCESS
) {
1110 return (IXGBE_FAILURE
);
1114 * Get the system page size
1116 ixgbe
->sys_page_size
= ddi_ptob(devinfo
, (ulong_t
)1);
1119 * Set rx buffer size
1121 * The IP header alignment room is counted in the calculation.
1122 * The rx buffer size is in unit of 1K that is required by the
1125 rx_size
= ixgbe
->max_frame_size
+ IPHDR_ALIGN_ROOM
;
1126 ixgbe
->rx_buf_size
= ((rx_size
>> 10) +
1127 ((rx_size
& (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1130 * Set tx buffer size
1132 tx_size
= ixgbe
->max_frame_size
;
1133 ixgbe
->tx_buf_size
= ((tx_size
>> 10) +
1134 ((tx_size
& (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1137 * Initialize rx/tx rings/groups parameters
1139 ring_per_group
= ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
;
1140 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
1141 rx_ring
= &ixgbe
->rx_rings
[i
];
1143 rx_ring
->ixgbe
= ixgbe
;
1144 rx_ring
->group_index
= i
/ ring_per_group
;
1145 rx_ring
->hw_index
= ixgbe_get_hw_rx_index(ixgbe
, i
);
1148 for (i
= 0; i
< ixgbe
->num_rx_groups
; i
++) {
1149 rx_group
= &ixgbe
->rx_groups
[i
];
1150 rx_group
->index
= i
;
1151 rx_group
->ixgbe
= ixgbe
;
1154 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
1155 tx_ring
= &ixgbe
->tx_rings
[i
];
1157 tx_ring
->ixgbe
= ixgbe
;
1158 if (ixgbe
->tx_head_wb_enable
)
1159 tx_ring
->tx_recycle
= ixgbe_tx_recycle_head_wb
;
1161 tx_ring
->tx_recycle
= ixgbe_tx_recycle_legacy
;
1163 tx_ring
->ring_size
= ixgbe
->tx_ring_size
;
1164 tx_ring
->free_list_size
= ixgbe
->tx_ring_size
+
1165 (ixgbe
->tx_ring_size
>> 1);
1169 * Initialize values of interrupt throttling rate
1171 for (i
= 1; i
< MAX_INTR_VECTOR
; i
++)
1172 ixgbe
->intr_throttling
[i
] = ixgbe
->intr_throttling
[0];
1175 * The initial link state should be "unknown"
1177 ixgbe
->link_state
= LINK_STATE_UNKNOWN
;
1179 return (IXGBE_SUCCESS
);
1183 * ixgbe_init_locks - Initialize locks.
1186 ixgbe_init_locks(ixgbe_t
*ixgbe
)
1188 ixgbe_rx_ring_t
*rx_ring
;
1189 ixgbe_tx_ring_t
*tx_ring
;
1192 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
1193 rx_ring
= &ixgbe
->rx_rings
[i
];
1194 mutex_init(&rx_ring
->rx_lock
, NULL
,
1195 MUTEX_DRIVER
, DDI_INTR_PRI(ixgbe
->intr_pri
));
1198 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
1199 tx_ring
= &ixgbe
->tx_rings
[i
];
1200 mutex_init(&tx_ring
->tx_lock
, NULL
,
1201 MUTEX_DRIVER
, DDI_INTR_PRI(ixgbe
->intr_pri
));
1202 mutex_init(&tx_ring
->recycle_lock
, NULL
,
1203 MUTEX_DRIVER
, DDI_INTR_PRI(ixgbe
->intr_pri
));
1204 mutex_init(&tx_ring
->tcb_head_lock
, NULL
,
1205 MUTEX_DRIVER
, DDI_INTR_PRI(ixgbe
->intr_pri
));
1206 mutex_init(&tx_ring
->tcb_tail_lock
, NULL
,
1207 MUTEX_DRIVER
, DDI_INTR_PRI(ixgbe
->intr_pri
));
1210 mutex_init(&ixgbe
->gen_lock
, NULL
,
1211 MUTEX_DRIVER
, DDI_INTR_PRI(ixgbe
->intr_pri
));
1213 mutex_init(&ixgbe
->watchdog_lock
, NULL
,
1214 MUTEX_DRIVER
, DDI_INTR_PRI(ixgbe
->intr_pri
));
1218 * ixgbe_destroy_locks - Destroy locks.
1221 ixgbe_destroy_locks(ixgbe_t
*ixgbe
)
1223 ixgbe_rx_ring_t
*rx_ring
;
1224 ixgbe_tx_ring_t
*tx_ring
;
1227 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
1228 rx_ring
= &ixgbe
->rx_rings
[i
];
1229 mutex_destroy(&rx_ring
->rx_lock
);
1232 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
1233 tx_ring
= &ixgbe
->tx_rings
[i
];
1234 mutex_destroy(&tx_ring
->tx_lock
);
1235 mutex_destroy(&tx_ring
->recycle_lock
);
1236 mutex_destroy(&tx_ring
->tcb_head_lock
);
1237 mutex_destroy(&tx_ring
->tcb_tail_lock
);
1240 mutex_destroy(&ixgbe
->gen_lock
);
1241 mutex_destroy(&ixgbe
->watchdog_lock
);
1245 ixgbe_resume(dev_info_t
*devinfo
)
1250 ixgbe
= (ixgbe_t
*)ddi_get_driver_private(devinfo
);
1252 return (DDI_FAILURE
);
1254 mutex_enter(&ixgbe
->gen_lock
);
1256 if (ixgbe
->ixgbe_state
& IXGBE_STARTED
) {
1257 if (ixgbe_start(ixgbe
, B_FALSE
) != IXGBE_SUCCESS
) {
1258 mutex_exit(&ixgbe
->gen_lock
);
1259 return (DDI_FAILURE
);
1263 * Enable and start the watchdog timer
1265 ixgbe_enable_watchdog_timer(ixgbe
);
1268 atomic_and_32(&ixgbe
->ixgbe_state
, ~IXGBE_SUSPENDED
);
1270 if (ixgbe
->ixgbe_state
& IXGBE_STARTED
) {
1271 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
1272 mac_tx_ring_update(ixgbe
->mac_hdl
,
1273 ixgbe
->tx_rings
[i
].ring_handle
);
1277 mutex_exit(&ixgbe
->gen_lock
);
1279 return (DDI_SUCCESS
);
1283 ixgbe_suspend(dev_info_t
*devinfo
)
1287 ixgbe
= (ixgbe_t
*)ddi_get_driver_private(devinfo
);
1289 return (DDI_FAILURE
);
1291 mutex_enter(&ixgbe
->gen_lock
);
1293 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_SUSPENDED
);
1294 if (!(ixgbe
->ixgbe_state
& IXGBE_STARTED
)) {
1295 mutex_exit(&ixgbe
->gen_lock
);
1296 return (DDI_SUCCESS
);
1298 ixgbe_stop(ixgbe
, B_FALSE
);
1300 mutex_exit(&ixgbe
->gen_lock
);
1303 * Disable and stop the watchdog timer
1305 ixgbe_disable_watchdog_timer(ixgbe
);
1307 return (DDI_SUCCESS
);
1311 * ixgbe_init - Initialize the device.
1314 ixgbe_init(ixgbe_t
*ixgbe
)
1316 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
1317 u8 pbanum
[IXGBE_PBANUM_LENGTH
];
1320 mutex_enter(&ixgbe
->gen_lock
);
1323 * Configure/Initialize hardware
1325 rv
= ixgbe_init_hw(hw
);
1326 if (rv
!= IXGBE_SUCCESS
) {
1330 * The first three errors are not prohibitive to us progressing
1331 * further, and are maily advisory in nature. In the case of a
1332 * SFP module not being present or not deemed supported by the
1333 * common code, we adivse the operator of this fact but carry on
1334 * instead of failing hard, as SFPs can be inserted or replaced
1335 * while the driver is running. In the case of a unknown error,
1336 * we fail-hard, logging the reason and emitting a FMA event.
1338 case IXGBE_ERR_EEPROM_VERSION
:
1340 "This Intel 10Gb Ethernet device is pre-release and"
1341 " contains outdated firmware. Please contact your"
1342 " hardware vendor for a replacement.");
1344 case IXGBE_ERR_SFP_NOT_PRESENT
:
1346 "No SFP+ module detected on this interface. Please "
1347 "install a supported SFP+ module for this "
1348 "interface to become operational.");
1350 case IXGBE_ERR_SFP_NOT_SUPPORTED
:
1352 "Unsupported SFP+ module detected. Please replace "
1353 "it with a supported SFP+ module per Intel "
1354 "documentation, or bypass this check with "
1355 "allow_unsupported_sfp=1 in ixgbe.conf.");
1359 "Failed to initialize hardware. ixgbe_init_hw "
1361 ixgbe_fm_ereport(ixgbe
, DDI_FM_DEVICE_INVAL_STATE
);
1367 * Need to init eeprom before validating the checksum.
1369 if (ixgbe_init_eeprom_params(hw
) < 0) {
1371 "Unable to intitialize the eeprom interface.");
1372 ixgbe_fm_ereport(ixgbe
, DDI_FM_DEVICE_INVAL_STATE
);
1379 if (ixgbe_validate_eeprom_checksum(hw
, NULL
) < 0) {
1381 * Some PCI-E parts fail the first check due to
1382 * the link being in sleep state. Call it again,
1383 * if it fails a second time it's a real issue.
1385 if (ixgbe_validate_eeprom_checksum(hw
, NULL
) < 0) {
1387 "Invalid NVM checksum. Please contact "
1388 "the vendor to update the NVM.");
1389 ixgbe_fm_ereport(ixgbe
, DDI_FM_DEVICE_INVAL_STATE
);
1395 * Setup default flow control thresholds - enable/disable
1396 * & flow control type is controlled by ixgbe.conf
1398 hw
->fc
.high_water
[0] = DEFAULT_FCRTH
;
1399 hw
->fc
.low_water
[0] = DEFAULT_FCRTL
;
1400 hw
->fc
.pause_time
= DEFAULT_FCPAUSE
;
1401 hw
->fc
.send_xon
= B_TRUE
;
1404 * Initialize flow control
1406 (void) ixgbe_start_hw(hw
);
1409 * Initialize link settings
1411 (void) ixgbe_driver_setup_link(ixgbe
, B_FALSE
);
1414 * Initialize the chipset hardware
1416 if (ixgbe_chip_start(ixgbe
) != IXGBE_SUCCESS
) {
1417 ixgbe_fm_ereport(ixgbe
, DDI_FM_DEVICE_INVAL_STATE
);
1422 * Read identifying information and place in devinfo.
1425 (void) ixgbe_read_pba_string(hw
, pbanum
, sizeof (pbanum
));
1426 if (*pbanum
!= '\0') {
1427 (void) ddi_prop_update_string(DDI_DEV_T_NONE
, ixgbe
->dip
,
1428 "printed-board-assembly", (char *)pbanum
);
1431 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
1435 mutex_exit(&ixgbe
->gen_lock
);
1436 return (IXGBE_SUCCESS
);
1442 (void) ixgbe_reset_phy(hw
);
1444 mutex_exit(&ixgbe
->gen_lock
);
1445 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
1446 return (IXGBE_FAILURE
);
1450 * ixgbe_chip_start - Initialize and start the chipset hardware.
1453 ixgbe_chip_start(ixgbe_t
*ixgbe
)
1455 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
1458 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
1461 * Get the mac address
1462 * This function should handle SPARC case correctly.
1464 if (!ixgbe_find_mac_address(ixgbe
)) {
1465 ixgbe_error(ixgbe
, "Failed to get the mac address");
1466 return (IXGBE_FAILURE
);
1470 * Validate the mac address
1472 (void) ixgbe_init_rx_addrs(hw
);
1473 if (!is_valid_mac_addr(hw
->mac
.addr
)) {
1474 ixgbe_error(ixgbe
, "Invalid mac address");
1475 return (IXGBE_FAILURE
);
1479 * Re-enable relaxed ordering for performance. It is disabled
1480 * by default in the hardware init.
1482 if (ixgbe
->relax_order_enable
== B_TRUE
)
1483 ixgbe_enable_relaxed_ordering(hw
);
1486 * Setup adapter interrupt vectors
1488 ixgbe_setup_adapter_vector(ixgbe
);
1491 * Initialize unicast addresses.
1493 ixgbe_init_unicst(ixgbe
);
1496 * Setup and initialize the mctable structures.
1498 ixgbe_setup_multicst(ixgbe
);
1501 * Set interrupt throttling rate
1503 for (i
= 0; i
< ixgbe
->intr_cnt
; i
++) {
1504 IXGBE_WRITE_REG(hw
, IXGBE_EITR(i
), ixgbe
->intr_throttling
[i
]);
1508 * Disable Wake-on-LAN
1510 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
1513 * Some adapters offer Energy Efficient Ethernet (EEE) support.
1514 * Due to issues with EEE in e1000g/igb, we disable this by default
1515 * as a precautionary measure.
1517 * Currently, the only known adapter which supports EEE in the ixgbe
1518 * line is 8086,15AB (IXGBE_DEV_ID_X550EM_X_KR), and only after the
1519 * first revision of it, as well as any X550 with MAC type 6 (non-EM)
1521 (void) ixgbe_setup_eee(hw
, B_FALSE
);
1524 * Turn on any present SFP Tx laser
1526 ixgbe_enable_tx_laser(hw
);
1531 (void) ixgbe_set_phy_power(hw
, B_TRUE
);
1534 * Save the state of the PHY
1536 ixgbe_get_hw_state(ixgbe
);
1539 * Make sure driver has control
1541 ixgbe_get_driver_control(hw
);
1543 return (IXGBE_SUCCESS
);
1547 * ixgbe_chip_stop - Stop the chipset hardware
1550 ixgbe_chip_stop(ixgbe_t
*ixgbe
)
1552 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
1555 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
1558 * Stop interupt generation and disable Tx unit
1560 hw
->adapter_stopped
= B_FALSE
;
1561 (void) ixgbe_stop_adapter(hw
);
1566 (void) ixgbe_reset_hw(hw
);
1571 (void) ixgbe_reset_phy(hw
);
1574 * Enter LPLU (Low Power, Link Up) mode, if available. Avoid resetting
1575 * the PHY while doing so. Else, just power down the PHY.
1577 if (hw
->phy
.ops
.enter_lplu
!= NULL
) {
1578 hw
->phy
.reset_disable
= B_TRUE
;
1579 rv
= hw
->phy
.ops
.enter_lplu(hw
);
1580 if (rv
!= IXGBE_SUCCESS
)
1581 ixgbe_error(ixgbe
, "Error while entering LPLU: %d", rv
);
1582 hw
->phy
.reset_disable
= B_FALSE
;
1584 (void) ixgbe_set_phy_power(hw
, B_FALSE
);
1588 * Turn off any present SFP Tx laser
1589 * Expected for health and safety reasons
1591 ixgbe_disable_tx_laser(hw
);
1594 * Tell firmware driver is no longer in control
1596 ixgbe_release_driver_control(hw
);
1601 * ixgbe_reset - Reset the chipset and re-start the driver.
1603 * It involves stopping and re-starting the chipset,
1604 * and re-configuring the rx/tx rings.
1607 ixgbe_reset(ixgbe_t
*ixgbe
)
1612 * Disable and stop the watchdog timer
1614 ixgbe_disable_watchdog_timer(ixgbe
);
1616 mutex_enter(&ixgbe
->gen_lock
);
1618 ASSERT(ixgbe
->ixgbe_state
& IXGBE_STARTED
);
1619 atomic_and_32(&ixgbe
->ixgbe_state
, ~IXGBE_STARTED
);
1621 ixgbe_stop(ixgbe
, B_FALSE
);
1623 if (ixgbe_start(ixgbe
, B_FALSE
) != IXGBE_SUCCESS
) {
1624 mutex_exit(&ixgbe
->gen_lock
);
1625 return (IXGBE_FAILURE
);
1629 * After resetting, need to recheck the link status.
1631 ixgbe
->link_check_complete
= B_FALSE
;
1632 ixgbe
->link_check_hrtime
= gethrtime() +
1633 (IXGBE_LINK_UP_TIME
* 100000000ULL);
1635 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_STARTED
);
1637 if (!(ixgbe
->ixgbe_state
& IXGBE_SUSPENDED
)) {
1638 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
1639 mac_tx_ring_update(ixgbe
->mac_hdl
,
1640 ixgbe
->tx_rings
[i
].ring_handle
);
1644 mutex_exit(&ixgbe
->gen_lock
);
1647 * Enable and start the watchdog timer
1649 ixgbe_enable_watchdog_timer(ixgbe
);
1651 return (IXGBE_SUCCESS
);
1655 * ixgbe_tx_clean - Clean the pending transmit packets and DMA resources.
1658 ixgbe_tx_clean(ixgbe_t
*ixgbe
)
1660 ixgbe_tx_ring_t
*tx_ring
;
1661 tx_control_block_t
*tcb
;
1662 link_list_t pending_list
;
1666 LINK_LIST_INIT(&pending_list
);
1668 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
1669 tx_ring
= &ixgbe
->tx_rings
[i
];
1671 mutex_enter(&tx_ring
->recycle_lock
);
1674 * Clean the pending tx data - the pending packets in the
1675 * work_list that have no chances to be transmitted again.
1677 * We must ensure the chipset is stopped or the link is down
1678 * before cleaning the transmit packets.
1681 for (j
= 0; j
< tx_ring
->ring_size
; j
++) {
1682 tcb
= tx_ring
->work_list
[j
];
1684 desc_num
+= tcb
->desc_num
;
1686 tx_ring
->work_list
[j
] = NULL
;
1688 ixgbe_free_tcb(tcb
);
1690 LIST_PUSH_TAIL(&pending_list
, &tcb
->link
);
1695 atomic_add_32(&tx_ring
->tbd_free
, desc_num
);
1696 ASSERT(tx_ring
->tbd_free
== tx_ring
->ring_size
);
1699 * Reset the head and tail pointers of the tbd ring;
1700 * Reset the writeback head if it's enable.
1702 tx_ring
->tbd_head
= 0;
1703 tx_ring
->tbd_tail
= 0;
1704 if (ixgbe
->tx_head_wb_enable
)
1705 *tx_ring
->tbd_head_wb
= 0;
1707 IXGBE_WRITE_REG(&ixgbe
->hw
,
1708 IXGBE_TDH(tx_ring
->index
), 0);
1709 IXGBE_WRITE_REG(&ixgbe
->hw
,
1710 IXGBE_TDT(tx_ring
->index
), 0);
1713 mutex_exit(&tx_ring
->recycle_lock
);
1716 * Add the tx control blocks in the pending list to
1719 ixgbe_put_free_list(tx_ring
, &pending_list
);
1724 * ixgbe_tx_drain - Drain the tx rings to allow pending packets to be
1728 ixgbe_tx_drain(ixgbe_t
*ixgbe
)
1730 ixgbe_tx_ring_t
*tx_ring
;
1735 * Wait for a specific time to allow pending tx packets
1736 * to be transmitted.
1738 * Check the counter tbd_free to see if transmission is done.
1739 * No lock protection is needed here.
1741 * Return B_TRUE if all pending packets have been transmitted;
1742 * Otherwise return B_FALSE;
1744 for (i
= 0; i
< TX_DRAIN_TIME
; i
++) {
1747 for (j
= 0; j
< ixgbe
->num_tx_rings
; j
++) {
1748 tx_ring
= &ixgbe
->tx_rings
[j
];
1750 (tx_ring
->tbd_free
== tx_ring
->ring_size
);
1763 * ixgbe_rx_drain - Wait for all rx buffers to be released by upper layer.
1766 ixgbe_rx_drain(ixgbe_t
*ixgbe
)
1768 boolean_t done
= B_TRUE
;
1772 * Polling the rx free list to check if those rx buffers held by
1773 * the upper layer are released.
1775 * Check the counter rcb_free to see if all pending buffers are
1776 * released. No lock protection is needed here.
1778 * Return B_TRUE if all pending buffers have been released;
1779 * Otherwise return B_FALSE;
1781 for (i
= 0; i
< RX_DRAIN_TIME
; i
++) {
1782 done
= (ixgbe
->rcb_pending
== 0);
1794 * ixgbe_start - Start the driver/chipset.
1797 ixgbe_start(ixgbe_t
*ixgbe
, boolean_t alloc_buffer
)
1799 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
1802 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
1805 if (ixgbe_alloc_rx_data(ixgbe
) != IXGBE_SUCCESS
) {
1807 "Failed to allocate software receive rings");
1808 return (IXGBE_FAILURE
);
1811 /* Allocate buffers for all the rx/tx rings */
1812 if (ixgbe_alloc_dma(ixgbe
) != IXGBE_SUCCESS
) {
1813 ixgbe_error(ixgbe
, "Failed to allocate DMA resource");
1814 return (IXGBE_FAILURE
);
1817 ixgbe
->tx_ring_init
= B_TRUE
;
1819 ixgbe
->tx_ring_init
= B_FALSE
;
1822 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++)
1823 mutex_enter(&ixgbe
->rx_rings
[i
].rx_lock
);
1824 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++)
1825 mutex_enter(&ixgbe
->tx_rings
[i
].tx_lock
);
1828 * Start the chipset hardware
1830 if (ixgbe_chip_start(ixgbe
) != IXGBE_SUCCESS
) {
1831 ixgbe_fm_ereport(ixgbe
, DDI_FM_DEVICE_INVAL_STATE
);
1836 * Configure link now for X550
1838 * X550 possesses a LPLU (Low-Power Link Up) mode which keeps the
1839 * resting state of the adapter at a 1Gb FDX speed. Prior to the X550,
1840 * the resting state of the link would be the maximum speed that
1841 * autonegotiation will allow (usually 10Gb, infrastructure allowing)
1842 * so we never bothered with explicitly setting the link to 10Gb as it
1843 * would already be at that state on driver attach. With X550, we must
1844 * trigger a re-negotiation of the link in order to switch from a LPLU
1845 * 1Gb link to 10Gb (cable and link partner permitting.)
1847 if (hw
->mac
.type
== ixgbe_mac_X550
||
1848 hw
->mac
.type
== ixgbe_mac_X550EM_x
) {
1849 (void) ixgbe_driver_setup_link(ixgbe
, B_TRUE
);
1850 ixgbe_get_hw_state(ixgbe
);
1853 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
1858 * Setup the rx/tx rings
1860 ixgbe_setup_rings(ixgbe
);
1863 * ixgbe_start() will be called when resetting, however if reset
1864 * happens, we need to clear the ERROR, STALL and OVERTEMP flags
1865 * before enabling the interrupts.
1867 atomic_and_32(&ixgbe
->ixgbe_state
, ~(IXGBE_ERROR
1868 | IXGBE_STALL
| IXGBE_OVERTEMP
));
1871 * Enable adapter interrupts
1872 * The interrupts must be enabled after the driver state is START
1874 ixgbe_enable_adapter_interrupts(ixgbe
);
1876 for (i
= ixgbe
->num_tx_rings
- 1; i
>= 0; i
--)
1877 mutex_exit(&ixgbe
->tx_rings
[i
].tx_lock
);
1878 for (i
= ixgbe
->num_rx_rings
- 1; i
>= 0; i
--)
1879 mutex_exit(&ixgbe
->rx_rings
[i
].rx_lock
);
1881 return (IXGBE_SUCCESS
);
1884 for (i
= ixgbe
->num_tx_rings
- 1; i
>= 0; i
--)
1885 mutex_exit(&ixgbe
->tx_rings
[i
].tx_lock
);
1886 for (i
= ixgbe
->num_rx_rings
- 1; i
>= 0; i
--)
1887 mutex_exit(&ixgbe
->rx_rings
[i
].rx_lock
);
1889 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
1891 return (IXGBE_FAILURE
);
1895 * ixgbe_stop - Stop the driver/chipset.
1898 ixgbe_stop(ixgbe_t
*ixgbe
, boolean_t free_buffer
)
1902 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
1905 * Disable the adapter interrupts
1907 ixgbe_disable_adapter_interrupts(ixgbe
);
1910 * Drain the pending tx packets
1912 (void) ixgbe_tx_drain(ixgbe
);
1914 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++)
1915 mutex_enter(&ixgbe
->rx_rings
[i
].rx_lock
);
1916 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++)
1917 mutex_enter(&ixgbe
->tx_rings
[i
].tx_lock
);
1920 * Stop the chipset hardware
1922 ixgbe_chip_stop(ixgbe
);
1924 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
1925 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
1929 * Clean the pending tx data/resources
1931 ixgbe_tx_clean(ixgbe
);
1933 for (i
= ixgbe
->num_tx_rings
- 1; i
>= 0; i
--)
1934 mutex_exit(&ixgbe
->tx_rings
[i
].tx_lock
);
1935 for (i
= ixgbe
->num_rx_rings
- 1; i
>= 0; i
--)
1936 mutex_exit(&ixgbe
->rx_rings
[i
].rx_lock
);
1938 if (ixgbe
->link_state
== LINK_STATE_UP
) {
1939 ixgbe
->link_state
= LINK_STATE_UNKNOWN
;
1940 mac_link_update(ixgbe
->mac_hdl
, ixgbe
->link_state
);
1945 * Release the DMA/memory resources of rx/tx rings
1947 ixgbe_free_dma(ixgbe
);
1948 ixgbe_free_rx_data(ixgbe
);
1953 * ixgbe_cbfunc - Driver interface for generic DDI callbacks
1957 ixgbe_cbfunc(dev_info_t
*dip
, ddi_cb_action_t cbaction
, void *cbarg
,
1958 void *arg1
, void *arg2
)
1960 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg1
;
1965 case DDI_CB_INTR_ADD
:
1966 case DDI_CB_INTR_REMOVE
:
1967 count
= (int)(uintptr_t)cbarg
;
1968 ASSERT(ixgbe
->intr_type
== DDI_INTR_TYPE_MSIX
);
1969 DTRACE_PROBE2(ixgbe__irm__callback
, int, count
,
1970 int, ixgbe
->intr_cnt
);
1971 if (ixgbe_intr_adjust(ixgbe
, cbaction
, count
) !=
1974 "IRM CB: Failed to adjust interrupts");
1979 IXGBE_DEBUGLOG_1(ixgbe
, "DDI CB: action 0x%x NOT supported",
1981 return (DDI_ENOTSUP
);
1983 return (DDI_SUCCESS
);
1985 return (DDI_FAILURE
);
1989 * ixgbe_intr_adjust - Adjust interrupt to respond to IRM request.
1992 ixgbe_intr_adjust(ixgbe_t
*ixgbe
, ddi_cb_action_t cbaction
, int count
)
1997 return (DDI_SUCCESS
);
1999 if ((cbaction
== DDI_CB_INTR_ADD
&&
2000 ixgbe
->intr_cnt
+ count
> ixgbe
->intr_cnt_max
) ||
2001 (cbaction
== DDI_CB_INTR_REMOVE
&&
2002 ixgbe
->intr_cnt
- count
< ixgbe
->intr_cnt_min
))
2003 return (DDI_FAILURE
);
2005 if (!(ixgbe
->ixgbe_state
& IXGBE_STARTED
)) {
2006 return (DDI_FAILURE
);
2009 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++)
2010 mac_ring_intr_set(ixgbe
->rx_rings
[i
].ring_handle
, NULL
);
2011 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++)
2012 mac_ring_intr_set(ixgbe
->tx_rings
[i
].ring_handle
, NULL
);
2014 mutex_enter(&ixgbe
->gen_lock
);
2015 ixgbe
->ixgbe_state
&= ~IXGBE_STARTED
;
2016 ixgbe
->ixgbe_state
|= IXGBE_INTR_ADJUST
;
2017 ixgbe
->ixgbe_state
|= IXGBE_SUSPENDED
;
2018 mac_link_update(ixgbe
->mac_hdl
, LINK_STATE_UNKNOWN
);
2020 ixgbe_stop(ixgbe
, B_FALSE
);
2022 * Disable interrupts
2024 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_ENABLE_INTR
) {
2025 rc
= ixgbe_disable_intrs(ixgbe
);
2026 ASSERT(rc
== IXGBE_SUCCESS
);
2028 ixgbe
->attach_progress
&= ~ATTACH_PROGRESS_ENABLE_INTR
;
2031 * Remove interrupt handlers
2033 if (ixgbe
->attach_progress
& ATTACH_PROGRESS_ADD_INTR
) {
2034 ixgbe_rem_intr_handlers(ixgbe
);
2036 ixgbe
->attach_progress
&= ~ATTACH_PROGRESS_ADD_INTR
;
2041 bzero(&ixgbe
->vect_map
, sizeof (ixgbe
->vect_map
));
2043 case DDI_CB_INTR_ADD
:
2044 rc
= ddi_intr_alloc(ixgbe
->dip
, ixgbe
->htable
,
2045 DDI_INTR_TYPE_MSIX
, ixgbe
->intr_cnt
, count
, &actual
,
2046 DDI_INTR_ALLOC_NORMAL
);
2047 if (rc
!= DDI_SUCCESS
|| actual
!= count
) {
2048 ixgbe_log(ixgbe
, "Adjust interrupts failed."
2049 "return: %d, irm cb size: %d, actual: %d",
2051 goto intr_adjust_fail
;
2053 ixgbe
->intr_cnt
+= count
;
2056 case DDI_CB_INTR_REMOVE
:
2057 for (i
= ixgbe
->intr_cnt
- count
;
2058 i
< ixgbe
->intr_cnt
; i
++) {
2059 rc
= ddi_intr_free(ixgbe
->htable
[i
]);
2060 ixgbe
->htable
[i
] = NULL
;
2061 if (rc
!= DDI_SUCCESS
) {
2062 ixgbe_log(ixgbe
, "Adjust interrupts failed."
2063 "return: %d, irm cb size: %d, actual: %d",
2065 goto intr_adjust_fail
;
2068 ixgbe
->intr_cnt
-= count
;
2073 * Get priority for first vector, assume remaining are all the same
2075 rc
= ddi_intr_get_pri(ixgbe
->htable
[0], &ixgbe
->intr_pri
);
2076 if (rc
!= DDI_SUCCESS
) {
2078 "Get interrupt priority failed: %d", rc
);
2079 goto intr_adjust_fail
;
2081 rc
= ddi_intr_get_cap(ixgbe
->htable
[0], &ixgbe
->intr_cap
);
2082 if (rc
!= DDI_SUCCESS
) {
2083 ixgbe_log(ixgbe
, "Get interrupt cap failed: %d", rc
);
2084 goto intr_adjust_fail
;
2086 ixgbe
->attach_progress
|= ATTACH_PROGRESS_ALLOC_INTR
;
2089 * Map rings to interrupt vectors
2091 if (ixgbe_map_intrs_to_vectors(ixgbe
) != IXGBE_SUCCESS
) {
2093 "IRM CB: Failed to map interrupts to vectors");
2094 goto intr_adjust_fail
;
2098 * Add interrupt handlers
2100 if (ixgbe_add_intr_handlers(ixgbe
) != IXGBE_SUCCESS
) {
2101 ixgbe_error(ixgbe
, "IRM CB: Failed to add interrupt handlers");
2102 goto intr_adjust_fail
;
2104 ixgbe
->attach_progress
|= ATTACH_PROGRESS_ADD_INTR
;
2107 * Now that mutex locks are initialized, and the chip is also
2108 * initialized, enable interrupts.
2110 if (ixgbe_enable_intrs(ixgbe
) != IXGBE_SUCCESS
) {
2111 ixgbe_error(ixgbe
, "IRM CB: Failed to enable DDI interrupts");
2112 goto intr_adjust_fail
;
2114 ixgbe
->attach_progress
|= ATTACH_PROGRESS_ENABLE_INTR
;
2115 if (ixgbe_start(ixgbe
, B_FALSE
) != IXGBE_SUCCESS
) {
2116 ixgbe_error(ixgbe
, "IRM CB: Failed to start");
2117 goto intr_adjust_fail
;
2119 ixgbe
->ixgbe_state
&= ~IXGBE_INTR_ADJUST
;
2120 ixgbe
->ixgbe_state
&= ~IXGBE_SUSPENDED
;
2121 ixgbe
->ixgbe_state
|= IXGBE_STARTED
;
2122 mutex_exit(&ixgbe
->gen_lock
);
2124 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
2125 mac_ring_intr_set(ixgbe
->rx_rings
[i
].ring_handle
,
2126 ixgbe
->htable
[ixgbe
->rx_rings
[i
].intr_vector
]);
2128 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
2129 mac_ring_intr_set(ixgbe
->tx_rings
[i
].ring_handle
,
2130 ixgbe
->htable
[ixgbe
->tx_rings
[i
].intr_vector
]);
2133 /* Wakeup all Tx rings */
2134 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
2135 mac_tx_ring_update(ixgbe
->mac_hdl
,
2136 ixgbe
->tx_rings
[i
].ring_handle
);
2139 IXGBE_DEBUGLOG_3(ixgbe
,
2140 "IRM CB: interrupts new value: 0x%x(0x%x:0x%x).",
2141 ixgbe
->intr_cnt
, ixgbe
->intr_cnt_min
, ixgbe
->intr_cnt_max
);
2142 return (DDI_SUCCESS
);
2145 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
2146 mutex_exit(&ixgbe
->gen_lock
);
2147 return (DDI_FAILURE
);
2151 * ixgbe_intr_cb_register - Register interrupt callback function.
2154 ixgbe_intr_cb_register(ixgbe_t
*ixgbe
)
2156 if (ddi_cb_register(ixgbe
->dip
, DDI_CB_FLAG_INTR
, ixgbe_cbfunc
,
2157 ixgbe
, NULL
, &ixgbe
->cb_hdl
) != DDI_SUCCESS
) {
2158 return (IXGBE_FAILURE
);
2160 IXGBE_DEBUGLOG_0(ixgbe
, "Interrupt callback function registered.");
2161 return (IXGBE_SUCCESS
);
2165 * ixgbe_alloc_rings - Allocate memory space for rx/tx rings.
2168 ixgbe_alloc_rings(ixgbe_t
*ixgbe
)
2171 * Allocate memory space for rx rings
2173 ixgbe
->rx_rings
= kmem_zalloc(
2174 sizeof (ixgbe_rx_ring_t
) * ixgbe
->num_rx_rings
,
2177 if (ixgbe
->rx_rings
== NULL
) {
2178 return (IXGBE_FAILURE
);
2182 * Allocate memory space for tx rings
2184 ixgbe
->tx_rings
= kmem_zalloc(
2185 sizeof (ixgbe_tx_ring_t
) * ixgbe
->num_tx_rings
,
2188 if (ixgbe
->tx_rings
== NULL
) {
2189 kmem_free(ixgbe
->rx_rings
,
2190 sizeof (ixgbe_rx_ring_t
) * ixgbe
->num_rx_rings
);
2191 ixgbe
->rx_rings
= NULL
;
2192 return (IXGBE_FAILURE
);
2196 * Allocate memory space for rx ring groups
2198 ixgbe
->rx_groups
= kmem_zalloc(
2199 sizeof (ixgbe_rx_group_t
) * ixgbe
->num_rx_groups
,
2202 if (ixgbe
->rx_groups
== NULL
) {
2203 kmem_free(ixgbe
->rx_rings
,
2204 sizeof (ixgbe_rx_ring_t
) * ixgbe
->num_rx_rings
);
2205 kmem_free(ixgbe
->tx_rings
,
2206 sizeof (ixgbe_tx_ring_t
) * ixgbe
->num_tx_rings
);
2207 ixgbe
->rx_rings
= NULL
;
2208 ixgbe
->tx_rings
= NULL
;
2209 return (IXGBE_FAILURE
);
2212 return (IXGBE_SUCCESS
);
2216 * ixgbe_free_rings - Free the memory space of rx/tx rings.
2219 ixgbe_free_rings(ixgbe_t
*ixgbe
)
2221 if (ixgbe
->rx_rings
!= NULL
) {
2222 kmem_free(ixgbe
->rx_rings
,
2223 sizeof (ixgbe_rx_ring_t
) * ixgbe
->num_rx_rings
);
2224 ixgbe
->rx_rings
= NULL
;
2227 if (ixgbe
->tx_rings
!= NULL
) {
2228 kmem_free(ixgbe
->tx_rings
,
2229 sizeof (ixgbe_tx_ring_t
) * ixgbe
->num_tx_rings
);
2230 ixgbe
->tx_rings
= NULL
;
2233 if (ixgbe
->rx_groups
!= NULL
) {
2234 kmem_free(ixgbe
->rx_groups
,
2235 sizeof (ixgbe_rx_group_t
) * ixgbe
->num_rx_groups
);
2236 ixgbe
->rx_groups
= NULL
;
2241 ixgbe_alloc_rx_data(ixgbe_t
*ixgbe
)
2243 ixgbe_rx_ring_t
*rx_ring
;
2246 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
2247 rx_ring
= &ixgbe
->rx_rings
[i
];
2248 if (ixgbe_alloc_rx_ring_data(rx_ring
) != IXGBE_SUCCESS
)
2249 goto alloc_rx_rings_failure
;
2251 return (IXGBE_SUCCESS
);
2253 alloc_rx_rings_failure
:
2254 ixgbe_free_rx_data(ixgbe
);
2255 return (IXGBE_FAILURE
);
2259 ixgbe_free_rx_data(ixgbe_t
*ixgbe
)
2261 ixgbe_rx_ring_t
*rx_ring
;
2262 ixgbe_rx_data_t
*rx_data
;
2265 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
2266 rx_ring
= &ixgbe
->rx_rings
[i
];
2268 mutex_enter(&ixgbe
->rx_pending_lock
);
2269 rx_data
= rx_ring
->rx_data
;
2271 if (rx_data
!= NULL
) {
2272 rx_data
->flag
|= IXGBE_RX_STOPPED
;
2274 if (rx_data
->rcb_pending
== 0) {
2275 ixgbe_free_rx_ring_data(rx_data
);
2276 rx_ring
->rx_data
= NULL
;
2280 mutex_exit(&ixgbe
->rx_pending_lock
);
2285 * ixgbe_setup_rings - Setup rx/tx rings.
2288 ixgbe_setup_rings(ixgbe_t
*ixgbe
)
2291 * Setup the rx/tx rings, including the following:
2293 * 1. Setup the descriptor ring and the control block buffers;
2294 * 2. Initialize necessary registers for receive/transmit;
2295 * 3. Initialize software pointers/parameters for receive/transmit;
2297 ixgbe_setup_rx(ixgbe
);
2299 ixgbe_setup_tx(ixgbe
);
2303 ixgbe_setup_rx_ring(ixgbe_rx_ring_t
*rx_ring
)
2305 ixgbe_t
*ixgbe
= rx_ring
->ixgbe
;
2306 ixgbe_rx_data_t
*rx_data
= rx_ring
->rx_data
;
2307 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2308 rx_control_block_t
*rcb
;
2309 union ixgbe_adv_rx_desc
*rbd
;
2316 ASSERT(mutex_owned(&rx_ring
->rx_lock
));
2317 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
2319 for (i
= 0; i
< ixgbe
->rx_ring_size
; i
++) {
2320 rcb
= rx_data
->work_list
[i
];
2321 rbd
= &rx_data
->rbd_ring
[i
];
2323 rbd
->read
.pkt_addr
= rcb
->rx_buf
.dma_address
;
2324 rbd
->read
.hdr_addr
= NULL
;
2328 * Initialize the length register
2330 size
= rx_data
->ring_size
* sizeof (union ixgbe_adv_rx_desc
);
2331 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(rx_ring
->hw_index
), size
);
2334 * Initialize the base address registers
2336 buf_low
= (uint32_t)rx_data
->rbd_area
.dma_address
;
2337 buf_high
= (uint32_t)(rx_data
->rbd_area
.dma_address
>> 32);
2338 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(rx_ring
->hw_index
), buf_high
);
2339 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(rx_ring
->hw_index
), buf_low
);
2342 * Setup head & tail pointers
2344 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->hw_index
),
2345 rx_data
->ring_size
- 1);
2346 IXGBE_WRITE_REG(hw
, IXGBE_RDH(rx_ring
->hw_index
), 0);
2348 rx_data
->rbd_next
= 0;
2349 rx_data
->lro_first
= 0;
2352 * Setup the Receive Descriptor Control Register (RXDCTL)
2353 * PTHRESH=32 descriptors (half the internal cache)
2354 * HTHRESH=0 descriptors (to minimize latency on fetch)
2355 * WTHRESH defaults to 1 (writeback each descriptor)
2357 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(rx_ring
->hw_index
));
2358 reg_val
|= IXGBE_RXDCTL_ENABLE
; /* enable queue */
2360 /* Not a valid value for 82599, X540 or X550 */
2361 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2362 reg_val
|= 0x0020; /* pthresh */
2364 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(rx_ring
->hw_index
), reg_val
);
2366 if (hw
->mac
.type
== ixgbe_mac_82599EB
||
2367 hw
->mac
.type
== ixgbe_mac_X540
||
2368 hw
->mac
.type
== ixgbe_mac_X550
||
2369 hw
->mac
.type
== ixgbe_mac_X550EM_x
) {
2370 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2371 reg_val
|= (IXGBE_RDRXCTL_CRCSTRIP
| IXGBE_RDRXCTL_AGGDIS
);
2372 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, reg_val
);
2376 * Setup the Split and Replication Receive Control Register.
2377 * Set the rx buffer size and the advanced descriptor type.
2379 reg_val
= (ixgbe
->rx_buf_size
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
) |
2380 IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2381 reg_val
|= IXGBE_SRRCTL_DROP_EN
;
2382 IXGBE_WRITE_REG(hw
, IXGBE_SRRCTL(rx_ring
->hw_index
), reg_val
);
2386 ixgbe_setup_rx(ixgbe_t
*ixgbe
)
2388 ixgbe_rx_ring_t
*rx_ring
;
2389 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2391 uint32_t ring_mapping
;
2393 uint32_t psrtype_rss_bit
;
2396 * Ensure that Rx is disabled while setting up
2397 * the Rx unit and Rx descriptor ring(s)
2399 ixgbe_disable_rx(hw
);
2401 /* PSRTYPE must be configured for 82599 */
2402 if (ixgbe
->classify_mode
!= IXGBE_CLASSIFY_VMDQ
&&
2403 ixgbe
->classify_mode
!= IXGBE_CLASSIFY_VMDQ_RSS
) {
2404 reg_val
= IXGBE_PSRTYPE_TCPHDR
| IXGBE_PSRTYPE_UDPHDR
|
2405 IXGBE_PSRTYPE_IPV4HDR
| IXGBE_PSRTYPE_IPV6HDR
;
2406 reg_val
|= IXGBE_PSRTYPE_L2HDR
;
2407 reg_val
|= 0x80000000;
2408 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(0), reg_val
);
2410 if (ixgbe
->num_rx_groups
> 32) {
2411 psrtype_rss_bit
= 0x20000000;
2413 psrtype_rss_bit
= 0x40000000;
2415 for (i
= 0; i
< ixgbe
->capab
->max_rx_grp_num
; i
++) {
2416 reg_val
= IXGBE_PSRTYPE_TCPHDR
| IXGBE_PSRTYPE_UDPHDR
|
2417 IXGBE_PSRTYPE_IPV4HDR
| IXGBE_PSRTYPE_IPV6HDR
;
2418 reg_val
|= IXGBE_PSRTYPE_L2HDR
;
2419 reg_val
|= psrtype_rss_bit
;
2420 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(i
), reg_val
);
2425 * Set filter control in FCTRL to determine types of packets are passed
2427 * - Pass broadcast packets.
2428 * - Do not pass flow control pause frames (82598-specific)
2430 reg_val
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2431 reg_val
|= IXGBE_FCTRL_BAM
; /* Broadcast Accept Mode */
2432 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2433 reg_val
|= IXGBE_FCTRL_DPF
; /* Discard Pause Frames */
2435 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, reg_val
);
2438 * Hardware checksum settings
2440 if (ixgbe
->rx_hcksum_enable
) {
2441 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2442 reg_val
|= IXGBE_RXCSUM_IPPCSE
; /* IP checksum */
2443 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, reg_val
);
2447 * Setup VMDq and RSS for multiple receive queues
2449 switch (ixgbe
->classify_mode
) {
2450 case IXGBE_CLASSIFY_RSS
:
2452 * One group, only RSS is needed when more than
2455 ixgbe_setup_rss(ixgbe
);
2458 case IXGBE_CLASSIFY_VMDQ
:
2460 * Multiple groups, each group has one ring,
2461 * only VMDq is needed.
2463 ixgbe_setup_vmdq(ixgbe
);
2466 case IXGBE_CLASSIFY_VMDQ_RSS
:
2468 * Multiple groups and multiple rings, both
2469 * VMDq and RSS are needed.
2471 ixgbe_setup_vmdq_rss(ixgbe
);
2479 * Enable the receive unit. This must be done after filter
2480 * control is set in FCTRL. On 82598, we disable the descriptor monitor.
2481 * 82598 is the only adapter which defines this RXCTRL option.
2483 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2484 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2485 reg_val
|= IXGBE_RXCTRL_DMBYPS
; /* descriptor monitor bypass */
2486 reg_val
|= IXGBE_RXCTRL_RXEN
;
2487 (void) ixgbe_enable_rx_dma(hw
, reg_val
);
2490 * ixgbe_setup_rx_ring must be called after configuring RXCTRL
2492 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
2493 rx_ring
= &ixgbe
->rx_rings
[i
];
2494 ixgbe_setup_rx_ring(rx_ring
);
2498 * Setup the per-ring statistics mapping.
2501 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
2502 index
= ixgbe
->rx_rings
[i
].hw_index
;
2503 ring_mapping
= IXGBE_READ_REG(hw
, IXGBE_RQSMR(index
>> 2));
2504 ring_mapping
|= (i
& 0xF) << (8 * (index
& 0x3));
2505 IXGBE_WRITE_REG(hw
, IXGBE_RQSMR(index
>> 2), ring_mapping
);
2509 * The Max Frame Size in MHADD/MAXFRS will be internally increased
2510 * by four bytes if the packet has a VLAN field, so includes MTU,
2511 * ethernet header and frame check sequence.
2512 * Register is MAXFRS in 82599.
2514 reg_val
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2515 reg_val
&= ~IXGBE_MHADD_MFS_MASK
;
2516 reg_val
|= (ixgbe
->default_mtu
+ sizeof (struct ether_header
)
2517 + ETHERFCSL
) << IXGBE_MHADD_MFS_SHIFT
;
2518 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, reg_val
);
2521 * Setup Jumbo Frame enable bit
2523 reg_val
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2524 if (ixgbe
->default_mtu
> ETHERMTU
)
2525 reg_val
|= IXGBE_HLREG0_JUMBOEN
;
2527 reg_val
&= ~IXGBE_HLREG0_JUMBOEN
;
2528 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, reg_val
);
2531 * Setup RSC for multiple receive queues.
2533 if (ixgbe
->lro_enable
) {
2534 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
2536 * Make sure rx_buf_size * MAXDESC not greater
2538 * Intel recommends 4 for MAXDESC field value.
2540 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(i
));
2541 reg_val
|= IXGBE_RSCCTL_RSCEN
;
2542 if (ixgbe
->rx_buf_size
== IXGBE_PKG_BUF_16k
)
2543 reg_val
|= IXGBE_RSCCTL_MAXDESC_1
;
2545 reg_val
|= IXGBE_RSCCTL_MAXDESC_4
;
2546 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(i
), reg_val
);
2549 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RSCDBU
);
2550 reg_val
|= IXGBE_RSCDBU_RSCACKDIS
;
2551 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
, reg_val
);
2553 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2554 reg_val
|= IXGBE_RDRXCTL_RSCACKC
;
2555 reg_val
|= IXGBE_RDRXCTL_FCOE_WRFIX
;
2556 reg_val
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2558 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, reg_val
);
2563 ixgbe_setup_tx_ring(ixgbe_tx_ring_t
*tx_ring
)
2565 ixgbe_t
*ixgbe
= tx_ring
->ixgbe
;
2566 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2572 ASSERT(mutex_owned(&tx_ring
->tx_lock
));
2573 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
2576 * Initialize the length register
2578 size
= tx_ring
->ring_size
* sizeof (union ixgbe_adv_tx_desc
);
2579 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(tx_ring
->index
), size
);
2582 * Initialize the base address registers
2584 buf_low
= (uint32_t)tx_ring
->tbd_area
.dma_address
;
2585 buf_high
= (uint32_t)(tx_ring
->tbd_area
.dma_address
>> 32);
2586 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(tx_ring
->index
), buf_low
);
2587 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(tx_ring
->index
), buf_high
);
2590 * Setup head & tail pointers
2592 IXGBE_WRITE_REG(hw
, IXGBE_TDH(tx_ring
->index
), 0);
2593 IXGBE_WRITE_REG(hw
, IXGBE_TDT(tx_ring
->index
), 0);
2596 * Setup head write-back
2598 if (ixgbe
->tx_head_wb_enable
) {
2600 * The memory of the head write-back is allocated using
2601 * the extra tbd beyond the tail of the tbd ring.
2603 tx_ring
->tbd_head_wb
= (uint32_t *)
2604 ((uintptr_t)tx_ring
->tbd_area
.address
+ size
);
2605 *tx_ring
->tbd_head_wb
= 0;
2607 buf_low
= (uint32_t)
2608 (tx_ring
->tbd_area
.dma_address
+ size
);
2609 buf_high
= (uint32_t)
2610 ((tx_ring
->tbd_area
.dma_address
+ size
) >> 32);
2612 /* Set the head write-back enable bit */
2613 buf_low
|= IXGBE_TDWBAL_HEAD_WB_ENABLE
;
2615 IXGBE_WRITE_REG(hw
, IXGBE_TDWBAL(tx_ring
->index
), buf_low
);
2616 IXGBE_WRITE_REG(hw
, IXGBE_TDWBAH(tx_ring
->index
), buf_high
);
2619 * Turn off relaxed ordering for head write back or it will
2620 * cause problems with the tx recycling
2623 reg_val
= (hw
->mac
.type
== ixgbe_mac_82598EB
) ?
2624 IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(tx_ring
->index
)) :
2625 IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(tx_ring
->index
));
2626 reg_val
&= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN
;
2627 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2629 IXGBE_DCA_TXCTRL(tx_ring
->index
), reg_val
);
2632 IXGBE_DCA_TXCTRL_82599(tx_ring
->index
), reg_val
);
2635 tx_ring
->tbd_head_wb
= NULL
;
2638 tx_ring
->tbd_head
= 0;
2639 tx_ring
->tbd_tail
= 0;
2640 tx_ring
->tbd_free
= tx_ring
->ring_size
;
2642 if (ixgbe
->tx_ring_init
== B_TRUE
) {
2643 tx_ring
->tcb_head
= 0;
2644 tx_ring
->tcb_tail
= 0;
2645 tx_ring
->tcb_free
= tx_ring
->free_list_size
;
2649 * Initialize the s/w context structure
2651 bzero(&tx_ring
->tx_context
, sizeof (ixgbe_tx_context_t
));
2655 ixgbe_setup_tx(ixgbe_t
*ixgbe
)
2657 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2658 ixgbe_tx_ring_t
*tx_ring
;
2660 uint32_t ring_mapping
;
2663 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
2664 tx_ring
= &ixgbe
->tx_rings
[i
];
2665 ixgbe_setup_tx_ring(tx_ring
);
2669 * Setup the per-ring statistics mapping.
2672 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
2673 ring_mapping
|= (i
& 0xF) << (8 * (i
& 0x3));
2674 if ((i
& 0x3) == 0x3) {
2675 switch (hw
->mac
.type
) {
2676 case ixgbe_mac_82598EB
:
2677 IXGBE_WRITE_REG(hw
, IXGBE_TQSMR(i
>> 2),
2681 case ixgbe_mac_82599EB
:
2682 case ixgbe_mac_X540
:
2683 case ixgbe_mac_X550
:
2684 case ixgbe_mac_X550EM_x
:
2685 IXGBE_WRITE_REG(hw
, IXGBE_TQSM(i
>> 2),
2697 switch (hw
->mac
.type
) {
2698 case ixgbe_mac_82598EB
:
2699 IXGBE_WRITE_REG(hw
, IXGBE_TQSMR(i
>> 2), ring_mapping
);
2702 case ixgbe_mac_82599EB
:
2703 case ixgbe_mac_X540
:
2704 case ixgbe_mac_X550
:
2705 case ixgbe_mac_X550EM_x
:
2706 IXGBE_WRITE_REG(hw
, IXGBE_TQSM(i
>> 2), ring_mapping
);
2715 * Enable CRC appending and TX padding (for short tx frames)
2717 reg_val
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2718 reg_val
|= IXGBE_HLREG0_TXCRCEN
| IXGBE_HLREG0_TXPADEN
;
2719 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, reg_val
);
2722 * enable DMA for 82599, X540 and X550 parts
2724 if (hw
->mac
.type
== ixgbe_mac_82599EB
||
2725 hw
->mac
.type
== ixgbe_mac_X540
||
2726 hw
->mac
.type
== ixgbe_mac_X550
||
2727 hw
->mac
.type
== ixgbe_mac_X550EM_x
) {
2728 /* DMATXCTL.TE must be set after all Tx config is complete */
2729 reg_val
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2730 reg_val
|= IXGBE_DMATXCTL_TE
;
2731 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, reg_val
);
2733 /* Disable arbiter to set MTQC */
2734 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2735 reg_val
|= IXGBE_RTTDCS_ARBDIS
;
2736 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, reg_val
);
2737 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2738 reg_val
&= ~IXGBE_RTTDCS_ARBDIS
;
2739 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, reg_val
);
2743 * Enabling tx queues ..
2744 * For 82599 must be done after DMATXCTL.TE is set
2746 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
2747 tx_ring
= &ixgbe
->tx_rings
[i
];
2748 reg_val
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(tx_ring
->index
));
2749 reg_val
|= IXGBE_TXDCTL_ENABLE
;
2750 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(tx_ring
->index
), reg_val
);
2755 * ixgbe_setup_rss - Setup receive-side scaling feature.
2758 ixgbe_setup_rss(ixgbe_t
*ixgbe
)
2760 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2764 * Initialize RETA/ERETA table
2766 ixgbe_setup_rss_table(ixgbe
);
2769 * Enable RSS & perform hash on these packet types
2771 mrqc
= IXGBE_MRQC_RSSEN
|
2772 IXGBE_MRQC_RSS_FIELD_IPV4
|
2773 IXGBE_MRQC_RSS_FIELD_IPV4_TCP
|
2774 IXGBE_MRQC_RSS_FIELD_IPV4_UDP
|
2775 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
|
2776 IXGBE_MRQC_RSS_FIELD_IPV6_EX
|
2777 IXGBE_MRQC_RSS_FIELD_IPV6
|
2778 IXGBE_MRQC_RSS_FIELD_IPV6_TCP
|
2779 IXGBE_MRQC_RSS_FIELD_IPV6_UDP
|
2780 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP
;
2781 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2785 * ixgbe_setup_vmdq - Setup MAC classification feature
2788 ixgbe_setup_vmdq(ixgbe_t
*ixgbe
)
2790 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2791 uint32_t vmdctl
, i
, vtctl
;
2794 * Setup the VMDq Control register, enable VMDq based on
2795 * packet destination MAC address:
2797 switch (hw
->mac
.type
) {
2798 case ixgbe_mac_82598EB
:
2801 * VMDq Filter = 0; MAC filtering
2802 * Default VMDq output index = 0;
2804 vmdctl
= IXGBE_VMD_CTL_VMDQ_EN
;
2805 IXGBE_WRITE_REG(hw
, IXGBE_VMD_CTL
, vmdctl
);
2808 case ixgbe_mac_82599EB
:
2809 case ixgbe_mac_X540
:
2810 case ixgbe_mac_X550
:
2811 case ixgbe_mac_X550EM_x
:
2815 vmdctl
= IXGBE_MRQC_VMDQEN
;
2816 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, vmdctl
);
2818 for (i
= 0; i
< hw
->mac
.num_rar_entries
; i
++) {
2819 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(i
), 0);
2820 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(i
), 0);
2824 * Enable Virtualization and Replication.
2826 vtctl
= IXGBE_VT_CTL_VT_ENABLE
| IXGBE_VT_CTL_REPLEN
;
2827 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vtctl
);
2830 * Enable receiving packets to all VFs
2832 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), IXGBE_VFRE_ENABLE_ALL
);
2833 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), IXGBE_VFRE_ENABLE_ALL
);
2842 * ixgbe_setup_vmdq_rss - Setup both vmdq feature and rss feature.
2845 ixgbe_setup_vmdq_rss(ixgbe_t
*ixgbe
)
2847 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2849 uint32_t vtctl
, vmdctl
;
2852 * Initialize RETA/ERETA table
2854 ixgbe_setup_rss_table(ixgbe
);
2857 * Enable and setup RSS and VMDq
2859 switch (hw
->mac
.type
) {
2860 case ixgbe_mac_82598EB
:
2862 * Enable RSS & Setup RSS Hash functions
2864 mrqc
= IXGBE_MRQC_RSSEN
|
2865 IXGBE_MRQC_RSS_FIELD_IPV4
|
2866 IXGBE_MRQC_RSS_FIELD_IPV4_TCP
|
2867 IXGBE_MRQC_RSS_FIELD_IPV4_UDP
|
2868 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
|
2869 IXGBE_MRQC_RSS_FIELD_IPV6_EX
|
2870 IXGBE_MRQC_RSS_FIELD_IPV6
|
2871 IXGBE_MRQC_RSS_FIELD_IPV6_TCP
|
2872 IXGBE_MRQC_RSS_FIELD_IPV6_UDP
|
2873 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP
;
2874 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2877 * Enable and Setup VMDq
2878 * VMDq Filter = 0; MAC filtering
2879 * Default VMDq output index = 0;
2881 vmdctl
= IXGBE_VMD_CTL_VMDQ_EN
;
2882 IXGBE_WRITE_REG(hw
, IXGBE_VMD_CTL
, vmdctl
);
2885 case ixgbe_mac_82599EB
:
2886 case ixgbe_mac_X540
:
2887 case ixgbe_mac_X550
:
2888 case ixgbe_mac_X550EM_x
:
2890 * Enable RSS & Setup RSS Hash functions
2892 mrqc
= IXGBE_MRQC_RSS_FIELD_IPV4
|
2893 IXGBE_MRQC_RSS_FIELD_IPV4_TCP
|
2894 IXGBE_MRQC_RSS_FIELD_IPV4_UDP
|
2895 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
|
2896 IXGBE_MRQC_RSS_FIELD_IPV6_EX
|
2897 IXGBE_MRQC_RSS_FIELD_IPV6
|
2898 IXGBE_MRQC_RSS_FIELD_IPV6_TCP
|
2899 IXGBE_MRQC_RSS_FIELD_IPV6_UDP
|
2900 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP
;
2905 if (ixgbe
->num_rx_groups
> 32) {
2906 mrqc
= mrqc
| IXGBE_MRQC_VMDQRSS64EN
;
2908 mrqc
= mrqc
| IXGBE_MRQC_VMDQRSS32EN
;
2911 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2913 for (i
= 0; i
< hw
->mac
.num_rar_entries
; i
++) {
2914 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(i
), 0);
2915 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(i
), 0);
2924 if (hw
->mac
.type
== ixgbe_mac_82599EB
||
2925 hw
->mac
.type
== ixgbe_mac_X540
||
2926 hw
->mac
.type
== ixgbe_mac_X550
||
2927 hw
->mac
.type
== ixgbe_mac_X550EM_x
) {
2929 * Enable Virtualization and Replication.
2931 vtctl
= IXGBE_VT_CTL_VT_ENABLE
| IXGBE_VT_CTL_REPLEN
;
2932 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vtctl
);
2935 * Enable receiving packets to all VFs
2937 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), IXGBE_VFRE_ENABLE_ALL
);
2938 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), IXGBE_VFRE_ENABLE_ALL
);
2943 * ixgbe_setup_rss_table - Setup RSS table
2946 ixgbe_setup_rss_table(ixgbe_t
*ixgbe
)
2948 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
2952 uint32_t ring_per_group
;
2954 uint32_t table_size
;
2955 uint32_t index_mult
;
2959 * Set multiplier for RETA setup and table size based on MAC type.
2960 * RETA table sizes vary by model:
2962 * 82598, 82599, X540: 128 table entries.
2963 * X550: 512 table entries.
2967 switch (ixgbe
->hw
.mac
.type
) {
2968 case ixgbe_mac_82598EB
:
2971 case ixgbe_mac_X550
:
2972 case ixgbe_mac_X550EM_x
:
2980 * Fill out RSS redirection table. The configuation of the indices is
2981 * hardware-dependent.
2983 * 82598: 8 bits wide containing two 4 bit RSS indices
2984 * 82599, X540: 8 bits wide containing one 4 bit RSS index
2985 * X550: 8 bits wide containing one 6 bit RSS index
2988 ring_per_group
= ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
;
2990 for (i
= 0, j
= 0; i
< table_size
; i
++, j
++) {
2991 if (j
== ring_per_group
) j
= 0;
2994 * The low 8 bits are for hash value (n+0);
2995 * The next 8 bits are for hash value (n+1), etc.
2997 ring
= (j
* index_mult
);
2999 reta
= reta
| (((uint32_t)ring
) << 24);
3003 * The first 128 table entries are programmed into the
3004 * RETA register, with any beyond that (eg; on X550)
3008 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
3010 IXGBE_WRITE_REG(hw
, IXGBE_ERETA((i
>> 2) - 32),
3017 * Fill out hash function seeds with a random constant
3019 for (i
= 0; i
< 10; i
++) {
3020 (void) random_get_pseudo_bytes((uint8_t *)&random
,
3022 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), random
);
3026 * Disable Packet Checksum to enable RSS for multiple receive queues.
3027 * It is an adapter hardware limitation that Packet Checksum is
3028 * mutually exclusive with RSS.
3030 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
3031 rxcsum
|= IXGBE_RXCSUM_PCSD
;
3032 rxcsum
&= ~IXGBE_RXCSUM_IPPCSE
;
3033 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
3037 * ixgbe_init_unicst - Initialize the unicast addresses.
3040 ixgbe_init_unicst(ixgbe_t
*ixgbe
)
3042 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3046 * Here we should consider two situations:
3048 * 1. Chipset is initialized at the first time,
3049 * Clear all the multiple unicast addresses.
3051 * 2. Chipset is reset
3052 * Recover the multiple unicast addresses from the
3053 * software data structure to the RAR registers.
3055 if (!ixgbe
->unicst_init
) {
3057 * Initialize the multiple unicast addresses
3059 ixgbe
->unicst_total
= hw
->mac
.num_rar_entries
;
3060 ixgbe
->unicst_avail
= ixgbe
->unicst_total
;
3061 for (slot
= 0; slot
< ixgbe
->unicst_total
; slot
++) {
3062 mac_addr
= ixgbe
->unicst_addr
[slot
].mac
.addr
;
3063 bzero(mac_addr
, ETHERADDRL
);
3064 (void) ixgbe_set_rar(hw
, slot
, mac_addr
, NULL
, NULL
);
3065 ixgbe
->unicst_addr
[slot
].mac
.set
= 0;
3067 ixgbe
->unicst_init
= B_TRUE
;
3069 /* Re-configure the RAR registers */
3070 for (slot
= 0; slot
< ixgbe
->unicst_total
; slot
++) {
3071 mac_addr
= ixgbe
->unicst_addr
[slot
].mac
.addr
;
3072 if (ixgbe
->unicst_addr
[slot
].mac
.set
== 1) {
3073 (void) ixgbe_set_rar(hw
, slot
, mac_addr
,
3074 ixgbe
->unicst_addr
[slot
].mac
.group_index
,
3077 bzero(mac_addr
, ETHERADDRL
);
3078 (void) ixgbe_set_rar(hw
, slot
, mac_addr
,
3086 * ixgbe_unicst_find - Find the slot for the specified unicast address
3089 ixgbe_unicst_find(ixgbe_t
*ixgbe
, const uint8_t *mac_addr
)
3093 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
3095 for (slot
= 0; slot
< ixgbe
->unicst_total
; slot
++) {
3096 if (bcmp(ixgbe
->unicst_addr
[slot
].mac
.addr
,
3097 mac_addr
, ETHERADDRL
) == 0)
3105 * ixgbe_multicst_add - Add a multicst address.
3108 ixgbe_multicst_add(ixgbe_t
*ixgbe
, const uint8_t *multiaddr
)
3110 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
3112 if ((multiaddr
[0] & 01) == 0) {
3116 if (ixgbe
->mcast_count
>= MAX_NUM_MULTICAST_ADDRESSES
) {
3121 &ixgbe
->mcast_table
[ixgbe
->mcast_count
], ETHERADDRL
);
3122 ixgbe
->mcast_count
++;
3125 * Update the multicast table in the hardware
3127 ixgbe_setup_multicst(ixgbe
);
3129 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
3130 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_DEGRADED
);
3138 * ixgbe_multicst_remove - Remove a multicst address.
3141 ixgbe_multicst_remove(ixgbe_t
*ixgbe
, const uint8_t *multiaddr
)
3145 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
3147 for (i
= 0; i
< ixgbe
->mcast_count
; i
++) {
3148 if (bcmp(multiaddr
, &ixgbe
->mcast_table
[i
],
3150 for (i
++; i
< ixgbe
->mcast_count
; i
++) {
3151 ixgbe
->mcast_table
[i
- 1] =
3152 ixgbe
->mcast_table
[i
];
3154 ixgbe
->mcast_count
--;
3160 * Update the multicast table in the hardware
3162 ixgbe_setup_multicst(ixgbe
);
3164 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
3165 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_DEGRADED
);
3173 * ixgbe_setup_multicast - Setup multicast data structures.
3175 * This routine initializes all of the multicast related structures
3176 * and save them in the hardware registers.
3179 ixgbe_setup_multicst(ixgbe_t
*ixgbe
)
3181 uint8_t *mc_addr_list
;
3182 uint32_t mc_addr_count
;
3183 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3185 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
3187 ASSERT(ixgbe
->mcast_count
<= MAX_NUM_MULTICAST_ADDRESSES
);
3189 mc_addr_list
= (uint8_t *)ixgbe
->mcast_table
;
3190 mc_addr_count
= ixgbe
->mcast_count
;
3193 * Update the multicast addresses to the MTA registers
3195 (void) ixgbe_update_mc_addr_list(hw
, mc_addr_list
, mc_addr_count
,
3196 ixgbe_mc_table_itr
, TRUE
);
3200 * ixgbe_setup_vmdq_rss_conf - Configure vmdq and rss (number and mode).
3202 * Configure the rx classification mode (vmdq & rss) and vmdq & rss numbers.
3203 * Different chipsets may have different allowed configuration of vmdq and rss.
3206 ixgbe_setup_vmdq_rss_conf(ixgbe_t
*ixgbe
)
3208 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3209 uint32_t ring_per_group
;
3211 switch (hw
->mac
.type
) {
3212 case ixgbe_mac_82598EB
:
3214 * 82598 supports the following combination:
3215 * vmdq no. x rss no.
3218 * However 8 rss queue per pool (vmdq) is sufficient for
3221 ring_per_group
= ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
;
3222 if (ixgbe
->num_rx_groups
> 4) {
3223 ixgbe
->num_rx_rings
= ixgbe
->num_rx_groups
;
3225 ixgbe
->num_rx_rings
= ixgbe
->num_rx_groups
*
3226 min(8, ring_per_group
);
3231 case ixgbe_mac_82599EB
:
3232 case ixgbe_mac_X540
:
3233 case ixgbe_mac_X550
:
3234 case ixgbe_mac_X550EM_x
:
3236 * 82599 supports the following combination:
3237 * vmdq no. x rss no.
3241 * However 8 rss queue per pool (vmdq) is sufficient for
3244 * For now, treat X540 and X550 like the 82599.
3246 ring_per_group
= ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
;
3247 if (ixgbe
->num_rx_groups
== 1) {
3248 ixgbe
->num_rx_rings
= min(8, ring_per_group
);
3249 } else if (ixgbe
->num_rx_groups
<= 32) {
3250 ixgbe
->num_rx_rings
= ixgbe
->num_rx_groups
*
3251 min(4, ring_per_group
);
3252 } else if (ixgbe
->num_rx_groups
<= 64) {
3253 ixgbe
->num_rx_rings
= ixgbe
->num_rx_groups
*
3254 min(2, ring_per_group
);
3262 ring_per_group
= ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
;
3264 if (ixgbe
->num_rx_groups
== 1 && ring_per_group
== 1) {
3265 ixgbe
->classify_mode
= IXGBE_CLASSIFY_NONE
;
3266 } else if (ixgbe
->num_rx_groups
!= 1 && ring_per_group
== 1) {
3267 ixgbe
->classify_mode
= IXGBE_CLASSIFY_VMDQ
;
3268 } else if (ixgbe
->num_rx_groups
!= 1 && ring_per_group
!= 1) {
3269 ixgbe
->classify_mode
= IXGBE_CLASSIFY_VMDQ_RSS
;
3271 ixgbe
->classify_mode
= IXGBE_CLASSIFY_RSS
;
3274 IXGBE_DEBUGLOG_2(ixgbe
, "rx group number:%d, rx ring number:%d",
3275 ixgbe
->num_rx_groups
, ixgbe
->num_rx_rings
);
3279 * ixgbe_get_conf - Get driver configurations set in driver.conf.
3281 * This routine gets user-configured values out of the configuration
3284 * For each configurable value, there is a minimum, a maximum, and a
3286 * If user does not configure a value, use the default.
3287 * If user configures below the minimum, use the minumum.
3288 * If user configures above the maximum, use the maxumum.
3291 ixgbe_get_conf(ixgbe_t
*ixgbe
)
3293 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3294 uint32_t flow_control
;
3297 * ixgbe driver supports the following user configurations:
3299 * Jumbo frame configuration:
3302 * Ethernet flow control configuration:
3305 * Multiple rings configurations:
3311 * Call ixgbe_get_prop() to get the value for a specific
3312 * configuration parameter.
3316 * Jumbo frame configuration - max_frame_size controls host buffer
3317 * allocation, so includes MTU, ethernet header, vlan tag and
3318 * frame check sequence.
3320 ixgbe
->default_mtu
= ixgbe_get_prop(ixgbe
, PROP_DEFAULT_MTU
,
3321 MIN_MTU
, ixgbe
->capab
->max_mtu
, DEFAULT_MTU
);
3323 ixgbe
->max_frame_size
= ixgbe
->default_mtu
+
3324 sizeof (struct ether_vlan_header
) + ETHERFCSL
;
3327 * Ethernet flow control configuration
3329 flow_control
= ixgbe_get_prop(ixgbe
, PROP_FLOW_CONTROL
,
3330 ixgbe_fc_none
, 3, ixgbe_fc_none
);
3331 if (flow_control
== 3)
3332 flow_control
= ixgbe_fc_default
;
3335 * fc.requested mode is what the user requests. After autoneg,
3336 * fc.current_mode will be the flow_control mode that was negotiated.
3338 hw
->fc
.requested_mode
= flow_control
;
3341 * Multiple rings configurations
3343 ixgbe
->num_tx_rings
= ixgbe_get_prop(ixgbe
, PROP_TX_QUEUE_NUM
,
3344 ixgbe
->capab
->min_tx_que_num
,
3345 ixgbe
->capab
->max_tx_que_num
,
3346 ixgbe
->capab
->def_tx_que_num
);
3347 ixgbe
->tx_ring_size
= ixgbe_get_prop(ixgbe
, PROP_TX_RING_SIZE
,
3348 MIN_TX_RING_SIZE
, MAX_TX_RING_SIZE
, DEFAULT_TX_RING_SIZE
);
3350 ixgbe
->num_rx_rings
= ixgbe_get_prop(ixgbe
, PROP_RX_QUEUE_NUM
,
3351 ixgbe
->capab
->min_rx_que_num
,
3352 ixgbe
->capab
->max_rx_que_num
,
3353 ixgbe
->capab
->def_rx_que_num
);
3354 ixgbe
->rx_ring_size
= ixgbe_get_prop(ixgbe
, PROP_RX_RING_SIZE
,
3355 MIN_RX_RING_SIZE
, MAX_RX_RING_SIZE
, DEFAULT_RX_RING_SIZE
);
3358 * Multiple groups configuration
3360 ixgbe
->num_rx_groups
= ixgbe_get_prop(ixgbe
, PROP_RX_GROUP_NUM
,
3361 ixgbe
->capab
->min_rx_grp_num
, ixgbe
->capab
->max_rx_grp_num
,
3362 ixgbe
->capab
->def_rx_grp_num
);
3364 ixgbe
->mr_enable
= ixgbe_get_prop(ixgbe
, PROP_MR_ENABLE
,
3365 0, 1, DEFAULT_MR_ENABLE
);
3367 if (ixgbe
->mr_enable
== B_FALSE
) {
3368 ixgbe
->num_tx_rings
= 1;
3369 ixgbe
->num_rx_rings
= 1;
3370 ixgbe
->num_rx_groups
= 1;
3371 ixgbe
->classify_mode
= IXGBE_CLASSIFY_NONE
;
3373 ixgbe
->num_rx_rings
= ixgbe
->num_rx_groups
*
3374 max(ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
, 1);
3376 * The combination of num_rx_rings and num_rx_groups
3377 * may be not supported by h/w. We need to adjust
3378 * them to appropriate values.
3380 ixgbe_setup_vmdq_rss_conf(ixgbe
);
3384 * Tunable used to force an interrupt type. The only use is
3385 * for testing of the lesser interrupt types.
3386 * 0 = don't force interrupt type
3387 * 1 = force interrupt type MSI-X
3388 * 2 = force interrupt type MSI
3389 * 3 = force interrupt type Legacy
3391 ixgbe
->intr_force
= ixgbe_get_prop(ixgbe
, PROP_INTR_FORCE
,
3392 IXGBE_INTR_NONE
, IXGBE_INTR_LEGACY
, IXGBE_INTR_NONE
);
3394 ixgbe
->tx_hcksum_enable
= ixgbe_get_prop(ixgbe
, PROP_TX_HCKSUM_ENABLE
,
3395 0, 1, DEFAULT_TX_HCKSUM_ENABLE
);
3396 ixgbe
->rx_hcksum_enable
= ixgbe_get_prop(ixgbe
, PROP_RX_HCKSUM_ENABLE
,
3397 0, 1, DEFAULT_RX_HCKSUM_ENABLE
);
3398 ixgbe
->lso_enable
= ixgbe_get_prop(ixgbe
, PROP_LSO_ENABLE
,
3399 0, 1, DEFAULT_LSO_ENABLE
);
3400 ixgbe
->lro_enable
= ixgbe_get_prop(ixgbe
, PROP_LRO_ENABLE
,
3401 0, 1, DEFAULT_LRO_ENABLE
);
3402 ixgbe
->tx_head_wb_enable
= ixgbe_get_prop(ixgbe
, PROP_TX_HEAD_WB_ENABLE
,
3403 0, 1, DEFAULT_TX_HEAD_WB_ENABLE
);
3404 ixgbe
->relax_order_enable
= ixgbe_get_prop(ixgbe
,
3405 PROP_RELAX_ORDER_ENABLE
, 0, 1, DEFAULT_RELAX_ORDER_ENABLE
);
3407 /* Head Write Back not recommended for 82599, X540 and X550 */
3408 if (hw
->mac
.type
== ixgbe_mac_82599EB
||
3409 hw
->mac
.type
== ixgbe_mac_X540
||
3410 hw
->mac
.type
== ixgbe_mac_X550
||
3411 hw
->mac
.type
== ixgbe_mac_X550EM_x
) {
3412 ixgbe
->tx_head_wb_enable
= B_FALSE
;
3416 * ixgbe LSO needs the tx h/w checksum support.
3417 * LSO will be disabled if tx h/w checksum is not
3420 if (ixgbe
->tx_hcksum_enable
== B_FALSE
) {
3421 ixgbe
->lso_enable
= B_FALSE
;
3425 * ixgbe LRO needs the rx h/w checksum support.
3426 * LRO will be disabled if rx h/w checksum is not
3429 if (ixgbe
->rx_hcksum_enable
== B_FALSE
) {
3430 ixgbe
->lro_enable
= B_FALSE
;
3434 * ixgbe LRO only supported by 82599, X540 and X550
3436 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3437 ixgbe
->lro_enable
= B_FALSE
;
3439 ixgbe
->tx_copy_thresh
= ixgbe_get_prop(ixgbe
, PROP_TX_COPY_THRESHOLD
,
3440 MIN_TX_COPY_THRESHOLD
, MAX_TX_COPY_THRESHOLD
,
3441 DEFAULT_TX_COPY_THRESHOLD
);
3442 ixgbe
->tx_recycle_thresh
= ixgbe_get_prop(ixgbe
,
3443 PROP_TX_RECYCLE_THRESHOLD
, MIN_TX_RECYCLE_THRESHOLD
,
3444 MAX_TX_RECYCLE_THRESHOLD
, DEFAULT_TX_RECYCLE_THRESHOLD
);
3445 ixgbe
->tx_overload_thresh
= ixgbe_get_prop(ixgbe
,
3446 PROP_TX_OVERLOAD_THRESHOLD
, MIN_TX_OVERLOAD_THRESHOLD
,
3447 MAX_TX_OVERLOAD_THRESHOLD
, DEFAULT_TX_OVERLOAD_THRESHOLD
);
3448 ixgbe
->tx_resched_thresh
= ixgbe_get_prop(ixgbe
,
3449 PROP_TX_RESCHED_THRESHOLD
, MIN_TX_RESCHED_THRESHOLD
,
3450 MAX_TX_RESCHED_THRESHOLD
, DEFAULT_TX_RESCHED_THRESHOLD
);
3452 ixgbe
->rx_copy_thresh
= ixgbe_get_prop(ixgbe
, PROP_RX_COPY_THRESHOLD
,
3453 MIN_RX_COPY_THRESHOLD
, MAX_RX_COPY_THRESHOLD
,
3454 DEFAULT_RX_COPY_THRESHOLD
);
3455 ixgbe
->rx_limit_per_intr
= ixgbe_get_prop(ixgbe
, PROP_RX_LIMIT_PER_INTR
,
3456 MIN_RX_LIMIT_PER_INTR
, MAX_RX_LIMIT_PER_INTR
,
3457 DEFAULT_RX_LIMIT_PER_INTR
);
3459 ixgbe
->intr_throttling
[0] = ixgbe_get_prop(ixgbe
, PROP_INTR_THROTTLING
,
3460 ixgbe
->capab
->min_intr_throttle
,
3461 ixgbe
->capab
->max_intr_throttle
,
3462 ixgbe
->capab
->def_intr_throttle
);
3464 * 82599, X540 and X550 require the interrupt throttling rate is
3465 * a multiple of 8. This is enforced by the register definiton.
3467 if (hw
->mac
.type
== ixgbe_mac_82599EB
||
3468 hw
->mac
.type
== ixgbe_mac_X540
||
3469 hw
->mac
.type
== ixgbe_mac_X550
||
3470 hw
->mac
.type
== ixgbe_mac_X550EM_x
)
3471 ixgbe
->intr_throttling
[0] = ixgbe
->intr_throttling
[0] & 0xFF8;
3473 hw
->allow_unsupported_sfp
= ixgbe_get_prop(ixgbe
,
3474 PROP_ALLOW_UNSUPPORTED_SFP
, 0, 1, DEFAULT_ALLOW_UNSUPPORTED_SFP
);
3478 ixgbe_init_params(ixgbe_t
*ixgbe
)
3480 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3481 ixgbe_link_speed speeds_supported
= 0;
3482 boolean_t negotiate
;
3485 * Get a list of speeds the adapter supports. If the hw struct hasn't
3486 * been populated with this information yet, retrieve it from the
3487 * adapter and save it to our own variable.
3489 * On certain adapters, such as ones which use SFPs, the contents of
3490 * hw->phy.speeds_supported (and hw->phy.autoneg_advertised) are not
3491 * updated, so we must rely on calling ixgbe_get_link_capabilities()
3492 * in order to ascertain the speeds which we are capable of supporting,
3493 * and in the case of SFP-equipped adapters, which speed we are
3494 * advertising. If ixgbe_get_link_capabilities() fails for some reason,
3495 * we'll go with a default list of speeds as a last resort.
3497 speeds_supported
= hw
->phy
.speeds_supported
;
3499 if (speeds_supported
== 0) {
3500 if (ixgbe_get_link_capabilities(hw
, &speeds_supported
,
3501 &negotiate
) != IXGBE_SUCCESS
) {
3502 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3504 IXGBE_LINK_SPEED_82598_AUTONEG
;
3507 IXGBE_LINK_SPEED_82599_AUTONEG
;
3511 ixgbe
->speeds_supported
= speeds_supported
;
3514 * By default, all supported speeds are enabled and advertised.
3516 if (speeds_supported
& IXGBE_LINK_SPEED_10GB_FULL
) {
3517 ixgbe
->param_en_10000fdx_cap
= 1;
3518 ixgbe
->param_adv_10000fdx_cap
= 1;
3520 ixgbe
->param_en_10000fdx_cap
= 0;
3521 ixgbe
->param_adv_10000fdx_cap
= 0;
3524 if (speeds_supported
& IXGBE_LINK_SPEED_5GB_FULL
) {
3525 ixgbe
->param_en_5000fdx_cap
= 1;
3526 ixgbe
->param_adv_5000fdx_cap
= 1;
3528 ixgbe
->param_en_5000fdx_cap
= 0;
3529 ixgbe
->param_adv_5000fdx_cap
= 0;
3532 if (speeds_supported
& IXGBE_LINK_SPEED_2_5GB_FULL
) {
3533 ixgbe
->param_en_2500fdx_cap
= 1;
3534 ixgbe
->param_adv_2500fdx_cap
= 1;
3536 ixgbe
->param_en_2500fdx_cap
= 0;
3537 ixgbe
->param_adv_2500fdx_cap
= 0;
3540 if (speeds_supported
& IXGBE_LINK_SPEED_1GB_FULL
) {
3541 ixgbe
->param_en_1000fdx_cap
= 1;
3542 ixgbe
->param_adv_1000fdx_cap
= 1;
3544 ixgbe
->param_en_1000fdx_cap
= 0;
3545 ixgbe
->param_adv_1000fdx_cap
= 0;
3548 if (speeds_supported
& IXGBE_LINK_SPEED_100_FULL
) {
3549 ixgbe
->param_en_100fdx_cap
= 1;
3550 ixgbe
->param_adv_100fdx_cap
= 1;
3552 ixgbe
->param_en_100fdx_cap
= 0;
3553 ixgbe
->param_adv_100fdx_cap
= 0;
3556 ixgbe
->param_pause_cap
= 1;
3557 ixgbe
->param_asym_pause_cap
= 1;
3558 ixgbe
->param_rem_fault
= 0;
3560 ixgbe
->param_adv_autoneg_cap
= 1;
3561 ixgbe
->param_adv_pause_cap
= 1;
3562 ixgbe
->param_adv_asym_pause_cap
= 1;
3563 ixgbe
->param_adv_rem_fault
= 0;
3565 ixgbe
->param_lp_10000fdx_cap
= 0;
3566 ixgbe
->param_lp_5000fdx_cap
= 0;
3567 ixgbe
->param_lp_2500fdx_cap
= 0;
3568 ixgbe
->param_lp_1000fdx_cap
= 0;
3569 ixgbe
->param_lp_100fdx_cap
= 0;
3570 ixgbe
->param_lp_autoneg_cap
= 0;
3571 ixgbe
->param_lp_pause_cap
= 0;
3572 ixgbe
->param_lp_asym_pause_cap
= 0;
3573 ixgbe
->param_lp_rem_fault
= 0;
3577 * ixgbe_get_prop - Get a property value out of the configuration file
3580 * Caller provides the name of the property, a default value, a minimum
3581 * value, and a maximum value.
3583 * Return configured value of the property, with default, minimum and
3584 * maximum properly applied.
3587 ixgbe_get_prop(ixgbe_t
*ixgbe
,
3588 char *propname
, /* name of the property */
3589 int minval
, /* minimum acceptable value */
3590 int maxval
, /* maximim acceptable value */
3591 int defval
) /* default value */
3596 * Call ddi_prop_get_int() to read the conf settings
3598 value
= ddi_prop_get_int(DDI_DEV_T_ANY
, ixgbe
->dip
,
3599 DDI_PROP_DONTPASS
, propname
, defval
);
3610 * ixgbe_driver_setup_link - Using the link properties to setup the link.
3613 ixgbe_driver_setup_link(ixgbe_t
*ixgbe
, boolean_t setup_hw
)
3615 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3616 ixgbe_link_speed advertised
= 0;
3619 * Assemble a list of enabled speeds to auto-negotiate with.
3621 if (ixgbe
->param_en_10000fdx_cap
== 1)
3622 advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
3624 if (ixgbe
->param_en_5000fdx_cap
== 1)
3625 advertised
|= IXGBE_LINK_SPEED_5GB_FULL
;
3627 if (ixgbe
->param_en_2500fdx_cap
== 1)
3628 advertised
|= IXGBE_LINK_SPEED_2_5GB_FULL
;
3630 if (ixgbe
->param_en_1000fdx_cap
== 1)
3631 advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
3633 if (ixgbe
->param_en_100fdx_cap
== 1)
3634 advertised
|= IXGBE_LINK_SPEED_100_FULL
;
3637 * As a last resort, autoneg with a default list of speeds.
3639 if (ixgbe
->param_adv_autoneg_cap
== 1 && advertised
== 0) {
3640 ixgbe_notice(ixgbe
, "Invalid link settings. Setting link "
3641 "to autonegotiate with full capabilities.");
3643 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3644 advertised
= IXGBE_LINK_SPEED_82598_AUTONEG
;
3646 advertised
= IXGBE_LINK_SPEED_82599_AUTONEG
;
3650 if (ixgbe_setup_link(&ixgbe
->hw
, advertised
,
3651 ixgbe
->param_adv_autoneg_cap
) != IXGBE_SUCCESS
) {
3652 ixgbe_notice(ixgbe
, "Setup link failed on this "
3654 return (IXGBE_FAILURE
);
3658 return (IXGBE_SUCCESS
);
3662 * ixgbe_driver_link_check - Link status processing.
3664 * This function can be called in both kernel context and interrupt context
3667 ixgbe_driver_link_check(ixgbe_t
*ixgbe
)
3669 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3670 ixgbe_link_speed speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3671 boolean_t link_up
= B_FALSE
;
3672 boolean_t link_changed
= B_FALSE
;
3674 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
3676 (void) ixgbe_check_link(hw
, &speed
, &link_up
, B_FALSE
);
3678 ixgbe
->link_check_complete
= B_TRUE
;
3680 /* Link is up, enable flow control settings */
3681 (void) ixgbe_fc_enable(hw
);
3684 * The Link is up, check whether it was marked as down earlier
3686 if (ixgbe
->link_state
!= LINK_STATE_UP
) {
3688 case IXGBE_LINK_SPEED_10GB_FULL
:
3689 ixgbe
->link_speed
= SPEED_10GB
;
3691 case IXGBE_LINK_SPEED_5GB_FULL
:
3692 ixgbe
->link_speed
= SPEED_5GB
;
3694 case IXGBE_LINK_SPEED_2_5GB_FULL
:
3695 ixgbe
->link_speed
= SPEED_2_5GB
;
3697 case IXGBE_LINK_SPEED_1GB_FULL
:
3698 ixgbe
->link_speed
= SPEED_1GB
;
3700 case IXGBE_LINK_SPEED_100_FULL
:
3701 ixgbe
->link_speed
= SPEED_100
;
3703 ixgbe
->link_duplex
= LINK_DUPLEX_FULL
;
3704 ixgbe
->link_state
= LINK_STATE_UP
;
3705 link_changed
= B_TRUE
;
3708 if (ixgbe
->link_check_complete
== B_TRUE
||
3709 (ixgbe
->link_check_complete
== B_FALSE
&&
3710 gethrtime() >= ixgbe
->link_check_hrtime
)) {
3712 * The link is really down
3714 ixgbe
->link_check_complete
= B_TRUE
;
3716 if (ixgbe
->link_state
!= LINK_STATE_DOWN
) {
3717 ixgbe
->link_speed
= 0;
3718 ixgbe
->link_duplex
= LINK_DUPLEX_UNKNOWN
;
3719 ixgbe
->link_state
= LINK_STATE_DOWN
;
3720 link_changed
= B_TRUE
;
3726 * If we are in an interrupt context, need to re-enable the
3727 * interrupt, which was automasked
3729 if (servicing_interrupt() != 0) {
3730 ixgbe
->eims
|= IXGBE_EICR_LSC
;
3731 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, ixgbe
->eims
);
3735 mac_link_update(ixgbe
->mac_hdl
, ixgbe
->link_state
);
3740 * ixgbe_sfp_check - sfp module processing done in taskq only for 82599.
3743 ixgbe_sfp_check(void *arg
)
3745 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg
;
3746 uint32_t eicr
= ixgbe
->eicr
;
3747 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3749 mutex_enter(&ixgbe
->gen_lock
);
3750 if (eicr
& IXGBE_EICR_GPI_SDP1_BY_MAC(hw
)) {
3751 /* clear the interrupt */
3752 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1_BY_MAC(hw
));
3754 /* if link up, do multispeed fiber setup */
3755 (void) ixgbe_setup_link(hw
, IXGBE_LINK_SPEED_82599_AUTONEG
,
3757 ixgbe_driver_link_check(ixgbe
);
3758 ixgbe_get_hw_state(ixgbe
);
3759 } else if (eicr
& IXGBE_EICR_GPI_SDP2_BY_MAC(hw
)) {
3760 /* clear the interrupt */
3761 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2_BY_MAC(hw
));
3763 /* if link up, do sfp module setup */
3764 (void) hw
->mac
.ops
.setup_sfp(hw
);
3766 /* do multispeed fiber setup */
3767 (void) ixgbe_setup_link(hw
, IXGBE_LINK_SPEED_82599_AUTONEG
,
3769 ixgbe_driver_link_check(ixgbe
);
3770 ixgbe_get_hw_state(ixgbe
);
3772 mutex_exit(&ixgbe
->gen_lock
);
3775 * We need to fully re-check the link later.
3777 ixgbe
->link_check_complete
= B_FALSE
;
3778 ixgbe
->link_check_hrtime
= gethrtime() +
3779 (IXGBE_LINK_UP_TIME
* 100000000ULL);
3783 * ixgbe_overtemp_check - overtemp module processing done in taskq
3785 * This routine will only be called on adapters with temperature sensor.
3786 * The indication of over-temperature can be either SDP0 interrupt or the link
3787 * status change interrupt.
3790 ixgbe_overtemp_check(void *arg
)
3792 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg
;
3793 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3794 uint32_t eicr
= ixgbe
->eicr
;
3795 ixgbe_link_speed speed
;
3798 mutex_enter(&ixgbe
->gen_lock
);
3800 /* make sure we know current state of link */
3801 (void) ixgbe_check_link(hw
, &speed
, &link_up
, B_FALSE
);
3803 /* check over-temp condition */
3804 if (((eicr
& IXGBE_EICR_GPI_SDP0_BY_MAC(hw
)) && (!link_up
)) ||
3805 (eicr
& IXGBE_EICR_LSC
)) {
3806 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
) {
3807 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_OVERTEMP
);
3810 * Disable the adapter interrupts
3812 ixgbe_disable_adapter_interrupts(ixgbe
);
3815 * Disable Rx/Tx units
3817 (void) ixgbe_stop_adapter(hw
);
3819 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
3821 "Problem: Network adapter has been stopped "
3822 "because it has overheated");
3824 "Action: Restart the computer. "
3825 "If the problem persists, power off the system "
3826 "and replace the adapter");
3830 /* write to clear the interrupt */
3831 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
3833 mutex_exit(&ixgbe
->gen_lock
);
3837 * ixgbe_phy_check - taskq to process interrupts from an external PHY
3839 * This routine will only be called on adapters with external PHYs
3840 * (such as X550) that may be trying to raise our attention to some event.
3841 * Currently, this is limited to claiming PHY overtemperature and link status
3842 * change (LSC) events, however this may expand to include other things in
3846 ixgbe_phy_check(void *arg
)
3848 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg
;
3849 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
3852 mutex_enter(&ixgbe
->gen_lock
);
3855 * X550 baseT PHY overtemp and LSC events are handled here.
3857 * If an overtemp event occurs, it will be reflected in the
3858 * return value of phy.ops.handle_lasi() and the common code will
3859 * automatically power off the baseT PHY. This is our cue to trigger
3862 * If a link status change event occurs, phy.ops.handle_lasi() will
3863 * automatically initiate a link setup between the integrated KR PHY
3864 * and the external X557 PHY to ensure that the link speed between
3865 * them matches the link speed of the baseT link.
3867 rv
= ixgbe_handle_lasi(hw
);
3869 if (rv
== IXGBE_ERR_OVERTEMP
) {
3870 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_OVERTEMP
);
3873 * Disable the adapter interrupts
3875 ixgbe_disable_adapter_interrupts(ixgbe
);
3878 * Disable Rx/Tx units
3880 (void) ixgbe_stop_adapter(hw
);
3882 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
3884 "Problem: Network adapter has been stopped due to a "
3885 "overtemperature event being detected.");
3887 "Action: Shut down or restart the computer. If the issue "
3888 "persists, please take action in accordance with the "
3889 "recommendations from your system vendor.");
3892 mutex_exit(&ixgbe
->gen_lock
);
3896 * ixgbe_link_timer - timer for link status detection
3899 ixgbe_link_timer(void *arg
)
3901 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg
;
3903 mutex_enter(&ixgbe
->gen_lock
);
3904 ixgbe_driver_link_check(ixgbe
);
3905 mutex_exit(&ixgbe
->gen_lock
);
3909 * ixgbe_local_timer - Driver watchdog function.
3911 * This function will handle the transmit stall check and other routines.
3914 ixgbe_local_timer(void *arg
)
3916 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg
;
3918 if (ixgbe
->ixgbe_state
& IXGBE_OVERTEMP
)
3921 if (ixgbe
->ixgbe_state
& IXGBE_ERROR
) {
3922 ixgbe
->reset_count
++;
3923 if (ixgbe_reset(ixgbe
) == IXGBE_SUCCESS
)
3924 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_RESTORED
);
3928 if (ixgbe_stall_check(ixgbe
)) {
3929 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_STALL
);
3930 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_DEGRADED
);
3932 ixgbe
->reset_count
++;
3933 if (ixgbe_reset(ixgbe
) == IXGBE_SUCCESS
)
3934 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_RESTORED
);
3938 ixgbe_restart_watchdog_timer(ixgbe
);
3942 * ixgbe_stall_check - Check for transmit stall.
3944 * This function checks if the adapter is stalled (in transmit).
3946 * It is called each time the watchdog timeout is invoked.
3947 * If the transmit descriptor reclaim continuously fails,
3948 * the watchdog value will increment by 1. If the watchdog
3949 * value exceeds the threshold, the ixgbe is assumed to
3950 * have stalled and need to be reset.
3953 ixgbe_stall_check(ixgbe_t
*ixgbe
)
3955 ixgbe_tx_ring_t
*tx_ring
;
3959 if (ixgbe
->link_state
!= LINK_STATE_UP
)
3963 * If any tx ring is stalled, we'll reset the chipset
3966 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
3967 tx_ring
= &ixgbe
->tx_rings
[i
];
3968 if (tx_ring
->tbd_free
<= ixgbe
->tx_recycle_thresh
) {
3969 tx_ring
->tx_recycle(tx_ring
);
3972 if (tx_ring
->recycle_fail
> 0)
3973 tx_ring
->stall_watchdog
++;
3975 tx_ring
->stall_watchdog
= 0;
3977 if (tx_ring
->stall_watchdog
>= STALL_WATCHDOG_TIMEOUT
) {
3984 tx_ring
->stall_watchdog
= 0;
3985 tx_ring
->recycle_fail
= 0;
3993 * is_valid_mac_addr - Check if the mac address is valid.
3996 is_valid_mac_addr(uint8_t *mac_addr
)
3998 const uint8_t addr_test1
[6] = { 0, 0, 0, 0, 0, 0 };
3999 const uint8_t addr_test2
[6] =
4000 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
4002 if (!(bcmp(addr_test1
, mac_addr
, ETHERADDRL
)) ||
4003 !(bcmp(addr_test2
, mac_addr
, ETHERADDRL
)))
4010 ixgbe_find_mac_address(ixgbe_t
*ixgbe
)
4013 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
4015 struct ether_addr sysaddr
;
4018 boolean_t found
= B_FALSE
;
4021 * The "vendor's factory-set address" may already have
4022 * been extracted from the chip, but if the property
4023 * "local-mac-address" is set we use that instead.
4025 * We check whether it looks like an array of 6
4026 * bytes (which it should, if OBP set it). If we can't
4027 * make sense of it this way, we'll ignore it.
4029 err
= ddi_prop_lookup_byte_array(DDI_DEV_T_ANY
, ixgbe
->dip
,
4030 DDI_PROP_DONTPASS
, "local-mac-address", &bytes
, &nelts
);
4031 if (err
== DDI_PROP_SUCCESS
) {
4032 if (nelts
== ETHERADDRL
) {
4034 hw
->mac
.addr
[nelts
] = bytes
[nelts
];
4037 ddi_prop_free(bytes
);
4041 * Look up the OBP property "local-mac-address?". If the user has set
4042 * 'local-mac-address? = false', use "the system address" instead.
4044 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY
, ixgbe
->dip
, 0,
4045 "local-mac-address?", &bytes
, &nelts
) == DDI_PROP_SUCCESS
) {
4046 if (strncmp("false", (caddr_t
)bytes
, (size_t)nelts
) == 0) {
4047 if (localetheraddr(NULL
, &sysaddr
) != 0) {
4048 bcopy(&sysaddr
, hw
->mac
.addr
, ETHERADDRL
);
4052 ddi_prop_free(bytes
);
4056 * Finally(!), if there's a valid "mac-address" property (created
4057 * if we netbooted from this interface), we must use this instead
4058 * of any of the above to ensure that the NFS/install server doesn't
4059 * get confused by the address changing as illumos takes over!
4061 err
= ddi_prop_lookup_byte_array(DDI_DEV_T_ANY
, ixgbe
->dip
,
4062 DDI_PROP_DONTPASS
, "mac-address", &bytes
, &nelts
);
4063 if (err
== DDI_PROP_SUCCESS
) {
4064 if (nelts
== ETHERADDRL
) {
4066 hw
->mac
.addr
[nelts
] = bytes
[nelts
];
4069 ddi_prop_free(bytes
);
4073 bcopy(hw
->mac
.addr
, hw
->mac
.perm_addr
, ETHERADDRL
);
4077 _NOTE(ARGUNUSED(ixgbe
));
4083 #pragma inline(ixgbe_arm_watchdog_timer)
4085 ixgbe_arm_watchdog_timer(ixgbe_t
*ixgbe
)
4088 * Fire a watchdog timer
4090 ixgbe
->watchdog_tid
=
4091 timeout(ixgbe_local_timer
,
4092 (void *)ixgbe
, 1 * drv_usectohz(1000000));
4097 * ixgbe_enable_watchdog_timer - Enable and start the driver watchdog timer.
4100 ixgbe_enable_watchdog_timer(ixgbe_t
*ixgbe
)
4102 mutex_enter(&ixgbe
->watchdog_lock
);
4104 if (!ixgbe
->watchdog_enable
) {
4105 ixgbe
->watchdog_enable
= B_TRUE
;
4106 ixgbe
->watchdog_start
= B_TRUE
;
4107 ixgbe_arm_watchdog_timer(ixgbe
);
4110 mutex_exit(&ixgbe
->watchdog_lock
);
4114 * ixgbe_disable_watchdog_timer - Disable and stop the driver watchdog timer.
4117 ixgbe_disable_watchdog_timer(ixgbe_t
*ixgbe
)
4121 mutex_enter(&ixgbe
->watchdog_lock
);
4123 ixgbe
->watchdog_enable
= B_FALSE
;
4124 ixgbe
->watchdog_start
= B_FALSE
;
4125 tid
= ixgbe
->watchdog_tid
;
4126 ixgbe
->watchdog_tid
= 0;
4128 mutex_exit(&ixgbe
->watchdog_lock
);
4131 (void) untimeout(tid
);
4135 * ixgbe_start_watchdog_timer - Start the driver watchdog timer.
4138 ixgbe_start_watchdog_timer(ixgbe_t
*ixgbe
)
4140 mutex_enter(&ixgbe
->watchdog_lock
);
4142 if (ixgbe
->watchdog_enable
) {
4143 if (!ixgbe
->watchdog_start
) {
4144 ixgbe
->watchdog_start
= B_TRUE
;
4145 ixgbe_arm_watchdog_timer(ixgbe
);
4149 mutex_exit(&ixgbe
->watchdog_lock
);
4153 * ixgbe_restart_watchdog_timer - Restart the driver watchdog timer.
4156 ixgbe_restart_watchdog_timer(ixgbe_t
*ixgbe
)
4158 mutex_enter(&ixgbe
->watchdog_lock
);
4160 if (ixgbe
->watchdog_start
)
4161 ixgbe_arm_watchdog_timer(ixgbe
);
4163 mutex_exit(&ixgbe
->watchdog_lock
);
4167 * ixgbe_stop_watchdog_timer - Stop the driver watchdog timer.
4170 ixgbe_stop_watchdog_timer(ixgbe_t
*ixgbe
)
4174 mutex_enter(&ixgbe
->watchdog_lock
);
4176 ixgbe
->watchdog_start
= B_FALSE
;
4177 tid
= ixgbe
->watchdog_tid
;
4178 ixgbe
->watchdog_tid
= 0;
4180 mutex_exit(&ixgbe
->watchdog_lock
);
4183 (void) untimeout(tid
);
4187 * ixgbe_disable_adapter_interrupts - Disable all adapter interrupts.
4190 ixgbe_disable_adapter_interrupts(ixgbe_t
*ixgbe
)
4192 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
4195 * mask all interrupts off
4197 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, 0xffffffff);
4200 * for MSI-X, also disable autoclear
4202 if (ixgbe
->intr_type
== DDI_INTR_TYPE_MSIX
) {
4203 IXGBE_WRITE_REG(hw
, IXGBE_EIAC
, 0x0);
4206 IXGBE_WRITE_FLUSH(hw
);
4210 * ixgbe_enable_adapter_interrupts - Enable all hardware interrupts.
4213 ixgbe_enable_adapter_interrupts(ixgbe_t
*ixgbe
)
4215 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
4216 uint32_t eiac
, eiam
;
4217 uint32_t gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
4219 /* interrupt types to enable */
4220 ixgbe
->eims
= IXGBE_EIMS_ENABLE_MASK
; /* shared code default */
4221 ixgbe
->eims
&= ~IXGBE_EIMS_TCP_TIMER
; /* minus tcp timer */
4222 ixgbe
->eims
|= ixgbe
->capab
->other_intr
; /* "other" interrupt types */
4224 /* enable automask on "other" causes that this adapter can generate */
4225 eiam
= ixgbe
->capab
->other_intr
;
4230 if (ixgbe
->intr_type
== DDI_INTR_TYPE_MSIX
) {
4231 /* enable autoclear but not on bits 29:20 */
4232 eiac
= (ixgbe
->eims
& ~IXGBE_OTHER_INTR
);
4234 /* general purpose interrupt enable */
4235 gpie
|= (IXGBE_GPIE_MSIX_MODE
4236 | IXGBE_GPIE_PBA_SUPPORT
4238 | IXGBE_GPIE_EIAME
);
4244 /* disable autoclear, leave gpie at default */
4248 * General purpose interrupt enable.
4249 * For 82599, X540 and X550, extended interrupt
4250 * automask enable only in MSI or MSI-X mode
4252 if ((hw
->mac
.type
== ixgbe_mac_82598EB
) ||
4253 (ixgbe
->intr_type
== DDI_INTR_TYPE_MSI
)) {
4254 gpie
|= IXGBE_GPIE_EIAME
;
4258 /* Enable specific "other" interrupt types */
4259 switch (hw
->mac
.type
) {
4260 case ixgbe_mac_82598EB
:
4261 gpie
|= ixgbe
->capab
->other_gpie
;
4264 case ixgbe_mac_82599EB
:
4265 case ixgbe_mac_X540
:
4266 case ixgbe_mac_X550
:
4267 case ixgbe_mac_X550EM_x
:
4268 gpie
|= ixgbe
->capab
->other_gpie
;
4270 /* Enable RSC Delay 8us when LRO enabled */
4271 if (ixgbe
->lro_enable
) {
4272 gpie
|= (1 << IXGBE_GPIE_RSC_DELAY_SHIFT
);
4280 /* write to interrupt control registers */
4281 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, ixgbe
->eims
);
4282 IXGBE_WRITE_REG(hw
, IXGBE_EIAC
, eiac
);
4283 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, eiam
);
4284 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
4285 IXGBE_WRITE_FLUSH(hw
);
4289 * ixgbe_loopback_ioctl - Loopback support.
4292 ixgbe_loopback_ioctl(ixgbe_t
*ixgbe
, struct iocblk
*iocp
, mblk_t
*mp
)
4295 lb_property_t
*lbpp
;
4300 if (mp
->b_cont
== NULL
)
4303 switch (iocp
->ioc_cmd
) {
4307 case LB_GET_INFO_SIZE
:
4308 size
= sizeof (lb_info_sz_t
);
4309 if (iocp
->ioc_count
!= size
)
4312 value
= sizeof (lb_normal
);
4313 value
+= sizeof (lb_mac
);
4314 value
+= sizeof (lb_external
);
4316 lbsp
= (lb_info_sz_t
*)(uintptr_t)mp
->b_cont
->b_rptr
;
4321 value
= sizeof (lb_normal
);
4322 value
+= sizeof (lb_mac
);
4323 value
+= sizeof (lb_external
);
4326 if (iocp
->ioc_count
!= size
)
4330 lbpp
= (lb_property_t
*)(uintptr_t)mp
->b_cont
->b_rptr
;
4332 lbpp
[value
++] = lb_normal
;
4333 lbpp
[value
++] = lb_mac
;
4334 lbpp
[value
++] = lb_external
;
4338 size
= sizeof (uint32_t);
4339 if (iocp
->ioc_count
!= size
)
4342 lbmp
= (uint32_t *)(uintptr_t)mp
->b_cont
->b_rptr
;
4343 *lbmp
= ixgbe
->loopback_mode
;
4348 if (iocp
->ioc_count
!= sizeof (uint32_t))
4351 lbmp
= (uint32_t *)(uintptr_t)mp
->b_cont
->b_rptr
;
4352 if (!ixgbe_set_loopback_mode(ixgbe
, *lbmp
))
4357 iocp
->ioc_count
= size
;
4358 iocp
->ioc_error
= 0;
4360 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
4361 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_DEGRADED
);
4369 * ixgbe_set_loopback_mode - Setup loopback based on the loopback mode.
4372 ixgbe_set_loopback_mode(ixgbe_t
*ixgbe
, uint32_t mode
)
4374 if (mode
== ixgbe
->loopback_mode
)
4377 ixgbe
->loopback_mode
= mode
;
4379 if (mode
== IXGBE_LB_NONE
) {
4383 (void) ixgbe_reset(ixgbe
);
4387 mutex_enter(&ixgbe
->gen_lock
);
4391 mutex_exit(&ixgbe
->gen_lock
);
4394 case IXGBE_LB_EXTERNAL
:
4397 case IXGBE_LB_INTERNAL_MAC
:
4398 ixgbe_set_internal_mac_loopback(ixgbe
);
4402 mutex_exit(&ixgbe
->gen_lock
);
4408 * ixgbe_set_internal_mac_loopback - Set the internal MAC loopback mode.
4411 ixgbe_set_internal_mac_loopback(ixgbe_t
*ixgbe
)
4413 struct ixgbe_hw
*hw
;
4420 * Setup MAC loopback
4422 reg
= IXGBE_READ_REG(&ixgbe
->hw
, IXGBE_HLREG0
);
4423 reg
|= IXGBE_HLREG0_LPBK
;
4424 IXGBE_WRITE_REG(&ixgbe
->hw
, IXGBE_HLREG0
, reg
);
4426 reg
= IXGBE_READ_REG(&ixgbe
->hw
, IXGBE_AUTOC
);
4427 reg
&= ~IXGBE_AUTOC_LMS_MASK
;
4428 IXGBE_WRITE_REG(&ixgbe
->hw
, IXGBE_AUTOC
, reg
);
4431 * Disable Atlas Tx lanes to keep packets in loopback and not on wire
4433 switch (hw
->mac
.type
) {
4434 case ixgbe_mac_82598EB
:
4435 (void) ixgbe_read_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_LPBK
,
4437 atlas
|= IXGBE_ATLAS_PDN_TX_REG_EN
;
4438 (void) ixgbe_write_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_LPBK
,
4441 (void) ixgbe_read_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_10G
,
4443 atlas
|= IXGBE_ATLAS_PDN_TX_10G_QL_ALL
;
4444 (void) ixgbe_write_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_10G
,
4447 (void) ixgbe_read_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_1G
,
4449 atlas
|= IXGBE_ATLAS_PDN_TX_1G_QL_ALL
;
4450 (void) ixgbe_write_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_1G
,
4453 (void) ixgbe_read_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_AN
,
4455 atlas
|= IXGBE_ATLAS_PDN_TX_AN_QL_ALL
;
4456 (void) ixgbe_write_analog_reg8(&ixgbe
->hw
, IXGBE_ATLAS_PDN_AN
,
4460 case ixgbe_mac_82599EB
:
4461 case ixgbe_mac_X540
:
4462 case ixgbe_mac_X550
:
4463 case ixgbe_mac_X550EM_x
:
4464 reg
= IXGBE_READ_REG(&ixgbe
->hw
, IXGBE_AUTOC
);
4465 reg
|= (IXGBE_AUTOC_FLU
|
4466 IXGBE_AUTOC_10G_KX4
);
4467 IXGBE_WRITE_REG(&ixgbe
->hw
, IXGBE_AUTOC
, reg
);
4469 (void) ixgbe_setup_link(&ixgbe
->hw
, IXGBE_LINK_SPEED_10GB_FULL
,
4478 #pragma inline(ixgbe_intr_rx_work)
4480 * ixgbe_intr_rx_work - RX processing of ISR.
4483 ixgbe_intr_rx_work(ixgbe_rx_ring_t
*rx_ring
)
4487 mutex_enter(&rx_ring
->rx_lock
);
4489 mp
= ixgbe_ring_rx(rx_ring
, IXGBE_POLL_NULL
);
4490 mutex_exit(&rx_ring
->rx_lock
);
4493 mac_rx_ring(rx_ring
->ixgbe
->mac_hdl
, rx_ring
->ring_handle
, mp
,
4494 rx_ring
->ring_gen_num
);
4497 #pragma inline(ixgbe_intr_tx_work)
4499 * ixgbe_intr_tx_work - TX processing of ISR.
4502 ixgbe_intr_tx_work(ixgbe_tx_ring_t
*tx_ring
)
4504 ixgbe_t
*ixgbe
= tx_ring
->ixgbe
;
4507 * Recycle the tx descriptors
4509 tx_ring
->tx_recycle(tx_ring
);
4512 * Schedule the re-transmit
4514 if (tx_ring
->reschedule
&&
4515 (tx_ring
->tbd_free
>= ixgbe
->tx_resched_thresh
)) {
4516 tx_ring
->reschedule
= B_FALSE
;
4517 mac_tx_ring_update(tx_ring
->ixgbe
->mac_hdl
,
4518 tx_ring
->ring_handle
);
4519 tx_ring
->stat_reschedule
++;
4523 #pragma inline(ixgbe_intr_other_work)
4525 * ixgbe_intr_other_work - Process interrupt types other than tx/rx
4528 ixgbe_intr_other_work(ixgbe_t
*ixgbe
, uint32_t eicr
)
4530 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
4532 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
4535 * handle link status change
4537 if (eicr
& IXGBE_EICR_LSC
) {
4538 ixgbe_driver_link_check(ixgbe
);
4539 ixgbe_get_hw_state(ixgbe
);
4543 * check for fan failure on adapters with fans
4545 if ((ixgbe
->capab
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
4546 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
4547 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_OVERTEMP
);
4550 * Disable the adapter interrupts
4552 ixgbe_disable_adapter_interrupts(ixgbe
);
4555 * Disable Rx/Tx units
4557 (void) ixgbe_stop_adapter(&ixgbe
->hw
);
4559 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_LOST
);
4561 "Problem: Network adapter has been stopped "
4562 "because the fan has stopped.\n");
4564 "Action: Replace the adapter.\n");
4566 /* re-enable the interrupt, which was automasked */
4567 ixgbe
->eims
|= IXGBE_EICR_GPI_SDP1
;
4571 * Do SFP check for adapters with hot-plug capability
4573 if ((ixgbe
->capab
->flags
& IXGBE_FLAG_SFP_PLUG_CAPABLE
) &&
4574 ((eicr
& IXGBE_EICR_GPI_SDP1_BY_MAC(hw
)) ||
4575 (eicr
& IXGBE_EICR_GPI_SDP2_BY_MAC(hw
)))) {
4577 if ((ddi_taskq_dispatch(ixgbe
->sfp_taskq
,
4578 ixgbe_sfp_check
, (void *)ixgbe
,
4579 DDI_NOSLEEP
)) != DDI_SUCCESS
) {
4580 ixgbe_log(ixgbe
, "No memory available to dispatch "
4581 "taskq for SFP check");
4586 * Do over-temperature check for adapters with temp sensor
4588 if ((ixgbe
->capab
->flags
& IXGBE_FLAG_TEMP_SENSOR_CAPABLE
) &&
4589 ((eicr
& IXGBE_EICR_GPI_SDP0_BY_MAC(hw
)) ||
4590 (eicr
& IXGBE_EICR_LSC
))) {
4592 if ((ddi_taskq_dispatch(ixgbe
->overtemp_taskq
,
4593 ixgbe_overtemp_check
, (void *)ixgbe
,
4594 DDI_NOSLEEP
)) != DDI_SUCCESS
) {
4595 ixgbe_log(ixgbe
, "No memory available to dispatch "
4596 "taskq for overtemp check");
4601 * Process an external PHY interrupt
4603 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_X_10G_T
&&
4604 (eicr
& IXGBE_EICR_GPI_SDP0_X540
)) {
4606 if ((ddi_taskq_dispatch(ixgbe
->phy_taskq
,
4607 ixgbe_phy_check
, (void *)ixgbe
,
4608 DDI_NOSLEEP
)) != DDI_SUCCESS
) {
4609 ixgbe_log(ixgbe
, "No memory available to dispatch "
4610 "taskq for PHY check");
4616 * ixgbe_intr_legacy - Interrupt handler for legacy interrupts.
4619 ixgbe_intr_legacy(void *arg1
, void *arg2
)
4621 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg1
;
4622 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
4623 ixgbe_tx_ring_t
*tx_ring
;
4624 ixgbe_rx_ring_t
*rx_ring
;
4627 boolean_t tx_reschedule
;
4630 _NOTE(ARGUNUSED(arg2
));
4632 mutex_enter(&ixgbe
->gen_lock
);
4633 if (ixgbe
->ixgbe_state
& IXGBE_SUSPENDED
) {
4634 mutex_exit(&ixgbe
->gen_lock
);
4635 return (DDI_INTR_UNCLAIMED
);
4639 tx_reschedule
= B_FALSE
;
4642 * Any bit set in eicr: claim this interrupt
4644 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
4646 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
4647 mutex_exit(&ixgbe
->gen_lock
);
4648 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_DEGRADED
);
4649 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_ERROR
);
4650 return (DDI_INTR_CLAIMED
);
4655 * For legacy interrupt, we have only one interrupt,
4656 * so we have only one rx ring and one tx ring enabled.
4658 ASSERT(ixgbe
->num_rx_rings
== 1);
4659 ASSERT(ixgbe
->num_tx_rings
== 1);
4662 * For legacy interrupt, rx rings[0] will use RTxQ[0].
4665 ixgbe
->eimc
|= IXGBE_EICR_RTX_QUEUE
;
4666 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, ixgbe
->eimc
);
4667 ixgbe
->eims
|= IXGBE_EICR_RTX_QUEUE
;
4669 * Clean the rx descriptors
4671 rx_ring
= &ixgbe
->rx_rings
[0];
4672 mp
= ixgbe_ring_rx(rx_ring
, IXGBE_POLL_NULL
);
4676 * For legacy interrupt, tx rings[0] will use RTxQ[1].
4680 * Recycle the tx descriptors
4682 tx_ring
= &ixgbe
->tx_rings
[0];
4683 tx_ring
->tx_recycle(tx_ring
);
4686 * Schedule the re-transmit
4688 tx_reschedule
= (tx_ring
->reschedule
&&
4689 (tx_ring
->tbd_free
>= ixgbe
->tx_resched_thresh
));
4692 /* any interrupt type other than tx/rx */
4693 if (eicr
& ixgbe
->capab
->other_intr
) {
4694 switch (hw
->mac
.type
) {
4695 case ixgbe_mac_82598EB
:
4696 ixgbe
->eims
&= ~(eicr
& IXGBE_OTHER_INTR
);
4699 case ixgbe_mac_82599EB
:
4700 case ixgbe_mac_X540
:
4701 case ixgbe_mac_X550
:
4702 case ixgbe_mac_X550EM_x
:
4703 ixgbe
->eimc
= IXGBE_82599_OTHER_INTR
;
4704 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, ixgbe
->eimc
);
4710 ixgbe_intr_other_work(ixgbe
, eicr
);
4711 ixgbe
->eims
&= ~(eicr
& IXGBE_OTHER_INTR
);
4714 mutex_exit(&ixgbe
->gen_lock
);
4716 result
= DDI_INTR_CLAIMED
;
4718 mutex_exit(&ixgbe
->gen_lock
);
4721 * No interrupt cause bits set: don't claim this interrupt.
4723 result
= DDI_INTR_UNCLAIMED
;
4726 /* re-enable the interrupts which were automasked */
4727 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, ixgbe
->eims
);
4730 * Do the following work outside of the gen_lock
4733 mac_rx_ring(rx_ring
->ixgbe
->mac_hdl
, rx_ring
->ring_handle
, mp
,
4734 rx_ring
->ring_gen_num
);
4737 if (tx_reschedule
) {
4738 tx_ring
->reschedule
= B_FALSE
;
4739 mac_tx_ring_update(ixgbe
->mac_hdl
, tx_ring
->ring_handle
);
4740 tx_ring
->stat_reschedule
++;
4747 * ixgbe_intr_msi - Interrupt handler for MSI.
4750 ixgbe_intr_msi(void *arg1
, void *arg2
)
4752 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg1
;
4753 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
4756 _NOTE(ARGUNUSED(arg2
));
4758 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
4760 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) != DDI_FM_OK
) {
4761 ddi_fm_service_impact(ixgbe
->dip
, DDI_SERVICE_DEGRADED
);
4762 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_ERROR
);
4763 return (DDI_INTR_CLAIMED
);
4767 * For MSI interrupt, we have only one vector,
4768 * so we have only one rx ring and one tx ring enabled.
4770 ASSERT(ixgbe
->num_rx_rings
== 1);
4771 ASSERT(ixgbe
->num_tx_rings
== 1);
4774 * For MSI interrupt, rx rings[0] will use RTxQ[0].
4777 ixgbe_intr_rx_work(&ixgbe
->rx_rings
[0]);
4781 * For MSI interrupt, tx rings[0] will use RTxQ[1].
4784 ixgbe_intr_tx_work(&ixgbe
->tx_rings
[0]);
4787 /* any interrupt type other than tx/rx */
4788 if (eicr
& ixgbe
->capab
->other_intr
) {
4789 mutex_enter(&ixgbe
->gen_lock
);
4790 switch (hw
->mac
.type
) {
4791 case ixgbe_mac_82598EB
:
4792 ixgbe
->eims
&= ~(eicr
& IXGBE_OTHER_INTR
);
4795 case ixgbe_mac_82599EB
:
4796 case ixgbe_mac_X540
:
4797 case ixgbe_mac_X550
:
4798 case ixgbe_mac_X550EM_x
:
4799 ixgbe
->eimc
= IXGBE_82599_OTHER_INTR
;
4800 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, ixgbe
->eimc
);
4806 ixgbe_intr_other_work(ixgbe
, eicr
);
4807 ixgbe
->eims
&= ~(eicr
& IXGBE_OTHER_INTR
);
4808 mutex_exit(&ixgbe
->gen_lock
);
4811 /* re-enable the interrupts which were automasked */
4812 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, ixgbe
->eims
);
4814 return (DDI_INTR_CLAIMED
);
4818 * ixgbe_intr_msix - Interrupt handler for MSI-X.
4821 ixgbe_intr_msix(void *arg1
, void *arg2
)
4823 ixgbe_intr_vector_t
*vect
= (ixgbe_intr_vector_t
*)arg1
;
4824 ixgbe_t
*ixgbe
= vect
->ixgbe
;
4825 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
4829 _NOTE(ARGUNUSED(arg2
));
4832 * Clean each rx ring that has its bit set in the map
4834 r_idx
= bt_getlowbit(vect
->rx_map
, 0, (ixgbe
->num_rx_rings
- 1));
4835 while (r_idx
>= 0) {
4836 ixgbe_intr_rx_work(&ixgbe
->rx_rings
[r_idx
]);
4837 r_idx
= bt_getlowbit(vect
->rx_map
, (r_idx
+ 1),
4838 (ixgbe
->num_rx_rings
- 1));
4842 * Clean each tx ring that has its bit set in the map
4844 r_idx
= bt_getlowbit(vect
->tx_map
, 0, (ixgbe
->num_tx_rings
- 1));
4845 while (r_idx
>= 0) {
4846 ixgbe_intr_tx_work(&ixgbe
->tx_rings
[r_idx
]);
4847 r_idx
= bt_getlowbit(vect
->tx_map
, (r_idx
+ 1),
4848 (ixgbe
->num_tx_rings
- 1));
4853 * Clean other interrupt (link change) that has its bit set in the map
4855 if (BT_TEST(vect
->other_map
, 0) == 1) {
4856 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
4858 if (ixgbe_check_acc_handle(ixgbe
->osdep
.reg_handle
) !=
4860 ddi_fm_service_impact(ixgbe
->dip
,
4861 DDI_SERVICE_DEGRADED
);
4862 atomic_or_32(&ixgbe
->ixgbe_state
, IXGBE_ERROR
);
4863 return (DDI_INTR_CLAIMED
);
4867 * Check "other" cause bits: any interrupt type other than tx/rx
4869 if (eicr
& ixgbe
->capab
->other_intr
) {
4870 mutex_enter(&ixgbe
->gen_lock
);
4871 switch (hw
->mac
.type
) {
4872 case ixgbe_mac_82598EB
:
4873 ixgbe
->eims
&= ~(eicr
& IXGBE_OTHER_INTR
);
4874 ixgbe_intr_other_work(ixgbe
, eicr
);
4877 case ixgbe_mac_82599EB
:
4878 case ixgbe_mac_X540
:
4879 case ixgbe_mac_X550
:
4880 case ixgbe_mac_X550EM_x
:
4881 ixgbe
->eims
|= IXGBE_EICR_RTX_QUEUE
;
4882 ixgbe_intr_other_work(ixgbe
, eicr
);
4888 mutex_exit(&ixgbe
->gen_lock
);
4891 /* re-enable the interrupts which were automasked */
4892 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, ixgbe
->eims
);
4895 return (DDI_INTR_CLAIMED
);
4899 * ixgbe_alloc_intrs - Allocate interrupts for the driver.
4901 * Normal sequence is to try MSI-X; if not sucessful, try MSI;
4902 * if not successful, try Legacy.
4903 * ixgbe->intr_force can be used to force sequence to start with
4904 * any of the 3 types.
4905 * If MSI-X is not used, number of tx/rx rings is forced to 1.
4908 ixgbe_alloc_intrs(ixgbe_t
*ixgbe
)
4910 dev_info_t
*devinfo
;
4914 devinfo
= ixgbe
->dip
;
4917 * Get supported interrupt types
4919 rc
= ddi_intr_get_supported_types(devinfo
, &intr_types
);
4921 if (rc
!= DDI_SUCCESS
) {
4923 "Get supported interrupt types failed: %d", rc
);
4924 return (IXGBE_FAILURE
);
4926 IXGBE_DEBUGLOG_1(ixgbe
, "Supported interrupt types: %x", intr_types
);
4928 ixgbe
->intr_type
= 0;
4931 * Install MSI-X interrupts
4933 if ((intr_types
& DDI_INTR_TYPE_MSIX
) &&
4934 (ixgbe
->intr_force
<= IXGBE_INTR_MSIX
)) {
4935 rc
= ixgbe_alloc_intr_handles(ixgbe
, DDI_INTR_TYPE_MSIX
);
4936 if (rc
== IXGBE_SUCCESS
)
4937 return (IXGBE_SUCCESS
);
4940 "Allocate MSI-X failed, trying MSI interrupts...");
4944 * MSI-X not used, force rings and groups to 1
4946 ixgbe
->num_rx_rings
= 1;
4947 ixgbe
->num_rx_groups
= 1;
4948 ixgbe
->num_tx_rings
= 1;
4949 ixgbe
->classify_mode
= IXGBE_CLASSIFY_NONE
;
4951 "MSI-X not used, force rings and groups number to 1");
4954 * Install MSI interrupts
4956 if ((intr_types
& DDI_INTR_TYPE_MSI
) &&
4957 (ixgbe
->intr_force
<= IXGBE_INTR_MSI
)) {
4958 rc
= ixgbe_alloc_intr_handles(ixgbe
, DDI_INTR_TYPE_MSI
);
4959 if (rc
== IXGBE_SUCCESS
)
4960 return (IXGBE_SUCCESS
);
4963 "Allocate MSI failed, trying Legacy interrupts...");
4967 * Install legacy interrupts
4969 if (intr_types
& DDI_INTR_TYPE_FIXED
) {
4971 * Disallow legacy interrupts for X550. X550 has a silicon
4972 * bug which prevents Shared Legacy interrupts from working.
4973 * For details, please reference:
4975 * Intel Ethernet Controller X550 Specification Update rev. 2.1
4976 * May 2016, erratum 22: PCIe Interrupt Status Bit
4978 if (ixgbe
->hw
.mac
.type
== ixgbe_mac_X550
||
4979 ixgbe
->hw
.mac
.type
== ixgbe_mac_X550EM_x
||
4980 ixgbe
->hw
.mac
.type
== ixgbe_mac_X550_vf
||
4981 ixgbe
->hw
.mac
.type
== ixgbe_mac_X550EM_x_vf
) {
4983 "Legacy interrupts are not supported on this "
4984 "adapter. Please use MSI or MSI-X instead.");
4985 return (IXGBE_FAILURE
);
4987 rc
= ixgbe_alloc_intr_handles(ixgbe
, DDI_INTR_TYPE_FIXED
);
4988 if (rc
== IXGBE_SUCCESS
)
4989 return (IXGBE_SUCCESS
);
4992 "Allocate Legacy interrupts failed");
4996 * If none of the 3 types succeeded, return failure
4998 return (IXGBE_FAILURE
);
5002 * ixgbe_alloc_intr_handles - Allocate interrupt handles.
5004 * For legacy and MSI, only 1 handle is needed. For MSI-X,
5005 * if fewer than 2 handles are available, return failure.
5006 * Upon success, this maps the vectors to rx and tx rings for
5010 ixgbe_alloc_intr_handles(ixgbe_t
*ixgbe
, int intr_type
)
5012 dev_info_t
*devinfo
;
5013 int request
, count
, actual
;
5016 uint32_t ring_per_group
;
5018 devinfo
= ixgbe
->dip
;
5020 switch (intr_type
) {
5021 case DDI_INTR_TYPE_FIXED
:
5022 request
= 1; /* Request 1 legacy interrupt handle */
5024 IXGBE_DEBUGLOG_0(ixgbe
, "interrupt type: legacy");
5027 case DDI_INTR_TYPE_MSI
:
5028 request
= 1; /* Request 1 MSI interrupt handle */
5030 IXGBE_DEBUGLOG_0(ixgbe
, "interrupt type: MSI");
5033 case DDI_INTR_TYPE_MSIX
:
5035 * Best number of vectors for the adapter is
5036 * (# rx rings + # tx rings), however we will
5037 * limit the request number.
5039 request
= min(16, ixgbe
->num_rx_rings
+ ixgbe
->num_tx_rings
);
5040 if (request
> ixgbe
->capab
->max_ring_vect
)
5041 request
= ixgbe
->capab
->max_ring_vect
;
5043 IXGBE_DEBUGLOG_0(ixgbe
, "interrupt type: MSI-X");
5048 "invalid call to ixgbe_alloc_intr_handles(): %d\n",
5050 return (IXGBE_FAILURE
);
5052 IXGBE_DEBUGLOG_2(ixgbe
, "interrupt handles requested: %d minimum: %d",
5056 * Get number of supported interrupts
5058 rc
= ddi_intr_get_nintrs(devinfo
, intr_type
, &count
);
5059 if ((rc
!= DDI_SUCCESS
) || (count
< minimum
)) {
5061 "Get interrupt number failed. Return: %d, count: %d",
5063 return (IXGBE_FAILURE
);
5065 IXGBE_DEBUGLOG_1(ixgbe
, "interrupts supported: %d", count
);
5068 ixgbe
->intr_cnt
= 0;
5069 ixgbe
->intr_cnt_max
= 0;
5070 ixgbe
->intr_cnt_min
= 0;
5073 * Allocate an array of interrupt handles
5075 ixgbe
->intr_size
= request
* sizeof (ddi_intr_handle_t
);
5076 ixgbe
->htable
= kmem_alloc(ixgbe
->intr_size
, KM_SLEEP
);
5078 rc
= ddi_intr_alloc(devinfo
, ixgbe
->htable
, intr_type
, 0,
5079 request
, &actual
, DDI_INTR_ALLOC_NORMAL
);
5080 if (rc
!= DDI_SUCCESS
) {
5081 ixgbe_log(ixgbe
, "Allocate interrupts failed. "
5082 "return: %d, request: %d, actual: %d",
5083 rc
, request
, actual
);
5084 goto alloc_handle_fail
;
5086 IXGBE_DEBUGLOG_1(ixgbe
, "interrupts actually allocated: %d", actual
);
5089 * upper/lower limit of interrupts
5091 ixgbe
->intr_cnt
= actual
;
5092 ixgbe
->intr_cnt_max
= request
;
5093 ixgbe
->intr_cnt_min
= minimum
;
5096 * rss number per group should not exceed the rx interrupt number,
5097 * else need to adjust rx ring number.
5099 ring_per_group
= ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
;
5100 ASSERT((ixgbe
->num_rx_rings
% ixgbe
->num_rx_groups
) == 0);
5101 if (actual
< ring_per_group
) {
5102 ixgbe
->num_rx_rings
= ixgbe
->num_rx_groups
* actual
;
5103 ixgbe_setup_vmdq_rss_conf(ixgbe
);
5107 * Now we know the actual number of vectors. Here we map the vector
5108 * to other, rx rings and tx ring.
5110 if (actual
< minimum
) {
5111 ixgbe_log(ixgbe
, "Insufficient interrupt handles available: %d",
5113 goto alloc_handle_fail
;
5117 * Get priority for first vector, assume remaining are all the same
5119 rc
= ddi_intr_get_pri(ixgbe
->htable
[0], &ixgbe
->intr_pri
);
5120 if (rc
!= DDI_SUCCESS
) {
5122 "Get interrupt priority failed: %d", rc
);
5123 goto alloc_handle_fail
;
5126 rc
= ddi_intr_get_cap(ixgbe
->htable
[0], &ixgbe
->intr_cap
);
5127 if (rc
!= DDI_SUCCESS
) {
5129 "Get interrupt cap failed: %d", rc
);
5130 goto alloc_handle_fail
;
5133 ixgbe
->intr_type
= intr_type
;
5135 return (IXGBE_SUCCESS
);
5138 ixgbe_rem_intrs(ixgbe
);
5140 return (IXGBE_FAILURE
);
5144 * ixgbe_add_intr_handlers - Add interrupt handlers based on the interrupt type.
5146 * Before adding the interrupt handlers, the interrupt vectors have
5147 * been allocated, and the rx/tx rings have also been allocated.
5150 ixgbe_add_intr_handlers(ixgbe_t
*ixgbe
)
5155 switch (ixgbe
->intr_type
) {
5156 case DDI_INTR_TYPE_MSIX
:
5158 * Add interrupt handler for all vectors
5160 for (vector
= 0; vector
< ixgbe
->intr_cnt
; vector
++) {
5162 * install pointer to vect_map[vector]
5164 rc
= ddi_intr_add_handler(ixgbe
->htable
[vector
],
5165 (ddi_intr_handler_t
*)ixgbe_intr_msix
,
5166 (void *)&ixgbe
->vect_map
[vector
], NULL
);
5168 if (rc
!= DDI_SUCCESS
) {
5170 "Add interrupt handler failed. "
5171 "return: %d, vector: %d", rc
, vector
);
5172 for (vector
--; vector
>= 0; vector
--) {
5173 (void) ddi_intr_remove_handler(
5174 ixgbe
->htable
[vector
]);
5176 return (IXGBE_FAILURE
);
5182 case DDI_INTR_TYPE_MSI
:
5184 * Add interrupt handlers for the only vector
5186 rc
= ddi_intr_add_handler(ixgbe
->htable
[vector
],
5187 (ddi_intr_handler_t
*)ixgbe_intr_msi
,
5188 (void *)ixgbe
, NULL
);
5190 if (rc
!= DDI_SUCCESS
) {
5192 "Add MSI interrupt handler failed: %d", rc
);
5193 return (IXGBE_FAILURE
);
5198 case DDI_INTR_TYPE_FIXED
:
5200 * Add interrupt handlers for the only vector
5202 rc
= ddi_intr_add_handler(ixgbe
->htable
[vector
],
5203 (ddi_intr_handler_t
*)ixgbe_intr_legacy
,
5204 (void *)ixgbe
, NULL
);
5206 if (rc
!= DDI_SUCCESS
) {
5208 "Add legacy interrupt handler failed: %d", rc
);
5209 return (IXGBE_FAILURE
);
5215 return (IXGBE_FAILURE
);
5218 return (IXGBE_SUCCESS
);
5221 #pragma inline(ixgbe_map_rxring_to_vector)
5223 * ixgbe_map_rxring_to_vector - Map given rx ring to given interrupt vector.
5226 ixgbe_map_rxring_to_vector(ixgbe_t
*ixgbe
, int r_idx
, int v_idx
)
5231 BT_SET(ixgbe
->vect_map
[v_idx
].rx_map
, r_idx
);
5236 ixgbe
->vect_map
[v_idx
].rxr_cnt
++;
5239 * Remember bit position
5241 ixgbe
->rx_rings
[r_idx
].intr_vector
= v_idx
;
5242 ixgbe
->rx_rings
[r_idx
].vect_bit
= 1 << v_idx
;
5245 #pragma inline(ixgbe_map_txring_to_vector)
5247 * ixgbe_map_txring_to_vector - Map given tx ring to given interrupt vector.
5250 ixgbe_map_txring_to_vector(ixgbe_t
*ixgbe
, int t_idx
, int v_idx
)
5255 BT_SET(ixgbe
->vect_map
[v_idx
].tx_map
, t_idx
);
5260 ixgbe
->vect_map
[v_idx
].txr_cnt
++;
5263 * Remember bit position
5265 ixgbe
->tx_rings
[t_idx
].intr_vector
= v_idx
;
5266 ixgbe
->tx_rings
[t_idx
].vect_bit
= 1 << v_idx
;
5270 * ixgbe_setup_ivar - Set the given entry in the given interrupt vector
5271 * allocation register (IVAR).
5278 ixgbe_setup_ivar(ixgbe_t
*ixgbe
, uint16_t intr_alloc_entry
, uint8_t msix_vector
,
5281 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
5284 switch (hw
->mac
.type
) {
5285 case ixgbe_mac_82598EB
:
5286 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
5290 index
= (((cause
* 64) + intr_alloc_entry
) >> 2) & 0x1F;
5291 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
5292 ivar
&= ~(0xFF << (8 * (intr_alloc_entry
& 0x3)));
5293 ivar
|= (msix_vector
<< (8 * (intr_alloc_entry
& 0x3)));
5294 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
5297 case ixgbe_mac_82599EB
:
5298 case ixgbe_mac_X540
:
5299 case ixgbe_mac_X550
:
5300 case ixgbe_mac_X550EM_x
:
5303 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
5304 index
= (intr_alloc_entry
& 1) * 8;
5305 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR_MISC
);
5306 ivar
&= ~(0xFF << index
);
5307 ivar
|= (msix_vector
<< index
);
5308 IXGBE_WRITE_REG(hw
, IXGBE_IVAR_MISC
, ivar
);
5310 /* tx or rx causes */
5311 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
5312 index
= ((16 * (intr_alloc_entry
& 1)) + (8 * cause
));
5313 ivar
= IXGBE_READ_REG(hw
,
5314 IXGBE_IVAR(intr_alloc_entry
>> 1));
5315 ivar
&= ~(0xFF << index
);
5316 ivar
|= (msix_vector
<< index
);
5317 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(intr_alloc_entry
>> 1),
5328 * ixgbe_enable_ivar - Enable the given entry by setting the VAL bit of
5329 * given interrupt vector allocation register (IVAR).
5336 ixgbe_enable_ivar(ixgbe_t
*ixgbe
, uint16_t intr_alloc_entry
, int8_t cause
)
5338 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
5341 switch (hw
->mac
.type
) {
5342 case ixgbe_mac_82598EB
:
5346 index
= (((cause
* 64) + intr_alloc_entry
) >> 2) & 0x1F;
5347 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
5348 ivar
|= (IXGBE_IVAR_ALLOC_VAL
<< (8 *
5349 (intr_alloc_entry
& 0x3)));
5350 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
5353 case ixgbe_mac_82599EB
:
5354 case ixgbe_mac_X540
:
5355 case ixgbe_mac_X550
:
5356 case ixgbe_mac_X550EM_x
:
5359 index
= (intr_alloc_entry
& 1) * 8;
5360 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR_MISC
);
5361 ivar
|= (IXGBE_IVAR_ALLOC_VAL
<< index
);
5362 IXGBE_WRITE_REG(hw
, IXGBE_IVAR_MISC
, ivar
);
5364 /* tx or rx causes */
5365 index
= ((16 * (intr_alloc_entry
& 1)) + (8 * cause
));
5366 ivar
= IXGBE_READ_REG(hw
,
5367 IXGBE_IVAR(intr_alloc_entry
>> 1));
5368 ivar
|= (IXGBE_IVAR_ALLOC_VAL
<< index
);
5369 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(intr_alloc_entry
>> 1),
5380 * ixgbe_disable_ivar - Disble the given entry by clearing the VAL bit of
5381 * given interrupt vector allocation register (IVAR).
5388 ixgbe_disable_ivar(ixgbe_t
*ixgbe
, uint16_t intr_alloc_entry
, int8_t cause
)
5390 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
5393 switch (hw
->mac
.type
) {
5394 case ixgbe_mac_82598EB
:
5398 index
= (((cause
* 64) + intr_alloc_entry
) >> 2) & 0x1F;
5399 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
5400 ivar
&= ~(IXGBE_IVAR_ALLOC_VAL
<< (8 *
5401 (intr_alloc_entry
& 0x3)));
5402 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
5405 case ixgbe_mac_82599EB
:
5406 case ixgbe_mac_X540
:
5407 case ixgbe_mac_X550
:
5408 case ixgbe_mac_X550EM_x
:
5411 index
= (intr_alloc_entry
& 1) * 8;
5412 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR_MISC
);
5413 ivar
&= ~(IXGBE_IVAR_ALLOC_VAL
<< index
);
5414 IXGBE_WRITE_REG(hw
, IXGBE_IVAR_MISC
, ivar
);
5416 /* tx or rx causes */
5417 index
= ((16 * (intr_alloc_entry
& 1)) + (8 * cause
));
5418 ivar
= IXGBE_READ_REG(hw
,
5419 IXGBE_IVAR(intr_alloc_entry
>> 1));
5420 ivar
&= ~(IXGBE_IVAR_ALLOC_VAL
<< index
);
5421 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(intr_alloc_entry
>> 1),
5432 * Convert the rx ring index driver maintained to the rx ring index
5436 ixgbe_get_hw_rx_index(ixgbe_t
*ixgbe
, uint32_t sw_rx_index
)
5439 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
5440 uint32_t rx_ring_per_group
, hw_rx_index
;
5442 if (ixgbe
->classify_mode
== IXGBE_CLASSIFY_RSS
||
5443 ixgbe
->classify_mode
== IXGBE_CLASSIFY_NONE
) {
5444 return (sw_rx_index
);
5445 } else if (ixgbe
->classify_mode
== IXGBE_CLASSIFY_VMDQ
) {
5446 switch (hw
->mac
.type
) {
5447 case ixgbe_mac_82598EB
:
5448 return (sw_rx_index
);
5450 case ixgbe_mac_82599EB
:
5451 case ixgbe_mac_X540
:
5452 case ixgbe_mac_X550
:
5453 case ixgbe_mac_X550EM_x
:
5454 return (sw_rx_index
* 2);
5459 } else if (ixgbe
->classify_mode
== IXGBE_CLASSIFY_VMDQ_RSS
) {
5460 rx_ring_per_group
= ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
;
5462 switch (hw
->mac
.type
) {
5463 case ixgbe_mac_82598EB
:
5464 hw_rx_index
= (sw_rx_index
/ rx_ring_per_group
) *
5465 16 + (sw_rx_index
% rx_ring_per_group
);
5466 return (hw_rx_index
);
5468 case ixgbe_mac_82599EB
:
5469 case ixgbe_mac_X540
:
5470 case ixgbe_mac_X550
:
5471 case ixgbe_mac_X550EM_x
:
5472 if (ixgbe
->num_rx_groups
> 32) {
5473 hw_rx_index
= (sw_rx_index
/
5474 rx_ring_per_group
) * 2 +
5475 (sw_rx_index
% rx_ring_per_group
);
5477 hw_rx_index
= (sw_rx_index
/
5478 rx_ring_per_group
) * 4 +
5479 (sw_rx_index
% rx_ring_per_group
);
5481 return (hw_rx_index
);
5489 * Should never reach. Just to make compiler happy.
5491 return (sw_rx_index
);
5495 * ixgbe_map_intrs_to_vectors - Map different interrupts to MSI-X vectors.
5497 * For MSI-X, here will map rx interrupt, tx interrupt and other interrupt
5498 * to vector[0 - (intr_cnt -1)].
5501 ixgbe_map_intrs_to_vectors(ixgbe_t
*ixgbe
)
5505 /* initialize vector map */
5506 bzero(&ixgbe
->vect_map
, sizeof (ixgbe
->vect_map
));
5507 for (i
= 0; i
< ixgbe
->intr_cnt
; i
++) {
5508 ixgbe
->vect_map
[i
].ixgbe
= ixgbe
;
5512 * non-MSI-X case is very simple: rx rings[0] on RTxQ[0],
5513 * tx rings[0] on RTxQ[1].
5515 if (ixgbe
->intr_type
!= DDI_INTR_TYPE_MSIX
) {
5516 ixgbe_map_rxring_to_vector(ixgbe
, 0, 0);
5517 ixgbe_map_txring_to_vector(ixgbe
, 0, 1);
5518 return (IXGBE_SUCCESS
);
5522 * Interrupts/vectors mapping for MSI-X
5526 * Map other interrupt to vector 0,
5527 * Set bit in map and count the bits set.
5529 BT_SET(ixgbe
->vect_map
[vector
].other_map
, 0);
5530 ixgbe
->vect_map
[vector
].other_cnt
++;
5533 * Map rx ring interrupts to vectors
5535 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
5536 ixgbe_map_rxring_to_vector(ixgbe
, i
, vector
);
5537 vector
= (vector
+1) % ixgbe
->intr_cnt
;
5541 * Map tx ring interrupts to vectors
5543 for (i
= 0; i
< ixgbe
->num_tx_rings
; i
++) {
5544 ixgbe_map_txring_to_vector(ixgbe
, i
, vector
);
5545 vector
= (vector
+1) % ixgbe
->intr_cnt
;
5548 return (IXGBE_SUCCESS
);
5552 * ixgbe_setup_adapter_vector - Setup the adapter interrupt vector(s).
5554 * This relies on ring/vector mapping already set up in the
5555 * vect_map[] structures
5558 ixgbe_setup_adapter_vector(ixgbe_t
*ixgbe
)
5560 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
5561 ixgbe_intr_vector_t
*vect
; /* vector bitmap */
5562 int r_idx
; /* ring index */
5563 int v_idx
; /* vector index */
5567 * Clear any previous entries
5569 switch (hw
->mac
.type
) {
5570 case ixgbe_mac_82598EB
:
5571 for (v_idx
= 0; v_idx
< 25; v_idx
++)
5572 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(v_idx
), 0);
5575 case ixgbe_mac_82599EB
:
5576 case ixgbe_mac_X540
:
5577 case ixgbe_mac_X550
:
5578 case ixgbe_mac_X550EM_x
:
5579 for (v_idx
= 0; v_idx
< 64; v_idx
++)
5580 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(v_idx
), 0);
5581 IXGBE_WRITE_REG(hw
, IXGBE_IVAR_MISC
, 0);
5589 * For non MSI-X interrupt, rx rings[0] will use RTxQ[0], and
5590 * tx rings[0] will use RTxQ[1].
5592 if (ixgbe
->intr_type
!= DDI_INTR_TYPE_MSIX
) {
5593 ixgbe_setup_ivar(ixgbe
, 0, 0, 0);
5594 ixgbe_setup_ivar(ixgbe
, 0, 1, 1);
5599 * For MSI-X interrupt, "Other" is always on vector[0].
5601 ixgbe_setup_ivar(ixgbe
, IXGBE_IVAR_OTHER_CAUSES_INDEX
, 0, -1);
5604 * For each interrupt vector, populate the IVAR table
5606 for (v_idx
= 0; v_idx
< ixgbe
->intr_cnt
; v_idx
++) {
5607 vect
= &ixgbe
->vect_map
[v_idx
];
5610 * For each rx ring bit set
5612 r_idx
= bt_getlowbit(vect
->rx_map
, 0,
5613 (ixgbe
->num_rx_rings
- 1));
5615 while (r_idx
>= 0) {
5616 hw_index
= ixgbe
->rx_rings
[r_idx
].hw_index
;
5617 ixgbe_setup_ivar(ixgbe
, hw_index
, v_idx
, 0);
5618 r_idx
= bt_getlowbit(vect
->rx_map
, (r_idx
+ 1),
5619 (ixgbe
->num_rx_rings
- 1));
5623 * For each tx ring bit set
5625 r_idx
= bt_getlowbit(vect
->tx_map
, 0,
5626 (ixgbe
->num_tx_rings
- 1));
5628 while (r_idx
>= 0) {
5629 ixgbe_setup_ivar(ixgbe
, r_idx
, v_idx
, 1);
5630 r_idx
= bt_getlowbit(vect
->tx_map
, (r_idx
+ 1),
5631 (ixgbe
->num_tx_rings
- 1));
5637 * ixgbe_rem_intr_handlers - Remove the interrupt handlers.
5640 ixgbe_rem_intr_handlers(ixgbe_t
*ixgbe
)
5645 for (i
= 0; i
< ixgbe
->intr_cnt
; i
++) {
5646 rc
= ddi_intr_remove_handler(ixgbe
->htable
[i
]);
5647 if (rc
!= DDI_SUCCESS
) {
5648 IXGBE_DEBUGLOG_1(ixgbe
,
5649 "Remove intr handler failed: %d", rc
);
5655 * ixgbe_rem_intrs - Remove the allocated interrupts.
5658 ixgbe_rem_intrs(ixgbe_t
*ixgbe
)
5663 for (i
= 0; i
< ixgbe
->intr_cnt
; i
++) {
5664 rc
= ddi_intr_free(ixgbe
->htable
[i
]);
5665 if (rc
!= DDI_SUCCESS
) {
5666 IXGBE_DEBUGLOG_1(ixgbe
,
5667 "Free intr failed: %d", rc
);
5671 kmem_free(ixgbe
->htable
, ixgbe
->intr_size
);
5672 ixgbe
->htable
= NULL
;
5676 * ixgbe_enable_intrs - Enable all the ddi interrupts.
5679 ixgbe_enable_intrs(ixgbe_t
*ixgbe
)
5687 if (ixgbe
->intr_cap
& DDI_INTR_FLAG_BLOCK
) {
5689 * Call ddi_intr_block_enable() for MSI
5691 rc
= ddi_intr_block_enable(ixgbe
->htable
, ixgbe
->intr_cnt
);
5692 if (rc
!= DDI_SUCCESS
) {
5694 "Enable block intr failed: %d", rc
);
5695 return (IXGBE_FAILURE
);
5699 * Call ddi_intr_enable() for Legacy/MSI non block enable
5701 for (i
= 0; i
< ixgbe
->intr_cnt
; i
++) {
5702 rc
= ddi_intr_enable(ixgbe
->htable
[i
]);
5703 if (rc
!= DDI_SUCCESS
) {
5705 "Enable intr failed: %d", rc
);
5706 return (IXGBE_FAILURE
);
5711 return (IXGBE_SUCCESS
);
5715 * ixgbe_disable_intrs - Disable all the interrupts.
5718 ixgbe_disable_intrs(ixgbe_t
*ixgbe
)
5724 * Disable all interrupts
5726 if (ixgbe
->intr_cap
& DDI_INTR_FLAG_BLOCK
) {
5727 rc
= ddi_intr_block_disable(ixgbe
->htable
, ixgbe
->intr_cnt
);
5728 if (rc
!= DDI_SUCCESS
) {
5730 "Disable block intr failed: %d", rc
);
5731 return (IXGBE_FAILURE
);
5734 for (i
= 0; i
< ixgbe
->intr_cnt
; i
++) {
5735 rc
= ddi_intr_disable(ixgbe
->htable
[i
]);
5736 if (rc
!= DDI_SUCCESS
) {
5738 "Disable intr failed: %d", rc
);
5739 return (IXGBE_FAILURE
);
5744 return (IXGBE_SUCCESS
);
5748 * ixgbe_get_hw_state - Get and save parameters related to adapter hardware.
5751 ixgbe_get_hw_state(ixgbe_t
*ixgbe
)
5753 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
5754 ixgbe_link_speed speed
= 0;
5755 boolean_t link_up
= B_FALSE
;
5756 uint32_t pcs1g_anlp
= 0;
5758 ASSERT(mutex_owned(&ixgbe
->gen_lock
));
5759 ixgbe
->param_lp_1000fdx_cap
= 0;
5760 ixgbe
->param_lp_100fdx_cap
= 0;
5762 /* check for link, don't wait */
5763 (void) ixgbe_check_link(hw
, &speed
, &link_up
, B_FALSE
);
5766 * Update the observed Link Partner's capabilities. Not all adapters
5767 * can provide full information on the LP's capable speeds, so we
5768 * provide what we can.
5771 pcs1g_anlp
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
5773 ixgbe
->param_lp_1000fdx_cap
=
5774 (pcs1g_anlp
& IXGBE_PCS1GANLP_LPFD
) ? 1 : 0;
5775 ixgbe
->param_lp_100fdx_cap
=
5776 (pcs1g_anlp
& IXGBE_PCS1GANLP_LPFD
) ? 1 : 0;
5780 * Update GLD's notion of the adapter's currently advertised speeds.
5781 * Since the common code doesn't always record the current autonegotiate
5782 * settings in the phy struct for all parts (specifically, adapters with
5783 * SFPs) we first test to see if it is 0, and if so, we fall back to
5784 * using the adapter's speed capabilities which we saved during instance
5785 * init in ixgbe_init_params().
5787 * Adapters with SFPs will always be shown as advertising all of their
5788 * supported speeds, and adapters with baseT PHYs (where the phy struct
5789 * is maintained by the common code) will always have a factual view of
5790 * their currently-advertised speeds. In the case of SFPs, this is
5791 * acceptable as we default to advertising all speeds that the adapter
5792 * claims to support, and those properties are immutable; unlike on
5793 * baseT (copper) PHYs, where speeds can be enabled or disabled at will.
5795 speed
= hw
->phy
.autoneg_advertised
;
5797 speed
= ixgbe
->speeds_supported
;
5799 ixgbe
->param_adv_10000fdx_cap
=
5800 (speed
& IXGBE_LINK_SPEED_10GB_FULL
) ? 1 : 0;
5801 ixgbe
->param_adv_5000fdx_cap
=
5802 (speed
& IXGBE_LINK_SPEED_5GB_FULL
) ? 1 : 0;
5803 ixgbe
->param_adv_2500fdx_cap
=
5804 (speed
& IXGBE_LINK_SPEED_2_5GB_FULL
) ? 1 : 0;
5805 ixgbe
->param_adv_1000fdx_cap
=
5806 (speed
& IXGBE_LINK_SPEED_1GB_FULL
) ? 1 : 0;
5807 ixgbe
->param_adv_100fdx_cap
=
5808 (speed
& IXGBE_LINK_SPEED_100_FULL
) ? 1 : 0;
5812 * ixgbe_get_driver_control - Notify that driver is in control of device.
5815 ixgbe_get_driver_control(struct ixgbe_hw
*hw
)
5820 * Notify firmware that driver is in control of device
5822 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
5823 ctrl_ext
|= IXGBE_CTRL_EXT_DRV_LOAD
;
5824 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
5828 * ixgbe_release_driver_control - Notify that driver is no longer in control
5832 ixgbe_release_driver_control(struct ixgbe_hw
*hw
)
5837 * Notify firmware that driver is no longer in control of device
5839 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
5840 ctrl_ext
&= ~IXGBE_CTRL_EXT_DRV_LOAD
;
5841 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
5845 * ixgbe_atomic_reserve - Atomic decrease operation.
5848 ixgbe_atomic_reserve(uint32_t *count_p
, uint32_t n
)
5860 newval
= oldval
- n
;
5861 } while (atomic_cas_32(count_p
, oldval
, newval
) != oldval
);
5867 * ixgbe_mc_table_itr - Traverse the entries in the multicast table.
5870 ixgbe_mc_table_itr(struct ixgbe_hw
*hw
, uint8_t **upd_ptr
, uint32_t *vmdq
)
5872 uint8_t *addr
= *upd_ptr
;
5875 _NOTE(ARGUNUSED(hw
));
5876 _NOTE(ARGUNUSED(vmdq
));
5878 new_ptr
= addr
+ IXGBE_ETH_LENGTH_OF_ADDRESS
;
5887 ixgbe_check_acc_handle(ddi_acc_handle_t handle
)
5891 ddi_fm_acc_err_get(handle
, &de
, DDI_FME_VERSION
);
5892 ddi_fm_acc_err_clear(handle
, DDI_FME_VERSION
);
5893 return (de
.fme_status
);
5897 ixgbe_check_dma_handle(ddi_dma_handle_t handle
)
5901 ddi_fm_dma_err_get(handle
, &de
, DDI_FME_VERSION
);
5902 return (de
.fme_status
);
5906 * ixgbe_fm_error_cb - The IO fault service error handling callback function.
5909 ixgbe_fm_error_cb(dev_info_t
*dip
, ddi_fm_error_t
*err
, const void *impl_data
)
5911 _NOTE(ARGUNUSED(impl_data
));
5913 * as the driver can always deal with an error in any dma or
5914 * access handle, we can just return the fme_status value.
5916 pci_ereport_post(dip
, err
, NULL
);
5917 return (err
->fme_status
);
5921 ixgbe_fm_init(ixgbe_t
*ixgbe
)
5923 ddi_iblock_cookie_t iblk
;
5927 * Only register with IO Fault Services if we have some capability
5929 if (ixgbe
->fm_capabilities
& DDI_FM_ACCCHK_CAPABLE
) {
5930 ixgbe_regs_acc_attr
.devacc_attr_access
= DDI_FLAGERR_ACC
;
5932 ixgbe_regs_acc_attr
.devacc_attr_access
= DDI_DEFAULT_ACC
;
5935 if (ixgbe
->fm_capabilities
& DDI_FM_DMACHK_CAPABLE
) {
5941 ixgbe_set_fma_flags(fma_dma_flag
);
5943 if (ixgbe
->fm_capabilities
) {
5946 * Register capabilities with IO Fault Services
5948 ddi_fm_init(ixgbe
->dip
, &ixgbe
->fm_capabilities
, &iblk
);
5951 * Initialize pci ereport capabilities if ereport capable
5953 if (DDI_FM_EREPORT_CAP(ixgbe
->fm_capabilities
) ||
5954 DDI_FM_ERRCB_CAP(ixgbe
->fm_capabilities
))
5955 pci_ereport_setup(ixgbe
->dip
);
5958 * Register error callback if error callback capable
5960 if (DDI_FM_ERRCB_CAP(ixgbe
->fm_capabilities
))
5961 ddi_fm_handler_register(ixgbe
->dip
,
5962 ixgbe_fm_error_cb
, (void*) ixgbe
);
5967 ixgbe_fm_fini(ixgbe_t
*ixgbe
)
5970 * Only unregister FMA capabilities if they are registered
5972 if (ixgbe
->fm_capabilities
) {
5975 * Release any resources allocated by pci_ereport_setup()
5977 if (DDI_FM_EREPORT_CAP(ixgbe
->fm_capabilities
) ||
5978 DDI_FM_ERRCB_CAP(ixgbe
->fm_capabilities
))
5979 pci_ereport_teardown(ixgbe
->dip
);
5982 * Un-register error callback if error callback capable
5984 if (DDI_FM_ERRCB_CAP(ixgbe
->fm_capabilities
))
5985 ddi_fm_handler_unregister(ixgbe
->dip
);
5988 * Unregister from IO Fault Service
5990 ddi_fm_fini(ixgbe
->dip
);
5995 ixgbe_fm_ereport(ixgbe_t
*ixgbe
, char *detail
)
5998 char buf
[FM_MAX_CLASS
];
6000 (void) snprintf(buf
, FM_MAX_CLASS
, "%s.%s", DDI_FM_DEVICE
, detail
);
6001 ena
= fm_ena_generate(0, FM_ENA_FMT1
);
6002 if (DDI_FM_EREPORT_CAP(ixgbe
->fm_capabilities
)) {
6003 ddi_fm_ereport_post(ixgbe
->dip
, buf
, ena
, DDI_NOSLEEP
,
6004 FM_VERSION
, DATA_TYPE_UINT8
, FM_EREPORT_VERS0
, NULL
);
6009 ixgbe_ring_start(mac_ring_driver_t rh
, uint64_t mr_gen_num
)
6011 ixgbe_rx_ring_t
*rx_ring
= (ixgbe_rx_ring_t
*)rh
;
6013 mutex_enter(&rx_ring
->rx_lock
);
6014 rx_ring
->ring_gen_num
= mr_gen_num
;
6015 mutex_exit(&rx_ring
->rx_lock
);
6020 * Get the global ring index by a ring index within a group.
6023 ixgbe_get_rx_ring_index(ixgbe_t
*ixgbe
, int gindex
, int rindex
)
6025 ixgbe_rx_ring_t
*rx_ring
;
6028 for (i
= 0; i
< ixgbe
->num_rx_rings
; i
++) {
6029 rx_ring
= &ixgbe
->rx_rings
[i
];
6030 if (rx_ring
->group_index
== gindex
)
6040 * Callback funtion for MAC layer to register all rings.
6044 ixgbe_fill_ring(void *arg
, mac_ring_type_t rtype
, const int group_index
,
6045 const int ring_index
, mac_ring_info_t
*infop
, mac_ring_handle_t rh
)
6047 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg
;
6048 mac_intr_t
*mintr
= &infop
->mri_intr
;
6051 case MAC_RING_TYPE_RX
: {
6053 * 'index' is the ring index within the group.
6054 * Need to get the global ring index by searching in groups.
6056 int global_ring_index
= ixgbe_get_rx_ring_index(
6057 ixgbe
, group_index
, ring_index
);
6059 ASSERT(global_ring_index
>= 0);
6061 ixgbe_rx_ring_t
*rx_ring
= &ixgbe
->rx_rings
[global_ring_index
];
6062 rx_ring
->ring_handle
= rh
;
6064 infop
->mri_driver
= (mac_ring_driver_t
)rx_ring
;
6065 infop
->mri_start
= ixgbe_ring_start
;
6066 infop
->mri_stop
= NULL
;
6067 infop
->mri_poll
= ixgbe_ring_rx_poll
;
6068 infop
->mri_stat
= ixgbe_rx_ring_stat
;
6070 mintr
->mi_handle
= (mac_intr_handle_t
)rx_ring
;
6071 mintr
->mi_enable
= ixgbe_rx_ring_intr_enable
;
6072 mintr
->mi_disable
= ixgbe_rx_ring_intr_disable
;
6073 if (ixgbe
->intr_type
&
6074 (DDI_INTR_TYPE_MSIX
| DDI_INTR_TYPE_MSI
)) {
6075 mintr
->mi_ddi_handle
=
6076 ixgbe
->htable
[rx_ring
->intr_vector
];
6081 case MAC_RING_TYPE_TX
: {
6082 ASSERT(group_index
== -1);
6083 ASSERT(ring_index
< ixgbe
->num_tx_rings
);
6085 ixgbe_tx_ring_t
*tx_ring
= &ixgbe
->tx_rings
[ring_index
];
6086 tx_ring
->ring_handle
= rh
;
6088 infop
->mri_driver
= (mac_ring_driver_t
)tx_ring
;
6089 infop
->mri_start
= NULL
;
6090 infop
->mri_stop
= NULL
;
6091 infop
->mri_tx
= ixgbe_ring_tx
;
6092 infop
->mri_stat
= ixgbe_tx_ring_stat
;
6093 if (ixgbe
->intr_type
&
6094 (DDI_INTR_TYPE_MSIX
| DDI_INTR_TYPE_MSI
)) {
6095 mintr
->mi_ddi_handle
=
6096 ixgbe
->htable
[tx_ring
->intr_vector
];
6106 * Callback funtion for MAC layer to register all groups.
6109 ixgbe_fill_group(void *arg
, mac_ring_type_t rtype
, const int index
,
6110 mac_group_info_t
*infop
, mac_group_handle_t gh
)
6112 ixgbe_t
*ixgbe
= (ixgbe_t
*)arg
;
6115 case MAC_RING_TYPE_RX
: {
6116 ixgbe_rx_group_t
*rx_group
;
6118 rx_group
= &ixgbe
->rx_groups
[index
];
6119 rx_group
->group_handle
= gh
;
6121 infop
->mgi_driver
= (mac_group_driver_t
)rx_group
;
6122 infop
->mgi_start
= NULL
;
6123 infop
->mgi_stop
= NULL
;
6124 infop
->mgi_addmac
= ixgbe_addmac
;
6125 infop
->mgi_remmac
= ixgbe_remmac
;
6126 infop
->mgi_count
= (ixgbe
->num_rx_rings
/ ixgbe
->num_rx_groups
);
6130 case MAC_RING_TYPE_TX
:
6138 * Enable interrupt on the specificed rx ring.
6141 ixgbe_rx_ring_intr_enable(mac_intr_handle_t intrh
)
6143 ixgbe_rx_ring_t
*rx_ring
= (ixgbe_rx_ring_t
*)intrh
;
6144 ixgbe_t
*ixgbe
= rx_ring
->ixgbe
;
6145 int r_idx
= rx_ring
->index
;
6146 int hw_r_idx
= rx_ring
->hw_index
;
6147 int v_idx
= rx_ring
->intr_vector
;
6149 mutex_enter(&ixgbe
->gen_lock
);
6150 if (ixgbe
->ixgbe_state
& IXGBE_INTR_ADJUST
) {
6151 mutex_exit(&ixgbe
->gen_lock
);
6154 * Interrupts are being adjusted. ixgbe_intr_adjust()
6155 * will eventually re-enable the interrupt when it's
6156 * done with the adjustment.
6162 * To enable interrupt by setting the VAL bit of given interrupt
6163 * vector allocation register (IVAR).
6165 ixgbe_enable_ivar(ixgbe
, hw_r_idx
, 0);
6167 BT_SET(ixgbe
->vect_map
[v_idx
].rx_map
, r_idx
);
6170 * Trigger a Rx interrupt on this ring
6172 IXGBE_WRITE_REG(&ixgbe
->hw
, IXGBE_EICS
, (1 << v_idx
));
6173 IXGBE_WRITE_FLUSH(&ixgbe
->hw
);
6175 mutex_exit(&ixgbe
->gen_lock
);
6181 * Disable interrupt on the specificed rx ring.
6184 ixgbe_rx_ring_intr_disable(mac_intr_handle_t intrh
)
6186 ixgbe_rx_ring_t
*rx_ring
= (ixgbe_rx_ring_t
*)intrh
;
6187 ixgbe_t
*ixgbe
= rx_ring
->ixgbe
;
6188 int r_idx
= rx_ring
->index
;
6189 int hw_r_idx
= rx_ring
->hw_index
;
6190 int v_idx
= rx_ring
->intr_vector
;
6192 mutex_enter(&ixgbe
->gen_lock
);
6193 if (ixgbe
->ixgbe_state
& IXGBE_INTR_ADJUST
) {
6194 mutex_exit(&ixgbe
->gen_lock
);
6197 * In the rare case where an interrupt is being
6198 * disabled while interrupts are being adjusted,
6199 * we don't fail the operation. No interrupts will
6200 * be generated while they are adjusted, and
6201 * ixgbe_intr_adjust() will cause the interrupts
6202 * to be re-enabled once it completes. Note that
6203 * in this case, packets may be delivered to the
6204 * stack via interrupts before xgbe_rx_ring_intr_enable()
6205 * is called again. This is acceptable since interrupt
6206 * adjustment is infrequent, and the stack will be
6207 * able to handle these packets.
6213 * To disable interrupt by clearing the VAL bit of given interrupt
6214 * vector allocation register (IVAR).
6216 ixgbe_disable_ivar(ixgbe
, hw_r_idx
, 0);
6218 BT_CLEAR(ixgbe
->vect_map
[v_idx
].rx_map
, r_idx
);
6220 mutex_exit(&ixgbe
->gen_lock
);
6226 * Add a mac address.
6229 ixgbe_addmac(void *arg
, const uint8_t *mac_addr
)
6231 ixgbe_rx_group_t
*rx_group
= (ixgbe_rx_group_t
*)arg
;
6232 ixgbe_t
*ixgbe
= rx_group
->ixgbe
;
6233 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
6236 mutex_enter(&ixgbe
->gen_lock
);
6238 if (ixgbe
->ixgbe_state
& IXGBE_SUSPENDED
) {
6239 mutex_exit(&ixgbe
->gen_lock
);
6243 if (ixgbe
->unicst_avail
== 0) {
6244 /* no slots available */
6245 mutex_exit(&ixgbe
->gen_lock
);
6250 * The first ixgbe->num_rx_groups slots are reserved for each respective
6251 * group. The rest slots are shared by all groups. While adding a
6252 * MAC address, reserved slots are firstly checked then the shared
6253 * slots are searched.
6256 if (ixgbe
->unicst_addr
[rx_group
->index
].mac
.set
== 1) {
6257 for (i
= ixgbe
->num_rx_groups
; i
< ixgbe
->unicst_total
; i
++) {
6258 if (ixgbe
->unicst_addr
[i
].mac
.set
== 0) {
6264 slot
= rx_group
->index
;
6268 /* no slots available */
6269 mutex_exit(&ixgbe
->gen_lock
);
6273 bcopy(mac_addr
, ixgbe
->unicst_addr
[slot
].mac
.addr
, ETHERADDRL
);
6274 (void) ixgbe_set_rar(hw
, slot
, ixgbe
->unicst_addr
[slot
].mac
.addr
,
6275 rx_group
->index
, IXGBE_RAH_AV
);
6276 ixgbe
->unicst_addr
[slot
].mac
.set
= 1;
6277 ixgbe
->unicst_addr
[slot
].mac
.group_index
= rx_group
->index
;
6278 ixgbe
->unicst_avail
--;
6280 mutex_exit(&ixgbe
->gen_lock
);
6286 * Remove a mac address.
6289 ixgbe_remmac(void *arg
, const uint8_t *mac_addr
)
6291 ixgbe_rx_group_t
*rx_group
= (ixgbe_rx_group_t
*)arg
;
6292 ixgbe_t
*ixgbe
= rx_group
->ixgbe
;
6293 struct ixgbe_hw
*hw
= &ixgbe
->hw
;
6296 mutex_enter(&ixgbe
->gen_lock
);
6298 if (ixgbe
->ixgbe_state
& IXGBE_SUSPENDED
) {
6299 mutex_exit(&ixgbe
->gen_lock
);
6303 slot
= ixgbe_unicst_find(ixgbe
, mac_addr
);
6305 mutex_exit(&ixgbe
->gen_lock
);
6309 if (ixgbe
->unicst_addr
[slot
].mac
.set
== 0) {
6310 mutex_exit(&ixgbe
->gen_lock
);
6314 bzero(ixgbe
->unicst_addr
[slot
].mac
.addr
, ETHERADDRL
);
6315 (void) ixgbe_clear_rar(hw
, slot
);
6316 ixgbe
->unicst_addr
[slot
].mac
.set
= 0;
6317 ixgbe
->unicst_avail
++;
6319 mutex_exit(&ixgbe
->gen_lock
);