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Merge commit '6dfcdabd85f09409c5d2f9fb25a3013384ffaf74' into merges
[unleashed.git] / include / sys / smbios.h
blobd3dc2b4d8ed219fb507c61959cd33c1f3b724796
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
24 * Copyright (c) 2017, Joyent, Inc.
25 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
26 * Use is subject to license terms.
27 */
28
29 /*
30 * This header file defines the interfaces available from the SMBIOS access
31 * library, libsmbios, and an equivalent kernel module. This API can be used
32 * to access DMTF SMBIOS data from a device, file, or raw memory buffer.
33 *
34 * This is NOT a Public interface, and should be considered Unstable, as it is
35 * subject to change without notice as the DMTF SMBIOS specification evolves.
36 * Therefore, be aware that any program linked with this API in this
37 * instance of illumos is almost guaranteed to break in the next release.
38 */
39
40 #ifndef _SYS_SMBIOS_H
41 #define _SYS_SMBIOS_H
42
43 #include <sys/types.h>
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 typedef enum smbios_entry_point_type {
50 SMBIOS_ENTRY_POINT_21,
51 SMBIOS_ENTRY_POINT_30
52 } smbios_entry_point_t;
53
54 /*
55 * SMBIOS Structure Table Entry Point. See DSP0134 5.2.1 for more information.
56 * The structure table entry point is located by searching for the anchor.
57 */
58 #pragma pack(1)
59
60 typedef struct smbios_21_entry {
61 char smbe_eanchor[4]; /* anchor tag (SMB_ENTRY_EANCHOR) */
62 uint8_t smbe_ecksum; /* checksum of entry point structure */
63 uint8_t smbe_elen; /* length in bytes of entry point */
64 uint8_t smbe_major; /* major version of the SMBIOS spec */
65 uint8_t smbe_minor; /* minor version of the SMBIOS spec */
66 uint16_t smbe_maxssize; /* maximum size in bytes of a struct */
67 uint8_t smbe_revision; /* entry point structure revision */
68 uint8_t smbe_format[5]; /* entry point revision-specific data */
69 char smbe_ianchor[5]; /* intermed. tag (SMB_ENTRY_IANCHOR) */
70 uint8_t smbe_icksum; /* intermed. checksum */
71 uint16_t smbe_stlen; /* length in bytes of structure table */
72 uint32_t smbe_staddr; /* physical addr of structure table */
73 uint16_t smbe_stnum; /* number of structure table entries */
74 uint8_t smbe_bcdrev; /* BCD value representing DMI version */
75 } smbios_21_entry_t;
76
77 /*
78 * The 64-bit SMBIOS 3.0 Entry Point. See DSP0134 5.2.2 for more information.
79 * The structure table entry point is located by searching for the anchor.
80 */
81
82 typedef struct smbios_30_entry {
83 char smbe_eanchor[5]; /* anchor tag (SMB3_ENTRY_EANCHOR) */
84 uint8_t smbe_ecksum; /* checksum of entry point structure */
85 uint8_t smbe_elen; /* length in bytes of entry point */
86 uint8_t smbe_major; /* major version of the SMBIOS spec */
87 uint8_t smbe_minor; /* minor version of the SMBIOS spec */
88 uint8_t smbe_docrev; /* specification docrev */
89 uint8_t smbe_revision; /* entry point structure revision */
90 uint8_t smbe_reserved;
91 uint32_t smbe_stlen; /* length in bytes of structure table */
92 uint64_t smbe_staddr; /* physical addr of structure table */
93 } smbios_30_entry_t;
94
95 typedef union {
96 smbios_21_entry_t ep21;
97 smbios_30_entry_t ep30;
98 } smbios_entry_t;
99
100 #pragma pack()
101
102 #define SMB_ENTRY_EANCHOR "_SM_" /* structure table entry point anchor */
103 #define SMB_ENTRY_EANCHORLEN 4 /* length of entry point anchor */
104 #define SMB3_ENTRY_EANCHOR "_SM3_" /* structure table entry point anchor */
105 #define SMB3_ENTRY_EANCHORLEN 5 /* length of entry point anchor */
106 #define SMB_ENTRY_IANCHOR "_DMI_" /* intermediate anchor string */
107 #define SMB_ENTRY_IANCHORLEN 5 /* length of intermediate anchor */
108 #define SMB_ENTRY_MAXLEN 255 /* maximum length of entry point */
109
110 /*
111 * Structure type codes. The comments next to each type include an (R) note to
112 * indicate a structure that is required as of SMBIOS v2.8 and an (O) note to
113 * indicate a structure that is obsolete as of SMBIOS v2.8.
114 */
115 #define SMB_TYPE_BIOS 0 /* BIOS information (R) */
116 #define SMB_TYPE_SYSTEM 1 /* system information (R) */
117 #define SMB_TYPE_BASEBOARD 2 /* base board */
118 #define SMB_TYPE_CHASSIS 3 /* system enclosure or chassis (R) */
119 #define SMB_TYPE_PROCESSOR 4 /* processor (R) */
120 #define SMB_TYPE_MEMCTL 5 /* memory controller (O) */
121 #define SMB_TYPE_MEMMOD 6 /* memory module (O) */
122 #define SMB_TYPE_CACHE 7 /* processor cache (R) */
123 #define SMB_TYPE_PORT 8 /* port connector */
124 #define SMB_TYPE_SLOT 9 /* upgradeable system slot (R) */
125 #define SMB_TYPE_OBDEVS 10 /* on-board devices (O) */
126 #define SMB_TYPE_OEMSTR 11 /* OEM string table */
127 #define SMB_TYPE_SYSCONFSTR 12 /* system configuration string table */
128 #define SMB_TYPE_LANG 13 /* BIOS language information */
129 #define SMB_TYPE_GROUP 14 /* group associations */
130 #define SMB_TYPE_EVENTLOG 15 /* system event log */
131 #define SMB_TYPE_MEMARRAY 16 /* physical memory array (R) */
132 #define SMB_TYPE_MEMDEVICE 17 /* memory device (R) */
133 #define SMB_TYPE_MEMERR32 18 /* 32-bit memory error information */
134 #define SMB_TYPE_MEMARRAYMAP 19 /* memory array mapped address (R) */
135 #define SMB_TYPE_MEMDEVICEMAP 20 /* memory device mapped address */
136 #define SMB_TYPE_POINTDEV 21 /* built-in pointing device */
137 #define SMB_TYPE_BATTERY 22 /* portable battery */
138 #define SMB_TYPE_RESET 23 /* system reset settings */
139 #define SMB_TYPE_SECURITY 24 /* hardware security settings */
140 #define SMB_TYPE_POWERCTL 25 /* system power controls */
141 #define SMB_TYPE_VPROBE 26 /* voltage probe */
142 #define SMB_TYPE_COOLDEV 27 /* cooling device */
143 #define SMB_TYPE_TPROBE 28 /* temperature probe */
144 #define SMB_TYPE_IPROBE 29 /* current probe */
145 #define SMB_TYPE_OOBRA 30 /* out-of-band remote access facility */
146 #define SMB_TYPE_BIS 31 /* boot integrity services */
147 #define SMB_TYPE_BOOT 32 /* system boot status (R) */
148 #define SMB_TYPE_MEMERR64 33 /* 64-bit memory error information */
149 #define SMB_TYPE_MGMTDEV 34 /* management device */
150 #define SMB_TYPE_MGMTDEVCP 35 /* management device component */
151 #define SMB_TYPE_MGMTDEVDATA 36 /* management device threshold data */
152 #define SMB_TYPE_MEMCHAN 37 /* memory channel */
153 #define SMB_TYPE_IPMIDEV 38 /* IPMI device information */
154 #define SMB_TYPE_POWERSUP 39 /* system power supply */
155 #define SMB_TYPE_ADDINFO 40 /* additional information */
156 #define SMB_TYPE_OBDEVEXT 41 /* on-board device extended info */
157 #define SMB_TYPE_MCHI 42 /* mgmt controller host interface */
158 #define SMB_TYPE_TPM 43 /* TPM device */
159 #define SMB_TYPE_INACTIVE 126 /* inactive table entry */
160 #define SMB_TYPE_EOT 127 /* end of table */
161
162 #define SMB_TYPE_OEM_LO 128 /* start of OEM-specific type range */
163 #define SUN_OEM_EXT_PROCESSOR 132 /* processor extended info */
164 #define SUN_OEM_EXT_PORT 136 /* port exteded info */
165 #define SUN_OEM_PCIEXRC 138 /* PCIE RootComplex/RootPort info */
166 #define SUN_OEM_EXT_MEMARRAY 144 /* phys memory array extended info */
167 #define SUN_OEM_EXT_MEMDEVICE 145 /* memory device extended info */
168 #define SMB_TYPE_OEM_HI 256 /* end of OEM-specific type range */
169
170 /*
171 * OEM string indicating "Platform Resource Management Specification"
172 * compliance.
173 */
174 #define SMB_PRMS1 "SUNW-PRMS-1"
175
176 /*
177 * Some default values set by BIOS vendor
178 */
179 #define SMB_DEFAULT1 "To Be Filled By O.E.M."
180 #define SMB_DEFAULT2 "Not Available"
181
182 /*
183 * SMBIOS Common Information. These structures do not correspond to anything
184 * in the SMBIOS specification, but allow library clients to more easily read
185 * information that is frequently encoded into the various SMBIOS structures.
186 */
187 typedef struct smbios_info {
188 const char *smbi_manufacturer; /* manufacturer */
189 const char *smbi_product; /* product name */
190 const char *smbi_version; /* version */
191 const char *smbi_serial; /* serial number */
192 const char *smbi_asset; /* asset tag */
193 const char *smbi_location; /* location tag */
194 const char *smbi_part; /* part number */
195 } smbios_info_t;
196
197 typedef struct smbios_version {
198 uint8_t smbv_major; /* version major number */
199 uint8_t smbv_minor; /* version minor number */
200 } smbios_version_t;
201
202 #define SMB_CONT_BYTE 1 /* contained elements are byte size */
203 #define SMB_CONT_WORD 2 /* contained elements are word size */
204 #define SMB_CONT_MAX 255 /* maximum contained objects */
205
206 /*
207 * SMBIOS Bios Information. See DSP0134 Section 7.1 for more information.
208 * smbb_romsize is converted from the implementation format into bytes. Note, if
209 * we do not have an extended BIOS ROM size, it is filled in with the default
210 * BIOS ROM size.
211 */
212 typedef struct smbios_bios {
213 const char *smbb_vendor; /* bios vendor string */
214 const char *smbb_version; /* bios version string */
215 const char *smbb_reldate; /* bios release date */
216 uint32_t smbb_segment; /* bios address segment location */
217 uint32_t smbb_romsize; /* bios rom size in bytes */
218 uint32_t smbb_runsize; /* bios image size in bytes */
219 uint64_t smbb_cflags; /* bios characteristics */
220 const uint8_t *smbb_xcflags; /* bios characteristics extensions */
221 size_t smbb_nxcflags; /* number of smbb_xcflags[] bytes */
222 smbios_version_t smbb_biosv; /* bios version */
223 smbios_version_t smbb_ecfwv; /* bios embedded ctrl f/w version */
224 uint64_t smbb_extromsize; /* Extended bios ROM Size */
225 } smbios_bios_t;
226
227 #define SMB_BIOSFL_RSV0 0x00000001 /* reserved bit zero */
228 #define SMB_BIOSFL_RSV1 0x00000002 /* reserved bit one */
229 #define SMB_BIOSFL_UNKNOWN 0x00000004 /* unknown */
230 #define SMB_BIOSFL_BCNOTSUP 0x00000008 /* BIOS chars not supported */
231 #define SMB_BIOSFL_ISA 0x00000010 /* ISA is supported */
232 #define SMB_BIOSFL_MCA 0x00000020 /* MCA is supported */
233 #define SMB_BIOSFL_EISA 0x00000040 /* EISA is supported */
234 #define SMB_BIOSFL_PCI 0x00000080 /* PCI is supported */
235 #define SMB_BIOSFL_PCMCIA 0x00000100 /* PCMCIA is supported */
236 #define SMB_BIOSFL_PLUGNPLAY 0x00000200 /* Plug and Play is supported */
237 #define SMB_BIOSFL_APM 0x00000400 /* APM is supported */
238 #define SMB_BIOSFL_FLASH 0x00000800 /* BIOS is Flash Upgradeable */
239 #define SMB_BIOSFL_SHADOW 0x00001000 /* BIOS shadowing is allowed */
240 #define SMB_BIOSFL_VLVESA 0x00002000 /* VL-VESA is supported */
241 #define SMB_BIOSFL_ESCD 0x00004000 /* ESCD support is available */
242 #define SMB_BIOSFL_CDBOOT 0x00008000 /* Boot from CD is supported */
243 #define SMB_BIOSFL_SELBOOT 0x00010000 /* Selectable Boot supported */
244 #define SMB_BIOSFL_ROMSOCK 0x00020000 /* BIOS ROM is socketed */
245 #define SMB_BIOSFL_PCMBOOT 0x00040000 /* Boot from PCMCIA supported */
246 #define SMB_BIOSFL_EDD 0x00080000 /* EDD Spec is supported */
247 #define SMB_BIOSFL_NEC9800 0x00100000 /* int 0x13 NEC 9800 floppy */
248 #define SMB_BIOSFL_TOSHIBA 0x00200000 /* int 0x13 Toshiba floppy */
249 #define SMB_BIOSFL_525_360K 0x00400000 /* int 0x13 5.25" 360K floppy */
250 #define SMB_BIOSFL_525_12M 0x00800000 /* int 0x13 5.25" 1.2M floppy */
251 #define SMB_BIOSFL_35_720K 0x01000000 /* int 0x13 3.5" 720K floppy */
252 #define SMB_BIOSFL_35_288M 0x02000000 /* int 0x13 3.5" 2.88M floppy */
253 #define SMB_BIOSFL_I5_PRINT 0x04000000 /* int 0x5 print screen svcs */
254 #define SMB_BIOSFL_I9_KBD 0x08000000 /* int 0x9 8042 keyboard svcs */
255 #define SMB_BIOSFL_I14_SER 0x10000000 /* int 0x14 serial svcs */
256 #define SMB_BIOSFL_I17_PRINTER 0x20000000 /* int 0x17 printer svcs */
257 #define SMB_BIOSFL_I10_CGA 0x40000000 /* int 0x10 CGA svcs */
258 #define SMB_BIOSFL_NEC_PC98 0x80000000 /* NEC PC-98 */
259
260 /*
261 * These values are used to allow consumers to have raw access to the extended
262 * characteristic flags. We explicitly don't include the extended BIOS
263 * information from section 3.1 as part of this as it has its own member.
264 */
265 #define SMB_BIOSXB_1 0 /* bios extension byte 1 (7.1.2.1) */
266 #define SMB_BIOSXB_2 1 /* bios extension byte 2 (7.1.2.2) */
267 #define SMB_BIOSXB_BIOS_MAJ 2 /* bios major version */
268 #define SMB_BIOSXB_BIOS_MIN 3 /* bios minor version */
269 #define SMB_BIOSXB_ECFW_MAJ 4 /* extended ctlr f/w major version */
270 #define SMB_BIOSXB_ECFW_MIN 5 /* extended ctlr f/w minor version */
271
272 #define SMB_BIOSXB1_ACPI 0x01 /* ACPI is supported */
273 #define SMB_BIOSXB1_USBL 0x02 /* USB legacy is supported */
274 #define SMB_BIOSXB1_AGP 0x04 /* AGP is supported */
275 #define SMB_BIOSXB1_I20 0x08 /* I2O boot is supported */
276 #define SMB_BIOSXB1_LS120 0x10 /* LS-120 boot is supported */
277 #define SMB_BIOSXB1_ATZIP 0x20 /* ATAPI ZIP drive boot is supported */
278 #define SMB_BIOSXB1_1394 0x40 /* 1394 boot is supported */
279 #define SMB_BIOSXB1_SMBAT 0x80 /* Smart Battery is supported */
280
281 #define SMB_BIOSXB2_BBOOT 0x01 /* BIOS Boot Specification supported */
282 #define SMB_BIOSXB2_FKNETSVC 0x02 /* F-key Network Svc boot supported */
283 #define SMB_BIOSXB2_ETCDIST 0x04 /* Enable Targeted Content Distrib. */
284 #define SMB_BIOSXB2_UEFI 0x08 /* UEFI Specification supported */
285 #define SMB_BIOSXB2_VM 0x10 /* SMBIOS table describes a VM */
286
287 /*
288 * SMBIOS System Information. See DSP0134 Section 7.2 for more information.
289 * The current set of smbs_wakeup values is defined after the structure.
290 */
291 typedef struct smbios_system {
292 const uint8_t *smbs_uuid; /* UUID byte array */
293 uint8_t smbs_uuidlen; /* UUID byte array length */
294 uint8_t smbs_wakeup; /* wake-up event */
295 const char *smbs_sku; /* SKU number */
296 const char *smbs_family; /* family */
297 } smbios_system_t;
298
299 #define SMB_WAKEUP_RSV0 0x00 /* reserved */
300 #define SMB_WAKEUP_OTHER 0x01 /* other */
301 #define SMB_WAKEUP_UNKNOWN 0x02 /* unknown */
302 #define SMB_WAKEUP_APM 0x03 /* APM timer */
303 #define SMB_WAKEUP_MODEM 0x04 /* modem ring */
304 #define SMB_WAKEUP_LAN 0x05 /* LAN remote */
305 #define SMB_WAKEUP_SWITCH 0x06 /* power switch */
306 #define SMB_WAKEUP_PCIPME 0x07 /* PCI PME# */
307 #define SMB_WAKEUP_AC 0x08 /* AC power restored */
308
309 /*
310 * SMBIOS Base Board description. See DSP0134 Section 7.3 for more
311 * information. smbb_flags and smbb_type definitions are below.
312 */
313 typedef struct smbios_bboard {
314 id_t smbb_chassis; /* chassis containing this board */
315 uint8_t smbb_flags; /* flags (see below) */
316 uint8_t smbb_type; /* board type (see below) */
317 uint8_t smbb_contn; /* number of contained object hdls */
318 } smbios_bboard_t;
319
320 #define SMB_BBFL_MOTHERBOARD 0x01 /* board is a motherboard */
321 #define SMB_BBFL_NEEDAUX 0x02 /* auxiliary card or daughter req'd */
322 #define SMB_BBFL_REMOVABLE 0x04 /* board is removable */
323 #define SMB_BBFL_REPLACABLE 0x08 /* board is field-replacable */
324 #define SMB_BBFL_HOTSWAP 0x10 /* board is hot-swappable */
325
326 #define SMB_BBT_UNKNOWN 0x1 /* unknown */
327 #define SMB_BBT_OTHER 0x2 /* other */
328 #define SMB_BBT_SBLADE 0x3 /* server blade */
329 #define SMB_BBT_CSWITCH 0x4 /* connectivity switch */
330 #define SMB_BBT_SMM 0x5 /* system management module */
331 #define SMB_BBT_PROC 0x6 /* processor module */
332 #define SMB_BBT_IO 0x7 /* i/o module */
333 #define SMB_BBT_MEM 0x8 /* memory module */
334 #define SMB_BBT_DAUGHTER 0x9 /* daughterboard */
335 #define SMB_BBT_MOTHER 0xA /* motherboard */
336 #define SMB_BBT_PROCMEM 0xB /* processor/memory module */
337 #define SMB_BBT_PROCIO 0xC /* processor/i/o module */
338 #define SMB_BBT_INTER 0xD /* interconnect board */
339
340 /*
341 * SMBIOS Chassis description. See DSP0134 Section 7.4 for more information.
342 * We move the lock bit of the type field into smbc_lock for easier processing.
343 */
344 typedef struct smbios_chassis {
345 uint32_t smbc_oemdata; /* OEM-specific data */
346 uint8_t smbc_lock; /* lock present? */
347 uint8_t smbc_type; /* type */
348 uint8_t smbc_bustate; /* boot-up state */
349 uint8_t smbc_psstate; /* power supply state */
350 uint8_t smbc_thstate; /* thermal state */
351 uint8_t smbc_security; /* security status */
352 uint8_t smbc_uheight; /* enclosure height in U's */
353 uint8_t smbc_cords; /* number of power cords */
354 uint8_t smbc_elems; /* number of element records (n) */
355 uint8_t smbc_elemlen; /* length of contained element (m) */
356 char smbc_sku[256]; /* SKU number (as a string) */
357 } smbios_chassis_t;
358
359 #define SMB_CHT_OTHER 0x01 /* other */
360 #define SMB_CHT_UNKNOWN 0x02 /* unknown */
361 #define SMB_CHT_DESKTOP 0x03 /* desktop */
362 #define SMB_CHT_LPDESKTOP 0x04 /* low-profile desktop */
363 #define SMB_CHT_PIZZA 0x05 /* pizza box */
364 #define SMB_CHT_MINITOWER 0x06 /* mini-tower */
365 #define SMB_CHT_TOWER 0x07 /* tower */
366 #define SMB_CHT_PORTABLE 0x08 /* portable */
367 #define SMB_CHT_LAPTOP 0x09 /* laptop */
368 #define SMB_CHT_NOTEBOOK 0x0A /* notebook */
369 #define SMB_CHT_HANDHELD 0x0B /* hand-held */
370 #define SMB_CHT_DOCK 0x0C /* docking station */
371 #define SMB_CHT_ALLIN1 0x0D /* all-in-one */
372 #define SMB_CHT_SUBNOTE 0x0E /* sub-notebook */
373 #define SMB_CHT_SPACESAVE 0x0F /* space-saving */
374 #define SMB_CHT_LUNCHBOX 0x10 /* lunchbox */
375 #define SMB_CHT_MAIN 0x11 /* main server chassis */
376 #define SMB_CHT_EXPANSION 0x12 /* expansion chassis */
377 #define SMB_CHT_SUB 0x13 /* sub-chassis */
378 #define SMB_CHT_BUS 0x14 /* bus expansion chassis */
379 #define SMB_CHT_PERIPHERAL 0x15 /* peripheral chassis */
380 #define SMB_CHT_RAID 0x16 /* raid chassis */
381 #define SMB_CHT_RACK 0x17 /* rack mount chassis */
382 #define SMB_CHT_SEALED 0x18 /* sealed case pc */
383 #define SMB_CHT_MULTI 0x19 /* multi-system chassis */
384 #define SMB_CHT_CPCI 0x1A /* compact PCI */
385 #define SMB_CHT_ATCA 0x1B /* advanced TCA */
386 #define SMB_CHT_BLADE 0x1C /* blade */
387 #define SMB_CHT_BLADEENC 0x1D /* blade enclosure */
388 #define SMB_CHT_TABLET 0x1E /* tablet */
389 #define SMB_CHT_CONVERTIBLE 0x1F /* convertible */
390 #define SMB_CHT_DETACHABLE 0x20 /* detachable */
391 #define SMB_CHT_IOTGW 0x21 /* IoT Gateway */
392 #define SMB_CHT_EMBEDPC 0x22 /* Embedded PC */
393 #define SMB_CHT_MINIPC 0x23 /* Mini PC */
394 #define SMB_CHT_STICKPC 0x24 /* Stick PC */
395
396 #define SMB_CHST_OTHER 0x01 /* other */
397 #define SMB_CHST_UNKNOWN 0x02 /* unknown */
398 #define SMB_CHST_SAFE 0x03 /* safe */
399 #define SMB_CHST_WARNING 0x04 /* warning */
400 #define SMB_CHST_CRITICAL 0x05 /* critical */
401 #define SMB_CHST_NONREC 0x06 /* non-recoverable */
402
403 #define SMB_CHSC_OTHER 0x01 /* other */
404 #define SMB_CHSC_UNKNOWN 0x02 /* unknown */
405 #define SMB_CHSC_NONE 0x03 /* none */
406 #define SMB_CHSC_EILOCK 0x04 /* external interface locked out */
407 #define SMB_CHSC_EIENAB 0x05 /* external interface enabled */
408
409 /*
410 * SMBIOS Processor description. See DSP0134 Section 7.5 for more details.
411 * If the L1, L2, or L3 cache handle is -1, the cache information is unknown.
412 * If the handle refers to something of size 0, that type of cache is absent.
413 *
414 * NOTE: Although SMBIOS exports a 64-bit CPUID result, this value should not
415 * be used for any purpose other than BIOS debugging. illumos itself computes
416 * its own CPUID value and applies knowledge of additional errata and processor
417 * specific CPUID variations, so this value should not be used for anything.
418 */
419 typedef struct smbios_processor {
420 uint64_t smbp_cpuid; /* processor cpuid information */
421 uint32_t smbp_family; /* processor family */
422 uint8_t smbp_type; /* processor type (SMB_PRT_*) */
423 uint8_t smbp_voltage; /* voltage (SMB_PRV_*) */
424 uint8_t smbp_status; /* status (SMB_PRS_*) */
425 uint8_t smbp_upgrade; /* upgrade (SMB_PRU_*) */
426 uint32_t smbp_clkspeed; /* external clock speed in MHz */
427 uint32_t smbp_maxspeed; /* maximum speed in MHz */
428 uint32_t smbp_curspeed; /* current speed in MHz */
429 id_t smbp_l1cache; /* L1 cache handle */
430 id_t smbp_l2cache; /* L2 cache handle */
431 id_t smbp_l3cache; /* L3 cache handle */
432 uint32_t smbp_corecount;
433 /* number of cores per processor socket */
434 uint32_t smbp_coresenabled;
435 /* number of enabled cores per processor socket */
436 uint32_t smbp_threadcount;
437 /* number of threads per processor socket */
438 uint16_t smbp_cflags;
439 /* processor characteristics (SMB_PRC_*) */
440 uint16_t smbp_family2; /* processor family 2 */
441 uint16_t smbp_corecount2; /* core count 2 */
442 uint16_t smbp_coresenabled2; /* cores enabled 2 */
443 uint16_t smbp_threadcount2; /* thread count 2 */
444 } smbios_processor_t;
445
446 #define SMB_PRT_OTHER 0x01 /* other */
447 #define SMB_PRT_UNKNOWN 0x02 /* unknown */
448 #define SMB_PRT_CENTRAL 0x03 /* central processor */
449 #define SMB_PRT_MATH 0x04 /* math processor */
450 #define SMB_PRT_DSP 0x05 /* DSP processor */
451 #define SMB_PRT_VIDEO 0x06 /* video processor */
452
453 #define SMB_PRV_LEGACY(v) (!((v) & 0x80)) /* legacy voltage mode */
454 #define SMB_PRV_FIXED(v) ((v) & 0x80) /* fixed voltage mode */
455
456 #define SMB_PRV_5V 0x01 /* 5V is supported */
457 #define SMB_PRV_33V 0x02 /* 3.3V is supported */
458 #define SMB_PRV_29V 0x04 /* 2.9V is supported */
459
460 #define SMB_PRV_VOLTAGE(v) ((v) & 0x7f)
461
462 #define SMB_PRSTATUS_PRESENT(s) ((s) & 0x40) /* socket is populated */
463 #define SMB_PRSTATUS_STATUS(s) ((s) & 0x07) /* status (see below) */
464
465 #define SMB_PRS_UNKNOWN 0x0 /* unknown */
466 #define SMB_PRS_ENABLED 0x1 /* enabled */
467 #define SMB_PRS_BDISABLED 0x2 /* disabled in bios user setup */
468 #define SMB_PRS_PDISABLED 0x3 /* disabled in bios from post error */
469 #define SMB_PRS_IDLE 0x4 /* waiting to be enabled */
470 #define SMB_PRS_OTHER 0x7 /* other */
471
472 #define SMB_PRU_OTHER 0x01 /* other */
473 #define SMB_PRU_UNKNOWN 0x02 /* unknown */
474 #define SMB_PRU_DAUGHTER 0x03 /* daughter board */
475 #define SMB_PRU_ZIF 0x04 /* ZIF socket */
476 #define SMB_PRU_PIGGY 0x05 /* replaceable piggy back */
477 #define SMB_PRU_NONE 0x06 /* none */
478 #define SMB_PRU_LIF 0x07 /* LIF socket */
479 #define SMB_PRU_SLOT1 0x08 /* slot 1 */
480 #define SMB_PRU_SLOT2 0x09 /* slot 2 */
481 #define SMB_PRU_370PIN 0x0A /* 370-pin socket */
482 #define SMB_PRU_SLOTA 0x0B /* slot A */
483 #define SMB_PRU_SLOTM 0x0C /* slot M */
484 #define SMB_PRU_423 0x0D /* socket 423 */
485 #define SMB_PRU_A 0x0E /* socket A (socket 462) */
486 #define SMB_PRU_478 0x0F /* socket 478 */
487 #define SMB_PRU_754 0x10 /* socket 754 */
488 #define SMB_PRU_940 0x11 /* socket 940 */
489 #define SMB_PRU_939 0x12 /* socket 939 */
490 #define SMB_PRU_MPGA604 0x13 /* mPGA604 */
491 #define SMB_PRU_LGA771 0x14 /* LGA771 */
492 #define SMB_PRU_LGA775 0x15 /* LGA775 */
493 #define SMB_PRU_S1 0x16 /* socket S1 */
494 #define SMB_PRU_AM2 0x17 /* socket AM2 */
495 #define SMB_PRU_F 0x18 /* socket F */
496 #define SMB_PRU_LGA1366 0x19 /* LGA1366 */
497 #define SMB_PRU_G34 0x1A /* socket G34 */
498 #define SMB_PRU_AM3 0x1B /* socket AM3 */
499 #define SMB_PRU_C32 0x1C /* socket C32 */
500 #define SMB_PRU_LGA1156 0x1D /* LGA1156 */
501 #define SMB_PRU_LGA1567 0x1E /* LGA1567 */
502 #define SMB_PRU_PGA988A 0x1F /* PGA988A */
503 #define SMB_PRU_BGA1288 0x20 /* BGA1288 */
504 #define SMB_PRU_RPGA988B 0x21 /* rPGA988B */
505 #define SMB_PRU_BGA1023 0x22 /* BGA1023 */
506 #define SMB_PRU_BGA1224 0x23 /* BGA1224 */
507 #define SMB_PRU_LGA1155 0x24 /* LGA1155 */
508 #define SMB_PRU_LGA1356 0x25 /* LGA1356 */
509 #define SMB_PRU_LGA2011 0x26 /* LGA2011 */
510 #define SMB_PRU_FS1 0x27 /* socket FS1 */
511 #define SMB_PRU_FS2 0x28 /* socket FS2 */
512 #define SMB_PRU_FM1 0x29 /* socket FM1 */
513 #define SMB_PRU_FM2 0x2A /* socket FM2 */
514 #define SMB_PRU_LGA20113 0x2B /* LGA2011-3 */
515 #define SMB_PRU_LGA13563 0x2C /* LGA1356-3 */
516 #define SMB_PRU_LGA1150 0x2D /* LGA1150 */
517 #define SMB_PRU_BGA1168 0x2E /* BGA1168 */
518 #define SMB_PRU_BGA1234 0x2F /* BGA1234 */
519 #define SMB_PRU_BGA1364 0x30 /* BGA1364 */
520 #define SMB_PRU_AM4 0x31 /* socket AM4 */
521 #define SMB_PRU_LGA1151 0x32 /* LGA1151 */
522 #define SMB_PRU_BGA1356 0x33 /* BGA1356 */
523 #define SMB_PRU_BGA1440 0x34 /* BGA1440 */
524 #define SMB_PRU_BGA1515 0x35 /* BGA1515 */
525 #define SMB_PRU_LGA36471 0x36 /* LGA3647-1 */
526 #define SMB_PRU_SP3 0x37 /* socket SP3 */
527 #define SMB_PRU_SP3r2 0x38 /* socket SP3r2 */
528
529 #define SMB_PRC_RESERVED 0x0001 /* reserved */
530 #define SMB_PRC_UNKNOWN 0x0002 /* unknown */
531 #define SMB_PRC_64BIT 0x0004 /* 64-bit capable */
532 #define SMB_PRC_MC 0x0008 /* multi-core */
533 #define SMB_PRC_HT 0x0010 /* hardware thread */
534 #define SMB_PRC_NX 0x0020 /* execution protection */
535 #define SMB_PRC_VT 0x0040 /* enhanced virtualization */
536 #define SMB_PRC_PM 0x0080 /* power/performance control */
537
538 #define SMB_PRF_OTHER 0x01 /* other */
539 #define SMB_PRF_UNKNOWN 0x02 /* unknown */
540 #define SMB_PRF_8086 0x03 /* 8086 */
541 #define SMB_PRF_80286 0x04 /* 80286 */
542 #define SMB_PRF_I386 0x05 /* Intel 386 */
543 #define SMB_PRF_I486 0x06 /* Intel 486 */
544 #define SMB_PRF_8087 0x07 /* 8087 */
545 #define SMB_PRF_80287 0x08 /* 80287 */
546 #define SMB_PRF_80387 0x09 /* 80387 */
547 #define SMB_PRF_80487 0x0A /* 80487 */
548 #define SMB_PRF_PENTIUM 0x0B /* Pentium Family */
549 #define SMB_PRF_PENTIUMPRO 0x0C /* Pentium Pro */
550 #define SMB_PRF_PENTIUMII 0x0D /* Pentium II */
551 #define SMB_PRF_PENTIUM_MMX 0x0E /* Pentium w/ MMX */
552 #define SMB_PRF_CELERON 0x0F /* Celeron */
553 #define SMB_PRF_PENTIUMII_XEON 0x10 /* Pentium II Xeon */
554 #define SMB_PRF_PENTIUMIII 0x11 /* Pentium III */
555 #define SMB_PRF_M1 0x12 /* M1 */
556 #define SMB_PRF_M2 0x13 /* M2 */
557 #define SMB_PRF_CELERON_M 0x14 /* Celeron M */
558 #define SMB_PRF_PENTIUMIV_HT 0x15 /* Pentium 4 HT */
559 #define SMB_PRF_DURON 0x18 /* AMD Duron */
560 #define SMB_PRF_K5 0x19 /* K5 */
561 #define SMB_PRF_K6 0x1A /* K6 */
562 #define SMB_PRF_K6_2 0x1B /* K6-2 */
563 #define SMB_PRF_K6_3 0x1C /* K6-3 */
564 #define SMB_PRF_ATHLON 0x1D /* Athlon */
565 #define SMB_PRF_2900 0x1E /* AMD 2900 */
566 #define SMB_PRF_K6_2PLUS 0x1F /* K6-2+ */
567 #define SMB_PRF_PPC 0x20 /* PowerPC */
568 #define SMB_PRF_PPC_601 0x21 /* PowerPC 601 */
569 #define SMB_PRF_PPC_603 0x22 /* PowerPC 603 */
570 #define SMB_PRF_PPC_603PLUS 0x23 /* PowerPC 603+ */
571 #define SMB_PRF_PPC_604 0x24 /* PowerPC 604 */
572 #define SMB_PRF_PPC_620 0x25 /* PowerPC 620 */
573 #define SMB_PRF_PPC_704 0x26 /* PowerPC x704 */
574 #define SMB_PRF_PPC_750 0x27 /* PowerPC 750 */
575 #define SMB_PRF_CORE_DUO 0x28 /* Core Duo */
576 #define SMB_PRF_CORE_DUO_M 0x29 /* Core Duo mobile */
577 #define SMB_PRF_CORE_SOLO_M 0x2A /* Core Solo mobile */
578 #define SMB_PRF_ATOM 0x2B /* Intel Atom */
579 #define SMB_PRF_CORE_M 0x2C /* Intel Core M */
580 #define SMB_PRF_CORE_M3 0x2D /* Intel Core m3 */
581 #define SMB_PRF_CORE_M5 0x2E /* Intel Core m5 */
582 #define SMB_PRF_CORE_M7 0x2F /* Intel Core m7 */
583 #define SMB_PRF_ALPHA 0x30 /* Alpha */
584 #define SMB_PRF_ALPHA_21064 0x31 /* Alpha 21064 */
585 #define SMB_PRF_ALPHA_21066 0x32 /* Alpha 21066 */
586 #define SMB_PRF_ALPHA_21164 0x33 /* Alpha 21164 */
587 #define SMB_PRF_ALPHA_21164PC 0x34 /* Alpha 21164PC */
588 #define SMB_PRF_ALPHA_21164A 0x35 /* Alpha 21164a */
589 #define SMB_PRF_ALPHA_21264 0x36 /* Alpha 21264 */
590 #define SMB_PRF_ALPHA_21364 0x37 /* Alpha 21364 */
591 #define SMB_PRF_TURION2U_2C_MM 0x38
592 /* AMD Turion II Ultra Dual-Core Mobile M */
593 #define SMB_PRF_TURION2_2C_MM 0x39 /* AMD Turion II Dual-Core Mobile M */
594 #define SMB_PRF_ATHLON2_2C_M 0x3A /* AMD Athlon II Dual-Core M */
595 #define SMB_PRF_OPTERON_6100 0x3B /* AMD Opteron 6100 series */
596 #define SMB_PRF_OPTERON_4100 0x3C /* AMD Opteron 4100 series */
597 #define SMB_PRF_OPTERON_6200 0x3D /* AMD Opteron 6200 series */
598 #define SMB_PRF_OPTERON_4200 0x3E /* AMD Opteron 4200 series */
599 #define SMB_PRF_AMD_FX 0x3F /* AMD FX series */
600 #define SMB_PRF_MIPS 0x40 /* MIPS */
601 #define SMB_PRF_MIPS_R4000 0x41 /* MIPS R4000 */
602 #define SMB_PRF_MIPS_R4200 0x42 /* MIPS R4200 */
603 #define SMB_PRF_MIPS_R4400 0x43 /* MIPS R4400 */
604 #define SMB_PRF_MIPS_R4600 0x44 /* MIPS R4600 */
605 #define SMB_PRF_MIPS_R10000 0x45 /* MIPS R10000 */
606 #define SMB_PRF_AMD_C 0x46 /* AMD C-series */
607 #define SMB_PRF_AMD_E 0x47 /* AMD E-series */
608 #define SMB_PRF_AMD_A 0x48 /* AMD A-series */
609 #define SMB_PRF_AMD_G 0x49 /* AMD G-series */
610 #define SMB_PRF_AMD_Z 0x4A /* AMD Z-series */
611 #define SMB_PRF_AMD_R 0x4B /* AMD R-series */
612 #define SMB_PRF_OPTERON_4300 0x4C /* AMD Opteron 4300 series */
613 #define SMB_PRF_OPTERON_6300 0x4D /* AMD Opteron 6300 series */
614 #define SMB_PRF_OPTERON_3300 0x4E /* AMD Opteron 3300 series */
615 #define SMB_PRF_AMD_FIREPRO 0x4F /* AMD FirePro series */
616 #define SMB_PRF_SPARC 0x50 /* SPARC */
617 #define SMB_PRF_SUPERSPARC 0x51 /* SuperSPARC */
618 #define SMB_PRF_MICROSPARCII 0x52 /* microSPARC II */
619 #define SMB_PRF_MICROSPARCIIep 0x53 /* microSPARC IIep */
620 #define SMB_PRF_ULTRASPARC 0x54 /* UltraSPARC */
621 #define SMB_PRF_USII 0x55 /* UltraSPARC II */
622 #define SMB_PRF_USIIi 0x56 /* UltraSPARC IIi */
623 #define SMB_PRF_USIII 0x57 /* UltraSPARC III */
624 #define SMB_PRF_USIIIi 0x58 /* UltraSPARC IIIi */
625 #define SMB_PRF_68040 0x60 /* 68040 */
626 #define SMB_PRF_68XXX 0x61 /* 68XXX */
627 #define SMB_PRF_68000 0x62 /* 68000 */
628 #define SMB_PRF_68010 0x63 /* 68010 */
629 #define SMB_PRF_68020 0x64 /* 68020 */
630 #define SMB_PRF_68030 0x65 /* 68030 */
631 #define SMB_PRF_ATHLON_X4 0x66 /* AMD Athlon X4 Quad-Core */
632 #define SMB_PRF_OPTERON_X1K 0x67 /* AMD Opteron X1000 */
633 #define SMB_PRF_OPTERON_X2K 0x68 /* AMD Opteron X2000 APU */
634 #define SMB_PRF_OPTERON_A 0x69 /* AMD Opteron A Series */
635 #define SMB_PRF_OPTERON_X3K 0x6A /* AMD Opteron X3000 APU */
636 #define SMB_PRF_ZEN 0x6B /* AMD Zen Processor Family */
637 #define SMB_PRF_HOBBIT 0x70 /* Hobbit */
638 #define SMB_PRF_TM5000 0x78 /* Crusoe TM5000 */
639 #define SMB_PRF_TM3000 0x79 /* Crusoe TM3000 */
640 #define SMB_PRF_TM8000 0x7A /* Efficeon TM8000 */
641 #define SMB_PRF_WEITEK 0x80 /* Weitek */
642 #define SMB_PRF_ITANIC 0x82 /* Itanium */
643 #define SMB_PRF_ATHLON64 0x83 /* Athlon64 */
644 #define SMB_PRF_OPTERON 0x84 /* Opteron */
645 #define SMB_PRF_SEMPRON 0x85 /* Sempron */
646 #define SMB_PRF_TURION64_M 0x86 /* Turion 64 Mobile */
647 #define SMB_PRF_OPTERON_2C 0x87 /* AMD Opteron Dual-Core */
648 #define SMB_PRF_ATHLON64_X2_2C 0x88 /* AMD Athlon 64 X2 Dual-Core */
649 #define SMB_PRF_TURION64_X2_M 0x89 /* AMD Turion 64 X2 Mobile */
650 #define SMB_PRF_OPTERON_4C 0x8A /* AMD Opteron Quad-Core */
651 #define SMB_PRF_OPTERON_3G 0x8B /* AMD Opteron 3rd Generation */
652 #define SMB_PRF_PHENOM_FX_4C 0x8C /* AMD Phenom FX Quad-Core */
653 #define SMB_PRF_PHENOM_X4_4C 0x8D /* AMD Phenom X4 Quad-Core */
654 #define SMB_PRF_PHENOM_X2_2C 0x8E /* AMD Phenom X2 Dual-Core */
655 #define SMB_PRF_ATHLON_X2_2C 0x8F /* AMD Athlon X2 Dual-Core */
656 #define SMB_PRF_PA 0x90 /* PA-RISC */
657 #define SMB_PRF_PA8500 0x91 /* PA-RISC 8500 */
658 #define SMB_PRF_PA8000 0x92 /* PA-RISC 8000 */
659 #define SMB_PRF_PA7300LC 0x93 /* PA-RISC 7300LC */
660 #define SMB_PRF_PA7200 0x94 /* PA-RISC 7200 */
661 #define SMB_PRF_PA7100LC 0x95 /* PA-RISC 7100LC */
662 #define SMB_PRF_PA7100 0x96 /* PA-RISC 7100 */
663 #define SMB_PRF_V30 0xA0 /* V30 */
664 #define SMB_PRF_XEON_4C_3200 0xA1 /* Xeon Quad Core 3200 */
665 #define SMB_PRF_XEON_2C_3000 0xA2 /* Xeon Dual Core 3000 */
666 #define SMB_PRF_XEON_4C_5300 0xA3 /* Xeon Quad Core 5300 */
667 #define SMB_PRF_XEON_2C_5100 0xA4 /* Xeon Dual Core 5100 */
668 #define SMB_PRF_XEON_2C_5000 0xA5 /* Xeon Dual Core 5000 */
669 #define SMB_PRF_XEON_2C_LV 0xA6 /* Xeon Dual Core LV */
670 #define SMB_PRF_XEON_2C_ULV 0xA7 /* Xeon Dual Core ULV */
671 #define SMB_PRF_XEON_2C_7100 0xA8 /* Xeon Dual Core 7100 */
672 #define SMB_PRF_XEON_4C_5400 0xA9 /* Xeon Quad Core 5400 */
673 #define SMB_PRF_XEON_4C 0xAA /* Xeon Quad Core */
674 #define SMB_PRF_XEON_2C_5200 0xAB /* Xeon Dual Core 5200 */
675 #define SMB_PRF_XEON_2C_7200 0xAC /* Xeon Dual Core 7200 */
676 #define SMB_PRF_XEON_4C_7300 0xAD /* Xeon Quad Core 7300 */
677 #define SMB_PRF_XEON_4C_7400 0xAE /* Xeon Quad Core 7400 */
678 #define SMB_PRF_XEON_XC_7400 0xAF /* Xeon Multi Core 7400 */
679 #define SMB_PRF_PENTIUMIII_XEON 0xB0 /* Pentium III Xeon */
680 #define SMB_PRF_PENTIUMIII_SS 0xB1 /* Pentium III with SpeedStep */
681 #define SMB_PRF_P4 0xB2 /* Pentium 4 */
682 #define SMB_PRF_XEON 0xB3 /* Intel Xeon */
683 #define SMB_PRF_AS400 0xB4 /* AS400 */
684 #define SMB_PRF_XEON_MP 0xB5 /* Intel Xeon MP */
685 #define SMB_PRF_ATHLON_XP 0xB6 /* AMD Athlon XP */
686 #define SMB_PRF_ATHLON_MP 0xB7 /* AMD Athlon MP */
687 #define SMB_PRF_ITANIC2 0xB8 /* Itanium 2 */
688 #define SMB_PRF_PENTIUM_M 0xB9 /* Pentium M */
689 #define SMB_PRF_CELERON_D 0xBA /* Celeron D */
690 #define SMB_PRF_PENTIUM_D 0xBB /* Pentium D */
691 #define SMB_PRF_PENTIUM_EE 0xBC /* Pentium Extreme Edition */
692 #define SMB_PRF_CORE_SOLO 0xBD /* Intel Core Solo */
693 #define SMB_PRF_CORE2_DUO 0xBF /* Intel Core 2 Duo */
694 #define SMB_PRF_CORE2_SOLO 0xC0 /* Intel Core 2 Solo */
695 #define SMB_PRF_CORE2_EX 0xC1 /* Intel Core 2 Extreme */
696 #define SMB_PRF_CORE2_QUAD 0xC2 /* Intel Core 2 Quad */
697 #define SMB_PRF_CORE2_EX_M 0xC3 /* Intel Core 2 Extreme mobile */
698 #define SMB_PRF_CORE2_DUO_M 0xC4 /* Intel Core 2 Duo mobile */
699 #define SMB_PRF_CORE2_SOLO_M 0xC5 /* Intel Core 2 Solo mobile */
700 #define SMB_PRF_CORE_I7 0xC6 /* Intel Core i7 */
701 #define SMB_PRF_CELERON_2C 0xC7 /* Celeron Dual-Core */
702 #define SMB_PRF_IBM390 0xC8 /* IBM 390 */
703 #define SMB_PRF_G4 0xC9 /* G4 */
704 #define SMB_PRF_G5 0xCA /* G5 */
705 #define SMB_PRF_ESA390 0xCB /* ESA390 */
706 #define SMB_PRF_ZARCH 0xCC /* z/Architecture */
707 #define SMB_PRF_CORE_I5 0xCD /* Intel Core i5 */
708 #define SMB_PRF_CORE_I3 0xCE /* Intel Core i3 */
709 #define SMB_PRF_C7M 0xD2 /* VIA C7-M */
710 #define SMB_PRF_C7D 0xD3 /* VIA C7-D */
711 #define SMB_PRF_C7 0xD4 /* VIA C7 */
712 #define SMB_PRF_EDEN 0xD5 /* VIA Eden */
713 #define SMB_PRF_XEON_XC 0xD6 /* Intel Xeon Multi-Core */
714 #define SMB_PRF_XEON_2C_3XXX 0xD7 /* Intel Xeon Dual-Core 3xxx */
715 #define SMB_PRF_XEON_4C_3XXX 0xD8 /* Intel Xeon Quad-Core 3xxx */
716 #define SMB_PRF_VIA_NANO 0xD9 /* VIA Nano */
717 #define SMB_PRF_XEON_2C_5XXX 0xDA /* Intel Xeon Dual-Core 5xxx */
718 #define SMB_PRF_XEON_4C_5XXX 0xDB /* Intel Xeon Quad-Core 5xxx */
719 #define SMB_PRF_XEON_2C_7XXX 0xDD /* Intel Xeon Dual-Core 7xxx */
720 #define SMB_PRF_XEON_4C_7XXX 0xDE /* Intel Xeon Quad-Core 7xxx */
721 #define SMB_PRF_XEON_XC_7XXX 0xDF /* Intel Xeon Multi-Core 7xxx */
722 #define SMB_PRF_XEON_XC_3400 0xE0 /* Intel Xeon Multi-Core 3400 */
723 #define SMB_PRF_OPTERON_3000 0xE4 /* AMD Opteron 3000 */
724 #define SMB_PRF_SEMPRON_II 0xE5 /* AMD Sempron II */
725 #define SMB_PRF_OPTERON_4C_EM 0xE6 /* AMD Opteron Quad-Core embedded */
726 #define SMB_PRF_PHENOM_3C 0xE7 /* AMD Phenom Triple-Core */
727 #define SMB_PRF_TURIONU_2C_M 0xE8 /* AMD Turion Ultra Dual-Core mobile */
728 #define SMB_PRF_TURION_2C_M 0xE9 /* AMD Turion Dual-Core mobile */
729 #define SMB_PRF_ATHLON_2C 0xEA /* AMD Athlon Dual-Core */
730 #define SMB_PRF_SEMPRON_SI 0xEB /* AMD Sempron SI */
731 #define SMB_PRF_PHENOM_II 0xEC /* AMD Phenom II */
732 #define SMB_PRF_ATHLON_II 0xED /* AMD Athlon II */
733 #define SMB_PRF_OPTERON_6C 0xEE /* AMD Opteron Six-Core */
734 #define SMB_PRF_SEMPRON_M 0xEF /* AMD Sempron M */
735 #define SMB_PRF_I860 0xFA /* i860 */
736 #define SMB_PRF_I960 0xFB /* i960 */
737 #define SMB_PRF_ARMv7 0x100 /* ARMv7 */
738 #define SMB_PRF_ARMv8 0x101 /* ARMv8 */
739 #define SMB_PRF_SH3 0x104 /* SH-3 */
740 #define SMB_PRF_SH4 0x105 /* SH-4 */
741 #define SMB_PRF_ARM 0x118 /* ARM */
742 #define SMB_PRF_SARM 0x119 /* StrongARM */
743 #define SMB_PRF_6X86 0x12C /* 6x86 */
744 #define SMB_PRF_MEDIAGX 0x12D /* MediaGX */
745 #define SMB_PRF_MII 0x12E /* MII */
746 #define SMB_PRF_WINCHIP 0x140 /* WinChip */
747 #define SMB_PRF_DSP 0x15E /* DSP */
748 #define SMB_PRF_VIDEO 0x1F4 /* Video Processor */
749
750 /*
751 * SMBIOS Cache Information. See DSP0134 Section 7.8 for more information.
752 * If smba_size is zero, this indicates the specified cache is not present.
753 *
754 * SMBIOS 3.1 added extended cache sizes. Unfortunately, we had already baked in
755 * the uint32_t sizes, so we added extended uint64_t's that correspond to the
756 * new fields. To make life easier for consumers, we always make sure that the
757 * _maxsize2 and _size2 members are filled in with the old value if no other
758 * value is present.
759 */
760 typedef struct smbios_cache {
761 uint32_t smba_maxsize; /* maximum installed size in bytes */
762 uint32_t smba_size; /* installed size in bytes */
763 uint16_t smba_stype; /* supported SRAM types (SMB_CAT_*) */
764 uint16_t smba_ctype; /* current SRAM type (SMB_CAT_*) */
765 uint8_t smba_speed; /* speed in nanoseconds */
766 uint8_t smba_etype; /* error correction type (SMB_CAE_*) */
767 uint8_t smba_ltype; /* logical cache type (SMB_CAG_*) */
768 uint8_t smba_assoc; /* associativity (SMB_CAA_*) */
769 uint8_t smba_level; /* cache level */
770 uint8_t smba_mode; /* cache mode (SMB_CAM_*) */
771 uint8_t smba_location; /* cache location (SMB_CAL_*) */
772 uint8_t smba_flags; /* cache flags (SMB_CAF_*) */
773 uint64_t smba_maxsize2; /* maximum installed size in bytes */
774 uint64_t smba_size2; /* installed size in bytes */
775 } smbios_cache_t;
776
777 #define SMB_CAT_OTHER 0x0001 /* other */
778 #define SMB_CAT_UNKNOWN 0x0002 /* unknown */
779 #define SMB_CAT_NONBURST 0x0004 /* non-burst */
780 #define SMB_CAT_BURST 0x0008 /* burst */
781 #define SMB_CAT_PBURST 0x0010 /* pipeline burst */
782 #define SMB_CAT_SYNC 0x0020 /* synchronous */
783 #define SMB_CAT_ASYNC 0x0040 /* asynchronous */
784
785 #define SMB_CAE_OTHER 0x01 /* other */
786 #define SMB_CAE_UNKNOWN 0x02 /* unknown */
787 #define SMB_CAE_NONE 0x03 /* none */
788 #define SMB_CAE_PARITY 0x04 /* parity */
789 #define SMB_CAE_SBECC 0x05 /* single-bit ECC */
790 #define SMB_CAE_MBECC 0x06 /* multi-bit ECC */
791
792 #define SMB_CAG_OTHER 0x01 /* other */
793 #define SMB_CAG_UNKNOWN 0x02 /* unknown */
794 #define SMB_CAG_INSTR 0x03 /* instruction */
795 #define SMB_CAG_DATA 0x04 /* data */
796 #define SMB_CAG_UNIFIED 0x05 /* unified */
797
798 #define SMB_CAA_OTHER 0x01 /* other */
799 #define SMB_CAA_UNKNOWN 0x02 /* unknown */
800 #define SMB_CAA_DIRECT 0x03 /* direct mapped */
801 #define SMB_CAA_2WAY 0x04 /* 2-way set associative */
802 #define SMB_CAA_4WAY 0x05 /* 4-way set associative */
803 #define SMB_CAA_FULL 0x06 /* fully associative */
804 #define SMB_CAA_8WAY 0x07 /* 8-way set associative */
805 #define SMB_CAA_16WAY 0x08 /* 16-way set associative */
806 #define SMB_CAA_12WAY 0x09 /* 12-way set associative */
807 #define SMB_CAA_24WAY 0x0A /* 24-way set associative */
808 #define SMB_CAA_32WAY 0x0B /* 32-way set associative */
809 #define SMB_CAA_48WAY 0x0C /* 48-way set associative */
810 #define SMB_CAA_64WAY 0x0D /* 64-way set associative */
811 #define SMB_CAA_20WAY 0x0E /* 20-way set associative */
812
813 #define SMB_CAM_WT 0x00 /* write-through */
814 #define SMB_CAM_WB 0x01 /* write-back */
815 #define SMB_CAM_VARY 0x02 /* varies by address */
816 #define SMB_CAM_UNKNOWN 0x03 /* unknown */
817
818 #define SMB_CAL_INTERNAL 0x00 /* internal */
819 #define SMB_CAL_EXTERNAL 0x01 /* external */
820 #define SMB_CAL_RESERVED 0x02 /* reserved */
821 #define SMB_CAL_UNKNOWN 0x03 /* unknown */
822
823 #define SMB_CAF_ENABLED 0x01 /* enabled at boot time */
824 #define SMB_CAF_SOCKETED 0x02 /* cache is socketed */
825
826 /*
827 * SMBIOS Port Information. See DSP0134 Section 7.9 for more information.
828 * The internal reference designator string is also mapped to the location.
829 */
830 typedef struct smbios_port {
831 const char *smbo_iref; /* internal reference designator */
832 const char *smbo_eref; /* external reference designator */
833 uint8_t smbo_itype; /* internal connector type (SMB_POC_*) */
834 uint8_t smbo_etype; /* external connector type (SMB_POC_*) */
835 uint8_t smbo_ptype; /* port type (SMB_POT_*) */
836 uint8_t smbo_pad; /* padding */
837 } smbios_port_t;
838
839 #define SMB_POC_NONE 0x00 /* none */
840 #define SMB_POC_CENT 0x01 /* Centronics */
841 #define SMB_POC_MINICENT 0x02 /* Mini-Centronics */
842 #define SMB_POC_PROPRIETARY 0x03 /* proprietary */
843 #define SMB_POC_DB25M 0x04 /* DB-25 pin male */
844 #define SMB_POC_DB25F 0x05 /* DB-25 pin female */
845 #define SMB_POC_DB15M 0x06 /* DB-15 pin male */
846 #define SMB_POC_DB15F 0x07 /* DB-15 pin female */
847 #define SMB_POC_DB9M 0x08 /* DB-9 pin male */
848 #define SMB_POC_DB9F 0x09 /* DB-9 pin female */
849 #define SMB_POC_RJ11 0x0A /* RJ-11 */
850 #define SMB_POC_RJ45 0x0B /* RJ-45 */
851 #define SMB_POC_MINISCSI 0x0C /* 50-pin MiniSCSI */
852 #define SMB_POC_MINIDIN 0x0D /* Mini-DIN */
853 #define SMB_POC_MICRODIN 0x0E /* Micro-DIN */
854 #define SMB_POC_PS2 0x0F /* PS/2 */
855 #define SMB_POC_IR 0x10 /* Infrared */
856 #define SMB_POC_HPHIL 0x11 /* HP-HIL */
857 #define SMB_POC_USB 0x12 /* USB */
858 #define SMB_POC_SSA 0x13 /* SSA SCSI */
859 #define SMB_POC_DIN8M 0x14 /* Circular DIN-8 male */
860 #define SMB_POC_DIN8F 0x15 /* Circular DIN-8 female */
861 #define SMB_POC_OBIDE 0x16 /* on-board IDE */
862 #define SMB_POC_OBFLOPPY 0x17 /* on-board floppy */
863 #define SMB_POC_DI9 0x18 /* 9p dual inline (p10 cut) */
864 #define SMB_POC_DI25 0x19 /* 25p dual inline (p26 cut) */
865 #define SMB_POC_DI50 0x1A /* 50p dual inline */
866 #define SMB_POC_DI68 0x1B /* 68p dual inline */
867 #define SMB_POC_CDROM 0x1C /* on-board sound from CDROM */
868 #define SMB_POC_MINI14 0x1D /* Mini-Centronics Type 14 */
869 #define SMB_POC_MINI26 0x1E /* Mini-Centronics Type 26 */
870 #define SMB_POC_MINIJACK 0x1F /* Mini-jack (headphones) */
871 #define SMB_POC_BNC 0x20 /* BNC */
872 #define SMB_POC_1394 0x21 /* 1394 */
873 #define SMB_POC_SATA 0x22 /* SAS/SATA plug receptacle */
874 #define SMB_POC_PC98 0xA0 /* PC-98 */
875 #define SMB_POC_PC98HR 0xA1 /* PC-98Hireso */
876 #define SMB_POC_PCH98 0xA2 /* PC-H98 */
877 #define SMB_POC_PC98NOTE 0xA3 /* PC-98Note */
878 #define SMB_POC_PC98FULL 0xA4 /* PC-98Full */
879 #define SMB_POC_OTHER 0xFF /* other */
880
881 #define SMB_POT_NONE 0x00 /* none */
882 #define SMB_POT_PP_XTAT 0x01 /* Parallel Port XT/AT compat */
883 #define SMB_POT_PP_PS2 0x02 /* Parallel Port PS/2 */
884 #define SMB_POT_PP_ECP 0x03 /* Parallel Port ECP */
885 #define SMB_POT_PP_EPP 0x04 /* Parallel Port EPP */
886 #define SMB_POT_PP_ECPEPP 0x05 /* Parallel Port ECP/EPP */
887 #define SMB_POT_SP_XTAT 0x06 /* Serial Port XT/AT compat */
888 #define SMB_POT_SP_16450 0x07 /* Serial Port 16450 compat */
889 #define SMB_POT_SP_16550 0x08 /* Serial Port 16550 compat */
890 #define SMB_POT_SP_16550A 0x09 /* Serial Port 16550A compat */
891 #define SMB_POT_SCSI 0x0A /* SCSI port */
892 #define SMB_POT_MIDI 0x0B /* MIDI port */
893 #define SMB_POT_JOYSTICK 0x0C /* Joystick port */
894 #define SMB_POT_KEYBOARD 0x0D /* Keyboard port */
895 #define SMB_POT_MOUSE 0x0E /* Mouse port */
896 #define SMB_POT_SSA 0x0F /* SSA SCSI */
897 #define SMB_POT_USB 0x10 /* USB */
898 #define SMB_POT_FIREWIRE 0x11 /* FireWrite (IEEE P1394) */
899 #define SMB_POT_PCMII 0x12 /* PCMCIA Type II */
900 #define SMB_POT_PCMIIa 0x13 /* PCMCIA Type II (alternate) */
901 #define SMB_POT_PCMIII 0x14 /* PCMCIA Type III */
902 #define SMB_POT_CARDBUS 0x15 /* Cardbus */
903 #define SMB_POT_ACCESS 0x16 /* Access Bus Port */
904 #define SMB_POT_SCSI2 0x17 /* SCSI II */
905 #define SMB_POT_SCSIW 0x18 /* SCSI Wide */
906 #define SMB_POT_PC98 0x19 /* PC-98 */
907 #define SMB_POT_PC98HR 0x1A /* PC-98Hireso */
908 #define SMB_POT_PCH98 0x1B /* PC-H98 */
909 #define SMB_POT_VIDEO 0x1C /* Video port */
910 #define SMB_POT_AUDIO 0x1D /* Audio port */
911 #define SMB_POT_MODEM 0x1E /* Modem port */
912 #define SMB_POT_NETWORK 0x1F /* Network port */
913 #define SMB_POT_SATA 0x20 /* SATA */
914 #define SMB_POT_SAS 0x21 /* SAS */
915 #define SMB_POT_8251 0xA0 /* 8251 compatible */
916 #define SMB_POT_8251F 0xA1 /* 8251 FIFO compatible */
917 #define SMB_POT_OTHER 0xFF /* other */
918
919 /*
920 * SMBIOS Slot Information. See DSP0134 Section 7.10 for more information.
921 * See DSP0134 7.10.5 for how to interpret the value of smbl_id.
922 */
923 typedef struct smbios_slot {
924 const char *smbl_name; /* reference designation */
925 uint8_t smbl_type; /* slot type */
926 uint8_t smbl_width; /* slot data bus width */
927 uint8_t smbl_usage; /* current usage */
928 uint8_t smbl_length; /* slot length */
929 uint16_t smbl_id; /* slot ID */
930 uint8_t smbl_ch1; /* slot characteristics 1 */
931 uint8_t smbl_ch2; /* slot characteristics 2 */
932 uint16_t smbl_sg; /* segment group number */
933 uint8_t smbl_bus; /* bus number */
934 uint8_t smbl_df; /* device/function number */
935 } smbios_slot_t;
936
937 #define SMB_SLT_OTHER 0x01 /* other */
938 #define SMB_SLT_UNKNOWN 0x02 /* unknown */
939 #define SMB_SLT_ISA 0x03 /* ISA */
940 #define SMB_SLT_MCA 0x04 /* MCA */
941 #define SMB_SLT_EISA 0x05 /* EISA */
942 #define SMB_SLT_PCI 0x06 /* PCI */
943 #define SMB_SLT_PCMCIA 0x07 /* PCMCIA */
944 #define SMB_SLT_VLVESA 0x08 /* VL-VESA */
945 #define SMB_SLT_PROPRIETARY 0x09 /* proprietary */
946 #define SMB_SLT_PROC 0x0A /* processor card slot */
947 #define SMB_SLT_MEM 0x0B /* proprietary memory card slot */
948 #define SMB_SLT_IOR 0x0C /* I/O riser card slot */
949 #define SMB_SLT_NUBUS 0x0D /* NuBus */
950 #define SMB_SLT_PCI66 0x0E /* PCI (66MHz capable) */
951 #define SMB_SLT_AGP 0x0F /* AGP */
952 #define SMB_SLT_AGP2X 0x10 /* AGP 2X */
953 #define SMB_SLT_AGP4X 0x11 /* AGP 4X */
954 #define SMB_SLT_PCIX 0x12 /* PCI-X */
955 #define SMB_SLT_AGP8X 0x13 /* AGP 8X */
956 #define SMB_SLT_M2_1DP 0x14 /* M.2 Socket 1-DP (Mechanical Key A) */
957 #define SMB_SLT_M2_1SD 0x15 /* M.2 Socket 1-SD (Mechanical Key E) */
958 #define SMB_SLT_M2_2 0x16 /* M.2 Socket 2 (Mechanical Key B) */
959 #define SMB_SLT_M2_3 0x17 /* M.2 Socket 3 (Mechanical Key M) */
960 #define SMB_SLT_MXM_I 0x18 /* MXM Type I */
961 #define SMB_SLT_MXM_II 0x19 /* MXM Type II */
962 #define SMB_SLT_MXM_III 0x1A /* MXM Type III (standard connector) */
963 #define SMB_SLT_MXM_III_HE 0x1B /* MXM Type III (HE connector) */
964 #define SMB_SLT_MXM_V 0x1C /* MXM Type IV */
965 #define SMB_SLT_MXM3_A 0x1D /* MXM 3.0 Type A */
966 #define SMB_SLT_MXM3_B 0x1E /* MXM 3.0 Type B */
967 #define SMB_SLT_PCIEG2_SFF 0x1F /* PCI Express Gen 2 SFF-8639 */
968 #define SMB_SLT_PCIEG3_SFF 0x20 /* PCI Express Gen 3 SFF-8639 */
969 /*
970 * These lines must be on one line for the string generating code.
971 */
972 /* BEGIN CSTYLED */
973 #define SMB_SLT_PCIE_M52_WBSKO 0x21 /* PCI Express Mini 52-pin with bottom-side keep-outs */
974 #define SMB_SLT_PCIE_M52_WOBSKO 0x22 /* PCI Express Mini 52-pin without bottom-side keep-outs */
975 /* END CSTYLED */
976 #define SMB_SLT_PCIE_M76 0x23 /* PCI Express Mini 72-pin */
977 #define SMB_SLT_PC98_C20 0xA0 /* PC-98/C20 */
978 #define SMB_SLT_PC98_C24 0xA1 /* PC-98/C24 */
979 #define SMB_SLT_PC98_E 0xA2 /* PC-98/E */
980 #define SMB_SLT_PC98_LB 0xA3 /* PC-98/Local Bus */
981 #define SMB_SLT_PC98_C 0xA4 /* PC-98/Card */
982 #define SMB_SLT_PCIE 0xA5 /* PCI Express */
983 #define SMB_SLT_PCIE1 0xA6 /* PCI Express x1 */
984 #define SMB_SLT_PCIE2 0xA7 /* PCI Express x2 */
985 #define SMB_SLT_PCIE4 0xA8 /* PCI Express x4 */
986 #define SMB_SLT_PCIE8 0xA9 /* PCI Express x8 */
987 #define SMB_SLT_PCIE16 0xAA /* PCI Express x16 */
988 #define SMB_SLT_PCIE2G 0xAB /* PCI Exp. Gen 2 */
989 #define SMB_SLT_PCIE2G1 0xAC /* PCI Exp. Gen 2 x1 */
990 #define SMB_SLT_PCIE2G2 0xAD /* PCI Exp. Gen 2 x2 */
991 #define SMB_SLT_PCIE2G4 0xAE /* PCI Exp. Gen 2 x4 */
992 #define SMB_SLT_PCIE2G8 0xAF /* PCI Exp. Gen 2 x8 */
993 #define SMB_SLT_PCIE2G16 0xB0 /* PCI Exp. Gen 2 x16 */
994 #define SMB_SLT_PCIE3G 0xB1 /* PCI Exp. Gen 3 */
995 #define SMB_SLT_PCIE3G1 0xB2 /* PCI Exp. Gen 3 x1 */
996 #define SMB_SLT_PCIE3G2 0xB3 /* PCI Exp. Gen 3 x2 */
997 #define SMB_SLT_PCIE3G4 0xB4 /* PCI Exp. Gen 3 x4 */
998 #define SMB_SLT_PCIE3G8 0xB5 /* PCI Exp. Gen 3 x8 */
999 #define SMB_SLT_PCIE3G16 0xB6 /* PCI Exp. Gen 3 x16 */
1000
1001 #define SMB_SLW_OTHER 0x01 /* other */
1002 #define SMB_SLW_UNKNOWN 0x02 /* unknown */
1003 #define SMB_SLW_8 0x03 /* 8 bit */
1004 #define SMB_SLW_16 0x04 /* 16 bit */
1005 #define SMB_SLW_32 0x05 /* 32 bit */
1006 #define SMB_SLW_64 0x06 /* 64 bit */
1007 #define SMB_SLW_128 0x07 /* 128 bit */
1008 #define SMB_SLW_1X 0x08 /* 1x or x1 */
1009 #define SMB_SLW_2X 0x09 /* 2x or x2 */
1010 #define SMB_SLW_4X 0x0A /* 4x or x4 */
1011 #define SMB_SLW_8X 0x0B /* 8x or x8 */
1012 #define SMB_SLW_12X 0x0C /* 12x or x12 */
1013 #define SMB_SLW_16X 0x0D /* 16x or x16 */
1014 #define SMB_SLW_32X 0x0E /* 32x or x32 */
1015
1016 #define SMB_SLU_OTHER 0x01 /* other */
1017 #define SMB_SLU_UNKNOWN 0x02 /* unknown */
1018 #define SMB_SLU_AVAIL 0x03 /* available */
1019 #define SMB_SLU_INUSE 0x04 /* in use */
1020
1021 #define SMB_SLL_OTHER 0x01 /* other */
1022 #define SMB_SLL_UNKNOWN 0x02 /* unknown */
1023 #define SMB_SLL_SHORT 0x03 /* short length */
1024 #define SMB_SLL_LONG 0x04 /* long length */
1025
1026 #define SMB_SLCH1_UNKNOWN 0x01 /* characteristics unknown */
1027 #define SMB_SLCH1_5V 0x02 /* provides 5.0V */
1028 #define SMB_SLCH1_33V 0x04 /* provides 3.3V */
1029 #define SMB_SLCH1_SHARED 0x08 /* opening shared with other slot */
1030 #define SMB_SLCH1_PC16 0x10 /* slot supports PC Card-16 */
1031 #define SMB_SLCH1_PCCB 0x20 /* slot supports CardBus */
1032 #define SMB_SLCH1_PCZV 0x40 /* slot supports Zoom Video */
1033 #define SMB_SLCH1_PCMRR 0x80 /* slot supports Modem Ring Resume */
1034
1035 #define SMB_SLCH2_PME 0x01 /* slot supports PME# signal */
1036 #define SMB_SLCH2_HOTPLUG 0x02 /* slot supports hot-plug devices */
1037 #define SMB_SLCH2_SMBUS 0x04 /* slot supports SMBus signal */
1038
1039 /*
1040 * SMBIOS On-Board Device Information. See DSP0134 Section 7.11 for more
1041 * information. Any number of on-board device sections may be present, each
1042 * containing one or more records. The smbios_info_obdevs() function permits
1043 * the caller to retrieve one or more of the records from a given section.
1044 */
1045 typedef struct smbios_obdev {
1046 const char *smbd_name; /* description string for this device */
1047 uint8_t smbd_type; /* type code (SMB_OBT_*) */
1048 uint8_t smbd_enabled; /* boolean (device is enabled) */
1049 } smbios_obdev_t;
1050
1051 #define SMB_OBT_OTHER 0x01 /* other */
1052 #define SMB_OBT_UNKNOWN 0x02 /* unknown */
1053 #define SMB_OBT_VIDEO 0x03 /* video */
1054 #define SMB_OBT_SCSI 0x04 /* scsi */
1055 #define SMB_OBT_ETHERNET 0x05 /* ethernet */
1056 #define SMB_OBT_TOKEN 0x06 /* token ring */
1057 #define SMB_OBT_SOUND 0x07 /* sound */
1058 #define SMB_OBT_PATA 0x08 /* pata */
1059 #define SMB_OBT_SATA 0x09 /* sata */
1060 #define SMB_OBT_SAS 0x0A /* sas */
1061
1062 /*
1063 * SMBIOS BIOS Language Information. See DSP0134 Section 7.14 for more
1064 * information. The smbios_info_strtab() function can be applied using a
1065 * count of smbla_num to retrieve the other possible language settings.
1066 */
1067 typedef struct smbios_lang {
1068 const char *smbla_cur; /* current language setting */
1069 uint_t smbla_fmt; /* language name format (see below) */
1070 uint_t smbla_num; /* number of installed languages */
1071 } smbios_lang_t;
1072
1073 #define SMB_LFMT_LONG 0 /* <ISO639>|<ISO3166>|Encoding Method */
1074 #define SMB_LFMT_SHORT 1 /* <ISO930><ISO3166> */
1075
1076 /*
1077 * SMBIOS System Event Log Information. See DSP0134 Section 7.16 for more
1078 * information. Accessing the event log itself requires additional interfaces.
1079 */
1080 typedef struct smbios_evtype {
1081 uint8_t smbevt_ltype; /* log type */
1082 uint8_t smbevt_dtype; /* variable data format type */
1083 } smbios_evtype_t;
1084
1085 typedef struct smbios_evlog {
1086 size_t smbev_size; /* size in bytes of log area */
1087 size_t smbev_hdr; /* offset or index of header */
1088 size_t smbev_data; /* offset or index of data */
1089 uint8_t smbev_method; /* data access method (see below) */
1090 uint8_t smbev_flags; /* flags (see below) */
1091 uint8_t smbev_format; /* log header format (see below) */
1092 uint8_t smbev_pad; /* padding */
1093 uint32_t smbev_token; /* data update change token */
1094 union {
1095 struct {
1096 uint16_t evi_iaddr; /* index address */
1097 uint16_t evi_daddr; /* data address */
1098 } eva_io; /* i/o address for SMB_EVM_XxY */
1099 uint32_t eva_addr; /* address for SMB_EVM_MEM32 */
1100 uint16_t eva_gpnv; /* handle for SMB_EVM_GPNV */
1101 } smbev_addr;
1102 uint32_t smbev_typec; /* number of type descriptors */
1103 const smbios_evtype_t *smbev_typev; /* type descriptor array */
1104 } smbios_evlog_t;
1105
1106 #define SMB_EVM_1x1i_1x1d 0 /* I/O: 1 1b idx port, 1 1b data port */
1107 #define SMB_EVM_2x1i_1x1d 1 /* I/O: 2 1b idx port, 1 1b data port */
1108 #define SMB_EVM_1x2i_1x1d 2 /* I/O: 1 2b idx port, 1 1b data port */
1109 #define SMB_EVM_MEM32 3 /* Memory-Mapped 32-bit Physical Addr */
1110 #define SMB_EVM_GPNV 4 /* GP Non-Volatile API Access */
1111
1112 #define SMB_EVFL_VALID 0x1 /* log area valid */
1113 #define SMB_EVFL_FULL 0x2 /* log area full */
1114
1115 #define SMB_EVHF_NONE 0 /* no log headers used */
1116 #define SMB_EVHF_F1 1 /* DMTF log header type 1 */
1117
1118 /*
1119 * SMBIOS Physical Memory Array Information. See DSP0134 Section 7.17 for
1120 * more information. This describes a collection of physical memory devices.
1121 */
1122 typedef struct smbios_memarray {
1123 uint8_t smbma_location; /* physical device location */
1124 uint8_t smbma_use; /* physical device functional purpose */
1125 uint8_t smbma_ecc; /* error detect/correct mechanism */
1126 uint8_t smbma_pad0; /* padding */
1127 uint32_t smbma_pad1; /* padding */
1128 uint32_t smbma_ndevs; /* number of slots or sockets */
1129 id_t smbma_err; /* handle of error (if any) */
1130 uint64_t smbma_size; /* maximum capacity in bytes */
1131 } smbios_memarray_t;
1132
1133 #define SMB_MAL_OTHER 0x01 /* other */
1134 #define SMB_MAL_UNKNOWN 0x02 /* unknown */
1135 #define SMB_MAL_SYSMB 0x03 /* system board or motherboard */
1136 #define SMB_MAL_ISA 0x04 /* ISA add-on card */
1137 #define SMB_MAL_EISA 0x05 /* EISA add-on card */
1138 #define SMB_MAL_PCI 0x06 /* PCI add-on card */
1139 #define SMB_MAL_MCA 0x07 /* MCA add-on card */
1140 #define SMB_MAL_PCMCIA 0x08 /* PCMCIA add-on card */
1141 #define SMB_MAL_PROP 0x09 /* proprietary add-on card */
1142 #define SMB_MAL_NUBUS 0x0A /* NuBus */
1143 #define SMB_MAL_PC98C20 0xA0 /* PC-98/C20 add-on card */
1144 #define SMB_MAL_PC98C24 0xA1 /* PC-98/C24 add-on card */
1145 #define SMB_MAL_PC98E 0xA2 /* PC-98/E add-on card */
1146 #define SMB_MAL_PC98LB 0xA3 /* PC-98/Local bus add-on card */
1147
1148 #define SMB_MAU_OTHER 0x01 /* other */
1149 #define SMB_MAU_UNKNOWN 0x02 /* unknown */
1150 #define SMB_MAU_SYSTEM 0x03 /* system memory */
1151 #define SMB_MAU_VIDEO 0x04 /* video memory */
1152 #define SMB_MAU_FLASH 0x05 /* flash memory */
1153 #define SMB_MAU_NVRAM 0x06 /* non-volatile RAM */
1154 #define SMB_MAU_CACHE 0x07 /* cache memory */
1155
1156 #define SMB_MAE_OTHER 0x01 /* other */
1157 #define SMB_MAE_UNKNOWN 0x02 /* unknown */
1158 #define SMB_MAE_NONE 0x03 /* none */
1159 #define SMB_MAE_PARITY 0x04 /* parity */
1160 #define SMB_MAE_SECC 0x05 /* single-bit ECC */
1161 #define SMB_MAE_MECC 0x06 /* multi-bit ECC */
1162 #define SMB_MAE_CRC 0x07 /* CRC */
1163
1164 /*
1165 * SMBIOS Memory Device Information. See DSP0134 Section 7.18 for more
1166 * information. One or more of these structures are associated with each
1167 * smbios_memarray_t. A structure is present even for unpopulated sockets.
1168 * Unknown values are set to -1. A smbmd_size of 0 indicates unpopulated.
1169 * WARNING: Some BIOSes appear to export the *maximum* size of the device
1170 * that can appear in the corresponding socket as opposed to the current one.
1171 */
1172 typedef struct smbios_memdevice {
1173 id_t smbmd_array; /* handle of physical memory array */
1174 id_t smbmd_error; /* handle of memory error data */
1175 uint32_t smbmd_twidth; /* total width in bits including ecc */
1176 uint32_t smbmd_dwidth; /* data width in bits */
1177 uint64_t smbmd_size; /* size in bytes (see note above) */
1178 uint8_t smbmd_form; /* form factor */
1179 uint8_t smbmd_set; /* set (0x00=none, 0xFF=unknown) */
1180 uint8_t smbmd_type; /* memory type */
1181 uint8_t smbmd_pad; /* padding */
1182 uint32_t smbmd_flags; /* flags (see below) */
1183 uint32_t smbmd_speed; /* speed in MT/s */
1184 const char *smbmd_dloc; /* physical device locator string */
1185 const char *smbmd_bloc; /* physical bank locator string */
1186 uint8_t smbmd_rank; /* rank */
1187 uint16_t smbmd_clkspeed; /* configured clock speed */
1188 uint16_t smbmd_minvolt; /* minimum voltage */
1189 uint16_t smbmd_maxvolt; /* maximum voltage */
1190 uint16_t smbmd_confvolt; /* configured voltage */
1191 } smbios_memdevice_t;
1192
1193 #define SMB_MDFF_OTHER 0x01 /* other */
1194 #define SMB_MDFF_UNKNOWN 0x02 /* unknown */
1195 #define SMB_MDFF_SIMM 0x03 /* SIMM */
1196 #define SMB_MDFF_SIP 0x04 /* SIP */
1197 #define SMB_MDFF_CHIP 0x05 /* chip */
1198 #define SMB_MDFF_DIP 0x06 /* DIP */
1199 #define SMB_MDFF_ZIP 0x07 /* ZIP */
1200 #define SMB_MDFF_PROP 0x08 /* proprietary card */
1201 #define SMB_MDFF_DIMM 0x09 /* DIMM */
1202 #define SMB_MDFF_TSOP 0x0A /* TSOP */
1203 #define SMB_MDFF_CHIPROW 0x0B /* row of chips */
1204 #define SMB_MDFF_RIMM 0x0C /* RIMM */
1205 #define SMB_MDFF_SODIMM 0x0D /* SODIMM */
1206 #define SMB_MDFF_SRIMM 0x0E /* SRIMM */
1207 #define SMB_MDFF_FBDIMM 0x0F /* FBDIMM */
1208
1209 #define SMB_MDT_OTHER 0x01 /* other */
1210 #define SMB_MDT_UNKNOWN 0x02 /* unknown */
1211 #define SMB_MDT_DRAM 0x03 /* DRAM */
1212 #define SMB_MDT_EDRAM 0x04 /* EDRAM */
1213 #define SMB_MDT_VRAM 0x05 /* VRAM */
1214 #define SMB_MDT_SRAM 0x06 /* SRAM */
1215 #define SMB_MDT_RAM 0x07 /* RAM */
1216 #define SMB_MDT_ROM 0x08 /* ROM */
1217 #define SMB_MDT_FLASH 0x09 /* FLASH */
1218 #define SMB_MDT_EEPROM 0x0A /* EEPROM */
1219 #define SMB_MDT_FEPROM 0x0B /* FEPROM */
1220 #define SMB_MDT_EPROM 0x0C /* EPROM */
1221 #define SMB_MDT_CDRAM 0x0D /* CDRAM */
1222 #define SMB_MDT_3DRAM 0x0E /* 3DRAM */
1223 #define SMB_MDT_SDRAM 0x0F /* SDRAM */
1224 #define SMB_MDT_SGRAM 0x10 /* SGRAM */
1225 #define SMB_MDT_RDRAM 0x11 /* RDRAM */
1226 #define SMB_MDT_DDR 0x12 /* DDR */
1227 #define SMB_MDT_DDR2 0x13 /* DDR2 */
1228 #define SMB_MDT_DDR2FBDIMM 0x14 /* DDR2 FBDIMM */
1229 #define SMB_MDT_DDR3 0x18 /* DDR3 */
1230 #define SMB_MDT_FBD2 0x19 /* FBD2 */
1231 #define SMB_MDT_DDR4 0x1A /* DDR4 */
1232 #define SMB_MDT_LPDDR 0x1B /* LPDDR */
1233 #define SMB_MDT_LPDDR2 0x1C /* LPDDR2 */
1234 #define SMB_MDT_LPDDR3 0x1D /* LPDDR3 */
1235 #define SMB_MDT_LPDDR4 0x1E /* LPDDR4 */
1236
1237 #define SMB_MDF_OTHER 0x0002 /* other */
1238 #define SMB_MDF_UNKNOWN 0x0004 /* unknown */
1239 #define SMB_MDF_FASTPG 0x0008 /* fast-paged */
1240 #define SMB_MDF_STATIC 0x0010 /* static column */
1241 #define SMB_MDF_PSTATIC 0x0020 /* pseudo-static */
1242 #define SMB_MDF_RAMBUS 0x0040 /* RAMBUS */
1243 #define SMB_MDF_SYNC 0x0080 /* synchronous */
1244 #define SMB_MDF_CMOS 0x0100 /* CMOS */
1245 #define SMB_MDF_EDO 0x0200 /* EDO */
1246 #define SMB_MDF_WDRAM 0x0400 /* Window DRAM */
1247 #define SMB_MDF_CDRAM 0x0800 /* Cache DRAM */
1248 #define SMB_MDF_NV 0x1000 /* non-volatile */
1249 #define SMB_MDF_REG 0x2000 /* Registered (Buffered) */
1250 #define SMB_MDF_UNREG 0x4000 /* Unregistered (Unbuffered) */
1251 #define SMB_MDF_LRDIMM 0x8000 /* LRDIMM */
1252
1253 #define SMB_MDR_SINGLE 0x01 /* single */
1254 #define SMB_MDR_DUAL 0x02 /* dual */
1255 #define SMB_MDR_QUAD 0x04 /* quad */
1256 #define SMB_MDR_OCTAL 0x08 /* octal */
1257
1258 /*
1259 * SMBIOS Memory Array Mapped Address. See DSP0134 Section 7.20 for more
1260 * information. We convert start/end addresses into addr/size for convenience.
1261 */
1262 typedef struct smbios_memarrmap {
1263 id_t smbmam_array; /* physical memory array handle */
1264 uint32_t smbmam_width; /* number of devices that form a row */
1265 uint64_t smbmam_addr; /* physical address of mapping */
1266 uint64_t smbmam_size; /* size in bytes of address range */
1267 } smbios_memarrmap_t;
1268
1269 /*
1270 * SMBIOS Memory Device Mapped Address. See DSP0134 Section 7.21 for more
1271 * information. We convert start/end addresses into addr/size for convenience.
1272 */
1273 typedef struct smbios_memdevmap {
1274 id_t smbmdm_device; /* memory device handle */
1275 id_t smbmdm_arrmap; /* memory array mapped address handle */
1276 uint64_t smbmdm_addr; /* physical address of mapping */
1277 uint64_t smbmdm_size; /* size in bytes of address range */
1278 uint8_t smbmdm_rpos; /* partition row position */
1279 uint8_t smbmdm_ipos; /* interleave position */
1280 uint8_t smbmdm_idepth; /* interleave data depth */
1281 } smbios_memdevmap_t;
1282
1283 /*
1284 * SMBIOS Hardware Security Settings. See DSP0134 Section 7.25 for more
1285 * information. Only one such record will be present in the SMBIOS.
1286 */
1287 typedef struct smbios_hwsec {
1288 uint8_t smbh_pwr_ps; /* power-on password status */
1289 uint8_t smbh_kbd_ps; /* keyboard password status */
1290 uint8_t smbh_adm_ps; /* administrator password status */
1291 uint8_t smbh_pan_ps; /* front panel reset status */
1292 } smbios_hwsec_t;
1293
1294 #define SMB_HWSEC_PS_DISABLED 0x00 /* password disabled */
1295 #define SMB_HWSEC_PS_ENABLED 0x01 /* password enabled */
1296 #define SMB_HWSEC_PS_NOTIMPL 0x02 /* password not implemented */
1297 #define SMB_HWSEC_PS_UNKNOWN 0x03 /* password status unknown */
1298
1299 /*
1300 * SMBIOS System Boot Information. See DSP0134 Section 7.33 for more
1301 * information. The contents of the data varies by type and is undocumented
1302 * from the perspective of DSP0134 -- it seems to be left as vendor-specific.
1303 * The (D) annotation next to SMB_BOOT_* below indicates possible data payload.
1304 */
1305 typedef struct smbios_boot {
1306 uint8_t smbt_status; /* boot status code (see below) */
1307 const void *smbt_data; /* data buffer specific to status */
1308 size_t smbt_size; /* size of smbt_data buffer in bytes */
1309 } smbios_boot_t;
1310
1311 #define SMB_BOOT_NORMAL 0 /* no errors detected */
1312 #define SMB_BOOT_NOMEDIA 1 /* no bootable media */
1313 #define SMB_BOOT_OSFAIL 2 /* normal o/s failed to load */
1314 #define SMB_BOOT_FWHWFAIL 3 /* firmware-detected hardware failure */
1315 #define SMB_BOOT_OSHWFAIL 4 /* o/s-detected hardware failure */
1316 #define SMB_BOOT_USERREQ 5 /* user-requested boot (keystroke) */
1317 #define SMB_BOOT_SECURITY 6 /* system security violation */
1318 #define SMB_BOOT_PREVREQ 7 /* previously requested image (D) */
1319 #define SMB_BOOT_WATCHDOG 8 /* watchdog initiated reboot */
1320 #define SMB_BOOT_RESV_LO 9 /* low end of reserved range */
1321 #define SMB_BOOT_RESV_HI 127 /* high end of reserved range */
1322 #define SMB_BOOT_OEM_LO 128 /* low end of OEM-specific range */
1323 #define SMB_BOOT_OEM_HI 191 /* high end of OEM-specific range */
1324 #define SMB_BOOT_PROD_LO 192 /* low end of product-specific range */
1325 #define SMB_BOOT_PROD_HI 255 /* high end of product-specific range */
1326
1327 /*
1328 * SMBIOS IPMI Device Information. See DSP0134 Section 7.39 and also
1329 * Appendix C1 of the IPMI specification for more information on this record.
1330 */
1331 typedef struct smbios_ipmi {
1332 uint_t smbip_type; /* BMC interface type */
1333 smbios_version_t smbip_vers; /* BMC's IPMI specification version */
1334 uint32_t smbip_i2c; /* BMC I2C bus slave address */
1335 uint32_t smbip_bus; /* bus ID of NV storage device, or -1 */
1336 uint64_t smbip_addr; /* BMC base address */
1337 uint32_t smbip_flags; /* flags (see below) */
1338 uint16_t smbip_intr; /* interrupt number (or zero if none) */
1339 uint16_t smbip_regspacing; /* i/o space register spacing (bytes) */
1340 } smbios_ipmi_t;
1341
1342 #define SMB_IPMI_T_UNKNOWN 0x00 /* unknown */
1343 #define SMB_IPMI_T_KCS 0x01 /* KCS: Keyboard Controller Style */
1344 #define SMB_IPMI_T_SMIC 0x02 /* SMIC: Server Mgmt Interface Chip */
1345 #define SMB_IPMI_T_BT 0x03 /* BT: Block Transfer */
1346 #define SMB_IPMI_T_SSIF 0x04 /* SSIF: SMBus System Interface */
1347
1348 #define SMB_IPMI_F_IOADDR 0x01 /* base address is in i/o space */
1349 #define SMB_IPMI_F_INTRSPEC 0x02 /* intr information is specified */
1350 #define SMB_IPMI_F_INTRHIGH 0x04 /* intr active high (else low) */
1351 #define SMB_IPMI_F_INTREDGE 0x08 /* intr is edge triggered (else lvl) */
1352
1353 /*
1354 * SMBIOS Onboard Devices Extended Information. See DSP0134 Section 7.42
1355 * for more information.
1356 */
1357 typedef struct smbios_obdev_ext {
1358 const char *smboe_name; /* reference designation */
1359 uint8_t smboe_dtype; /* device type */
1360 uint8_t smboe_dti; /* device type instance */
1361 uint16_t smboe_sg; /* segment group number */
1362 uint8_t smboe_bus; /* bus number */
1363 uint8_t smboe_df; /* device/function number */
1364 } smbios_obdev_ext_t;
1365
1366
1367 /*
1368 * SMBIOS OEM-specific (Type 132) Processor Extended Information.
1369 */
1370 typedef struct smbios_processor_ext {
1371 uint16_t smbpe_processor; /* extending processor handle */
1372 uint8_t smbpe_fru; /* FRU indicaor */
1373 uint8_t smbpe_n; /* number of APIC IDs */
1374 uint16_t *smbpe_apicid; /* strand Inital APIC IDs */
1375 } smbios_processor_ext_t;
1376
1377 /*
1378 * SMBIOS OEM-specific (Type 136) Port Extended Information.
1379 */
1380 typedef struct smbios_port_ext {
1381 uint16_t smbporte_chassis; /* chassis handle */
1382 uint16_t smbporte_port; /* port connector handle */
1383 uint8_t smbporte_dtype; /* device type */
1384 uint16_t smbporte_devhdl; /* device handle */
1385 uint8_t smbporte_phy; /* PHY number */
1386 } smbios_port_ext_t;
1387
1388 /*
1389 * SMBIOS OEM-specific (Type 138) PCI-Express RC/RP Information.
1390 */
1391 typedef struct smbios_pciexrc {
1392 uint16_t smbpcie_bb; /* base board handle */
1393 uint16_t smbpcie_bdf; /* Bus/Dev/Funct (PCI) */
1394 } smbios_pciexrc_t;
1395
1396 /*
1397 * SMBIOS OEM-specific (Type 144) Memory Array Extended Information.
1398 */
1399 typedef struct smbios_memarray_ext {
1400 uint16_t smbmae_ma; /* memory array handle */
1401 uint16_t smbmae_comp; /* component parent handle */
1402 uint16_t smbmae_bdf; /* Bus/Dev/Funct (PCI) */
1403 } smbios_memarray_ext_t;
1404
1405 /*
1406 * SMBIOS OEM-specific (Type 145) Memory Device Extended Information.
1407 */
1408 typedef struct smbios_memdevice_ext {
1409 uint16_t smbmdeve_md; /* memory device handle */
1410 uint8_t smbmdeve_drch; /* DRAM channel */
1411 uint8_t smbmdeve_ncs; /* number of chip selects */
1412 uint8_t *smbmdeve_cs; /* array of chip select numbers */
1413 } smbios_memdevice_ext_t;
1414
1415 /*
1416 * SMBIOS Interfaces. An SMBIOS image can be opened by either providing a file
1417 * pathname, device pathname, file descriptor, or raw memory buffer. Once an
1418 * image is opened the functions below can be used to iterate over the various
1419 * structures and convert the underlying data representation into the simpler
1420 * data structures described earlier in this header file. The SMB_VERSION
1421 * constant specified when opening an image indicates the version of the ABI
1422 * the caller expects and the DMTF SMBIOS version the client can understand.
1423 * The library will then map older or newer data structures to that as needed.
1424 */
1425
1426 #define SMB_VERSION_23 0x0203 /* SMBIOS encoding for DMTF spec 2.3 */
1427 #define SMB_VERSION_24 0x0204 /* SMBIOS encoding for DMTF spec 2.4 */
1428 #define SMB_VERSION_25 0x0205 /* SMBIOS encoding for DMTF spec 2.5 */
1429 #define SMB_VERSION_26 0x0206 /* SMBIOS encoding for DMTF spec 2.6 */
1430 #define SMB_VERSION_27 0x0207 /* SMBIOS encoding for DMTF spec 2.7 */
1431 #define SMB_VERSION_28 0x0208 /* SMBIOS encoding for DMTF spec 2.8 */
1432 #define SMB_VERSION_30 0x0300 /* SMBIOS encoding for DMTF spec 3.0 */
1433 #define SMB_VERSION_31 0x0301 /* SMBIOS encoding for DMTF spec 3.1 */
1434 #define SMB_VERSION SMB_VERSION_31 /* SMBIOS latest version definitions */
1435
1436 #define SMB_O_NOCKSUM 0x1 /* do not verify header checksums */
1437 #define SMB_O_NOVERS 0x2 /* do not verify header versions */
1438 #define SMB_O_ZIDS 0x4 /* strip out identification numbers */
1439 #define SMB_O_MASK 0x7 /* mask of valid smbios_*open flags */
1440
1441 #define SMB_ID_NOTSUP 0xFFFE /* structure is not supported by BIOS */
1442 #define SMB_ID_NONE 0xFFFF /* structure is a null reference */
1443
1444 #define SMB_ERR (-1) /* id_t value indicating error */
1445
1446 typedef struct smbios_hdl smbios_hdl_t;
1447
1448 typedef struct smbios_struct {
1449 id_t smbstr_id; /* structure ID handle */
1450 uint_t smbstr_type; /* structure type */
1451 const void *smbstr_data; /* structure data */
1452 size_t smbstr_size; /* structure size */
1453 } smbios_struct_t;
1454
1455 typedef int smbios_struct_f(smbios_hdl_t *,
1456 const smbios_struct_t *, void *);
1457
1458 extern smbios_hdl_t *smbios_open(const char *, int, int, int *);
1459 extern smbios_hdl_t *smbios_fdopen(int, int, int, int *);
1460 extern smbios_hdl_t *smbios_bufopen(const smbios_entry_t *,
1461 const void *, size_t, int, int, int *);
1462
1463 extern const void *smbios_buf(smbios_hdl_t *);
1464 extern size_t smbios_buflen(smbios_hdl_t *);
1465
1466 extern void smbios_checksum(smbios_hdl_t *, smbios_entry_t *);
1467 extern int smbios_write(smbios_hdl_t *, int);
1468 extern void smbios_close(smbios_hdl_t *);
1469
1470 extern boolean_t smbios_truncated(smbios_hdl_t *);
1471 extern int smbios_errno(smbios_hdl_t *);
1472 extern const char *smbios_errmsg(int);
1473
1474 extern int smbios_lookup_id(smbios_hdl_t *, id_t, smbios_struct_t *);
1475 extern int smbios_lookup_type(smbios_hdl_t *, uint_t, smbios_struct_t *);
1476 extern int smbios_iter(smbios_hdl_t *, smbios_struct_f *, void *);
1477
1478 extern smbios_entry_point_t smbios_info_smbios(smbios_hdl_t *,
1479 smbios_entry_t *);
1480 extern void smbios_info_smbios_version(smbios_hdl_t *, smbios_version_t *);
1481 extern int smbios_info_common(smbios_hdl_t *, id_t, smbios_info_t *);
1482 extern int smbios_info_contains(smbios_hdl_t *, id_t, uint_t, id_t *);
1483 extern id_t smbios_info_bios(smbios_hdl_t *, smbios_bios_t *);
1484 extern id_t smbios_info_system(smbios_hdl_t *, smbios_system_t *);
1485 extern int smbios_info_bboard(smbios_hdl_t *, id_t, smbios_bboard_t *);
1486 extern int smbios_info_chassis(smbios_hdl_t *, id_t, smbios_chassis_t *);
1487 extern int smbios_info_processor(smbios_hdl_t *, id_t, smbios_processor_t *);
1488 extern int smbios_info_extprocessor(smbios_hdl_t *, id_t,
1489 smbios_processor_ext_t *);
1490 extern int smbios_info_cache(smbios_hdl_t *, id_t, smbios_cache_t *);
1491 extern int smbios_info_port(smbios_hdl_t *, id_t, smbios_port_t *);
1492 extern int smbios_info_extport(smbios_hdl_t *, id_t, smbios_port_ext_t *);
1493 extern int smbios_info_slot(smbios_hdl_t *, id_t, smbios_slot_t *);
1494 extern int smbios_info_obdevs(smbios_hdl_t *, id_t, int, smbios_obdev_t *);
1495 extern int smbios_info_obdevs_ext(smbios_hdl_t *, id_t, smbios_obdev_ext_t *);
1496 extern int smbios_info_strtab(smbios_hdl_t *, id_t, int, const char *[]);
1497 extern id_t smbios_info_lang(smbios_hdl_t *, smbios_lang_t *);
1498 extern id_t smbios_info_eventlog(smbios_hdl_t *, smbios_evlog_t *);
1499 extern int smbios_info_memarray(smbios_hdl_t *, id_t, smbios_memarray_t *);
1500 extern int smbios_info_extmemarray(smbios_hdl_t *, id_t,
1501 smbios_memarray_ext_t *);
1502 extern int smbios_info_memarrmap(smbios_hdl_t *, id_t, smbios_memarrmap_t *);
1503 extern int smbios_info_memdevice(smbios_hdl_t *, id_t, smbios_memdevice_t *);
1504 extern int smbios_info_extmemdevice(smbios_hdl_t *, id_t,
1505 smbios_memdevice_ext_t *);
1506 extern int smbios_info_memdevmap(smbios_hdl_t *, id_t, smbios_memdevmap_t *);
1507 extern id_t smbios_info_hwsec(smbios_hdl_t *, smbios_hwsec_t *);
1508 extern id_t smbios_info_boot(smbios_hdl_t *, smbios_boot_t *);
1509 extern id_t smbios_info_ipmi(smbios_hdl_t *, smbios_ipmi_t *);
1510 extern int smbios_info_pciexrc(smbios_hdl_t *, id_t, smbios_pciexrc_t *);
1511
1512 extern const char *smbios_psn(smbios_hdl_t *);
1513 extern const char *smbios_csn(smbios_hdl_t *);
1514
1515 #ifndef _KERNEL
1516 /*
1517 * The smbios_*_desc() and smbios_*_name() interfaces can be used for utilities
1518 * such as smbios(8) that wish to decode SMBIOS fields for humans. The _desc
1519 * functions return the comment string next to the #defines listed above, and
1520 * the _name functions return the appropriate #define identifier itself.
1521 */
1522 extern const char *smbios_bboard_flag_desc(uint_t);
1523 extern const char *smbios_bboard_flag_name(uint_t);
1524 extern const char *smbios_bboard_type_desc(uint_t);
1525
1526 extern const char *smbios_bios_flag_desc(uint64_t);
1527 extern const char *smbios_bios_flag_name(uint64_t);
1528
1529 extern const char *smbios_bios_xb1_desc(uint_t);
1530 extern const char *smbios_bios_xb1_name(uint_t);
1531 extern const char *smbios_bios_xb2_desc(uint_t);
1532 extern const char *smbios_bios_xb2_name(uint_t);
1533
1534 extern const char *smbios_boot_desc(uint_t);
1535
1536 extern const char *smbios_cache_assoc_desc(uint_t);
1537 extern const char *smbios_cache_ctype_desc(uint_t);
1538 extern const char *smbios_cache_ctype_name(uint_t);
1539 extern const char *smbios_cache_ecc_desc(uint_t);
1540 extern const char *smbios_cache_flag_desc(uint_t);
1541 extern const char *smbios_cache_flag_name(uint_t);
1542 extern const char *smbios_cache_loc_desc(uint_t);
1543 extern const char *smbios_cache_logical_desc(uint_t);
1544 extern const char *smbios_cache_mode_desc(uint_t);
1545
1546 extern const char *smbios_chassis_state_desc(uint_t);
1547 extern const char *smbios_chassis_type_desc(uint_t);
1548
1549 extern const char *smbios_evlog_flag_desc(uint_t);
1550 extern const char *smbios_evlog_flag_name(uint_t);
1551 extern const char *smbios_evlog_format_desc(uint_t);
1552 extern const char *smbios_evlog_method_desc(uint_t);
1553
1554 extern const char *smbios_ipmi_flag_name(uint_t);
1555 extern const char *smbios_ipmi_flag_desc(uint_t);
1556 extern const char *smbios_ipmi_type_desc(uint_t);
1557
1558 extern const char *smbios_hwsec_desc(uint_t);
1559
1560 extern const char *smbios_memarray_loc_desc(uint_t);
1561 extern const char *smbios_memarray_use_desc(uint_t);
1562 extern const char *smbios_memarray_ecc_desc(uint_t);
1563
1564 extern const char *smbios_memdevice_form_desc(uint_t);
1565 extern const char *smbios_memdevice_type_desc(uint_t);
1566 extern const char *smbios_memdevice_flag_name(uint_t);
1567 extern const char *smbios_memdevice_flag_desc(uint_t);
1568 extern const char *smbios_memdevice_rank_desc(uint_t);
1569
1570 extern const char *smbios_onboard_type_desc(uint_t);
1571
1572 extern const char *smbios_port_conn_desc(uint_t);
1573 extern const char *smbios_port_type_desc(uint_t);
1574
1575 extern const char *smbios_processor_family_desc(uint_t);
1576 extern const char *smbios_processor_status_desc(uint_t);
1577 extern const char *smbios_processor_type_desc(uint_t);
1578 extern const char *smbios_processor_upgrade_desc(uint_t);
1579 extern const char *smbios_processor_core_flag_name(uint_t);
1580 extern const char *smbios_processor_core_flag_desc(uint_t);
1581
1582 extern const char *smbios_slot_type_desc(uint_t);
1583 extern const char *smbios_slot_width_desc(uint_t);
1584 extern const char *smbios_slot_usage_desc(uint_t);
1585 extern const char *smbios_slot_length_desc(uint_t);
1586 extern const char *smbios_slot_ch1_desc(uint_t);
1587 extern const char *smbios_slot_ch1_name(uint_t);
1588 extern const char *smbios_slot_ch2_desc(uint_t);
1589 extern const char *smbios_slot_ch2_name(uint_t);
1590
1591 extern const char *smbios_type_desc(uint_t);
1592 extern const char *smbios_type_name(uint_t);
1593
1594 extern const char *smbios_system_wakeup_desc(uint_t);
1595 #endif /* !_KERNEL */
1596
1597 #ifdef _KERNEL
1598 /*
1599 * For SMBIOS clients within the kernel itself, ksmbios is used to refer to
1600 * the kernel's current snapshot of the SMBIOS, if one exists, and the
1601 * ksmbios_flags tunable is the set of flags for use with smbios_open().
1602 */
1603 extern smbios_hdl_t *ksmbios;
1604 extern int ksmbios_flags;
1605 #endif /* _KERNEL */
1606
1607 #ifdef __cplusplus
1608 }
1609 #endif
1610
1611 #endif /* _SYS_SMBIOS_H */
Unleashed OS