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Merge commit 'a71e11eee4676204c7609c4c9703cc98fbf4669d' into merges
[unleashed.git] / usr / src / uts / common / io / ib / adapters / tavor / tavor_ioctl.c
blobbc90fc3a387c6565696024554194c608a70396be
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 /*
28 * tavor_ioctl.c
29 * Tavor IOCTL Routines
30 *
31 * Implements all ioctl access into the driver. This includes all routines
32 * necessary for updating firmware, accessing the tavor flash device, and
33 * providing interfaces for VTS.
34 */
35
36 #include <sys/types.h>
37 #include <sys/conf.h>
38 #include <sys/ddi.h>
39 #include <sys/sunddi.h>
40 #include <sys/modctl.h>
41 #include <sys/file.h>
42
43 #include <sys/ib/adapters/tavor/tavor.h>
44
45 /* Tavor HCA state pointer (extern) */
46 extern void *tavor_statep;
47
48 /*
49 * The ioctl declarations (for firmware flash burning, register read/write
50 * (DEBUG-only), and VTS interfaces)
51 */
52 static int tavor_ioctl_flash_read(tavor_state_t *state, dev_t dev,
53 intptr_t arg, int mode);
54 static int tavor_ioctl_flash_write(tavor_state_t *state, dev_t dev,
55 intptr_t arg, int mode);
56 static int tavor_ioctl_flash_erase(tavor_state_t *state, dev_t dev,
57 intptr_t arg, int mode);
58 static int tavor_ioctl_flash_init(tavor_state_t *state, dev_t dev,
59 intptr_t arg, int mode);
60 static int tavor_ioctl_flash_fini(tavor_state_t *state, dev_t dev);
61 static void tavor_ioctl_flash_cleanup(tavor_state_t *state);
62 static void tavor_ioctl_flash_cleanup_nolock(tavor_state_t *state);
63 #ifdef DEBUG
64 static int tavor_ioctl_reg_write(tavor_state_t *state, intptr_t arg,
65 int mode);
66 static int tavor_ioctl_reg_read(tavor_state_t *state, intptr_t arg,
67 int mode);
68 #endif /* DEBUG */
69 static int tavor_ioctl_info(tavor_state_t *state, dev_t dev,
70 intptr_t arg, int mode);
71 static int tavor_ioctl_ports(tavor_state_t *state, intptr_t arg,
72 int mode);
73 static int tavor_ioctl_loopback(tavor_state_t *state, intptr_t arg,
74 int mode);
75 static int tavor_ioctl_ddr_read(tavor_state_t *state, intptr_t arg,
76 int mode);
77
78 /* Tavor Flash Functions */
79 static void tavor_flash_read_sector(tavor_state_t *state, uint32_t sector_num);
80 static void tavor_flash_read_quadlet(tavor_state_t *state, uint32_t *data,
81 uint32_t addr);
82 static int tavor_flash_write_sector(tavor_state_t *state, uint32_t sector_num);
83 static int tavor_flash_write_byte(tavor_state_t *state, uint32_t addr,
84 uchar_t data);
85 static int tavor_flash_erase_sector(tavor_state_t *state, uint32_t sector_num);
86 static int tavor_flash_erase_chip(tavor_state_t *state);
87 static void tavor_flash_bank(tavor_state_t *state, uint32_t addr);
88 static uint32_t tavor_flash_read(tavor_state_t *state, uint32_t addr);
89 static void tavor_flash_write(tavor_state_t *state, uint32_t addr,
90 uchar_t data);
91 static void tavor_flash_init(tavor_state_t *state);
92 static void tavor_flash_cfi_init(tavor_state_t *state, uint32_t *cfi_info,
93 int *intel_xcmd);
94 static void tavor_flash_fini(tavor_state_t *state);
95 static void tavor_flash_reset(tavor_state_t *state);
96 static uint32_t tavor_flash_read_cfg(ddi_acc_handle_t pci_config_hdl,
97 uint32_t addr);
98 static void tavor_flash_write_cfg(ddi_acc_handle_t pci_config_hdl,
99 uint32_t addr, uint32_t data);
100 static void tavor_flash_cfi_byte(uint8_t *ch, uint32_t dword, int i);
101 static void tavor_flash_cfi_dword(uint32_t *dword, uint8_t *ch, int i);
102
103 /* Tavor loopback test functions */
104 static void tavor_loopback_free_qps(tavor_loopback_state_t *lstate);
105 static void tavor_loopback_free_state(tavor_loopback_state_t *lstate);
106 static int tavor_loopback_init(tavor_state_t *state,
107 tavor_loopback_state_t *lstate);
108 static void tavor_loopback_init_qp_info(tavor_loopback_state_t *lstate,
109 tavor_loopback_comm_t *comm);
110 static int tavor_loopback_alloc_mem(tavor_loopback_state_t *lstate,
111 tavor_loopback_comm_t *comm, int sz);
112 static int tavor_loopback_alloc_qps(tavor_loopback_state_t *lstate,
113 tavor_loopback_comm_t *comm);
114 static int tavor_loopback_modify_qp(tavor_loopback_state_t *lstate,
115 tavor_loopback_comm_t *comm, uint_t qp_num);
116 static int tavor_loopback_copyout(tavor_loopback_ioctl_t *lb,
117 intptr_t arg, int mode);
118 static int tavor_loopback_post_send(tavor_loopback_state_t *lstate,
119 tavor_loopback_comm_t *tx, tavor_loopback_comm_t *rx);
120 static int tavor_loopback_poll_cq(tavor_loopback_state_t *lstate,
121 tavor_loopback_comm_t *comm);
122
123 /* Patchable timeout values for flash operations */
124 int tavor_hw_flash_timeout_gpio_sema = TAVOR_HW_FLASH_TIMEOUT_GPIO_SEMA;
125 int tavor_hw_flash_timeout_config = TAVOR_HW_FLASH_TIMEOUT_CONFIG;
126 int tavor_hw_flash_timeout_write = TAVOR_HW_FLASH_TIMEOUT_WRITE;
127 int tavor_hw_flash_timeout_erase = TAVOR_HW_FLASH_TIMEOUT_ERASE;
128
129 /*
130 * tavor_ioctl()
131 */
132 /* ARGSUSED */
133 int
134 tavor_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
135 int *rvalp)
136 {
137 tavor_state_t *state;
138 minor_t instance;
139 int status;
140
141 if (drv_priv(credp) != 0) {
142 return (EPERM);
143 }
144
145 instance = TAVOR_DEV_INSTANCE(dev);
146 if (instance == -1) {
147 return (EBADF);
148 }
149
150 state = ddi_get_soft_state(tavor_statep, instance);
151 if (state == NULL) {
152 return (EBADF);
153 }
154
155 status = 0;
156
157 switch (cmd) {
158 case TAVOR_IOCTL_FLASH_READ:
159 status = tavor_ioctl_flash_read(state, dev, arg, mode);
160 break;
161
162 case TAVOR_IOCTL_FLASH_WRITE:
163 status = tavor_ioctl_flash_write(state, dev, arg, mode);
164 break;
165
166 case TAVOR_IOCTL_FLASH_ERASE:
167 status = tavor_ioctl_flash_erase(state, dev, arg, mode);
168 break;
169
170 case TAVOR_IOCTL_FLASH_INIT:
171 status = tavor_ioctl_flash_init(state, dev, arg, mode);
172 break;
173
174 case TAVOR_IOCTL_FLASH_FINI:
175 status = tavor_ioctl_flash_fini(state, dev);
176 break;
177
178 case TAVOR_IOCTL_INFO:
179 status = tavor_ioctl_info(state, dev, arg, mode);
180 break;
181
182 case TAVOR_IOCTL_PORTS:
183 status = tavor_ioctl_ports(state, arg, mode);
184 break;
185
186 case TAVOR_IOCTL_DDR_READ:
187 status = tavor_ioctl_ddr_read(state, arg, mode);
188 break;
189
190 case TAVOR_IOCTL_LOOPBACK:
191 status = tavor_ioctl_loopback(state, arg, mode);
192 break;
193
194 #ifdef DEBUG
195 case TAVOR_IOCTL_REG_WRITE:
196 status = tavor_ioctl_reg_write(state, arg, mode);
197 break;
198
199 case TAVOR_IOCTL_REG_READ:
200 status = tavor_ioctl_reg_read(state, arg, mode);
201 break;
202 #endif /* DEBUG */
203
204 default:
205 status = ENOTTY;
206 break;
207 }
208 *rvalp = status;
209
210 return (status);
211 }
212
213 /*
214 * tavor_ioctl_flash_read()
215 */
216 static int
217 tavor_ioctl_flash_read(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
218 {
219 tavor_flash_ioctl_t ioctl_info;
220 int status = 0;
221
222 /*
223 * Check that flash init ioctl has been called first. And check
224 * that the same dev_t that called init is the one calling read now.
225 */
226 mutex_enter(&state->ts_fw_flashlock);
227 if ((state->ts_fw_flashdev != dev) ||
228 (state->ts_fw_flashstarted == 0)) {
229 mutex_exit(&state->ts_fw_flashlock);
230 return (EIO);
231 }
232
233 /* copy user struct to kernel */
234 #ifdef _MULTI_DATAMODEL
235 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
236 tavor_flash_ioctl32_t info32;
237
238 if (ddi_copyin((void *)arg, &info32,
239 sizeof (tavor_flash_ioctl32_t), mode) != 0) {
240 mutex_exit(&state->ts_fw_flashlock);
241 return (EFAULT);
242 }
243 ioctl_info.tf_type = info32.tf_type;
244 ioctl_info.tf_sector = (caddr_t)(uintptr_t)info32.tf_sector;
245 ioctl_info.tf_sector_num = info32.tf_sector_num;
246 ioctl_info.tf_addr = info32.tf_addr;
247 } else
248 #endif /* _MULTI_DATAMODEL */
249 if (ddi_copyin((void *)arg, &ioctl_info, sizeof (tavor_flash_ioctl_t),
250 mode) != 0) {
251 mutex_exit(&state->ts_fw_flashlock);
252 return (EFAULT);
253 }
254
255 /*
256 * Determine type of READ ioctl
257 */
258 switch (ioctl_info.tf_type) {
259 case TAVOR_FLASH_READ_SECTOR:
260 /* Check if sector num is too large for flash device */
261 if (ioctl_info.tf_sector_num >=
262 (state->ts_fw_device_sz >> state->ts_fw_log_sector_sz)) {
263 mutex_exit(&state->ts_fw_flashlock);
264 return (EFAULT);
265 }
266
267 /* Perform the Sector Read */
268 tavor_flash_reset(state);
269 tavor_flash_read_sector(state, ioctl_info.tf_sector_num);
270
271 /* copyout the firmware sector image data */
272 if (ddi_copyout(&state->ts_fw_sector[0],
273 &ioctl_info.tf_sector[0], 1 << state->ts_fw_log_sector_sz,
274 mode) != 0) {
275 mutex_exit(&state->ts_fw_flashlock);
276 return (EFAULT);
277 }
278 break;
279
280 case TAVOR_FLASH_READ_QUADLET:
281 /* Check if addr is too large for flash device */
282 if (ioctl_info.tf_addr >= state->ts_fw_device_sz) {
283 mutex_exit(&state->ts_fw_flashlock);
284 return (EFAULT);
285 }
286
287 /* Perform the Quadlet Read */
288 tavor_flash_reset(state);
289 tavor_flash_read_quadlet(state, &ioctl_info.tf_quadlet,
290 ioctl_info.tf_addr);
291 break;
292
293 default:
294 status = EIO;
295 break;
296 }
297
298 /* copy results back to userland */
299 #ifdef _MULTI_DATAMODEL
300 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
301 tavor_flash_ioctl32_t info32;
302
303 info32.tf_quadlet = ioctl_info.tf_quadlet;
304 info32.tf_type = ioctl_info.tf_type;
305 info32.tf_sector_num = ioctl_info.tf_sector_num;
306 info32.tf_sector = (caddr32_t)(uintptr_t)ioctl_info.tf_sector;
307 info32.tf_addr = ioctl_info.tf_addr;
308
309 if (ddi_copyout(&info32, (void *)arg,
310 sizeof (tavor_flash_ioctl32_t), mode) != 0) {
311 mutex_exit(&state->ts_fw_flashlock);
312 return (EFAULT);
313 }
314 } else
315 #endif /* _MULTI_DATAMODEL */
316 if (ddi_copyout(&ioctl_info, (void *)arg,
317 sizeof (tavor_flash_ioctl_t), mode) != 0) {
318 mutex_exit(&state->ts_fw_flashlock);
319 return (EFAULT);
320 }
321
322 mutex_exit(&state->ts_fw_flashlock);
323 return (status);
324 }
325
326 /*
327 * tavor_ioctl_flash_write()
328 */
329 static int
330 tavor_ioctl_flash_write(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
331 {
332 tavor_flash_ioctl_t ioctl_info;
333 int status = 0;
334
335 /*
336 * Check that flash init ioctl has been called first. And check
337 * that the same dev_t that called init is the one calling write now.
338 */
339 mutex_enter(&state->ts_fw_flashlock);
340 if ((state->ts_fw_flashdev != dev) ||
341 (state->ts_fw_flashstarted == 0)) {
342 mutex_exit(&state->ts_fw_flashlock);
343 return (EIO);
344 }
345
346 /* copy user struct to kernel */
347 #ifdef _MULTI_DATAMODEL
348 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
349 tavor_flash_ioctl32_t info32;
350
351 if (ddi_copyin((void *)arg, &info32,
352 sizeof (tavor_flash_ioctl32_t), mode) != 0) {
353 mutex_exit(&state->ts_fw_flashlock);
354 return (EFAULT);
355 }
356 ioctl_info.tf_type = info32.tf_type;
357 ioctl_info.tf_sector = (caddr_t)(uintptr_t)info32.tf_sector;
358 ioctl_info.tf_sector_num = info32.tf_sector_num;
359 ioctl_info.tf_addr = info32.tf_addr;
360 ioctl_info.tf_byte = info32.tf_byte;
361 } else
362 #endif /* _MULTI_DATAMODEL */
363 if (ddi_copyin((void *)arg, &ioctl_info,
364 sizeof (tavor_flash_ioctl_t), mode) != 0) {
365 mutex_exit(&state->ts_fw_flashlock);
366 return (EFAULT);
367 }
368
369 /*
370 * Determine type of WRITE ioctl
371 */
372 switch (ioctl_info.tf_type) {
373 case TAVOR_FLASH_WRITE_SECTOR:
374 /* Check if sector num is too large for flash device */
375 if (ioctl_info.tf_sector_num >=
376 (state->ts_fw_device_sz >> state->ts_fw_log_sector_sz)) {
377 mutex_exit(&state->ts_fw_flashlock);
378 return (EFAULT);
379 }
380
381 /* copy in fw sector image data */
382 if (ddi_copyin(&ioctl_info.tf_sector[0],
383 &state->ts_fw_sector[0], 1 << state->ts_fw_log_sector_sz,
384 mode) != 0) {
385 mutex_exit(&state->ts_fw_flashlock);
386 return (EFAULT);
387 }
388
389 /* Perform Write Sector */
390 status = tavor_flash_write_sector(state,
391 ioctl_info.tf_sector_num);
392 break;
393
394 case TAVOR_FLASH_WRITE_BYTE:
395 /* Check if addr is too large for flash device */
396 if (ioctl_info.tf_addr >= state->ts_fw_device_sz) {
397 mutex_exit(&state->ts_fw_flashlock);
398 return (EFAULT);
399 }
400
401 /* Perform Write Byte */
402 tavor_flash_bank(state, ioctl_info.tf_addr);
403 tavor_flash_reset(state);
404 status = tavor_flash_write_byte(state, ioctl_info.tf_addr,
405 ioctl_info.tf_byte);
406 tavor_flash_reset(state);
407 break;
408
409 default:
410 status = EIO;
411 break;
412 }
413
414 mutex_exit(&state->ts_fw_flashlock);
415 return (status);
416 }
417
418 /*
419 * tavor_ioctl_flash_erase()
420 */
421 static int
422 tavor_ioctl_flash_erase(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
423 {
424 tavor_flash_ioctl_t ioctl_info;
425 int status = 0;
426
427 /*
428 * Check that flash init ioctl has been called first. And check
429 * that the same dev_t that called init is the one calling erase now.
430 */
431 mutex_enter(&state->ts_fw_flashlock);
432 if ((state->ts_fw_flashdev != dev) ||
433 (state->ts_fw_flashstarted == 0)) {
434 mutex_exit(&state->ts_fw_flashlock);
435 return (EIO);
436 }
437
438 /* copy user struct to kernel */
439 #ifdef _MULTI_DATAMODEL
440 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
441 tavor_flash_ioctl32_t info32;
442
443 if (ddi_copyin((void *)arg, &info32,
444 sizeof (tavor_flash_ioctl32_t), mode) != 0) {
445 mutex_exit(&state->ts_fw_flashlock);
446 return (EFAULT);
447 }
448 ioctl_info.tf_type = info32.tf_type;
449 ioctl_info.tf_sector_num = info32.tf_sector_num;
450 } else
451 #endif /* _MULTI_DATAMODEL */
452 if (ddi_copyin((void *)arg, &ioctl_info, sizeof (tavor_flash_ioctl_t),
453 mode) != 0) {
454 mutex_exit(&state->ts_fw_flashlock);
455 return (EFAULT);
456 }
457
458 /*
459 * Determine type of ERASE ioctl
460 */
461 switch (ioctl_info.tf_type) {
462 case TAVOR_FLASH_ERASE_SECTOR:
463 /* Check if sector num is too large for flash device */
464 if (ioctl_info.tf_sector_num >=
465 (state->ts_fw_device_sz >> state->ts_fw_log_sector_sz)) {
466 mutex_exit(&state->ts_fw_flashlock);
467 return (EFAULT);
468 }
469
470 /* Perform Sector Erase */
471 status = tavor_flash_erase_sector(state,
472 ioctl_info.tf_sector_num);
473 break;
474
475 case TAVOR_FLASH_ERASE_CHIP:
476 /* Perform Chip Erase */
477 status = tavor_flash_erase_chip(state);
478 break;
479
480 default:
481 status = EIO;
482 break;
483 }
484
485 mutex_exit(&state->ts_fw_flashlock);
486 return (status);
487 }
488
489 /*
490 * tavor_ioctl_flash_init()
491 */
492 static int
493 tavor_ioctl_flash_init(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
494 {
495 tavor_flash_init_ioctl_t init_info;
496 int ret;
497 int intel_xcmd = 0;
498
499 /*
500 * init cannot be called more than once. If we have already init'd the
501 * flash, return directly.
502 */
503 mutex_enter(&state->ts_fw_flashlock);
504 if (state->ts_fw_flashstarted == 1) {
505 mutex_exit(&state->ts_fw_flashlock);
506 return (EIO);
507 }
508
509 /* copyin the user struct to kernel */
510 if (ddi_copyin((void *)arg, &init_info,
511 sizeof (tavor_flash_init_ioctl_t), mode) != 0) {
512 mutex_exit(&state->ts_fw_flashlock);
513 return (EFAULT);
514 }
515
516 /* Init Flash */
517 tavor_flash_init(state);
518
519 /* Read CFI info */
520 tavor_flash_cfi_init(state, &init_info.tf_cfi_info[0], &intel_xcmd);
521
522 /*
523 * Return error if the command set is unknown.
524 */
525 if (state->ts_fw_cmdset == TAVOR_FLASH_UNKNOWN_CMDSET) {
526 mutex_exit(&state->ts_fw_flashlock);
527 return (EFAULT);
528 }
529
530 /* Read HWREV - least significant 8 bits is revision ID */
531 init_info.tf_hwrev = pci_config_get32(state->ts_pci_cfghdl,
532 TAVOR_HW_FLASH_CFG_HWREV) & 0xFF;
533
534 /* Fill in the firmwate revision numbers */
535 init_info.tf_fwrev.tfi_maj = state->ts_fw.fw_rev_major;
536 init_info.tf_fwrev.tfi_min = state->ts_fw.fw_rev_minor;
537 init_info.tf_fwrev.tfi_sub = state->ts_fw.fw_rev_subminor;
538
539 /* Alloc flash mem for one sector size */
540 state->ts_fw_sector = kmem_zalloc(1 <<
541 state->ts_fw_log_sector_sz, KM_SLEEP);
542
543 /* Set HW part number and length */
544 init_info.tf_pn_len = state->ts_hca_pn_len;
545 if (state->ts_hca_pn_len != 0) {
546 (void) memcpy(init_info.tf_hwpn, state->ts_hca_pn,
547 state->ts_hca_pn_len);
548 }
549
550 /* Copy ioctl results back to userland */
551 if (ddi_copyout(&init_info, (void *)arg,
552 sizeof (tavor_flash_init_ioctl_t), mode) != 0) {
553
554 tavor_ioctl_flash_cleanup_nolock(state);
555
556 mutex_exit(&state->ts_fw_flashlock);
557 return (EFAULT);
558 }
559
560 /* Set flash state to started */
561 state->ts_fw_flashstarted = 1;
562 state->ts_fw_flashdev = dev;
563
564 mutex_exit(&state->ts_fw_flashlock);
565
566 /*
567 * If "flash init" is successful, add an "on close" callback to the
568 * current dev node to ensure that "flash fini" gets called later
569 * even if the userland process prematurely exits.
570 */
571 ret = tavor_umap_db_set_onclose_cb(dev,
572 TAVOR_ONCLOSE_FLASH_INPROGRESS,
573 (void (*)(void *))tavor_ioctl_flash_cleanup, state);
574 if (ret != DDI_SUCCESS) {
575 (void) tavor_ioctl_flash_fini(state, dev);
576
577 return (EFAULT);
578 }
579
580 return (0);
581 }
582
583 /*
584 * tavor_ioctl_flash_fini()
585 */
586 static int
587 tavor_ioctl_flash_fini(tavor_state_t *state, dev_t dev)
588 {
589 int ret;
590
591 /*
592 * Check that flash init ioctl has been called first. And check
593 * that the same dev_t that called init is the one calling fini now.
594 */
595 mutex_enter(&state->ts_fw_flashlock);
596 if ((state->ts_fw_flashdev != dev) ||
597 (state->ts_fw_flashstarted == 0)) {
598 mutex_exit(&state->ts_fw_flashlock);
599 return (EIO);
600 }
601
602 tavor_ioctl_flash_cleanup_nolock(state);
603
604 mutex_exit(&state->ts_fw_flashlock);
605
606 /*
607 * If "flash fini" is successful, remove the "on close" callback
608 * that was setup during "flash init".
609 */
610 ret = tavor_umap_db_clear_onclose_cb(dev,
611 TAVOR_ONCLOSE_FLASH_INPROGRESS);
612 if (ret != DDI_SUCCESS) {
613 return (EFAULT);
614 }
615
616 return (0);
617 }
618
619
620 /*
621 * tavor_ioctl_flash_cleanup()
622 */
623 static void
624 tavor_ioctl_flash_cleanup(tavor_state_t *state)
625 {
626 mutex_enter(&state->ts_fw_flashlock);
627 tavor_ioctl_flash_cleanup_nolock(state);
628 mutex_exit(&state->ts_fw_flashlock);
629 }
630
631
632 /*
633 * tavor_ioctl_flash_cleanup_nolock()
634 */
635 static void
636 tavor_ioctl_flash_cleanup_nolock(tavor_state_t *state)
637 {
638 ASSERT(MUTEX_HELD(&state->ts_fw_flashlock));
639
640 /* free flash mem */
641 kmem_free(state->ts_fw_sector, 1 << state->ts_fw_log_sector_sz);
642
643 /* Fini the Flash */
644 tavor_flash_fini(state);
645
646 /* Set flash state to fini */
647 state->ts_fw_flashstarted = 0;
648 state->ts_fw_flashdev = 0;
649 }
650
651
652 /*
653 * tavor_ioctl_info()
654 */
655 static int
656 tavor_ioctl_info(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
657 {
658 tavor_info_ioctl_t info;
659 tavor_flash_init_ioctl_t init_info;
660
661 /*
662 * Access to Tavor VTS ioctls is not allowed in "maintenance mode".
663 */
664 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
665 return (EFAULT);
666 }
667
668 /* copyin the user struct to kernel */
669 if (ddi_copyin((void *)arg, &info, sizeof (tavor_info_ioctl_t),
670 mode) != 0) {
671 return (EFAULT);
672 }
673
674 /*
675 * Check ioctl revision
676 */
677 if (info.ti_revision != TAVOR_VTS_IOCTL_REVISION) {
678 return (EINVAL);
679 }
680
681 /*
682 * If the 'fw_device_sz' has not been initialized yet, we initialize it
683 * here. This is done by leveraging the
684 * tavor_ioctl_flash_init()/fini() calls. We also hold our own mutex
685 * around this operation in case we have multiple VTS threads in
686 * process at the same time.
687 */
688 mutex_enter(&state->ts_info_lock);
689 if (state->ts_fw_device_sz == 0) {
690 if (tavor_ioctl_flash_init(state, dev, (intptr_t)&init_info,
691 (FKIOCTL | mode)) != 0) {
692 mutex_exit(&state->ts_info_lock);
693 return (EFAULT);
694 }
695 (void) tavor_ioctl_flash_fini(state, dev);
696 }
697 mutex_exit(&state->ts_info_lock);
698
699 info.ti_hw_rev = state->ts_adapter.rev_id;
700 info.ti_flash_sz = state->ts_fw_device_sz;
701 info.ti_fw_rev.tfi_maj = state->ts_fw.fw_rev_major;
702 info.ti_fw_rev.tfi_min = state->ts_fw.fw_rev_minor;
703 info.ti_fw_rev.tfi_sub = state->ts_fw.fw_rev_subminor;
704 info.ti_mem_start_offset = 0;
705 info.ti_mem_end_offset = state->ts_ddr.ddr_endaddr -
706 state->ts_ddr.ddr_baseaddr;
707
708 /* Copy ioctl results back to user struct */
709 if (ddi_copyout(&info, (void *)arg, sizeof (tavor_info_ioctl_t),
710 mode) != 0) {
711 return (EFAULT);
712 }
713
714 return (0);
715 }
716
717 /*
718 * tavor_ioctl_ports()
719 */
720 static int
721 tavor_ioctl_ports(tavor_state_t *state, intptr_t arg, int mode)
722 {
723 tavor_ports_ioctl_t info;
724 tavor_stat_port_ioctl_t portstat;
725 ibt_hca_portinfo_t pi;
726 uint_t tbl_size;
727 ib_gid_t *sgid_tbl;
728 ib_pkey_t *pkey_tbl;
729 int i;
730
731 /*
732 * Access to Tavor VTS ioctls is not allowed in "maintenance mode".
733 */
734 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
735 return (EFAULT);
736 }
737
738 /* copyin the user struct to kernel */
739 #ifdef _MULTI_DATAMODEL
740 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
741 tavor_ports_ioctl32_t info32;
742
743 if (ddi_copyin((void *)arg, &info32,
744 sizeof (tavor_ports_ioctl32_t), mode) != 0) {
745 return (EFAULT);
746 }
747 info.tp_revision = info32.tp_revision;
748 info.tp_ports =
749 (tavor_stat_port_ioctl_t *)(uintptr_t)info32.tp_ports;
750 info.tp_num_ports = info32.tp_num_ports;
751
752 } else
753 #endif /* _MULTI_DATAMODEL */
754 if (ddi_copyin((void *)arg, &info, sizeof (tavor_ports_ioctl_t),
755 mode) != 0) {
756 return (EFAULT);
757 }
758
759 /*
760 * Check ioctl revision
761 */
762 if (info.tp_revision != TAVOR_VTS_IOCTL_REVISION) {
763 return (EINVAL);
764 }
765
766 /* Allocate space for temporary GID table/PKey table */
767 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
768 sgid_tbl = (ib_gid_t *)kmem_zalloc(tbl_size * sizeof (ib_gid_t),
769 KM_SLEEP);
770 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
771 pkey_tbl = (ib_pkey_t *)kmem_zalloc(tbl_size * sizeof (ib_pkey_t),
772 KM_SLEEP);
773
774 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*sgid_tbl, *pkey_tbl))
775
776 /*
777 * Setup the number of ports, then loop through all ports and
778 * query properties of each.
779 */
780 info.tp_num_ports = (uint8_t)state->ts_cfg_profile->cp_num_ports;
781 for (i = 0; i < info.tp_num_ports; i++) {
782 /*
783 * Get portstate information from the device. If
784 * tavor_port_query() fails, leave zeroes in user
785 * struct port entry and continue.
786 */
787 bzero(&pi, sizeof (ibt_hca_portinfo_t));
788 pi.p_sgid_tbl = sgid_tbl;
789 pi.p_pkey_tbl = pkey_tbl;
790 if (tavor_port_query(state, i + 1, &pi) != 0) {
791 }
792
793 portstat.tsp_port_num = pi.p_port_num;
794 portstat.tsp_state = pi.p_linkstate;
795 portstat.tsp_guid = pi.p_sgid_tbl[0].gid_guid;
796
797 /*
798 * Copy queried port results back to user struct. If
799 * this fails, then break out of loop, attempt to copy
800 * out remaining info to user struct, and return (without
801 * error).
802 */
803 if (ddi_copyout(&portstat,
804 &(((tavor_stat_port_ioctl_t *)info.tp_ports)[i]),
805 sizeof (tavor_stat_port_ioctl_t), mode) != 0) {
806 break;
807 }
808 }
809
810 /* Free the temporary space used for GID table/PKey table */
811 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
812 kmem_free(sgid_tbl, tbl_size * sizeof (ib_gid_t));
813 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
814 kmem_free(pkey_tbl, tbl_size * sizeof (ib_pkey_t));
815
816 /* Copy ioctl results back to user struct */
817 #ifdef _MULTI_DATAMODEL
818 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
819 tavor_ports_ioctl32_t info32;
820
821 info32.tp_revision = info.tp_revision;
822 info32.tp_ports = (caddr32_t)(uintptr_t)info.tp_ports;
823 info32.tp_num_ports = info.tp_num_ports;
824
825 if (ddi_copyout(&info32, (void *)arg,
826 sizeof (tavor_ports_ioctl32_t), mode) != 0) {
827 return (EFAULT);
828 }
829 } else
830 #endif /* _MULTI_DATAMODEL */
831 if (ddi_copyout(&info, (void *)arg, sizeof (tavor_ports_ioctl_t),
832 mode) != 0) {
833 return (EFAULT);
834 }
835
836 return (0);
837 }
838
839 /*
840 * tavor_ioctl_loopback()
841 */
842 static int
843 tavor_ioctl_loopback(tavor_state_t *state, intptr_t arg, int mode)
844 {
845 tavor_loopback_ioctl_t lb;
846 tavor_loopback_state_t lstate;
847 ibt_hca_portinfo_t pi;
848 uint_t tbl_size, loopmax, max_usec;
849 ib_gid_t *sgid_tbl;
850 ib_pkey_t *pkey_tbl;
851 int j, iter, ret;
852
853 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(lstate))
854
855 /*
856 * Access to Tavor VTS ioctls is not allowed in "maintenance mode".
857 */
858 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
859 return (EFAULT);
860 }
861
862 /* copyin the user struct to kernel */
863 #ifdef _MULTI_DATAMODEL
864 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
865 tavor_loopback_ioctl32_t lb32;
866
867 if (ddi_copyin((void *)arg, &lb32,
868 sizeof (tavor_loopback_ioctl32_t), mode) != 0) {
869 return (EFAULT);
870 }
871 lb.tlb_revision = lb32.tlb_revision;
872 lb.tlb_send_buf = (caddr_t)(uintptr_t)lb32.tlb_send_buf;
873 lb.tlb_fail_buf = (caddr_t)(uintptr_t)lb32.tlb_fail_buf;
874 lb.tlb_buf_sz = lb32.tlb_buf_sz;
875 lb.tlb_num_iter = lb32.tlb_num_iter;
876 lb.tlb_pass_done = lb32.tlb_pass_done;
877 lb.tlb_timeout = lb32.tlb_timeout;
878 lb.tlb_error_type = lb32.tlb_error_type;
879 lb.tlb_port_num = lb32.tlb_port_num;
880 lb.tlb_num_retry = lb32.tlb_num_retry;
881 } else
882 #endif /* _MULTI_DATAMODEL */
883 if (ddi_copyin((void *)arg, &lb, sizeof (tavor_loopback_ioctl_t),
884 mode) != 0) {
885 return (EFAULT);
886 }
887
888 /* Initialize the internal loopback test state structure */
889 bzero(&lstate, sizeof (tavor_loopback_state_t));
890
891 /*
892 * Check ioctl revision
893 */
894 if (lb.tlb_revision != TAVOR_VTS_IOCTL_REVISION) {
895 lb.tlb_error_type = TAVOR_LOOPBACK_INVALID_REVISION;
896 (void) tavor_loopback_copyout(&lb, arg, mode);
897 return (EINVAL);
898 }
899
900 /* Validate that specified port number is legal */
901 if (!tavor_portnum_is_valid(state, lb.tlb_port_num)) {
902 lb.tlb_error_type = TAVOR_LOOPBACK_INVALID_PORT;
903 (void) tavor_loopback_copyout(&lb, arg, mode);
904 return (EINVAL);
905 }
906
907 /* Allocate space for temporary GID table/PKey table */
908 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
909 sgid_tbl = (ib_gid_t *)kmem_zalloc(tbl_size * sizeof (ib_gid_t),
910 KM_SLEEP);
911 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
912 pkey_tbl = (ib_pkey_t *)kmem_zalloc(tbl_size * sizeof (ib_pkey_t),
913 KM_SLEEP);
914
915 /*
916 * Get portstate information from specific port on device
917 */
918 bzero(&pi, sizeof (ibt_hca_portinfo_t));
919 pi.p_sgid_tbl = sgid_tbl;
920 pi.p_pkey_tbl = pkey_tbl;
921 if (tavor_port_query(state, lb.tlb_port_num, &pi) != 0) {
922 /* Free the temporary space used for GID table/PKey table */
923 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
924 kmem_free(sgid_tbl, tbl_size * sizeof (ib_gid_t));
925 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
926 kmem_free(pkey_tbl, tbl_size * sizeof (ib_pkey_t));
927
928 lb.tlb_error_type = TAVOR_LOOPBACK_INVALID_PORT;
929 (void) tavor_loopback_copyout(&lb, arg, mode);
930 tavor_loopback_free_state(&lstate);
931 return (EINVAL);
932 }
933
934 lstate.tls_port = pi.p_port_num;
935 lstate.tls_lid = pi.p_base_lid;
936 lstate.tls_pkey_ix = (pi.p_linkstate == TAVOR_PORT_LINK_ACTIVE) ? 1 : 0;
937 lstate.tls_state = state;
938 lstate.tls_retry = lb.tlb_num_retry;
939
940 /* Free the temporary space used for GID table/PKey table */
941 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
942 kmem_free(sgid_tbl, tbl_size * sizeof (ib_gid_t));
943 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
944 kmem_free(pkey_tbl, tbl_size * sizeof (ib_pkey_t));
945
946 /*
947 * Compute the timeout duration in usec per the formula:
948 * to_usec_per_retry = 4.096us * (2 ^ supplied_timeout)
949 * (plus we add a little fudge-factor here too)
950 */
951 lstate.tls_timeout = lb.tlb_timeout;
952 max_usec = (4096 * (1 << lstate.tls_timeout)) / 1000;
953 max_usec = max_usec * (lstate.tls_retry + 1);
954 max_usec = max_usec + 10000;
955
956 /*
957 * Determine how many times we should loop before declaring a
958 * timeout failure.
959 */
960 loopmax = max_usec/TAVOR_VTS_LOOPBACK_MIN_WAIT_DUR;
961 if ((max_usec % TAVOR_VTS_LOOPBACK_MIN_WAIT_DUR) != 0) {
962 loopmax++;
963 }
964
965 if (lb.tlb_send_buf == NULL || lb.tlb_buf_sz == 0) {
966 lb.tlb_error_type = TAVOR_LOOPBACK_SEND_BUF_INVALID;
967 (void) tavor_loopback_copyout(&lb, arg, mode);
968 tavor_loopback_free_state(&lstate);
969 return (EINVAL);
970 }
971
972 /* Allocate protection domain (PD) */
973 if (tavor_loopback_init(state, &lstate) != 0) {
974 lb.tlb_error_type = lstate.tls_err;
975 (void) tavor_loopback_copyout(&lb, arg, mode);
976 tavor_loopback_free_state(&lstate);
977 return (EFAULT);
978 }
979
980 /* Allocate and register a TX buffer */
981 if (tavor_loopback_alloc_mem(&lstate, &lstate.tls_tx,
982 lb.tlb_buf_sz) != 0) {
983 lb.tlb_error_type =
984 TAVOR_LOOPBACK_SEND_BUF_MEM_REGION_ALLOC_FAIL;
985 (void) tavor_loopback_copyout(&lb, arg, mode);
986 tavor_loopback_free_state(&lstate);
987 return (EFAULT);
988 }
989
990 /* Allocate and register an RX buffer */
991 if (tavor_loopback_alloc_mem(&lstate, &lstate.tls_rx,
992 lb.tlb_buf_sz) != 0) {
993 lb.tlb_error_type =
994 TAVOR_LOOPBACK_RECV_BUF_MEM_REGION_ALLOC_FAIL;
995 (void) tavor_loopback_copyout(&lb, arg, mode);
996 tavor_loopback_free_state(&lstate);
997 return (EFAULT);
998 }
999
1000 /* Copy in the transmit buffer data */
1001 if (ddi_copyin((void *)lb.tlb_send_buf, lstate.tls_tx.tlc_buf,
1002 lb.tlb_buf_sz, mode) != 0) {
1003 lb.tlb_error_type = TAVOR_LOOPBACK_SEND_BUF_COPY_FAIL;
1004 (void) tavor_loopback_copyout(&lb, arg, mode);
1005 tavor_loopback_free_state(&lstate);
1006 return (EFAULT);
1007 }
1008
1009 /* Allocate the transmit QP and CQs */
1010 lstate.tls_err = TAVOR_LOOPBACK_XMIT_SEND_CQ_ALLOC_FAIL;
1011 if (tavor_loopback_alloc_qps(&lstate, &lstate.tls_tx) != 0) {
1012 lb.tlb_error_type = lstate.tls_err;
1013 (void) tavor_loopback_copyout(&lb, arg, mode);
1014 tavor_loopback_free_state(&lstate);
1015 return (EFAULT);
1016 }
1017
1018 /* Allocate the receive QP and CQs */
1019 lstate.tls_err = TAVOR_LOOPBACK_RECV_SEND_CQ_ALLOC_FAIL;
1020 if (tavor_loopback_alloc_qps(&lstate, &lstate.tls_rx) != 0) {
1021 lb.tlb_error_type = lstate.tls_err;
1022 (void) tavor_loopback_copyout(&lb, arg, mode);
1023 tavor_loopback_free_state(&lstate);
1024 return (EFAULT);
1025 }
1026
1027 /* Activate the TX QP (connect to RX QP) */
1028 lstate.tls_err = TAVOR_LOOPBACK_XMIT_QP_INIT_FAIL;
1029 if (tavor_loopback_modify_qp(&lstate, &lstate.tls_tx,
1030 lstate.tls_rx.tlc_qp_num) != 0) {
1031 lb.tlb_error_type = lstate.tls_err;
1032 (void) tavor_loopback_copyout(&lb, arg, mode);
1033 tavor_loopback_free_state(&lstate);
1034 return (EFAULT);
1035 }
1036
1037 /* Activate the RX QP (connect to TX QP) */
1038 lstate.tls_err = TAVOR_LOOPBACK_RECV_QP_INIT_FAIL;
1039 if (tavor_loopback_modify_qp(&lstate, &lstate.tls_rx,
1040 lstate.tls_tx.tlc_qp_num) != 0) {
1041 lb.tlb_error_type = lstate.tls_err;
1042 (void) tavor_loopback_copyout(&lb, arg, mode);
1043 tavor_loopback_free_state(&lstate);
1044 return (EFAULT);
1045 }
1046
1047 /* Run the loopback test (for specified number of iterations) */
1048 lb.tlb_pass_done = 0;
1049 for (iter = 0; iter < lb.tlb_num_iter; iter++) {
1050 lstate.tls_err = 0;
1051 bzero(lstate.tls_rx.tlc_buf, lb.tlb_buf_sz);
1052
1053 /* Post RDMA Write work request */
1054 if (tavor_loopback_post_send(&lstate, &lstate.tls_tx,
1055 &lstate.tls_rx) != IBT_SUCCESS) {
1056 lb.tlb_error_type = TAVOR_LOOPBACK_WQE_POST_FAIL;
1057 (void) tavor_loopback_copyout(&lb, arg, mode);
1058 tavor_loopback_free_state(&lstate);
1059 return (EFAULT);
1060 }
1061
1062 /* Poll the TX CQ for a completion every few ticks */
1063 for (j = 0; j < loopmax; j++) {
1064 delay(drv_usectohz(TAVOR_VTS_LOOPBACK_MIN_WAIT_DUR));
1065
1066 ret = tavor_loopback_poll_cq(&lstate, &lstate.tls_tx);
1067 if (((ret != IBT_SUCCESS) && (ret != IBT_CQ_EMPTY)) ||
1068 ((ret == IBT_CQ_EMPTY) && (j == loopmax - 1))) {
1069 lb.tlb_error_type = TAVOR_LOOPBACK_CQ_POLL_FAIL;
1070 if (ddi_copyout(lstate.tls_rx.tlc_buf,
1071 lb.tlb_fail_buf, lstate.tls_tx.tlc_buf_sz,
1072 mode) != 0) {
1073 return (EFAULT);
1074 }
1075 (void) tavor_loopback_copyout(&lb, arg, mode);
1076 tavor_loopback_free_state(&lstate);
1077 return (EFAULT);
1078 } else if (ret == IBT_CQ_EMPTY) {
1079 continue;
1080 }
1081
1082 /* Compare the data buffers */
1083 if (bcmp(lstate.tls_tx.tlc_buf, lstate.tls_rx.tlc_buf,
1084 lb.tlb_buf_sz) == 0) {
1085 break;
1086 } else {
1087 lb.tlb_error_type =
1088 TAVOR_LOOPBACK_SEND_RECV_COMPARE_FAIL;
1089 if (ddi_copyout(lstate.tls_rx.tlc_buf,
1090 lb.tlb_fail_buf, lstate.tls_tx.tlc_buf_sz,
1091 mode) != 0) {
1092 return (EFAULT);
1093 }
1094 (void) tavor_loopback_copyout(&lb, arg, mode);
1095 tavor_loopback_free_state(&lstate);
1096 return (EFAULT);
1097 }
1098 }
1099
1100 lstate.tls_err = TAVOR_LOOPBACK_SUCCESS;
1101 lb.tlb_pass_done = iter + 1;
1102 }
1103
1104 lb.tlb_error_type = TAVOR_LOOPBACK_SUCCESS;
1105
1106 /* Copy ioctl results back to user struct */
1107 ret = tavor_loopback_copyout(&lb, arg, mode);
1108
1109 /* Free up everything and release all consumed resources */
1110 tavor_loopback_free_state(&lstate);
1111
1112 return (ret);
1113 }
1114
1115 /*
1116 * tavor_ioctl_ddr_read()
1117 */
1118 static int
1119 tavor_ioctl_ddr_read(tavor_state_t *state, intptr_t arg, int mode)
1120 {
1121 tavor_ddr_read_ioctl_t rdreg;
1122 uint32_t *addr;
1123 uintptr_t baseaddr;
1124 uint64_t ddr_size;
1125
1126 /*
1127 * Access to Tavor VTS ioctls is not allowed in "maintenance mode".
1128 */
1129 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
1130 return (EFAULT);
1131 }
1132
1133 /* copyin the user struct to kernel */
1134 if (ddi_copyin((void *)arg, &rdreg, sizeof (tavor_ddr_read_ioctl_t),
1135 mode) != 0) {
1136 return (EFAULT);
1137 }
1138
1139 /*
1140 * Check ioctl revision
1141 */
1142 if (rdreg.tdr_revision != TAVOR_VTS_IOCTL_REVISION) {
1143 return (EINVAL);
1144 }
1145
1146 /*
1147 * Check for valid offset
1148 */
1149 ddr_size = (state->ts_ddr.ddr_endaddr - state->ts_ddr.ddr_baseaddr + 1);
1150 if ((uint64_t)rdreg.tdr_offset >= ddr_size) {
1151 return (EINVAL);
1152 }
1153
1154 /* Determine base address for requested register read */
1155 baseaddr = (uintptr_t)state->ts_reg_ddr_baseaddr;
1156
1157 /* Ensure that address is properly-aligned */
1158 addr = (uint32_t *)((baseaddr + rdreg.tdr_offset) & ~0x3);
1159
1160 /* Read the register pointed to by addr */
1161 rdreg.tdr_data = ddi_get32(state->ts_reg_cmdhdl, addr);
1162
1163 /* Copy ioctl results back to user struct */
1164 if (ddi_copyout(&rdreg, (void *)arg, sizeof (tavor_ddr_read_ioctl_t),
1165 mode) != 0) {
1166 return (EFAULT);
1167 }
1168
1169 return (0);
1170 }
1171
1172
1173 #ifdef DEBUG
1174 /*
1175 * tavor_ioctl_reg_read()
1176 */
1177 static int
1178 tavor_ioctl_reg_read(tavor_state_t *state, intptr_t arg, int mode)
1179 {
1180 tavor_reg_ioctl_t rdreg;
1181 uint32_t *addr;
1182 uintptr_t baseaddr;
1183 int status;
1184
1185 /*
1186 * Access to Tavor registers is not allowed in "maintenance mode".
1187 * This is primarily because the device may not have BARs to access
1188 */
1189 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
1190 return (EFAULT);
1191 }
1192
1193 /* Copy in the tavor_reg_ioctl_t structure */
1194 status = ddi_copyin((void *)arg, &rdreg, sizeof (tavor_reg_ioctl_t),
1195 mode);
1196 if (status != 0) {
1197 return (EFAULT);
1198 }
1199
1200 /* Determine base address for requested register set */
1201 switch (rdreg.trg_reg_set) {
1202 case TAVOR_CMD_BAR:
1203 baseaddr = (uintptr_t)state->ts_reg_cmd_baseaddr;
1204 break;
1205
1206 case TAVOR_UAR_BAR:
1207 baseaddr = (uintptr_t)state->ts_reg_uar_baseaddr;
1208 break;
1209
1210 case TAVOR_DDR_BAR:
1211 baseaddr = (uintptr_t)state->ts_reg_ddr_baseaddr;
1212 break;
1213
1214 default:
1215 return (EFAULT);
1216 }
1217
1218 /* Ensure that address is properly-aligned */
1219 addr = (uint32_t *)((baseaddr + rdreg.trg_offset) & ~0x3);
1220
1221 /* Read the register pointed to by addr */
1222 rdreg.trg_data = ddi_get32(state->ts_reg_cmdhdl, addr);
1223
1224 /* Copy in the result into the tavor_reg_ioctl_t structure */
1225 status = ddi_copyout(&rdreg, (void *)arg, sizeof (tavor_reg_ioctl_t),
1226 mode);
1227 if (status != 0) {
1228 return (EFAULT);
1229 }
1230
1231 return (0);
1232 }
1233
1234
1235 /*
1236 * tavor_ioctl_reg_write()
1237 */
1238 static int
1239 tavor_ioctl_reg_write(tavor_state_t *state, intptr_t arg, int mode)
1240 {
1241 tavor_reg_ioctl_t wrreg;
1242 uint32_t *addr;
1243 uintptr_t baseaddr;
1244 int status;
1245
1246 /*
1247 * Access to Tavor registers is not allowed in "maintenance mode".
1248 * This is primarily because the device may not have BARs to access
1249 */
1250 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
1251 return (EFAULT);
1252 }
1253
1254 /* Copy in the tavor_reg_ioctl_t structure */
1255 status = ddi_copyin((void *)arg, &wrreg, sizeof (tavor_reg_ioctl_t),
1256 mode);
1257 if (status != 0) {
1258 return (EFAULT);
1259 }
1260
1261 /* Determine base address for requested register set */
1262 switch (wrreg.trg_reg_set) {
1263 case TAVOR_CMD_BAR:
1264 baseaddr = (uintptr_t)state->ts_reg_cmd_baseaddr;
1265 break;
1266
1267 case TAVOR_UAR_BAR:
1268 baseaddr = (uintptr_t)state->ts_reg_uar_baseaddr;
1269 break;
1270
1271 case TAVOR_DDR_BAR:
1272 baseaddr = (uintptr_t)state->ts_reg_ddr_baseaddr;
1273 break;
1274
1275 default:
1276 return (EFAULT);
1277 }
1278
1279 /* Ensure that address is properly-aligned */
1280 addr = (uint32_t *)((baseaddr + wrreg.trg_offset) & ~0x3);
1281
1282 /* Write the data to the register pointed to by addr */
1283 ddi_put32(state->ts_reg_cmdhdl, addr, wrreg.trg_data);
1284
1285 return (0);
1286 }
1287 #endif /* DEBUG */
1288
1289 /*
1290 * tavor_flash_reset()
1291 */
1292 static void
1293 tavor_flash_reset(tavor_state_t *state)
1294 {
1295 /*
1296 * Performs a reset to the flash device. After a reset the flash will
1297 * be operating in normal mode (capable of read/write, etc.).
1298 */
1299 switch (state->ts_fw_cmdset) {
1300 case TAVOR_FLASH_AMD_CMDSET:
1301 tavor_flash_write(state, 0x555, TAVOR_HW_FLASH_RESET_AMD);
1302 break;
1303
1304 case TAVOR_FLASH_INTEL_CMDSET:
1305 tavor_flash_write(state, 0x555, TAVOR_HW_FLASH_RESET_INTEL);
1306 break;
1307
1308 default:
1309 break;
1310 }
1311 }
1312
1313 /*
1314 * tavor_flash_read_sector()
1315 */
1316 static void
1317 tavor_flash_read_sector(tavor_state_t *state, uint32_t sector_num)
1318 {
1319 uint32_t addr;
1320 uint32_t end_addr;
1321 uint32_t *image;
1322 int i;
1323
1324 image = (uint32_t *)&state->ts_fw_sector[0];
1325
1326 /*
1327 * Calculate the start and end address of the sector, based on the
1328 * sector number passed in.
1329 */
1330 addr = sector_num << state->ts_fw_log_sector_sz;
1331 end_addr = addr + (1 << state->ts_fw_log_sector_sz);
1332
1333 /* Set the flash bank correctly for the given address */
1334 tavor_flash_bank(state, addr);
1335
1336 /* Read the entire sector, one quadlet at a time */
1337 for (i = 0; addr < end_addr; i++, addr += 4) {
1338 image[i] = tavor_flash_read(state, addr);
1339 }
1340 }
1341
1342 /*
1343 * tavor_flash_read_quadlet()
1344 */
1345 static void
1346 tavor_flash_read_quadlet(tavor_state_t *state, uint32_t *data,
1347 uint32_t addr)
1348 {
1349 /* Set the flash bank correctly for the given address */
1350 tavor_flash_bank(state, addr);
1351
1352 /* Read one quadlet of data */
1353 *data = tavor_flash_read(state, addr);
1354 }
1355
1356 /*
1357 * tavor_flash_write_sector()
1358 */
1359 static int
1360 tavor_flash_write_sector(tavor_state_t *state, uint32_t sector_num)
1361 {
1362 uint32_t addr;
1363 uint32_t end_addr;
1364 uchar_t *sector;
1365 int status = 0;
1366 int i;
1367
1368 sector = (uchar_t *)&state->ts_fw_sector[0];
1369
1370 /*
1371 * Calculate the start and end address of the sector, based on the
1372 * sector number passed in.
1373 */
1374 addr = sector_num << state->ts_fw_log_sector_sz;
1375 end_addr = addr + (1 << state->ts_fw_log_sector_sz);
1376
1377 /* Set the flash bank correctly for the given address */
1378 tavor_flash_bank(state, addr);
1379
1380 /* Erase the sector before writing */
1381 tavor_flash_reset(state);
1382 status = tavor_flash_erase_sector(state, sector_num);
1383 if (status != 0) {
1384 return (status);
1385 }
1386
1387 /* Write the entire sector, one byte at a time */
1388 for (i = 0; addr < end_addr; i++, addr++) {
1389 status = tavor_flash_write_byte(state, addr, sector[i]);
1390 if (status != 0) {
1391 break;
1392 }
1393 }
1394
1395 tavor_flash_reset(state);
1396 return (status);
1397 }
1398
1399 /*
1400 * tavor_flash_write_byte()
1401 */
1402 static int
1403 tavor_flash_write_byte(tavor_state_t *state, uint32_t addr, uchar_t data)
1404 {
1405 uint32_t stat;
1406 int status = 0;
1407 int i;
1408
1409 switch (state->ts_fw_cmdset) {
1410 case TAVOR_FLASH_AMD_CMDSET:
1411 /* Issue Flash Byte program command */
1412 tavor_flash_write(state, addr, 0xAA);
1413 tavor_flash_write(state, addr, 0x55);
1414 tavor_flash_write(state, addr, 0xA0);
1415 tavor_flash_write(state, addr, data);
1416
1417 /*
1418 * Wait for Write Byte to Complete:
1419 * 1) Wait 1usec
1420 * 2) Read status of the write operation
1421 * 3) Determine if we have timed out the write operation
1422 * 4) Compare correct data value to the status value that
1423 * was read from the same address.
1424 */
1425 i = 0;
1426 do {
1427 drv_usecwait(1);
1428 stat = tavor_flash_read(state, addr & ~3);
1429
1430 if (i == tavor_hw_flash_timeout_write) {
1431 cmn_err(CE_WARN,
1432 "tavor_flash_write_byte: ACS write "
1433 "timeout: addr: 0x%x, data: 0x%x\n",
1434 addr, data);
1435 status = EIO;
1436 break;
1437 }
1438
1439 i++;
1440 } while (data != ((stat >> ((3 - (addr & 3)) << 3)) & 0xFF));
1441 break;
1442
1443 case TAVOR_FLASH_INTEL_CMDSET:
1444 /* Issue Flash Byte program command */
1445 tavor_flash_write(state, addr, TAVOR_HW_FLASH_ICS_WRITE);
1446 tavor_flash_write(state, addr, data);
1447
1448 /* wait for completion */
1449 i = 0;
1450 do {
1451 drv_usecwait(1);
1452 stat = tavor_flash_read(state, addr & ~3);
1453
1454 if (i == tavor_hw_flash_timeout_write) {
1455 cmn_err(CE_WARN,
1456 "tavor_flash_write_byte: ICS write "
1457 "timeout: addr: %x, data: %x\n",
1458 addr, data);
1459 status = EIO;
1460 break;
1461 }
1462
1463 i++;
1464 } while ((stat & TAVOR_HW_FLASH_ICS_READY) == 0);
1465
1466 if (stat & TAVOR_HW_FLASH_ICS_ERROR) {
1467 cmn_err(CE_WARN,
1468 "tavor_flash_write_byte: ICS write cmd error: "
1469 "addr: %x, data: %x\n",
1470 addr, data);
1471 status = EIO;
1472 }
1473 break;
1474
1475 default:
1476 cmn_err(CE_WARN,
1477 "tavor_flash_write_byte: unknown cmd set: 0x%x\n",
1478 state->ts_fw_cmdset);
1479 status = EIO;
1480 break;
1481 }
1482
1483 return (status);
1484 }
1485
1486 /*
1487 * tavor_flash_erase_sector()
1488 */
1489 static int
1490 tavor_flash_erase_sector(tavor_state_t *state, uint32_t sector_num)
1491 {
1492 uint32_t addr;
1493 uint32_t stat;
1494 int status = 0;
1495 int i;
1496
1497 /* Get address from sector num */
1498 addr = sector_num << state->ts_fw_log_sector_sz;
1499
1500 switch (state->ts_fw_cmdset) {
1501 case TAVOR_FLASH_AMD_CMDSET:
1502 /* Issue Flash Sector Erase Command */
1503 tavor_flash_write(state, addr, 0xAA);
1504 tavor_flash_write(state, addr, 0x55);
1505 tavor_flash_write(state, addr, 0x80);
1506 tavor_flash_write(state, addr, 0xAA);
1507 tavor_flash_write(state, addr, 0x55);
1508 tavor_flash_write(state, addr, 0x30);
1509
1510 /*
1511 * Wait for Sector Erase to Complete
1512 * 1) Wait 1usec
1513 * 2) read the status at the base addr of the sector
1514 * 3) Determine if we have timed out
1515 * 4) Compare status of address with the value of a fully
1516 * erased quadlet. If these are equal, the sector
1517 * has been erased.
1518 */
1519 i = 0;
1520 do {
1521 /* wait 1usec */
1522 drv_usecwait(1);
1523 stat = tavor_flash_read(state, addr);
1524
1525 if (i == tavor_hw_flash_timeout_erase) {
1526 cmn_err(CE_WARN,
1527 "tavor_flash_erase_sector: "
1528 "ACS erase timeout\n");
1529 status = EIO;
1530 break;
1531 }
1532
1533 i++;
1534 } while (stat != 0xFFFFFFFF);
1535 break;
1536
1537 case TAVOR_FLASH_INTEL_CMDSET:
1538 /* Issue Erase Command */
1539 tavor_flash_write(state, addr, TAVOR_HW_FLASH_ICS_ERASE);
1540 tavor_flash_write(state, addr, TAVOR_HW_FLASH_ICS_CONFIRM);
1541
1542 /* wait for completion */
1543 i = 0;
1544 do {
1545 drv_usecwait(1);
1546 stat = tavor_flash_read(state, addr & ~3);
1547
1548 if (i == tavor_hw_flash_timeout_erase) {
1549 cmn_err(CE_WARN,
1550 "tavor_flash_erase_sector: "
1551 "ICS erase timeout\n");
1552 status = EIO;
1553 break;
1554 }
1555
1556 i++;
1557 } while ((stat & TAVOR_HW_FLASH_ICS_READY) == 0);
1558
1559 if (stat & TAVOR_HW_FLASH_ICS_ERROR) {
1560 cmn_err(CE_WARN,
1561 "tavor_flash_erase_sector: "
1562 "ICS erase cmd error\n");
1563 status = EIO;
1564 }
1565 break;
1566
1567 default:
1568 cmn_err(CE_WARN,
1569 "tavor_flash_erase_sector: unknown cmd set: 0x%x\n",
1570 state->ts_fw_cmdset);
1571 status = EIO;
1572 break;
1573 }
1574
1575 tavor_flash_reset(state);
1576
1577 return (status);
1578 }
1579
1580 /*
1581 * tavor_flash_erase_chip()
1582 */
1583 static int
1584 tavor_flash_erase_chip(tavor_state_t *state)
1585 {
1586 uint_t size;
1587 uint32_t stat;
1588 int status = 0;
1589 int num_sect;
1590 int i;
1591
1592 switch (state->ts_fw_cmdset) {
1593 case TAVOR_FLASH_AMD_CMDSET:
1594 /* Issue Flash Chip Erase Command */
1595 tavor_flash_write(state, 0, 0xAA);
1596 tavor_flash_write(state, 0, 0x55);
1597 tavor_flash_write(state, 0, 0x80);
1598 tavor_flash_write(state, 0, 0xAA);
1599 tavor_flash_write(state, 0, 0x55);
1600 tavor_flash_write(state, 0, 0x10);
1601
1602 /*
1603 * Wait for Chip Erase to Complete
1604 * 1) Wait 1usec
1605 * 2) read the status at the base addr of the sector
1606 * 3) Determine if we have timed out
1607 * 4) Compare status of address with the value of a
1608 * fully erased quadlet. If these are equal, the
1609 * chip has been erased.
1610 */
1611 i = 0;
1612 do {
1613 /* wait 1usec */
1614 drv_usecwait(1);
1615 stat = tavor_flash_read(state, 0);
1616
1617 if (i == tavor_hw_flash_timeout_erase) {
1618 cmn_err(CE_WARN,
1619 "tavor_flash_erase_chip: erase timeout\n");
1620 status = EIO;
1621 break;
1622 }
1623
1624 i++;
1625 } while (stat != 0xFFFFFFFF);
1626 break;
1627
1628 case TAVOR_FLASH_INTEL_CMDSET:
1629 /*
1630 * The Intel chip doesn't have a chip erase command, so erase
1631 * all blocks one at a time.
1632 */
1633 size = (0x1 << state->ts_fw_log_sector_sz);
1634 num_sect = state->ts_fw_device_sz / size;
1635
1636 for (i = 0; i < num_sect; i++) {
1637 status = tavor_flash_erase_sector(state, i);
1638 if (status != 0) {
1639 cmn_err(CE_WARN,
1640 "tavor_flash_erase_chip: "
1641 "ICS sector %d erase error\n", i);
1642 status = EIO;
1643 break;
1644 }
1645 }
1646 break;
1647
1648 default:
1649 cmn_err(CE_WARN, "tavor_flash_erase_chip: "
1650 "unknown cmd set: 0x%x\n", state->ts_fw_cmdset);
1651 status = EIO;
1652 break;
1653 }
1654
1655 return (status);
1656 }
1657
1658 /*
1659 * tavor_flash_bank()
1660 */
1661 static void
1662 tavor_flash_bank(tavor_state_t *state, uint32_t addr)
1663 {
1664 ddi_acc_handle_t hdl;
1665 uint32_t bank;
1666
1667 /* Set handle */
1668 hdl = state->ts_pci_cfghdl;
1669
1670 /* Determine the bank setting from the address */
1671 bank = addr & TAVOR_HW_FLASH_BANK_MASK;
1672
1673 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(state->ts_fw_flashbank))
1674
1675 /*
1676 * If the bank is different from the currently set bank, we need to
1677 * change it. Also, if an 'addr' of 0 is given, this allows the
1678 * capability to force the flash bank to 0. This is useful at init
1679 * time to initially set the bank value
1680 */
1681 if (state->ts_fw_flashbank != bank || addr == 0) {
1682 /* Set bank using the GPIO settings */
1683 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_DATACLEAR, 0x70);
1684 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_DATASET,
1685 (bank >> 15) & 0x70);
1686
1687 /* Save the bank state */
1688 state->ts_fw_flashbank = bank;
1689 }
1690 }
1691
1692 /*
1693 * tavor_flash_read()
1694 */
1695 static uint32_t
1696 tavor_flash_read(tavor_state_t *state, uint32_t addr)
1697 {
1698 ddi_acc_handle_t hdl;
1699 uint32_t data;
1700 int timeout;
1701
1702 /* Set handle */
1703 hdl = state->ts_pci_cfghdl;
1704
1705 /*
1706 * The Read operation does the following:
1707 * 1) Write the masked address to the TAVOR_FLASH_ADDR register.
1708 * Only the least significant 19 bits are valid.
1709 * 2) Read back the register until the command has completed.
1710 * 3) Read the data retrieved from the address at the TAVOR_FLASH_DATA
1711 * register.
1712 */
1713 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_ADDR,
1714 (addr & TAVOR_HW_FLASH_ADDR_MASK) | (1 << 29));
1715
1716 timeout = 0;
1717 do {
1718 data = tavor_flash_read_cfg(hdl, TAVOR_HW_FLASH_ADDR);
1719 timeout++;
1720 } while ((data & TAVOR_HW_FLASH_CMD_MASK) &&
1721 (timeout < tavor_hw_flash_timeout_config));
1722
1723 if (timeout == tavor_hw_flash_timeout_config) {
1724 cmn_err(CE_WARN, "tavor_flash_read: config command timeout.\n");
1725 }
1726
1727 data = tavor_flash_read_cfg(hdl, TAVOR_HW_FLASH_DATA);
1728
1729 return (data);
1730 }
1731
1732 /*
1733 * tavor_flash_write()
1734 */
1735 static void
1736 tavor_flash_write(tavor_state_t *state, uint32_t addr, uchar_t data)
1737 {
1738 ddi_acc_handle_t hdl;
1739 int cmd;
1740 int timeout;
1741
1742 /* Set handle */
1743 hdl = state->ts_pci_cfghdl;
1744
1745 /*
1746 * The Write operation does the following:
1747 * 1) Write the data to be written to the TAVOR_FLASH_DATA offset.
1748 * 2) Write the address to write the data to to the TAVOR_FLASH_ADDR
1749 * offset.
1750 * 3) Wait until the write completes.
1751 */
1752 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_DATA, data << 24);
1753 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_ADDR,
1754 (addr & 0x7FFFF) | (2 << 29));
1755
1756 timeout = 0;
1757 do {
1758 cmd = tavor_flash_read_cfg(hdl, TAVOR_HW_FLASH_ADDR);
1759 timeout++;
1760 } while ((cmd & TAVOR_HW_FLASH_CMD_MASK) &&
1761 (timeout < tavor_hw_flash_timeout_config));
1762
1763 if (timeout == tavor_hw_flash_timeout_config) {
1764 cmn_err(CE_WARN, "tavor_flash_write: config cmd timeout.\n");
1765 }
1766 }
1767
1768 /*
1769 * tavor_flash_init()
1770 */
1771 static void
1772 tavor_flash_init(tavor_state_t *state)
1773 {
1774 uint32_t word;
1775 ddi_acc_handle_t hdl;
1776 int sema_cnt;
1777 int gpio;
1778
1779 /* Set handle */
1780 hdl = state->ts_pci_cfghdl;
1781
1782 /* Init the flash */
1783
1784 /*
1785 * Grab the GPIO semaphore. This allows us exclusive access to the
1786 * GPIO settings on the Tavor for the duration of the flash burning
1787 * procedure.
1788 */
1789 sema_cnt = 0;
1790 do {
1791 word = tavor_flash_read_cfg(hdl, TAVOR_HW_FLASH_GPIO_SEMA);
1792 if (word == 0) {
1793 break;
1794 }
1795
1796 sema_cnt++;
1797 drv_usecwait(1);
1798 } while (sema_cnt < tavor_hw_flash_timeout_gpio_sema);
1799
1800 /*
1801 * Determine if we timed out trying to grab the GPIO semaphore
1802 */
1803 if (sema_cnt == tavor_hw_flash_timeout_gpio_sema) {
1804 cmn_err(CE_WARN, "tavor_flash_init: GPIO SEMA timeout\n");
1805 }
1806
1807 /* Save away original GPIO Values */
1808 state->ts_fw_gpio[0] = tavor_flash_read_cfg(hdl,
1809 TAVOR_HW_FLASH_GPIO_DIR);
1810 state->ts_fw_gpio[1] = tavor_flash_read_cfg(hdl,
1811 TAVOR_HW_FLASH_GPIO_POL);
1812 state->ts_fw_gpio[2] = tavor_flash_read_cfg(hdl,
1813 TAVOR_HW_FLASH_GPIO_MOD);
1814 state->ts_fw_gpio[3] = tavor_flash_read_cfg(hdl,
1815 TAVOR_HW_FLASH_GPIO_DAT);
1816
1817 /* Set New GPIO Values */
1818 gpio = state->ts_fw_gpio[0] | 0x70;
1819 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_DIR, gpio);
1820
1821 gpio = state->ts_fw_gpio[1] & ~0x70;
1822 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_POL, gpio);
1823
1824 gpio = state->ts_fw_gpio[2] & ~0x70;
1825 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_MOD, gpio);
1826
1827 /* Set CPUMODE to enable tavor to access the flash device */
1828 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_CPUMODE,
1829 1 << TAVOR_HW_FLASH_CPU_SHIFT);
1830
1831 /* Initialize to bank 0 */
1832 tavor_flash_bank(state, 0);
1833 }
1834
1835 /*
1836 * tavor_flash_cfi_init
1837 * Implements access to the CFI (Common Flash Interface) data
1838 */
1839 static void
1840 tavor_flash_cfi_init(tavor_state_t *state, uint32_t *cfi_info, int *intel_xcmd)
1841 {
1842 uint32_t data;
1843 uint32_t sector_sz_bytes;
1844 uint32_t bit_count;
1845 uint8_t cfi_ch_info[TAVOR_CFI_INFO_SIZE];
1846 int i;
1847
1848 /*
1849 * Determine if the user command supports the Intel Extended
1850 * Command Set. The query string is contained in the fourth
1851 * quad word.
1852 */
1853 tavor_flash_cfi_byte(cfi_ch_info, cfi_info[0x04], 0x10);
1854 if (cfi_ch_info[0x10] == 'M' &&
1855 cfi_ch_info[0x11] == 'X' &&
1856 cfi_ch_info[0x12] == '2') {
1857 *intel_xcmd = 1; /* support is there */
1858 }
1859
1860 /* CFI QUERY */
1861 tavor_flash_write(state, 0x55, TAVOR_FLASH_CFI_INIT);
1862
1863 /* Read in CFI data */
1864 for (i = 0; i < TAVOR_CFI_INFO_SIZE; i += 4) {
1865 data = tavor_flash_read(state, i);
1866 tavor_flash_cfi_byte(cfi_ch_info, data, i);
1867 }
1868
1869 /* Determine chip set */
1870 state->ts_fw_cmdset = TAVOR_FLASH_UNKNOWN_CMDSET;
1871 if (cfi_ch_info[0x20] == 'Q' &&
1872 cfi_ch_info[0x22] == 'R' &&
1873 cfi_ch_info[0x24] == 'Y') {
1874 /*
1875 * Mode: x16 working in x8 mode (Intel).
1876 * Pack data - skip spacing bytes.
1877 */
1878 for (i = 0; i < TAVOR_CFI_INFO_SIZE; i += 2) {
1879 cfi_ch_info[i/2] = cfi_ch_info[i];
1880 }
1881 }
1882 state->ts_fw_cmdset = cfi_ch_info[0x13];
1883 if (state->ts_fw_cmdset != TAVOR_FLASH_INTEL_CMDSET &&
1884 state->ts_fw_cmdset != TAVOR_FLASH_AMD_CMDSET) {
1885 cmn_err(CE_WARN,
1886 "tavor_flash_cfi_init: UNKNOWN chip cmd set\n");
1887 state->ts_fw_cmdset = TAVOR_FLASH_UNKNOWN_CMDSET;
1888 return;
1889 }
1890
1891 /* Determine total bytes in one sector size */
1892 sector_sz_bytes = ((cfi_ch_info[0x30] << 8) | cfi_ch_info[0x2F]) << 8;
1893
1894 /* Calculate equivalent of log2 (n) */
1895 for (bit_count = 0; sector_sz_bytes > 1; bit_count++) {
1896 sector_sz_bytes >>= 1;
1897 }
1898
1899 /* Set sector size */
1900 state->ts_fw_log_sector_sz = bit_count;
1901
1902 /* Set flash size */
1903 state->ts_fw_device_sz = 0x1 << cfi_ch_info[0x27];
1904
1905 /* Reset to turn off CFI mode */
1906 tavor_flash_reset(state);
1907
1908 /*
1909 * Pass CFI data back to user command.
1910 */
1911 for (i = 0; i < TAVOR_FLASH_CFI_SIZE_QUADLET; i++) {
1912 tavor_flash_cfi_dword(&cfi_info[i], cfi_ch_info, i << 2);
1913 }
1914
1915 if (*intel_xcmd == 1) {
1916 /*
1917 * Inform the user cmd that this driver does support the
1918 * Intel Extended Command Set.
1919 */
1920 cfi_ch_info[0x10] = 'M';
1921 cfi_ch_info[0x11] = 'X';
1922 cfi_ch_info[0x12] = '2';
1923 } else {
1924 cfi_ch_info[0x10] = 'Q';
1925 cfi_ch_info[0x11] = 'R';
1926 cfi_ch_info[0x12] = 'Y';
1927 }
1928 cfi_ch_info[0x13] = state->ts_fw_cmdset;
1929 tavor_flash_cfi_dword(&cfi_info[0x4], cfi_ch_info, 0x10);
1930 }
1931
1932 /*
1933 * tavor_flash_fini()
1934 */
1935 static void
1936 tavor_flash_fini(tavor_state_t *state)
1937 {
1938 ddi_acc_handle_t hdl;
1939
1940 /* Set handle */
1941 hdl = state->ts_pci_cfghdl;
1942
1943 /* Restore original GPIO Values */
1944 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_DIR,
1945 state->ts_fw_gpio[0]);
1946 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_POL,
1947 state->ts_fw_gpio[1]);
1948 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_MOD,
1949 state->ts_fw_gpio[2]);
1950 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_DAT,
1951 state->ts_fw_gpio[3]);
1952
1953 /* Give up semaphore */
1954 tavor_flash_write_cfg(hdl, TAVOR_HW_FLASH_GPIO_SEMA, 0);
1955 }
1956
1957 /*
1958 * tavor_flash_read_cfg
1959 */
1960 static uint32_t
1961 tavor_flash_read_cfg(ddi_acc_handle_t pci_config_hdl, uint32_t addr)
1962 {
1963 uint32_t read;
1964
1965 /*
1966 * Perform flash read operation:
1967 * 1) Place addr to read from on the TAVOR_HW_FLASH_CFG_ADDR register
1968 * 2) Read data at that addr from the TAVOR_HW_FLASH_CFG_DATA register
1969 */
1970 pci_config_put32(pci_config_hdl, TAVOR_HW_FLASH_CFG_ADDR, addr);
1971 read = pci_config_get32(pci_config_hdl, TAVOR_HW_FLASH_CFG_DATA);
1972
1973 return (read);
1974 }
1975
1976 /*
1977 * tavor_flash_write_cfg
1978 */
1979 static void
1980 tavor_flash_write_cfg(ddi_acc_handle_t pci_config_hdl, uint32_t addr,
1981 uint32_t data)
1982 {
1983 /*
1984 * Perform flash write operation:
1985 * 1) Place addr to write to on the TAVOR_HW_FLASH_CFG_ADDR register
1986 * 2) Place data to write on to the TAVOR_HW_FLASH_CFG_DATA register
1987 */
1988 pci_config_put32(pci_config_hdl, TAVOR_HW_FLASH_CFG_ADDR, addr);
1989 pci_config_put32(pci_config_hdl, TAVOR_HW_FLASH_CFG_DATA, data);
1990 }
1991
1992 /*
1993 * Support routines to convert Common Flash Interface (CFI) data
1994 * from a 32 bit word to a char array, and from a char array to
1995 * a 32 bit word.
1996 */
1997 static void
1998 tavor_flash_cfi_byte(uint8_t *ch, uint32_t dword, int i)
1999 {
2000 ch[i] = (uint8_t)((dword & 0xFF000000) >> 24);
2001 ch[i+1] = (uint8_t)((dword & 0x00FF0000) >> 16);
2002 ch[i+2] = (uint8_t)((dword & 0x0000FF00) >> 8);
2003 ch[i+3] = (uint8_t)((dword & 0x000000FF));
2004 }
2005
2006 static void
2007 tavor_flash_cfi_dword(uint32_t *dword, uint8_t *ch, int i)
2008 {
2009 *dword = (uint32_t)
2010 ((uint32_t)ch[i] << 24 |
2011 (uint32_t)ch[i+1] << 16 |
2012 (uint32_t)ch[i+2] << 8 |
2013 (uint32_t)ch[i+3]);
2014 }
2015
2016 /*
2017 * tavor_loopback_free_qps
2018 */
2019 static void
2020 tavor_loopback_free_qps(tavor_loopback_state_t *lstate)
2021 {
2022 int i;
2023
2024 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*lstate))
2025
2026 if (lstate->tls_tx.tlc_qp_hdl != NULL) {
2027 (void) tavor_qp_free(lstate->tls_state,
2028 &lstate->tls_tx.tlc_qp_hdl, IBC_FREE_QP_AND_QPN, NULL,
2029 TAVOR_NOSLEEP);
2030 }
2031 if (lstate->tls_rx.tlc_qp_hdl != NULL) {
2032 (void) tavor_qp_free(lstate->tls_state,
2033 &lstate->tls_rx.tlc_qp_hdl, IBC_FREE_QP_AND_QPN, NULL,
2034 TAVOR_NOSLEEP);
2035 }
2036 lstate->tls_tx.tlc_qp_hdl = NULL;
2037 lstate->tls_rx.tlc_qp_hdl = NULL;
2038 for (i = 0; i < 2; i++) {
2039 if (lstate->tls_tx.tlc_cqhdl[i] != NULL) {
2040 (void) tavor_cq_free(lstate->tls_state,
2041 &lstate->tls_tx.tlc_cqhdl[i], TAVOR_NOSLEEP);
2042 }
2043 if (lstate->tls_rx.tlc_cqhdl[i] != NULL) {
2044 (void) tavor_cq_free(lstate->tls_state,
2045 &lstate->tls_rx.tlc_cqhdl[i], TAVOR_NOSLEEP);
2046 }
2047 lstate->tls_tx.tlc_cqhdl[i] = NULL;
2048 lstate->tls_rx.tlc_cqhdl[i] = NULL;
2049 }
2050 }
2051
2052 /*
2053 * tavor_loopback_free_state
2054 */
2055 static void
2056 tavor_loopback_free_state(tavor_loopback_state_t *lstate)
2057 {
2058 tavor_loopback_free_qps(lstate);
2059 if (lstate->tls_tx.tlc_mrhdl != NULL) {
2060 (void) tavor_mr_deregister(lstate->tls_state,
2061 &lstate->tls_tx.tlc_mrhdl, TAVOR_MR_DEREG_ALL,
2062 TAVOR_NOSLEEP);
2063 }
2064 if (lstate->tls_rx.tlc_mrhdl != NULL) {
2065 (void) tavor_mr_deregister(lstate->tls_state,
2066 &lstate->tls_rx.tlc_mrhdl, TAVOR_MR_DEREG_ALL,
2067 TAVOR_NOSLEEP);
2068 }
2069 if (lstate->tls_pd_hdl != NULL) {
2070 (void) tavor_pd_free(lstate->tls_state, &lstate->tls_pd_hdl);
2071 }
2072 if (lstate->tls_tx.tlc_buf != NULL) {
2073 kmem_free(lstate->tls_tx.tlc_buf, lstate->tls_tx.tlc_buf_sz);
2074 }
2075 if (lstate->tls_rx.tlc_buf != NULL) {
2076 kmem_free(lstate->tls_rx.tlc_buf, lstate->tls_rx.tlc_buf_sz);
2077 }
2078 bzero(lstate, sizeof (tavor_loopback_state_t));
2079 }
2080
2081 /*
2082 * tavor_loopback_init
2083 */
2084 static int
2085 tavor_loopback_init(tavor_state_t *state, tavor_loopback_state_t *lstate)
2086 {
2087 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*lstate))
2088
2089 lstate->tls_hca_hdl = (ibc_hca_hdl_t)state;
2090 lstate->tls_status = tavor_pd_alloc(lstate->tls_state,
2091 &lstate->tls_pd_hdl, TAVOR_NOSLEEP);
2092 if (lstate->tls_status != IBT_SUCCESS) {
2093 lstate->tls_err = TAVOR_LOOPBACK_PROT_DOMAIN_ALLOC_FAIL;
2094 return (EFAULT);
2095 }
2096
2097 return (0);
2098 }
2099
2100 /*
2101 * tavor_loopback_init_qp_info
2102 */
2103 static void
2104 tavor_loopback_init_qp_info(tavor_loopback_state_t *lstate,
2105 tavor_loopback_comm_t *comm)
2106 {
2107 bzero(&comm->tlc_cq_attr, sizeof (ibt_cq_attr_t));
2108 bzero(&comm->tlc_qp_attr, sizeof (ibt_qp_alloc_attr_t));
2109 bzero(&comm->tlc_qp_info, sizeof (ibt_qp_info_t));
2110
2111 comm->tlc_wrid = 1;
2112 comm->tlc_cq_attr.cq_size = 128;
2113 comm->tlc_qp_attr.qp_sizes.cs_sq_sgl = 3;
2114 comm->tlc_qp_attr.qp_sizes.cs_rq_sgl = 3;
2115 comm->tlc_qp_attr.qp_sizes.cs_sq = 16;
2116 comm->tlc_qp_attr.qp_sizes.cs_rq = 16;
2117 comm->tlc_qp_attr.qp_flags = IBT_WR_SIGNALED;
2118
2119 comm->tlc_qp_info.qp_state = IBT_STATE_RESET;
2120 comm->tlc_qp_info.qp_trans = IBT_RC_SRV;
2121 comm->tlc_qp_info.qp_flags = IBT_CEP_RDMA_RD | IBT_CEP_RDMA_WR;
2122 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_hca_port_num =
2123 lstate->tls_port;
2124 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_pkey_ix =
2125 lstate->tls_pkey_ix;
2126 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_timeout =
2127 lstate->tls_timeout;
2128 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_adds_vect.av_srvl = 0;
2129 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_adds_vect.av_srate =
2130 IBT_SRATE_4X;
2131 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_adds_vect.av_send_grh = 0;
2132 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_adds_vect.av_dlid =
2133 lstate->tls_lid;
2134 comm->tlc_qp_info.qp_transport.rc.rc_retry_cnt = lstate->tls_retry;
2135 comm->tlc_qp_info.qp_transport.rc.rc_sq_psn = 0;
2136 comm->tlc_qp_info.qp_transport.rc.rc_rq_psn = 0;
2137 comm->tlc_qp_info.qp_transport.rc.rc_rdma_ra_in = 4;
2138 comm->tlc_qp_info.qp_transport.rc.rc_rdma_ra_out = 4;
2139 comm->tlc_qp_info.qp_transport.rc.rc_dst_qpn = 0;
2140 comm->tlc_qp_info.qp_transport.rc.rc_min_rnr_nak = IBT_RNR_NAK_655ms;
2141 comm->tlc_qp_info.qp_transport.rc.rc_path_mtu = IB_MTU_1K;
2142 }
2143
2144 /*
2145 * tavor_loopback_alloc_mem
2146 */
2147 static int
2148 tavor_loopback_alloc_mem(tavor_loopback_state_t *lstate,
2149 tavor_loopback_comm_t *comm, int sz)
2150 {
2151 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*comm))
2152
2153 /* Allocate buffer of specified size */
2154 comm->tlc_buf_sz = sz;
2155 comm->tlc_buf = kmem_zalloc(sz, KM_NOSLEEP);
2156 if (comm->tlc_buf == NULL) {
2157 return (EFAULT);
2158 }
2159
2160 /* Register the buffer as a memory region */
2161 comm->tlc_memattr.mr_vaddr = (uint64_t)(uintptr_t)comm->tlc_buf;
2162 comm->tlc_memattr.mr_len = (ib_msglen_t)sz;
2163 comm->tlc_memattr.mr_as = NULL;
2164 comm->tlc_memattr.mr_flags = IBT_MR_NOSLEEP |
2165 IBT_MR_ENABLE_REMOTE_WRITE | IBT_MR_ENABLE_LOCAL_WRITE;
2166
2167 comm->tlc_status = tavor_mr_register(lstate->tls_state,
2168 lstate->tls_pd_hdl, &comm->tlc_memattr, &comm->tlc_mrhdl, NULL);
2169
2170 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*comm->tlc_mrhdl))
2171
2172 comm->tlc_mrdesc.md_vaddr = comm->tlc_mrhdl->mr_bindinfo.bi_addr;
2173 comm->tlc_mrdesc.md_lkey = comm->tlc_mrhdl->mr_lkey;
2174 comm->tlc_mrdesc.md_rkey = comm->tlc_mrhdl->mr_rkey;
2175 if (comm->tlc_status != IBT_SUCCESS) {
2176 return (EFAULT);
2177 }
2178 return (0);
2179 }
2180
2181 /*
2182 * tavor_loopback_alloc_qps
2183 */
2184 static int
2185 tavor_loopback_alloc_qps(tavor_loopback_state_t *lstate,
2186 tavor_loopback_comm_t *comm)
2187 {
2188 uint32_t i, real_size;
2189 tavor_qp_info_t qpinfo;
2190
2191 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*comm))
2192 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*lstate))
2193
2194 /* Allocate send and recv CQs */
2195 for (i = 0; i < 2; i++) {
2196 bzero(&comm->tlc_cq_attr, sizeof (ibt_cq_attr_t));
2197 comm->tlc_cq_attr.cq_size = 128;
2198 comm->tlc_status = tavor_cq_alloc(lstate->tls_state,
2199 (ibt_cq_hdl_t)NULL, &comm->tlc_cq_attr, &real_size,
2200 &comm->tlc_cqhdl[i], TAVOR_NOSLEEP);
2201 if (comm->tlc_status != IBT_SUCCESS) {
2202 lstate->tls_err += i;
2203 return (EFAULT);
2204 }
2205 }
2206
2207 /* Allocate the QP */
2208 tavor_loopback_init_qp_info(lstate, comm);
2209 comm->tlc_qp_attr.qp_pd_hdl = (ibt_pd_hdl_t)lstate->tls_pd_hdl;
2210 comm->tlc_qp_attr.qp_scq_hdl = (ibt_cq_hdl_t)comm->tlc_cqhdl[0];
2211 comm->tlc_qp_attr.qp_rcq_hdl = (ibt_cq_hdl_t)comm->tlc_cqhdl[1];
2212 comm->tlc_qp_attr.qp_ibc_scq_hdl = (ibt_opaque1_t)comm->tlc_cqhdl[0];
2213 comm->tlc_qp_attr.qp_ibc_rcq_hdl = (ibt_opaque1_t)comm->tlc_cqhdl[1];
2214 qpinfo.qpi_attrp = &comm->tlc_qp_attr;
2215 qpinfo.qpi_type = IBT_RC_RQP;
2216 qpinfo.qpi_ibt_qphdl = NULL;
2217 qpinfo.qpi_queueszp = &comm->tlc_chan_sizes;
2218 qpinfo.qpi_qpn = &comm->tlc_qp_num;
2219 comm->tlc_status = tavor_qp_alloc(lstate->tls_state, &qpinfo,
2220 TAVOR_NOSLEEP, NULL);
2221 if (comm->tlc_status == DDI_SUCCESS) {
2222 comm->tlc_qp_hdl = qpinfo.qpi_qphdl;
2223 }
2224
2225 if (comm->tlc_status != IBT_SUCCESS) {
2226 lstate->tls_err += 2;
2227 return (EFAULT);
2228 }
2229 return (0);
2230 }
2231
2232 /*
2233 * tavor_loopback_modify_qp
2234 */
2235 static int
2236 tavor_loopback_modify_qp(tavor_loopback_state_t *lstate,
2237 tavor_loopback_comm_t *comm, uint_t qp_num)
2238 {
2239 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*comm))
2240 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*lstate))
2241
2242 /* Modify QP to INIT */
2243 tavor_loopback_init_qp_info(lstate, comm);
2244 comm->tlc_qp_info.qp_state = IBT_STATE_INIT;
2245 comm->tlc_status = tavor_qp_modify(lstate->tls_state, comm->tlc_qp_hdl,
2246 IBT_CEP_SET_STATE, &comm->tlc_qp_info, &comm->tlc_queue_sizes);
2247 if (comm->tlc_status != IBT_SUCCESS) {
2248 return (EFAULT);
2249 }
2250
2251 /*
2252 * Modify QP to RTR (set destination LID and QP number to local
2253 * LID and QP number)
2254 */
2255 comm->tlc_qp_info.qp_state = IBT_STATE_RTR;
2256 comm->tlc_qp_info.qp_transport.rc.rc_path.cep_adds_vect.av_dlid
2257 = lstate->tls_lid;
2258 comm->tlc_qp_info.qp_transport.rc.rc_dst_qpn = qp_num;
2259 comm->tlc_status = tavor_qp_modify(lstate->tls_state, comm->tlc_qp_hdl,
2260 IBT_CEP_SET_STATE, &comm->tlc_qp_info, &comm->tlc_queue_sizes);
2261 if (comm->tlc_status != IBT_SUCCESS) {
2262 lstate->tls_err += 1;
2263 return (EFAULT);
2264 }
2265
2266 /* Modify QP to RTS */
2267 comm->tlc_qp_info.qp_current_state = IBT_STATE_RTR;
2268 comm->tlc_qp_info.qp_state = IBT_STATE_RTS;
2269 comm->tlc_status = tavor_qp_modify(lstate->tls_state, comm->tlc_qp_hdl,
2270 IBT_CEP_SET_STATE, &comm->tlc_qp_info, &comm->tlc_queue_sizes);
2271 if (comm->tlc_status != IBT_SUCCESS) {
2272 lstate->tls_err += 2;
2273 return (EFAULT);
2274 }
2275 return (0);
2276 }
2277
2278 /*
2279 * tavor_loopback_copyout
2280 */
2281 static int
2282 tavor_loopback_copyout(tavor_loopback_ioctl_t *lb, intptr_t arg, int mode)
2283 {
2284 #ifdef _MULTI_DATAMODEL
2285 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
2286 tavor_loopback_ioctl32_t lb32;
2287
2288 lb32.tlb_revision = lb->tlb_revision;
2289 lb32.tlb_send_buf =
2290 (caddr32_t)(uintptr_t)lb->tlb_send_buf;
2291 lb32.tlb_fail_buf =
2292 (caddr32_t)(uintptr_t)lb->tlb_fail_buf;
2293 lb32.tlb_buf_sz = lb->tlb_buf_sz;
2294 lb32.tlb_num_iter = lb->tlb_num_iter;
2295 lb32.tlb_pass_done = lb->tlb_pass_done;
2296 lb32.tlb_timeout = lb->tlb_timeout;
2297 lb32.tlb_error_type = lb->tlb_error_type;
2298 lb32.tlb_port_num = lb->tlb_port_num;
2299 lb32.tlb_num_retry = lb->tlb_num_retry;
2300
2301 if (ddi_copyout(&lb32, (void *)arg,
2302 sizeof (tavor_loopback_ioctl32_t), mode) != 0) {
2303 return (EFAULT);
2304 }
2305 } else
2306 #endif /* _MULTI_DATAMODEL */
2307 if (ddi_copyout(lb, (void *)arg, sizeof (tavor_loopback_ioctl_t),
2308 mode) != 0) {
2309 return (EFAULT);
2310 }
2311 return (0);
2312 }
2313
2314 /*
2315 * tavor_loopback_post_send
2316 */
2317 static int
2318 tavor_loopback_post_send(tavor_loopback_state_t *lstate,
2319 tavor_loopback_comm_t *tx, tavor_loopback_comm_t *rx)
2320 {
2321 int ret;
2322
2323 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*tx))
2324
2325 bzero(&tx->tlc_sgl, sizeof (ibt_wr_ds_t));
2326 bzero(&tx->tlc_wr, sizeof (ibt_send_wr_t));
2327
2328 /* Initialize local address for TX buffer */
2329 tx->tlc_sgl.ds_va = tx->tlc_mrdesc.md_vaddr;
2330 tx->tlc_sgl.ds_key = tx->tlc_mrdesc.md_lkey;
2331 tx->tlc_sgl.ds_len = tx->tlc_buf_sz;
2332
2333 /* Initialize the remaining details of the work request */
2334 tx->tlc_wr.wr_id = tx->tlc_wrid++;
2335 tx->tlc_wr.wr_flags = IBT_WR_SEND_SIGNAL;
2336 tx->tlc_wr.wr_nds = 1;
2337 tx->tlc_wr.wr_sgl = &tx->tlc_sgl;
2338 tx->tlc_wr.wr_opcode = IBT_WRC_RDMAW;
2339 tx->tlc_wr.wr_trans = IBT_RC_SRV;
2340
2341 /* Initialize the remote address for RX buffer */
2342 tx->tlc_wr.wr.rc.rcwr.rdma.rdma_raddr = rx->tlc_mrdesc.md_vaddr;
2343 tx->tlc_wr.wr.rc.rcwr.rdma.rdma_rkey = rx->tlc_mrdesc.md_rkey;
2344 tx->tlc_complete = 0;
2345 ret = tavor_post_send(lstate->tls_state, tx->tlc_qp_hdl, &tx->tlc_wr,
2346 1, NULL);
2347 if (ret != IBT_SUCCESS) {
2348 return (EFAULT);
2349 }
2350 return (0);
2351 }
2352
2353 /*
2354 * tavor_loopback_poll_cq
2355 */
2356 static int
2357 tavor_loopback_poll_cq(tavor_loopback_state_t *lstate,
2358 tavor_loopback_comm_t *comm)
2359 {
2360 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*comm))
2361
2362 comm->tlc_wc.wc_status = 0;
2363 comm->tlc_num_polled = 0;
2364 comm->tlc_status = tavor_cq_poll(lstate->tls_state,
2365 comm->tlc_cqhdl[0], &comm->tlc_wc, 1, &comm->tlc_num_polled);
2366 if ((comm->tlc_status == IBT_SUCCESS) &&
2367 (comm->tlc_wc.wc_status != IBT_WC_SUCCESS)) {
2368 comm->tlc_status = ibc_get_ci_failure(0);
2369 }
2370 return (comm->tlc_status);
2371 }
Unleashed OS