4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 2010-2013, by Broadcom, Inc.
24 * All Rights Reserved.
28 * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
29 * All rights reserved.
30 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
35 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset)))
36 #define APE_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->ape_regs+(offset)))
39 * Future features ... ?
41 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */
42 #define BGE_IND_IO32 1 /* indirect access code */
43 #define BGE_SEE_IO32 1 /* SEEPROM access code */
44 #define BGE_FLASH_IO32 1 /* FLASH access code */
49 * By default MSI is enabled on all supported platforms but it is disabled
50 * for some Broadcom chips due to known MSI hardware issues. Currently MSI
51 * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
53 boolean_t bge_enable_msi
= B_TRUE
;
56 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
58 boolean_t bge_relaxed_ordering
= B_TRUE
;
64 * Enables/disables automatic recovery after fault detection
67 * Value to program into the MLCR; controls the chip's GPIO pins
70 * Relative priorities of DMA reads & DMA writes respectively.
71 * These may each be patched to any value 0-3. Equal values
72 * will give "fair" (round-robin) arbitration for PCI access.
73 * Unequal values will give one or the other function priority.
76 * Value to put in the Read/Write DMA control register. See
77 * the Broadcom PRM for things you can fiddle with in this
80 * bge_{tx,rx}_{count,ticks}_{norm,intr}
81 * Send/receive interrupt coalescing parameters. Counts are
82 * #s of descriptors, ticks are in microseconds. *norm* values
83 * apply between status updates/interrupts; the *intr* values
84 * refer to the 'during-interrupt' versions - see the PRM.
86 * NOTE: these values have been determined by measurement. They
87 * differ significantly from the values recommended in the PRM.
89 static uint32_t bge_autorecover
= 1;
90 static uint32_t bge_mlcr_default_5714
= MLCR_DEFAULT_5714
;
92 static uint32_t bge_dma_rdprio
= 1;
93 static uint32_t bge_dma_wrprio
= 0;
94 static uint32_t bge_dma_rwctrl
= PDRWCR_VAR_DEFAULT
;
95 static uint32_t bge_dma_rwctrl_5721
= PDRWCR_VAR_5721
;
96 static uint32_t bge_dma_rwctrl_5714
= PDRWCR_VAR_5714
;
97 static uint32_t bge_dma_rwctrl_5715
= PDRWCR_VAR_5715
;
99 uint32_t bge_rx_ticks_norm
= 128;
100 uint32_t bge_tx_ticks_norm
= 512;
101 uint32_t bge_rx_count_norm
= 8;
102 uint32_t bge_tx_count_norm
= 128;
104 static uint32_t bge_rx_ticks_intr
= 128;
105 static uint32_t bge_tx_ticks_intr
= 0; /* 8 for FJ2+ !?!? */
106 static uint32_t bge_rx_count_intr
= 2;
107 static uint32_t bge_tx_count_intr
= 0;
110 * Memory pool configuration parameters.
112 * These are generally specific to each member of the chip family, since
113 * each one may have a different memory size/configuration.
115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits
116 * the driver from programming the various registers; instead they are left
117 * at their hardware defaults. This is the preferred option for later chips
118 * (5705+), whereas the older chips *required* these registers to be set,
119 * since the h/w default was 0 ;-(
121 static uint32_t bge_mbuf_pool_base
= MBUF_POOL_BASE_DEFAULT
;
122 static uint32_t bge_mbuf_pool_base_5704
= MBUF_POOL_BASE_5704
;
123 static uint32_t bge_mbuf_pool_base_5705
= MBUF_POOL_BASE_5705
;
124 static uint32_t bge_mbuf_pool_base_5721
= MBUF_POOL_BASE_5721
;
125 static uint32_t bge_mbuf_pool_len
= MBUF_POOL_LENGTH_DEFAULT
;
126 static uint32_t bge_mbuf_pool_len_5704
= MBUF_POOL_LENGTH_5704
;
127 static uint32_t bge_mbuf_pool_len_5705
= 0; /* use h/w default */
128 static uint32_t bge_mbuf_pool_len_5721
= 0;
131 * Various high and low water marks, thresholds, etc ...
133 * Note: these are taken from revision 7 of the PRM, and some are different
134 * from both the values in earlier PRMs *and* those determined experimentally
135 * and used in earlier versions of this driver ...
137 static uint32_t bge_mbuf_hi_water
= MBUF_HIWAT_DEFAULT
;
138 static uint32_t bge_mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_DEFAULT
;
139 static uint32_t bge_mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_DEFAULT
;
141 static uint32_t bge_dmad_lo_water
= DMAD_POOL_LOWAT_DEFAULT
;
142 static uint32_t bge_dmad_hi_water
= DMAD_POOL_HIWAT_DEFAULT
;
143 static uint32_t bge_lowat_recv_frames
= LOWAT_MAX_RECV_FRAMES_DEFAULT
;
145 static uint32_t bge_replenish_std
= STD_RCV_BD_REPLENISH_DEFAULT
;
146 static uint32_t bge_replenish_mini
= MINI_RCV_BD_REPLENISH_DEFAULT
;
147 static uint32_t bge_replenish_jumbo
= JUMBO_RCV_BD_REPLENISH_DEFAULT
;
149 static uint32_t bge_watchdog_count
= 1 << 16;
150 static uint16_t bge_dma_miss_limit
= 20;
152 static uint32_t bge_stop_start_on_sync
= 0;
155 * bge_intr_max_loop controls the maximum loop number within bge_intr.
156 * When loading NIC with heavy network traffic, it is useful.
157 * Increasing this value could have positive effect to throughput,
158 * but it might also increase ticks of a bge ISR stick on CPU, which might
159 * lead to bad UI interactive experience. So tune this with caution.
161 static int bge_intr_max_loop
= 1;
164 * ========== Low-level chip & ring buffer manipulation ==========
167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */
171 * Config space read-modify-write routines
176 static void bge_cfg_clr16(bge_t
*bgep
, bge_regno_t regno
, uint16_t bits
);
177 #pragma inline(bge_cfg_clr16)
180 bge_cfg_clr16(bge_t
*bgep
, bge_regno_t regno
, uint16_t bits
)
184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
185 (void *)bgep
, regno
, bits
));
187 regval
= pci_config_get16(bgep
->cfg_handle
, regno
);
189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
190 (void *)bgep
, regno
, bits
, regval
, regval
& ~bits
));
193 pci_config_put16(bgep
->cfg_handle
, regno
, regval
);
196 #endif /* BGE_CFG_IO8 */
198 static void bge_cfg_clr32(bge_t
*bgep
, bge_regno_t regno
, uint32_t bits
);
199 #pragma inline(bge_cfg_clr32)
202 bge_cfg_clr32(bge_t
*bgep
, bge_regno_t regno
, uint32_t bits
)
206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
207 (void *)bgep
, regno
, bits
));
209 regval
= pci_config_get32(bgep
->cfg_handle
, regno
);
211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
212 (void *)bgep
, regno
, bits
, regval
, regval
& ~bits
));
215 pci_config_put32(bgep
->cfg_handle
, regno
, regval
);
221 * Indirect access to registers & RISC scratchpads, using config space
224 * This isn't currently used, but someday we might want to use it for
225 * restoring the Subsystem Device/Vendor registers (which aren't directly
226 * writable in Config Space), or for downloading firmware into the RISCs
228 * In any case there are endian issues to be resolved before this code is
229 * enabled; the bizarre way that bytes get twisted by this chip AND by
230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until
231 * it's been thoroughly tested for all access sizes on all supported
232 * architectures (SPARC *and* x86!).
234 uint32_t bge_ind_get32(bge_t
*bgep
, bge_regno_t regno
);
235 #pragma inline(bge_ind_get32)
238 bge_ind_get32(bge_t
*bgep
, bge_regno_t regno
)
242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep
, regno
));
245 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
246 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
247 regno
= LE_32(regno
);
250 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_RIAAR
, regno
);
251 val
= pci_config_get32(bgep
->cfg_handle
, PCI_CONF_BGE_RIADR
);
253 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
254 (void *)bgep
, regno
, val
));
261 void bge_ind_put32(bge_t
*bgep
, bge_regno_t regno
, uint32_t val
);
262 #pragma inline(bge_ind_put32)
265 bge_ind_put32(bge_t
*bgep
, bge_regno_t regno
, uint32_t val
)
267 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
268 (void *)bgep
, regno
, val
));
272 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
273 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
274 regno
= LE_32(regno
);
277 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_RIAAR
, regno
);
278 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_RIADR
, val
);
281 #endif /* BGE_IND_IO32 */
285 static void bge_pci_check(bge_t
*bgep
);
286 #pragma no_inline(bge_pci_check)
289 bge_pci_check(bge_t
*bgep
)
293 pcistatus
= pci_config_get16(bgep
->cfg_handle
, PCI_CONF_STAT
);
294 if ((pcistatus
& (PCI_STAT_R_MAST_AB
| PCI_STAT_R_TARG_AB
)) != 0)
295 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
296 (void *)bgep
, pcistatus
));
299 #endif /* BGE_DEBUGGING */
302 * Perform first-stage chip (re-)initialisation, using only config-space
305 * + Read the vendor/device/revision/subsystem/cache-line-size registers,
306 * returning the data in the structure pointed to by <idp>.
307 * + Configure the target-mode endianness (swap) options.
308 * + Disable interrupts and enable Memory Space accesses.
309 * + Enable or disable Bus Mastering according to the <enable_dma> flag.
311 * This sequence is adapted from Broadcom document 570X-PG102-R,
312 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence
313 * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
315 * This function MUST be called before any non-config-space accesses
316 * are made; on this first call <enable_dma> is B_FALSE, and it
317 * effectively performs steps 3-1(!) of the initialisation sequence
318 * (the rest are not required but should be harmless).
320 * It MUST also be called after a chip reset, as this disables
321 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and
322 * it is effectively performing steps 6-8.
324 void bge_chip_cfg_init(bge_t
*bgep
, chip_id_t
*cidp
, boolean_t enable_dma
);
325 #pragma no_inline(bge_chip_cfg_init)
328 bge_chip_cfg_init(bge_t
*bgep
, chip_id_t
*cidp
, boolean_t enable_dma
)
330 ddi_acc_handle_t handle
;
338 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
339 (void *)bgep
, (void *)cidp
, enable_dma
));
342 * Step 3: save PCI cache line size and subsystem vendor ID
344 * Read all the config-space registers that characterise the
345 * chip, specifically vendor/device/revision/subsystem vendor
346 * and subsystem device id. We expect (but don't check) that
347 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
349 * Also save all bus-transaction related registers (cache-line
350 * size, bus-grant/latency parameters, etc). Some of these are
351 * cleared by reset, so we'll have to restore them later. This
352 * comes from the Broadcom document 570X-PG102-R ...
354 * Note: Broadcom document 570X-PG102-R seems to be in error
355 * here w.r.t. the offsets of the Subsystem Vendor ID and
356 * Subsystem (Device) ID registers, which are the opposite way
357 * round according to the PCI standard. For good measure, we
358 * save/restore both anyway.
360 handle
= bgep
->cfg_handle
;
363 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP
364 * has been set in PCI_CONF_COMM already, we need to write the
365 * byte-swapped value to it. So we just write zero first for simplicity.
367 cidp
->device
= pci_config_get16(handle
, PCI_CONF_DEVID
);
368 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
369 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
370 pci_config_put32(handle
, PCI_CONF_BGE_MHCR
, 0);
373 mhcr
= pci_config_get32(handle
, PCI_CONF_BGE_MHCR
);
374 cidp
->asic_rev
= (mhcr
& MHCR_CHIP_REV_MASK
);
375 cidp
->asic_rev_prod_id
= 0;
376 if ((cidp
->asic_rev
& 0xf0000000) == CHIP_ASIC_REV_USE_PROD_ID_REG
) {
377 prodid
= CHIP_ASIC_REV_PROD_ID_REG
;
378 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
379 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
380 prodid
= CHIP_ASIC_REV_PROD_ID_GEN2_REG
;
382 cidp
->asic_rev_prod_id
= pci_config_get32(handle
, prodid
);
385 cidp
->businfo
= pci_config_get32(handle
, PCI_CONF_BGE_PCISTATE
);
386 cidp
->command
= pci_config_get16(handle
, PCI_CONF_COMM
);
388 cidp
->vendor
= pci_config_get16(handle
, PCI_CONF_VENID
);
389 cidp
->subven
= pci_config_get16(handle
, PCI_CONF_SUBVENID
);
390 cidp
->subdev
= pci_config_get16(handle
, PCI_CONF_SUBSYSID
);
391 cidp
->revision
= pci_config_get8(handle
, PCI_CONF_REVID
);
392 cidp
->clsize
= pci_config_get8(handle
, PCI_CONF_CACHE_LINESZ
);
393 cidp
->latency
= pci_config_get8(handle
, PCI_CONF_LATENCY_TIMER
);
395 /* 5717 C0 is treated just like 5720 A0 */
396 if (pci_config_get16(bgep
->cfg_handle
, PCI_CONF_DEVID
) ==
398 cidp
->device
= DEVICE_ID_5720
;
401 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
402 cidp
->businfo
& PCISTATE_BUS_IS_PCI
? "PCI" : "PCI-X",
403 cidp
->businfo
& PCISTATE_BUS_IS_FAST
? "fast" : "slow",
404 cidp
->businfo
& PCISTATE_BUS_IS_32_BIT
? "narrow" : "wide",
405 cidp
->businfo
& PCISTATE_INTA_STATE
? "high" : "low"));
406 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
407 cidp
->vendor
, cidp
->device
, cidp
->revision
));
408 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
409 cidp
->subven
, cidp
->subdev
, cidp
->asic_rev
));
410 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
411 cidp
->clsize
, cidp
->latency
, cidp
->command
));
414 * Step 2 (also step 6): disable and clear interrupts.
415 * Steps 11-13: configure PIO endianness options, and enable
416 * indirect register access. We'll also select any other
417 * options controlled by the MHCR (e.g. tagged status, mask
418 * interrupt mode) at this stage ...
420 * Note: internally, the chip is 64-bit and BIG-endian, but
421 * since it talks to the host over a (LITTLE-endian) PCI bus,
422 * it normally swaps bytes around at the PCI interface.
423 * However, the PCI host bridge on SPARC systems normally
424 * swaps the byte lanes around too, since SPARCs are also
425 * BIG-endian. So it turns out that on SPARC, the right
426 * option is to tell the chip to swap (and the host bridge
427 * will swap back again), whereas on x86 we ask the chip
428 * NOT to swap, so the natural little-endianness of the
429 * PCI bus is assumed. Then the only thing that doesn't
430 * automatically work right is access to an 8-byte register
431 * by a little-endian host; but we don't want to set the
432 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
433 * accesses don't go where expected ;-( So we live with
434 * that, and perform word-swaps in software in the few cases
435 * where a chip register is defined as an 8-byte value --
436 * see the code below for details ...
438 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
439 * very clear in the register description in the PRM, but
440 * Broadcom document 570X-PG104-R page 248 explains a little
441 * more (under "Broadcom Mask Mode"). The bit changes the way
442 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
443 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
444 * way as the 5700 did, which isn't very convenient. Setting
445 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
446 * bit do just what its name says -- MASK the PCI #INTA output
447 * (i.e. deassert the signal at the pin) leaving all internal
448 * state unchanged. This is much more convenient for our
449 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
451 * Note: the inconvenient semantics of the interrupt mailbox
452 * (nonzero disables and acknowledges/clears the interrupt,
453 * zero enables AND CLEARS it) would make race conditions
454 * likely in the interrupt handler:
456 * (1) acknowledge & disable interrupts
457 * (2) while (more to do)
459 * (3) enable interrupts -- also clears pending
461 * If the chip received more packets and internally generated
462 * an interrupt between the check at (2) and the mbox write
463 * at (3), this interrupt would be lost :-(
465 * The best way to avoid this is to use TAGGED STATUS mode,
466 * where the chip includes a unique tag in each status block
467 * update, and the host, when re-enabling interrupts, passes
468 * the last tag it saw back to the chip; then the chip can
469 * see whether the host is truly up to date, and regenerate
470 * its interrupt if not.
472 mhcr
= MHCR_ENABLE_INDIRECT_ACCESS
|
473 MHCR_ENABLE_PCI_STATE_RW
|
474 MHCR_ENABLE_TAGGED_STATUS_MODE
|
475 MHCR_MASK_INTERRUPT_MODE
|
476 MHCR_CLEAR_INTERRUPT_INTA
;
477 if (bgep
->intr_type
== DDI_INTR_TYPE_FIXED
)
478 mhcr
|= MHCR_MASK_PCI_INT_OUTPUT
;
481 mhcr
|= MHCR_ENABLE_ENDIAN_WORD_SWAP
| MHCR_ENABLE_ENDIAN_BYTE_SWAP
;
482 #endif /* _BIG_ENDIAN */
483 pci_config_put32(handle
, PCI_CONF_BGE_MHCR
, mhcr
);
486 bgep
->asf_wordswapped
= B_FALSE
;
489 pci_state
= (PCISTATE_EXT_ROM_ENABLE
| PCISTATE_EXT_ROM_RETRY
);
490 /* allow reads and writes to the APE register and memory space */
491 if (bgep
->ape_enabled
) {
492 pci_state
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
493 PCISTATE_ALLOW_APE_SHMEM_WR
| PCISTATE_ALLOW_APE_PSPACE_WR
;
495 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_PCISTATE
, pci_state
);
498 * Step 1 (also step 7): Enable PCI Memory Space accesses
499 * Disable Memory Write/Invalidate
500 * Enable or disable Bus Mastering
502 * Note that all other bits are taken from the original value saved
503 * the first time through here, rather than from the current register
504 * value, 'cos that will have been cleared by a soft RESET since.
505 * In this way we preserve the OBP/nexus-parent's preferred settings
506 * of the parity-error and system-error enable bits across multiple
509 command
= bgep
->chipid
.command
| PCI_COMM_MAE
;
510 command
&= ~(PCI_COMM_ME
|PCI_COMM_MEMWR_INVAL
);
512 command
|= PCI_COMM_ME
;
514 * on BCM5714 revision A0, false parity error gets generated
515 * due to a logic bug. Provide a workaround by disabling parity
518 if (((cidp
->device
== DEVICE_ID_5714C
) ||
519 (cidp
->device
== DEVICE_ID_5714S
)) &&
520 (cidp
->revision
== REVISION_ID_5714_A0
)) {
521 command
&= ~PCI_COMM_PARITY_DETECT
;
523 pci_config_put16(handle
, PCI_CONF_COMM
, command
);
526 * On some PCI-E device, there were instances when
527 * the device was still link training.
529 if (bgep
->chipid
.pci_type
== BGE_PCI_E
) {
531 value16
= pci_config_get16(handle
, PCI_CONF_COMM
);
532 while ((value16
!= command
) && (i
< 100)) {
534 value16
= pci_config_get16(handle
, PCI_CONF_COMM
);
540 * Clear any remaining error status bits
542 pci_config_put16(handle
, PCI_CONF_STAT
, ~0);
545 * Do following if and only if the device is NOT BCM5714C OR
548 if (!((cidp
->device
== DEVICE_ID_5714C
) ||
549 (cidp
->device
== DEVICE_ID_5715C
))) {
551 * Make sure these indirect-access registers are sane
552 * rather than random after power-up or reset
554 pci_config_put32(handle
, PCI_CONF_BGE_RIAAR
, 0);
555 pci_config_put32(handle
, PCI_CONF_BGE_MWBAR
, 0);
558 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
560 bge_cfg_clr16(bgep
, PCIX_CONF_COMM
, PCIX_COMM_RELAXED
);
562 if (cidp
->pci_type
== BGE_PCI_E
) {
563 if (DEVICE_5723_SERIES_CHIPSETS(bgep
)) {
564 bge_cfg_clr16(bgep
, PCI_CONF_DEV_CTRL_5723
,
565 DEV_CTRL_NO_SNOOP
| DEV_CTRL_RELAXED
);
566 } else if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
567 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
568 bge_cfg_clr16(bgep
, PCI_CONF_DEV_CTRL_5717
,
569 DEV_CTRL_NO_SNOOP
| DEV_CTRL_RELAXED
);
571 bge_cfg_clr16(bgep
, PCI_CONF_DEV_CTRL
,
572 DEV_CTRL_NO_SNOOP
| DEV_CTRL_RELAXED
);
579 * Distinguish CPU types
581 * These use to distinguish AMD64 or Intel EM64T of CPU running mode.
582 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
583 * for PCI-Express based network interface card. This is the work-around
586 static boolean_t
bge_get_em64t_type(void);
587 #pragma inline(bge_get_em64t_type)
590 bge_get_em64t_type(void)
593 return (x86_vendor
== X86_VENDOR_Intel
);
598 * Operating register get/set access routines
601 uint32_t bge_reg_get32(bge_t
*bgep
, bge_regno_t regno
);
602 #pragma inline(bge_reg_get32)
605 bge_reg_get32(bge_t
*bgep
, bge_regno_t regno
)
607 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
608 (void *)bgep
, regno
));
610 return (ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
)));
613 void bge_reg_put32(bge_t
*bgep
, bge_regno_t regno
, uint32_t data
);
614 #pragma inline(bge_reg_put32)
617 bge_reg_put32(bge_t
*bgep
, bge_regno_t regno
, uint32_t data
)
619 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
620 (void *)bgep
, regno
, data
));
622 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
), data
);
626 void bge_reg_set32(bge_t
*bgep
, bge_regno_t regno
, uint32_t bits
);
627 #pragma inline(bge_reg_set32)
630 bge_reg_set32(bge_t
*bgep
, bge_regno_t regno
, uint32_t bits
)
634 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
635 (void *)bgep
, regno
, bits
));
637 regval
= bge_reg_get32(bgep
, regno
);
639 bge_reg_put32(bgep
, regno
, regval
);
642 void bge_reg_clr32(bge_t
*bgep
, bge_regno_t regno
, uint32_t bits
);
643 #pragma inline(bge_reg_clr32)
646 bge_reg_clr32(bge_t
*bgep
, bge_regno_t regno
, uint32_t bits
)
650 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
651 (void *)bgep
, regno
, bits
));
653 regval
= bge_reg_get32(bgep
, regno
);
655 bge_reg_put32(bgep
, regno
, regval
);
658 static uint64_t bge_reg_get64(bge_t
*bgep
, bge_regno_t regno
);
659 #pragma inline(bge_reg_get64)
662 bge_reg_get64(bge_t
*bgep
, bge_regno_t regno
)
667 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
668 bge_get_em64t_type() ||
669 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
670 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
671 regval
= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
+ 4));
673 regval
|= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
));
675 regval
= ddi_get64(bgep
->io_handle
, PIO_ADDR(bgep
, regno
));
677 #elif defined(__sparc)
678 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
679 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
680 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
681 regval
= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
));
683 regval
|= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
+ 4));
685 regval
= ddi_get64(bgep
->io_handle
, PIO_ADDR(bgep
, regno
));
688 regval
= ddi_get64(bgep
->io_handle
, PIO_ADDR(bgep
, regno
));
691 #ifdef _LITTLE_ENDIAN
692 regval
= (regval
>> 32) | (regval
<< 32);
693 #endif /* _LITTLE_ENDIAN */
695 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
696 (void *)bgep
, regno
, regval
));
701 static void bge_reg_put64(bge_t
*bgep
, bge_regno_t regno
, uint64_t data
);
702 #pragma inline(bge_reg_put64)
705 bge_reg_put64(bge_t
*bgep
, bge_regno_t regno
, uint64_t data
)
707 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
708 (void *)bgep
, regno
, data
));
710 #ifdef _LITTLE_ENDIAN
711 data
= ((data
>> 32) | (data
<< 32));
712 #endif /* _LITTLE_ENDIAN */
715 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
716 bge_get_em64t_type() ||
717 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
718 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
719 ddi_put32(bgep
->io_handle
,
720 PIO_ADDR(bgep
, regno
), (uint32_t)data
);
722 ddi_put32(bgep
->io_handle
,
723 PIO_ADDR(bgep
, regno
+ 4), (uint32_t)(data
>> 32));
726 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, regno
), data
);
728 #elif defined(__sparc)
729 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
730 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
731 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
732 ddi_put32(bgep
->io_handle
,
733 PIO_ADDR(bgep
, regno
+ 4), (uint32_t)data
);
735 ddi_put32(bgep
->io_handle
,
736 PIO_ADDR(bgep
, regno
), (uint32_t)(data
>> 32));
738 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, regno
), data
);
741 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, regno
), data
);
748 * The DDI doesn't provide get/put functions for 128 bit data
749 * so we put RCBs out as two 64-bit chunks instead.
751 static void bge_reg_putrcb(bge_t
*bgep
, bge_regno_t addr
, bge_rcb_t
*rcbp
);
752 #pragma inline(bge_reg_putrcb)
755 bge_reg_putrcb(bge_t
*bgep
, bge_regno_t addr
, bge_rcb_t
*rcbp
)
759 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
760 (void *)bgep
, addr
, rcbp
->host_ring_addr
,
761 rcbp
->max_len
, rcbp
->flags
, rcbp
->nic_ring_addr
));
763 ASSERT((addr
% sizeof (*rcbp
)) == 0);
766 bge_reg_put64(bgep
, addr
, *p
++);
767 bge_reg_put64(bgep
, addr
+8, *p
);
770 void bge_mbx_put(bge_t
*bgep
, bge_regno_t regno
, uint64_t data
);
771 #pragma inline(bge_mbx_put)
774 bge_mbx_put(bge_t
*bgep
, bge_regno_t regno
, uint64_t data
)
776 if (DEVICE_5906_SERIES_CHIPSETS(bgep
))
777 regno
+= INTERRUPT_LP_MBOX_0_REG
- INTERRUPT_MBOX_0_REG
+ 4;
779 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
780 (void *)bgep
, regno
, data
));
783 * Mailbox registers are nominally 64 bits on the 5701, but
784 * the MSW isn't used. On the 5703, they're only 32 bits
785 * anyway. So here we just write the lower(!) 32 bits -
786 * remembering that the chip is big-endian, even though the
787 * PCI bus is little-endian ...
790 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
+4), (uint32_t)data
);
792 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
), (uint32_t)data
);
793 #endif /* _BIG_ENDIAN */
797 uint32_t bge_mbx_get(bge_t
*bgep
, bge_regno_t regno
);
798 #pragma inline(bge_mbx_get)
801 bge_mbx_get(bge_t
*bgep
, bge_regno_t regno
)
805 if (DEVICE_5906_SERIES_CHIPSETS(bgep
))
806 regno
+= INTERRUPT_LP_MBOX_0_REG
- INTERRUPT_MBOX_0_REG
+ 4;
808 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
809 (void *)bgep
, regno
));
812 val32
= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
+4));
814 val32
= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
));
815 #endif /* _BIG_ENDIAN */
818 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x",
819 (void *)bgep
, regno
, val32
));
827 void bge_led_mark(bge_t
*bgep
);
828 #pragma no_inline(bge_led_mark)
831 bge_led_mark(bge_t
*bgep
)
833 uint32_t led_ctrl
= LED_CONTROL_OVERRIDE_LINK
|
834 LED_CONTROL_1000MBPS_LED
|
835 LED_CONTROL_100MBPS_LED
|
836 LED_CONTROL_10MBPS_LED
;
839 * Blink all three LINK LEDs on simultaneously, then all off,
840 * then restore to automatic hardware control. This is used
841 * in laboratory testing to trigger a logic analyser or scope.
843 bge_reg_set32(bgep
, ETHERNET_MAC_LED_CONTROL_REG
, led_ctrl
);
844 led_ctrl
^= LED_CONTROL_OVERRIDE_LINK
;
845 bge_reg_clr32(bgep
, ETHERNET_MAC_LED_CONTROL_REG
, led_ctrl
);
846 led_ctrl
= LED_CONTROL_OVERRIDE_LINK
;
847 bge_reg_clr32(bgep
, ETHERNET_MAC_LED_CONTROL_REG
, led_ctrl
);
850 #endif /* BGE_DEBUGGING */
853 * NIC on-chip memory access routines
855 * Only 32K of NIC memory is visible at a time, controlled by the
856 * Memory Window Base Address Register (in PCI config space). Once
857 * this is set, the 32K region of NIC-local memory that it refers
858 * to can be directly addressed in the upper 32K of the 64K of PCI
859 * memory space used for the device.
862 static void bge_nic_setwin(bge_t
*bgep
, bge_regno_t base
);
863 #pragma inline(bge_nic_setwin)
866 bge_nic_setwin(bge_t
*bgep
, bge_regno_t base
)
870 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
871 (void *)bgep
, base
));
873 ASSERT((base
& MWBAR_GRANULE_MASK
) == 0);
876 * Don't do repeated zero data writes,
877 * if the device is BCM5714C/15C.
879 cidp
= &bgep
->chipid
;
880 if ((cidp
->device
== DEVICE_ID_5714C
) ||
881 (cidp
->device
== DEVICE_ID_5715C
)) {
882 if (bgep
->lastWriteZeroData
&& (base
== (bge_regno_t
)0))
884 /* Adjust lastWriteZeroData */
885 bgep
->lastWriteZeroData
= ((base
== (bge_regno_t
)0) ?
888 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MWBAR
, base
);
891 static uint32_t bge_nic_get32(bge_t
*bgep
, bge_regno_t addr
);
892 #pragma inline(bge_nic_get32)
895 bge_nic_get32(bge_t
*bgep
, bge_regno_t addr
)
899 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
900 if (bgep
->asf_enabled
&& !bgep
->asf_wordswapped
) {
901 /* workaround for word swap error */
909 bge_nic_setwin(bgep
, addr
& ~MWBAR_GRANULE_MASK
);
910 addr
&= MWBAR_GRANULE_MASK
;
911 addr
+= NIC_MEM_WINDOW_OFFSET
;
913 data
= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
));
915 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
916 (void *)bgep
, addr
, data
));
921 void bge_nic_put32(bge_t
*bgep
, bge_regno_t addr
, uint32_t data
);
922 #pragma inline(bge_nic_put32)
925 bge_nic_put32(bge_t
*bgep
, bge_regno_t addr
, uint32_t data
)
927 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
928 (void *)bgep
, addr
, data
));
930 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
931 if (bgep
->asf_enabled
&& !bgep
->asf_wordswapped
) {
932 /* workaround for word swap error */
940 bge_nic_setwin(bgep
, addr
& ~MWBAR_GRANULE_MASK
);
941 addr
&= MWBAR_GRANULE_MASK
;
942 addr
+= NIC_MEM_WINDOW_OFFSET
;
943 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
), data
);
947 static uint64_t bge_nic_get64(bge_t
*bgep
, bge_regno_t addr
);
948 #pragma inline(bge_nic_get64)
951 bge_nic_get64(bge_t
*bgep
, bge_regno_t addr
)
955 bge_nic_setwin(bgep
, addr
& ~MWBAR_GRANULE_MASK
);
956 addr
&= MWBAR_GRANULE_MASK
;
957 addr
+= NIC_MEM_WINDOW_OFFSET
;
960 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
961 bge_get_em64t_type() ||
962 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
963 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
964 data
= ddi_get32(bgep
->io_handle
,
965 PIO_ADDR(bgep
, addr
+ 4));
967 data
|= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
));
969 data
= ddi_get64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
));
971 #elif defined(__sparc)
972 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
973 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
974 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
975 data
= ddi_get32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
));
977 data
|= ddi_get32(bgep
->io_handle
,
978 PIO_ADDR(bgep
, addr
+ 4));
980 data
= ddi_get64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
));
983 data
= ddi_get64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
));
986 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
987 (void *)bgep
, addr
, data
));
992 static void bge_nic_put64(bge_t
*bgep
, bge_regno_t addr
, uint64_t data
);
993 #pragma inline(bge_nic_put64)
996 bge_nic_put64(bge_t
*bgep
, bge_regno_t addr
, uint64_t data
)
998 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
999 (void *)bgep
, addr
, data
));
1001 bge_nic_setwin(bgep
, addr
& ~MWBAR_GRANULE_MASK
);
1002 addr
&= MWBAR_GRANULE_MASK
;
1003 addr
+= NIC_MEM_WINDOW_OFFSET
;
1006 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1007 bge_get_em64t_type() ||
1008 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1009 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
1010 ddi_put32(bgep
->io_handle
,
1011 PIO_ADDR(bgep
, addr
+ 4), (uint32_t)data
);
1013 ddi_put32(bgep
->io_handle
,
1014 PIO_ADDR(bgep
, addr
), (uint32_t)(data
>> 32));
1016 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
), data
);
1018 #elif defined(__sparc)
1019 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1020 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1021 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
1022 ddi_put32(bgep
->io_handle
,
1023 PIO_ADDR(bgep
, addr
+ 4), (uint32_t)data
);
1025 ddi_put32(bgep
->io_handle
,
1026 PIO_ADDR(bgep
, addr
), (uint32_t)(data
>> 32));
1028 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
), data
);
1031 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
), data
);
1038 * The DDI doesn't provide get/put functions for 128 bit data
1039 * so we put RCBs out as two 64-bit chunks instead.
1041 static void bge_nic_putrcb(bge_t
*bgep
, bge_regno_t addr
, bge_rcb_t
*rcbp
);
1042 #pragma inline(bge_nic_putrcb)
1045 bge_nic_putrcb(bge_t
*bgep
, bge_regno_t addr
, bge_rcb_t
*rcbp
)
1049 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
1050 (void *)bgep
, addr
, rcbp
->host_ring_addr
,
1051 rcbp
->max_len
, rcbp
->flags
, rcbp
->nic_ring_addr
));
1053 ASSERT((addr
% sizeof (*rcbp
)) == 0);
1055 bge_nic_setwin(bgep
, addr
& ~MWBAR_GRANULE_MASK
);
1056 addr
&= MWBAR_GRANULE_MASK
;
1057 addr
+= NIC_MEM_WINDOW_OFFSET
;
1061 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1062 bge_get_em64t_type() ||
1063 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1064 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
1065 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
),
1067 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 4),
1068 (uint32_t)(*p
++ >> 32));
1069 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 8),
1071 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 12),
1072 (uint32_t)(*p
>> 32));
1075 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
), *p
++);
1076 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+8), *p
);
1078 #elif defined(__sparc)
1079 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1080 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1081 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
1082 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 4),
1084 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
),
1085 (uint32_t)(*p
++ >> 32));
1086 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 12),
1088 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 8),
1089 (uint32_t)(*p
>> 32));
1091 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
), *p
++);
1092 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 8), *p
);
1095 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
), *p
++);
1096 ddi_put64(bgep
->io_handle
, PIO_ADDR(bgep
, addr
+ 8), *p
);
1102 static void bge_nic_zero(bge_t
*bgep
, bge_regno_t addr
, uint32_t nbytes
);
1103 #pragma inline(bge_nic_zero)
1106 bge_nic_zero(bge_t
*bgep
, bge_regno_t addr
, uint32_t nbytes
)
1108 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1109 (void *)bgep
, addr
, nbytes
));
1111 ASSERT((addr
& ~MWBAR_GRANULE_MASK
) ==
1112 ((addr
+nbytes
) & ~MWBAR_GRANULE_MASK
));
1114 bge_nic_setwin(bgep
, addr
& ~MWBAR_GRANULE_MASK
);
1115 addr
&= MWBAR_GRANULE_MASK
;
1116 addr
+= NIC_MEM_WINDOW_OFFSET
;
1118 (void) ddi_device_zero(bgep
->io_handle
, PIO_ADDR(bgep
, addr
),
1119 nbytes
, 1, DDI_DATA_SZ08_ACC
);
1124 * MII (PHY) register get/set access routines
1126 * These use the chip's MII auto-access method, controlled by the
1127 * MII Communication register at 0x044c, so the CPU doesn't have
1128 * to fiddle with the individual bits.
1132 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */
1134 static uint16_t bge_mii_access(bge_t
*bgep
, bge_regno_t regno
,
1135 uint16_t data
, uint32_t cmd
);
1136 #pragma no_inline(bge_mii_access)
1139 bge_mii_access(bge_t
*bgep
, bge_regno_t regno
, uint16_t data
, uint32_t cmd
)
1145 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1146 (void *)bgep
, regno
, data
, cmd
));
1148 ASSERT(mutex_owned(bgep
->genlock
));
1151 * Assemble the command ...
1153 cmd
|= data
<< MI_COMMS_DATA_SHIFT
;
1154 cmd
|= regno
<< MI_COMMS_REGISTER_SHIFT
;
1155 cmd
|= bgep
->phy_mii_addr
<< MI_COMMS_ADDRESS_SHIFT
;
1156 cmd
|= MI_COMMS_START
;
1159 * Wait for any command already in progress ...
1161 * Note: this *shouldn't* ever find that there is a command
1162 * in progress, because we already hold the <genlock> mutex.
1163 * Nonetheless, we have sometimes seen the MI_COMMS_START
1164 * bit set here -- it seems that the chip can initiate MII
1165 * accesses internally, even with polling OFF.
1167 regval1
= regval2
= bge_reg_get32(bgep
, MI_COMMS_REG
);
1168 for (timeout
= 100; ; ) {
1169 if ((regval2
& MI_COMMS_START
) == 0) {
1170 bge_reg_put32(bgep
, MI_COMMS_REG
, cmd
);
1176 regval2
= bge_reg_get32(bgep
, MI_COMMS_REG
);
1180 return ((uint16_t)~0u);
1183 BGE_REPORT((bgep
, "bge_mii_access: cmd 0x%x -- "
1184 "MI_COMMS_START set for %d us; 0x%x->0x%x",
1185 cmd
, 10*(100-timeout
), regval1
, regval2
));
1187 regval1
= bge_reg_get32(bgep
, MI_COMMS_REG
);
1188 for (timeout
= 1000; ; ) {
1189 if ((regval1
& MI_COMMS_START
) == 0)
1194 regval1
= bge_reg_get32(bgep
, MI_COMMS_REG
);
1198 * Drop out early if the READ FAILED bit is set -- this chip
1199 * could be a 5703/4S, with a SerDes instead of a PHY!
1201 if (regval2
& MI_COMMS_READ_FAILED
)
1202 return ((uint16_t)~0u);
1205 return ((uint16_t)~0u);
1208 * The PRM says to wait 5us after seeing the START bit clear
1209 * and then re-read the register to get the final value of the
1210 * data field, in order to avoid a race condition where the
1211 * START bit is clear but the data field isn't yet valid.
1213 * Note: we don't actually seem to be encounter this race;
1214 * except when the START bit is seen set again (see below),
1215 * the data field doesn't change during this 5us interval.
1218 regval2
= bge_reg_get32(bgep
, MI_COMMS_REG
);
1221 * Unfortunately, when following the PRMs instructions above,
1222 * we have occasionally seen the START bit set again(!) in the
1223 * value read after the 5us delay. This seems to be due to the
1224 * chip autonomously starting another MII access internally.
1225 * In such cases, the command/data/etc fields relate to the
1226 * internal command, rather than the one that we thought had
1227 * just finished. So in this case, we fall back to returning
1228 * the data from the original read that showed START clear.
1230 if (regval2
& MI_COMMS_START
) {
1231 BGE_REPORT((bgep
, "bge_mii_access: cmd 0x%x -- "
1232 "MI_COMMS_START set after transaction; 0x%x->0x%x",
1233 cmd
, regval1
, regval2
));
1237 if (regval2
& MI_COMMS_START
)
1238 return ((uint16_t)~0u);
1240 if (regval2
& MI_COMMS_READ_FAILED
)
1241 return ((uint16_t)~0u);
1243 return ((regval2
& MI_COMMS_DATA_MASK
) >> MI_COMMS_DATA_SHIFT
);
1246 uint16_t bge_mii_get16(bge_t
*bgep
, bge_regno_t regno
);
1247 #pragma no_inline(bge_mii_get16)
1250 bge_mii_get16(bge_t
*bgep
, bge_regno_t regno
)
1252 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1253 (void *)bgep
, regno
));
1255 ASSERT(mutex_owned(bgep
->genlock
));
1257 if (DEVICE_5906_SERIES_CHIPSETS(bgep
) && ((regno
== MII_AUX_CONTROL
) ||
1258 (regno
== MII_MSCONTROL
)))
1261 return (bge_mii_access(bgep
, regno
, 0, MI_COMMS_COMMAND_READ
));
1264 void bge_mii_put16(bge_t
*bgep
, bge_regno_t regno
, uint16_t data
);
1265 #pragma no_inline(bge_mii_put16)
1268 bge_mii_put16(bge_t
*bgep
, bge_regno_t regno
, uint16_t data
)
1270 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1271 (void *)bgep
, regno
, data
));
1273 ASSERT(mutex_owned(bgep
->genlock
));
1275 if (DEVICE_5906_SERIES_CHIPSETS(bgep
) && ((regno
== MII_AUX_CONTROL
) ||
1276 (regno
== MII_MSCONTROL
)))
1279 (void) bge_mii_access(bgep
, regno
, data
, MI_COMMS_COMMAND_WRITE
);
1283 bge_phydsp_read(bge_t
*bgep
, bge_regno_t regno
)
1285 BGE_TRACE(("bge_phydsp_read($%p, 0x%lx)",
1286 (void *)bgep
, regno
));
1288 ASSERT(mutex_owned(bgep
->genlock
));
1290 bge_mii_put16(bgep
, MII_DSP_ADDRESS
, regno
);
1291 return bge_mii_get16(bgep
, MII_DSP_RW_PORT
);
1294 #pragma no_inline(bge_phydsp_write)
1297 bge_phydsp_write(bge_t
*bgep
, bge_regno_t regno
, uint16_t data
)
1299 BGE_TRACE(("bge_phydsp_write($%p, 0x%lx, 0x%x)",
1300 (void *)bgep
, regno
, data
));
1302 ASSERT(mutex_owned(bgep
->genlock
));
1304 bge_mii_put16(bgep
, MII_DSP_ADDRESS
, regno
);
1305 bge_mii_put16(bgep
, MII_DSP_RW_PORT
, data
);
1309 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */
1311 #if BGE_SEE_IO32 || BGE_FLASH_IO32
1314 * Basic SEEPROM get/set access routine
1316 * This uses the chip's SEEPROM auto-access method, controlled by the
1317 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1318 * doesn't have to fiddle with the individual bits.
1320 * The caller should hold <genlock> and *also* have already acquired
1321 * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1325 * ENODATA on access timeout (maybe retryable: device may just be busy)
1326 * EPROTO on other h/w or s/w errors.
1328 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1329 * from a (successful) SEEPROM_ACCESS_READ.
1331 static int bge_seeprom_access(bge_t
*bgep
, uint32_t cmd
, bge_regno_t addr
,
1333 #pragma no_inline(bge_seeprom_access)
1336 bge_seeprom_access(bge_t
*bgep
, uint32_t cmd
, bge_regno_t addr
, uint32_t *dp
)
1341 ASSERT(mutex_owned(bgep
->genlock
));
1344 * On the newer chips that support both SEEPROM & Flash, we need
1345 * to specifically enable SEEPROM access (Flash is the default).
1346 * On older chips, we don't; SEEPROM is the only NVtype supported,
1347 * and the NVM control registers don't exist ...
1349 switch (bgep
->chipid
.nvtype
) {
1350 case BGE_NVTYPE_NONE
:
1351 case BGE_NVTYPE_UNKNOWN
:
1353 case BGE_NVTYPE_SEEPROM
:
1356 case BGE_NVTYPE_LEGACY_SEEPROM
:
1357 case BGE_NVTYPE_UNBUFFERED_FLASH
:
1358 case BGE_NVTYPE_BUFFERED_FLASH
:
1360 bge_reg_set32(bgep
, NVM_CONFIG1_REG
,
1361 NVM_CFG1_LEGACY_SEEPROM_MODE
);
1366 * Check there's no command in progress.
1368 * Note: this *shouldn't* ever find that there is a command
1369 * in progress, because we already hold the <genlock> mutex.
1370 * Also, to ensure we don't have a conflict with the chip's
1371 * internal firmware or a process accessing the same (shared)
1372 * SEEPROM through the other port of a 5704, we've already
1373 * been through the "software arbitration" protocol.
1374 * So this is just a final consistency check: we shouldn't
1375 * see EITHER the START bit (command started but not complete)
1376 * OR the COMPLETE bit (command completed but not cleared).
1378 regval
= bge_reg_get32(bgep
, SERIAL_EEPROM_ADDRESS_REG
);
1379 if (regval
& SEEPROM_ACCESS_START
)
1381 if (regval
& SEEPROM_ACCESS_COMPLETE
)
1385 * Assemble the command ...
1387 cmd
|= addr
& SEEPROM_ACCESS_ADDRESS_MASK
;
1388 addr
>>= SEEPROM_ACCESS_ADDRESS_SIZE
;
1389 addr
<<= SEEPROM_ACCESS_DEVID_SHIFT
;
1390 cmd
|= addr
& SEEPROM_ACCESS_DEVID_MASK
;
1391 cmd
|= SEEPROM_ACCESS_START
;
1392 cmd
|= SEEPROM_ACCESS_COMPLETE
;
1393 cmd
|= regval
& SEEPROM_ACCESS_HALFCLOCK_MASK
;
1395 bge_reg_put32(bgep
, SERIAL_EEPROM_DATA_REG
, *dp
);
1396 bge_reg_put32(bgep
, SERIAL_EEPROM_ADDRESS_REG
, cmd
);
1399 * By observation, a successful access takes ~20us on a 5703/4,
1400 * but apparently much longer (up to 1000us) on the obsolescent
1401 * BCM5700/BCM5701. We want to be sure we don't get any false
1402 * timeouts here; but OTOH, we don't want a bogus access to lock
1403 * out interrupts for longer than necessary. So we'll allow up
1406 for (tries
= 0; tries
< 1000; ++tries
) {
1407 regval
= bge_reg_get32(bgep
, SERIAL_EEPROM_ADDRESS_REG
);
1408 if (regval
& SEEPROM_ACCESS_COMPLETE
)
1413 if (regval
& SEEPROM_ACCESS_COMPLETE
) {
1415 * All OK; read the SEEPROM data register, then write back
1416 * the value read from the address register in order to
1417 * clear the <complete> bit and leave the SEEPROM access
1418 * state machine idle, ready for the next access ...
1420 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries
));
1421 *dp
= bge_reg_get32(bgep
, SERIAL_EEPROM_DATA_REG
);
1422 bge_reg_put32(bgep
, SERIAL_EEPROM_ADDRESS_REG
, regval
);
1427 * Hmm ... what happened here?
1429 * Most likely, the user addressed a non-existent SEEPROM. Or
1430 * maybe the SEEPROM was busy internally (e.g. processing a write)
1431 * and didn't respond to being addressed. Either way, it's left
1432 * the SEEPROM access state machine wedged. So we'll reset it
1433 * before we leave, so it's ready for next time ...
1435 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries
));
1436 bge_reg_set32(bgep
, SERIAL_EEPROM_ADDRESS_REG
, SEEPROM_ACCESS_INIT
);
1441 * Basic Flash get/set access routine
1443 * These use the chip's Flash auto-access method, controlled by the
1444 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1445 * fiddle with the individual bits.
1447 * The caller should hold <genlock> and *also* have already acquired
1448 * the right to access the Flash, via bge_nvmem_acquire() above.
1452 * ENODATA on access timeout (maybe retryable: device may just be busy)
1453 * ENODEV if the NVmem device is missing or otherwise unusable
1455 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1456 * from a (successful) NVM_FLASH_CMD_RD.
1458 static int bge_flash_access(bge_t
*bgep
, uint32_t cmd
, bge_regno_t addr
,
1460 #pragma no_inline(bge_flash_access)
1463 bge_flash_access(bge_t
*bgep
, uint32_t cmd
, bge_regno_t addr
, uint32_t *dp
)
1468 ASSERT(mutex_owned(bgep
->genlock
));
1471 * On the newer chips that support both SEEPROM & Flash, we need
1472 * to specifically disable SEEPROM access while accessing Flash.
1473 * The older chips don't support Flash, and the NVM registers don't
1474 * exist, so we shouldn't be here at all!
1476 switch (bgep
->chipid
.nvtype
) {
1477 case BGE_NVTYPE_NONE
:
1478 case BGE_NVTYPE_UNKNOWN
:
1480 case BGE_NVTYPE_SEEPROM
:
1483 case BGE_NVTYPE_LEGACY_SEEPROM
:
1484 case BGE_NVTYPE_UNBUFFERED_FLASH
:
1485 case BGE_NVTYPE_BUFFERED_FLASH
:
1487 bge_reg_clr32(bgep
, NVM_CONFIG1_REG
,
1488 NVM_CFG1_LEGACY_SEEPROM_MODE
);
1493 * Assemble the command ...
1495 addr
&= NVM_FLASH_ADDR_MASK
;
1496 cmd
|= NVM_FLASH_CMD_DOIT
;
1497 cmd
|= NVM_FLASH_CMD_FIRST
;
1498 cmd
|= NVM_FLASH_CMD_LAST
;
1499 cmd
|= NVM_FLASH_CMD_DONE
;
1501 bge_reg_put32(bgep
, NVM_FLASH_WRITE_REG
, *dp
);
1502 bge_reg_put32(bgep
, NVM_FLASH_ADDR_REG
, addr
);
1503 bge_reg_put32(bgep
, NVM_FLASH_CMD_REG
, cmd
);
1506 * Allow up to 1000ms ...
1508 for (tries
= 0; tries
< 1000; ++tries
) {
1509 regval
= bge_reg_get32(bgep
, NVM_FLASH_CMD_REG
);
1510 if (regval
& NVM_FLASH_CMD_DONE
)
1515 if (regval
& NVM_FLASH_CMD_DONE
) {
1517 * All OK; read the data from the Flash read register
1519 BGE_DEBUG(("bge_flash_access: complete after %d us", tries
));
1520 *dp
= bge_reg_get32(bgep
, NVM_FLASH_READ_REG
);
1525 * Hmm ... what happened here?
1527 * Most likely, the user addressed a non-existent Flash. Or
1528 * maybe the Flash was busy internally (e.g. processing a write)
1529 * and didn't respond to being addressed. Either way, there's
1530 * nothing we can here ...
1532 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries
));
1537 * The next two functions regulate access to the NVram (if fitted).
1539 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1540 * (SPI) interface, but they can be accessed through either port. These
1541 * are managed by different instance of this driver and have no software
1544 * In addition (and even on a single core chip) the chip's internal
1545 * firmware can access the SEEPROM/Flash, most notably after a RESET
1546 * when it may download code to run internally.
1548 * So we need to arbitrate between these various software agents. For
1549 * this purpose, the chip provides the Software Arbitration Register,
1550 * which implements hardware(!) arbitration.
1552 * This functionality didn't exist on older (5700/5701) chips, so there's
1553 * nothing we can do by way of arbitration on those; also, if there's no
1554 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1557 * The internal firmware appears to use Request 0, which is the highest
1558 * priority. So we'd like to use Request 2, leaving one higher and one
1559 * lower for any future developments ... but apparently this doesn't
1560 * always work. So for now, the code uses Request 1 ;-(
1563 #define NVM_READ_REQ NVM_READ_REQ1
1564 #define NVM_RESET_REQ NVM_RESET_REQ1
1565 #define NVM_SET_REQ NVM_SET_REQ1
1567 static void bge_nvmem_relinquish(bge_t
*bgep
);
1568 #pragma no_inline(bge_nvmem_relinquish)
1571 bge_nvmem_relinquish(bge_t
*bgep
)
1573 ASSERT(mutex_owned(bgep
->genlock
));
1575 switch (bgep
->chipid
.nvtype
) {
1576 case BGE_NVTYPE_NONE
:
1577 case BGE_NVTYPE_UNKNOWN
:
1581 case BGE_NVTYPE_SEEPROM
:
1583 * No arbitration performed, no release needed
1587 case BGE_NVTYPE_LEGACY_SEEPROM
:
1588 case BGE_NVTYPE_UNBUFFERED_FLASH
:
1589 case BGE_NVTYPE_BUFFERED_FLASH
:
1595 * Our own request should be present (whether or not granted) ...
1597 (void) bge_reg_get32(bgep
, NVM_SW_ARBITRATION_REG
);
1600 * ... this will make it go away.
1602 bge_reg_put32(bgep
, NVM_SW_ARBITRATION_REG
, NVM_RESET_REQ
);
1603 (void) bge_reg_get32(bgep
, NVM_SW_ARBITRATION_REG
);
1607 * Arbitrate for access to the NVmem, if necessary
1611 * EAGAIN if the device is in use (retryable)
1612 * ENODEV if the NVmem device is missing or otherwise unusable
1614 static int bge_nvmem_acquire(bge_t
*bgep
);
1615 #pragma no_inline(bge_nvmem_acquire)
1618 bge_nvmem_acquire(bge_t
*bgep
)
1623 ASSERT(mutex_owned(bgep
->genlock
));
1625 switch (bgep
->chipid
.nvtype
) {
1626 case BGE_NVTYPE_NONE
:
1627 case BGE_NVTYPE_UNKNOWN
:
1629 * Access denied: no (recognisable) device fitted
1633 case BGE_NVTYPE_SEEPROM
:
1635 * Access granted: no arbitration needed (or possible)
1639 case BGE_NVTYPE_LEGACY_SEEPROM
:
1640 case BGE_NVTYPE_UNBUFFERED_FLASH
:
1641 case BGE_NVTYPE_BUFFERED_FLASH
:
1644 * Access conditional: conduct arbitration protocol
1650 * We're holding the per-port mutex <genlock>, so no-one other
1651 * thread can be attempting to access the NVmem through *this*
1652 * port. But it could be in use by the *other* port (of a 5704),
1653 * or by the chip's internal firmware, so we have to go through
1654 * the full (hardware) arbitration protocol ...
1656 * Note that *because* we're holding <genlock>, the interrupt handler
1657 * won't be able to progress. So we're only willing to spin for a
1658 * fairly short time. Specifically:
1660 * We *must* wait long enough for the hardware to resolve all
1661 * requests and determine the winner. Fortunately, this is
1662 * "almost instantaneous", even as observed by GHz CPUs.
1664 * A successful access by another Solaris thread (via either
1665 * port) typically takes ~20us. So waiting a bit longer than
1666 * that will give a good chance of success, if the other user
1667 * *is* another thread on the other port.
1669 * However, the internal firmware can hold on to the NVmem
1670 * for *much* longer: at least 10 milliseconds just after a
1671 * RESET, and maybe even longer if the NVmem actually contains
1672 * code to download and run on the internal CPUs.
1674 * So, we'll allow 50us; if that's not enough then it's up to the
1675 * caller to retry later (hence the choice of return code EAGAIN).
1677 regval
= bge_reg_get32(bgep
, NVM_SW_ARBITRATION_REG
);
1678 bge_reg_put32(bgep
, NVM_SW_ARBITRATION_REG
, NVM_SET_REQ
);
1680 for (tries
= 0; tries
< 50; ++tries
) {
1681 regval
= bge_reg_get32(bgep
, NVM_SW_ARBITRATION_REG
);
1682 if (regval
& NVM_WON_REQ1
)
1687 if (regval
& NVM_WON_REQ1
) {
1688 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries
));
1693 * Somebody else must be accessing the NVmem, so abandon our
1694 * attempt take control of it. The caller can try again later ...
1696 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries
));
1697 bge_nvmem_relinquish(bgep
);
1702 * This code assumes that the GPIO1 bit has been wired up to the NVmem
1703 * write protect line in such a way that the NVmem is protected when
1704 * GPIO1 is an input, or is an output but driven high. Thus, to make the
1705 * NVmem writable we have to change GPIO1 to an output AND drive it low.
1707 * Note: there's only one set of GPIO pins on a 5704, even though they
1708 * can be accessed through either port. So the chip has to resolve what
1709 * happens if the two ports program a single pin differently ... the rule
1710 * it uses is that if the ports disagree about the *direction* of a pin,
1711 * "output" wins over "input", but if they disagree about its *value* as
1712 * an output, then the pin is TRISTATED instead! In such a case, no-one
1713 * wins, and the external signal does whatever the external circuitry
1714 * defines as the default -- which we've assumed is the PROTECTED state.
1715 * So, we always change GPIO1 back to being an *input* whenever we're not
1716 * specifically using it to unprotect the NVmem. This allows either port
1717 * to update the NVmem, although obviously only one at a time!
1719 * The caller should hold <genlock> and *also* have already acquired the
1720 * right to access the NVmem, via bge_nvmem_acquire() above.
1722 static void bge_nvmem_protect(bge_t
*bgep
, boolean_t protect
);
1723 #pragma inline(bge_nvmem_protect)
1726 bge_nvmem_protect(bge_t
*bgep
, boolean_t protect
)
1730 ASSERT(mutex_owned(bgep
->genlock
));
1732 regval
= bge_reg_get32(bgep
, MISC_LOCAL_CONTROL_REG
);
1734 regval
|= MLCR_MISC_PINS_OUTPUT_1
;
1735 regval
&= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
1737 regval
&= ~MLCR_MISC_PINS_OUTPUT_1
;
1738 regval
|= MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
1740 bge_reg_put32(bgep
, MISC_LOCAL_CONTROL_REG
, regval
);
1744 * Now put it all together ...
1746 * Try to acquire control of the NVmem; if successful, then:
1747 * unprotect it (if we want to write to it)
1748 * perform the requested access
1749 * reprotect it (after a write)
1750 * relinquish control
1754 * EAGAIN if the device is in use (retryable)
1755 * ENODATA on access timeout (maybe retryable: device may just be busy)
1756 * ENODEV if the NVmem device is missing or otherwise unusable
1757 * EPROTO on other h/w or s/w errors.
1760 bge_nvmem_rw32(bge_t
*bgep
, uint32_t cmd
, bge_regno_t addr
, uint32_t *dp
)
1764 if ((err
= bge_nvmem_acquire(bgep
)) == 0) {
1767 err
= bge_seeprom_access(bgep
,
1768 SEEPROM_ACCESS_READ
, addr
, dp
);
1772 bge_nvmem_protect(bgep
, B_FALSE
);
1773 err
= bge_seeprom_access(bgep
,
1774 SEEPROM_ACCESS_WRITE
, addr
, dp
);
1775 bge_nvmem_protect(bgep
, B_TRUE
);
1778 case BGE_FLASH_READ
:
1779 if (DEVICE_5721_SERIES_CHIPSETS(bgep
) ||
1780 DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1781 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1782 DEVICE_5725_SERIES_CHIPSETS(bgep
) ||
1783 DEVICE_5714_SERIES_CHIPSETS(bgep
)) {
1784 bge_reg_set32(bgep
, NVM_ACCESS_REG
,
1787 err
= bge_flash_access(bgep
,
1788 NVM_FLASH_CMD_RD
, addr
, dp
);
1789 if (DEVICE_5721_SERIES_CHIPSETS(bgep
) ||
1790 DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1791 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1792 DEVICE_5725_SERIES_CHIPSETS(bgep
) ||
1793 DEVICE_5714_SERIES_CHIPSETS(bgep
)) {
1794 bge_reg_clr32(bgep
, NVM_ACCESS_REG
,
1799 case BGE_FLASH_WRITE
:
1800 if (DEVICE_5721_SERIES_CHIPSETS(bgep
) ||
1801 DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1802 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1803 DEVICE_5725_SERIES_CHIPSETS(bgep
) ||
1804 DEVICE_5714_SERIES_CHIPSETS(bgep
)) {
1805 bge_reg_set32(bgep
, NVM_ACCESS_REG
,
1806 NVM_WRITE_ENABLE
|NVM_ACCESS_ENABLE
);
1808 bge_nvmem_protect(bgep
, B_FALSE
);
1809 err
= bge_flash_access(bgep
,
1810 NVM_FLASH_CMD_WR
, addr
, dp
);
1811 bge_nvmem_protect(bgep
, B_TRUE
);
1812 if (DEVICE_5721_SERIES_CHIPSETS(bgep
) ||
1813 DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
1814 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
1815 DEVICE_5725_SERIES_CHIPSETS(bgep
) ||
1816 DEVICE_5714_SERIES_CHIPSETS(bgep
)) {
1817 bge_reg_clr32(bgep
, NVM_ACCESS_REG
,
1818 NVM_WRITE_ENABLE
|NVM_ACCESS_ENABLE
);
1827 bge_nvmem_relinquish(bgep
);
1830 BGE_DEBUG(("bge_nvmem_rw32: err %d", err
));
1835 bge_nvmem_access_cmd(bge_t
*bgep
, boolean_t read
)
1837 switch (bgep
->chipid
.nvtype
) {
1838 case BGE_NVTYPE_NONE
:
1839 case BGE_NVTYPE_UNKNOWN
:
1843 case BGE_NVTYPE_SEEPROM
:
1844 case BGE_NVTYPE_LEGACY_SEEPROM
:
1845 return (read
? BGE_SEE_READ
: BGE_SEE_WRITE
);
1847 case BGE_NVTYPE_UNBUFFERED_FLASH
:
1848 case BGE_NVTYPE_BUFFERED_FLASH
:
1849 return (read
? BGE_FLASH_READ
: BGE_FLASH_WRITE
);
1855 bge_nvmem_read32(bge_t
*bgep
, bge_regno_t addr
, uint32_t *dp
)
1857 return (bge_nvmem_rw32(bgep
, bge_nvmem_access_cmd(bgep
, B_TRUE
),
1863 bge_nvmem_write32(bge_t
*bgep
, bge_regno_t addr
, uint32_t *dp
)
1865 return (bge_nvmem_rw32(bgep
, bge_nvmem_access_cmd(bgep
, B_FALSE
),
1871 * Attempt to get a MAC address from the SEEPROM or Flash, if any
1873 static uint64_t bge_get_nvmac(bge_t
*bgep
);
1874 #pragma no_inline(bge_get_nvmac)
1877 bge_get_nvmac(bge_t
*bgep
)
1885 BGE_TRACE(("bge_get_nvmac($%p)",
1888 switch (bgep
->chipid
.nvtype
) {
1889 case BGE_NVTYPE_NONE
:
1890 case BGE_NVTYPE_UNKNOWN
:
1894 case BGE_NVTYPE_SEEPROM
:
1895 case BGE_NVTYPE_LEGACY_SEEPROM
:
1899 case BGE_NVTYPE_UNBUFFERED_FLASH
:
1900 case BGE_NVTYPE_BUFFERED_FLASH
:
1901 cmd
= BGE_FLASH_READ
;
1905 if (DEVICE_5906_SERIES_CHIPSETS(bgep
))
1906 addr
= NVMEM_DATA_MAC_ADDRESS_5906
;
1908 addr
= NVMEM_DATA_MAC_ADDRESS
;
1910 if (bge_nvmem_rw32(bgep
, cmd
, addr
, &mac_high
))
1913 if (bge_nvmem_rw32(bgep
, cmd
, addr
, &mac_low
))
1917 * The Broadcom chip is natively BIG-endian, so that's how the
1918 * MAC address is represented in NVmem. We may need to swap it
1919 * around on a little-endian host ...
1926 mac
= BGE_BSWAP_32(mac_high
);
1928 mac
|= BGE_BSWAP_32(mac_low
);
1929 #endif /* _BIG_ENDIAN */
1934 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1937 * Dummy version for when we're not supporting NVmem access
1939 static uint64_t bge_get_nvmac(bge_t
*bgep
);
1940 #pragma inline(bge_get_nvmac)
1943 bge_get_nvmac(bge_t
*bgep
)
1945 _NOTE(ARGUNUSED(bgep
))
1949 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1952 * Determine the type of NVmem that is (or may be) attached to this chip,
1954 static enum bge_nvmem_type
bge_nvmem_id(bge_t
*bgep
);
1955 #pragma no_inline(bge_nvmem_id)
1957 static enum bge_nvmem_type
1958 bge_nvmem_id(bge_t
*bgep
)
1960 enum bge_nvmem_type nvtype
;
1963 BGE_TRACE(("bge_nvmem_id($%p)",
1966 switch (bgep
->chipid
.device
) {
1969 * We shouldn't get here; it means we don't recognise
1970 * the chip, which means we don't know how to determine
1971 * what sort of NVmem (if any) it has. So we'll say
1972 * NONE, to disable the NVmem access code ...
1974 nvtype
= BGE_NVTYPE_NONE
;
1977 case DEVICE_ID_5700
:
1978 case DEVICE_ID_5700x
:
1979 case DEVICE_ID_5701
:
1981 * These devices support *only* SEEPROMs
1983 nvtype
= BGE_NVTYPE_SEEPROM
;
1986 case DEVICE_ID_5702
:
1987 case DEVICE_ID_5702fe
:
1988 case DEVICE_ID_5703C
:
1989 case DEVICE_ID_5703S
:
1990 case DEVICE_ID_5704C
:
1991 case DEVICE_ID_5704S
:
1992 case DEVICE_ID_5704
:
1993 case DEVICE_ID_5705M
:
1994 case DEVICE_ID_5705C
:
1995 case DEVICE_ID_5705_2
:
1996 case DEVICE_ID_5717
:
1997 case DEVICE_ID_5718
:
1998 case DEVICE_ID_5719
:
1999 case DEVICE_ID_5720
:
2000 case DEVICE_ID_5724
:
2001 case DEVICE_ID_5725
:
2002 case DEVICE_ID_5727
:
2003 case DEVICE_ID_57780
:
2004 case DEVICE_ID_5780
:
2005 case DEVICE_ID_5782
:
2006 case DEVICE_ID_5785
:
2007 case DEVICE_ID_5787
:
2008 case DEVICE_ID_5787M
:
2009 case DEVICE_ID_5788
:
2010 case DEVICE_ID_5789
:
2011 case DEVICE_ID_5751
:
2012 case DEVICE_ID_5751M
:
2013 case DEVICE_ID_5752
:
2014 case DEVICE_ID_5752M
:
2015 case DEVICE_ID_5754
:
2016 case DEVICE_ID_5755
:
2017 case DEVICE_ID_5755M
:
2018 case DEVICE_ID_5756M
:
2019 case DEVICE_ID_5721
:
2020 case DEVICE_ID_5722
:
2021 case DEVICE_ID_5723
:
2022 case DEVICE_ID_5761
:
2023 case DEVICE_ID_5761E
:
2024 case DEVICE_ID_5764
:
2025 case DEVICE_ID_5714C
:
2026 case DEVICE_ID_5714S
:
2027 case DEVICE_ID_5715C
:
2028 case DEVICE_ID_5715S
:
2029 config1
= bge_reg_get32(bgep
, NVM_CONFIG1_REG
);
2030 if (config1
& NVM_CFG1_FLASH_MODE
)
2031 if (config1
& NVM_CFG1_BUFFERED_MODE
)
2032 nvtype
= BGE_NVTYPE_BUFFERED_FLASH
;
2034 nvtype
= BGE_NVTYPE_UNBUFFERED_FLASH
;
2036 nvtype
= BGE_NVTYPE_LEGACY_SEEPROM
;
2038 case DEVICE_ID_5906
:
2039 case DEVICE_ID_5906M
:
2040 nvtype
= BGE_NVTYPE_BUFFERED_FLASH
;
2048 #define BGE_DBG BGE_DBG_APE /* debug flag for this code */
2050 uint32_t bge_ape_get32(bge_t
*bgep
, bge_regno_t regno
);
2051 #pragma inline(bge_ape_get32)
2054 bge_ape_get32(bge_t
*bgep
, bge_regno_t regno
)
2056 BGE_TRACE(("bge_ape_get32($%p, 0x%lx)",
2057 (void *)bgep
, regno
));
2059 return (ddi_get32(bgep
->ape_handle
, APE_ADDR(bgep
, regno
)));
2062 void bge_ape_put32(bge_t
*bgep
, bge_regno_t regno
, uint32_t data
);
2063 #pragma inline(bge_ape_put32)
2066 bge_ape_put32(bge_t
*bgep
, bge_regno_t regno
, uint32_t data
)
2068 BGE_TRACE(("bge_ape_put32($%p, 0x%lx, 0x%x)",
2069 (void *)bgep
, regno
, data
));
2071 ddi_put32(bgep
->ape_handle
, APE_ADDR(bgep
, regno
), data
);
2076 bge_ape_lock_init(bge_t
*bgep
)
2082 BGE_TRACE(("bge_ape_lock_init($%p)", (void *)bgep
));
2084 if (bgep
->chipid
.device
== DEVICE_ID_5761
)
2085 regbase
= BGE_APE_LOCK_GRANT
;
2087 regbase
= BGE_APE_PER_LOCK_GRANT
;
2089 /* Make sure the driver hasn't any stale locks. */
2090 for (i
= BGE_APE_LOCK_PHY0
; i
<= BGE_APE_LOCK_GPIO
; i
++) {
2092 case BGE_APE_LOCK_PHY0
:
2093 case BGE_APE_LOCK_PHY1
:
2094 case BGE_APE_LOCK_PHY2
:
2095 case BGE_APE_LOCK_PHY3
:
2096 bit
= APE_LOCK_GRANT_DRIVER
;
2099 if (!bgep
->pci_func
)
2100 bit
= APE_LOCK_GRANT_DRIVER
;
2102 bit
= 1 << bgep
->pci_func
;
2104 bge_ape_put32(bgep
, regbase
+ 4 * i
, bit
);
2109 bge_ape_lock(bge_t
*bgep
, int locknum
)
2118 BGE_TRACE(("bge_ape_lock($%p, 0x%x)", (void *)bgep
, locknum
));
2120 if (!bgep
->ape_enabled
)
2124 case BGE_APE_LOCK_GPIO
:
2125 if (bgep
->chipid
.device
== DEVICE_ID_5761
)
2127 case BGE_APE_LOCK_GRC
:
2128 case BGE_APE_LOCK_MEM
:
2129 if (!bgep
->pci_func
)
2130 bit
= APE_LOCK_REQ_DRIVER
;
2132 bit
= 1 << bgep
->pci_func
;
2134 case BGE_APE_LOCK_PHY0
:
2135 case BGE_APE_LOCK_PHY1
:
2136 case BGE_APE_LOCK_PHY2
:
2137 case BGE_APE_LOCK_PHY3
:
2138 bit
= APE_LOCK_REQ_DRIVER
;
2144 if (bgep
->chipid
.device
== DEVICE_ID_5761
) {
2145 req
= BGE_APE_LOCK_REQ
;
2146 gnt
= BGE_APE_LOCK_GRANT
;
2148 req
= BGE_APE_PER_LOCK_REQ
;
2149 gnt
= BGE_APE_PER_LOCK_GRANT
;
2154 bge_ape_put32(bgep
, req
+ off
, bit
);
2156 /* Wait for up to 1 millisecond to acquire lock. */
2157 for (i
= 0; i
< 100; i
++) {
2158 status
= bge_ape_get32(bgep
, gnt
+ off
);
2164 if (status
!= bit
) {
2165 /* Revoke the lock request. */
2166 bge_ape_put32(bgep
, gnt
+ off
, bit
);
2174 bge_ape_unlock(bge_t
*bgep
, int locknum
)
2179 BGE_TRACE(("bge_ape_unlock($%p, 0x%x)", (void *)bgep
, locknum
));
2181 if (!bgep
->ape_enabled
)
2185 case BGE_APE_LOCK_GPIO
:
2186 if (bgep
->chipid
.device
== DEVICE_ID_5761
)
2188 case BGE_APE_LOCK_GRC
:
2189 case BGE_APE_LOCK_MEM
:
2190 if (!bgep
->pci_func
)
2191 bit
= APE_LOCK_GRANT_DRIVER
;
2193 bit
= 1 << bgep
->pci_func
;
2195 case BGE_APE_LOCK_PHY0
:
2196 case BGE_APE_LOCK_PHY1
:
2197 case BGE_APE_LOCK_PHY2
:
2198 case BGE_APE_LOCK_PHY3
:
2199 bit
= APE_LOCK_GRANT_DRIVER
;
2205 if (bgep
->chipid
.device
== DEVICE_ID_5761
)
2206 gnt
= BGE_APE_LOCK_GRANT
;
2208 gnt
= BGE_APE_PER_LOCK_GRANT
;
2210 bge_ape_put32(bgep
, gnt
+ 4 * locknum
, bit
);
2213 /* wait for pending event to finish, if successful returns with MEM locked */
2215 bge_ape_event_lock(bge_t
*bgep
, uint32_t timeout_us
)
2219 BGE_TRACE(("bge_ape_event_lock($%p, %d)", (void *)bgep
, timeout_us
));
2221 ASSERT(timeout_us
> 0);
2223 while (timeout_us
) {
2224 if (bge_ape_lock(bgep
, BGE_APE_LOCK_MEM
))
2227 apedata
= bge_ape_get32(bgep
, BGE_APE_EVENT_STATUS
);
2228 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
2231 bge_ape_unlock(bgep
, BGE_APE_LOCK_MEM
);
2234 timeout_us
-= (timeout_us
> 10) ? 10 : timeout_us
;
2237 return (timeout_us
? 0 : -1);
2240 /* wait for pending event to finish, returns non-zero if not finished */
2242 bge_ape_wait_for_event(bge_t
*bgep
, uint32_t timeout_us
)
2247 BGE_TRACE(("bge_ape_wait_for_event($%p, %d)", (void *)bgep
, timeout_us
));
2249 ASSERT(timeout_us
> 0);
2251 for (i
= 0; i
< timeout_us
/ 10; i
++) {
2252 apedata
= bge_ape_get32(bgep
, BGE_APE_EVENT_STATUS
);
2254 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
2260 return (i
== timeout_us
/ 10);
2264 bge_ape_scratchpad_read(bge_t
*bgep
, uint32_t *data
, uint32_t base_off
,
2274 BGE_TRACE(("bge_ape_scratchpad_read($%p, %p, 0x%0x, %d)",
2275 (void *)bgep
, (void*)data
, base_off
, lenToRead
));
2277 if (!bgep
->ape_has_ncsi
)
2280 apedata
= bge_ape_get32(bgep
, BGE_APE_SEG_SIG
);
2281 if (apedata
!= APE_SEG_SIG_MAGIC
)
2284 apedata
= bge_ape_get32(bgep
, BGE_APE_FW_STATUS
);
2285 if (!(apedata
& APE_FW_STATUS_READY
))
2288 bufoff
= (bge_ape_get32(bgep
, BGE_APE_SEG_MSG_BUF_OFF
) +
2289 BGE_APE_SHMEM_BASE
);
2290 msgoff
= bufoff
+ 2 * sizeof(uint32_t);
2291 maxlen
= bge_ape_get32(bgep
, BGE_APE_SEG_MSG_BUF_LEN
);
2294 uint32_t transferLen
;
2296 /* Cap xfer sizes to scratchpad limits. */
2297 transferLen
= (lenToRead
> maxlen
) ? maxlen
: lenToRead
;
2298 lenToRead
-= transferLen
;
2300 apedata
= bge_ape_get32(bgep
, BGE_APE_FW_STATUS
);
2301 if (!(apedata
& APE_FW_STATUS_READY
))
2304 /* Wait for up to 1 millisecond for APE to service previous event. */
2305 err
= bge_ape_event_lock(bgep
, 1000);
2309 apedata
= (APE_EVENT_STATUS_DRIVER_EVNT
|
2310 APE_EVENT_STATUS_SCRTCHPD_READ
|
2311 APE_EVENT_STATUS_EVENT_PENDING
);
2312 bge_ape_put32(bgep
, BGE_APE_EVENT_STATUS
, apedata
);
2314 bge_ape_put32(bgep
, bufoff
, base_off
);
2315 bge_ape_put32(bgep
, bufoff
+ sizeof(uint32_t), transferLen
);
2317 bge_ape_unlock(bgep
, BGE_APE_LOCK_MEM
);
2318 bge_ape_put32(bgep
, BGE_APE_EVENT
, APE_EVENT_1
);
2320 base_off
+= transferLen
;
2322 if (bge_ape_wait_for_event(bgep
, 30000))
2325 for (i
= 0; transferLen
; i
+= 4, transferLen
-= 4) {
2326 uint32_t val
= bge_ape_get32(bgep
, msgoff
+ i
);
2327 memcpy(data
, &val
, sizeof(uint32_t));
2336 bge_ape_scratchpad_write(bge_t
*bgep
, uint32_t dstoff
, uint32_t *data
,
2337 uint32_t lenToWrite
)
2346 BGE_TRACE(("bge_ape_scratchpad_write($%p, %d, %p, %d)",
2347 (void *)bgep
, dstoff
, data
, lenToWrite
));
2349 if (!bgep
->ape_has_ncsi
)
2352 apedata
= bge_ape_get32(bgep
, BGE_APE_SEG_SIG
);
2353 if (apedata
!= APE_SEG_SIG_MAGIC
)
2356 apedata
= bge_ape_get32(bgep
, BGE_APE_FW_STATUS
);
2357 if (!(apedata
& APE_FW_STATUS_READY
))
2360 bufoff
= (bge_ape_get32(bgep
, BGE_APE_SEG_MSG_BUF_OFF
) +
2361 BGE_APE_SHMEM_BASE
);
2362 msgoff
= bufoff
+ 2 * sizeof(uint32_t);
2363 maxlen
= bge_ape_get32(bgep
, BGE_APE_SEG_MSG_BUF_LEN
);
2365 while (lenToWrite
) {
2366 uint32_t transferLen
;
2368 /* Cap xfer sizes to scratchpad limits. */
2369 transferLen
= (lenToWrite
> maxlen
) ? maxlen
: lenToWrite
;
2370 lenToWrite
-= transferLen
;
2372 /* Wait for up to 1 millisecond for
2373 * APE to service previous event.
2375 err
= bge_ape_event_lock(bgep
, 1000);
2379 bge_ape_put32(bgep
, bufoff
, dstoff
);
2380 bge_ape_put32(bgep
, bufoff
+ sizeof(uint32_t), transferLen
);
2383 dstoff
+= transferLen
;
2385 for (i
= 0; transferLen
; i
+= 4, transferLen
-= 4) {
2386 bge_ape_put32(bgep
, apedata
, *data
++);
2387 apedata
+= sizeof(uint32_t);
2390 apedata
= (APE_EVENT_STATUS_DRIVER_EVNT
|
2391 APE_EVENT_STATUS_SCRTCHPD_WRITE
|
2392 APE_EVENT_STATUS_EVENT_PENDING
);
2393 bge_ape_put32(bgep
, BGE_APE_EVENT_STATUS
, apedata
);
2395 bge_ape_unlock(bgep
, BGE_APE_LOCK_MEM
);
2396 bge_ape_put32(bgep
, BGE_APE_EVENT
, APE_EVENT_1
);
2403 bge_ape_send_event(bge_t
*bgep
, uint32_t event
)
2408 BGE_TRACE(("bge_ape_send_event($%p, %d)", (void *)bgep
, event
));
2410 apedata
= bge_ape_get32(bgep
, BGE_APE_SEG_SIG
);
2411 if (apedata
!= APE_SEG_SIG_MAGIC
)
2414 apedata
= bge_ape_get32(bgep
, BGE_APE_FW_STATUS
);
2415 if (!(apedata
& APE_FW_STATUS_READY
))
2418 /* Wait for up to 1 millisecond for APE to service previous event. */
2419 err
= bge_ape_event_lock(bgep
, 1000);
2423 bge_ape_put32(bgep
, BGE_APE_EVENT_STATUS
,
2424 event
| APE_EVENT_STATUS_EVENT_PENDING
);
2426 bge_ape_unlock(bgep
, BGE_APE_LOCK_MEM
);
2427 bge_ape_put32(bgep
, BGE_APE_EVENT
, APE_EVENT_1
);
2433 bge_ape_driver_state_change(bge_t
*bgep
, int mode
)
2438 BGE_TRACE(("bge_ape_driver_state_change($%p, %d)",
2439 (void *)bgep
, mode
));
2441 if (!bgep
->ape_enabled
)
2445 case BGE_INIT_RESET
:
2446 bge_ape_put32(bgep
, BGE_APE_HOST_SEG_SIG
,
2447 APE_HOST_SEG_SIG_MAGIC
);
2448 bge_ape_put32(bgep
, BGE_APE_HOST_SEG_LEN
,
2449 APE_HOST_SEG_LEN_MAGIC
);
2450 apedata
= bge_ape_get32(bgep
, BGE_APE_HOST_INIT_COUNT
);
2451 bge_ape_put32(bgep
, BGE_APE_HOST_INIT_COUNT
, ++apedata
);
2452 bge_ape_put32(bgep
, BGE_APE_HOST_DRIVER_ID
,
2453 APE_HOST_DRIVER_ID_MAGIC(1, 0));
2454 bge_ape_put32(bgep
, BGE_APE_HOST_BEHAVIOR
,
2455 APE_HOST_BEHAV_NO_PHYLOCK
);
2456 bge_ape_put32(bgep
, BGE_APE_HOST_DRVR_STATE
,
2457 BGE_APE_HOST_DRVR_STATE_START
);
2459 event
= APE_EVENT_STATUS_STATE_START
;
2461 case BGE_SHUTDOWN_RESET
:
2462 /* With the interface we are currently using,
2463 * APE does not track driver state. Wiping
2464 * out the HOST SEGMENT SIGNATURE forces
2465 * the APE to assume OS absent status.
2467 bge_ape_put32(bgep
, BGE_APE_HOST_SEG_SIG
, 0x0);
2470 if (WOL supported
) {
2471 bge_ape_put32(bgep
, BGE_APE_HOST_WOL_SPEED
,
2472 BGE_APE_HOST_WOL_SPEED_AUTO
);
2473 apedata
= BGE_APE_HOST_DRVR_STATE_WOL
;
2476 apedata
= BGE_APE_HOST_DRVR_STATE_UNLOAD
;
2478 bge_ape_put32(bgep
, BGE_APE_HOST_DRVR_STATE
, apedata
);
2480 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
2482 case BGE_SUSPEND_RESET
:
2483 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
2489 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
2491 bge_ape_send_event(bgep
, event
);
2495 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */
2498 bge_init_recv_rule(bge_t
*bgep
)
2500 bge_recv_rule_t
*rulep
= bgep
->recv_rules
;
2504 * Initialize receive rule registers.
2505 * Note that rules may persist across each bge_m_start/stop() call.
2507 for (i
= 0; i
< RECV_RULES_NUM_MAX
; i
++, rulep
++) {
2508 bge_reg_put32(bgep
, RECV_RULE_MASK_REG(i
), rulep
->mask_value
);
2509 bge_reg_put32(bgep
, RECV_RULE_CONTROL_REG(i
), rulep
->control
);
2514 * Using the values captured by bge_chip_cfg_init(), and additional probes
2515 * as required, characterise the chip fully: determine the label by which
2516 * to refer to this chip, the correct settings for various registers, and
2517 * of course whether the device and/or subsystem are supported!
2519 int bge_chip_id_init(bge_t
*bgep
);
2520 #pragma no_inline(bge_chip_id_init)
2523 bge_chip_id_init(bge_t
*bgep
)
2525 char buf
[MAXPATHLEN
]; /* any risk of stack overflow? */
2536 cidp
= &bgep
->chipid
;
2539 * Check the PCI device ID to determine the generic chip type and
2540 * select parameters that depend on this.
2542 * Note: because the SPARC platforms in general don't fit the
2543 * SEEPROM 'behind' the chip, the PCI revision ID register reads
2544 * as zero - which is why we use <asic_rev> rather than <revision>
2547 * Note: in general we can't distinguish between the Copper/SerDes
2548 * versions by ID alone, as some Copper devices (e.g. some but not
2549 * all 5703Cs) have the same ID as the SerDes equivalents. So we
2550 * treat them the same here, and the MII code works out the media
2553 cidp
->mbuf_base
= bge_mbuf_pool_base
;
2554 cidp
->mbuf_length
= bge_mbuf_pool_len
;
2555 cidp
->recv_slots
= BGE_RECV_SLOTS_USED
;
2556 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl
;
2557 cidp
->pci_type
= BGE_PCI_X
;
2558 cidp
->statistic_type
= BGE_STAT_BLK
;
2559 cidp
->mbuf_lo_water_rdma
= bge_mbuf_lo_water_rdma
;
2560 cidp
->mbuf_lo_water_rmac
= bge_mbuf_lo_water_rmac
;
2561 cidp
->mbuf_hi_water
= bge_mbuf_hi_water
;
2562 cidp
->rx_ticks_norm
= bge_rx_ticks_norm
;
2563 cidp
->rx_count_norm
= bge_rx_count_norm
;
2564 cidp
->tx_ticks_norm
= bge_tx_ticks_norm
;
2565 cidp
->tx_count_norm
= bge_tx_count_norm
;
2566 cidp
->mask_pci_int
= MHCR_MASK_PCI_INT_OUTPUT
;
2568 if (cidp
->rx_rings
== 0 || cidp
->rx_rings
> BGE_RECV_RINGS_MAX
)
2569 cidp
->rx_rings
= BGE_RECV_RINGS_DEFAULT
;
2570 if (cidp
->tx_rings
== 0 || cidp
->tx_rings
> BGE_SEND_RINGS_MAX
)
2571 cidp
->tx_rings
= BGE_SEND_RINGS_DEFAULT
;
2573 cidp
->msi_enabled
= B_FALSE
;
2575 switch (cidp
->device
) {
2576 case DEVICE_ID_5717
:
2577 case DEVICE_ID_5718
:
2578 case DEVICE_ID_5719
:
2579 case DEVICE_ID_5720
:
2580 case DEVICE_ID_5724
:
2581 case DEVICE_ID_5725
:
2582 case DEVICE_ID_5727
:
2583 if (cidp
->device
== DEVICE_ID_5717
) {
2584 cidp
->chip_label
= 5717;
2585 } else if (cidp
->device
== DEVICE_ID_5718
) {
2586 cidp
->chip_label
= 5718;
2587 } else if (cidp
->device
== DEVICE_ID_5719
) {
2588 cidp
->chip_label
= 5719;
2589 } else if (cidp
->device
== DEVICE_ID_5720
) {
2590 if (pci_config_get16(bgep
->cfg_handle
, PCI_CONF_DEVID
) ==
2591 DEVICE_ID_5717_C0
) {
2592 cidp
->chip_label
= 5717;
2594 cidp
->chip_label
= 5720;
2596 } else if (cidp
->device
== DEVICE_ID_5724
) {
2597 cidp
->chip_label
= 5724;
2598 } else if (cidp
->device
== DEVICE_ID_5725
) {
2599 cidp
->chip_label
= 5725;
2600 } else /* (cidp->device == DEVICE_ID_5727) */ {
2601 cidp
->chip_label
= 5727;
2603 cidp
->msi_enabled
= bge_enable_msi
;
2604 cidp
->bge_dma_rwctrl
= LE_32(PDRWCR_VAR_5717
);
2605 cidp
->pci_type
= BGE_PCI_E
;
2606 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2607 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5717
;
2608 cidp
->mbuf_hi_water
= MBUF_HIWAT_5717
;
2609 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2610 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2611 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2612 cidp
->bge_mlcr_default
= MLCR_DEFAULT_5717
;
2613 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2614 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2615 cidp
->statistic_type
= BGE_STAT_REG
;
2619 case DEVICE_ID_5700
:
2620 case DEVICE_ID_5700x
:
2621 cidp
->chip_label
= 5700;
2622 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2625 case DEVICE_ID_5701
:
2626 cidp
->chip_label
= 5701;
2628 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2631 case DEVICE_ID_5702
:
2632 case DEVICE_ID_5702fe
:
2633 cidp
->chip_label
= 5702;
2635 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2636 cidp
->pci_type
= BGE_PCI
;
2639 case DEVICE_ID_5703C
:
2640 case DEVICE_ID_5703S
:
2641 case DEVICE_ID_5703
:
2643 * Revision A0 of the 5703/5793 had various errata
2644 * that we can't or don't work around, so it's not
2645 * supported, but all later versions are
2647 cidp
->chip_label
= cidp
->subven
== VENDOR_ID_SUN
? 5793 : 5703;
2648 if (bgep
->chipid
.asic_rev
!= MHCR_CHIP_REV_5703_A0
)
2650 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2653 case DEVICE_ID_5704C
:
2654 case DEVICE_ID_5704S
:
2655 case DEVICE_ID_5704
:
2656 cidp
->chip_label
= cidp
->subven
== VENDOR_ID_SUN
? 5794 : 5704;
2657 cidp
->mbuf_base
= bge_mbuf_pool_base_5704
;
2658 cidp
->mbuf_length
= bge_mbuf_pool_len_5704
;
2660 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2663 case DEVICE_ID_5705C
:
2664 case DEVICE_ID_5705M
:
2665 case DEVICE_ID_5705MA3
:
2666 case DEVICE_ID_5705F
:
2667 case DEVICE_ID_5705_2
:
2668 case DEVICE_ID_5754
:
2669 if (cidp
->device
== DEVICE_ID_5754
) {
2670 cidp
->chip_label
= 5754;
2671 cidp
->pci_type
= BGE_PCI_E
;
2673 cidp
->chip_label
= 5705;
2674 cidp
->pci_type
= BGE_PCI
;
2675 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2677 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2678 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2679 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2680 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2681 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2682 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2683 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2684 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2685 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2686 cidp
->statistic_type
= BGE_STAT_REG
;
2690 case DEVICE_ID_5906
:
2691 case DEVICE_ID_5906M
:
2692 cidp
->chip_label
= 5906;
2693 cidp
->pci_type
= BGE_PCI_E
;
2694 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5906
;
2695 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5906
;
2696 cidp
->mbuf_hi_water
= MBUF_HIWAT_5906
;
2697 cidp
->mbuf_base
= bge_mbuf_pool_base
;
2698 cidp
->mbuf_length
= bge_mbuf_pool_len
;
2699 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2700 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2701 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2702 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2703 cidp
->statistic_type
= BGE_STAT_REG
;
2707 case DEVICE_ID_5753
:
2708 cidp
->chip_label
= 5753;
2709 cidp
->pci_type
= BGE_PCI_E
;
2710 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2711 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2712 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2713 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2714 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2715 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2716 cidp
->bge_mlcr_default
|= MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
2717 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2718 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2719 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2720 cidp
->statistic_type
= BGE_STAT_REG
;
2724 case DEVICE_ID_5755
:
2725 case DEVICE_ID_5755M
:
2726 cidp
->chip_label
= 5755;
2727 cidp
->pci_type
= BGE_PCI_E
;
2728 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2729 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2730 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2731 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2732 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2733 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2734 cidp
->bge_mlcr_default
|= MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
2735 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2736 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2737 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2738 if (cidp
->device
== DEVICE_ID_5755M
)
2739 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2740 cidp
->statistic_type
= BGE_STAT_REG
;
2744 case DEVICE_ID_5756M
:
2746 * This is nearly identical to the 5755M.
2747 * (Actually reports the 5755 chip ID.)
2749 cidp
->chip_label
= 5756;
2750 cidp
->pci_type
= BGE_PCI_E
;
2751 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2752 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2753 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2754 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2755 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2756 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2757 cidp
->bge_mlcr_default
|= MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
2758 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2759 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2760 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2761 cidp
->statistic_type
= BGE_STAT_REG
;
2765 case DEVICE_ID_5787
:
2766 case DEVICE_ID_5787M
:
2767 cidp
->chip_label
= 5787;
2768 cidp
->pci_type
= BGE_PCI_E
;
2769 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2770 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2771 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2772 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2773 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2774 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2775 cidp
->bge_mlcr_default
|= MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
2776 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2777 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2778 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2779 cidp
->statistic_type
= BGE_STAT_REG
;
2783 case DEVICE_ID_5723
:
2784 case DEVICE_ID_5761
:
2785 case DEVICE_ID_5761E
:
2786 case DEVICE_ID_57780
:
2787 cidp
->msi_enabled
= bge_enable_msi
;
2789 * We don't use MSI for BCM5764 and BCM5785, as the
2790 * status block may fail to update when the network
2794 case DEVICE_ID_5785
:
2795 case DEVICE_ID_5764
:
2796 if (cidp
->device
== DEVICE_ID_5723
)
2797 cidp
->chip_label
= 5723;
2798 else if (cidp
->device
== DEVICE_ID_5764
)
2799 cidp
->chip_label
= 5764;
2800 else if (cidp
->device
== DEVICE_ID_5785
)
2801 cidp
->chip_label
= 5785;
2802 else if (cidp
->device
== DEVICE_ID_57780
)
2803 cidp
->chip_label
= 57780;
2805 cidp
->chip_label
= 5761;
2806 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl_5721
;
2807 cidp
->pci_type
= BGE_PCI_E
;
2808 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2809 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2810 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2811 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2812 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2813 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2814 cidp
->bge_mlcr_default
|= MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
2815 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2816 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2817 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2818 cidp
->statistic_type
= BGE_STAT_REG
;
2822 /* PCI-X device, identical to 5714 */
2823 case DEVICE_ID_5780
:
2824 cidp
->chip_label
= 5780;
2825 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2826 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2827 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2828 cidp
->mbuf_base
= bge_mbuf_pool_base_5721
;
2829 cidp
->mbuf_length
= bge_mbuf_pool_len_5721
;
2830 cidp
->recv_slots
= BGE_RECV_SLOTS_5721
;
2831 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2832 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2833 cidp
->statistic_type
= BGE_STAT_REG
;
2837 case DEVICE_ID_5782
:
2839 * Apart from the label, we treat this as a 5705(?)
2841 cidp
->chip_label
= 5782;
2842 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2843 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2844 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2845 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2846 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2847 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2848 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2849 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2850 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2851 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2852 cidp
->statistic_type
= BGE_STAT_REG
;
2856 case DEVICE_ID_5788
:
2858 * Apart from the label, we treat this as a 5705(?)
2860 cidp
->chip_label
= 5788;
2861 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2862 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2863 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2864 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2865 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2866 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2867 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2868 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2869 cidp
->statistic_type
= BGE_STAT_REG
;
2870 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2874 case DEVICE_ID_5714C
:
2875 if (cidp
->revision
>= REVISION_ID_5714_A2
)
2876 cidp
->msi_enabled
= bge_enable_msi
;
2878 case DEVICE_ID_5714S
:
2879 cidp
->chip_label
= 5714;
2880 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2881 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2882 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2883 cidp
->mbuf_base
= bge_mbuf_pool_base_5721
;
2884 cidp
->mbuf_length
= bge_mbuf_pool_len_5721
;
2885 cidp
->recv_slots
= BGE_RECV_SLOTS_5721
;
2886 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl_5714
;
2887 cidp
->bge_mlcr_default
= bge_mlcr_default_5714
;
2888 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2889 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2890 cidp
->pci_type
= BGE_PCI_E
;
2891 cidp
->statistic_type
= BGE_STAT_REG
;
2895 case DEVICE_ID_5715C
:
2896 case DEVICE_ID_5715S
:
2897 cidp
->chip_label
= 5715;
2898 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2899 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2900 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2901 cidp
->mbuf_base
= bge_mbuf_pool_base_5721
;
2902 cidp
->mbuf_length
= bge_mbuf_pool_len_5721
;
2903 cidp
->recv_slots
= BGE_RECV_SLOTS_5721
;
2904 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl_5715
;
2905 cidp
->bge_mlcr_default
= bge_mlcr_default_5714
;
2906 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2907 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2908 cidp
->pci_type
= BGE_PCI_E
;
2909 cidp
->statistic_type
= BGE_STAT_REG
;
2910 if (cidp
->revision
>= REVISION_ID_5715_A2
)
2911 cidp
->msi_enabled
= bge_enable_msi
;
2915 case DEVICE_ID_5721
:
2916 cidp
->chip_label
= 5721;
2917 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2918 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2919 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2920 cidp
->mbuf_base
= bge_mbuf_pool_base_5721
;
2921 cidp
->mbuf_length
= bge_mbuf_pool_len_5721
;
2922 cidp
->recv_slots
= BGE_RECV_SLOTS_5721
;
2923 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl_5721
;
2924 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2925 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2926 cidp
->pci_type
= BGE_PCI_E
;
2927 cidp
->statistic_type
= BGE_STAT_REG
;
2928 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2932 case DEVICE_ID_5722
:
2933 cidp
->chip_label
= 5722;
2934 cidp
->pci_type
= BGE_PCI_E
;
2935 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2936 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2937 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2938 cidp
->mbuf_base
= bge_mbuf_pool_base_5705
;
2939 cidp
->mbuf_length
= bge_mbuf_pool_len_5705
;
2940 cidp
->recv_slots
= BGE_RECV_SLOTS_5705
;
2941 cidp
->bge_mlcr_default
|= MLCR_MISC_PINS_OUTPUT_ENABLE_1
;
2942 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2943 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2944 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2945 cidp
->statistic_type
= BGE_STAT_REG
;
2949 case DEVICE_ID_5751
:
2950 case DEVICE_ID_5751M
:
2951 cidp
->chip_label
= 5751;
2952 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2953 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2954 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2955 cidp
->mbuf_base
= bge_mbuf_pool_base_5721
;
2956 cidp
->mbuf_length
= bge_mbuf_pool_len_5721
;
2957 cidp
->recv_slots
= BGE_RECV_SLOTS_5721
;
2958 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl_5721
;
2959 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2960 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2961 cidp
->pci_type
= BGE_PCI_E
;
2962 cidp
->statistic_type
= BGE_STAT_REG
;
2963 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2967 case DEVICE_ID_5752
:
2968 case DEVICE_ID_5752M
:
2969 cidp
->chip_label
= 5752;
2970 cidp
->mbuf_lo_water_rdma
= RDMA_MBUF_LOWAT_5705
;
2971 cidp
->mbuf_lo_water_rmac
= MAC_RX_MBUF_LOWAT_5705
;
2972 cidp
->mbuf_hi_water
= MBUF_HIWAT_5705
;
2973 cidp
->mbuf_base
= bge_mbuf_pool_base_5721
;
2974 cidp
->mbuf_length
= bge_mbuf_pool_len_5721
;
2975 cidp
->recv_slots
= BGE_RECV_SLOTS_5721
;
2976 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl_5721
;
2977 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2978 cidp
->tx_rings
= BGE_SEND_RINGS_MAX_5705
;
2979 cidp
->pci_type
= BGE_PCI_E
;
2980 cidp
->statistic_type
= BGE_STAT_REG
;
2981 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2985 case DEVICE_ID_5789
:
2986 cidp
->chip_label
= 5789;
2987 cidp
->mbuf_base
= bge_mbuf_pool_base_5721
;
2988 cidp
->mbuf_length
= bge_mbuf_pool_len_5721
;
2989 cidp
->recv_slots
= BGE_RECV_SLOTS_5721
;
2990 cidp
->bge_dma_rwctrl
= bge_dma_rwctrl_5721
;
2991 cidp
->rx_rings
= BGE_RECV_RINGS_MAX_5705
;
2992 cidp
->tx_rings
= BGE_RECV_RINGS_MAX_5705
;
2993 cidp
->pci_type
= BGE_PCI_E
;
2994 cidp
->statistic_type
= BGE_STAT_REG
;
2995 cidp
->flags
|= CHIP_FLAG_PARTIAL_CSUM
;
2996 cidp
->flags
|= CHIP_FLAG_NO_JUMBO
;
2997 cidp
->msi_enabled
= B_TRUE
;
3004 * Setup the default jumbo parameter.
3006 cidp
->ethmax_size
= ETHERMAX
;
3007 cidp
->snd_buff_size
= BGE_SEND_BUFF_SIZE_DEFAULT
;
3008 cidp
->std_buf_size
= BGE_STD_BUFF_SIZE
;
3011 * If jumbo is enabled and this kind of chipset supports jumbo feature,
3012 * setup below jumbo specific parameters.
3014 * For BCM5714/5715, there is only one standard receive ring. So the
3015 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
3016 * feature is enabled.
3018 * For the BCM5718 family we hijack the standard receive ring for
3019 * the jumboframe traffic, keeps it simple.
3021 if (!(cidp
->flags
& CHIP_FLAG_NO_JUMBO
) &&
3022 (cidp
->default_mtu
> BGE_DEFAULT_MTU
)) {
3023 if (DEVICE_5714_SERIES_CHIPSETS(bgep
) ||
3024 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
3025 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
3026 cidp
->mbuf_lo_water_rdma
=
3027 RDMA_MBUF_LOWAT_5714_JUMBO
;
3028 cidp
->mbuf_lo_water_rmac
=
3029 MAC_RX_MBUF_LOWAT_5714_JUMBO
;
3030 cidp
->mbuf_hi_water
= MBUF_HIWAT_5714_JUMBO
;
3031 cidp
->jumbo_slots
= 0;
3032 cidp
->std_buf_size
= BGE_JUMBO_BUFF_SIZE
;
3034 cidp
->mbuf_lo_water_rdma
=
3035 RDMA_MBUF_LOWAT_JUMBO
;
3036 cidp
->mbuf_lo_water_rmac
=
3037 MAC_RX_MBUF_LOWAT_JUMBO
;
3038 cidp
->mbuf_hi_water
= MBUF_HIWAT_JUMBO
;
3039 cidp
->jumbo_slots
= BGE_JUMBO_SLOTS_USED
;
3041 cidp
->recv_jumbo_size
= BGE_JUMBO_BUFF_SIZE
;
3042 cidp
->snd_buff_size
= BGE_SEND_BUFF_SIZE_JUMBO
;
3043 cidp
->ethmax_size
= cidp
->default_mtu
+
3044 sizeof (struct ether_header
);
3048 * Identify the NV memory type: SEEPROM or Flash?
3050 cidp
->nvtype
= bge_nvmem_id(bgep
);
3053 * Now check what we've discovered: is this truly a supported
3054 * chip on (the motherboard of) a supported platform?
3056 * Possible problems here:
3057 * 1) it's a completely unheard-of chip
3058 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
3059 * 3) it's a chip we would support if it were on the motherboard
3060 * of a Sun platform, but this one isn't ;-(
3062 if (cidp
->chip_label
== 0)
3064 "Device 'pci%04x,%04x' not recognized (%d?)",
3065 cidp
->vendor
, cidp
->device
, cidp
->device
);
3068 "Device 'pci%04x,%04x' (%d) revision %d not supported",
3069 cidp
->vendor
, cidp
->device
, cidp
->chip_label
,
3072 cidp
->flags
|= CHIP_FLAG_SUPPORTED
;
3074 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) != DDI_FM_OK
)
3081 bge_chip_msi_trig(bge_t
*bgep
)
3085 regval
= bgep
->param_msi_cnt
<<4;
3086 bge_reg_set32(bgep
, HOST_COALESCE_MODE_REG
, regval
);
3087 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval
));
3091 * Various registers that control the chip's internal engines (state
3092 * machines) have a <reset> and <enable> bits (fortunately, in the
3093 * same place in each such register :-).
3095 * To reset the state machine, the <reset> bit must be written with 1;
3096 * it will then read back as 1 while the reset is in progress, but
3097 * self-clear to 0 when the reset completes.
3099 * To enable a state machine, one must set the <enable> bit, which
3100 * will continue to read back as 0 until the state machine is running.
3102 * To disable a state machine, the <enable> bit must be cleared, but
3103 * it will continue to read back as 1 until the state machine actually
3106 * This routine implements polling for completion of a reset, enable
3107 * or disable operation, returning B_TRUE on success (bit reached the
3108 * required state) or B_FALSE on timeout (200*100us == 20ms).
3110 static boolean_t
bge_chip_poll_engine(bge_t
*bgep
, bge_regno_t regno
,
3111 uint32_t mask
, uint32_t val
);
3112 #pragma no_inline(bge_chip_poll_engine)
3115 bge_chip_poll_engine(bge_t
*bgep
, bge_regno_t regno
,
3116 uint32_t mask
, uint32_t val
)
3121 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
3122 (void *)bgep
, regno
, mask
, val
));
3124 for (n
= 200; n
; --n
) {
3125 regval
= bge_reg_get32(bgep
, regno
);
3126 if ((regval
& mask
) == val
)
3131 bge_problem(bgep
, "bge_chip_poll_engine failed: regno = 0x%lx", regno
);
3132 bge_fm_ereport(bgep
, DDI_FM_DEVICE_NO_RESPONSE
);
3137 * Various registers that control the chip's internal engines (state
3138 * machines) have a <reset> bit (fortunately, in the same place in
3139 * each such register :-). To reset the state machine, this bit must
3140 * be written with 1; it will then read back as 1 while the reset is
3141 * in progress, but self-clear to 0 when the reset completes.
3143 * This code sets the bit, then polls for it to read back as zero.
3144 * The return value is B_TRUE on success (reset bit cleared itself),
3145 * or B_FALSE if the state machine didn't recover :(
3147 * NOTE: the Core reset is similar to other resets, except that we
3148 * can't poll for completion, since the Core reset disables memory
3149 * access! So we just have to assume that it will all complete in
3150 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5.
3152 static boolean_t
bge_chip_reset_engine(bge_t
*bgep
, bge_regno_t regno
);
3153 #pragma no_inline(bge_chip_reset_engine)
3156 bge_chip_reset_engine(bge_t
*bgep
, bge_regno_t regno
)
3163 regval
= bge_reg_get32(bgep
, regno
);
3165 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
3166 (void *)bgep
, regno
));
3167 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
3170 regval
|= STATE_MACHINE_RESET_BIT
;
3173 case MISC_CONFIG_REG
:
3175 * BCM5714/5721/5751 pcie chip special case. In order to avoid
3176 * resetting PCIE block and bringing PCIE link down, bit 29
3177 * in the register needs to be set first, and then set it again
3178 * while the reset bit is written.
3179 * See:P500 of 57xx-PG102-RDS.pdf.
3181 if (DEVICE_5705_SERIES_CHIPSETS(bgep
) ||
3182 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
3183 DEVICE_5725_SERIES_CHIPSETS(bgep
) ||
3184 DEVICE_5721_SERIES_CHIPSETS(bgep
) ||
3185 DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
3186 DEVICE_5714_SERIES_CHIPSETS(bgep
) ||
3187 DEVICE_5906_SERIES_CHIPSETS(bgep
)) {
3188 regval
|= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE
;
3189 if (bgep
->chipid
.pci_type
== BGE_PCI_E
) {
3190 if (bgep
->chipid
.asic_rev
==
3191 MHCR_CHIP_REV_5751_A0
||
3192 bgep
->chipid
.asic_rev
==
3193 MHCR_CHIP_REV_5721_A0
||
3194 bgep
->chipid
.asic_rev
==
3195 MHCR_CHIP_REV_5755_A0
) {
3196 val32
= bge_reg_get32(bgep
,
3198 if (val32
== (PHY_PCIE_SCRAM_MODE
|
3199 PHY_PCIE_LTASS_MODE
))
3202 PHY_PCIE_SCRAM_MODE
);
3203 val32
= pci_config_get32
3205 PCI_CONF_BGE_CLKCTL
);
3206 val32
|= CLKCTL_PCIE_A0_FIX
;
3207 pci_config_put32(bgep
->cfg_handle
,
3208 PCI_CONF_BGE_CLKCTL
, val32
);
3210 bge_reg_set32(bgep
, regno
,
3211 MISC_CONFIG_GRC_RESET_DISABLE
);
3212 regval
|= MISC_CONFIG_GRC_RESET_DISABLE
;
3217 * Special case - causes Core reset
3219 * On SPARC v9 we want to ensure that we don't start
3220 * timing until the I/O access has actually reached
3221 * the chip, otherwise we might make the next access
3222 * too early. And we can't just force the write out
3223 * by following it with a read (even to config space)
3224 * because that would cause the fault we're trying
3225 * to avoid. Hence the need for membar_sync() here.
3227 ddi_put32(bgep
->io_handle
, PIO_ADDR(bgep
, regno
), regval
);
3229 * On some platforms,system need about 300us for
3233 if (DEVICE_5906_SERIES_CHIPSETS(bgep
)) {
3234 bge_reg_set32(bgep
, VCPU_STATUS_REG
, VCPU_DRV_RESET
);
3236 bgep
, VCPU_EXT_CTL
, VCPU_EXT_CTL_HALF
);
3239 if (bgep
->chipid
.pci_type
== BGE_PCI_E
) {
3240 /* PCI-E device need more reset time */
3241 drv_usecwait(120000);
3244 * (re)Disable interrupts as the bit can be reset after a
3247 mhcr
= pci_config_get32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
);
3248 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
,
3249 mhcr
| MHCR_MASK_PCI_INT_OUTPUT
);
3251 /* Set PCIE max payload size and clear error status. */
3252 if ((bgep
->chipid
.chip_label
== 5721) ||
3253 (bgep
->chipid
.chip_label
== 5751) ||
3254 (bgep
->chipid
.chip_label
== 5752) ||
3255 (bgep
->chipid
.chip_label
== 5789) ||
3256 (bgep
->chipid
.chip_label
== 5906)) {
3257 pci_config_put16(bgep
->cfg_handle
,
3258 PCI_CONF_DEV_CTRL
, READ_REQ_SIZE_MAX
);
3259 pci_config_put16(bgep
->cfg_handle
,
3260 PCI_CONF_DEV_STUS
, DEVICE_ERROR_STUS
);
3263 if ((bgep
->chipid
.chip_label
== 5723) ||
3264 (bgep
->chipid
.chip_label
== 5761)) {
3265 pci_config_put16(bgep
->cfg_handle
,
3266 PCI_CONF_DEV_CTRL_5723
, READ_REQ_SIZE_MAX
);
3267 pci_config_put16(bgep
->cfg_handle
,
3268 PCI_CONF_DEV_STUS_5723
, DEVICE_ERROR_STUS
);
3271 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
3272 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
3273 val16
= pci_config_get16(bgep
->cfg_handle
,
3274 PCI_CONF_DEV_CTRL_5717
);
3275 val16
&= ~READ_REQ_SIZE_MASK
;
3276 val16
|= READ_REQ_SIZE_2K
;
3277 pci_config_put16(bgep
->cfg_handle
,
3278 PCI_CONF_DEV_CTRL_5717
, val16
);
3286 bge_reg_put32(bgep
, regno
, regval
);
3287 return (bge_chip_poll_engine(bgep
, regno
,
3288 STATE_MACHINE_RESET_BIT
, 0));
3293 * Various registers that control the chip's internal engines (state
3294 * machines) have an <enable> bit (fortunately, in the same place in
3295 * each such register :-). To stop the state machine, this bit must
3296 * be written with 0, then polled to see when the state machine has
3299 * The return value is B_TRUE on success (enable bit cleared), or
3300 * B_FALSE if the state machine didn't stop :(
3302 static boolean_t
bge_chip_disable_engine(bge_t
*bgep
, bge_regno_t regno
,
3304 #pragma no_inline(bge_chip_disable_engine)
3307 bge_chip_disable_engine(bge_t
*bgep
, bge_regno_t regno
, uint32_t morebits
)
3311 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
3312 (void *)bgep
, regno
, morebits
));
3317 * For Schumacher's bugfix CR6490108
3320 #ifdef BGE_NETCONSOLE
3321 if (bgep
->asf_enabled
)
3326 * Not quite like the others; it doesn't
3327 * have an <enable> bit, but instead we
3328 * have to set and then clear all the bits
3330 bge_reg_put32(bgep
, regno
, ~0u);
3332 bge_reg_put32(bgep
, regno
, 0);
3336 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
3340 if ((regno
== RCV_LIST_SELECTOR_MODE_REG
) ||
3341 (regno
== DMA_COMPLETION_MODE_REG
) ||
3342 (regno
== MBUF_CLUSTER_FREE_MODE_REG
) ||
3343 (regno
== BUFFER_MANAGER_MODE_REG
) ||
3344 (regno
== MEMORY_ARBITER_MODE_REG
)) {
3351 regval
= bge_reg_get32(bgep
, regno
);
3352 regval
&= ~STATE_MACHINE_ENABLE_BIT
;
3353 regval
&= ~morebits
;
3354 bge_reg_put32(bgep
, regno
, regval
);
3356 return bge_chip_poll_engine(bgep
, regno
, STATE_MACHINE_ENABLE_BIT
, 0);
3360 * Various registers that control the chip's internal engines (state
3361 * machines) have an <enable> bit (fortunately, in the same place in
3362 * each such register :-). To start the state machine, this bit must
3363 * be written with 1, then polled to see when the state machine has
3366 * The return value is B_TRUE on success (enable bit set), or
3367 * B_FALSE if the state machine didn't start :(
3369 static boolean_t
bge_chip_enable_engine(bge_t
*bgep
, bge_regno_t regno
,
3371 #pragma no_inline(bge_chip_enable_engine)
3374 bge_chip_enable_engine(bge_t
*bgep
, bge_regno_t regno
, uint32_t morebits
)
3378 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
3379 (void *)bgep
, regno
, morebits
));
3384 #ifdef BGE_NETCONSOLE
3385 if (bgep
->asf_enabled
)
3390 * Not quite like the others; it doesn't
3391 * have an <enable> bit, but instead we
3392 * have to set and then clear all the bits
3394 bge_reg_put32(bgep
, regno
, ~0u);
3396 bge_reg_put32(bgep
, regno
, 0);
3400 regval
= bge_reg_get32(bgep
, regno
);
3401 regval
|= STATE_MACHINE_ENABLE_BIT
;
3403 bge_reg_put32(bgep
, regno
, regval
);
3404 return (bge_chip_poll_engine(bgep
, regno
,
3405 STATE_MACHINE_ENABLE_BIT
, STATE_MACHINE_ENABLE_BIT
));
3410 * Reprogram the Ethernet, Transmit, and Receive MAC
3411 * modes to match the param_* variables
3413 void bge_sync_mac_modes(bge_t
*bgep
);
3414 #pragma no_inline(bge_sync_mac_modes)
3417 bge_sync_mac_modes(bge_t
*bgep
)
3422 ASSERT(mutex_owned(bgep
->genlock
));
3425 * Reprogram the Ethernet MAC mode ...
3427 macmode
= regval
= bge_reg_get32(bgep
, ETHERNET_MAC_MODE_REG
);
3428 macmode
&= ~ETHERNET_MODE_LINK_POLARITY
;
3429 macmode
&= ~ETHERNET_MODE_PORTMODE_MASK
;
3430 if ((bgep
->chipid
.flags
& CHIP_FLAG_SERDES
) &&
3431 (bgep
->param_loop_mode
!= BGE_LOOP_INTERNAL_MAC
)) {
3432 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
3433 DEVICE_5725_SERIES_CHIPSETS(bgep
) ||
3434 DEVICE_5714_SERIES_CHIPSETS(bgep
))
3435 macmode
|= ETHERNET_MODE_PORTMODE_GMII
;
3437 macmode
|= ETHERNET_MODE_PORTMODE_TBI
;
3438 } else if (bgep
->param_link_speed
== 10 ||
3439 bgep
->param_link_speed
== 100)
3440 macmode
|= ETHERNET_MODE_PORTMODE_MII
;
3442 macmode
|= ETHERNET_MODE_PORTMODE_GMII
;
3443 if (bgep
->param_link_duplex
== LINK_DUPLEX_HALF
)
3444 macmode
|= ETHERNET_MODE_HALF_DUPLEX
;
3446 macmode
&= ~ETHERNET_MODE_HALF_DUPLEX
;
3447 if (bgep
->param_loop_mode
== BGE_LOOP_INTERNAL_MAC
)
3448 macmode
|= ETHERNET_MODE_MAC_LOOPBACK
;
3450 macmode
&= ~ETHERNET_MODE_MAC_LOOPBACK
;
3451 bge_reg_put32(bgep
, ETHERNET_MAC_MODE_REG
, macmode
);
3452 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
3453 (void *)bgep
, regval
, macmode
));
3456 * ... the Transmit MAC mode ...
3458 macmode
= regval
= bge_reg_get32(bgep
, TRANSMIT_MAC_MODE_REG
);
3459 if (bgep
->param_link_tx_pause
)
3460 macmode
|= TRANSMIT_MODE_FLOW_CONTROL
;
3462 macmode
&= ~TRANSMIT_MODE_FLOW_CONTROL
;
3463 bge_reg_put32(bgep
, TRANSMIT_MAC_MODE_REG
, macmode
);
3464 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
3465 (void *)bgep
, regval
, macmode
));
3468 * ... and the Receive MAC mode
3470 macmode
= regval
= bge_reg_get32(bgep
, RECEIVE_MAC_MODE_REG
);
3471 if (bgep
->param_link_rx_pause
)
3472 macmode
|= RECEIVE_MODE_FLOW_CONTROL
;
3474 macmode
&= ~RECEIVE_MODE_FLOW_CONTROL
;
3475 bge_reg_put32(bgep
, RECEIVE_MAC_MODE_REG
, macmode
);
3476 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
3477 (void *)bgep
, regval
, macmode
));
3480 * For BCM5785, we need to configure the link status in the MI Status
3481 * register with a write command when auto-polling is disabled.
3483 if (bgep
->chipid
.device
== DEVICE_ID_5785
)
3484 if (bgep
->param_link_speed
== 10)
3485 bge_reg_put32(bgep
, MI_STATUS_REG
, MI_STATUS_LINK
3486 | MI_STATUS_10MBPS
);
3488 bge_reg_put32(bgep
, MI_STATUS_REG
, MI_STATUS_LINK
);
3492 * bge_chip_sync() -- program the chip with the unicast MAC address,
3493 * the multicast hash table, the required level of promiscuity, and
3494 * the current loopback mode ...
3497 int bge_chip_sync(bge_t
*bgep
, boolean_t asf_keeplive
);
3499 int bge_chip_sync(bge_t
*bgep
);
3501 #pragma no_inline(bge_chip_sync)
3505 bge_chip_sync(bge_t
*bgep
, boolean_t asf_keeplive
)
3507 bge_chip_sync(bge_t
*bgep
)
3510 void (*opfn
)(bge_t
*bgep
, bge_regno_t reg
, uint32_t bits
);
3515 int retval
= DDI_SUCCESS
;
3517 BGE_TRACE(("bge_chip_sync($%p)",
3520 ASSERT(mutex_owned(bgep
->genlock
));
3531 * If the TX/RX MAC engines are already running, we should stop
3532 * them (and reset the RX engine) before changing the parameters.
3533 * If they're not running, this will have no effect ...
3535 * NOTE: this is currently disabled by default because stopping
3536 * and restarting the Tx engine may cause an outgoing packet in
3537 * transit to be truncated. Also, stopping and restarting the
3538 * Rx engine seems to not work correctly on the 5705. Testing
3539 * has not (yet!) revealed any problems with NOT stopping and
3540 * restarting these engines (and Broadcom say their drivers don't
3541 * do this), but if it is found to cause problems, this variable
3542 * can be patched to re-enable the old behaviour ...
3544 if (bge_stop_start_on_sync
) {
3546 if (!bgep
->asf_enabled
) {
3547 if (!bge_chip_disable_engine(bgep
,
3548 RECEIVE_MAC_MODE_REG
, RECEIVE_MODE_KEEP_VLAN_TAG
))
3549 retval
= DDI_FAILURE
;
3551 if (!bge_chip_disable_engine(bgep
,
3552 RECEIVE_MAC_MODE_REG
, 0))
3553 retval
= DDI_FAILURE
;
3556 if (!bge_chip_disable_engine(bgep
, RECEIVE_MAC_MODE_REG
,
3557 RECEIVE_MODE_KEEP_VLAN_TAG
))
3558 retval
= DDI_FAILURE
;
3560 if (!bge_chip_disable_engine(bgep
, TRANSMIT_MAC_MODE_REG
, 0))
3561 retval
= DDI_FAILURE
;
3562 if (!bge_chip_reset_engine(bgep
, RECEIVE_MAC_MODE_REG
))
3563 retval
= DDI_FAILURE
;
3567 * Reprogram the hashed multicast address table ...
3569 for (i
= 0; i
< BGE_HASH_TABLE_SIZE
/32; ++i
)
3570 bge_reg_put32(bgep
, MAC_HASH_REG(i
), 0);
3572 for (i
= 0; i
< BGE_HASH_TABLE_SIZE
/32; ++i
)
3573 bge_reg_put32(bgep
, MAC_HASH_REG(i
),
3574 bgep
->mcast_hash
[i
] | fill
);
3577 if (!bgep
->asf_enabled
|| !asf_keeplive
) {
3580 * Transform the MAC address(es) from host to chip format, then
3581 * reprogram the transmit random backoff seed and the unicast
3582 * MAC address(es) ...
3584 for (j
= 0; j
< MAC_ADDRESS_REGS_MAX
; j
++) {
3585 for (i
= 0, macaddr
= 0ull;
3586 i
< ETHERADDRL
; ++i
) {
3588 macaddr
|= bgep
->curr_addr
[j
].addr
[i
];
3590 fill
+= (macaddr
>> 16) + (macaddr
& 0xffffffff);
3591 bge_reg_put64(bgep
, MAC_ADDRESS_REG(j
), macaddr
);
3593 BGE_DEBUG(("bge_chip_sync($%p) "
3594 "setting MAC address %012llx",
3595 (void *)bgep
, macaddr
));
3601 * Set random seed of backoff interval
3602 * - Writing zero means no backoff interval
3604 fill
= ((fill
>> 20) + (fill
>> 10) + fill
) & 0x3ff;
3607 bge_reg_put32(bgep
, MAC_TX_RANDOM_BACKOFF_REG
, fill
);
3610 * Set or clear the PROMISCUOUS mode bit
3612 opfn
= promisc
? bge_reg_set32
: bge_reg_clr32
;
3613 (*opfn
)(bgep
, RECEIVE_MAC_MODE_REG
, RECEIVE_MODE_PROMISCUOUS
);
3616 * Sync the rest of the MAC modes too ...
3618 bge_sync_mac_modes(bgep
);
3621 * Restart RX/TX MAC engines if required ...
3623 if (bgep
->bge_chip_state
== BGE_CHIP_RUNNING
) {
3624 if (!bge_chip_enable_engine(bgep
, TRANSMIT_MAC_MODE_REG
, 0))
3625 retval
= DDI_FAILURE
;
3627 if (!bgep
->asf_enabled
) {
3628 if (!bge_chip_enable_engine(bgep
,
3629 RECEIVE_MAC_MODE_REG
, RECEIVE_MODE_KEEP_VLAN_TAG
))
3630 retval
= DDI_FAILURE
;
3632 if (!bge_chip_enable_engine(bgep
,
3633 RECEIVE_MAC_MODE_REG
, 0))
3634 retval
= DDI_FAILURE
;
3637 if (!bge_chip_enable_engine(bgep
, RECEIVE_MAC_MODE_REG
,
3638 RECEIVE_MODE_KEEP_VLAN_TAG
))
3639 retval
= DDI_FAILURE
;
3645 static bge_regno_t quiesce_regs
[] = {
3647 DMA_COMPLETION_MODE_REG
,
3652 void bge_chip_stop_nonblocking(bge_t
*bgep
);
3653 #pragma no_inline(bge_chip_stop_nonblocking)
3656 * This function is called by bge_quiesce(). We
3657 * turn off all the DMA engines here.
3660 bge_chip_stop_nonblocking(bge_t
*bgep
)
3665 * Flag that no more activity may be initiated
3667 bgep
->progress
&= ~PROGRESS_READY
;
3670 while (*rbp
!= BGE_REGNO_NONE
) {
3671 (void) bge_chip_disable_engine(bgep
, *rbp
, 0);
3675 bgep
->bge_chip_state
= BGE_CHIP_STOPPED
;
3680 * bge_chip_stop() -- stop all chip processing
3682 * If the <fault> parameter is B_TRUE, we're stopping the chip because
3683 * we've detected a problem internally; otherwise, this is a normal
3684 * (clean) stop (at user request i.e. the last STREAM has been closed).
3686 void bge_chip_stop(bge_t
*bgep
, boolean_t fault
);
3687 #pragma no_inline(bge_chip_stop)
3690 bge_chip_stop(bge_t
*bgep
, boolean_t fault
)
3694 boolean_t ok
= B_TRUE
;
3696 BGE_TRACE(("bge_chip_stop($%p)",
3699 ASSERT(mutex_owned(bgep
->genlock
));
3701 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
,
3702 (pci_config_get32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
) |
3703 MHCR_MASK_PCI_INT_OUTPUT
));
3705 ok
&= bge_chip_disable_engine(bgep
, RECEIVE_MAC_MODE_REG
, 0);
3706 ok
&= bge_chip_disable_engine(bgep
, RCV_BD_INITIATOR_MODE_REG
, 0);
3707 ok
&= bge_chip_disable_engine(bgep
, RCV_LIST_PLACEMENT_MODE_REG
, 0);
3708 ok
&= bge_chip_disable_engine(bgep
, RCV_LIST_SELECTOR_MODE_REG
, 0);
3709 ok
&= bge_chip_disable_engine(bgep
, RCV_DATA_BD_INITIATOR_MODE_REG
, 0);
3710 ok
&= bge_chip_disable_engine(bgep
, RCV_DATA_COMPLETION_MODE_REG
, 0);
3711 ok
&= bge_chip_disable_engine(bgep
, RCV_BD_COMPLETION_MODE_REG
, 0);
3713 ok
&= bge_chip_disable_engine(bgep
, SEND_BD_SELECTOR_MODE_REG
, 0);
3714 ok
&= bge_chip_disable_engine(bgep
, SEND_BD_INITIATOR_MODE_REG
, 0);
3715 ok
&= bge_chip_disable_engine(bgep
, SEND_DATA_INITIATOR_MODE_REG
, 0);
3716 ok
&= bge_chip_disable_engine(bgep
, READ_DMA_MODE_REG
, 0);
3717 ok
&= bge_chip_disable_engine(bgep
, SEND_DATA_COMPLETION_MODE_REG
, 0);
3718 ok
&= bge_chip_disable_engine(bgep
, DMA_COMPLETION_MODE_REG
, 0);
3719 ok
&= bge_chip_disable_engine(bgep
, SEND_BD_COMPLETION_MODE_REG
, 0);
3720 ok
&= bge_chip_disable_engine(bgep
, TRANSMIT_MAC_MODE_REG
, 0);
3722 bge_reg_clr32(bgep
, ETHERNET_MAC_MODE_REG
, ETHERNET_MODE_ENABLE_TDE
);
3725 ok
&= bge_chip_disable_engine(bgep
, HOST_COALESCE_MODE_REG
, 0);
3726 ok
&= bge_chip_disable_engine(bgep
, WRITE_DMA_MODE_REG
, 0);
3727 ok
&= bge_chip_disable_engine(bgep
, MBUF_CLUSTER_FREE_MODE_REG
, 0);
3728 ok
&= bge_chip_disable_engine(bgep
, FTQ_RESET_REG
, 0);
3729 ok
&= bge_chip_disable_engine(bgep
, BUFFER_MANAGER_MODE_REG
, 0);
3730 ok
&= bge_chip_disable_engine(bgep
, MEMORY_ARBITER_MODE_REG
, 0);
3731 ok
&= bge_chip_disable_engine(bgep
, MEMORY_ARBITER_MODE_REG
, 0);
3734 ddi_fm_service_impact(bgep
->devinfo
, DDI_SERVICE_UNAFFECTED
);
3737 * Finally, disable (all) MAC events & clear the MAC status
3739 bge_reg_put32(bgep
, ETHERNET_MAC_EVENT_ENABLE_REG
, 0);
3740 bge_reg_put32(bgep
, ETHERNET_MAC_STATUS_REG
, ~0);
3743 * if we're stopping the chip because of a detected fault then do
3744 * appropriate actions
3747 if (bgep
->bge_chip_state
!= BGE_CHIP_FAULT
) {
3748 bgep
->bge_chip_state
= BGE_CHIP_FAULT
;
3749 if (!bgep
->manual_reset
)
3750 ddi_fm_service_impact(bgep
->devinfo
,
3752 if (bgep
->bge_dma_error
) {
3754 * need to free buffers in case the fault was
3755 * due to a memory error in a buffer - got to
3756 * do a fair bit of tidying first
3758 if (bgep
->progress
& PROGRESS_KSTATS
) {
3759 bge_fini_kstats(bgep
);
3760 bgep
->progress
&= ~PROGRESS_KSTATS
;
3762 if (bgep
->progress
& PROGRESS_INTR
) {
3763 bge_intr_disable(bgep
);
3764 rw_enter(bgep
->errlock
, RW_WRITER
);
3765 bge_fini_rings(bgep
);
3766 rw_exit(bgep
->errlock
);
3767 bgep
->progress
&= ~PROGRESS_INTR
;
3769 if (bgep
->progress
& PROGRESS_BUFS
) {
3770 bge_free_bufs(bgep
);
3771 bgep
->progress
&= ~PROGRESS_BUFS
;
3773 bgep
->bge_dma_error
= B_FALSE
;
3777 bgep
->bge_chip_state
= BGE_CHIP_STOPPED
;
3781 * Poll for completion of chip's ROM firmware; also, at least on the
3782 * first time through, find and return the hardware MAC address, if any.
3784 static uint64_t bge_poll_firmware(bge_t
*bgep
);
3785 #pragma no_inline(bge_poll_firmware)
3788 bge_poll_firmware(bge_t
*bgep
)
3796 * Step 19: poll for firmware completion (GENCOMM port set
3797 * to the ones complement of T3_MAGIC_NUMBER).
3799 * While we're at it, we also read the MAC address register;
3800 * at some stage the firmware will load this with the
3801 * factory-set value.
3803 * When both the magic number and the MAC address are set,
3804 * we're done; but we impose a time limit of one second
3805 * (1000*1000us) in case the firmware fails in some fashion
3806 * or the SEEPROM that provides that MAC address isn't fitted.
3808 * After the first time through (chip state != INITIAL), we
3809 * don't need the MAC address to be set (we've already got it
3810 * or not, from the first time), so we don't wait for it, but
3811 * we still have to wait for the T3_MAGIC_NUMBER.
3813 * Note: the magic number is only a 32-bit quantity, but the NIC
3814 * memory is 64-bit (and big-endian) internally. Addressing the
3815 * GENCOMM word as "the upper half of a 64-bit quantity" makes
3816 * it work correctly on both big- and little-endian hosts.
3818 if (MHCR_CHIP_ASIC_REV(bgep
) == MHCR_CHIP_ASIC_REV_5906
) {
3819 for (i
= 0; i
< 1000; ++i
) {
3821 val
= bge_reg_get32(bgep
, VCPU_STATUS_REG
);
3822 if (val
& VCPU_INIT_DONE
)
3825 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
3827 mac
= bge_reg_get64(bgep
, MAC_ADDRESS_REG(0));
3829 for (i
= 0; i
< 1000; ++i
) {
3831 gen
= bge_nic_get64(bgep
, NIC_MEM_GENCOMM
) >> 32;
3832 if (i
== 0 && DEVICE_5704_SERIES_CHIPSETS(bgep
))
3833 drv_usecwait(100000);
3834 mac
= bge_reg_get64(bgep
, MAC_ADDRESS_REG(0));
3836 if (!bgep
->asf_enabled
) {
3838 if (gen
!= ~T3_MAGIC_NUMBER
)
3845 if (bgep
->bge_chip_state
!= BGE_CHIP_INITIAL
)
3850 magic
= bge_nic_get64(bgep
, NIC_MEM_GENCOMM
);
3851 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3852 (void *)bgep
, gen
, i
));
3853 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3860 * Maximum times of trying to get the NVRAM access lock
3861 * by calling bge_nvmem_acquire()
3863 #define MAX_TRY_NVMEM_ACQUIRE 10000
3866 int bge_chip_reset(bge_t
*bgep
, boolean_t enable_dma
, uint_t asf_mode
);
3868 int bge_chip_reset(bge_t
*bgep
, boolean_t enable_dma
);
3870 #pragma no_inline(bge_chip_reset)
3874 bge_chip_reset(bge_t
*bgep
, boolean_t enable_dma
, uint_t asf_mode
)
3876 bge_chip_reset(bge_t
*bgep
, boolean_t enable_dma
)
3890 int retval
= DDI_SUCCESS
;
3892 BGE_TRACE(("bge_chip_reset($%p, %d)",
3893 (void *)bgep
, enable_dma
));
3895 ASSERT(mutex_owned(bgep
->genlock
));
3897 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3898 (void *)bgep
, enable_dma
, bgep
->bge_chip_state
));
3901 * Do we need to stop the chip cleanly before resetting?
3903 switch (bgep
->bge_chip_state
) {
3906 return (DDI_FAILURE
);
3908 case BGE_CHIP_INITIAL
:
3909 case BGE_CHIP_STOPPED
:
3910 case BGE_CHIP_RESET
:
3913 case BGE_CHIP_RUNNING
:
3914 case BGE_CHIP_ERROR
:
3915 case BGE_CHIP_FAULT
:
3916 bge_chip_stop(bgep
, B_FALSE
);
3920 mhcr_base
= MHCR_ENABLE_INDIRECT_ACCESS
|
3921 MHCR_ENABLE_PCI_STATE_RW
|
3922 MHCR_ENABLE_TAGGED_STATUS_MODE
|
3923 MHCR_MASK_INTERRUPT_MODE
|
3924 MHCR_MASK_PCI_INT_OUTPUT
|
3925 MHCR_CLEAR_INTERRUPT_INTA
;
3928 if (bgep
->asf_enabled
) {
3931 mhcr
|= (MHCR_ENABLE_ENDIAN_WORD_SWAP
|
3932 MHCR_ENABLE_ENDIAN_BYTE_SWAP
);
3934 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
, mhcr
);
3936 bge_reg_put32(bgep
, MEMORY_ARBITER_MODE_REG
,
3937 bge_reg_get32(bgep
, MEMORY_ARBITER_MODE_REG
) |
3938 MEMORY_ARBITER_ENABLE
);
3940 if (asf_mode
== ASF_MODE_INIT
) {
3941 bge_asf_pre_reset_operations(bgep
, BGE_INIT_RESET
);
3942 } else if (asf_mode
== ASF_MODE_SHUTDOWN
) {
3943 bge_asf_pre_reset_operations(bgep
, BGE_SHUTDOWN_RESET
);
3949 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3950 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3952 * Before reset Core clock,it is
3953 * also required to initialize the Memory Arbiter as specified in step9
3954 * and Misc Host Control Register as specified in step-13
3955 * Step 4-5: reset Core clock & wait for completion
3956 * Steps 6-8: are done by bge_chip_cfg_init()
3957 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3959 if (!bge_chip_enable_engine(bgep
, MEMORY_ARBITER_MODE_REG
, 0))
3960 retval
= DDI_FAILURE
;
3964 mhcr
|= (MHCR_ENABLE_ENDIAN_WORD_SWAP
|
3965 MHCR_ENABLE_ENDIAN_BYTE_SWAP
);
3967 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
, mhcr
);
3970 if (bgep
->asf_enabled
)
3971 bgep
->asf_wordswapped
= B_FALSE
;
3974 * NVRAM Corruption Workaround
3976 for (tries
= 0; tries
< MAX_TRY_NVMEM_ACQUIRE
; tries
++)
3977 if (bge_nvmem_acquire(bgep
) != EAGAIN
)
3979 if (tries
>= MAX_TRY_NVMEM_ACQUIRE
)
3980 BGE_DEBUG(("%s: fail to acquire nvram lock",
3983 bge_ape_lock(bgep
, BGE_APE_LOCK_GRC
);
3986 if (!bgep
->asf_enabled
) {
3988 magic
= (uint64_t)T3_MAGIC_NUMBER
<< 32;
3989 bge_nic_put64(bgep
, NIC_MEM_GENCOMM
, magic
);
3994 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
3995 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
3996 bge_reg_set32(bgep
, FAST_BOOT_PC
, 0);
3997 if (!bge_chip_enable_engine(bgep
, MEMORY_ARBITER_MODE_REG
, 0))
3998 retval
= DDI_FAILURE
;
4003 mhcr
|= (MHCR_ENABLE_ENDIAN_WORD_SWAP
|
4004 MHCR_ENABLE_ENDIAN_BYTE_SWAP
);
4006 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
, mhcr
);
4008 if (!bge_chip_reset_engine(bgep
, MISC_CONFIG_REG
))
4009 retval
= DDI_FAILURE
;
4011 bge_chip_cfg_init(bgep
, &chipid
, enable_dma
);
4014 * Step 8a: This may belong elsewhere, but BCM5721 needs
4015 * a bit set to avoid a fifo overflow/underflow bug.
4017 if ((bgep
->chipid
.chip_label
== 5721) ||
4018 (bgep
->chipid
.chip_label
== 5751) ||
4019 (bgep
->chipid
.chip_label
== 5752) ||
4020 (bgep
->chipid
.chip_label
== 5755) ||
4021 (bgep
->chipid
.chip_label
== 5756) ||
4022 (bgep
->chipid
.chip_label
== 5789) ||
4023 (bgep
->chipid
.chip_label
== 5906))
4024 bge_reg_set32(bgep
, TLP_CONTROL_REG
, TLP_DATA_FIFO_PROTECT
);
4027 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
4030 if (!bge_chip_enable_engine(bgep
, MEMORY_ARBITER_MODE_REG
, 0))
4031 retval
= DDI_FAILURE
;
4034 * Steps 10-11: configure PIO endianness options and
4035 * enable indirect register access -- already done
4036 * Steps 12-13: enable writing to the PCI state & clock
4037 * control registers -- not required; we aren't going to
4038 * use those features.
4039 * Steps 14-15: Configure DMA endianness options. See
4040 * the comments on the setting of the MHCR above.
4042 tmp
= MODE_WORD_SWAP_FRAME
| MODE_BYTE_SWAP_FRAME
;
4044 tmp
|= (MODE_WORD_SWAP_NONFRAME
| MODE_BYTE_SWAP_NONFRAME
);
4047 if (bgep
->asf_enabled
)
4048 tmp
|= MODE_HOST_STACK_UP
;
4050 bge_reg_put32(bgep
, MODE_CONTROL_REG
, tmp
);
4053 if (bgep
->asf_enabled
) {
4055 bge_reg_put32(bgep
, MEMORY_ARBITER_MODE_REG
,
4056 MEMORY_ARBITER_ENABLE
|
4057 bge_reg_get32(bgep
, MEMORY_ARBITER_MODE_REG
));
4060 #ifdef BGE_NETCONSOLE
4061 if (!bgep
->asf_newhandshake
) {
4062 if ((asf_mode
== ASF_MODE_INIT
) ||
4063 (asf_mode
== ASF_MODE_POST_INIT
)) {
4064 bge_asf_post_reset_old_mode(bgep
,
4067 bge_asf_post_reset_old_mode(bgep
,
4068 BGE_SHUTDOWN_RESET
);
4073 /* Wait for NVRAM init */
4076 mailbox
= bge_nic_get32(bgep
, BGE_FIRMWARE_MAILBOX
);
4078 while ((mailbox
!= (uint32_t)
4079 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE
) &&
4082 mailbox
= bge_nic_get32(bgep
,
4083 BGE_FIRMWARE_MAILBOX
);
4087 #ifndef BGE_NETCONSOLE
4088 if (!bgep
->asf_newhandshake
) {
4089 if ((asf_mode
== ASF_MODE_INIT
) ||
4090 (asf_mode
== ASF_MODE_POST_INIT
)) {
4092 bge_asf_post_reset_old_mode(bgep
,
4095 bge_asf_post_reset_old_mode(bgep
,
4096 BGE_SHUTDOWN_RESET
);
4103 bge_ape_unlock(bgep
, BGE_APE_LOCK_GRC
);
4106 * Steps 16-17: poll for firmware completion
4108 mac
= bge_poll_firmware(bgep
);
4110 if (bgep
->chipid
.device
== DEVICE_ID_5720
) {
4111 tmp
= bge_reg_get32(bgep
, CPMU_CLCK_ORIDE_REG
);
4112 bge_reg_put32(bgep
, CPMU_CLCK_ORIDE_REG
,
4113 (tmp
& ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN
));
4117 * Step 18: enable external memory -- doesn't apply.
4119 * However we take the opportunity to set the MLCR anyway, as
4120 * this register also controls the SEEPROM auto-access method
4121 * which we may want to use later ...
4123 * The proper value here depends on the way the chip is wired
4124 * into the circuit board, as this register *also* controls which
4125 * of the "Miscellaneous I/O" pins are driven as outputs and the
4126 * values driven onto those pins!
4128 * See also step 74 in the PRM ...
4130 bge_reg_put32(bgep
, MISC_LOCAL_CONTROL_REG
,
4131 bgep
->chipid
.bge_mlcr_default
);
4133 if ((bgep
->chipid
.flags
& CHIP_FLAG_SERDES
) &&
4134 DEVICE_5714_SERIES_CHIPSETS(bgep
)) {
4135 tmp
= bge_reg_get32(bgep
, SERDES_RX_CONTROL
);
4136 tmp
|= SERDES_RX_CONTROL_SIG_DETECT
;
4137 bge_reg_put32(bgep
, SERDES_RX_CONTROL
, tmp
);
4140 bge_reg_set32(bgep
, SERIAL_EEPROM_ADDRESS_REG
, SEEPROM_ACCESS_INIT
);
4143 * Step 20: clear the Ethernet MAC mode register
4145 if (bgep
->ape_enabled
)
4146 bge_reg_put32(bgep
, ETHERNET_MAC_MODE_REG
,
4147 ETHERNET_MODE_APE_TX_EN
| ETHERNET_MODE_APE_RX_EN
);
4149 bge_reg_put32(bgep
, ETHERNET_MAC_MODE_REG
, 0);
4152 * Step 21: restore cache-line-size, latency timer, and
4153 * subsystem ID registers to their original values (not
4154 * those read into the local structure <chipid>, 'cos
4155 * that was after they were cleared by the RESET).
4157 * Note: the Subsystem Vendor/Device ID registers are not
4158 * directly writable in config space, so we use the shadow
4159 * copy in "Page Zero" of register space to restore them
4160 * both in one go ...
4162 pci_config_put8(bgep
->cfg_handle
, PCI_CONF_CACHE_LINESZ
,
4163 bgep
->chipid
.clsize
);
4164 pci_config_put8(bgep
->cfg_handle
, PCI_CONF_LATENCY_TIMER
,
4165 bgep
->chipid
.latency
);
4166 bge_reg_put32(bgep
, PCI_CONF_SUBVENID
,
4167 (bgep
->chipid
.subdev
<< 16) | bgep
->chipid
.subven
);
4170 * The SEND INDEX registers should be reset to zero by the
4171 * global chip reset; if they're not, there'll be trouble
4174 sx0
= bge_reg_get32(bgep
, NIC_DIAG_SEND_INDEX_REG(0));
4176 BGE_REPORT((bgep
, "SEND INDEX - device didn't RESET"));
4177 bge_fm_ereport(bgep
, DDI_FM_DEVICE_INVAL_STATE
);
4178 retval
= DDI_FAILURE
;
4181 /* Enable MSI code */
4182 if (bgep
->intr_type
== DDI_INTR_TYPE_MSI
)
4183 bge_reg_set32(bgep
, MSI_MODE_REG
,
4184 MSI_PRI_HIGHEST
|MSI_MSI_ENABLE
|MSI_ERROR_ATTENTION
);
4187 * On the first time through, save the factory-set MAC address
4188 * (if any). If bge_poll_firmware() above didn't return one
4189 * (from a chip register) consider looking in the attached NV
4190 * memory device, if any. Once we have it, we save it in both
4191 * register-image (64-bit) and byte-array forms. All-zero and
4192 * all-one addresses are not valid, and we refuse to stash those.
4194 if (bgep
->bge_chip_state
== BGE_CHIP_INITIAL
) {
4196 mac
= bge_get_nvmac(bgep
);
4197 if (mac
!= 0ULL && mac
!= ~0ULL) {
4198 bgep
->chipid
.hw_mac_addr
= mac
;
4199 for (i
= ETHERADDRL
; i
-- != 0; ) {
4200 bgep
->chipid
.vendor_addr
.addr
[i
] = (uchar_t
)mac
;
4203 bgep
->chipid
.vendor_addr
.set
= B_TRUE
;
4208 if (bgep
->asf_enabled
&& bgep
->asf_newhandshake
) {
4209 if (asf_mode
!= ASF_MODE_NONE
) {
4210 if ((asf_mode
== ASF_MODE_INIT
) ||
4211 (asf_mode
== ASF_MODE_POST_INIT
)) {
4213 bge_asf_post_reset_new_mode(bgep
,
4216 bge_asf_post_reset_new_mode(bgep
,
4217 BGE_SHUTDOWN_RESET
);
4224 * Record the new state
4226 bgep
->chip_resets
+= 1;
4227 bgep
->bge_chip_state
= BGE_CHIP_RESET
;
4232 * bge_chip_start() -- start the chip transmitting and/or receiving,
4233 * including enabling interrupts
4235 int bge_chip_start(bge_t
*bgep
, boolean_t reset_phys
);
4236 #pragma no_inline(bge_chip_start)
4239 bge_chip_coalesce_update(bge_t
*bgep
)
4241 bge_reg_put32(bgep
, SEND_COALESCE_MAX_BD_REG
,
4242 bgep
->chipid
.tx_count_norm
);
4243 bge_reg_put32(bgep
, SEND_COALESCE_TICKS_REG
,
4244 bgep
->chipid
.tx_ticks_norm
);
4245 bge_reg_put32(bgep
, RCV_COALESCE_MAX_BD_REG
,
4246 bgep
->chipid
.rx_count_norm
);
4247 bge_reg_put32(bgep
, RCV_COALESCE_TICKS_REG
,
4248 bgep
->chipid
.rx_ticks_norm
);
4252 bge_chip_start(bge_t
*bgep
, boolean_t reset_phys
)
4258 uint32_t stats_mask
;
4259 uint32_t dma_wrprio
;
4264 int retval
= DDI_SUCCESS
;
4267 BGE_TRACE(("bge_chip_start($%p)",
4270 ASSERT(mutex_owned(bgep
->genlock
));
4271 ASSERT(bgep
->bge_chip_state
== BGE_CHIP_RESET
);
4273 /* Initialize EEE, enable MAC control of LPI */
4276 if (bgep
->ape_enabled
) {
4278 * Allow reads and writes to the
4279 * APE register and memory space.
4281 regval
= pci_config_get32(bgep
->cfg_handle
,
4282 PCI_CONF_BGE_PCISTATE
);
4283 regval
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
4284 PCISTATE_ALLOW_APE_SHMEM_WR
| PCISTATE_ALLOW_APE_PSPACE_WR
;
4285 pci_config_put32(bgep
->cfg_handle
,
4286 PCI_CONF_BGE_PCISTATE
, regval
);
4290 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
4291 * The document specifies 95 separate steps to fully
4292 * initialise the chip!!!!
4294 * The reset code above has already got us as far as step
4295 * 21, so we continue with ...
4297 * Step 22: clear the MAC statistics block
4298 * (0x0300-0x0aff in NIC-local memory)
4300 if (bgep
->chipid
.statistic_type
== BGE_STAT_BLK
)
4301 bge_nic_zero(bgep
, NIC_MEM_STATISTICS
,
4302 NIC_MEM_STATISTICS_SIZE
);
4305 * Step 23: clear the status block (in host memory)
4307 DMA_ZERO(bgep
->status_block
);
4310 * Step 24: set DMA read/write control register
4312 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_PDRWCR
,
4313 bgep
->chipid
.bge_dma_rwctrl
);
4316 * Step 25: Configure DMA endianness -- already done (16/17)
4317 * Step 26: Configure Host-Based Send Rings
4318 * Step 27: Indicate Host Stack Up
4320 bge_reg_set32(bgep
, MODE_CONTROL_REG
,
4321 MODE_HOST_SEND_BDS
|
4322 MODE_HOST_STACK_UP
);
4324 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
4325 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
4326 reg
= (CHIP_ASIC_REV(bgep
) == CHIP_ASIC_REV_5762
)
4327 ? RDMA_RSRV_CTRL_REG2
: RDMA_RSRV_CTRL_REG
;
4328 regval
= bge_reg_get32(bgep
, reg
);
4329 if ((bgep
->chipid
.device
== DEVICE_ID_5719
) ||
4330 (bgep
->chipid
.device
== DEVICE_ID_5720
) ||
4331 (CHIP_ASIC_REV(bgep
) == CHIP_ASIC_REV_5762
)) {
4332 regval
&= ~(RDMA_RSRV_CTRL_TXMRGN_MASK
|
4333 RDMA_RSRV_CTRL_FIFO_LWM_MASK
|
4334 RDMA_RSRV_CTRL_FIFO_HWM_MASK
);
4335 regval
|= (RDMA_RSRV_CTRL_TXMRGN_320B
|
4336 RDMA_RSRV_CTRL_FIFO_LWM_1_5K
|
4337 RDMA_RSRV_CTRL_FIFO_HWM_1_5K
);
4339 /* Enable the DMA FIFO Overrun fix. */
4340 bge_reg_put32(bgep
, reg
,
4341 (regval
| RDMA_RSRV_CTRL_FIFO_OFLW_FIX
));
4343 if ((CHIP_ASIC_REV(bgep
) == CHIP_ASIC_REV_5719
) ||
4344 (CHIP_ASIC_REV(bgep
) == CHIP_ASIC_REV_5720
) ||
4345 (CHIP_ASIC_REV(bgep
) == CHIP_ASIC_REV_5762
)) {
4346 reg
= (CHIP_ASIC_REV(bgep
) == CHIP_ASIC_REV_5762
)
4347 ? RDMA_CORR_CTRL_REG2
: RDMA_CORR_CTRL_REG
;
4348 regval
= bge_reg_get32(bgep
, reg
);
4349 bge_reg_put32(bgep
, reg
, (regval
|
4350 RDMA_CORR_CTRL_BLEN_BD_4K
|
4351 RDMA_CORR_CTRL_BLEN_LSO_4K
));
4356 * Step 28: Configure checksum options:
4357 * Solaris supports the hardware default checksum options.
4359 * Workaround for Incorrect pseudo-header checksum calculation.
4361 if (bgep
->chipid
.flags
& CHIP_FLAG_PARTIAL_CSUM
)
4362 bge_reg_set32(bgep
, MODE_CONTROL_REG
,
4363 MODE_SEND_NO_PSEUDO_HDR_CSUM
);
4366 * Step 29: configure Timer Prescaler. The value is always the
4367 * same: the Core Clock frequency in MHz (66), minus 1, shifted
4368 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit
4369 * for the whole chip!
4371 regval
= bge_reg_get32(bgep
, MISC_CONFIG_REG
);
4372 regval
= (regval
& 0xffffff00) | MISC_CONFIG_DEFAULT
;
4373 bge_reg_put32(bgep
, MISC_CONFIG_REG
, regval
);
4375 if (DEVICE_5906_SERIES_CHIPSETS(bgep
)) {
4377 /* put PHY into ready state */
4378 bge_reg_clr32(bgep
, MISC_CONFIG_REG
, MISC_CONFIG_EPHY_IDDQ
);
4379 (void) bge_reg_get32(bgep
, MISC_CONFIG_REG
); /* flush */
4384 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
4386 * If the mbuf_length is specified as 0, we just leave these at
4387 * their hardware defaults, rather than explicitly setting them.
4388 * As the Broadcom HRM,driver better not change the parameters
4389 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
4391 if ((bgep
->chipid
.mbuf_length
!= 0) &&
4392 (DEVICE_5704_SERIES_CHIPSETS(bgep
))) {
4393 bge_reg_put32(bgep
, MBUF_POOL_BASE_REG
,
4394 bgep
->chipid
.mbuf_base
);
4395 bge_reg_put32(bgep
, MBUF_POOL_LENGTH_REG
,
4396 bgep
->chipid
.mbuf_length
);
4397 bge_reg_put32(bgep
, DMAD_POOL_BASE_REG
,
4398 DMAD_POOL_BASE_DEFAULT
);
4399 bge_reg_put32(bgep
, DMAD_POOL_LENGTH_REG
,
4400 DMAD_POOL_LENGTH_DEFAULT
);
4404 * Step 32: configure MAC memory pool watermarks
4406 bge_reg_put32(bgep
, RDMA_MBUF_LOWAT_REG
,
4407 bgep
->chipid
.mbuf_lo_water_rdma
);
4408 bge_reg_put32(bgep
, MAC_RX_MBUF_LOWAT_REG
,
4409 bgep
->chipid
.mbuf_lo_water_rmac
);
4410 bge_reg_put32(bgep
, MBUF_HIWAT_REG
,
4411 bgep
->chipid
.mbuf_hi_water
);
4414 * Step 33: configure DMA resource watermarks
4416 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
4417 bge_reg_put32(bgep
, DMAD_POOL_LOWAT_REG
,
4419 bge_reg_put32(bgep
, DMAD_POOL_HIWAT_REG
,
4422 bge_reg_put32(bgep
, LOWAT_MAX_RECV_FRAMES_REG
, bge_lowat_recv_frames
);
4425 * Steps 34-36: enable buffer manager & internal h/w queues
4427 regval
= STATE_MACHINE_ATTN_ENABLE_BIT
;
4428 if (bgep
->chipid
.device
== DEVICE_ID_5719
)
4429 regval
|= BUFFER_MANAGER_MODE_NO_TX_UNDERRUN
;
4430 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
4431 DEVICE_5725_SERIES_CHIPSETS(bgep
))
4432 regval
|= BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE
;
4433 if (!bge_chip_enable_engine(bgep
, BUFFER_MANAGER_MODE_REG
, regval
))
4434 retval
= DDI_FAILURE
;
4436 if (!bge_chip_enable_engine(bgep
, FTQ_RESET_REG
, 0))
4437 retval
= DDI_FAILURE
;
4440 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
4442 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
4443 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
4444 buff_ring_t
*brp
= &bgep
->buff
[BGE_STD_BUFF_RING
];
4445 bge_reg_put64(bgep
, STD_RCV_BD_RING_RCB_REG
,
4446 brp
->desc
.cookie
.dmac_laddress
);
4447 bge_reg_put32(bgep
, STD_RCV_BD_RING_RCB_REG
+ 8,
4448 (brp
->desc
.nslots
) << 16 | brp
->buf
[0].size
<< 2);
4449 bge_reg_put32(bgep
, STD_RCV_BD_RING_RCB_REG
+ 0xc,
4450 NIC_MEM_SHADOW_BUFF_STD_5717
);
4452 bge_reg_putrcb(bgep
, STD_RCV_BD_RING_RCB_REG
,
4453 &bgep
->buff
[BGE_STD_BUFF_RING
].hw_rcb
);
4455 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
4456 bge_reg_putrcb(bgep
, JUMBO_RCV_BD_RING_RCB_REG
,
4457 &bgep
->buff
[BGE_JUMBO_BUFF_RING
].hw_rcb
);
4458 bge_reg_putrcb(bgep
, MINI_RCV_BD_RING_RCB_REG
,
4459 &bgep
->buff
[BGE_MINI_BUFF_RING
].hw_rcb
);
4463 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
4465 bge_reg_put32(bgep
, STD_RCV_BD_REPLENISH_REG
, bge_replenish_std
);
4466 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
4467 bge_reg_put32(bgep
, JUMBO_RCV_BD_REPLENISH_REG
,
4468 bge_replenish_jumbo
);
4469 bge_reg_put32(bgep
, MINI_RCV_BD_REPLENISH_REG
,
4470 bge_replenish_mini
);
4474 * Steps 41-43: clear Send Ring Producer Indices and initialise
4475 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
4477 if (DEVICE_5704_SERIES_CHIPSETS(bgep
))
4478 maxring
= BGE_SEND_RINGS_MAX
;
4480 maxring
= BGE_SEND_RINGS_MAX_5705
;
4481 for (ring
= 0; ring
< maxring
; ++ring
) {
4482 bge_mbx_put(bgep
, SEND_RING_HOST_INDEX_REG(ring
), 0);
4483 bge_mbx_put(bgep
, SEND_RING_NIC_INDEX_REG(ring
), 0);
4484 bge_nic_putrcb(bgep
, NIC_MEM_SEND_RING(ring
),
4485 &bgep
->send
[ring
].hw_rcb
);
4489 * Steps 44-45: initialise Receive Return Rings
4490 * (0x0200-0x02ff in NIC-local memory)
4492 if (DEVICE_5704_SERIES_CHIPSETS(bgep
))
4493 maxring
= BGE_RECV_RINGS_MAX
;
4495 maxring
= BGE_RECV_RINGS_MAX_5705
;
4496 for (ring
= 0; ring
< maxring
; ++ring
)
4497 bge_nic_putrcb(bgep
, NIC_MEM_RECV_RING(ring
),
4498 &bgep
->recv
[ring
].hw_rcb
);
4501 * Step 46: initialise Receive Buffer (Producer) Ring indexes
4503 bge_mbx_put(bgep
, RECV_STD_PROD_INDEX_REG
, 0);
4504 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
4505 bge_mbx_put(bgep
, RECV_JUMBO_PROD_INDEX_REG
, 0);
4506 bge_mbx_put(bgep
, RECV_MINI_PROD_INDEX_REG
, 0);
4509 * Step 47: configure the MAC unicast address
4510 * Step 48: configure the random backoff seed
4511 * Step 96: set up multicast filters
4514 if (bge_chip_sync(bgep
, B_FALSE
) == DDI_FAILURE
)
4516 if (bge_chip_sync(bgep
) == DDI_FAILURE
)
4518 retval
= DDI_FAILURE
;
4521 * Step 49: configure the MTU
4523 mtu
= bgep
->chipid
.ethmax_size
+ETHERFCSL
+VLAN_TAGSZ
;
4524 bge_reg_put32(bgep
, MAC_RX_MTU_SIZE_REG
, mtu
);
4527 * Step 50: configure the IPG et al
4529 bge_reg_put32(bgep
, MAC_TX_LENGTHS_REG
, MAC_TX_LENGTHS_DEFAULT
);
4532 * Step 51: configure the default Rx Return Ring
4534 bge_reg_put32(bgep
, RCV_RULES_CONFIG_REG
, RCV_RULES_CONFIG_DEFAULT
);
4537 * Steps 52-54: configure Receive List Placement,
4538 * and enable Receive List Placement Statistics
4540 bge_reg_put32(bgep
, RCV_LP_CONFIG_REG
,
4541 RCV_LP_CONFIG(bgep
->chipid
.rx_rings
));
4542 switch (MHCR_CHIP_ASIC_REV(bgep
)) {
4543 case MHCR_CHIP_ASIC_REV_5700
:
4544 case MHCR_CHIP_ASIC_REV_5701
:
4545 case MHCR_CHIP_ASIC_REV_5703
:
4546 case MHCR_CHIP_ASIC_REV_5704
:
4547 bge_reg_put32(bgep
, RCV_LP_STATS_ENABLE_MASK_REG
, ~0);
4549 case MHCR_CHIP_ASIC_REV_5705
:
4552 stats_mask
= bge_reg_get32(bgep
, RCV_LP_STATS_ENABLE_MASK_REG
);
4553 stats_mask
&= ~RCV_LP_STATS_DISABLE_MACTQ
;
4554 bge_reg_put32(bgep
, RCV_LP_STATS_ENABLE_MASK_REG
, stats_mask
);
4557 bge_reg_set32(bgep
, RCV_LP_STATS_CONTROL_REG
, RCV_LP_STATS_ENABLE
);
4559 if (bgep
->chipid
.rx_rings
> 1)
4560 bge_init_recv_rule(bgep
);
4563 * Steps 55-56: enable Send Data Initiator Statistics
4565 bge_reg_put32(bgep
, SEND_INIT_STATS_ENABLE_MASK_REG
, ~0);
4566 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
4567 bge_reg_put32(bgep
, SEND_INIT_STATS_CONTROL_REG
,
4568 SEND_INIT_STATS_ENABLE
| SEND_INIT_STATS_FASTER
);
4570 bge_reg_put32(bgep
, SEND_INIT_STATS_CONTROL_REG
,
4571 SEND_INIT_STATS_ENABLE
);
4574 * Steps 57-58: stop (?) the Host Coalescing Engine
4576 if (!bge_chip_disable_engine(bgep
, HOST_COALESCE_MODE_REG
, ~0))
4577 retval
= DDI_FAILURE
;
4580 * Steps 59-62: initialise Host Coalescing parameters
4582 bge_chip_coalesce_update(bgep
);
4583 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
4584 bge_reg_put32(bgep
, SEND_COALESCE_INT_BD_REG
,
4586 bge_reg_put32(bgep
, SEND_COALESCE_INT_TICKS_REG
,
4588 bge_reg_put32(bgep
, RCV_COALESCE_INT_BD_REG
,
4590 bge_reg_put32(bgep
, RCV_COALESCE_INT_TICKS_REG
,
4595 * Steps 63-64: initialise status block & statistics
4596 * host memory addresses
4597 * The statistic block does not exist in some chipsets
4598 * Step 65: initialise Statistics Coalescing Tick Counter
4600 bge_reg_put64(bgep
, STATUS_BLOCK_HOST_ADDR_REG
,
4601 bgep
->status_block
.cookie
.dmac_laddress
);
4604 * Steps 66-67: initialise status block & statistics
4605 * NIC-local memory addresses
4607 if (DEVICE_5704_SERIES_CHIPSETS(bgep
)) {
4608 bge_reg_put64(bgep
, STATISTICS_HOST_ADDR_REG
,
4609 bgep
->statistics
.cookie
.dmac_laddress
);
4610 bge_reg_put32(bgep
, STATISTICS_TICKS_REG
,
4611 STATISTICS_TICKS_DEFAULT
);
4612 bge_reg_put32(bgep
, STATUS_BLOCK_BASE_ADDR_REG
,
4613 NIC_MEM_STATUS_BLOCK
);
4614 bge_reg_put32(bgep
, STATISTICS_BASE_ADDR_REG
,
4615 NIC_MEM_STATISTICS
);
4619 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
4620 * Completion Engine, the Receive List Placement Engine, and the
4621 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
4625 if (bgep
->chipid
.device
== DEVICE_ID_5719
) {
4626 for (i
= 0; i
< BGE_NUM_RDMA_CHANNELS
; i
++) {
4627 if (bge_reg_get32(bgep
, (BGE_RDMA_LENGTH
+ (i
<< 2))) >
4628 bgep
->chipid
.default_mtu
)
4631 if (i
< BGE_NUM_RDMA_CHANNELS
) {
4632 regval
= bge_reg_get32(bgep
, RDMA_CORR_CTRL_REG
);
4633 regval
|= RDMA_CORR_CTRL_TX_LENGTH_WA
;
4634 bge_reg_put32(bgep
, RDMA_CORR_CTRL_REG
, regval
);
4635 bgep
->rdma_length_bug_on_5719
= B_TRUE
;
4639 if (bgep
->chipid
.tx_rings
<= COALESCE_64_BYTE_RINGS
&&
4640 bgep
->chipid
.rx_rings
<= COALESCE_64_BYTE_RINGS
)
4641 coalmode
= COALESCE_64_BYTE_STATUS
;
4644 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
4645 DEVICE_5725_SERIES_CHIPSETS(bgep
))
4646 coalmode
= COALESCE_CLR_TICKS_RX
;
4647 if (!bge_chip_enable_engine(bgep
, HOST_COALESCE_MODE_REG
, coalmode
))
4648 retval
= DDI_FAILURE
;
4649 if (!bge_chip_enable_engine(bgep
, RCV_BD_COMPLETION_MODE_REG
,
4650 STATE_MACHINE_ATTN_ENABLE_BIT
))
4651 retval
= DDI_FAILURE
;
4652 if (!bge_chip_enable_engine(bgep
, RCV_LIST_PLACEMENT_MODE_REG
, 0))
4653 retval
= DDI_FAILURE
;
4655 if (DEVICE_5704_SERIES_CHIPSETS(bgep
))
4656 if (!bge_chip_enable_engine(bgep
, RCV_LIST_SELECTOR_MODE_REG
,
4657 STATE_MACHINE_ATTN_ENABLE_BIT
))
4658 retval
= DDI_FAILURE
;
4661 * Step 72: Enable MAC DMA engines
4662 * Step 73: Clear & enable MAC statistics
4664 if (bgep
->ape_enabled
) {
4665 /* XXX put32 instead of set32 ? */
4666 bge_reg_put32(bgep
, ETHERNET_MAC_MODE_REG
,
4667 ETHERNET_MODE_APE_TX_EN
| ETHERNET_MODE_APE_RX_EN
);
4669 bge_reg_set32(bgep
, ETHERNET_MAC_MODE_REG
,
4670 ETHERNET_MODE_ENABLE_FHDE
|
4671 ETHERNET_MODE_ENABLE_RDE
|
4672 ETHERNET_MODE_ENABLE_TDE
);
4673 bge_reg_set32(bgep
, ETHERNET_MAC_MODE_REG
,
4674 ETHERNET_MODE_ENABLE_TX_STATS
|
4675 ETHERNET_MODE_ENABLE_RX_STATS
|
4676 ETHERNET_MODE_CLEAR_TX_STATS
|
4677 ETHERNET_MODE_CLEAR_RX_STATS
);
4681 if (bgep
->ape_enabled
) {
4682 /* Write our heartbeat update interval to APE. */
4683 bge_ape_put32(bgep
, BGE_APE_HOST_HEARTBEAT_INT_MS
,
4684 APE_HOST_HEARTBEAT_INT_DISABLE
);
4688 * Step 74: configure the MLCR (Miscellaneous Local Control
4689 * Register); not required, as we set up the MLCR in step 10
4690 * (part of the reset code) above.
4692 * Step 75: clear Interrupt Mailbox 0
4694 bge_mbx_put(bgep
, INTERRUPT_MBOX_0_REG
, 0);
4697 * Steps 76-87: Gentlemen, start your engines ...
4699 * Enable the DMA Completion Engine, the Write DMA Engine,
4700 * the Read DMA Engine, Receive Data Completion Engine,
4701 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
4702 * the Send BD Completion Engine, the Receive BD Initiator Engine,
4703 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
4704 * the Send BD Initiator Engine, and the Send BD Selector Engine.
4706 * Beware exhaust fumes?
4708 if (DEVICE_5704_SERIES_CHIPSETS(bgep
))
4709 if (!bge_chip_enable_engine(bgep
, DMA_COMPLETION_MODE_REG
, 0))
4710 retval
= DDI_FAILURE
;
4711 dma_wrprio
= (bge_dma_wrprio
<< DMA_PRIORITY_SHIFT
) |
4713 /* the 5723 check here covers all newer chip families (OK) */
4714 if ((MHCR_CHIP_ASIC_REV(bgep
) == MHCR_CHIP_ASIC_REV_5755
) ||
4715 (MHCR_CHIP_ASIC_REV(bgep
) == MHCR_CHIP_ASIC_REV_5723
) ||
4716 (MHCR_CHIP_ASIC_REV(bgep
) == MHCR_CHIP_ASIC_REV_5906
)) {
4717 dma_wrprio
|= DMA_STATUS_TAG_FIX_CQ12384
;
4719 if (!bge_chip_enable_engine(bgep
, WRITE_DMA_MODE_REG
,
4721 retval
= DDI_FAILURE
;
4725 if (DEVICE_5723_SERIES_CHIPSETS(bgep
) ||
4726 DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
4727 DEVICE_5725_SERIES_CHIPSETS(bgep
))
4729 if (!bge_chip_enable_engine(bgep
, READ_DMA_MODE_REG
,
4730 (bge_dma_rdprio
<< DMA_PRIORITY_SHIFT
) | ALL_DMA_ATTN_BITS
))
4731 retval
= DDI_FAILURE
;
4735 if (!bge_chip_enable_engine(bgep
, RCV_DATA_COMPLETION_MODE_REG
,
4736 STATE_MACHINE_ATTN_ENABLE_BIT
))
4737 retval
= DDI_FAILURE
;
4738 if (DEVICE_5704_SERIES_CHIPSETS(bgep
))
4739 if (!bge_chip_enable_engine(bgep
,
4740 MBUF_CLUSTER_FREE_MODE_REG
, 0))
4741 retval
= DDI_FAILURE
;
4742 if (!bge_chip_enable_engine(bgep
, SEND_DATA_COMPLETION_MODE_REG
, 0))
4743 retval
= DDI_FAILURE
;
4744 if (!bge_chip_enable_engine(bgep
, SEND_BD_COMPLETION_MODE_REG
,
4745 STATE_MACHINE_ATTN_ENABLE_BIT
))
4746 retval
= DDI_FAILURE
;
4747 if (!bge_chip_enable_engine(bgep
, RCV_BD_INITIATOR_MODE_REG
,
4748 RCV_BD_DISABLED_RING_ATTN
))
4749 retval
= DDI_FAILURE
;
4750 if (!bge_chip_enable_engine(bgep
, RCV_DATA_BD_INITIATOR_MODE_REG
,
4751 RCV_DATA_BD_ILL_RING_ATTN
))
4752 retval
= DDI_FAILURE
;
4753 if (!bge_chip_enable_engine(bgep
, SEND_DATA_INITIATOR_MODE_REG
, 0))
4754 retval
= DDI_FAILURE
;
4755 if (!bge_chip_enable_engine(bgep
, SEND_BD_INITIATOR_MODE_REG
,
4756 STATE_MACHINE_ATTN_ENABLE_BIT
))
4757 retval
= DDI_FAILURE
;
4758 if (!bge_chip_enable_engine(bgep
, SEND_BD_SELECTOR_MODE_REG
,
4759 STATE_MACHINE_ATTN_ENABLE_BIT
))
4760 retval
= DDI_FAILURE
;
4765 * Step 88: download firmware -- doesn't apply
4766 * Steps 89-90: enable Transmit & Receive MAC Engines
4769 if (DEVICE_5717_SERIES_CHIPSETS(bgep
)) {
4770 regval
|= TRANSMIT_MODE_MBUF_LOCKUP_FIX
;
4772 if (!bge_chip_enable_engine(bgep
, TRANSMIT_MAC_MODE_REG
, regval
))
4773 retval
= DDI_FAILURE
;
4778 if (!bgep
->asf_enabled
) {
4779 if (!bge_chip_enable_engine(bgep
, RECEIVE_MAC_MODE_REG
,
4780 RECEIVE_MODE_KEEP_VLAN_TAG
))
4781 retval
= DDI_FAILURE
;
4783 if (!bge_chip_enable_engine(bgep
, RECEIVE_MAC_MODE_REG
, 0))
4784 retval
= DDI_FAILURE
;
4787 if (!bge_chip_enable_engine(bgep
, RECEIVE_MAC_MODE_REG
,
4788 RECEIVE_MODE_KEEP_VLAN_TAG
))
4789 retval
= DDI_FAILURE
;
4795 * Step 91: disable auto-polling of PHY status
4797 bge_reg_put32(bgep
, MI_MODE_REG
, MI_MODE_DEFAULT
);
4800 * Step 92: configure D0 power state (not required)
4801 * Step 93: initialise LED control register ()
4803 ledctl
= LED_CONTROL_DEFAULT
;
4804 switch (bgep
->chipid
.device
) {
4805 case DEVICE_ID_5700
:
4806 case DEVICE_ID_5700x
:
4807 case DEVICE_ID_5701
:
4809 * Switch to 5700 (MAC) mode on these older chips
4811 ledctl
&= ~LED_CONTROL_LED_MODE_MASK
;
4812 ledctl
|= LED_CONTROL_LED_MODE_5700
;
4818 bge_reg_put32(bgep
, ETHERNET_MAC_LED_CONTROL_REG
, ledctl
);
4821 * Step 94: activate link
4823 bge_reg_put32(bgep
, MI_STATUS_REG
, MI_STATUS_LINK
);
4826 * Step 95: set up physical layer (PHY/SerDes)
4827 * restart autoneg (if required)
4831 if (bge_phys_update(bgep
) == DDI_FAILURE
)
4832 retval
= DDI_FAILURE
;
4833 /* forcing a mac link update here */
4834 bge_phys_check(bgep
);
4835 bgep
->link_state
= (bgep
->param_link_up
) ? LINK_STATE_UP
:
4837 bge_sync_mac_modes(bgep
);
4838 mac_link_update(bgep
->mh
, bgep
->link_state
);
4842 * Extra step (DSG): hand over all the Receive Buffers to the chip
4844 for (ring
= 0; ring
< BGE_BUFF_RINGS_USED
; ++ring
)
4845 bge_mbx_put(bgep
, bgep
->buff
[ring
].chip_mbx_reg
,
4846 bgep
->buff
[ring
].rf_next
);
4849 * MSI bits:The least significant MSI 16-bit word.
4850 * ISR will be triggered different.
4852 if (bgep
->intr_type
== DDI_INTR_TYPE_MSI
)
4853 bge_reg_set32(bgep
, HOST_COALESCE_MODE_REG
, 0x70);
4856 * Extra step (DSG): select which interrupts are enabled
4858 * Program the Ethernet MAC engine to signal attention on
4859 * Link Change events, then enable interrupts on MAC, DMA,
4860 * and FLOW attention signals.
4862 bge_reg_set32(bgep
, ETHERNET_MAC_EVENT_ENABLE_REG
,
4863 ETHERNET_EVENT_LINK_INT
|
4864 ETHERNET_STATUS_PCS_ERROR_INT
);
4866 if (bgep
->asf_enabled
) {
4867 bge_reg_set32(bgep
, MODE_CONTROL_REG
,
4868 MODE_INT_ON_FLOW_ATTN
|
4869 MODE_INT_ON_DMA_ATTN
|
4871 MODE_INT_ON_MAC_ATTN
);
4874 bge_reg_set32(bgep
, MODE_CONTROL_REG
,
4875 MODE_INT_ON_FLOW_ATTN
|
4876 MODE_INT_ON_DMA_ATTN
|
4877 MODE_INT_ON_MAC_ATTN
);
4882 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
4883 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
4884 bge_cfg_clr16(bgep
, PCI_CONF_DEV_CTRL_5717
,
4885 DEV_CTRL_NO_SNOOP
| DEV_CTRL_RELAXED
);
4887 mhcr
= pci_config_get32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
);
4888 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MHCR
,
4889 (mhcr
| MHCR_TLP_MINOR_ERR_TOLERANCE
));
4894 * Step 97: enable PCI interrupts!!!
4896 if (bgep
->intr_type
== DDI_INTR_TYPE_FIXED
)
4897 bge_cfg_clr32(bgep
, PCI_CONF_BGE_MHCR
,
4898 bgep
->chipid
.mask_pci_int
);
4903 bgep
->bge_chip_state
= BGE_CHIP_RUNNING
;
4909 * ========== Hardware interrupt handler ==========
4913 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */
4916 * Sync the status block, then atomically clear the specified bits in
4917 * the <flags-and-tag> field of the status block.
4918 * the <flags> word of the status block, returning the value of the
4919 * <tag> and the <flags> before the bits were cleared.
4921 static int bge_status_sync(bge_t
*bgep
, uint64_t bits
, uint64_t *flags
);
4922 #pragma inline(bge_status_sync)
4925 bge_status_sync(bge_t
*bgep
, uint64_t bits
, uint64_t *flags
)
4930 BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
4931 (void *)bgep
, bits
));
4933 ASSERT(bgep
->bge_guard
== BGE_GUARD
);
4935 DMA_SYNC(bgep
->status_block
, DDI_DMA_SYNC_FORKERNEL
);
4936 retval
= bge_check_dma_handle(bgep
, bgep
->status_block
.dma_hdl
);
4937 if (retval
!= DDI_FM_OK
)
4940 bsp
= DMA_VPTR(bgep
->status_block
);
4941 *flags
= bge_atomic_clr64(&bsp
->flags_n_tag
, bits
);
4943 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
4944 (void *)bgep
, bits
, *flags
));
4949 void bge_wake_factotum(bge_t
*bgep
);
4950 #pragma inline(bge_wake_factotum)
4953 bge_wake_factotum(bge_t
*bgep
)
4955 mutex_enter(bgep
->softintrlock
);
4956 if (bgep
->factotum_flag
== 0) {
4957 bgep
->factotum_flag
= 1;
4958 ddi_trigger_softintr(bgep
->factotum_id
);
4960 mutex_exit(bgep
->softintrlock
);
4964 bge_intr_error_handler(bge_t
*bgep
)
4976 ASSERT(mutex_owned(bgep
->genlock
));
4979 * Read all the registers that show the possible
4980 * reasons for the ERROR bit to be asserted
4982 flow
= bge_reg_get32(bgep
, FLOW_ATTN_REG
);
4983 rdma
= bge_reg_get32(bgep
, READ_DMA_STATUS_REG
);
4984 wdma
= bge_reg_get32(bgep
, WRITE_DMA_STATUS_REG
);
4985 tmac
= bge_reg_get32(bgep
, TRANSMIT_MAC_STATUS_REG
);
4986 rmac
= bge_reg_get32(bgep
, RECEIVE_MAC_STATUS_REG
);
4987 rxrs
= bge_reg_get32(bgep
, RX_RISC_STATE_REG
);
4988 emac
= bge_reg_get32(bgep
, ETHERNET_MAC_STATUS_REG
);
4989 msis
= bge_reg_get32(bgep
, MSI_STATUS_REG
);
4990 if (DEVICE_5704_SERIES_CHIPSETS(bgep
))
4991 txrs
= bge_reg_get32(bgep
, TX_RISC_STATE_REG
);
4993 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x emac 0x%x msis 0x%x",
4994 (void *)bgep
, flow
, rdma
, wdma
, emac
, msis
));
4995 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4996 (void *)bgep
, tmac
, rmac
, rxrs
, txrs
));
4999 * For now, just clear all the errors ...
5001 if (DEVICE_5704_SERIES_CHIPSETS(bgep
))
5002 bge_reg_put32(bgep
, TX_RISC_STATE_REG
, ~0);
5003 bge_reg_put32(bgep
, RX_RISC_STATE_REG
, ~0);
5004 bge_reg_put32(bgep
, RECEIVE_MAC_STATUS_REG
, ~0);
5005 bge_reg_put32(bgep
, WRITE_DMA_STATUS_REG
, ~0);
5006 bge_reg_put32(bgep
, READ_DMA_STATUS_REG
, ~0);
5007 bge_reg_put32(bgep
, FLOW_ATTN_REG
, ~0);
5011 * bge_intr() -- handle chip interrupts
5013 uint_t
bge_intr(caddr_t arg1
, caddr_t arg2
);
5014 #pragma no_inline(bge_intr)
5017 bge_intr(caddr_t arg1
, caddr_t arg2
)
5019 bge_t
*bgep
= (void *)arg1
; /* private device info */
5024 int retval
, loop_cnt
= 0;
5026 BGE_TRACE(("bge_intr($%p) ($%p)", arg1
, arg2
));
5029 * GLD v2 checks that s/w setup is complete before passing
5030 * interrupts to this routine, thus eliminating the old
5031 * (and well-known) race condition around ddi_add_intr()
5033 ASSERT(bgep
->progress
& PROGRESS_HWINT
);
5035 result
= DDI_INTR_UNCLAIMED
;
5036 mutex_enter(bgep
->genlock
);
5038 if (bgep
->intr_type
== DDI_INTR_TYPE_FIXED
) {
5040 * Check whether chip's says it's asserting #INTA;
5041 * if not, don't process or claim the interrupt.
5043 * Note that the PCI signal is active low, so the
5044 * bit is *zero* when the interrupt is asserted.
5046 regval
= bge_reg_get32(bgep
, MISC_LOCAL_CONTROL_REG
);
5047 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
5048 DEVICE_5725_SERIES_CHIPSETS(bgep
)) &&
5049 (regval
& MLCR_INTA_STATE
)) {
5050 if (bge_check_acc_handle(bgep
, bgep
->io_handle
)
5053 mutex_exit(bgep
->genlock
);
5058 * Block further PCI interrupts ...
5060 bge_reg_set32(bgep
, PCI_CONF_BGE_MHCR
,
5061 bgep
->chipid
.mask_pci_int
);
5067 regval
= bge_reg_get32(bgep
, MSI_STATUS_REG
);
5068 if (regval
& MSI_ERROR_ATTENTION
) {
5069 BGE_REPORT((bgep
, "msi error attention,"
5070 " status=0x%x", regval
));
5071 bge_reg_put32(bgep
, MSI_STATUS_REG
, regval
);
5075 result
= DDI_INTR_CLAIMED
;
5077 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1
, arg2
, regval
));
5080 * Sync the status block and grab the flags-n-tag from it.
5081 * We count the number of interrupts where there doesn't
5082 * seem to have been a DMA update of the status block; if
5083 * it *has* been updated, the counter will be cleared in
5084 * the while() loop below ...
5086 bgep
->missed_dmas
+= 1;
5087 bsp
= DMA_VPTR(bgep
->status_block
);
5088 for (loop_cnt
= 0; loop_cnt
< bge_intr_max_loop
; loop_cnt
++) {
5089 if (bgep
->bge_chip_state
!= BGE_CHIP_RUNNING
) {
5091 * bge_chip_stop() may have freed dma area etc
5092 * while we were in this interrupt handler -
5093 * better not call bge_status_sync()
5095 (void) bge_check_acc_handle(bgep
,
5097 mutex_exit(bgep
->genlock
);
5098 return (DDI_INTR_CLAIMED
);
5101 retval
= bge_status_sync(bgep
, STATUS_FLAG_UPDATED
|
5102 STATUS_FLAG_LINK_CHANGED
| STATUS_FLAG_ERROR
, &flags
);
5103 if (retval
!= DDI_FM_OK
) {
5104 bgep
->bge_dma_error
= B_TRUE
;
5108 if (!(flags
& STATUS_FLAG_UPDATED
))
5112 * Tell the chip that we're processing the interrupt
5114 bge_mbx_put(bgep
, INTERRUPT_MBOX_0_REG
,
5115 INTERRUPT_MBOX_DISABLE(flags
));
5116 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) !=
5120 if (flags
& STATUS_FLAG_LINK_CHANGED
) {
5121 BGE_DEBUG(("bge_intr($%p) ($%p) link event", arg1
, arg2
));
5122 if (bge_phys_check(bgep
)) {
5123 bgep
->link_state
= bgep
->param_link_up
?
5124 LINK_STATE_UP
: LINK_STATE_DOWN
;
5125 bge_sync_mac_modes(bgep
);
5126 mac_link_update(bgep
->mh
, bgep
->link_state
);
5129 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) !=
5134 if (flags
& STATUS_FLAG_ERROR
) {
5135 bge_intr_error_handler(bgep
);
5137 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) !=
5143 * Drop the mutex while we:
5144 * Receive any newly-arrived packets
5145 * Recycle any newly-finished send buffers
5147 bgep
->bge_intr_running
= B_TRUE
;
5148 mutex_exit(bgep
->genlock
);
5149 bge_receive(bgep
, bsp
);
5150 (void) bge_recycle(bgep
, bsp
);
5151 mutex_enter(bgep
->genlock
);
5152 bgep
->bge_intr_running
= B_FALSE
;
5155 * Tell the chip we've finished processing, and
5156 * give it the tag that we got from the status
5157 * block earlier, so that it knows just how far
5158 * we've gone. If it's got more for us to do,
5159 * it will now update the status block and try
5160 * to assert an interrupt (but we've got the
5161 * #INTA blocked at present). If we see the
5162 * update, we'll loop around to do some more.
5163 * Eventually we'll get out of here ...
5165 bge_mbx_put(bgep
, INTERRUPT_MBOX_0_REG
,
5166 INTERRUPT_MBOX_ENABLE(flags
));
5167 if (bgep
->chipid
.pci_type
== BGE_PCI_E
)
5168 (void) bge_mbx_get(bgep
, INTERRUPT_MBOX_0_REG
);
5169 bgep
->missed_dmas
= 0;
5172 if (bgep
->missed_dmas
) {
5174 * Probably due to the internal status tag not
5175 * being reset. Force a status block update now;
5176 * this should ensure that we get an update and
5177 * a new interrupt. After that, we should be in
5180 BGE_REPORT((bgep
, "interrupt: flags 0x%llx - "
5181 "not updated?", flags
));
5182 bgep
->missed_updates
++;
5183 bge_reg_set32(bgep
, HOST_COALESCE_MODE_REG
,
5186 if (bgep
->missed_dmas
>= bge_dma_miss_limit
) {
5188 * If this happens multiple times in a row,
5189 * it means DMA is just not working. Maybe
5190 * the chip's failed, or maybe there's a
5191 * problem on the PCI bus or in the host-PCI
5192 * bridge (Tomatillo).
5194 * At all events, we want to stop further
5195 * interrupts and let the recovery code take
5196 * over to see whether anything can be done
5199 bge_fm_ereport(bgep
,
5200 DDI_FM_DEVICE_BADINT_LIMIT
);
5206 * Reenable assertion of #INTA, unless there's a DMA fault
5208 if (bgep
->intr_type
== DDI_INTR_TYPE_FIXED
) {
5209 bge_reg_clr32(bgep
, PCI_CONF_BGE_MHCR
,
5210 bgep
->chipid
.mask_pci_int
);
5211 if (bge_check_acc_handle(bgep
, bgep
->cfg_handle
) !=
5216 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) != DDI_FM_OK
)
5219 mutex_exit(bgep
->genlock
);
5225 if (bgep
->asf_enabled
&& bgep
->asf_status
== ASF_STAT_RUN
) {
5227 * We must stop ASF heart beat before
5228 * bge_chip_stop(), otherwise some
5229 * computers (ex. IBM HS20 blade
5230 * server) may crash.
5232 bge_asf_update_status(bgep
);
5233 bge_asf_stop_timer(bgep
);
5234 bgep
->asf_status
= ASF_STAT_STOP
;
5236 bge_asf_pre_reset_operations(bgep
, BGE_INIT_RESET
);
5237 (void) bge_check_acc_handle(bgep
, bgep
->cfg_handle
);
5240 bge_chip_stop(bgep
, B_TRUE
);
5241 (void) bge_check_acc_handle(bgep
, bgep
->io_handle
);
5242 mutex_exit(bgep
->genlock
);
5247 * ========== Factotum, implemented as a softint handler ==========
5251 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */
5254 * Factotum routine to check for Tx stall, using the 'watchdog' counter
5256 static boolean_t
bge_factotum_stall_check(bge_t
*bgep
);
5257 #pragma no_inline(bge_factotum_stall_check)
5260 bge_factotum_stall_check(bge_t
*bgep
)
5264 uint64_t now
= gethrtime();
5266 if ((now
- bgep
->timestamp
) < BGE_CYCLIC_PERIOD
)
5269 bgep
->timestamp
= now
;
5271 ASSERT(mutex_owned(bgep
->genlock
));
5274 * Specific check for Tx stall ...
5276 * The 'watchdog' counter is incremented whenever a packet
5277 * is queued, reset to 1 when some (but not all) buffers
5278 * are reclaimed, reset to 0 (disabled) when all buffers
5279 * are reclaimed, and shifted left here. If it exceeds the
5280 * threshold value, the chip is assumed to have stalled and
5281 * is put into the ERROR state. The factotum will then reset
5282 * it on the next pass.
5284 * All of which should ensure that we don't get into a state
5285 * where packets are left pending indefinitely!
5287 dogval
= bge_atomic_shl32(&bgep
->watchdog
, 1);
5288 bsp
= DMA_VPTR(bgep
->status_block
);
5289 if (dogval
< bge_watchdog_count
|| bge_recycle(bgep
, bsp
))
5292 #if !defined(BGE_NETCONSOLE)
5293 BGE_REPORT((bgep
, "Tx stall detected, watchdog code 0x%x", dogval
));
5295 bge_fm_ereport(bgep
, DDI_FM_DEVICE_STALL
);
5300 * The factotum is woken up when there's something to do that we'd rather
5301 * not do from inside a hardware interrupt handler or high-level cyclic.
5302 * Its main task is to reset & restart the chip after an error.
5304 uint_t
bge_chip_factotum(caddr_t arg
);
5305 #pragma no_inline(bge_chip_factotum)
5308 bge_chip_factotum(caddr_t arg
)
5317 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep
));
5319 mutex_enter(bgep
->softintrlock
);
5320 if (bgep
->factotum_flag
== 0) {
5321 mutex_exit(bgep
->softintrlock
);
5322 return (DDI_INTR_UNCLAIMED
);
5324 bgep
->factotum_flag
= 0;
5325 mutex_exit(bgep
->softintrlock
);
5327 result
= DDI_INTR_CLAIMED
;
5330 mutex_enter(bgep
->genlock
);
5331 switch (bgep
->bge_chip_state
) {
5335 case BGE_CHIP_RUNNING
:
5337 if (bgep
->chipid
.device
== DEVICE_ID_5700
) {
5338 if (bge_phys_check(bgep
)) {
5339 bgep
->link_state
= (bgep
->param_link_up
) ?
5340 LINK_STATE_UP
: LINK_STATE_DOWN
;
5341 bge_sync_mac_modes(bgep
);
5342 mac_link_update(bgep
->mh
, bgep
->link_state
);
5346 error
= bge_factotum_stall_check(bgep
);
5347 if (dma_state
!= DDI_FM_OK
) {
5348 bgep
->bge_dma_error
= B_TRUE
;
5351 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) != DDI_FM_OK
)
5354 bgep
->bge_chip_state
= BGE_CHIP_ERROR
;
5357 case BGE_CHIP_ERROR
:
5361 case BGE_CHIP_FAULT
:
5363 * Fault detected, time to reset ...
5365 if (bge_autorecover
) {
5366 if (!(bgep
->progress
& PROGRESS_BUFS
)) {
5368 * if we can't allocate the ring buffers,
5371 if (bge_alloc_bufs(bgep
) != DDI_SUCCESS
) {
5372 mutex_exit(bgep
->genlock
);
5375 bgep
->progress
|= PROGRESS_BUFS
;
5377 if (!(bgep
->progress
& PROGRESS_INTR
)) {
5378 bge_init_rings(bgep
);
5379 bge_intr_enable(bgep
);
5380 bgep
->progress
|= PROGRESS_INTR
;
5382 if (!(bgep
->progress
& PROGRESS_KSTATS
)) {
5383 bge_init_kstats(bgep
,
5384 ddi_get_instance(bgep
->devinfo
));
5385 bgep
->progress
|= PROGRESS_KSTATS
;
5388 BGE_REPORT((bgep
, "automatic recovery activated"));
5390 if (bge_restart(bgep
, B_FALSE
) != DDI_SUCCESS
) {
5391 bgep
->bge_chip_state
= BGE_CHIP_ERROR
;
5394 if (bge_check_acc_handle(bgep
, bgep
->cfg_handle
) !=
5396 bgep
->bge_chip_state
= BGE_CHIP_ERROR
;
5399 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) !=
5401 bgep
->bge_chip_state
= BGE_CHIP_ERROR
;
5404 if (error
== B_FALSE
) {
5406 if (bgep
->asf_enabled
&&
5407 bgep
->asf_status
!= ASF_STAT_RUN
) {
5408 bgep
->asf_timeout_id
= timeout(
5409 bge_asf_heartbeat
, (void *)bgep
,
5411 BGE_ASF_HEARTBEAT_INTERVAL
));
5412 bgep
->asf_status
= ASF_STAT_RUN
;
5415 if (!bgep
->manual_reset
) {
5416 ddi_fm_service_impact(bgep
->devinfo
,
5417 DDI_SERVICE_RESTORED
);
5425 * If an error is detected, stop the chip now, marking it as
5426 * faulty, so that it will be reset next time through ...
5428 * Note that if intr_running is set, then bge_intr() has dropped
5429 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
5430 * this point so have to wait until the next time the factotum runs.
5432 if (error
&& !bgep
->bge_intr_running
) {
5434 if (bgep
->asf_enabled
&& (bgep
->asf_status
== ASF_STAT_RUN
)) {
5436 * We must stop ASF heart beat before bge_chip_stop(),
5437 * otherwise some computers (ex. IBM HS20 blade server)
5440 bge_asf_update_status(bgep
);
5441 bge_asf_stop_timer(bgep
);
5442 bgep
->asf_status
= ASF_STAT_STOP
;
5444 bge_asf_pre_reset_operations(bgep
, BGE_INIT_RESET
);
5445 (void) bge_check_acc_handle(bgep
, bgep
->cfg_handle
);
5448 bge_chip_stop(bgep
, B_TRUE
);
5449 (void) bge_check_acc_handle(bgep
, bgep
->io_handle
);
5451 mutex_exit(bgep
->genlock
);
5457 * High-level cyclic handler
5459 * This routine schedules a (low-level) softint callback to the
5460 * factotum, and prods the chip to update the status block (which
5461 * will cause a hardware interrupt when complete).
5463 void bge_chip_cyclic(void *arg
);
5464 #pragma no_inline(bge_chip_cyclic)
5467 bge_chip_cyclic(void *arg
)
5474 switch (bgep
->bge_chip_state
) {
5478 case BGE_CHIP_RUNNING
:
5480 /* XXX I really don't like this forced interrupt... */
5481 bge_reg_set32(bgep
, HOST_COALESCE_MODE_REG
, COALESCE_NOW
);
5482 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) != DDI_FM_OK
)
5483 ddi_fm_service_impact(bgep
->devinfo
,
5484 DDI_SERVICE_UNAFFECTED
);
5488 case BGE_CHIP_FAULT
:
5489 case BGE_CHIP_ERROR
:
5494 mutex_enter(bgep
->genlock
);
5496 if (bgep
->eee_lpi_wait
&& !--bgep
->eee_lpi_wait
) {
5497 BGE_DEBUG(("eee cyclic, lpi enabled"));
5498 bge_eee_enable(bgep
);
5501 if (bgep
->rdma_length_bug_on_5719
) {
5502 if ((bge_reg_get32(bgep
, STAT_IFHCOUT_UPKGS_REG
) +
5503 bge_reg_get32(bgep
, STAT_IFHCOUT_MPKGS_REG
) +
5504 bge_reg_get32(bgep
, STAT_IFHCOUT_BPKGS_REG
)) >
5505 BGE_NUM_RDMA_CHANNELS
) {
5506 regval
= bge_reg_get32(bgep
, RDMA_CORR_CTRL_REG
);
5507 regval
&= ~RDMA_CORR_CTRL_TX_LENGTH_WA
;
5508 bge_reg_put32(bgep
, RDMA_CORR_CTRL_REG
, regval
);
5509 bgep
->rdma_length_bug_on_5719
= B_FALSE
;
5513 mutex_exit(bgep
->genlock
);
5515 bge_wake_factotum(bgep
);
5521 * ========== Ioctl subfunctions ==========
5525 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */
5527 #if BGE_DEBUGGING || BGE_DO_PPIO
5529 static void bge_chip_peek_cfg(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5530 #pragma no_inline(bge_chip_peek_cfg)
5533 bge_chip_peek_cfg(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5538 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
5539 (void *)bgep
, (void *)ppd
));
5541 regno
= ppd
->pp_acc_offset
;
5543 switch (ppd
->pp_acc_size
) {
5545 regval
= pci_config_get8(bgep
->cfg_handle
, regno
);
5549 regval
= pci_config_get16(bgep
->cfg_handle
, regno
);
5553 regval
= pci_config_get32(bgep
->cfg_handle
, regno
);
5557 regval
= pci_config_get64(bgep
->cfg_handle
, regno
);
5561 ppd
->pp_acc_data
= regval
;
5564 static void bge_chip_poke_cfg(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5565 #pragma no_inline(bge_chip_poke_cfg)
5568 bge_chip_poke_cfg(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5573 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
5574 (void *)bgep
, (void *)ppd
));
5576 regno
= ppd
->pp_acc_offset
;
5577 regval
= ppd
->pp_acc_data
;
5579 switch (ppd
->pp_acc_size
) {
5581 pci_config_put8(bgep
->cfg_handle
, regno
, regval
);
5585 pci_config_put16(bgep
->cfg_handle
, regno
, regval
);
5589 pci_config_put32(bgep
->cfg_handle
, regno
, regval
);
5593 pci_config_put64(bgep
->cfg_handle
, regno
, regval
);
5598 static void bge_chip_peek_reg(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5599 #pragma no_inline(bge_chip_peek_reg)
5602 bge_chip_peek_reg(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5607 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
5608 (void *)bgep
, (void *)ppd
));
5610 regaddr
= PIO_ADDR(bgep
, ppd
->pp_acc_offset
);
5612 switch (ppd
->pp_acc_size
) {
5614 regval
= ddi_get8(bgep
->io_handle
, regaddr
);
5618 regval
= ddi_get16(bgep
->io_handle
, regaddr
);
5622 regval
= ddi_get32(bgep
->io_handle
, regaddr
);
5626 regval
= ddi_get64(bgep
->io_handle
, regaddr
);
5630 ppd
->pp_acc_data
= regval
;
5633 static void bge_chip_poke_reg(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5634 #pragma no_inline(bge_chip_peek_reg)
5637 bge_chip_poke_reg(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5642 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
5643 (void *)bgep
, (void *)ppd
));
5645 regaddr
= PIO_ADDR(bgep
, ppd
->pp_acc_offset
);
5646 regval
= ppd
->pp_acc_data
;
5648 switch (ppd
->pp_acc_size
) {
5650 ddi_put8(bgep
->io_handle
, regaddr
, regval
);
5654 ddi_put16(bgep
->io_handle
, regaddr
, regval
);
5658 ddi_put32(bgep
->io_handle
, regaddr
, regval
);
5662 ddi_put64(bgep
->io_handle
, regaddr
, regval
);
5668 static void bge_chip_peek_nic(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5669 #pragma no_inline(bge_chip_peek_nic)
5672 bge_chip_peek_nic(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5678 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
5679 (void *)bgep
, (void *)ppd
));
5681 regoff
= ppd
->pp_acc_offset
;
5682 bge_nic_setwin(bgep
, regoff
& ~MWBAR_GRANULE_MASK
);
5683 regoff
&= MWBAR_GRANULE_MASK
;
5684 regoff
+= NIC_MEM_WINDOW_OFFSET
;
5685 regaddr
= PIO_ADDR(bgep
, regoff
);
5687 switch (ppd
->pp_acc_size
) {
5689 regval
= ddi_get8(bgep
->io_handle
, regaddr
);
5693 regval
= ddi_get16(bgep
->io_handle
, regaddr
);
5697 regval
= ddi_get32(bgep
->io_handle
, regaddr
);
5701 regval
= ddi_get64(bgep
->io_handle
, regaddr
);
5705 ppd
->pp_acc_data
= regval
;
5708 static void bge_chip_poke_nic(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5709 #pragma no_inline(bge_chip_poke_nic)
5712 bge_chip_poke_nic(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5718 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
5719 (void *)bgep
, (void *)ppd
));
5721 regoff
= ppd
->pp_acc_offset
;
5722 bge_nic_setwin(bgep
, regoff
& ~MWBAR_GRANULE_MASK
);
5723 regoff
&= MWBAR_GRANULE_MASK
;
5724 regoff
+= NIC_MEM_WINDOW_OFFSET
;
5725 regaddr
= PIO_ADDR(bgep
, regoff
);
5726 regval
= ppd
->pp_acc_data
;
5728 switch (ppd
->pp_acc_size
) {
5730 ddi_put8(bgep
->io_handle
, regaddr
, regval
);
5734 ddi_put16(bgep
->io_handle
, regaddr
, regval
);
5738 ddi_put32(bgep
->io_handle
, regaddr
, regval
);
5742 ddi_put64(bgep
->io_handle
, regaddr
, regval
);
5748 static void bge_chip_peek_mii(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5749 #pragma no_inline(bge_chip_peek_mii)
5752 bge_chip_peek_mii(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5754 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
5755 (void *)bgep
, (void *)ppd
));
5757 ppd
->pp_acc_data
= bge_mii_get16(bgep
, ppd
->pp_acc_offset
/2);
5760 static void bge_chip_poke_mii(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5761 #pragma no_inline(bge_chip_poke_mii)
5764 bge_chip_poke_mii(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5766 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
5767 (void *)bgep
, (void *)ppd
));
5769 bge_mii_put16(bgep
, ppd
->pp_acc_offset
/2, ppd
->pp_acc_data
);
5774 static void bge_chip_peek_seeprom(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5775 #pragma no_inline(bge_chip_peek_seeprom)
5778 bge_chip_peek_seeprom(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5783 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
5784 (void *)bgep
, (void *)ppd
));
5786 err
= bge_nvmem_rw32(bgep
, BGE_SEE_READ
, ppd
->pp_acc_offset
, &data
);
5787 ppd
->pp_acc_data
= err
? ~0ull : data
;
5790 static void bge_chip_poke_seeprom(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5791 #pragma no_inline(bge_chip_poke_seeprom)
5794 bge_chip_poke_seeprom(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5798 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
5799 (void *)bgep
, (void *)ppd
));
5801 data
= ppd
->pp_acc_data
;
5802 (void) bge_nvmem_rw32(bgep
, BGE_SEE_WRITE
, ppd
->pp_acc_offset
, &data
);
5804 #endif /* BGE_SEE_IO32 */
5808 static void bge_chip_peek_flash(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5809 #pragma no_inline(bge_chip_peek_flash)
5812 bge_chip_peek_flash(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5817 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
5818 (void *)bgep
, (void *)ppd
));
5820 err
= bge_nvmem_rw32(bgep
, BGE_FLASH_READ
, ppd
->pp_acc_offset
, &data
);
5821 ppd
->pp_acc_data
= err
? ~0ull : data
;
5824 static void bge_chip_poke_flash(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5825 #pragma no_inline(bge_chip_poke_flash)
5828 bge_chip_poke_flash(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5832 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
5833 (void *)bgep
, (void *)ppd
));
5835 data
= ppd
->pp_acc_data
;
5836 (void) bge_nvmem_rw32(bgep
, BGE_FLASH_WRITE
,
5837 ppd
->pp_acc_offset
, &data
);
5839 #endif /* BGE_FLASH_IO32 */
5841 static void bge_chip_peek_mem(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5842 #pragma no_inline(bge_chip_peek_mem)
5845 bge_chip_peek_mem(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5850 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
5851 (void *)bgep
, (void *)ppd
));
5853 vaddr
= (void *)(uintptr_t)ppd
->pp_acc_offset
;
5855 switch (ppd
->pp_acc_size
) {
5857 regval
= *(uint8_t *)vaddr
;
5861 regval
= *(uint16_t *)vaddr
;
5865 regval
= *(uint32_t *)vaddr
;
5869 regval
= *(uint64_t *)vaddr
;
5873 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
5874 (void *)bgep
, (void *)ppd
, regval
, vaddr
));
5876 ppd
->pp_acc_data
= regval
;
5879 static void bge_chip_poke_mem(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5880 #pragma no_inline(bge_chip_poke_mem)
5883 bge_chip_poke_mem(bge_t
*bgep
, bge_peekpoke_t
*ppd
)
5888 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
5889 (void *)bgep
, (void *)ppd
));
5891 vaddr
= (void *)(uintptr_t)ppd
->pp_acc_offset
;
5892 regval
= ppd
->pp_acc_data
;
5894 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
5895 (void *)bgep
, (void *)ppd
, regval
, vaddr
));
5897 switch (ppd
->pp_acc_size
) {
5899 *(uint8_t *)vaddr
= (uint8_t)regval
;
5903 *(uint16_t *)vaddr
= (uint16_t)regval
;
5907 *(uint32_t *)vaddr
= (uint32_t)regval
;
5911 *(uint64_t *)vaddr
= (uint64_t)regval
;
5916 static enum ioc_reply
bge_pp_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
,
5917 struct iocblk
*iocp
);
5918 #pragma no_inline(bge_pp_ioctl)
5920 static enum ioc_reply
5921 bge_pp_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
, struct iocblk
*iocp
)
5923 void (*ppfn
)(bge_t
*bgep
, bge_peekpoke_t
*ppd
);
5924 bge_peekpoke_t
*ppd
;
5934 bge_error(bgep
, "bge_pp_ioctl: invalid cmd 0x%x", cmd
);
5947 * Validate format of ioctl
5949 if (iocp
->ioc_count
!= sizeof (bge_peekpoke_t
))
5951 if (mp
->b_cont
== NULL
)
5953 ppd
= (void *)mp
->b_cont
->b_rptr
;
5956 * Validate request parameters
5958 switch (ppd
->pp_acc_space
) {
5962 case BGE_PP_SPACE_CFG
:
5968 maxoff
= PCI_CONF_HDR_SIZE
;
5969 ppfn
= peek
? bge_chip_peek_cfg
: bge_chip_poke_cfg
;
5972 case BGE_PP_SPACE_REG
:
5974 * Memory-mapped I/O space
5978 maxoff
= RIAAR_REGISTER_MAX
;
5979 ppfn
= peek
? bge_chip_peek_reg
: bge_chip_poke_reg
;
5982 case BGE_PP_SPACE_NIC
:
5984 * NIC on-chip memory
5988 maxoff
= MWBAR_ONCHIP_MAX
;
5989 ppfn
= peek
? bge_chip_peek_nic
: bge_chip_poke_nic
;
5992 case BGE_PP_SPACE_MII
:
5994 * PHY's MII registers
5995 * NB: all PHY registers are two bytes, but the
5996 * addresses increment in ones (word addressing).
5997 * So we scale the address here, then undo the
5998 * transformation inside the peek/poke functions.
6000 ppd
->pp_acc_offset
*= 2;
6003 maxoff
= (MII_MAXREG
+1)*2;
6004 ppfn
= peek
? bge_chip_peek_mii
: bge_chip_poke_mii
;
6008 case BGE_PP_SPACE_SEEPROM
:
6010 * Attached SEEPROM(s), if any.
6011 * NB: we use the high-order bits of the 'address' as
6012 * a device select to accommodate multiple SEEPROMS,
6013 * If each one is the maximum size (64kbytes), this
6014 * makes them appear contiguous. Otherwise, there may
6015 * be holes in the mapping. ENxS doesn't have any
6016 * SEEPROMs anyway ...
6020 maxoff
= SEEPROM_DEV_AND_ADDR_MASK
;
6021 ppfn
= peek
? bge_chip_peek_seeprom
: bge_chip_poke_seeprom
;
6023 #endif /* BGE_SEE_IO32 */
6026 case BGE_PP_SPACE_FLASH
:
6028 * Attached Flash device (if any); a maximum of one device
6029 * is currently supported. But it can be up to 1MB (unlike
6030 * the 64k limit on SEEPROMs) so why would you need more ;-)
6034 maxoff
= NVM_FLASH_ADDR_MASK
;
6035 ppfn
= peek
? bge_chip_peek_flash
: bge_chip_poke_flash
;
6037 #endif /* BGE_FLASH_IO32 */
6039 case BGE_PP_SPACE_BGE
:
6041 * BGE data structure!
6044 mem_va
= (uintptr_t)bgep
;
6045 maxoff
= sizeof (*bgep
);
6046 ppfn
= peek
? bge_chip_peek_mem
: bge_chip_poke_mem
;
6049 case BGE_PP_SPACE_STATUS
:
6050 case BGE_PP_SPACE_STATISTICS
:
6051 case BGE_PP_SPACE_TXDESC
:
6052 case BGE_PP_SPACE_TXBUFF
:
6053 case BGE_PP_SPACE_RXDESC
:
6054 case BGE_PP_SPACE_RXBUFF
:
6058 switch (ppd
->pp_acc_space
) {
6059 case BGE_PP_SPACE_TXDESC
:
6060 areap
= &bgep
->tx_desc
;
6062 case BGE_PP_SPACE_TXBUFF
:
6063 areap
= &bgep
->tx_buff
[0];
6065 case BGE_PP_SPACE_RXDESC
:
6066 areap
= &bgep
->rx_desc
[0];
6068 case BGE_PP_SPACE_RXBUFF
:
6069 areap
= &bgep
->rx_buff
[0];
6071 case BGE_PP_SPACE_STATUS
:
6072 areap
= &bgep
->status_block
;
6074 case BGE_PP_SPACE_STATISTICS
:
6075 if (bgep
->chipid
.statistic_type
== BGE_STAT_BLK
)
6076 areap
= &bgep
->statistics
;
6081 mem_va
= (uintptr_t)areap
->mem_va
;
6082 maxoff
= areap
->alength
;
6083 ppfn
= peek
? bge_chip_peek_mem
: bge_chip_poke_mem
;
6087 switch (ppd
->pp_acc_size
) {
6095 if ((ppd
->pp_acc_size
& sizemask
) == 0)
6100 if ((ppd
->pp_acc_offset
% ppd
->pp_acc_size
) != 0)
6103 if (ppd
->pp_acc_offset
>= maxoff
)
6106 if (ppd
->pp_acc_offset
+ppd
->pp_acc_size
> maxoff
)
6110 * All OK - go do it!
6112 ppd
->pp_acc_offset
+= mem_va
;
6114 return (peek
? IOC_REPLY
: IOC_ACK
);
6117 static enum ioc_reply
bge_diag_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
,
6118 struct iocblk
*iocp
);
6119 #pragma no_inline(bge_diag_ioctl)
6121 static enum ioc_reply
6122 bge_diag_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
, struct iocblk
*iocp
)
6124 ASSERT(mutex_owned(bgep
->genlock
));
6129 bge_error(bgep
, "bge_diag_ioctl: invalid cmd 0x%x", cmd
);
6140 return (bge_pp_ioctl(bgep
, cmd
, mp
, iocp
));
6143 return (IOC_RESTART_ACK
);
6145 case BGE_SOFT_RESET
:
6146 case BGE_HARD_RESET
:
6148 * Reset and reinitialise the 570x hardware
6150 bgep
->bge_chip_state
= BGE_CHIP_FAULT
;
6151 ddi_trigger_softintr(bgep
->factotum_id
);
6152 (void) bge_restart(bgep
, cmd
== BGE_HARD_RESET
);
6159 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */
6161 static enum ioc_reply
bge_mii_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
,
6162 struct iocblk
*iocp
);
6163 #pragma no_inline(bge_mii_ioctl)
6165 static enum ioc_reply
6166 bge_mii_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
, struct iocblk
*iocp
)
6168 struct bge_mii_rw
*miirwp
;
6171 * Validate format of ioctl
6173 if (iocp
->ioc_count
!= sizeof (struct bge_mii_rw
))
6175 if (mp
->b_cont
== NULL
)
6177 miirwp
= (void *)mp
->b_cont
->b_rptr
;
6180 * Validate request parameters ...
6182 if (miirwp
->mii_reg
> MII_MAXREG
)
6188 bge_error(bgep
, "bge_mii_ioctl: invalid cmd 0x%x", cmd
);
6192 miirwp
->mii_data
= bge_mii_get16(bgep
, miirwp
->mii_reg
);
6196 bge_mii_put16(bgep
, miirwp
->mii_reg
, miirwp
->mii_data
);
6205 static enum ioc_reply
bge_see_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
,
6206 struct iocblk
*iocp
);
6207 #pragma no_inline(bge_see_ioctl)
6209 static enum ioc_reply
6210 bge_see_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
, struct iocblk
*iocp
)
6212 struct bge_see_rw
*seerwp
;
6215 * Validate format of ioctl
6217 if (iocp
->ioc_count
!= sizeof (struct bge_see_rw
))
6219 if (mp
->b_cont
== NULL
)
6221 seerwp
= (void *)mp
->b_cont
->b_rptr
;
6224 * Validate request parameters ...
6226 if (seerwp
->see_addr
& ~SEEPROM_DEV_AND_ADDR_MASK
)
6232 bge_error(bgep
, "bge_see_ioctl: invalid cmd 0x%x", cmd
);
6237 iocp
->ioc_error
= bge_nvmem_rw32(bgep
, cmd
,
6238 seerwp
->see_addr
, &seerwp
->see_data
);
6245 #endif /* BGE_SEE_IO32 */
6249 static enum ioc_reply
bge_flash_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
,
6250 struct iocblk
*iocp
);
6251 #pragma no_inline(bge_flash_ioctl)
6253 static enum ioc_reply
6254 bge_flash_ioctl(bge_t
*bgep
, int cmd
, mblk_t
*mp
, struct iocblk
*iocp
)
6256 struct bge_flash_rw
*flashrwp
;
6259 * Validate format of ioctl
6261 if (iocp
->ioc_count
!= sizeof (struct bge_flash_rw
))
6263 if (mp
->b_cont
== NULL
)
6265 flashrwp
= (void *)mp
->b_cont
->b_rptr
;
6268 * Validate request parameters ...
6270 if (flashrwp
->flash_addr
& ~NVM_FLASH_ADDR_MASK
)
6276 bge_error(bgep
, "bge_flash_ioctl: invalid cmd 0x%x", cmd
);
6279 case BGE_FLASH_READ
:
6280 case BGE_FLASH_WRITE
:
6281 iocp
->ioc_error
= bge_nvmem_rw32(bgep
, cmd
,
6282 flashrwp
->flash_addr
, &flashrwp
->flash_data
);
6289 #endif /* BGE_FLASH_IO32 */
6291 enum ioc_reply
bge_chip_ioctl(bge_t
*bgep
, queue_t
*wq
, mblk_t
*mp
,
6292 struct iocblk
*iocp
);
6293 #pragma no_inline(bge_chip_ioctl)
6296 bge_chip_ioctl(bge_t
*bgep
, queue_t
*wq
, mblk_t
*mp
, struct iocblk
*iocp
)
6300 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
6301 (void *)bgep
, (void *)wq
, (void *)mp
, (void *)iocp
));
6303 ASSERT(mutex_owned(bgep
->genlock
));
6305 cmd
= iocp
->ioc_cmd
;
6309 bge_error(bgep
, "bge_chip_ioctl: invalid cmd 0x%x", cmd
);
6316 case BGE_SOFT_RESET
:
6317 case BGE_HARD_RESET
:
6318 #if BGE_DEBUGGING || BGE_DO_PPIO
6319 return (bge_diag_ioctl(bgep
, cmd
, mp
, iocp
));
6322 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */
6326 return (bge_mii_ioctl(bgep
, cmd
, mp
, iocp
));
6331 return (bge_see_ioctl(bgep
, cmd
, mp
, iocp
));
6332 #endif /* BGE_SEE_IO32 */
6335 case BGE_FLASH_READ
:
6336 case BGE_FLASH_WRITE
:
6337 return (bge_flash_ioctl(bgep
, cmd
, mp
, iocp
));
6338 #endif /* BGE_FLASH_IO32 */
6346 bge_chip_blank(void *arg
, time_t ticks
, uint_t count
, int flag
)
6348 recv_ring_t
*rrp
= arg
;
6349 bge_t
*bgep
= rrp
->bgep
;
6351 mutex_enter(bgep
->genlock
);
6352 rrp
->poll_flag
= flag
;
6355 * XXX-Sunay: Since most broadcom cards support only one
6356 * interrupt but multiple rx rings, we can't disable the
6357 * physical interrupt. This need to be done via capability
6358 * negotiation depending on the NIC.
6360 bge_reg_put32(bgep
, RCV_COALESCE_TICKS_REG
, ticks
);
6361 bge_reg_put32(bgep
, RCV_COALESCE_MAX_BD_REG
, count
);
6363 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) != DDI_FM_OK
)
6364 ddi_fm_service_impact(bgep
->devinfo
, DDI_SERVICE_UNAFFECTED
);
6365 mutex_exit(bgep
->genlock
);
6371 bge_nic_read32(bge_t
*bgep
, bge_regno_t addr
)
6376 if (!bgep
->asf_wordswapped
) {
6377 /* a workaround word swap error */
6384 if (DEVICE_5717_SERIES_CHIPSETS(bgep
) ||
6385 DEVICE_5725_SERIES_CHIPSETS(bgep
)) {
6390 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MWBAR
, addr
);
6391 data
= pci_config_get32(bgep
->cfg_handle
, PCI_CONF_BGE_MWDAR
);
6392 pci_config_put32(bgep
->cfg_handle
, PCI_CONF_BGE_MWBAR
, 0);
6396 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x",
6397 (void *)bgep
, addr
, data
));
6403 bge_asf_update_status(bge_t
*bgep
)
6407 bge_nic_put32(bgep
, BGE_CMD_MAILBOX
, BGE_CMD_NICDRV_ALIVE
);
6408 bge_nic_put32(bgep
, BGE_CMD_LENGTH_MAILBOX
, 4);
6409 bge_nic_put32(bgep
, BGE_CMD_DATA_MAILBOX
, 3);
6411 event
= bge_reg_get32(bgep
, RX_RISC_EVENT_REG
);
6412 bge_reg_put32(bgep
, RX_RISC_EVENT_REG
, event
| RRER_ASF_EVENT
);
6417 * The driver is supposed to notify ASF that the OS is still running
6418 * every three seconds, otherwise the management server may attempt
6419 * to reboot the machine. If it hasn't actually failed, this is
6420 * not a desirable result. However, this isn't running as a real-time
6421 * thread, and even if it were, it might not be able to generate the
6422 * heartbeat in a timely manner due to system load. As it isn't a
6423 * significant strain on the machine, we will set the interval to half
6424 * of the required value.
6427 bge_asf_heartbeat(void *arg
)
6429 bge_t
*bgep
= (bge_t
*)arg
;
6431 mutex_enter(bgep
->genlock
);
6432 bge_asf_update_status((bge_t
*)bgep
);
6433 if (bge_check_acc_handle(bgep
, bgep
->io_handle
) != DDI_FM_OK
)
6434 ddi_fm_service_impact(bgep
->devinfo
, DDI_SERVICE_DEGRADED
);
6435 if (bge_check_acc_handle(bgep
, bgep
->cfg_handle
) != DDI_FM_OK
)
6436 ddi_fm_service_impact(bgep
->devinfo
, DDI_SERVICE_DEGRADED
);
6437 mutex_exit(bgep
->genlock
);
6438 ((bge_t
*)bgep
)->asf_timeout_id
= timeout(bge_asf_heartbeat
, bgep
,
6439 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL
));
6444 bge_asf_stop_timer(bge_t
*bgep
)
6446 timeout_id_t tmp_id
= 0;
6448 while ((bgep
->asf_timeout_id
!= 0) &&
6449 (tmp_id
!= bgep
->asf_timeout_id
)) {
6450 tmp_id
= bgep
->asf_timeout_id
;
6451 (void) untimeout(tmp_id
);
6453 bgep
->asf_timeout_id
= 0;
6459 * This function should be placed at the earliest position of bge_attach().
6462 bge_asf_get_config(bge_t
*bgep
)
6467 bgep
->asf_enabled
= B_FALSE
;
6469 /* No ASF if APE present. */
6470 if (bgep
->ape_enabled
)
6473 nicsig
= bge_nic_read32(bgep
, BGE_NIC_DATA_SIG_ADDR
);
6474 if (nicsig
== BGE_NIC_DATA_SIG
) {
6475 niccfg
= bge_nic_read32(bgep
, BGE_NIC_DATA_NIC_CFG_ADDR
);
6476 if (niccfg
& BGE_NIC_CFG_ENABLE_ASF
)
6478 * Here, we don't consider BAXTER, because BGE haven't
6479 * supported BAXTER (that is 5752). Also, as I know,
6480 * BAXTER doesn't support ASF feature.
6482 bgep
->asf_enabled
= B_TRUE
;
6484 bgep
->asf_enabled
= B_FALSE
;
6486 bgep
->asf_enabled
= B_FALSE
;
6491 bge_asf_pre_reset_operations(bge_t
*bgep
, uint32_t mode
)
6496 ASSERT(bgep
->asf_enabled
);
6498 /* Issues "pause firmware" command and wait for ACK */
6499 bge_nic_put32(bgep
, BGE_CMD_MAILBOX
, BGE_CMD_NICDRV_PAUSE_FW
);
6500 event
= bge_reg_get32(bgep
, RX_RISC_EVENT_REG
);
6501 bge_reg_put32(bgep
, RX_RISC_EVENT_REG
, event
| RRER_ASF_EVENT
);
6503 event
= bge_reg_get32(bgep
, RX_RISC_EVENT_REG
);
6505 while ((event
& RRER_ASF_EVENT
) && (tries
< 100)) {
6508 event
= bge_reg_get32(bgep
, RX_RISC_EVENT_REG
);
6511 bge_nic_put32(bgep
, BGE_FIRMWARE_MAILBOX
,
6512 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE
);
6514 if (bgep
->asf_newhandshake
) {
6516 case BGE_INIT_RESET
:
6517 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6518 BGE_DRV_STATE_START
);
6520 case BGE_SHUTDOWN_RESET
:
6521 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6522 BGE_DRV_STATE_UNLOAD
);
6524 case BGE_SUSPEND_RESET
:
6525 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6526 BGE_DRV_STATE_SUSPEND
);
6533 if (mode
== BGE_INIT_RESET
||
6534 mode
== BGE_SUSPEND_RESET
)
6535 bge_ape_driver_state_change(bgep
, mode
);
6540 bge_asf_post_reset_old_mode(bge_t
*bgep
, uint32_t mode
)
6543 case BGE_INIT_RESET
:
6544 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6545 BGE_DRV_STATE_START
);
6547 case BGE_SHUTDOWN_RESET
:
6548 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6549 BGE_DRV_STATE_UNLOAD
);
6551 case BGE_SUSPEND_RESET
:
6552 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6553 BGE_DRV_STATE_SUSPEND
);
6562 bge_asf_post_reset_new_mode(bge_t
*bgep
, uint32_t mode
)
6565 case BGE_INIT_RESET
:
6566 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6567 BGE_DRV_STATE_START_DONE
);
6569 case BGE_SHUTDOWN_RESET
:
6570 bge_nic_put32(bgep
, BGE_DRV_STATE_MAILBOX
,
6571 BGE_DRV_STATE_UNLOAD_DONE
);
6577 if (mode
== BGE_SHUTDOWN_RESET
)
6578 bge_ape_driver_state_change(bgep
, mode
);
6581 #endif /* BGE_IPMI_ASF */